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Fujitsu MB91F109 FR30 User's Manual

1. Explanation of operation Q1 QIW Q2 Q3 Q4 Q4w Q5 4 1 X X Y 0 row adr X 0 cdl adr E X d i RN A X Y 0 row adr X 0 cdl adr E X yo i i X MEE gt aa gt Q1 wait 04 K Usual DRAM interface gt When adding only one wait clock cycle to the Q1 and Q4 cycles set the Q1W and Q4W bits of DMCR4 and DMCRS5 The inserted cycles are called the Q1W and Q4W cycles The Q1W and Q4W cycles execute the same cycles as the Q1 and Q4 cycles By this operation the H width of RAS and the L width of CAS can be extended by one cycle respectively Set the widths according to the DRAM access time 181 CHAPTER 4 BUS INTERFACE 4 17 13 DRAM Interface in High Speed Page Mode This section provides DRAM interface operation timing charts in high speed page mode DRAM Interface Timing Charts in High Speed Page Mode O Read cycle bus width 16 bits access words Figure 4 17 25 Example 1 of DRAM Interface Timing Chart in High Speed Page Mode Q1 Q2 Q3 Q4 Q5 Q4 Q5 Q4 Q5 Q4 Q5 cx 1 1CAS 2WE i i i A24 00 X X X 0 row adr 0 col adr X 2 col adr 4 col adr 6 coladr X D31 24 Go x Ga x x 46
2. ck 1 1CAS 2WE A24 00 X X rowad X col adr X X X3 row adr col adr X 031 24 X 0 X X X D23 16 X X X 1 X RAS N CAS NES WEL Upper address side 1 WEH Lower address side 2 2CAS 1WE A24 00 X X X 0 row adr X X row adr 1 col adr X 031 24 X 0 X 1 AX 023 16 X X X 1 X RAS K CASL Upper address side CASH Lower address side WE Bus width 8 bits access half words Figure 4 17 23 Example 3 of Usual DRAM Write Cycle Timing Chart Q1 Q2 05 01 Q2 04 O5 MEE A24 00 Y X X30 row adr 0 col adr X X X4 row adr 1 col adr 031 24 X 0 X X X D23 16 RAS 7 MW CAS 7 WE 1 4 17 Bus Timing 4 17 12 Automatic Wait Cycles in Usual DRAM Interface This section provides an automatic wait cycle timing chart in the usual DRAM interface Automatic Wait Cycle Timing Chart in Usual DRAM Interface O Bus width 8 bits access bytes Figure 4 17 24 Example of Automatic Wait Cycle Timing Chart in Usual DRAM Interface CLK 1 Read A24 00 D31 24 D23 16 RAS CAS WE RDX 2 Write A24 00 D31 24 D23 16 RAS CAS WE RDX
3. WRITE Resource request gt ICR gt IL MP DICR ICR ILM Delayed interrupt Interrupt controller CPU 220 7 2 Delayed Interrupt Control Register DICR 7 2 Delayed Interrupt Control Register DICR The delayed interrupt control register DICR is used to control delayed interrupts B Configuration of the Delayed Interrupt Control Register DICR The configuration of the delayed interrupt control register DICR is shown below bit7 6 5 4 3 2 1 0 DLYI Initial value R W Bit Function of the Delayed Interrupt Control Register DICR bit 0 DLYI Clear the cause of a delayed interrupt respectively do not issue a delayed interrupt request Initial value Generate the cause of a delayed interrupt This bit generates or clears an applicable interrupt cause 221 CHAPTER 7 DELAYED INTERRUPT MODULE 7 3 Operation of Delayed Interrupt Module The delayed interrupt module causes an interrupt for changing a task Software can use this module to issue or cancel an interrupt request to the CPU B Interrupt Number A delayed interrupt is assigned to the interrupt having the largest interrupt number This model assigns the delayed interrupt to interrupt number 63 B DICR DLYI Bit Writing 1 to the DLYI bit of the DICR register generates the cause of a del
4. Q4 Q5 BA1 BA2 1 BA2 Idle Q4 Q5 Q4 Q5 ok A24 00 5 col adr XCS2X basic bus X CS2X basic bus X_CS4xX col adr X CS4X col adr X D31 24 XRead X Write X Read Read Read D23 16 XRead X Write X Read Read gt Read CS2X 7 CS4AX mx ee 2 WROX CS4 RAS CS4 CASL CS4 CASH i CS4 WE i i CS4 high speed gt gt lt CS2 basic bus gt lt CS4 high speed page Explanation of operation Evenifthe CS area switches and another CS area is accessed RAS remains at L in high speed page mode 184 4 17 Bus Timing 4 17 14 Single DRAM Interface Read This section provides a read timing chart for a single DRAM interface Single DRAM Interface Read Timing Chart O Bus width 16 bits access words Figure 4 17 29 Example of Single DRAM Interface Read Timing Chart Q1 Q2 Q3 Q4SR Q4SR Q4SR Q4SR Ide Q1 Q2 Q3 CLK 1 CAS 2WE A24 00 X X X row adr 1 X X X rowad X D31 24 Redd Redd Read gt Redd D23 16 XRedd j Redd ARead Read RAS EN E id CAS WEL LEA WEH CENE 271
5. 246 UART Block Diagram erit reet rta imet tds 247 Format of Data Transferred in Asynchronous Start Stop Mode Mode 0 or 1 257 Format of Data Transferred in CLK Synchronous Mode Mode 2 258 ORE FRE and RDRF Set Timing Mode 0 enne 260 ORE FRE and RDRF Set Timing Mode 1 sse 261 ORE and RDRF Set Timing Mode 2 261 TDRE Set Timing Mode 0071 424 eere aee tee de vede de ee 262 TDRE Set Timing Mode 2 ie e Ere tet ete einen th eed hd 262 Sample System Structure for Mode 1 nennen nennen 263 Communication Flowchart for Mode 1 20222 0 1 0 nennen ener 264 A D Converter Registers 22 44 1111 nentes entr 268 Block Diagram of the A D Converter 2 nennen 269 Workflow of the Data Protection Function when DMA Transfer is Used 279 16 Bit Reload Timer Registers enn nnns 282 16 Bit Reload Timer Block nnns 283 Counter Start and Operation 287 Underflow Operation 288 Counter States
6. 33 35 register 33 36 releasing from external reset pin or software reset 68 reload register 22 2 22 1 241 reload timer 4 reset reason register RSRR and watchdog cycle control register WTCR bit function of 76 reset reason register RSRR and watchdog cycle control register WTCR configuration of 76 reset request return by way of 96 r set Sequerce inn tere 68 reset source hold circuit block diagram of 101 reset source holding setting for 101 reset type citet bee ier tenias 4 resetting cause 68 resetting initialization by 68 resource instruction esee 422 resource interrupt request as a DMA transfer request Wim 339 RETI instruction operation 67 return point RP 37 RISC architecture ne 30 ROM writer writing 22 2 4 2 4 222 353 row and column address 156 RSTX pin return by way 93 S save restore processing 297 second word of descriptor 334 FIXE ee
7. 338 15 85 Notes on o e i it e te e tree o ee Ete p tee eret eee o dtm te 339 15 9 DMAC Timing Harte 5 oin eret e ER eer De RE BEER EU EIE xU Dina aed ange 342 15 9 1 Timing Charts of the Descriptor Access Block 343 15 9 2 Timing Charts of Data Transfer Block 345 15 9 3 Transfer Stop Timing Charts in Continuous Transfer Mode 2 347 15 9 4 Transfer Termination Timing Charts nens 349 CHAPTER 16 FLASH MEMORY 351 16 1 Outline of Flash Memory 352 16 2 Block Diagram of Flash 354 16 3 Flash Memory Status Register FSTR cccccccseceeeseeeceeeeeeeeeeceneeeesaaeeseeeeseaaeeseneeeecaeeeeeaeeseeeeeeneaes 355 16 4 Sector Configuration of Flash Memory sse enne nnns en rentrer 357 16 5 Flash Memory Modas EA RNE KAEA 359 16 6 Starting the Automatic Algorithm sess 361 16 7 Execution Status of the Automatic 364 APPENDIX e 369 APPENDIX A VO Maps due tr
8. 289 Bit Search Module 292 Block Diagram of the Bit Search 292 PWM Timer Registers ne ne 301 General Block Diagram of PWM Timer 2 2 24100 00 eene nn nnne nns 302 Block Diagram of Single PWM Timer Channel 2 303 PWM Operation Timing Chart Trigger Restart Disabled 316 PWM Operation Timing Chart Trigger Restart Enabled 316 XV Figure 14 10 1 Figure 14 10 2 Figure 14 11 1 Figure 14 12 1 Figure 14 12 2 Figure 15 1 1 Figure 15 1 2 Figure 16 1 1 Figure 16 2 1 Figure 16 4 1 Figure 16 7 1 Xvi One Shot Operation Timing Chart Trigger Restart Disabled 318 One Shot Operation Timing Chart Trigger Restart Enabled 318 Causes of Interrupts and Their Timing PWM Output Normal Polarity 319 Example of Keeping PWM Output at a Lower Level 2 320 Example of Keeping PWM Output at a High Level 320 324 DMAG Block Diagram iei e ania Ace eee 325 Flash M mory REGISters oe cheap dementiae REED 352 Block diagram of the Flash
9. 354 Memory and Sector Configuration sse eee 357 Structure of the Hardware Sequence Flag sss 364 TABLES Table 1 4 1 Table 1 5 1 Table 1 5 2 Table 1 5 3 Table 1 5 4 Table 1 5 5 Table 1 6 1 Table 1 6 2 Table 2 8 1 Table 2 8 2 Table 2 8 3 Table 2 8 4 Table 2 8 5 Table 2 10 1 Table 2 10 2 Table 3 2 1 Table 3 3 1 Table 3 6 1 Table 3 6 2 Table 3 7 1 Table 3 10 1 Table 3 14 1 Table 4 3 1 Table 4 10 1 Table 4 10 2 Table 4 15 1 Table 4 16 1 Table 4 16 2 Table 4 16 3 Table 5 4 1 Table 5 4 2 Table 5 4 3 Table 5 4 4 Table 6 4 1 FBGA Package Pin Names sens 13 3 inia Sea ehe 14 2 5 2 ini divin davies inven 15 Pin Functons 35D ti as ave tae 17 PIn FUNCHONS 4 5 2 5 itur ie dana es 18 Funcions 5 5 e esie eiie eie or ia o e Ue siu 20 2 ted np hs Sl fede 22 VO cirouit format 1 2 qp ed Ene er ent 23 Intermpt Level xin i a 54 Assignments of Interrupt Causes and Interrupt Vectors 56 Vector Elo ae ee ni ae 61 Priority for EIT Event Acceptance and
10. 218 Figure 7 1 1 Figure 7 1 2 Figure 8 1 1 Figure 8 1 2 Figure 8 2 1 Figure 8 8 1 Figure 8 8 2 Figure 8 8 3 Figure 9 1 1 Figure 9 1 2 Figure 9 3 1 Figure 10 1 1 Figure 10 1 2 Figure 10 7 1 Figure 10 8 1 Figure 10 9 1 Figure 10 9 2 Figure 10 9 3 Figure 10 9 4 Figure 10 9 5 Figure 10 10 1 Figure 10 10 2 Figure 11 1 1 Figure 11 1 2 Figure 11 5 1 Figure 12 1 1 Figure 12 1 2 Figure 12 4 1 Figure 12 4 2 Figure 12 5 1 Figure 13 1 1 Figure 13 1 2 Figure 14 1 1 Figure 14 2 1 Figure 14 2 2 Figure 14 9 1 Figure 14 9 2 Delayed Interrupt Module Register 220 Delayed Interrupt Module Block 220 Interrupt Controller Registers 1 2 2 4 0404 000 225 Interrupt Controller Registers 2 2 226 Block Diagram of the Interrupt Controller 2 227 Example of Hardware Configuration for Using the Hold Request Cancel Request Function 236 Example of Timing for Hold Request Cancel Request Sequence Interrupt Level HRCL a 237 Example of Timing for Hold Request Cancel Request Sequence Interrupt Levels HRGOL a D re teret rr treno lage tpe daret 237 U TIMER REGISTOS n e PERRO IL egit 240 USTIMER Block Diagram te e ee Fee ERE ER RR han 240 Example of Using U TIMER Channels 0 and 1 in Cascade Mode 243
11. 99 watchdog timer reset delay register WPR bit FUNCION Of 85 watchdog timer reset delay register WPR configuration 85 watchdog timer starting 99 141 147 151 write cycle timing 168 write timing chart hyper DRAM interface 189 write timing chart single DRAM interface 186 writing by ROM writer 2 4222227 353 433 INDEX 434 CM71 10106 1E FUJITSU SEMICONDUCTOR CONTROLLER MANUALI FR30 32 Bit Microcontroller MB91F109 Hardware Manual February 2000 the first edition Published FUJITSU LIMITED Electronic Devices Edited Technical Communication Dept co FUJITSU 6CM71 101086 1E FUJITSU SEMICONDUCTOR FR30 32 Bit Microcontroller MB91F109 Hardware Manual
12. 639 018 6181609 C0000 9 009 21919 01018 EDO GOON S LOr 519616194606 61816 84819 019101909 SOOO OOC OCS E CS A B D E F G H J K rc Table 1 4 1 shows the cross references of the FBGA package pin names Table 1 4 1 FBGA Package Pin Names BALL No PIN NAME N C RAS1 PB4 EOP2 CSOL PB1 INT1 PE1 x1 BALL No PIN NAME VCC DREQO PE4 PF7 ATGX AN2 AVRH 1 4 Pin Arrangement Diagrams BALL No PIN NAME A14 P56 A13 P55 N C RDX P83 WROX P84 INT3 SC2 PE3 DACK1 PE7 512 OCPA1 PF5 SC0 OCPA3 PF2 510 TRGO PFO CS1X PA1 50 PAO NMIX VCC D21 P25 D24 P30 N C VSS VCC N C CS1L PB5 DREQ2 CS1H PB6 DACK2 CSOH PB2 INTO PEO AVSS AVRL N C A23 P67 A22 P66 RSTX 06 P46 A12 P54 A11 P53 N C D16 P20 INT2 SC1 PE2 DACKO0 PE6 5 2 OPCA2 PF6 511 TRG2 VSS MDO MD2 A24 P70 EOPO VSS D18 P22 D20 P24 D23 P27 D27 P33 D30 P36 SO0 TRG1 PF1 ANS DW1X PB7 VCC CLK PA6 A21 P65 A20 P64 N C MD1 RDY P80 A00 P40 A02 P42 A05 P45 A10 P52 A09 P51 DWOX PB3 N C VSS DREQ1 5 N C N C A19 P63 A18 P62 A17 P61 A16 P60 N C D17 P21 D19 P23 D22 P26 D26 P32 SO1 TRG3 PF4 AN1 ANO CS5X PA5 CSAX 4 BGRNTX P81
13. 90 Stop States pei ee ee alee 92 3 10 2 Sleep Stale 1 reu ertt heat pd e Resort runs 95 3 10 3 Standby Mode State Transition 98 3 11 Watchdog Function rn red reete eet e re teer tenter arti 99 3 12 Reset Source Hold Circuit ind e e lad dide et ite aeu Rd eae 101 343 DMA SUuppresSiOR dece eet etu done e pas e dee 103 3 14 Clock Doubler Function 1 0 eeeeaeeeeaeeeeaaaeseaaeeecaaaeseaaeeseaeeeesaaeesseeeeesaaeesseneeeseaeeesenees 105 3 15 Example of PLL Clock 108 CHAPTER 4 Sai corda 111 4 1 Outline of Bus Interface 112 4 2 Chip Select Area iet Tr d im eie Ee ne HE 115 Uc PUENTE 116 4 4 Area Select Register ASR and Area Mask Register AMR sse 118 4 5 Area Mode Register 0 0 2222 1 1 00 121 4 6 Area Mode Register 1 1 02244 0 0 a 123 4 7 Area Mode Register 32 32 4002 41 010 000 nennen nennt nennen 124 4 8 Area Mode Register 4
14. 04 002244 1 nennen entrent nnn 125 4 9 Area Mode Register 5 AMD5 44222222 1 antenne innen needs nennen 126 4 10 DRAM Control Register 4 5 DMCR4 5 127 4 11 Refresh Control Register 130 4 12 External Pin Control Register 0 132 4 13 External Pin Control Register 1 135 4 14 DRAM Signal Control Register 05 44044 2 1 00000 nennen nennen nnne 136 4 15 Little Endian Register A nennen ennt A nnne 138 4 16 Relationship between Data Bus Widths and Control Signals 2 139 4 16 1 Bus Access with Big piseanna 141 4 16 2 Bus Access with Little Endians 147 4 16 3 External ACCESS 2 151 4 16 4 DRAM Relationships regredi de dh teed 155 4217 Bus TIMING red Rete td se A etsi 159 417 1 eaten aeneus e 162 4 17 2 Basic Write Cycles 5 er E er IU it ere to cioe Ee eg i tees ttu Pe HE uae 164 4 17 3 Read
15. 4 l X X X50 row adr X 0 col adr Y X 0 row adr X 2 col adr Y Go G uH i 3 ix a E D 1 D D s D D D a 1 1 D ke e a gt Half word access of Half word access of upper address side lower address side Explanation of operation A24 to 00 address 24 to address 00 output a row address from the rising edge of Q2 and then output a column address from the rising edge of Q4 for the read address specified by PGSS to PGSO of the DMCR as well as by the bus width The address output in the Q1 cycle is undefined D31 to D16 data 31 to data 16 represent read data from external memory and I O In read cycles D31 to D16 are fetched at the rising edge of CAS for the 1CAS 2WE and at the rising 173 CHAPTER 4 BUS INTERFACE 174 edge of CASL or CASH for the 2CAS 1WE For the 1CAS 2WE CAS corresponds to D31 to D16 For the 2CAS 1WE CASL corresponds to D31 to D24 and CASH corresponds to D23 to D16 In read cycles all of D31 to D16 are fetched irrespective of the bus width and word half word and byte access Whether the read data is valid is determined inside the chip RAS is a row address strobe signal which becomes H at the falling edge of Q1 and L at the rising edge of Q3 When the PAGE bit is 0 non high speed
16. 173 timing chart usual DRAM interface write 175 timing chart usual DRAM read cycle 177 timing chart usual DRAM write cycle 179 timing chart write 168 IMGSR fu atm us ets 284 432 transfer end signal output 338 transfer mode 337 transfer mode continuous 336 transfer mode single block 335 transfer request acknowledgment signal OUPO satan Dette een ies 338 transfer stop in continuous transfer mode for 16 8 bit data both address are changed 348 transfer stop in continuous transfer mode for 16 8 bit data either address is unchanged 347 transfer termination both address are changed 350 transfer termination either address is 349 transfer to DMC internal register 340 transition to sleep 95 transition to stop 92 transition to stop state using intruction 92 transmit 257 treatment of NC 27 treatment of unused input pin 26 U UABT it eaten hi
17. 410 addressing area 25 addressing mode 405 architecture 32 30 architecture 20 00000 30 area mode register 0 AMDO bit function of 121 area mode register 0 AMDO configuration of 121 area mode register 1 AMD1 bit function of 123 area mode register 1 AMD1 configuration of 123 area mode register 32 AMD32 bit function of 124 area mode register 32 AMD32 configuration of 124 area mode register 4 AMD4 bit function of 125 426 area mode register 4 AMD4 configuration of 125 area mode register 5 AMD5 bit function of 126 area mode register 5 AMD5 configuration of 126 area select register ASR and area mask register AMR configuration 118 arithmetic 46 assembler source example 109 asynchronous start stop mode format of data transferred 257 asynchronous mode start stop 243 automatic algorithm execution status of 353 automatic erase operation status 365 automatic wait cycle of CBR refresh 192 automatic wait cycle timing chart
18. Read and Write Combination Cycle Timing Chart 50 area 16 bit bus width word read CS1 area 8 bit bus width half word read Figure 4 17 13 Example of Read and Write Combination Cycle Timing Chart BA1 2 1 2 Idle 1 2 1 BA A24 00 X_ 0 X 2 X 0 X D31 24 X 0 A O42 T 0 D23 16 X 3g X ow35 X X X X RDX 7 WROX i WR1X i i i i csox CS1X 1 l 5 gt Word read cycle Half word write cycle CSO area CS1 area Explanation of operation The above example shows the case where an idle cycle idle bus cycle is inserted in between the chip select areas When an idle cycle is inserted in between bus cycles the address of the previous bus cycle is output as is until the next bus cycle starts Because of this CSO to CS5X which corresponds to the output address are continuously asserted The above example is a combination of 16 bit and 8 bit data buses As the maximum bus width is 16 bits D23 to D16 WR1X do not become ports even in the 8 bit access area the CS1 area D23 to D16 output indefinite data and WR1X is negated 170 4 17 Bus Timing 4 17 6 Automatic Wait Cycles This section provides an automatic wait cycle timing chart Automatic Wait Cycle Timing
19. enn 304 14 4 PWM Cycle Setting Register sssssssssssssssess esent enn sinn nens 308 14 5 PWM Duty Cycle Setting Register PDUT 309 14 6 PWM Timer Register seni NA 310 14 7 General Control Register 1 200444 1110 0 00 311 14 8 General Control Register 2 GCN2 2 22 2 10 314 14 9 PWM Operation i rere tr ERR e eee itu Lei d ruat 315 14 10 One Shot Operation 317 IL EMI 319 14 12 Constant L or Constant Output from PWM Timer 320 14 13 Starting Multiple PWM Timer Channels 321 5 323 15 1 Overview ot DMAQG cene epee ie eens nee ia 324 15 2 DMAC Parameter Descriptor Pointer DPDP 2 2 202 24 1 010 326 15 3 DMAC Control Status Register DACSR 327 15 4 DMAC Pin Control Register DATOR rrangata nnana aaa a aaa Ea aa aaa 329 15 5 Descriptor Register in RAM 332 15 6 DMAC Transfer Modes 335 15 7 Output of Transfer Request Acknowledgment and Transfer End signals
20. fini Pe OG E Ev DREQn I rx Addr pin D XD XD X 0H XH XL Data pin D XD Xp XsH XuH WHL XL gt RDXD 522 24 22 2 2 2 2 25 222 7 WRnX DACK EOP 348 15 9 DMAC Timing Charts 15 9 4 Transfer Termination Timing Charts This section shows transfer termination timing charts Transfer Termination When Either Address is Unchanged O Bus width 16 bits data length 8 16 bits CLK 1 1 Addr pin D Xs X Xp Xs 3 Xp XL Data pin D gt lt 8 AD gt K s XD X 2L RDXD WRnX XW XC XW XX WX AWX AKD 1 L Lj LJ LCT oss ee EPSE 1 Lf 2 AKSE 1 DACK EPDE 1 Both are 1 o L O Bus width 16 bits data length 32 bits CLK Addr pin Data pin lt SPP lt Sm RDXD WRnX XwX XW XK WX XW XX WX XW AKDE 1 Both are 1 RER EPSE 1 EOP AKSE 1 DACK EPDE 1 Both are 1 349 CHAPTER 15 DMAC Transfer Termination When Both Addresses are Changed O Bus width 16 bits data length 8 16 bits CLK Addr pin D AS XD AS XD AsH Data pin gt lt 5 XD gt lt 5 XD AH gt RDXD WRnX AKSE 1 AKDE 1 Botharet U 2 EPSE 1 EPDE 1 Lm Both are 1 LJ Bus width 16 bits data length 32 bits
21. 36 program status 37 program status register 39 PWM cycle setting register PCSR 308 PWM duty cycle setting register PDUT 309 PWM 4 4 48 0 315 PWM timer register 01 002 42122 301 PWM timer register 310 PWM timer characteristic 300 PWM timer general block diagram of 302 PWM timer L or H output from 320 Q QFP 100 outside dimension 7 QFP 100 pin 10 R read and write combination cycle timing chart 170 read cycle timing 166 read timing chart hyper DRAM interface 188 read timing chart single DRAM interface 185 read reset command 361 ready busy signal 364 receive operation 257 recovery from sleep or stopped state 28 refresh control register RFCF bit function of 130 refresh control register RFCR configuration of 130 register of clock generator and controller 74 register
22. CLK Pp gp el ET Er Addr pin Data pin SH SL DH DL SH SL DH DL 1H RDXD eS es ee ee WRnX wX XWX XWX AWX XAWX AKSE 1 Lo L J LJ ee erp EE Boharei LT LI mr EPSE 1 Le celica eR aS SS EOP EPDE 1 a G EX Both are 1 PC ubt e CLK a Jor i a Addr pin 2H Data pin XL X RDXD LE WRnX 350 CHAPTER 16 FLASH MEMORY This chapter explains the flash memory functions and operations The chapter provides information on using the flash memory from the FR CPU For information on using the flash memory from the ROM writer refer to the user s guide for the ROM writer 16 1 Outline 16 2 Block Diagram of Flash Memory 16 3 Flash Memory Status Register FSTR 16 4 Sector Configuration of Flash Memory 16 5 Flash Memory Access Modes 16 6 Starting the Automatic Algorithm 16 7 Execution Status of the Automatic Algorithm 351 CHAPTER 16 FLASH MEMORY 16 1 Outline of Flash Memory This device type has an internal flash memory of 254 kilobytes 2 megabits that enables to perform the following functions with a single 3 V power supply simultaneous erasure of all sectors erasure in sector units and writing in half word 16 bits units via the FR CPU The flash memory employed here is basically the same as the Fujitsu 2 megabit 254 kilobits x 8 or 127 kilobits x 16 fl
23. DO7 150 4 16 Relationship between Data Bus Widths and Control Signals 4 16 3 External Access This section lists several external accesses Word Access Bus width 16 bit bus width Big endian mode Internal register External pi Control pin address 0 2 D31 D31 AA AA CC WROX CASL WEL BB WR1X CASH WEH CC DD Little endian mode Internal register External pin Control pin address 0 2 D31 D31 AA DD BB WROX CASL WEL BB WR1X CASH WEH DD 8 bit bus width Internal register External pin Control pin address 0 1 2 3 D31 D31 AA CC DD WROX CAS WE BB cc DD Internal register External pin Control pin address 0 1 2 3 D31 D31 AA DD BB WROX CAS WE BB cc DD 151 CHAPTER 4 BUS INTERFACE B Half Word Access Bus width Big endian mode Little endian mode 16 bit bus width Internal register External pin Control pin Internal register External pin Control pin address 0 address 0 D31 D31 D31 D31 AA WROX CASL WEL BB WROX CASO WEL BB WR1X CASH WEH AA WR1X 51 WEH Internal register External pin Control pin Internal register External pin Control pin address 2 address O D31 D31 D31 D31 WROX CASL WEL DD WR
24. 22 166 Example 2 of Read Cycle Timing Char 2 entrent 166 Example of Read Cycle Timing Chart enne 166 Example 4 of Read Cycle Timing Chart sess 167 Example 5 of Read Cycle Timing Chart 22 167 Example 1 of Write Cycle Timing Chart ssssssssssssseeeeennennneren nennen nenne 168 Example 2 of Write Cycle Timing 0 2 1 nennen nenne 168 Example of Write Cycle Timing 168 Example 4 of Write Cycle Timing Chart sssssssssssssseeneeneeneneen nennen enne 169 Figure 4 17 12 Figure 4 17 13 Figure 4 17 14 Figure 4 17 15 Figure 4 17 16 Figure 4 17 17 Figure 4 17 18 Figure 4 17 19 Figure 4 17 20 Figure 4 17 21 Figure 4 17 22 Figure 4 17 23 Figure 4 17 24 Figure 4 17 25 Figure 4 17 26 Figure 4 17 27 Figure 4 17 28 Figure 4 17 29 Figure 4 17 30 Figure 4 17 31 Figure 4 17 32 Figure 4 17 33 Figure 4 17 34 Figure 4 17 35 Figure 4 17 36 Figure 4 17 37 Figure 4 17 38 Figure 4 17 39 Figure 4 18 1 Figure 4 18 2 Figure 5 1 1 Figure 6 1 1 Figure 6 1 2 Figure 6 5 1 Figure 6 6 1 Figure 6 6 2 Figure 6 7 1 Example 5 of Write Cycle Timing 2 0 22 0 01 eene enn 169 Example of Read and Write Combination Cycle Timing Chart 170 Example o
25. 401 execution status of automatic algorithm 353 external bus 143 external bus operation program example for 196 external bus operation program specification example for sse 196 external bus request 161 external 256 external clock not on USING 26 external interrupt operation 216 external interrupt operation procedure 216 external interrupt request level 217 external interrupt request register EIRR 214 external interrupt NMI controller block diagram 212 external interrupt NMI controller register 212 external level register ELVR 215 external pin control register 0 EPCRO bit UNCION OF bee tie 132 external pin control register 0 EPCRO Configuration 132 external pin control register 1 EPCR1 bit function 135 external pin control register 1 EPCR1 configuration 2222 2 135 external pin function I O port or control pin selection 205 external reset or software reset releasing from68 external reset signal input 26 external transfer from internal
26. 4 17 Bus Timing O Bus width 8 bits access half words Figure 4 17 6 Example 4 of Read Cycle Timing Chart 1 2 BAI BA2 BAI BA2 BA2 ert A2400 X 0 X H X X 3543 X D31 24 4057 CH 2 483 023 16 ROM s qo eI IS O Bus width 8 bits access bytes Figure 4 17 7 Example 5 of Read Cycle Timing Chart BA1 BA2 1 BA2 BA BA2 BA alma E 1 A24 00 X 4 D31 24 0 gt X 1 5 X 2 gt X 3 023 16 RDX 1 167 CHAPTER 4 BUS INTERFACE 4 17 4 Write Cycles in Each Mode This section provides write cycle timing charts in each mode Write Cycle Timing Chart O Bus width 16 bits access words Figure 4 17 8 Example 1 of Write Cycle Timing Chart BAI 2 BAI 2 24 00 X 0 2 X D31 24 X 0 X 2 X 023 16 Y 1 X R x WROX WRIX C Bus width 16 bits access half words Figure 4 17 9 Example 2 of Write Cycle Timing Chart BAI BA2 BAT BA2 cx A24 00 X 0
27. Reserved for the system 380 000FFF44 Table B 2 Interrupt Vectors 2 2 Interrupt cause Reserved for the system Interrupt number Decimal Hexa decimal Interrupt level 1 APPENDIX B Interrupt Vectors Offset TBR default address 2 000FFF40 Reserved for the system 000FFF3C Reserved for the system 000FFF38 Reserved for the system 000FFF34 Reserved for the system 000FFF30 Reserved for the system 000FFF2C Reserved for the system 000FFF28 Reserved for the system 000FFF24 Reserved for the system 000FFF20 Reserved for the system 000FFF1C Reserved for the system 000FFF18 Reserved for the system 000FFF14 Reserved for the system 000FFF10 Reserved for the system 000FFF0C Reserved for the system 000FFF08 Reserved for the system 000FFF04 Delay interrupt cause bit 000FFFO0 System reservation used by REALOS 3 000FFEFC System reservation used by REALOS 3 000FFEF8 Used for INT instruction OOOFFEF4 to OOOFFCOO 1 ICR is a register provided in the interrupt controller that sets an interrupt level for each interrupt request It is provided for each interrupt request 2 TBR is a register that indicates the first address of vector tables for EIT The address gi
28. The serial input data register SIDR is a data buffer register for receiving data and the serial output data register SODR is a data buffer register for transmitting data When 7 bit data is used bit 7 D7 is invalid Write to the SODR register when TDRE of the SSR register is 1 Configuration of Serial Input Data Register SIDR and Serial Output Data Register SODR 252 The configuration of the serial input data register SIDR and serial output data register SODR is shown below Initial value 7 6 5 4 3 2 1 0 Adress 0000217 Undefined 7 6 5 4 3 2 1 0 hae eine as above D7 06 05 4 D2 Di 00 Undefined W lt Note gt An instruction to write to the above address means to write to the SODR register and an instruction to read from the above address means to read the SIDR register 10 5 Serial Status Register SSR 10 5 Serial Status Register SSR The serial status register SSR consists of flags that show the UART operating status Configuration of Serial Status Register SSR The configuration of the serial status register SSR is shown below 99025 re r Rone 00001 00 RW Bit Function of Serial Status Register SSR bit 7 PE Parity Error This bit is an interrupt request flag that is set when a parity error is detected for received data To clear the flag once it is set set the REC
29. 000 0000 256 00100000 FFFFFFFFH lt Note gt HalfWord I O Word Other I O Access inhibited Internal RAM or access inhibited External area Instruction ROM or external area Internal ROM or external area External area The external areas cannot be accessed in single chip mode The MB91F109 assigns internal ROM area 060000 to 0CO7FF to 2 kilobytes of internal RAM 45 CHAPTER 2 CPU 2 7 Instruction Overview The FR series supports logical operation bit manipulation and direct addressing instructions which are optimized for embedding applications in addition to general RISC instructions Each instruction which is 16 bits long Some are 32 bits or 48 bits long shows excellent memory use efficiency See Appendix E Instructions for details about instructions The instruction set can be divided into the following function groups Arithmetic operation Load and store Logical operation and bit manipulation Direct addressing 46 Instruction Overview O Arithmetic operation Arithmetic operation includes the standard arithmetic operation instructions addition subtraction and comparison and shift instructions logical shift and arithmetic shift For addition and subtraction operation with carry for multiword length operation and operation without changing the flag value which is useful for address calculation are also
30. 295 detection 296 device handling e E A 26 DICR DLYI 222 direct 47 direct addressing 25 44 direct addressing instruction 422 DMA controller 3 DMA request suppression register PDRR bit TUNCUON Of e 80 DMA request suppression register PDRR 80 DMA suppression circuit block diagram 103 DMA suppression setting for 103 DMA transfer for interrupt with higher priority suppression 339 DMA transfer request using resource interrupt request aS 8 eis 339 DMAC block diagram 325 DMAC 324 DMAC control status register DACSR bit function of 327 DMAC control status register DACSR configuration 327 DMAC internal register transfer to 340 DMAC parameter descripter pointer DPDP 326 DMAC pin control register DATCR Dit TUnctlOn Of cerne 330 DMAC pin control register DATCR configuration 329 DMAC 8040 324 DMAC transfer o
31. 399 section type restriction 401 sector configuration of flash memory 357 SOClOF raS ms 362 sector erase operation status 366 367 serial control register SSR bit function of 250 serial control register SSR configuration of 250 serial input data register SIDR and serial output data register SODR configuration of 252 serial mode register SMR bit function of 248 serial mode register SMR configuration of 248 serial status register SSR bit function of 253 serial status register SSR configuration of 253 shift 412 simulator 402 single conversion 276 single DRAM interface read timing chart 185 single DRAM interface write timing chart 186 single DRAM interface timing chart 187 single PWM timer channel block diagram of 303 single block transfer 335 sleep controller block diagram 95 sleep mode DMA transfer operation in 340 Sleep or stopped state recovery from 28 sleep state outline 90 sleep state
32. 6 Outside Dimensions 100 06 7 Outside Dimensions of FPT 100P MO5 2 4 4 46 000 00000 0000 enne nennen nnns 8 Outside Dimensions of BGA 112P MO1 0 000000 440 0 eene 9 QFP 100 Pin Arrangements adotar drana opani idodi Dotie dinaa 10 LQFP 100 Pin Arrangements sss nennen eene nnn trennen nnn snnt snnt ens 11 FBGA 112 Pin Arrangements ssssssssssssssssseee 12 MB91F 109 Memory ere xe teta eee hrs 24 Example of Using an External Clock Normal Method 2 26 Example of Using an External Clock Possible at 12 5 MHz or Lower 27 Internal Architecture 31 Instr ction Pipeline iae Rete ettet ee 32 Configuration of general purpose registers 2 33 Configuration of special registers 2 242 0 0 34 Configuration of General Purpose Registers 35 Configuration of Special Registers 20020 36 Data Mapping in Bit Ordering Mode 2 22224400 4000 0 nennen nnne enne 42 Data Mapping in Byte Ordering Mode sssssssssesseeneennee eene 42 MB91F109 Memory a 44 Memory Map Common to the FR Series 45 Example of Interrup
33. DACK2 DSCR C1HE bit and DATCR AKSE2 AKDE2 bits AKSE2 AKDE2 000 PB6 100 CS1H Other DACK2 PB7 DW1X DSCR DW1E 0 PB7 1 DW1X 19 to 21 MDO to MD2 MDO to MD2 15 NMIX NMIX 75 to 78 ANO to AN3 ANO to AN3 AIC AIO to AI3 bits 0 ANO to AN3 1 setting not possible 98 to 97 PEO to PE1 INTO to INT1 PEO INTO to PE1 INT1 Table 5 4 3 External Bus Functions to be Selected 3 4 Pin No 92 to 91 Pin code PE2 to INT2 to SC1 to SC2 Initial value PE2 INT2 to PE3 Pin values always input to INTO to INT1 Switch over register SMR SCKE 0 pin values are input to SC1 and SC2 1 SC1 and SC2 output 90 to 89 PE4 to PES DREQO DREQ1 PEA DREQO to DREQ1 Pin values are always input to DREQO DREQ1 88 to 87 PE6 to DACKO DACK1 PE6 to PE7 DATCR 5 0 1 AKDEO 1 0 PE6 PE7 1 DACKO DACK1 PFO TRGO 510 PFO SIO TRGO Pin values are always input to SIO and TRGO during operation PF1 TRG1 500 PF1 TRG1 SMR SOE 0 PF1 1 SOO output Pin values are always input to TRG1 during operation 207 CHAPTER 5 I O PORTS Table 5 4 3 External Bus Functions to be Selected 3 4 Pin code Initial value Switch over register PF2 SCO PCNL POEN input 0 PF2 1 OPCA3
34. DMAC 5 end error 000FFF80 DMAC 6 end error 000FFF7C DMAC 7 end error 000FFF78 A D 000FFF74 Reload timer 0 000FFF70 Reload timer 1 000FFF6C Reload timer 2 000FFF68 PWM 0 000FFF64 PWM 1 000FFF60 PWM 2 000FFF5C PWM 3 Table 8 5 2 Relationships among Interrupt Causes Numbers and Levels 2 2 000FFF58 Cause of interrupt Interrupt number Interrupt Offset TBR default Decimal Hexadecimal ids ace U TIMER 0 42 2A ICR26 3544 000FFF54 U TIMER 1 43 2B ICR27 350 000FFF50 U TIMER 2 44 2C ICR28 34Cy OOOFFF4C Flash memory 45 2D ICR29 3481 OOOFFF48 Reserved by the system 46 2E ICR30 3444 OOOFFF44 Reserved by the system 47 2F ICR31 3404 OOOFFF40 Reserved by the system 48 30 33Cy OOOFFF3Cy Reserved by the system 49 31 x 3384H 000FFF38 Reserved by the system 50 32 334 OOOFFF34 Reserved by the system 51 33 330 000FFF30 Reserved by the system 52 34 E 32 000FFF2C Reserved by the system 53 35 328 OOOFFF28 232 8 5 Priority Check Table 8 5 2 Relationships among Interrupt Causes Numbers and Levels 2 2 Cause of interrupt Interrupt number Interrupt TBR default level address Decimal Hexadecimal Reserved by the system OOOFFF24 Reserved by the system OOOFFF20 Reserved by the system OOOFFF1C
35. Start trigger m n 0 PWM Tari us T Count clock cycle m PCSR value T m 1 us n PDUT value 316 14 10 One Shot Operation 14 10 One Shot Operation One shot operation outputs a single pulse One Shot Operation Upon detection of a trigger in one shot operation mode the PWM timer can output a single pulse of arbitrary width When an edge is detected during operation while restart is enabled the counter is reloaded Figure 14 10 1 shows a timing chart for one short operation performed while trigger restart is disabled Figure 14 10 2 shows a timing chart for one shot operation performed while trigger restart is enabled 317 CHAPTER 14 PWM TIMER O Trigger restart disabled Figure 14 10 1 One Shot Operation Timing Chart Trigger Restart Disabled A rising edge is detected A trigger is ignored Start trigger 9 PWM F o 5 3 D T n 1 us T Count clock cycle 2 otmen Trigger restart enabled Figure 14 10 2 One Shot Operation Timing Chart Trigger Restart Enabled A rising edge is detected Operation is restarted by a trigger Start trigger m 2 2 n 0 PWM D T n 1 ns T Count clock cycle m PCSR value T m 1 us n PDUT value 318 14 11 Interrupt 14 11 Interrupt Figure 14 11 1 shows the causes of interrupts
36. ene ete 24 1 8 Handling of Devices oti aei delere en Dien e dun us 26 2 GPU e Em 29 24 CRU Architecture niece deep te qe i ld pta EE HE 30 242 ntermal Architecture ure dete t de EE per et al ree terti ete ve Perte bed 31 2 3 Programming Model 33 2 3 1 General Purpose Registers 35 2 3 2 Special Registers oer e d tit d dd dn 36 2 3 3 Program Status Register PS 39 24 9 5 HMM 42 2 5 Word Alignment eo eoe eb EP 43 2 67 Memory Map oir ect tre rec trn E ed ib Gor etiarn tete th e bL PED 44 2 4 Instruction OVEM W D On E GE DR POLT tria tede 46 2 7 1 Branch Instructions with Delay Slots 48 2 7 2 Branch Instructions without Delay Slots sssssssssssssssseseeee eene nnne nnne 51 2 8 Exception Interrupt and Trap 52 282 ElT Interr pt Eevels i e tette ted e nitas dettes 54 2 8 2 Interrupt Control Register ICR 4 2 2 1 01 56 2 8 3 System Stack Pointer SSP iuri t Rr dantes steele edt tasted 57 2 8 4 Interrupt StacK
37. entente renis 312 Selection of Gh1 Trigger Input ttt tte tee re vp i nee 313 Selection of Trigger Input sssssssssssssseseeenenneen enne nennen entrent nnne renis 313 Channel Descriptor Addresses 2 2 2 enne nnne 326 Selection of Transfer Input Detection Levels 2 330 Specification of Transfer Request Acknowledgment Output 330 Specification of Transfer End Output 331 Specification of Transfer Source or Destination Address Update Modes 333 Address Increment Decrement Unit essere nnne nene 333 Specification of Transfer Data Size 333 Transfer Mode Specification sssesssssssssssssesse essent 334 Codes Used in the Timing Charts 2 22022440 0 0 342 Sector Addresses c ee 358 tete E t ated i oe e eas 361 Statuses of the Hardware Sequence 365 l Q Map 1 6 E PERPE 371 lt 2 aes HU RU ee eddie 372 lentem 373 Table A 4 Table
38. 100 8 outside dimension 100 7 P peripheral clock block that 89 pin arrangement 112 2 12 pin arrangement 100 11 pin arrangement 100 10 pin condition 27 PINTUNCHON AEEA E ertt 14 pin status for each CPU 384 pin status list term used in 383 PLL clock setting example of 108 PLL control register PCTR bit function of 86 PLL control register PCTR configuration of 86 port data register PDR configuration of 203 POSTPONING 99 power pins Vcc Vss connection of 27 power save 4 power on reset initialization by 28 DpoWer on al e e deca 27 power on input of source oscillation 27 power on pin condition 27 PPDR register 340 priority COCK 231 program FCA 362 program access 22 22 2 43 program counter
39. For details see the description of the mode register in Section 2 10 Operation Mode 68 2 10 Operation Mode 2 10 Operation Mode Two operation modes bus mode and access mode are available The mode pins MD2 MD1 and MDO and mode register MODR are used to control the operation mode Operation Mode Two operation modes bus mode and access mode are available _Bus mode e Recess mode Single chip Internal ROM external bus 16 bit bus width gt External ROM external bus 8 bit bus width O Bus mode In bus mode the operations of internal ROM and external access functions are controlled The mode pins MD2 MD1 MDO and the M1 MO bits of the mode register MODR are used for control in this mode O Access mode In access mode external data bus width is controlled The mode pins MD2 MD1 MDO and the BW1 and BWO bits of the area mode registers AMDO AMD1 AMD32 AMD4 AMD5 are used for control in this mode B Mode Pins Three mode pins MD2 MD1 and MDO are used for operation specification as shown in Table 2 10 1 Table 2 10 1 Mode Pins and Setting Modes Mode pins Mode name Reset External data Remarks vector bus width MD MDi MD access area External External External ROM vector mode 0 external bus mode External External External ROM vector mode 1 external bus mode Reserved Internal vector Internal Mode register Single chip mode mod
40. RDRF is set when received data is loaded to the SIDR register and is cleared when the data is read from the SIDR register Mode 1 does not support the parity check function and mode 2 does not support the parity check and framing error detection functions TDRE is set when the SODR register is emptied and ready to accept the next instance of write data and is cleared when the next data item is written to the SODR register In data receptuion mode PE ORE FRE or RDRF is used to request an interrupt In data transmission TDRE is used to request an interrupt B Interrupt Flag Set Timing for Data Reception in Mode 0 When the last stop bit is detected after data reception transfer is completed the PE ORE FRE and flags set to issue an interrupt request to the CPU If PE ORE or FRE is active the SIDR data is invalid Figure 10 9 1 ORE FRE and RDRF Set Timing Mode 0 Data PE ORE FRE RDRF Reception interrupt 260 10 9 UART Interrupt Occurrence and Flag Setting Timing B Interrupt Flag Set Timing for Data Recepion in Mode 1 When the last stop bit is detected after data reception transfer is completed the ORE FRE and RDRF flags are set to issue an interrupt request to the CPU Since the length of data items that can be received is eight bits the data at the last bit bit 9 indicates an address or that data is invalid If ORE or FRE is active the SIDR data is invalid Figure 10 9 2 ORE
41. The procedure for returning from the stop state to the normal run state is as follows Interrupt generation gt restart of oscillation circuit operation gt wait for oscillation stabilization gt restart of internal peripheral clock supply after stabilization gt restart of internal DMA clock supply gt restart of internal bus clock supply gt restart of internal CPU clock supply Program execution after the oscillation stabilization wait time is as follows When the level of the interrupt is enabled by the flag of CPU ILM The program saves the register fetches the interrupt vector and executes processing beginning from the interrupt processing routine When the level of the interrupt is disabled by the flag of CPU ILM The program executes instructions beginning from the instruction following the instruction that caused the transition to the stop state O Return by way of the RSTX pin The procedure for returning from the stop state to the normal run state is as follows 93 CHAPTER 3 CLOCK GENERATOR AND CONTROLLER 94 L level application to RSTX pin gt occurrence of internal reset gt restart of oscillation circuit operation gt wait for oscillation stabilization gt restart of internal peripheral clock supply after stabilization gt restart of internal DMA clock supply gt restart of internal bus clock supply gt restart of internal CPU clock supply gt reset vector fetch
42. These bits are reserved bits Their values during read operations are undefined and they do not affect write operations bit 0 reserved bit This bit is a reserved bit Read operations for this bit return 0 Always set this bit to 0 When the bit is set to 1 the results of subsequent operations may become uncertain This bit is initialized to 0 during a reset 16 4 Sector Configuration of Flash Memory 16 4 Sector Configuration of Flash Memory Figure 16 4 1 shows the sector configuration of the flash memory Table 16 4 1 lists the respective sector addresses Sector Configuration of the Flash Memory Flash memory address mapping for access from the FR CPU is different from the mapping for access from the ROM writer This section shows the mapping for access from the CPU Figure 16 4 1 Memory Map and Sector Configuration 0 SA9 16Kbyte MSB side 16 bits LSB side 16 bits RR 31 16 45 FFFFFFFFh OFFFFC Dh OFFFFE Fh SA4 16Kbyte OF8000 1h 0 8002 3 F7FFC Dh SF 40004 h SA3 8Kbyte SA8 8Kbyte SF 4002 3h OF3FFE Fh OF0002 3h OEFFFE Fh OF3FFF Dh OF0000 1h SA2 8Kbyte OEFFFC Dh SA1 32Kbyte 0E0000 1h ODFFFC Dh SA6 32Kbyte SA5 63Kbyte 0E0002 3h ODFFFE Fh 10000h Flash memory area 0C0800h 0C0800 1h 0CO7FC Dh 0C0000 1h Memory map Sector configuration SA sector address 0C0802 3h 0CO7FE Fh 0C0002 3h SA0 63Kbyte RAM 1Kbyte R
43. bit counter Reception parity counter Reception status check circuit Reception error generation signal for DMA to DMAC Reception shifter to CPU Transmission control circuit Tranmission start circuit Tranmission bit counter Tranmission parity counter SO lt o Transmit data Transmission shifter Start of transmission MD1 gt SMR register CSO gt SCKE m SOE PEN SBL register AID REC RXE TXE SSR register PE ORE FRE RDRF TDRE RIE TIE Control signal 247 CHAPTER 10 UART 10 2 Serial Mode Register SMR The serial mode register SMR specifies the UART operation mode Set the operation mode while UART operation is stopped Do not write to the register during UART operation Configuration of Serial Mode Register SMR The configuration of the serial mode register SMR is shown below 0 Address 000028 CORSE 10020908 RAN R W RAN RW B Bit Functions of Serial Mode Register SMR bit 7 6 MD1 MDO MoDe select These bits select the UART operation mode Table 10 2 1 Selection of UART Operation Modes Operating mode Asynchronous start stop normal mode Initial value Asynchronous start stop multiprocessor mode CLK synch
44. 1 2 When label20 PC 2 is from 0x800 to 0x7fe an instruction is created as follows CALL label12 When label20 PC 2 is outside of the range in 1 and includes an external reference symbol an instruction is created as follows LDI 20 label20 Ri CALL Reference 2 BRA20 1 2 When label20 PC 2 is from 0x100 to 0xfe an instruction is created as follows BRA label9 When label20 PC 2 is outside of the range in 1 and includes an external reference symbol an instruction is created as follows LDI 20 label20 Ri JMP Reference 3 Bcc20 1 When label20 PC 2 is from 0x100 to 0xfe an instruction is created as follows Bcc label9 APPENDIX E Instructions 2 When label20 PC 2 is outside of the range in 1 and includes an external reference symbol an instruction is created as follows Bxcc false xcc is the exclusion condition of cc LDI 20 label20 Ri JMP QHi false B 20 Bit Delayed Branch Macro Instructions Table E 1 15 20 Bit Delayed Branch Macro Instructions Mnemonic Operation Remarks CALL20 D label20 Ri Next instruction address 2 gt RP Ri Temporary register See Reference 1 label20 gt PC BRA20 D label20 Ri label20 gt PC Ri Temporary register See Reference 2 BEQ20 D label20 Ri if Z 1 then label20 gt PC Ri Temporary register See Reference 3 BNE20 D label20 Ri t S Z 0 BC20 D label20 Ri 1 s C BNC20 D label20 Ri 1 s C 0 BN20 D label20 Ri 1
45. 171 automatic wait cycle timing chart in usual DRAM 181 automatic write operation status 365 automatic write erase operation status 366 available 5 B basic read cycle timing chart 162 basic write cycle timing chart 164 baud rate and U TIMER reload value sample Setting TOL ioter it een cc tenet 265 baud rate 243 sj 284 bit operation 411 Bit ordei 42 bit search 4 bit search module 292 bit search module block diagram of 292 block diagram of MB91F 109 general 6 block that uses peripheral clock 89 irem c LR 46 branch instruction with delay slot 48 branch instruction with delay slot restriction on 50 branch instruction with delay slot theory of operation of 48 branch instruction without delay slot 51 branch instruction without delay slot theory of Operation of e eere eel 51 built in adder eee 30 burst transfer 337 DUS acces
46. 245 10 1 Overview of UART aei p de tuU 246 10 2 Serial Mode Register SMR a ea aaa aan ea are r aeae N a aaa Ea aaa a Eai aeaa daaa naaa sa aeie 248 10 3 Serial Control Register 250 10 4 Serial Input Data Register SIDR and Serial Output Data Register SODR 252 10 5 Serial Status Register SSR a inti ii aa 253 10 6 VART Operation 2 fetu b ine ee 255 10 7 Asynchronous Start Stop Mode sssssssssssssssssseeeeee eene nennen entren nnn nennen inns 257 10 8 GEK Synchronous iot petente titt Ete EE ea Pan 258 10 9 UART Interrupt Occurrence and Flag Setting Timing 260 10 10 Notes on Using the UART and Example for Using the UART 2 263 10 11 Setting Examples of Baud Rates and U TIMER Reload Values 265 CHAPTER 11 A D CONVERTER Successive approximation type 267 11 1 Overview of A D Converter Successive Approximation 268 14 2 Control Status Register ADCS i tenet nit taret ertt E oet 270 11 3 Data Register ADCR 2 22 1 275 11 4 A D Converter Operation 276 11 5 Conversion Data Protection Function ssssesssss
47. 8 bit data is accessed with a STB or LDB instruction STB 14 r5 If the MB91F109 accesses data with an operation for of a different size the data value cannot be guaranteed For example when two consecutive 16 bit data areas are simultaneously accessed using a 32 bit access instruction the data values cannot be assured 400 APPENDIX D Notes on Using Little Endian Areas D 3 Linker flnk911 The following two items require caution with respect to link time section allocation during program design when employing little endian areas e Restriction on section types Nodetection of errors Restriction on Section Types Only data sections with no initial value can be allocated to little endian areas If data stack and code sections with initial values are allocated to little endian areas the result of subsequent operations cannot be guaranteed because operations such as resolving addresses are executed by the linker in big endian areas B No Detection of Errors The linker outputs no error messages for allocations that violate the above restriction because it does not recognize little endian areas Before using little endian areas check the contents of the sections allocated to those areas 401 APPENDIX D Notes on Using Little Endian Areas D 4 Debuggers sim911 eml911 and mon911 This section provides notes on the simulator debugger and emulator or monitor debugger B Simulator Debugger Ther
48. 80000000 7FFFFFFCH 7FFFFFFCH 8 7 lt 58 2 8 EIT Exception Interrupt and Trap 2 8 5 Table Base Register TBR The table base register TBR indicates the first address of the EIT vector table B Table Base Register TBR The configuration of the table base register TBR is shown below bit31 gt 0 Initial value TBR 000FFC00m The address obtained by adding the offset defined for each EIT cause to the TBR is a vector address The initial value after resetting is OOOFFCOO 59 CHAPTER 2 CPU 2 8 6 EIT Vector Table The 1 kilobyte area beginning from the address indicated by the table base register TBR is the EIT vector area E EIT Vector Table The area size per vector is 4 bytes The relationship between a vector number and vector address is represented as follows vetadr TBR vctofs 3FCy 4 x vet vctadr vector address vctofs vector offset vet vector number The two low order bits of the result of addition are always treated as 00 The area ranging from 000 to 000FFFFF is the initial area of the vector table after it is reset 60 2 8 EIT Exception Interrupt and Trap Table 2 8 3 is the vector table in the architecture Special functions are assigned to some vectors Table 2 8 3 Vector Table Vector offset Vector number Explanation hexadecimal Hexadecima
49. 92 structure 22 396 suppression of DMA transfer for interrupt with higher 339 system condition code register SCR 40 system stack pointer SSP 37 57 table base register 37 59 37 temporary sector erase stop status 366 temporary stop 363 term used in pin status list explanation of 383 third word of 334 timebase 100 timebase timer clear register CTBR Dit TUNMCUONMOT bites 81 timebase timer clear register CTBR configuration 81 timing chart automatic wait 171 timing chart basic read cycle 162 timing chart basic write cycle 164 timing chart code used in 342 timing chart external wait cycle 172 timing chart hyper DRAM interface 190 timing chart read and write combination cycle 170 timing chart read 166 timing chart single DRAM interface 187 timing chart usual DRAM interface
50. Diffused resistor I Digital output Analog input 23 CHAPTER 1 OVERVIEW 1 7 Memory Address Space The logical address space of the FR series consists of 4 gigabytes 232 addresses and the CPU accesses them linearly Memory 0000 0000 0000 0000 0000 0001 FFFF 24 0000H 0400m 0800m 10004 18004 00004 Figure 1 7 1 shows the memory address space of the MB91F109 Figure 1 7 1 MB91F109 Memory External ROM external bus mode Internal ROM external bus mode Single chip mode Direct VO addressing area Access inhibited Access inhibited Access inhibited Internal RAM 2 KB Internal RAM 2 KB Internal RAM 2 KB Access inhibited Access inhibited Access inhibited See Abpendix A 0001 00004 External area Access inhibited 0008 00004 Access inhibited Access inhibited 000C 00004 External area Internal RAM 2 KB Internal RAM 2 KB 000C 08004 FLASH ROM FLASH ROM 254KB 254KB 0010 00004 External area Access inhibited FFFF Note The CPU can access no external areas in single chip mode To enable the CPU to access an external area select internal ROM external bus mode using the mode register 1 7 Memory Address Space O Direct addressing area The following area in the address space is
51. EPCRO BRE bit 0 P82 1 BRQ Table 5 4 2 External Bus Functions to be Selected 2 4 26 to 27 P83 RDX Pin code P84 to P85 WROX WR1X Initial value P84 P85 EPCRO RDXE bit 0 P83 1 RDX Switch over register Function automatically switches according to the mode set by MDO to MD2 AMDO to AMD5 and MO to M1 Single chip P84 and P85 8 bits WROX and P85 16 bits WROX and WR1X 14 to 12 PA 0 to PA2 to CS2X PA 0 to PA2 EPCRO COEO to COE2 bits 0 PAO to PA2 1 CS0X to CS2X 53 1 EPCRO bit and DATCR EPSE1 and EPDE1 bits COE3 EPSE1 EPDE1 000 100 CS3X Others EOP1 PA4 to PAS CS4X to CS5X PA4 to PAS EPCRO COE4 to COE5 bits 0 PA4 to PA5 1 CS4X to CS5X 6 EPCRO bit 0 PA6 1 CLK 99 to 100 1to2 PBO to PB3 RASO CSOL CSOH DWOX PBO to PB3 DSCR RSOE to DW1E bits 0 PBO to PB7 1 RASO to DWOX 206 PB4 RAS1 2 DSCR RS1E bit and DATCR EPSE2 EPDE2 bits RS1E EPSE2 EPDE2 000 PB4 100 RAS1 Other EOP2 Table 5 4 2 External Bus Functions to be Selected 2 4 Pin code 5 CS1L DREQ2 Initial value PB5 DREQ2 5 4 Using External Pins as I O Ports Switch over register DSCR C1LE 0 PB5 1 CS1L Pin values are always input to DESQ2 PB6 CS1H
52. Lp gt 3 gt EXTERNAL ADDRESS BUS address buffer shifter gt gt ASR gt gt 50 55 gt comparator DRAM control gt RASO RAS1 DMCR d CSOL CS1L CSOH CS1H underflow DWOX DW1X refresh counter from TBT T External pin control block Control of all registers amp control RDX WROX WR1X blocks BRQ BGRNTX lt gt RDY 114 4 2 Chip Select Area 4 2 Chip Select Area A total of six types of chip select area are prepared for the bus interface Setting Chip Select Areas 00000000H 00080000H OOOFFFFFH 0010 0011 0012 0013 0014 Each area be optionally located units of at least 64 kilobytes 4 gigabyte area using the area select registers ASR1 to ASR5 and area mask registers AMR1 to AMR5 If an attempt is made to access the area specified by these registers via the external bus the corresponding chip select signals CSOX to CS5X become active L When the registers are reset these pins excluding CSOX become inactive and are set to H lt Note gt Area 0 is allocated to a space other than the areas specified by ASR1 to ASR5 At reset time the external area other than 00010000
53. Reserved by the system 000 18 Reserved by the system OOOFFF14 Reserved by the system OOOFFF10 Reserved by the system OOOFFFOC Reserved by the system OOOFFFO08 Reserved by the system OOOFFF04 Delayed interrupt cause bit OOOFFFOO B Nonmaskable Interrupt NMI When NMI occurs simultaneously with other interrupts NMI is always selected O When NMI occurs the following types of information are posted to the CPU e Interrupt level 15 01111 Interrupt number 15 001111 O NMI detection NMI is set or detected by the external interrupt NMI module This module only generates an interrupt level and number according to an NMI request B Clearing Interrupt Causes Some restrictions apply between interrupts used to clear interrupt causes and the RETI instruction used in an interrupt routine See Section 2 8 EIT Exception Interrupt and Trap for details 233 CHAPTER 8 INTERRUPT CONTROLLER 8 6 Returning from the Standby Mode Stop Sleep This module implements the function to return from standby mode when an interrupt request is issued Returning from Standby Mode Stop or Sleep State When a peripheral interrupt request including NMI occurs a request to return from standby mode is issued to the clock controller The priority check block restarts operation when clock pulses are supplied after returning from the stop state Therefore the CPU ex
54. Rising edge Falling edge Both edges 305 CHAPTER 14 PWM TIMER 306 bit 5 IREN Interrupt request enable bit This bit enables or disables interrupt requests Disabled initial value Enabled bit 4 IRQF Interrupt request flag When the interrupt cause selected by bits 3 and 2 IRS1 and IRSO is generated while bit 5 IREN is set to 1 Enable this bit is set to cause an interrupt request to the CPU This Executing an operation for setting the bit to 1 does not change the bit value DMA transfer also starts if DMA transfer activation has been selected This bit is cleared when 0 is written to it or by the clear signal from the DMAC Executing an operation for setting the bit to 1 does not change the bit value A Read Modify Write instruction reads 1 from this bit regardless of the bit value bits 3 2 IRS1 IRSO Interrupt cause select bit These bits select the cause that sets bit 4 IRQF Table 14 3 4 Selection of Interrupt Causes IRS1 IRSO Interrupt cause Software trigger or trigger input Initial value Occurrence of counter borrow cycle matching Occurrence of duty cycle matching Occurrence of counter borrow cycle matching or duty cycle matching bit 1 POEN PWM output enable bit Setting this bit to 1 enables PWM output General purpose port Initial value PWM output pin bit 0 OSEL PWM output polarity specification bit This
55. XX CHAPTER1 OVERVIEW This chapter provides basic general information on the MB91F109 including its characteristics block diagram and function overview 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 MB91F 109 Characteristics General Block Diagram of MB91F 109 Outside Dimensions Pin Arrangement Diagrams Pin Functions I O Circuit Format Memory Address Space Handling of Devices CHAPTER 1 OVERVIEW 1 11 MB91F109 Characteristics The MB91F109 is a standard single chip microcontroller using a 32 bit RISC CPU FR30 series as its core It contains various I O resources and bus control mechanisms for embedded control applications that require high speed CPU processing This microcontroller contains 254 kilobyte flash ROM and 4 kilobyte RAM It has optimal specifications for embedding applications such as navigation systems high performance facsimiles and printer controls which require high CPU processing power Characteristics O FR CPU 32 bit RISC FR30 load store architecture 5 stage pipeline Operating frequency Internal 25 MHz external 25 MHz source oscillation 12 5 MHz with PLL used General purpose registers 32 bits x 16 16 bit fixed length instructions basic instructions one instruction per cycle Inter memory transfer bit processing and barrel shift instructions which are suitable for embedding applications Function entry exit instructions and register data multiload store instr
56. gt restart of instruction execution from reset entry address lt Notes gt e If a peripheral interrupt request has already been issued when 1 is written to STCR register bit 7 the writing is ignored and transition to the stop state does not occur After power on resetting every internal clock is supplied to initialize the internal states However after resetting other than power on resetting no internal clock is supplied during the oscillation stabilization wait time When transition to the sleep state has occurred because of a C bus RAM program do not use an interrupt but use resetting to return from the sleep state 3 10 Standby Mode Low Power Consumption Mechanism 3 10 2 Sleep State This section provides information on transition to the sleep state and returning from the sleep state Figure 3 10 2 shows a block diagram of the sleep controller Sleep Controller Block Diagram Figure 3 10 2 Sleep Controller Block Diagram r Sleep state transition request signal signal CPU clock Internal bus CPU clock generation Internal clock generation circuit Internal bus clock generation State decoder Internal interrupt Internal bus clock Internal reset Internal 77 DMA clock 77 2 5 generation External bus clock CPU hold request a Internal DMA clock External bus clock 3 o E o o o E o c 2
57. 0 15 006 0 15 006 Detail a 005 001 WS 010 142 s of B part 0 10 0 10 004 004 STAND OFF 0 50 0 20 020 008 Unit mm inches 1 3 Outside Dimensions Outside Dimensions FBGA 112 Figure 1 3 3 Outside Dimensions of BGA 112P M01 Ball pitch Plastic FBGA with 112 pins Ball matrix 11 Package width x length 10 00 x 10 00 mm Sealing Plastic mold Mount height 1 45 mm MAX Ball size 0 45 112 01 Plastic FBGA with 112 pins Note The actual corner shape may differ from the drawing BGA 112P M01 10 000 10 394 004 SQ_ 42224 1 25 oio 049 04 8 00 314 REF Mounting height 0 38 0 10 015 004 0 80 031 Stand off OC O D 66000000000 11 D D 9 D 8 D OOOO OOOO 7 D OOOO 6 5 0 10 004 O000 O0000 5 D 4 INDEX D 3 2 O q0000000000 LIKJHGFEDCBA pem 112 60 45 0 10 a 12 013 004 0 08 003 1998 FUJITSU LIMITED 1120015 20 2 Unit mm inches CHAPTER 1 OVERVIEW 1 4 Pin Arrangement Diagrams Figures 1 4 1 to 1 4 3 show the pin arrangements
58. 314 general purpose 33 35 H half word 141 148 152 hardware configuration 236 hardware sequence 364 Harvard Princeton bus converter 32 high coding 30 high speed page mode DRAM interface timing el ME 182 hold request cancel request level setting register HRCL bit function 230 hold request cancel request level setting register HRCL configuration of 230 hold request cancel request sequence 237 hold request cancel request criteria for 235 hold request cancel request interrupt level for 235 HRCL 339 hyper DRAM interface read timing chart 188 hyper DRAM write timing 189 hyper DRAM interface timing 190 flag uai e ed ae EH pt eden 55 circuit 22 Fio ripe 371 map how to 370 port 202 I O port basic block diagram of 202 immediate value setting or 16 31 bit immediate value transfer iiec tue
59. B Multiplication and Division Instructions Table E 1 5 Multiplication and Division Instructions Mnemonic MUL RjRi MULU Rj Ri MULH RjRi MULUH RJ Ri Operation Remarks Ri x Rj gt MDH MDL 32 bit x 32 bit 64 bit Ri x Rj gt MDH MDL Unsigned 16 bit x 16 bit 32 bit Ri x Rj gt MDL Unsigned Ri x Rj gt MDL DIVOS Ri DIVOU Ri DIVI Ri DIV2 DIV3 DIV4S DIV Rit gt gt DIVU Ri MDL Ri gt MDL Ri gt MDH MDL Ri gt MDL Ri gt MDH Step operation 32bit 32bit 32bit 1 DIVOS DIV1x 32 DIV2 DIV3 and DIVAS are created The instruction code length becomes 72 bytes 2 DIVOU and DIV1x 32 are created The instruction code length becomes 66 bytes 8 DIV3 instruction after the DIV2 instruction B Shift Instructions Table E 1 6 Shift Instructions Mnemonic Rj Ri u5 Ri u5 0 to 31 04 Ri u4 Ri Cycle NZVC Operation Ri lt lt Rj gt Ri Ri lt lt u5 gt Ri Ri lt lt u4 gt Ri Ri lt lt u4 16 gt Ri Remarks Logical shift Rj Ri u5 Ri u5 0 to 31 04 Ri 04 Ri Ri gt gt Rj gt Ri Ri gt gt u5 gt Ri Ri gt gt u4 gt Ri Ri gt gt u4 16 gt Ri Logical shift Rj Ri u5 Ri u5 0 to 31 04 Ri 04 Ri 412 gt gt Ri gt gt Rj gt Ri Ri gt gt u5 gt Ri Ri g
60. FUJITSU SEMICONDUCTOR CM71 10106 1E CONTROLLER MANUAL FR30 32 Bit Microcontroller 91 109 Hardware Manual FUJITSU FR30 32 Bit Microcontroller 91 109 Hardware Manual FUJITSU LIMITED PREFACE Objectives Trademarks and Intended Reader The MB91F109 has been developed as one of the 32 bit single chip microcontroller FR30 series products that use new RISC architecture CPUs as their cores It has optimal specifications for embedding applications that require high CPU processing power This manual explains the functions and operations of the MB91F109 for the engineers who actually develop products using the MB91F109 Read this manual thoroughly Refer to the instruction manual for details on individual instructions FR stands for FUJITSU RISC controller a product of Fujitsu Limited Embedded Algorithm is a trademark of Advanced Micro Devices Inc Organization of This Manual This manual consists of 16 chapters and an appendix Chapter 1 Overview Chapter 1 provides basic general information on the MB91F109 including its characteristics a block diagram and function overview Chapter 2 CPU Chapter 2 provides basic information on the FR series CPU core functions including the architecture specifications and instructions Chapter 3 Clock Generator and Controller Chapter 3 provides detailed information on the generation and control of the clock that controls the MB9
61. Rj Ri Rj Rj Rj gt gt gt gt gt gt gt gt gt gt gt gt Bit Operation Instructions Table E 1 4 Bit Operation Instructions Mnemonic BANDL u4 Ri BANDH u4 Ri BAND u8 OP Cycle NZVC Operation Ri amp 0xF0 u4 Ri amp u4 4 4 0x0F Ri amp u8 Word Word Half word Byte Remarks Lower 4 bits are subject to operation Upper 4 bits are subject to operation BORL u4 QRi BORH u4 Ri BOR 08 QRi Ri u4 Ri u4 lt lt 4 Ri u8 Lower 4 bits are subject to operation Upper 4 bits are subject to operation BEORL u4 Ri BEORH u4 Ri BEOR u8 QRi Ri u4 Ri 4 lt lt 4 Ri u8 Lower 4 bits are subject to operation Upper 4 bits are subject to operation BTSTL u4 Ri BTSTH u4 Ri Ri amp u4 Ri amp u4 lt lt 4 Lower 4 bit test Upper 4 bit test 1 The assembler creates BANDL if the bit is ON in u8 amp 0x0F and BANDH if the bit is ON in u8 amp 0xFO Both BANDL and BANDH may be created 2 assembler creates BORL if the bit is ON in u8 amp 0x0F and BORH if the bit is ON in 8 0 0 Both BORL and BORH may be created 411 APPENDIX E Instructions 8 assembler creates BEORL if the bit is ON in u8 amp 0x0F and BEORH if the bit is ON in u8 amp OxFO Both BEORL and BEORH may be created
62. The data length can be seven or eight bits in normal mode mode 0 but must be eight bits in multiprocessor mode mode 1 An A D bit is always added to data in multiprocessor mode instead of a parity bit Figure 10 7 1 Format of Data Transferred in Asynchronous Start Stop Mode Mode 0 or 1 Start LSB Mode 1 Transferred data is 010011015 O Receive operation The UART performs a receive operation as long as the RXE bit bit 1 of the SCR register is 1 When a start bit appears on the receiving line one data frame is received based on the data format specified by the SCR register If an error occurs after a frame has been received an error flag is set and the flag bit 4 of the SSR register is set subsequently thereby causing a receiver interrupt to the CPU if the RIE bit bit 1 of the same SSR register has been set to 1 Ensure in the program design that the flags of the SSR register are checked and the SIDR register is read if normal reception is indicated while the necessary processing for a countermeasure is performed if an error is indicated The flag is cleared when the SIDR register is read O Transmit operation Transmission data is written to the SODR register when the TDRE flag bit 11 of the SSR register is 1 When the TXE bit bit 0 of the SCR register is 1 the written data is transmitted When the data written to the SODR register is loaded to the transmission shift register and t
63. and BGRNTX set the BRE bit of EPCRO to 1 When releasing bus control set the corresponding pins to High Z and assert BGRNTX one cycle later B Bus Control Acquisition Figure 4 17 39 Example of Bus Control Acquisition Timing CLK A24 00 high Z r aC D31 16 high Z aC RDX high Z BRQ BGRNTX 1 Explanation of operation When performing bus arbitration by and BGRNTX set the BRE bit of EPCRO to 1 e When acquiring bus control negate BGRNTX and activate each pin one clock later 193 CHAPTER 4 BUS INTERFACE 4 18 Internal Clock Multiplication Clock Doubler MB91F109 has a clock multiplication circuit with which the inside of the CPU operates at a frequency one or two times that of the bus interface The bus interface operates synchronously with the CLK output pin regardless of which clock is chosen When an external access request is generated from the CPU access to the outside starts and waits for the CLK output to rise This device type is not provided with this function How to Choose Clocks For details on choosing the 1X and 2X clocks see Section 3 14 Clock Doubler Function A chosen clock can be optionally changed during chip operation When the clock is being switched the bus operation is temporarily suppressed When the chip is reset the 1X clock is selected automatically Figu
64. 000003FCH Read write R Initial value Undefined The result of 0 detection 1 detection or change point detection is read from this register The type of the detection result that is read from this register is determined by the data register written last 294 13 3 Bit Search Module Operation and Save Restore Processing 13 3 Bit Search Module Operation and Save Restore Processing This section explains the operations of the bit search module for 0 detection 1 detection and change point detection and also explains save and restore processing B O Detection The module scans the data written to the 0 detection data register from MSB to LSB and returns the position where the first 0 is detected The detection result can be obtained by reading the detection result register The relationship between the detected positions and the values to be returned are summarized in Table 13 3 1 If no 0 is found if the value is FFFFFFFF 32 is returned as the search result Execution example Write data Read value decimal 11111111 11111111 11110000 00000000g FFFFF000 gt 20 11111000 01001001 11100000 10101010g F849E0AA gt 5 10000000 00000010 10101010 101010106 8002 gt 1 11111111 11111111 11111111 111111116 FFFFFFFF gt 32 B 1 Detection The module scans the data written to the 1 detection data register from MSB to LSB and returns the position where the first 1
65. 00001 SSR R W SIDR R W SCR R W SMR R W UARTO 00001 00 XXXXXXXX 00000100 00 0 00 0000204 SSR R W SIDR R W SCR R W SMR R W UART 1 00001 00 XXXXXXXX 00000100 00 0 00 000024 SSR R W SIDR R W SCR R W SMR R W UART2 00001 00 XXXXXXXX 00000100 00 0 00 0000284 TMRLR w TMR w Reload Timer 0 00002C TMCSR R W 0000 00000000 000030 TMRLR w TMR w Reload Timer 1 XXXXXXXX XXXXXXXX XXXXXXXX 0000344 TMCSR R W 0000 00000000 000384 ADCR IW ADCS R W A D converter XX XXXXXXXX 00000000 00000000 Serially compared 00003C TMRLR w TMR IW Reload Timer 2 XXXXXXXX 000040 TMCSR R W 0000 00000000 000044 2 Reserved 000048 3 00004C4 E Reserved 000050 371 APPENDIX A I O Maps Table A 1 1 6 Internal resource Address Register 0000544 Reserved 0000584 Table A 2 2 6 Address Register Internal resource 00005 Reserved 0000604 0000644 Reserved 0000684 Reserved 00006 Reserved 000070 0000744 Reserved 0000784 UTIM UTIMR R W UTIMC R W U Timer 0 00000000 00000000 0 00001 0007C UTIM UTIMR R W 00000000 00000000 0 00001 R W U Timer 1 0000804 UTIM UTIMR R W UTIMC R W U Timer 2 0000000
66. 341 external trigger or internal timer to start A D converter USING M 280 external wait cycle timing 172 F FBGA 112 outside dimension 9 FBGA 112 pin 12 first word Of 332 flag and interrupt occurrence 260 flash memory register 352 flash memory status register FSTR 355 flash memory block diagram of 354 flash memory outline 352 flash memory sector configuration of 357 ous mc 2 FR CPU programming mode 16 bits read write 359 FR CPU ROM mode 32 bits read only 359 frequency combination depending on clock doubler function operating 106 instruction 409 G gear control register GCR bit function of 82 gear control register GCR configuration of 82 gear controller block 87 gear function 87 general control register 1 GCN1 bit function of 312 general control register 1 GCN1 configuration 311 general control register 2 GCN2
67. A31 A30 A29 15 14 13 12 2 1 0 A18 A17 A16 15 14 13 12 2 1 0 A18 A17 A16 15 14 13 12 2 1 0 A18 A17 A16 15 14 13 12 2 1 0 A18 A17 A16 15 14 13 12 2 1 0 A18 A17 A16 O Area mask registers AMR1 to AMR5 15 14 13 12 2 1 0 AMRI 6 5 5 ree 18 17 16 15 14 13 12 2 1 0 18 17 16 15 14 13 12 2 1 0 geo y ES A18 A17 A16 15 14 13 12 2 1 0 4 gt _ gt A18 A17 16 15 14 13 12 2 1 0 AMRS reee E a 8 A18 A17 A16 Address 0000061 A31 A30 A29 118 Initial value 00014 Initial value 00024 Initial value 00034 Initial value 00044 Initial value 00054 Initial value 00004 Initial value Initial value 0000 Initial value H Initial value 0000 Access 4 4 Area Select Register ASR and Area Mask Register AMR The area select registers ASR1 to ASR5 and area mask registers AMR1 to AMR5 specify the range of address space for chip select areas 1 to 5 ASR1 to ASR5 specify the upper 16 bits A31 to A16 of each address and AMR1 to 5 mask the corresponding address bits Each bit of AMR1 to AMR5 assumes care by 0 and don t care by 1 When the value set in the ASR is 0 c
68. Figure 4 17 27 Example 3 of DRAM Interface Timing Chart in High Speed Page Mode Q4 Q5 Idle Q4 Q5 Q4 Q5 Q4 Q5 Q4 Q5 EX ES A24 00 j CS5X col adi j CS5X col adr CS5X col adr X 54 col adr CS4X col Read D31 24 D23 16 Read X write Write ji Ready X write Write CS4X CS5X XRead Read RDX CS4 RAS CS4 CASL CS4 CASH CS4 WE CS5 RAS CS5 CASL CS5 CASH CS5 WE Explanation of operation CS5 area gt lt CS4 area Even if the CS area is switched RAS remains at L in high speed page mode When bus cycle starts from a high speed page RDX in a read cycle goes down to L from the rising edge of Q4 and is negated when the Q5 cycle ends In a write cycle it goes down to L from the rising edge of WE including WEL and WEH Q4 and is negated when the Q5 cycle ends CS4X and CS5X change at the same time as the output address When bus cycle starts from a high speed page they change from the Q4 cycle as with the column address 183 CHAPTER 4 BUS INTERFACE O Combination of high speed page mode and basic bus cycle Figure 4 17 28 Example 4 of DRAM Interface Timing Chart in High Speed Page Mode
69. The BW1 and BWO bits can control the same bus width as those of areas 2 and 3 The number of automatic wait cycles can be specified for each area B Configuration of Area Mode Register 32 AMD32 Area mode register 32 AMD32 is configured as follows AMD32 7 6 5 4 3 2 1 0 Initial value Address 0000 0622 BW1 BWO WT32 WT31 WT30 WT22 WT21 WT20 00000000 Bit Functions of Area Mode Register 32 AMD32 bit 7 and 6 BW1 and 0 Bus Width bit BW1 and BWO specify the bus width of area 2 or area 3 Bus width 8 bits 16 bits Setting disabled Reserved bit 5 to 3 WT32 to 30 Wait Cycle bit Access R W WT32 to WT30 specify the number of wait cycles to be inserted automatically when area 3 is accessed via memory The operation of the bits is similar to WTC2 to WTCO of AMDO The bits are reset to 000 and the number of wait cycles to be inserted becomes 0 bit 2 to 0 WT 22 to 20 Wait Cycle bit WT22 to WT20 specify the number of wait cycles to be inserted automatically when area 2 is accessed via memory The operation of the bits is similar to WTC2 to WTCO of AMDO The bits are reset to 000 and the number of wait cycles to be inserted becomes 0 124 4 8 Area Mode Register 4 AMD4 4 8 Area Mode Register 4 AMD4 Area mode register 4 AMD4 specifies the operation mode of chip select area 4 area specified by ASR4 and AMR4A Area 4 allo
70. Watchdog timer One channel O Bit search module Searches for the bit position that first changes between 1 and 0 beginning from MSB of a word in one cycle O Interrupt controller External interrupt input Nonmaskable interrupt normal interrupt x 4 INTO to INT3 Internal interrupt causes UART DMAC A D reload timer PWM UTIMER and delayed interrupt Up to 16 priority levels are programmable for interrupts other than nonmaskable interrupts O Reset types Power on reset watchdog timer reset software reset and external reset O Power save mode Sleep stop mode O Clock control Gear function Desired operating clock frequencies can be set for the CPU and peripherals independently A gear clock can be selected from 1 1 1 2 1 4 and 1 8 or 1 2 1 4 1 8 and 1 16 However the operating clock frequency for peripherals cannot exceed 25 MHz O Others Packages QFP 100 LQFP 100 FBGA 112 e CMOS technology 0 5 um Power supply 3 3 V plus or minus 0 3 V e 254 kilobyte flash ROM Can be read written and erased by a single power supply Available Types MB91V106 MB91106 63 Kbyte 1 1 MB91F109 Characteristics MB91F109 64 Kbyte 64 Kbyte 254 Kbyte 64 Kbyte 2 Kbyte 2 Kbyte 2 Kbyte 2 Kbyte CHAPTER 1 OVERVIEW 1 2 General Block Diagram of MB91F109 Figure 1 2 1 is a general MB91F109 block diagram General Block Diagram of MB91F10
71. in one cycle but does not enable to write to flash memory or to start the automatic algorithm O Mode specification When specifying this mode set the WE bit of the flash memory status register to 0 This mode is always set after a reset occurs at CPU run time This mode can be set only when the CPU is running O Detailed operation In this mode one word 32 bits can be read from the flash memory area in one cycle Depending on the read operation two cycles may be required per word when 1 wait cycle is included thereby making it possible to issue instructions to the FR CPU with no wait O Restrictions Address assignment and endians in this mode differ from those for writing with the ROM writer In this mode commands and data cannot be written to flash memory together B FR CPU Programming Mode 16 Bits Read Write This mode enables data to be written and erased As one word 32 bits cannot be accessed in one cycle program execution in flash memory is disabled in this mode O Mode specification When specifying this mode set the WE bit of the flash memory status register to 1 When a reset occurs at CPU run time the WE bit indicates 0 When setting this mode set the WE bit to 1 If the WE bit is set again to 0 through a writing operation or because of a reset the device enters ROM mode When the RDY bit of the flash memory status register is 0 the WE bit cannot be overwritten When overwriting the WE
72. in temporary erase stop Temporary erase Reverse stop and write to data sectors not in temporary erase stop Time limit Automatic write operation Reverse exceeded data Automatic erase operation 0 Undefined Write operation during 0 Undefined temporary erase stop 1 Bit 2 toggles for consecutive read operations from sectors in temporary erase stop 2 Bit 6 toggles for consecutive read operations from any address 2 During temporary erase stop and write operations bit 2 indicates 1 while reading the address for the write operation However bit 2 toggles for consecutive read operations from sectors in temporary erase stop bit 7 DPOLL Data polling O Automatic write operation status When a read operation is performed during execution of the automatic write algorithm flash memory outputs the inversion of the last written data When read access is performed at the end of the automatic write algorithm flash memory outputs the data of bit 7 of the read data in the address indicated by the address signal O Automatic erase operation status When a read operation is performed during execution of the automatic erase algorithm flash memory outputs 0 irrespective of the address indicated by the address signal Similarly flash memory outputs 1 at the end of the algorithm 365 CHAPTER 16 FLASH MEMORY 366 O Temporary sector erase stop status When a read operation is perf
73. page page page Explanation of operation Column addresses and write data are output in Q4SW cycles CAS is asserted at the falling edge of Q4SW and negated at the rising edge or end of the Q4SW cycle WE including WEL and WEH is asserted at the rising edge of the Q4SW cycle and negated when Q4SW ends 4 17 Bus Timing 4 17 16 Single DRAM Interface This section provides a single DRAM interface timing chart Single DRAM Interface Timing Chart O Combination of single DRAM and basic bus cycle CS switch over Figure 4 17 31 Example of Single DRAM Interface Timing Chart Q4SR_ Idle BA1 BA2 Q1 Q2 Q3 Q4SW Q4SR ldle Q4SR CLK A24 00 Xcol XCS2Xbasicbus X X X row adr Xcol Xcol Xco X D31 24 Read X Write Write X Read Read D23 16 Read X Write X write X Read Read CS2X CS4X CS5X RDX WROX CS4 RAS CS4 CASL CS4 CASH CS4 WE CS5 RAS CS5 CASL CS5 CASH CS5 WE CS5 Single gt lt CS2 usual gt lt CS4 Sine gt CS5 Explanation of operation When a bus cycle starts from a high speed page RDX in a read cycle goes down to L from the rising edge of Q4SR and is negated when the Q4SR cycle ends In a write cycle it goes down to L from
74. r0 r1 0x49 r0 0 622 1 r0 r1 0x88 r0 0 623 1 r0 r1 0x88 r0 0 624 1 r0 r1 0x0c90 r0 0x62c r1 r0 r1 0x10c0 r0 0x62e r1 r0 r1 0x0205 r0 4 19 Program Example for External Bus Operation Write to dscr register 16 bit bus 0 0 register address setting Write to 0 register 16 bit bus 2 wait amd1 register address setting Write to amd1 register Usual 16 bit bus 1 wait amd32 register address setting Write to amd32 register DRAM 16 bit bus amd4 register address setting Write to amd4 register DRAM 16 bit bus amd5 register address setting Write to amd5 register page size 256 Q1 Q4 wait Page 1CAS 2WE CBR without parity dmcr4 register address setting Write to dmcr4 register page size 512 without Q1 Q4 wait Page 2CAS 1WE CBR without parity dmcr5 register address setting Write to dmcr5 register REL 2 without R1W R3W wait refresh 1 8 197 CHAPTER 4 BUS INTERFACE init_asr init_ler init_modr 01 20 sth Idi 32 Idi 32 Idi 32 Idi 32 Idi 32 Idi 20 Idi 20 Idi 20 Idi 20 Idi 20 st st st st st ldi 8 Idi 20 stb Idi 8 Idi 20 stb External bus access adr_set 198 Idi 32 Idi 32 Idi 32 Idi 32 Idi 32 Idi 32 0 626 1 r0 r1 0x0013001 rO 0x0015001 r1 0x0017001 r2 0x0
75. watchdog timer reset ox 219 to 9 x 216 0x 217 to 9 x 278 o x 21 to 270 x 2 to x 222 is twice as large as X0 when GCR CHC is 1 and becomes the PLL oscillation frequency when CHC is 0 85 CHAPTER 3 CLOCK GENERATOR AND CONTROLLER 3 8 PLL Control Register PCTR The PLL control register PCTR is used to control PLL oscillation The setting of this register can be changed only when GCR CHC is 1 Configuration of PLL Control Register PCTR The PLL control register PCTR is used to control PLL oscillation The setting of this register can be changed only when GCR CHC is 1 15 14 13 12 11 10 09 08 Initial value Access 00000488 vse 00 0 B Bit Functions of PLL Control Register PCTR bit 15 14 SLCT1 0 These bits control PLL multiplying ratios The bits are initialized only at power on The internal operating frequency applicable when GCR CHC is set to 0 is written to this register Internal operating frequency at 12 5 MHz oscillation 12 5 MHz operation Initial value 25 0 MHz operation Reserved bit 13 12 Reserved Always write 0 to these bits bit 11 VSTP This bit controls PLL oscillation The bit is initialized only at power on Enable oscillation Initial value Stop oscillation Note When the system shifts to the stop mode PLL oscillation stops regardless of the setting
76. 0 01 gt Issue an interrupt request when the counter generates a borrow POEN 1 gt Enable PWM output OSEL 0 gt Normal polarity 5 Write data to GCN2 to generate a start trigger To start channels 0 and 1 simultaneously under the above settings write 1 to ENO and of GCN2 which generates a rising edge and causes pulses to be output from PWMO and PWM1 321 CHAPTER 14 PWM TIMER Starting Multiple PWM Timer Channels Using the 16 Bit Reload Timer 322 In step 3 of the foregoing setting procedure select the 16 bit reload timer as the start trigger in GCN1 and then start the 16 bit reload timer instead of GCN2 in step 5 The PWM timer can be restarted at regular intervals by setting toggle output for the 16 bit reload timer by setting the following in the control status register RTRG 1 gt Enable restart EGS1 0 11 gt Start at both edges CHAPTER 15 DMAC This chapter provides an overview of the DMAC and explains the register configuration and functions and the operations of the DMAC 15 1 15 2 15 3 15 4 15 5 15 6 15 7 15 8 15 9 Overview of DMAC DMAC Parameter Descriptor Pointer DPDP DMAC Control Status Register DACSR DMAC Pin Control Register DATCR Descriptor Register in RAM DMAC Transfer Modes Output of Transfer Request Acknowledgment and Transfer End signals Notes on DMAC DMAC Timing Charts 323 CHAPTER 15 DMAC 15 1 Overview of DMAC The DMAC is a bui
77. 100P 06 23 90 0 40 941 016 20 00 0 20 787 008 0 LEAD No 1 5 __ 30 0 10 _ 0122 0044 gt 124008 7 0 10 004 18 85 742 22 30 0 40 878 016 1994 FUJITSU LIMITED 100008 3 2 14 00 0 20 17 90 0 40 551 008 705 016 3 35 132 Mounting height 0 05 002 MIN STAND OFF sk 12 35 486 16 30 0 40 AEE 642 016 0 15 0 05 006 002 d 0 10 0 80 0 20 037 008 Unit mm inches CHAPTER 1 OVERVIEW Outside Dimensions LQFP 100 Figure 1 3 2 Outside Dimensions of FPT 100P M05 100 05 EIAJ code QFP100 P 1414 1 Plastic LQFP with 100 pins Lead pitch 0 50 mm Package 14 x 14 mm width x length Lead shape Gull wing Sealing Plastic mold Plastic LQFP with 100 pins 100 05 16 00 0 20 630 008 SQ INDEX 2 LEAD No 2 0 127 75 Ls P 0 08 003 9 B diese qu da 0 10 004 Q 1995 FUJITSU LIMITED 1000075 20 3 0 20 1 50 010 008 Mouting height 059 12 00 15 00 472 591 REF S M t Details of A part
78. Area mode register 5 AMD5 specifies the bus mode of chip select area 5 area specified by ASR5 and AMR5 Area 5 allows the use of the DRAM interface Configuration of Area Mode Register 5 AMD5 Area mode register 5 AMD5 is configured as follows Initial value Access AMD5 Address 0000 06244 DRME BW1 WTC2 WTC1 WTCO 0 00000 R W Bit Functions of Area Mode Register 5 AMD5 126 bit 7 DRME DRaM Enable bit The DRME bit selects the usual bus interface or DRAM interface for area 5 0 Usual bus interface 1 DRAM interface When the DRAM interface is used more details must be specified via the DMCR DRAM control register described later bit 4 and 3 BW1 and 0 Bus Width bit BW1 and BWO specify the bus width of area 5 These bits have functions similar to those of the BW bits of other AMD registers When the DRAM interface is used the bus width specified by these bits is also valid Bus width 8 bits 16 bits Setting disabled Reserved bit 2 to 0 WTC 2 to 0 Wait Cycle bit WTC2 to WTCO specify the number of wait cycles to be automatically inserted when area 5 is accessed via memory These bits have functions similar to those of the WTC bits of other AMD registers By resetting these bits to 000 the number of wait cycles to be automatically inserted becomes o When the DRAM interface is used because wait cycles are controlled by
79. Cycles in Each Mode 166 4 17 4 Write Cycles in Each 0 44 4 3 0000 0 enn sn ertet innen nns senten renis enne 168 4 17 5 Read and Write Combination Cycles 2 ennt 170 4 17 6 Automatic Wait 171 4177 External Watt CyGles etait des 172 4 17 8 Usual DRAM Interface Read 173 4 17 9 Usual DRAM Interface 175 4 17 10 Usual DRAM Read 177 4 17 11 Usual DRAM Write Cycles 2 24 4 100001 0000 179 4 17 12 Automatic Wait Cycles in Usual DRAM Interface 181 4 17 13 DRAM Interface in High Speed Page Mode 2 182 4 17 14 Single DRAM Interface 185 4 17 15 Single DRAM Interface 186 4 17 16 Single DRAM Interface 20 0 4 ii 187 viii 4 17 17 Hyper DRAM Interface Read 22 2 221 10000 ae neneen nennen enne enn 188 4 17 18 Hyper DRAM Interface Write 189 4 17 19 Hyper DRAM Interface 190 4 17 20 DRAM Refresh exortu te Lodel 191 4 17 21 External Bus Request c
80. D Notes on Using Little Endian Areas E Instruction 369 APPENDIX A I O Maps APPENDIX A Maps The addresses listed from Table A 1 to Table A 6 are assigned to the registers of the functions for peripherals that are built in in the MB91F109 How to Read the I O Maps Register Address Internal resource 1 000000 PDR3 R W PDR2 R W Port data register XXXXXXXX XXXXXXXX 2 Read write attribute Initial register value after reset Register name the register listed in the first column is at address 4n the register listed in the second column is at address 4n 1 Leftmost register address the first column register is on the MSB side of data in word access mode lt Note gt The register bit value has one of the following initial values 1 Initial value 1 0 Initial value 0 X Initial value X No register actually exists at this position 370 B Maps Table 1 1 6 Address Register APPENDIX A I O Maps Internal resource 000000 PDR3 R W PDR2 R W Port data register XXXXXXXX XXXXXXXX 0000044 PDR7 R W PDR6 R W PDR5 R W PDR4 R W XXXXXXXX XXXXXXXX XXXXXXXX 000008 PDRB R W PDRA R W PDR8 R W XXXXXXXX XXXXXXXX XXXXXX 00000C 000010 PDRE R W PDRF R W XXXXXXXX XXXXXXXX 0000144 0000184 Reserved
81. DACKO J J 1 1 7 gt K gt K gt gt Outside of page High speed High speed High speed Explanation of operation Column addresses are output in Q4SR cycles CAS is asserted at the falling edge of Q4SR 031 to D16 are fetched at the rising edge of CAS including CASL and CASH as in the case of the usual DRAM interface When a read cycle ends at least one idle clock cycle is inserted so as to prevent conflicts between the external data buses DACKO to DACK2 and EOPO to E002 are output at the same time as CAS 185 CHAPTER 4 BUS INTERFACE 4 17 15 Single DRAM Interface Write This section provides a single DRAM interface write timing chart Single DRAM Interface Write Timing Chart 186 O Bus width 16 bits access words Figure 4 17 30 Example of Single DRAM Interface Write Timing Chart Q1 Q2 Q3 Q4SW Q4SW Q4SW Q4SW Q1 Q2 Q3 Q4SW Ld 2 2CAS 1WE A24 00 X X X row adr Xco Xco Xco X X X row adr Xco X D31 24 X w XW yw XW X w X D23 16 YW YW yw yw yY w x RAS CASL CASH 5 ae HEX RDX DACKO q 1 1 1 EOPO Lf High speed High speed High speed
82. DRAM ndependent control of 2 banks RAS and CAS control signals Capable of selecting 2CAS 1WE and 1CAS 2WE DRAMs Support of high speed page mode Support of CBR or selfrefresh Programmable waveforms Capable of using unused address or data pins as I O ports Support of little endian mode 4 1 Outline of Bus Interface Bus Interface Registers Figure 4 1 1 shows the bus interface registers Figure 4 1 1 Bus Interface Registers 31 24 23 16 15 87 0 ASR1 Area Select Reg 1 1 Area Mode Reg 1 ASR2 Area Select Reg 2 AMR 2 Area Mode Reg 2 ASR3 Area Select Reg 3 AMR 3 Area Mode Reg 3 ASR4 Area Select Reg 4 AMR 4 Area Mode Reg 4 ASR5 Area Select Reg 5 AMR 5 Area Mode Reg 5 AMD 0 AMD 1 AMD 32 AMD 4 AMD 5 DSCR RFCR ReFresh Control Register EPCRO External Pin Control 0 EPCR1 External Pin Control 1 DMCR4 DRAMControl Reg 4 DMCR5 DRAMControl Reg 5 LER MODR For details on the mode register MODR see Section 2 10 Operation Mode 113 CHAPTER 4 BUS INTERFACE Block Diagram of the Bus Interface Figure 4 1 2 shows a block diagram of the bus interface Figure 4 1 2 Bus Interface Block Diagram ADDRESS BUS DATA BUS 32 m e buffer switch a read buffer switch A OUT EXTERNAL DATA BUS MUX DATA BLOCK ADDRESS BLOCK 10 2
83. Data Address Data Address Data Address Data Address Data Address Data XXXXxxxxh Read Reset 000D5556h 000EAAAAh 000D5556h RA Program 000D5556h 000EAAAAh 000D5556h PA Chip Erase 000D5556h 000EAAAAh 000D5556h 000D5556h 5555h 00005556 Sector Erase 000D5556h 000EAAAAh 000D5556h 000D5556h 000EAAAAh 5555h SA Temporarily Stop Sector Erase xxxxxxxxh Start Sector Erase xxxxxxxxh Notes e n FR CPU programming mode always issue the command in half word write mode e RA read address RD read data PA write address PD write data e SA sector address specify one sector address arbitrarily See Table 16 4 1 e The Temporarily Stop Sector Erase or Temporarily Stop Erase command BOH and the Start Sector Erase or Restart Erase command 30H are valid only during a sector erase operation e Both Reset commands can reset flash memory to the read mode O Read Reset command When returning to the read mode after the time limit was exceeded a Read Reset command sequence can be issued Data is read from the flash memory in the next read cycle The flash memory remains in reading state until another command is entered When the power is turned on flash memory is automatically set to the read or reset state In 361 CHAPTER 16 FLASH MEMORY 362 O Program Write In CPU programming mode data is basically written in half
84. E e CPU hold enabled Sleep state i Internal Dd M indication sign l Internal peripheral clock generation Clock stop Clock release request signal request signal Transition to Sleep State Write to STCR bit 7 and 1 to bit 6 to cause transition to the sleep state A sleep request is issued and when the CPU no longer uses the internal bus the clocks are stopped in the following order CPU clock gt internal bus clock Notes Always use the following routine to cause transition to the sleep state using an instruction Before writing to the STCR set the same value in CCK1 CCKO and PCK1 PCKO of the GCR to match the CPU clock and peripheral clock gear ratios The GCR CHC bit can be any value Atleast six consecutive NOP instructions must be provided immediately after writing to the STCR 95 CHAPTER 3 CLOCK GENERATOR AND CONTROLLER Example of setting the maximum gear speed 20 GCR RO LDI 8 0000001 1b R1 CHC 1 CPU peripheral gear ratio STB R1 RO If DBLON 0 LDI 20 4STCR RO LDI 8 01010000b R1 SLEP 1 STB R1 RO NOP NOP NOP NOP NOP 5 Returning from the Sleep State 96 An interrupt or resetting can be used to return from the sleep state Return by way of an interrupt When the enable bit for the interrupt which is one of the peripheral functions is on a peripheral interrupt can be used to
85. Example of Hyper DRAM Interface Read Timing Chart sss 188 Example of Hyper DRAM Interface Write Timing 189 Example of Hyper DRAM Interface Timing Chart 2 190 Example of CAS before RAS CBR Refresh Timing Chart 191 Example of Timing Chart of CBR Refresh Automatic Wait Cycle 192 Example of Selfrefresh Timing Chart ssssssssssssssseseeeneneneee eene 192 Example of Bus Control Release Timing Chart 2 193 Example of Bus Control Acquisition Timing essen eene 193 Example of Timing Chart for 2X Clock BW 16bit Access Word Read 194 Example of Timing for 1X Clock BW 16bit Access Word Read 195 Basic I O Port Block Diagram ssssssssssssesee ener ennemi inneren 202 External Interrupt NMI Controller Registers 004 enne 212 External Interrupt NMI Controller Block Diagram 2 22 2 4 22 212 External Interrupt Operation 216 Clearing the Interrupt Cause Hold Circuit at Level Setting for the Interrupt Request Mode 217 Input of an Interrupt Cause in Interrupt Enable Mode and a Request Issued to the Interrupt Controller E 217 NMI Request Detection
86. External bus Internal register External bus D31 D31 i i D23 D2 148 4 16 Relationship between Data Bus Widths and Control Signals Data Bus Width The following shows the relationship between the internal register and external data bus for each data bus width O 16 bit bus width Figure 4 16 14 Relationship between Internal Register and External Data Bus for 16 bit Bus Width Internal register External bus Lower part of the output address gt 00 1 0 D31 D31 AA Read Write DD BB D23 9 BB CC AA D15 CC D07 DD O 8 bit bus width Figure 4 16 15 Relationship between Internal Register and External Data Bus for 8 bit Bus Width Internal register External bus Lower part of the output address 00 01 1 0 1 1 D31 Read Write D31 o ee on D23 BB D15 CC 007 DD 149 CHAPTER 4 BUS INTERFACE Example of Connection to External Devices O 16 bit bus width Figure 4 16 16 Example of Connection between MB91F109 and External Devices 16 Bit Bus Width MB91F109 CSnX CSmx D31 R D23R em WEM D24X 016 VTE Little endian area 8 bit bus width Figure 4 16 17 Example of Connection between MB91F109 and External Devices 8 Bit Bus Width MB91F109 CSnX CSmX w D31R D23R lo 41 D24X D16X TEER Little endian area DO7
87. F CS EOP output P Same as left F H output Previous status retained 384 P Previous status retained F CS output P Same as left F H output HIZX 1 Output Hi Z Input fixed to 0 Bus release BGRNT Output Hi Z Reset time P Previous status retained F RDY input L output BRQ input H output H output L output H output APPENDIX C Pin Status for Each CPU Status Table C 2 Pin Status for 16 bit External Bus Length and 2CA1WR Mode Continued Pin name Function During sleep P Previous status retained F CLK output During stop HIZX 0 HIZX 1 P F Previous Output Hi Z status retained Input fixed to 0 RASO CSOL CS0H DWOX RAS1 EOP2 CS1L DREQ2 CS1H DACK2 DW1X P Previous status retained F Previous value retained Executed when DRAM pin is set P Previous status retained F Previous value retained During refresh 1 0 3 0 2 5 2 DREQO DREQ1 DACKO DACK1 510 TRGO 500 TRG1 SCO SH TRG2 Previous status retained Input Input possible possible Previous status retained Bus release BGRNT CLK Output Reset time CLK Output P Previous status retained F Previous value retained Operation during DRAM terminal sett
88. INTE instruction cannot be used in an environment where a step trace trap EIT event occurs Figure 2 8 2 shows an example of multiple EIT processing Figure 2 8 2 Example of Multiple EIT Processing Main routine NMI handler INT instruction d Priority handler High NMI occurrence 9 D Executed first Low INT instruction execution Executed next 63 CHAPTER 2 CPU 2 8 8 EIT Operation This section explains EIT operation Suppose the transfer source PC appearing in the following explanation indicates the address of the instruction that detected an EIT event Next instruction address appearing in the following explanation means the address of the instruction that detected EIT as follows LDI 32 PC 6 LDI 20 COPOP COPLD COPST COPSV PC 4 Other instructions PC 2 64 Operation for User Interrupt NMI When a user interrupt or user NMI interrupt request is issued the system checks whether to accept the request as follows O Checking whether to accept an interrupt request 1 The interrupt levels of the requests issued concurrently are compared and the request having the highest level smallest numeric value is selected For maskable interrupts the values held by the corresponding ICRs are used for the compared levels For nonmaskable interrupts the constants defined in advance are used 2 When multiple interrupt requests have the same level the interrupt request havin
89. Low power consumption Sleep mode and stop mode 30 2 2 Internal Architecture 2 2 Internal Architecture The FR CPU uses the Harvard architecture in which the instruction bus and data bus are independent of each other The 32 bits lt gt 16 bits bus converter is connected to the data bus D BUS to implement the interface between the CPU and peripheral resources The Harvard lt gt Princeton bus converter is connected to both I BUS and D BUS to implement the interface between the CPU and bus controller B Internal Architecture Figure 2 2 1 shows the internal architecture O CPU Figure 2 2 1 Internal Architecture FR CPU D BUS l Ta Princeton Bus converter 16bit Bus converter Resources Bus controller The CPU is a compact implement of the 32 bit RISC FR architecture It uses a five stage instruction pipeline system to execute one instruction per cycle pipeline consists of the following five stages Instruction fetch IF Outputs an instruction address and fetches the instruction Instruction decode ID Decodes the fetched instruction and also reads registers Execution EX Executes operation Memory access MA Accesses memory for loading or storing data Write back WB Writes the operation results or loaded memory data to registers Figure 2 2 2 shows the instruction pipeline The 31 CHAPTER 2 CPU 32 Figure 2 2 2 Instruction Pipeline CLK J Instr
90. PC is updated according to instruction execution Bit 0 may be set to 1 only when an odd numbered address is specified for the branch destination address Even at this event bit 0 is invalid and an instruction must be placed at an address consisting of a multiple of two No odd numbered address exception occurs B Data Access When data access is made in the FH series address alignment is performed forcibly in accordance with access width as follows Word access Addresses are aligned in multiples of four the two least significant bits are forcibly set to 00 Half word access Addresses are aligned in multiples of two on least significant bit is forcibly set to 0 Byteaccess As explained above some bits are forcibly set to 0 when a word or half word data access is made but this is applicable only to the calculation result of an effective address For instance in 9 R13 Ri addressing mode the register before addition is used as is for calculation even if the least significant bit is 1 and the least significant bit of the result of addition is masked Thus the register before calculation is not masked Example LD R13 R2 RO R13 00002222H R2 00000003H Result of addition 00002225H 7 Forced masking of two LSBs Address pin 00002224H 43 CHAPTER 2 CPU 2 6 Memory Map This section shows an MB91F109 memory map and a memory map common to the FR series MB91F109
91. PF1 General purpose I O port This function is valid when UARTO data output is disabled 81 5 2 SCO UARTO clock I O Clock output be used when UARTO clock output is enabled OCPA3 PWM timer output This function is valid when PWM timer output is enabled PF2 General purpose I O port This function is valid when UARTO clock output is disabled 82 SH TRG2 PF3 F 511 UART1 data input The input of each pin is used from time to time while input operation is selected Therefore it is needed to stop output by other functions except when such output is performed intentionally TRG2 External trigger input of PWM timer General purpose I O port CHAPTER 1 OVERVIEW Table 1 5 4 Pin Functions 4 5 Pin name SO1 TRG3 PF4 Table 1 5 5 Pin Functions 5 5 Pin name SI2 OCPA1 PF5 circuit format circuit format Function SO1 UART1 data output This function is valid when UART1 data output is enabled TRG3 External trigger input of PWM timer This function is valid when PF4 and UART1 data output is disabled PF4 General purpose I O port This function is valid when UART1 data output is disabled Function 512 UART2 data input This input is used from time to time while UART2 is operating for input Therefore it is needed to stop output by other functions except when such output is performed intentionall
92. R W 7 6 4 3 1 0 R W 2 DO EO R W R W R W R W R W R W R W Initial value 00000000H Bit Functions of DMAC Control Status Register DACSR bit 31 27 23 19 15 11 7 3 DERn DMA ERror Each of these bits indicates that DMA transfer was interrupted because an error occurred in the DMA request source for the corresponding channel n 0 No error 1 An error occurred Error occurrence depnds on the DMA request source resource Errors do not occur in some DMA request sources 327 CHAPTER 15 DMAC 328 These bits are initialized to 0 by resetting These bits can be both read and written but can only be set to 0 A Read Modify Write instruction always reads 1 from each of these bits bit 30 26 22 18 14 10 6 2 DEDn DMA EnD Each of these bits indicates whether DMA transfer in the corresponding channel n is finished 0 DMA transfer has not been finished 1 The counter reached 0 or an error occurred in the transfer request source These bits are initialized to 0 by resetting These bits can be both read and written but can only be set to 0 A Read Modify Write instruction always reads 1 from each of these bits bit 29 25 21 17 13 9 5 1 DIEn DMA Operation Enable Each of these bits specifies whether to cause an interrupt request when DMA transfer is finished in the corresponding channel n when DEDn is 1 0 Do not cause an interrupt request 1 Cause an i
93. RUN Bus hold Interrupt Interrupt processing l Interrupt processing Bus hold CPU X XO XO Geo x A HRQ hoo HACK e PDRR 0000 X0001 X 0002 X 0001 y 0000 237 CHAPTER 8 INTERRUPT CONTROLLER 238 Example of interrupt routines CD Incrementing PDRR 2 Clearing the interrupt cause 3 2 Decrementing 2 above example indicates that priority interrupt is caused during execution of interrupt routine 1 In this case incrementing PDRR at the beginning of each interrupt routine and decrementing it at the exit of each routine can also prevent a hold request from being issued accidentally lt Notes gt Always increment PDRR at the beginning of the interrupt routine to be executed during DMA transfer in CPU hold state and decrement it at the exit of the routine to prevent DMA transfer during execution of the interrupt routine On the other hand incrementing or decrementing PDRR during execution of an ordinary interrupt routine prevents DMA transfer during execution of the interrupt routine and may deteriorate performance Carefully note the relationship between the interrupt levels set in the HRCL and the ICR registers CHAPTER9 U TIMER This chapter provides an overview of the U TIMER and explains the register configuration and functions and the operations of the U TIM
94. Ri Temporary register See Reference 1 label32 gt PC 2 label32 Ri label32 gt PC Ri Temporary register See Reference 2 2 label32 Ri if Z 1 then label32 gt PC Ri Temporary register See Reference 3 2 label32 Ri 1 S Z 0 BC32 label32 Ri 1 s C BNC32 label32 Ri 1 s C 0 BN32 label32 Ri 1 S N 1 BP32 label32 Ri 1 S N 0 BV32 label32 Ri t 6 BNV32 label32 Ri 1 s V 0 BLT32 label32 Ri S N xor N 2 label32 Ri t S V xor N 0 BLE32 label32 Ri 1 S V xor or Z 1 BGT32 label32 Ri S V xor or Z 0 BLS32 label32 Ri 1 S C or 2 BHI32 label32 Ri S C or Z 0 Reference 1 CALL32 1 When label32 PC 2 is from 0x800 to 0x7fe an instruction is created as follows CALL label12 2 When label32 PC 2 is outside of the range in 1 and includes an external reference symbol an instruction is created as follows LDI 32 label32 Ri CALL Reference 2 BRA32 1 When label32 PC 2 is from 0x100 to 0xfe an instruction is created as follows BRA label9 2 When label32 PC 2 is outside of the range in 1 and includes an external reference symbol an instruction is created as follows LDI 32 label32 Ri JMP Reference 3 Bcc32 1 When label32 PC 2 is from 0x100 to 0xfe an instruction is created as follows Bcc label9 420 APPENDIX E Instructions 2 When label32 PC 2 is outside of the range in 1 and i
95. Rs TBR RP USP SSP MDH MDL Notes Zero expansion Zero expansion Zero expansion The assembler calculates and sets values in the 08 and o4 fields of hardware specifications as follows Disp10 4 gt 08 disp9 2 gt 08 disp8 gt 08 Disp10 disp9 and disp8 are signed Udisp6 4 gt 04 Udisp6 is unsigned 413 APPENDIX E Instructions Memory Store Instructions Table E 1 9 Memory Store Instructions Mnemonic Ri Rj Ri G R13 Rj Ri R14 disp1 0 Ri R15 udisp6 Ri R15 Rs R15 PS R15 Operation Ri gt Rj Ri gt R13 Rj Ri gt R14 disp10 Ri gt R15 udisp6 R15 4 Ri gt R15 R15 4 Rs gt R15 R15 4 PS gt R15 Remarks Word Word Word Rs Special register Half word Half word Half word Ri Rj Ri R13 Rj Ri R14 disp9 Ri Rj Ri R13 Rj Ri R14 disp8 Ri gt Rj Ri gt R13 Rj Ri gt R14 disp9 Ri gt Rj Ri gt R13 Rj Ri gt R14 disp8 Byte Byte Byte gt gt gt gt gt gt Special register Rs TBR RP USP SSP MDH MDL Notes The assembler calculates and sets values in the 08 and 04 fields of hardware specifications as follows Disp10 4 gt 08 disp9 2 gt 08 disp8 gt 08 Disp10 disp9 and disp8 are signed Udisp6 4 gt 04 Udisp6 is unsigned Interregister Transfer Instructions Table E 1 10 Interre
96. Setting prohibited External TRGO External TRG1 External TRG2 External TRG3 Reserved bits 3 0 TSEL 03 00 ch0 trigger input select bits Table 14 7 4 Selection of ChO Trigger Input 5 03 00 0 trigger input 1 GCN2 ENO bit Initial value GCN2 bit GCN2 EN2 bit GCN2 ENG bit 16 bit reload timer channel 0 16 bit reload timer channel 1 OcO oj o o Reserved External TRGO External TRG1 External TRG2 External TRG3 Reserved 313 CHAPTER 14 PWM TIMER 14 8 General Control Register 2 GCN2 The general control register 2 GCN2 is used for generating a start trigger by software General Control Register 2 GCN2 The configuration of the general control register 2 GCN2 is shown below GCN 2 bit Address 00000 7 6 5 4 3 2 1 0 11 Tes RW RW RW RW RW RW RW RW lt Attribute 0 0 0 0 0 0 0 0 lt lnitial value When EN bit of this register is selected by the general control register 1 GCN1 the value of this register is transmitted as is to the PWM timer trigger input Multiple PWM timer channels can be activated simultaneously by making software generate the edge selected by the EGS1 and EGSO bits of the control status register Always set bits 7 to 4 of this register to O 314 14 9 PWM Operation 14 9 PWM Operation PWM operation out
97. as 24 00 The 5 to CS5X signals are generated from decoded output addresses and remain unchanged unless those addresses change thereby changing the chip select areas set by the ASR and AMR Note that one of these signals is always asserted DACKO to DACK2 and EOPO to EOP2 are output in the DMA external bus cycles The DMAC register specifies whether to output these signals The output time is the same as for RDX 163 CHAPTER 4 BUS INTERFACE 4 17 2 Basic Write Cycles This section provides a chart of the basic write cycle timing Basic Write Cycle Timing Chart O Bus width 8 bits access words CSO area access CLK A24 00 D31 24 D23 16 RDX WROX WR1X CSOX CS1X CS2X CS3X 54 55 DACKO Figure 4 17 2 Example for Basic Write Cycle Timing BAI BA2 BA2 BA2 BAZ T gt X 3H X X 0 X X 2 X 3 iere DES EE SUE Byte access to Byte access to Byte access to Byte access to address 0 atthe address 1 atthe address 2 atthe address 3 at the lower 2bits lower 2bits lower 2bits lower 2bits Explanation of operation 164 A24 to 00 address 24 to address 00 output the address of the first byte location specified in
98. be created 3 If a register from RO to R7 is specified reglist STMO is created If a register from R8 to R15 is specified in reglist STM1 is created Both STMO and STM1 may be created 4 The assembler converts 10 to u8 by calculating u10 4 then sets a value u8 U10 is signed 417 APPENDIX E Instructions Notes LDMO reglist and LDM1 reglist have a n 1 b 1 execution cycles when the specified num ber of registers is n STMO reglist and STM1 reglist a n 1 execution cycles when the specified number of registers is n 20 Bit Standard Branch Macro Instructions Table E 1 14 20 Bit Standard Branch Macro Instructions CALL20 Mnemonic label20 Ri Operation Remarks Next instruction address gt RP Ri Temporary register See Reference 1 label20 gt PC BRA20 BEQ20 BNE20 BC20 BNC20 BN20 BP20 BV20 BNV20 BLT20 BGE20 BLE20 BGT20 BLS20 BHI20 418 label20 Ri label20 Ri label20 Ri label20 Ri label20 Ri label20 Ri label20 Ri label20 Ri label20 Ri label20 Ri label20 Ri label20 Ri label20 Ri label20 Ri label20 Ri label20 gt PC Ri Temporary register See Reference 2 if Z 1 then label20 gt PC Ri Temporary register See Reference 3 s Z 0 s C s C 0 s N s N 0 s V s V 0 s V xor N s V xor N 0 s V xor N or Z s V xor N or Z 0 s C or Z 1 s C or Z 0 Reference 1 CALL20
99. bit bit 10 of the SCR register to 0 When this bit is set SIDR data is invalidated 0 No parity error is present Initial value 1 A parity error is present bit 6 ORE Over Run Error This bit is an interrupt request flag that is set when an overrun is detected for received data To clear the flag once it is set set the REC bit of the SCR register to 0 When this bit is set SIDR data is invalidated 0 No overrun is present Initial value 1 An overrun is present bit 5 FRE FRaming Error This bit is an interrupt request flag that is set when a framing error is detected for received data To clear the flag once it is set set the REC bit of the SCR register to 0 When this bit is set SIDR data is invalidated 0 No framing error is present Initial value 1 A framing error is present 253 CHAPTER 10 UART 254 bit 4 RDRF Receive Data Register Full This bit is an interrupt request flag indicating that received data is stored in the SIDR register The bit is set when received data is loaded to the SIDR register and cleared automatically when the received data is read from the SIDR register 0 No received data is stored Initial value 1 Received data is stored bit 3 TDRE Transmitter Data Register Empty This bit is an interrupt request flag indicating that transmission data can be written to the SODR register The bit is cleared when transmission data has been written to the SODR register
100. circuit Function format A16 P60 Bits 16 to 23 of external address bus A17 P61 When these pins are not used for the address bus A18 P62 they can be used as general purpose I O ports P60 A19 P63 to P67 A20 P64 A21 P65 A22 P66 A23 P67 Table 1 5 2 Pin Functions 2 5 Pin name circuit Function format 41 A24 P70 EOPO F Bit 24 of external address bus This pin is enabled when DMAC EOP output is enabled EOPO DMAC EOP output 0 P70 When this pin is not used as A24 and EOPO the pin can be used as a general purpose port 42 RDY P80 E External Ready input 0 is input when the bus cycle being executed is not completed When the pin is not used for this purpose it can be used as a general purpose I O port 43 BGRNTX P81 F Output of external bus release acceptance L is output when the external bus has been released When the pin is not used for this purpose it can be used as a general purpose port 44 BRQ P82 E Input of external bus release request 1 is input to request that the external bus be released When the pin is not used for this purpose it can be used as a general purpose I O port 45 RDX P83 F External bus read strobe When the pin is not used for this purpose it can be used as a general purpose I O port 46 WROX P84 F External bus write strobe Individual control signals and data bus byte positions have the following relationships CHAPTER 1 OVE
101. err rd Ep DREQn Be a a a a Adar pin Data pin D gt lt 6 Xp Xau Xe gt RDXD 3 5 te aes 9 2157 WRnX WX XWX XW DACK ea x EOP T lr LALLQ 11AQ Q1 e n LLLLLLLL 2 O Transfer source area external transfer destination area internal RAM CLK JUUUUUUUUVUUUUUUUUUUUUUNU DREQn ae a a a Addr pin Data pin 5 0H 1 2H_ X 1 2L RDXD WRnX DACK E MEN S EOP DLL O Transfer source area internal RAM transfer destination area external CLK JUUUUUVUUUVUUUUUUUUUUUUUUULU DREQn a ea ee Addr pin Data pin RDXD T WRnX DACK St a j p eee 347 CHAPTER 15 DMAC Transfer Stop in Continuous Transfer Mode When Both Addresses are Changed for 16 Bit or 8 Bit Data O Transfer source area external transfer destination area external CLK ea eee Le i mE xo are oe LP E DREQn eT Addr pin Data pin D gt x s XD XH XL XH 2L gt RDXD WRnX DACK 1 0 2 2 2 Transfer source area external transfer destination area internal RAM CLK AVF E EB EE a lea DREQn gS ee SS Addr pin Data pin S 30H 2H 2L RDXD ee Leti cec WRnX DACK a a Ta 2 722 Transfer source area internal RAM transfer destination area external CLK _ 1 Ve
102. for 16 bit Bus Width 144 External Bus Access for 8 bit Bus Width nennen 145 Example of Connection between MB91F109 and External Devices 146 Relationship between Internal Register and External Data Bus for Word Access 147 Relationship between Internal Register and External Data Bus for Half word Access 148 Relationship between Internal Register and External Data Bus for Byte Access 148 Relationship between Internal Register and External Data Bus for 16 bit Bus Width 149 Relationship between Internal Register and External Data Bus for 8 bit Bus Width 149 Example of Connection between MB91F109 and External Devices 16 Bit Bus Width 150 Example of Connection between MB91F109 and External Devices 8 Bit Bus Width 150 Example of Connection between MB91F109 and One 8 bit Output DRAM 8 Bit Data Bus 156 Example of Connection between MB91F109 and Two 8 Bit Output DRAMs 16 Bit Data BUS ie piter M Im 157 Example of Connection between MB91F109 and Two 16 Bit Output DRAMs 16 Bit Data BUs cet ettari tem tet tbc e a tug Peer TEE AES 158 Example of Basic Read Cycle Timing Chart sssssssssssssseeeeeeen enne 162 Example for Basic Write Cycle Timing 2 200444 164 Example 1 of Read Cycle Timing Chart
103. for this operation because the X1 pin is disabled when H is output at STOP At 12 5 MHz an external clock can be used by supplying it to only the pin Figures 1 8 1 and 1 8 2 show examples of using an external clock Figure 1 8 1 Example of Using an External Clock Normal Method X1 MB91F109 Note STOP mode oscillation stop mode cannot be used 26 1 8 Handling of Devices Figure 1 8 2 Example of Using an External Clock Possible at 12 5 MHz or Lower be OPEN X1 MB91F109 Connection of power pins Vcc Vss When two or more Vcc or Vss pins are used the device is designed so that the pins which should be at the same potential are connected to one another inside the device to prevent a malfunction such as a latchup However to minimize unnecessary radiation prevent strobe signal malfunction that might be caused by an increase of the ground level and observe the total output current standard be sure to connect all power pins to the power supply and ground outside In addition consider measures so that impedance is minimized for connection from the power supply to Vcc and Vss of the device It is recommended to insert a ceramic capacitor of about 0 1uF as a bypass capacitor near the device between Vcc and Vss O Crystal oscillation circuit Noise generated near the or X1 pin causes the device to malfunction Design the PC board so that the and X1 pins c
104. frequency Therefore code as follows to enable the clock doubler function Example DOUBLER ON LDI 20 BORL BORH LOOP BTSTH BEQ BANDL GCR RO 0001B RO 0001B RO 0010B RO LOOP 1110B RO Disabling the Clock Doubler Function The clock doubler function is disabled by setting the GCR DBLON bit to 0 The CPU clock gear changes from 1 1 back to the setting in the CCK bit of the GCR register simultaneously Switches to the divide by two clock CHC Enables the clock doubler function DBLON 1 Checks DBLAK Loops until DBLAK becomes 1 Switches to the PLL clock CHC 0 105 CHAPTER 3 CLOCK GENERATOR AND CONTROLLER Example DOUBLER OFF LDI 20 GCR RO BORL 0001B RO Switches to the divide by two clock CHC 1 BANDH 1110B RO Disables the clock doubler function DBLON 0 Code as follows to use the PLL clock after the clock doubler function is disabled Example DOUBLER OFF LDI 20 GCR RO BORL 0001B RO Switches to the divide by two clock CHC 1 BANDH 1110B RO Disables the clock doubler function DBLON 0 LDI 20 PCTR R1 LDI 8 01000000B R2 STB R2 R1 PLL 25 MHz BANDL 1110 RO Switches to the PLL clock CHC 0 Note on Enabling or Disabling the Clock Doubler Function Enabling or disabling the clock doubler function may cause a dead cycle in the internal clock A dead cycle appears as an error if it occurs during time measurement by a
105. from sleep or stopped state To recover from the sleep or stopped state that has been entered from a program in C bus RAM do not use an interrupt but execute resetting 28 CHAPTER2 CPU This chapter provides basic information on the FR series CPU core functions including the architecture specifications and instructions 2 1 CPU Architecture 2 2 Internal Architecture 2 3 Programming Model 2 4 Data Structure 2 5 Word Alignment 2 6 Memory Map 2 7 Instruction Overview 2 8 EIT Exception Interrupt and Trap 2 9 Reset Sequence 2 10 Operation Mode 29 CHAPTER 2 CPU 2 1 CPU Architecture The FR30 CPU is a high performance core that uses the RISC architecture and supports advanced functional instructions geared to embedding applications Characteristics of CPU Architecture O RISC architecture Basicinstruction One instruction per cycle O 32 bit architecture 32 bit general purpose register x 16 O Linear 4 gigabyte memory space O Internal operation of the adder Addition of 32 bits x 32 bits Five cycles Addition of 16 bits x 16 bits Three cycles O Enhanced interrupt processing function High speed response six cycles Support of multiple concurrent interrupts Level mask function 16 levels Enhanced I O operation instructions nter memory transfer instruction Bit processing instruction O High coding efficiency Basic instruction word length 16 bits O
106. gt Internal reset State decoder Reset state State transition control circuit circuit Starting the Watchdog Timer Writing to the watchdog control register WTCR causes the watchdog timer to start operation For this operation set the interval time of the watchdog timer using the WT1 and WTO bits The interval time set first is valid but subsequent settings are ignored Example LDI 8 00000010b R1 WT1 0 10 10 20 WTCR R2 STB R1 R2 Starts the watchdog timer Postponing Resetting Once the watchdog timer starts operation a program must regularly write ABH and to the watchdog reset postpone register WPR The watchdog reset flip flop stores the falling edge of the tap selected by the timebase timer If the flip flop has not been cleared at the second falling edge a reset signal is generated Figure 3 11 2 shows the watchdog timer operation timing 99 CHAPTER 3 CLOCK GENERATOR AND CONTROLLER Figure 3 11 2 Watchdog Timer Operating Timing Timebase timer overflow Watchdog flip flop WTE write Watchdog start Watchdog clear A Watchdog resetting lt Note gt The time interval between the first A54 and the next 5A is not specified Watchdog resetting is postponed only if the time interval from one 5A to the next 5 is within the time specified by the WT bits and one is writt
107. implementing external wait cycles set the RDYE bit of EPCRO to 1 to validate the input of the external RDY pin When using the external RDY signal set at least 1 clock of automatic wait cycle that is set 001 or more in the WTC bit of the AMD The RDY signal is detected after not during automatic wait cycles Enter the RDY signal synchronously with the falling edge of the CLK pin output If the external RDY is L at the falling edge of the CLK a wait cycle is entered and the same BA1 cycle is repeated If the external RDY is H the end of the wait cycle is assumed and the BA2 cycle is entered 172 4 17 Bus Timing 4 17 8 Usual DRAM Interface Read This section provides a usual DRAM interface read timing chart Usual DRAM Interface Read Timing Chart O Bus width 16 bits access words CS4 area access CLK 1 1CAS 2WE A24 00 D31 24 D23 16 RAS CAS WEL WEH RDX CS4X DACKO EOPO 2 2CAS 1WE A24 00 D31 24 D23 16 RAS CASL CASH WE RDX CS4X DACKO Figure 4 17 16 Example of Usual DRAM Interface Read Timing Chart Q1 Q2 04 Q Q2 03 04 05 x X X530 row adr X 0 col adr x X __X 2 row adr X 2 col adr x gt n a r ca 1 1 E 1 i i i 1 1 i i a D
108. is detected The detection result can be obtained by reading the detection result register The relationship between the detected positions and the values to be returned are summarized in Table 13 3 1 If no 1 is found if the value is 00000000 j 32 is returned as the search result Execution example Write data Read value decimal 00100000 00000000 00000000 00000000g 20000000 gt 2 00000001 00100011 01000101 01100111 012345679 gt 7 00000000 00000011 11111111 11111111 OOOSFFFFY gt 14 00000000 00000000 00000000 000000016 00000001 gt 31 00000000 00000000 00000000 000000005 000000003 gt 32 295 CHAPTER 13 BIT SEARCH MODULE Change Point Detection The module scans the data written to the change point detection data register from bit 30 to LSB while comparing each bit with the MSB value and returns the position where the value different from the MSB was first detected The detection result can be obtained by reading the detection result register The relationships between the detected positions and the values to be returned are summarized in Table 13 3 1 If no change point is detected 32 is returned In change point detection mode 0 is not returned as the detection result Execution example Write data 00100000 00000000 00000000 00000000g 20000000 gt 2 Read value decimal 00000001 00100011 01000101 01100111g 01234567 gt 7 00000000 00000011 11111111 11
109. logical operation between general purpose registers or between a general purpose register and memory I O A bit manipulation instruction can directly manipulate the contents of memory or I O These instructions use general register indirect memory addressing Direct addressing The direct addressing instructions are used for access between I O and general purpose registers or between I O and memory Specifying an I O address directly in an instruction not via a register enables high speed and highly efficient access For some instructions register indirect memory addressing with register increment decrement is also available Others Other instructions are available for PS register flag setting stack operation and sign zero extension The FR series also supports function entry exit and register multiload store instructions compliant with high level languages 47 CHAPTER 2 CPU 2 7 1 Branch Instructions with Delay Slots A branch instruction causes the program to branch and execute the instruction at the branch destination after the instruction called the delay slot placed immediately after the branch instruction is executed Branch Instructions with Delay Slots The following instructions execute branch operation with a delay slot JMP D Ri CALL D labell2 0 Ri RET D BRA D label9 BNO D label9 BEQ D label9 BNE D label9 BC D label9 BNC D label9 BN D label9 BP D label9 BV D label9 BNV D label9 BLT D l
110. much or more cycle time than usual for the CPU to access these resources Operation executing unit System clock output from the clock generator to each internal resource connected to the R BUS The system clock at the highest speed shows the same cycle as source oscillation but is divided into 1 1 2 1 4 1 8 or 1 2 1 4 1 8 and 1 16 by PCK1 and of the clock generator GCR register System clock or operation clock for the CPU and resources connected to a bus other than the R BUS The system clock at the highest speed shows the same cycle as source oscillation but is divided into 1 1 2 1 4 and 1 8 or 1 2 1 4 1 8 and 1 16 by CCK1 and CCKO of the clock generator GCR register vi CONTENTS CHAPTER T 2 22 cansasiasssscveccvtes ceto cha enun nux aee a TAn uUa so aeu aa E E rr EE ar CE e Cer eis 1 11 91 109 Characteristics 22 2 4 00 2 1 2 General Block Diagram of 91 109 0022401 0 00000 aa 6 1 97 OUTSIDE DIMENSIONS eiie inrer 7 1 4 Pin Arrangement Diagrams 10 ESSE iod UTI CUOMS Rose 14 1 6 I O Girc it Format c ie 22 1 7 Memory Address Space si
111. of this bit 86 3 9 Gear Function 3 9 Gear Function The gear function supplies clock pulses by slowing down the clock pulse intervals The function uses two independent circuits for the CPU and peripherals Data can be transferred between the CPU and peripherals even when both circuits use different gear ratios The function also permits a source clock to be selected from two choices One is the clock having the same cycle as the clock from PLL and one is the clock that has passed through a divide by two frequency circuit Gear Controller Block Diagram Figure 3 9 1 is a block diagram of the gear controller Figure 3 9 1 Gear Controller Block Diagram RU clock gear interval GCR indication signal Internal bus CPU clock gear interval generation circuit gt CPU clock Internal bus clock Peripheral clock gear interval Y generation circuit Internal DMA clock _3 Oscilla tion circuit 3 o I i w E T c g E gt External bus clock Source clock Selector circuit PLL Internal peripheral clock A Peripheral clock gear interval indication signal Gear Function Setting The desired gear ratio for CPU clock control can be set by setting the CCK1 and CCKO bits of the gear control register GCR to the desired values Similarly the desi
112. on the CAS output which are set by the DSAS and HYPR bits of DMCR4 and DMCR5 Double CAS access DSAS 0 HYPR 0 usual DRAM interface in this manual Single CAS access DSAS 1 HYPR 0 single DRAM interface in this manual DRAM with hyper page mode DSAS 1 HYPR 1 hyper DRAM interface in this manual Set the C W bit of DMCR4 and DMCRB5 to select the 1CAS 2WE DRAM or 2CAS 1WE DRAM The page size specified by the PGS3 to PGSO bits of the DMCR as well as the bus width specified by the BW1 and BWO bits of AMD4 or AMD5 determine row and column addresses 159 CHAPTER 4 BUS INTERFACE 160 O Usual DRAM interface The usual DRAM interface converts the CAS cycle to a 2 clock cycle by setting the DSAS and HYPR bits of DMCR4 and DCMR5 to 0 It handles 5 clock cycles as basic bus cycles during read and write operations This manual represents these cycles as Q1 to Q5 The high speed page mode provides high speed memory access using column addresses and CAS control on the same page pace specified by the same row address When using this mode set 1 in the PAGE bit of DMCR4 and DMCR5 Whether access is within the same page is determined by the PGS3 to PGSO bits of DMCR4 and DMCR5 as well as the bus width Access in the high speed page mode starts when the usual access from the Q1 to Q5 cycle ends When the high speed page mode is entered the Q4 to Q5 cycles are repeated Once the page mode is entered the RAS control signal remai
113. or erase operation where new Write and Erase commands are not accepted When the value of the RDY bit is 1 the flash memory is in read write or erase operation wait state Hardware Sequence Flag 364 For obtaining the hardware sequence flag as data read an arbitrary address an odd address in byte access from flash memory when the automatic algorithm is executed The data contains five validity bits which indicate the status of the automatic algorithm Figure 16 7 1 shows the structure of the hardware sequence flag Reading in units of words is inhibited Figure 16 7 1 Structure of the Hardware Sequence Flag During half word read 15 Undefined 817 Hardware sequence flag 0 During byte read from odd address only 7 Hardware sequence flag 0 bit 7 6 5 4 3 2 1 0 In half word and byte access DPOLL TOGGLE TLOVER SETIMR TOGGL2 The hardware sequence flag becomes invalid in FR CPU ROM mode Always use FR CPU programming mode and write only in half words or bytes 16 7 Execution Status of the Automatic Algorithm Table 16 7 1 lists the possible statuses of the hardware sequence flag Table 16 7 1 Statuses of the Hardware Sequence Flag TOGGLE TLOVER SETIMR TOGGL2 Executing Automatic read operation Reverse data Automatic erase operation 0 Temporary Temporary erase 1 erase stop stop and read mode from sectors in temporary erase stop Temporary erase stop and read from sectors not
114. page mode RAS becomes Normally H CAS is a column address strobe signal CASL of the 2CAS 1WE represents CAS of the upper address side 0 of the lower 1 bit and CASH represents that of the lower address side 1 of the lower 1 bit This signal is asserted at the falling edge of Q4 and negated at the falling edge of Q5 In read cycles WE including WEL and WEH is negated In read cycles RDX stays at L from the Q1 cycle CS4X and CS5X are output from the rising edge of the Q1 cycle DACKO to DACK2 and EOPO to EOP2 are output in external bus cycles Whether to output these signals is determined by DMAC register settings The output time is the same as for CAS 4 17 Bus Timing 4 17 9 Usual DRAM Interface Write This section provides a usual DRAM interface write timing chart Usual DRAM Interface Write Timing Chart O Bus width 16 bits access words CS4 area access CLK 1 1CAS 2WE A24 00 X X30 row adr Y 0 col adr X X3 row adr X 2 col adr X D31 24 X 0 D23 16 X 1 3X 3 X RAS CAS Figure 4 17 17 Example of Usual DRAM Interface Write Timing Chart Q1 Q2 Q3 Q4 Q5 Qi Q2 Q3 Q4 Q5 2 x WEL WEH RDX CS4X DACKO 2 2CASAWE A24 00 X X X350 row adr 0 col aadr X _ 2 row adr X__ 2col adr J D31 24 X 0 X D23 16
115. return from the sleep state The procedure for returning from the stop state to the normal run state is as follows Interrupt generation gt restart of internal bus clock supply gt restart of internal CPU clock supply Program execution after clock supply is as follows When the level of the caused interrupt is enabled by the flag of CPU ILM The program saves the register fetches the interrupt vector and executes processing beginning from the interrupt processing routine When the level of the caused interrupt is disabled by the flag of CPU ILM The program executes instructions beginning from the instruction following the instruction that caused transition to the sleep state Return by way of a reset request The procedure for returning from the stop state to the normal run state is as follows Occurrence of internal reset gt restart of internal bus clock supply gt restart of internal CPU clock supply reset vector fetch gt restart of instruction execution from reset entry address Notes When a peripheral interrupt is used as a DMA transfer request the interrupt cannot be used to return from the sleep state f a peripheral interrupt request has already been issued when the STCR register bits 7 and 6 are written transition to the sleep state does not occur If a DMA request and sleep 3 10 Standby Mode Low Power Consumption Mechanism request occur simultaneously the DMA request is given p
116. s N 1 BP20 D label20 Ri t s N 0 BV20 D label20 Ri s V BNV20 D label20 Ri t s V 0 BLT20 D label20 Ri 1 S V xor N BGE20 D label20 Ri 1 S V xor N 0 BLE20 D label20 Ri 1 S V xor or Z 1 BGT20 D label20 Ri 1 S V xor or Z 0 BLS20 D label20 Ri 1 S CorZ BHI20 D label20 Ri 1 S C or Z 0 Reference 1 CALL20 D 1 When label20 PC 2 is from 0x800 to 0x7fe an instruction is created as follows CALL D label12 2 When label20 PC 2 is outside of the range in 1 and includes an external reference symbol an instruction is created as follows LDI 20 label20 Ri CALL D Ri Reference 2 BRA20 D 1 When label20 PC 2 is from 0x100 to 0xfe an instruction is created as follows BRA D label9 2 When label20 PC 2 is outside of the range in 1 and includes an external reference symbol an instruction is created as follows LDI 20 label20 Ri JMP D Ri Reference 3 Bcc20 D 1 When label20 PC 2 is from 0x100 to 0xfe an instruction is created as follows Bcc D label9 419 APPENDIX E Instructions 2 When label20 PC 2 is outside of the range in 1 and includes an external reference symbol an instruction is created as follows Bxcc false xcc Counter condition of cc LDI 20 label20 Ri JMP D Ri false B 32 Bit Standard Branch Macro Instructions Table E 1 16 32 Bit Standard Branch Macro Instructions Mnemonic Operation Remarks CALL32 label32 Ri Next instruction address gt RP
117. set the bus width For a bus width the value set to mode pins MD2 to MDO is valid before writing to the MODR and the value set to BW1 and BWO of AMDO to AMD5 is valid after writing to the MODR For instance external reset vectors are normally processed in the normal area 0 in which CSOX is active and the bus width for this operation is determined by the MD2 to MDO pins If a bus width of 16 bits is set to MD2 to MDO and the MODR is written without writing to AMDO area 0 shifts to an 8 bit bus mode after writing to the MODR This is because the default bus width of AMDO is 8 bits and consequently causes a malfunction To prevent this problem be sure to set AMDO to AMD5 before writing to the MODR 2 10 Operation Mode MODR writing Bus width specification MD2 1 0 4 BW1 BWO of AMDO to AMD5 71 CHAPTER 2 CPU 72 CHAPTER3 CLOCK GENERATOR AND CONTROLLER This chapter provides detailed information on the generation and control of clock pulses that control the MB91F109 3 1 Outline of Clock Generator and Controller 3 2 Reset Reason Resister RSRR and Watchdog Cycle Control Register WTCR 3 3 Standby Control Register STCR 3 4 DMA Request Suppression Register PDRR 3 5 Timebase Timer Clear Register CTBR 3 6 Gear Control Register GCR 3 7 Watchdog Timer Reset Delay Register WPR 3 8 PLL Control Register PCTR 3 9 Gear Function 3 10 Standby Mode Low Power Consumption Mechanism 3 11 Watchdog fun
118. status retained Output Hi Z Input fixed to 0 Output Hi Z Input fixed to 0 Output retained Address output Output retained Address output P60 to P67 P Previous status retained F Address output P Previous status retained F Address output Previous status retained Previous status retained P Previous status retained F RDY input P F Previous status retained BGRNTX P Previous status retained F H output P F Previous status retained P Previous status retained BRQ input P F Previous status retained Previous status retained Previous status retained Previous status retained Previous status retained Previous status retained H output P Previous status retained F CS output P Same as left F H output P Previous status retained F CS EOP output P Same as left F H output Previous status retained 390 P Previous status retained F CS output P Same as left F H output HIZX 1 Output Hi Z Input fixed to 0 Bus release BGRNT Previous status retained Output Hi Z Reset time P Previous status retained F RDY input L output BRQ input H output Previous status retained L output H output APPENDIX C Pin Status for Each CPU Status Table C 4 Pin Status in 8 bit External Bus Mode Continued Pi
119. that must be set in individual control registers for using CLK synchronous mode are shown below SMR register e MD1 MDO 10 CS Clock input e SCKE 1 for internal timer or 0 for external timer SOE 1 for transmission or 0 for reception only 258 10 8 CLK Synchronous Mode SCR register PEN 0 P SBL A D These bits are invalid CL 1 REC 0 for initialization RXE At least one must be set to 1 SSR register 1 for using interrupts or 0 for using no interrupt e TIE 0 Start of communication Writing to the SODR register starts communication Dummy transmission data must be written to the SODR register even for reception only O End of communication The end of communication can be detected by the fact that the RDRF flag of the SSR register changes to 1 Check the ORE bit of the SSR register to determine whether communication has been successful 259 CHAPTER 10 UART 10 9 UART Interrupt Occurrence and Flag Setting Timing The UART has five flags and two interrupt causes The five flags are PE ORE FRE RDRF and TDRE One of the two interrupt causes is for data reception and the other is for data transmission Interrupt Occurrence and Flags PE indicates a parity error ORE indicates an overrun and FRE indicates a framing error Each flag is set when the corresponding error occurs while data is received and is cleared when 0 is written to REC of the SCR register
120. the DMCR WTC2 to WTCO become invalid 4 10 DRAM Control Register 4 5 DMCR4 5 4 10 DRAM Control Register 4 5 DMCR4 5 DRAM control registers 4 and 5 DMCR4 and DMCR5 control the DRAM interface for areas 4 and 5 and are valid only when the DRME bits of AMD4 and AMD5 are set to 1 B Configuration of DRAM Control Register 4 5 DMCR4 5 DRAM control register 4 5 are configured as follows 15 14 13 12 11 10 9 8 DMCR4 initial value access Address 0000 062CH PGS3 PGS2 PGS1 PGS0 Q1W Q4W DSAS HYPR 00000000 R W 7 6 5 4 3 2 1 0 initial value access PAGE C W SLFR REFE PAR PERR PEIE 0000000 R W DMCR5 19 Te 11 10 9 8 initial value access Address 0000 062 PGS3 PGS2 PGS1 PGSO Q1W Q4W DSAS HYPR 00000000 R W 7 6 5 4 3 2 1 0 initial value access PAGE C W SLFR REFE PAR PERR PEIE 0000000 R W Bit Functions of DRAM Control Register 4 5 DMCR4 5 bit 15 to 12 PGS 3 to 0 PaGe size Select bit PGS3 to PGSO specify the page size of the DRAM to be connected see Table 4 10 1 Table 4 10 1 Page Size of DRAM Connected PGS3 0 Page size ROW Address Column Determine whether access address is within page A31 to 16 A15 to 00 8 bit bus 16 bit bus 256 A31 to 16 A23 to 08 A31 to 00 A31 to 08 A31 to 09 512 A31 to 16 A24 to 09 A31 to 00 A31 to 09 A31 to 10 1024 A31 to 16 A25 to 10 A31 to 00 A31 to 10 A31 to 11 4096 A
121. the cycle of PLL oscillation frequency when CHC is 0 bit 01 00 Reserved These bits are reserved The value read from this bit is undefined 79 CHAPTER 3 CLOCK GENERATOR AND CONTROLLER 3 4 DMA Request Suppression Register PDRR The DMA request suppression register PDRR is used to temporarily suppress DMA requests to lighten the load to the CPU Configuration of the DMA Request Suppression Register PDRR The configuration of the DMA request suppression register PDRR is shown below 15 14 13 12 11 10 09 08 Initial value Access ee or oo mw Bit Functions of the DMA Request Suppression Register PDRR bit 11 to bit 08 D3 to DO Writing a value other than 0 to this register suppresses any subsequent DMA transfer requests to the CPU Thereafter DMA transfer is disabled unless the register is set to 0 80 3 5 Timebase Timer Clear Register CTBR 3 5 Timebase Timer Clear Register CTBR The timebase timer clear register CTBR clears the timebase timer to 0 for initialization Configuration of the Timebase Timer Clear Register CTBR The configuration of the timebase timer clear register CTBR is shown below 07 06 05 04 03 02 01 00 Initial value Access Bit Functions of the Timebase Timer Clear Register CTBR bit 07 to bit 00 When 5 and 5 are written successively to this register the timebase timer is cleared to 0 immediately after i
122. timer or UART transfer Operating Frequency Combinations Depending on whether the Clock Doubler Function is Enabled or Disabled Table 3 14 1 lists the operating frequencies of this device that are applicable depending on the combination of settings in the GCR register and the SLCT1 and SLCTO bits of the PCTR 106 3 14 Clock Doubler Function register Table 3 14 1 shows an example for the case that a 12 5 MHz oscillation is used Table 3 14 1 Operating Frequency Combinations Depending on whether the Clock Doubler Function is Enabled or Disabled PLL Clock Internal External Remarks oscillation doubler Operating bus frequency frequency frequency MHz MHz MHz Divide by two Initial value Inhibited 1 Fixed to 1 1 regardless of settings 2 To disable the clock doubler function switch the clock to the divide by two clock in advance 3 When the PLL oscillation frequency is changed the clock must be switched to the divide by two clock 107 CHAPTER 3 CLOCK GENERATOR AND CONTROLLER 3 15 Example of PLL Clock Setting This section provides an example of PLL clock setting and an example of the assembler source Example of PLL Clock Setting An example of the procedure for switching to 25 MHz operation using PLL in the case of 12 5 MHz oscillation is shown below Figure 3 15 1 Example of PLL Clock Setting No CH
123. to 0005FFFF becomes area 0 Figure 4 2 1 a shows an example of area 1 to area 5 located in units of 64 kilobytes from 00100000 to 0014 Figure 4 2 1 b shows an example of area 1 located in 512 kilobytes from 00000000 to 0007FFFF and area 2 to area 5 located 1 megabyte units from 00100000 to OO4FFFFFy Figure 4 2 1 Example of Setting Chip Select Areas 00000000 CS1X 512K 00080000 CSOX 512K CSOX 1Mbyte OOOFFFFFH CS2X 1Mbyte 001FFFFFH CS1X 64kbyte CS3X 1 Mbyte CS2X 64kbyte 002FFFFFH CS3X 64kbyte CS4X 1 Mbyte CS4xX 64kbyte O03FFFFFH CS5X 64kbyte CS5X 1Mbyte OO4FFFFFH CSOX CSOX 115 CHAPTER 4 BUS INTERFACE 4 3 Bus Interface The bus interface include the following Usual bus interface e DRAM interface These interfaces can only be used in the predetermined area Chip Select Areas and Bus Interfaces Table 4 3 1 shows the correspondence between each chip select area and available interface functions The area mode register AMD specifies which interface to use When not specified the usual bus interface is selected Table 4 3 1 Correspondence between Chip Select Areas and Selectable Bus Interfaces Selectable bus interface Remarks Usual bus Time DRAM sharing Reset time O DRAM interface Two channels of DRAM interface are prepared and use areas 4 and 5 116 3 types of D
124. value 1 Enables high speed page mode enables high speed access to intrapage specified by PGSS to PGSO bit 6 C W 1CAS 2WE 2CAS 1WE Select bit The C W bit selects the 1CAS 2WE or 2CAS 1WE type memory interface when a 16 bit or greater bus width is used 0 1CAS 2WE interface initial value 1 2CAS AWE interface bit 5 SLFR SeLF Refresh bit When the SLFR bit is set to 1 the DRAM enters the selfrefresh mode The selfrefresh mode is enabled when the SLFR bit of DMCR4 or DMCR5 is set to 1 regardless of areas 4 and 5 0 Disables selfrefresh mode initial value 1 Enables selfrefresh mode 128 4 10 DRAM Control Register 4 5 DMCR4 5 bit 4 REFE REFresh Enable bit The REFE bit specifies whether to perform the cyclic refresh operation of the CAS before RAS CBR type When starting the cyclic refresh regardless of areas 4 and 5 set the REFE bit of DMCR4 or DMCR5 to 1 and set the STR bit of the refresh control register RFCF 0 Does not perform a cyclic refresh initial value 1 Performs cyclic refresh with an interval specified by the refresh control register RFCR bit 3 PAR PARity select bit This device supports no parity function Setting this bit has no effect bit 2 PERR Parity ERRor bit This device supports no parity function Setting this bit has no effect bit 1 PEIE Parity Error Interrupt Enable bit The PEIE bit specifies whether to output an interrupt request for a parity er
125. value as that in the cycle setting register to be written to the duty cycle setting register 14 13 Starting Multiple PWM Timer Channels 14 13 Starting Multiple PWM Timer Channels General control registers 1 and 2 GCN1 2 be used to start multiple PWM timer channels Selecting a start trigger with the GCN1 register enables simultaneous start of multiple channels This section provides an example of starting multiple channels using software based on the GCN2 register and another using the 16 bit reload timer Starting Multiple PWM Timer Channels Via Software Proceed as follows 1 Set the cycle in PCSR 2 Set the duty cycle in PDUT Write to PCSR and then PDUT 3 Set the source of trigger input for the channels to be started in GCN1 Leave the in the initial state because GCN2 is used in this example gt ENO ch1 gt ch2 gt EN2 ch3 gt EN3 4 Set the control status register for the channels to be started as follows CNTE 1 gt Enable timer operation STGR 0 gt Leave this bit as is because GCN2 is used to issue a start trigger MDSE 0 gt PWM operation RTRG 0 gt Disable restart CSK1 0 00 gt Count clock PGMS 0 gt Do not mask output Bit 8 gt 0 Unused bit Any value can be set EGS1 0 01 gt Start at a rising edge IREN 1 gt Enable interrupt requests IRQF 0 gt Clear the interrupt cause IRS1
126. x D23 16 HD oe X x at NE 07 a RAS EN CAS E WEL WEH RDX Explanation of operation Read control is performed with only the CAS control signals including CASL and CASH while RAS is lowered to L and H of WE including WEL and WEH is held Column addresses are output in Q4 and Q5 cycles O Write cycle bus width 16 bits access words Figure 4 17 26 Example 2 of DRAM Interface Timing Chart in High Speed Page Mode Qi Q2 Q3 Q4 Q5 Q4 Q5 Q4 Q5 Q4 Q5 2 2CAS 1WE i i A24 00 X __ X 0 coLadr X 2 col adr X 4 coLladr X 6 X 031 24 X 0 X 2 X 4 X 6 x 023 16 X 1 X 3 X 5 X 7 X RS i ES L CASL E E CASH 7 WE L ES RDX Usual DRAM bus cycle High speed page High speed page High speed page 182 Explanation of operation 4 17 Bus Timing Write control is performed with only the CAS control signals including CASL and CASH while RAS is lowered to L and then WE including WEL and WEH is lowered to Column addresses and output data are output in Q4 and Q5 cycles O CS area CS4 CS5 switch over in high speed page mode read and write combination 2CAS 1WE
127. 0 00000000 0 00001 0000844 Reserved 000088 00008C Reserved 000090 000094 EIRR R W 00000000 ENIR R W 00000000 0000984 372 ELVR R W 00000000 External interrupt NMI Table 2 2 6 Address Register APPENDIX A I O Maps Internal resource 00009C Reserved 0000A0 0000 4 0000A8 0000AC 0000B0 0000 4 0000B8 Table A 3 3 6 Address Register Internal resource 0000BCy Reserved 0000C0j 0000C4 0000C8 0000CC 000000 DDRE W 00000000 DDRF 00000000 W Data direction register 0000D44 000008 Reserved 373 APPENDIX A I O Maps Table A 3 3 6 Address 0000DC Register GCN1 R W 00110010 00010000 GCN2 R W 00000000 0000E0 PTMR 11111111 11111111 PCSR W XXXXXXXX XXXXXXXX 0000E4 PDUT IW XXXXXXXX PCNH R W 0000000 PCNL R W 00000000 0000E84 PTMR R 11111111 11111111 PCSR W XXXXXXXX XXXXXXXX 0000EC PDUT IW XXXXXXXX XXXXXXXX PCNH R W 0000000 PCNL R W 00000000 0000F0 PTMR 11111111 11111111 PCSR W XXXXXXXX XXXXXXXX 000F4 PDUT IW XXXXXXXX XXXXXXXX PCNH R W 0000000 PCNL R W
128. 0 9 8 Address 00000 RW RW RW RW RW RW RW RW amp Attribute 0 0 1 1 0 0 1 0 lt Initial value bit 7 6 5 4 3 2 1 0 RW RW RW RW RW RW RW RW lt Attribute 0 0 0 1 0 0 0 0 lt lnitial value 311 CHAPTER 14 PWM TIMER B Bit Functions of General Control Register 1 GCN1 bits 15 12 TSEL 33 30 ch3 trigger input select bits Table 14 7 1 Selection of Ch3 Trigger Input TSEL33 30 ch3 trigger input GCN2 ENO bit GCN2 EN1 bit GCN2 EN2 bit Initial value GCN2 bit 16 bit reload timer channel 0 16 bit reload timer channel 1 Reserved External TRGO External TRG1 External TRG2 External TRG3 Reserved bits 11 8 TSEL 23 20 ch2 trigger input select bits Table 14 7 2 Selection of Ch2 Trigger Input TSEL23 20 10 ch2 trigger input GCN2 ENO bit GCN2 EN1 bit Initial value GCN2 EN2 bit GCN2 bit 16 bit reload timer channel 0 16 bit reload timer channel 1 Reserved External TRGO External TRG1 External TRG2 External TRG3 312 Reserved 14 7 General Control Register 1 GCN1 bits 7 4 TSEL 13 10 ch1 trigger input select bits Table 14 7 3 Selection of Ch1 Trigger Input TSEL13 10 ch1 trigger input GCN2 ENO bit GCN2 EN1 bit Initial value GCN2 EN2 bit GCN2 ENG bit 16 bit reload timer channel 0 16 bit reload timer channel 1
129. 0 P52 9 51 8 50 07 47 06 46 A05 P45 1 4 Pin Arrangement Diagrams Pin Arrangements LQFP 100 DREQ2 PB5 CS1L DACK2 PB6 CS1H PB7 DW1X VCC PA6 CLK PA5 CS5X PA4 CS4X EOP1 PA3 CS3X PA2 CS2X PA1 CS1X 0 50 NMIX P80 RDY P81 BGRNTX P82 BRQ P83 RDX P84 WROX P85 WR1X P20 D16 Figure 1 4 2 LQFP 100 Pin Arrangements N N TA c 0 c 5 an o O O t ioco GO Sr OD Orr o QO LL L1 OOFLOFE or qorconroanoSgqxtFq t aana LL Lu LI LLL e e oL ALALU 25 552 8 2 925455886 or LL M gt gt 0000000 0 N Lo e Ro e no 889599388 58 69 c9 05 66 09 60 GJ GO Fo Fo Fo MB91F109 VIEW 100 05 85 5588580 9939 92 9898 UO ET EET EE ETE EE EE ET LT QI CO xt LO 0 QI CO xt LO CO OOOcg ooooocooooo gt gt 5555 lt lt lt BPRPHEBRPPPERRE Pe Saeaded AN3 AN2 AN1 ANO AVSS AVRL AVRH 24 70 A23 P67 A22 P66 VSS A21 P65 A20 P64 A19 P63 A18 P62 A17 P61 A16 P60 A15 P57 A14 P56 A13 P55 12 54 A11 P53 A10 P52 A09 P51 A08 P50 CHAPTER 1 OVERVIEW Pin Arrangements FBGA 112 Figure 1 4 3 FBGA 112 Pin Arrangements
130. 00000 Table 6 I O Address DDRA W 0000000 DDR8 W 000000 Register ASR1 00000000 00060C IW 00000001 AMR1 00000000 W 00000000 ASR2 00000000 0006104 IW 00000010 AMR2 00000000 W 00000000 ASR3 00000000 0006144 IW 0000001 1 AMR3 00000000 W 00000000 ASR4 00000000 0006184 IW 00000100 AMR4 00000000 W 00000000 ASR5 00000000 00061C IW 00000101 AMR5 00000000 W 00000000 0006204 AMDO R W XX111 AMD1 R W 0 00000 AMD32 R W 00000000 0 00000 AMD4 R W 0006244 AMD5 R W 0 00000 DSCR W 00000000 RFCR R W 00 000 0006284 1100 EPCRO 1111111 IW EPCRO W 11111111 00062C DMCR4 00000000 0000000 R W DMCR5 R W 00000000 0000000 Internal source External bus interface 000630 to 0007BC Reserved 0007C0 FSTR 000XXXX0 R W Flash memory 0007C4 to 0007F8 Reserved 0007 LER W MODR W XXXXXXXX Little endian register mode register 377 APPENDIX A I O Maps lt Note gt Do not execute RMW instructions for registers for which a write only bit is set RMW instructions RMW Read Modify Write AND Rj Ri OR Rij EOR Rj ANDH Rj Ri ORH Rj EORH ANDB Rj OR
131. 00000000 0000F8 PTMR R 11111111 11111111 PCSR W 0000FC PDUT IW XXXXXXXX PCNH R W 0000000 PCNL R W 00000000 Internal resource 000100 to 0001FCj Reserved 0002004 R W 0000000 0002044 R W 00000000 00000000 00000000 00000000 R W XX0000 XX0000 XX0000 00020C 000208 000210 to 0002504 Reserved 374 APPENDIX A I O Maps Table A 4 4 6 Address Register Internal resource 0002544 Reserved 000258 00025C 000260 000264 000268 00026C 0002704 000274 000278 to 0002 000300 Reserved 0003 4 Reserved 0003E84 Reserved 0003EC 0003F0y BSDO IW Bit search module XXXXXXXX 0003F4 BSD1 R W XXXXXXXX 0003F8 BSDC WI XXXXXXXX 0003FC BSRR R 375 APPENDIX A I O Maps Table A 5 5 6 Address Register Internal resource 000400 ICROO R W ICRO1 R W ICRO2 R W ICRO3 R W Interrupt controller 11111 11111 11111
132. 0000042 0000042 0000042 00000420 0000042 0000042 Address 00000431 4 Figure 8 1 2 Interrupt Controller Registers 2 2 bit7 6 5 4 3 2 1 0 ICR4 ICR3 ICR2 ICR1 ICRO R RW RW RW RW LVL4 LVL3 LVL2 LVL1 LVLO R RW RW RW RW ICR32 ICR33 ICR34 ICR35 ICR36 ICR37 ICR38 ICR39 ICR40 ICR41 ICR42 ICR43 ICR44 ICR45 ICR46 ICR47 HRCL 8 2 Interrupt Controller Block Diagram 8 2 Interrupt Controller Block Diagram Figure 8 2 1 is an interrupt controller block diagram Interrupt Controller Block Diagram Figure 8 2 1 Block Diagram of the Interrupt Controller INTO Priority check NMI processing LEVEL4 to 0 4 LEVEL check Oc request ICROO us RIOO gt 6 g 5 VECTOR check So VCT5 to 0 1 gt ICR47 R147 1 DLYIRQ R BUS 1 DLYI is the delayed interrupt module See Chapter 7 Delayed Interrupt Module for more information 2 INTO is a wakeup signal for the clock controller in sleep or stop state 3 HLDCAN is a bus yield request signal to a bus master other than t
133. 0000401 TBR 3B8y 00000402 TBR 3B4y 0000042D TBR4308 0000042E TBR 304 0000042F TBR 300 See Chapter 8 Interrupt Controller for more information 56 2 8 EIT Exception Interrupt and Trap 2 8 3 System Stack Pointer SSP The system stack pointer SSP indicates the stack used to save data for EIT processing or restore data for returning from EIT System Stack Pointer SSP The configuration of the system stack pointer SSP register is shown below bit31 gt gt 0 Initial value SSP 00000000 Value 8 is subtracted from the stack pointer during EIT processing and 8 is added to it during returning from EIT The initial value after resetting is 00000000 The SSP also functions as general purpose register R15 when the S flag of the CCR is 0 57 CHAPTER 2 CPU 2 8 44 Interrupt Stack The interrupt stack is the area indicated by the system stack pointer SSP The PC or PS value is saved to it or restored from it After an interrupt is caused the PC value is stored at the address indicated by the SSP and the PS value is stored at the address SSP 4 Interrupt Stack Figure 2 8 1 shows an example of the interrupt stack Figure 2 8 1 Example of Interrupt Stack Before interrupt After interrupt SSP 80000000 SSP 7FFFFFF8u Memory Memory 800000004
134. 019001 r3 0x001b001 r4 0 60 5 0x610 r6 0x614 r7 0x618 8 0x61C r9 r0 r5 r1 r6 r2 r7 r3 r8 r4 r9 0x02 r0 0x7fe r1 r0 r1 0x80 r0 0x7ff r1 r0 r1 0x00136da0 r0 0x00151300 r1 0x001 96434 2 0x0019657c r3 0x001 96600 4 0x001a6818 r5 II register address setting write to rfcr register and amr1 register setting values asr2 amr2 register setting values asr3 amr3 register setting values asr4 amr4 register setting values asr5 amr5 register setting values asri and amr1 register address setting asr2 amr2 register address setting asr3 amr3 register address setting asr4 amr4 register address setting asr5 amr5 register address setting Write to asr1 and amr1 registers Write to asr2 and amr2 registers Write to asr3 and amr3 registers Write to asr4 and amr4 registers Write to asr5 and amr5 registers CS2 little endian ler register address setting Write to ler register External ROM external bus modr register address setting Write to modr register CS1 address CS2 address CS4 address within the page CS4 address within the page CS4 address outside of the page CS5 address within the page bus acc 01 32 01 32 Id Iduh Idub st sth st stb 4 19 Program Example for External Bus Operation 0x001a6b8c 6 0x001a6c00
135. 1 A0 11 00 01 d PA1 PAO 11 1 Output A1 A0 11 00 01 10 145 CHAPTER 4 BUS INTERFACE Example of Connection to External Devices Figure 4 16 10 Example of Connection between MB91F109 and External Devices MB91F109 D31R D23R o 1 D24X D16X D15 008007 DOO DO7 DOO 16 bit device 8 bit device 0 1 is the lower 1 bit of the address the lower 1 bit of the address in X can be set to 0 or 1 For the 16 8 bit device the data bus on the MSB side of the MB91F109 is used 146 4 16 Relationship between Data Bus Widths and Control Signals 4 16 2 Bus Access with Little Endians When external bus access is performed for areas set by the little endian register LER those areas are handled as little endians Outline of Little Endians Little endian bus access by the MB91F 109 uses the bus access operation for big endians The address output sequence and control signal output for big endians are basically the same as those for little endians which are implemented by swapping data bus byte locations according to the bus width When the devices are connected exercise extreme caution as the big and little endian areas must be physically separated Data Format The address output sequence is the same for both big and little endians Word access The MSB side byte data which corresponds to address 00 of big endian
136. 11 A D CONVERTER Successive approximation type 11 1 Overview of A D Converter Successive Approximation Type The A D converter converts analog input voltage to digital values Characteristics of A D Converter Minimum conversion time 5 6 us ch for 25 MHz system clock Built in sample amp hold circuit e 10 bit resolution Program selection of analog input from four channels Single conversion mode One channel is selected and converted Scan conversion mode Multiple consecutive channels are converted Up to four channels can be programmed Continuous conversion mode The specified channel is converted repeatedly Convert and stop mode When one channel is converted the converter stops and waits for the next activation the beginning of conversion can be synchronized DMA transfer activated by an interrupt Choices of software external trigger falling edge and reload timer rising edge for activation A D Converter Registers Figure 11 1 1 shows the A D converter registers Figure 11 1 1 A D Converter Registers 15 0 lt 16bit gt bit 15 14 13 12 11 10 9 8 BUSY INT INTE PAUSI STS1 STSO STRT Control status register bit 7 6 5 4 3 2 1 0 ene MD1 MDO 52 ANS1 ANSO 2 1 ANEO bit 15 14 13 12 11 10 9 8 bit 7 6 5 4 3 2 1 0 268 11 1 Overview of A D Converter Successive Approximation
137. 11111 0004044 ICRO4 R W ICRO5 R W ICRO6 R W ICRO7 R W 11111 11111 11111 11111 0004084 ICRO8 R W 1 9 R W ICR10 R W ICR11 R W 11111 11111 11111 11111 00040C 12 R W ICR13 R W ICR14 R W ICR13 R W 11111 11111 11111 11111 000410 16 R W 17 R W ICR18 R W 19 R W 11111 11111 11111 11111 0004144 ICR20 R W ICR21 R W ICR22 R W ICR23 R W 11111 11111 11111 11111 0004184 ICR24 R W ICR25 R W ICR26 R W ICR27 R W 11111 11111 11111 11111 00041Ch ICR28 R W ICR29 R W ICR30 R W ICR31 R W 11111 11111 11111 11111 000420 000424 000428 00042C 47 R W 11111 0004304 DICR R W HRCL R W Delay interrupt 0 11111 0004344 Reserved to 00047C 000480 RSRR WTCR STCR R W RW CTBR W Clock control block R W 000111 0000 XXXXXXXX 1XXXX 00 0004844 GCR R W WPR W 110011 1 XXXXXXXX 0004804 PTCR R W For PLL control 00 0 00048C Reserved to 0005FC 376 Table A 5 5 6 Address Register APPENDIX A I O Maps Internal resource 000600 DDR3 W 00000000 DDR2 W 00000000 Data direction register 000604 DDR7 W DDR6 W 00000000 DDR5 W 00000000 DDR4 W 00000000 0006084 DDRB W 000
138. 111111g 0003FFFF gt 14 00000000 00000000 00000000 00000001 000000014 gt 31 00000000 00000000 00000000 000000006 000000004 gt 32 11111111 11111111 11110000 00000000g FFFFF0004 gt 20 11111000 01001001 11100000 10101010g FBA9EOAA gt 5 10000000 00000010 10101010 10101010g 8002AAAA gt 1 11111111 11111111 11111111 111111116 FFFFFFFFY gt 32 Table 13 3 1 Bit Positions and Returned Values Decimal Detected bit position Returned value Detected bit position Returned value Detected bit position Returned value Detected bit position 7 Returned value 6 5 4 3 2 1 0 296 Not detected 13 3 Bit Search Module Operation and Save Restore Processing Save Restore Processing When the internal status of the bit search module must be saved and restored such as when the module is used in the interrupt handler proceed as follows 1 Read the 1 detection data register and store the read data Save 2 Use the bit search module 3 Write the data saved in step 1 to the 1 detection data register Restore As a result of the above operation the value obtained by reading the next detection result register corresponds to the data written to the bit search module before step 1 Even if the last register to which data was written is a O detection or point change detection register the data can be restored by pro
139. 1F109 Chapter 4 Bus Interface Chapter 4 explains the basic items of the external bus interface register configuration and functions bus operations bus timing and provides bus operation program samples Chapter 5 I O Ports Chapter 5 provides an overview of I O ports explains the I O port register configuration and the conditions for using external terminals as I O ports Chapter 6 External Interrupt NMI Controller Chapter 6 provides an overview of the external interrupt NMI controller explains the register configuration and functions and operations of the external interrupt NMI controller Chapter 7 Delayed Interrupt Module Chapter 7 provides an overview of the delayed interrupt module explains the register configuration and functions and operations of the delayed interrupt module Chapter 8 Interrupt Controller Chapter 8 provides an overview of the interrupt controller explains the register configuration and functions and operations of the interrupt controller The chapter also explains the hold request cancel request function using examples Chapter 9 U TIMER Chapter 9 provides an overview of the U TIMER explains the register configuration and functions and operations of the U TIMER Chapter 10 UART Chapter 10 provides an overview of the UART explains the register configuration and functions and operations of the UART Chapter 11 A D Converter Successive Approximation Type Chapter 11 provides an overvi
140. 233 interrupt 353 interrupt control register ICR mapping 56 interrupt control register ICR bit function of 56 228 interrupt control register ICR Configuration 56 228 interrupt 4 interrupt controller block diagram 227 interrupt controller hardware configuration 224 interrupt controller 225 interrupt controller major function 224 interrupt flag set timing for data reception in Mode Onnar ana e t a re 260 INDEX interrupt flag set timing for data reception in mode rn 261 interrupt flag set timing for data reception in mode 2 5 e oet eee tides 261 interrupt flag set timing for data tranmission in mode OF TOR A inni ite ettet 262 interrupt level 54 interrupt level mask register ILM 41 55 interrupt number saai 222 interrupt occurrence and flag 260 interrupt 58 interrupt vector i 379 interrupt with higher priority suppression DMA transter TOM ate c 339 interrupt return by way 93 96 interrupt NML iie ete beet nien d 50 interrupt NMI
141. 31 to 16 A27 to 12 A31 to 00 A31 to 12 A31 to 13 reserved The bus interface unit determines the row size page size by the values of PGS3 to PGSO as well as the specified bus width If an intrapage access occurs when the register allows a page access mode a high speed page access is executed 127 CHAPTER 4 BUS INTERFACE bit 11 QIW Q1 wait bit The Q1W bit specifies whether to extend the Q1cycle the interval of RAS specified at DRAM access time by one cycle 0 Does not extend Q1 cycle initial value 1 Extends Q1 cycle bit 10 Q4W Q4 wait bit The Q4W bit specifies whether to extend the Q4 cycle the L interval of CAS specified at DRAM access time by one cycle This bit is valid only when the DSAS bit bit 9 is 0 0 Does not extend Q4 cycle initial value 1 Extends Q4 cycle bit 9 DSAS Double Single cas Access cycle Select bit The DSAS bit selects one cycle single CAS access or two cycles double CAS access for CAS access when a high speed DRAM access mode is used 0 Double CAS access initial value 1 Single CAS access bit 8 HYPR HYPeR page mode enable The HYPR bit is set to connect a DRAM with a hyper page mode to the outside 0 Double single CAS DRAM initial value 1 DRAM with hyper page mode bit 7 PAGE PAGe Enable bit The PAGE bit specifies whether to enable the high speed page mode 0 Disables high speed page mode random access operation by initial
142. 4 16 2 Functions and Bus Widths of DRAM Control Pins Pin name Data bus in 16 bit mode Data bus in 8 bit mode 2CAS 1WE mode Area 4 RAS 1CAS 2WE mode Area 4 RAS Area 4 RAS Area 5 RAS Area 5 RAS Area 5 RAS Area 4 CASL Area 4 CAS Area 4 CAS Area 4 CASH Area 4 WEL Area 4 CAS Area 5 CASL Area 5 CAS Area 5 CAS Area 5 CASH Area 5 WEL Area 5 CAS Area 4 WE Area 4 WEH Area 4 WE Area 5 WE Area 5 WEH Area 5 WE Remarks Correspondence between L and H and lower 1 bit of address for data bus in 16 bit mode e 1 CASL CAS corresponding to area containing 0 in AO CASH CAS corresponding to area containing 1 in AO WEL WE corresponding to area containing 0 in AO WEH WE corresponding to area containing 1 in AO 155 CHAPTER 4 BUS INTERFACE Row and Column Addresses The page size select bits PGS3 to PGSO of DRAM control registers 4 and 5 DMCR4 and DMCR5 determines whether to create DRAM interface addresses When the high speed page mode is used PGS3 to PGSO and the data bus width determine whether access is within a page Table 4 16 3 Page Size Select Bits PGS3 to 0 0000 Row address 256 A31 16 A15 00 Column address Determine whether access is within page 8 bit bus 16 bit bus 0001 512 0010 1024 001 1 4096 0100 to 1111 res
143. 4 16 Relationship between Data Bus Widths and Control Signals O 8 bit bus width Figure 4 16 9 External Bus Access for 8 bit Bus Width A Word access a PA1 PAO 00 gt 1 Output A1 A0 00 2 Output A1 A0 01 3 Output A1 A0 10 4 Output A1 A0 11 MSB LSB b PA1 PAO 01 gt 1 Output A1 A0 00 2 Output A1 A0 01 3 Output A1 A0 10 4 Output A1 A0 11 8bit B Half word access a PA1 PAO 00 gt 1 Output A1 A0 00 2 Output A1 A0 01 b PA1 PA0 01 gt 1 Output A1 A0 00 2 Output A1 A0 01 11 C Byte access PA1 PAO 00 gt 1 Output A1 A0 00 b PA1 PAO 01 gt 1 Output A1 A0 01 10 11 PA1 PAO Output A1 A0 Lower 2 bits of output address First byte location of output address Data byte location for access Bus access count 1 to 4 c PA1 PAO 10 gt 1 Output A1 A0 00 2 Output A1 A0 01 3 Output A1 A0 10 4 Output A1 A0 11 c PA1 PAO 10 1 Output A1 A0 10 2 Output A1 A0 11 00 01 c 1 10 gt 1 Output A1 A0 10 00 01 Lower 2 bits of address specified by program d PA1 PAO 11 1 Output A1 A0 00 2 Output A1 A0 01 3 Output A1 A0 10 4 Output A1 A0 11 d PAt PAO 11 1 Output A1 A0 10 2 Output A
144. 44 149 150 16 bit data Dus eornm ete 157 16 bit reload register TMRLR 286 16 bit reload time register 282 16 bit reload timer block diagram 283 16 bit timer register 286 1 detection 295 1 detection data register BSD1 293 20 bit delayed branch macro instruction 419 20 bit standard branch macro instruction 418 32 bits 16 bits bus 32 32 bit architecture 30 32 bit delayed branch macro instruction 421 32 bit standard branch macro instruction 420 8 bit bus width 148 145 149 150 8 bit data 156 A A D converter block diagram 269 A D converter operation mode 276 A D converter register 268 A D converter characteristic of 268 A D converter note on 280 A D converter other note on using 280 A D converter successive approximation conversion TDC 3 access modes ertet noit retta 69 addition and subtraction instruction
145. 5 OUTK INTE x GATE CTL 2 gt UF gt PIRQ CSL1 Clock selector K CNTE K CSLO a TRG 5 Retrigger IN CTL EXCK PWM ch 0 ch 1 y 009 3 A D ch 2 K 2 2 25 Prescaler clearing MOD2 MOD1 Internal clock MODO 3 283 CHAPTER 12 16 BIT RELOAD TIMER 12 2 Control Status Register TMCSR The control status register is used to control the 16 bit timer operation mode and interrupts Set the bits other than UF CNTE and TRG again when CNTE is 0 Simultaneous writing is enabled Configuration of Control Status Register TMCSR The configuration of the control status register TMCSR is shown below 11 10 9 8 7 6 5 4 3 2 1 0 TMCSR Initial value Address 00002EH CSL1 CSLO MOD2 MOD1 MODO OUTE OUTL RELD INTE UF TRG 0000364 000m 000042m RW RW RW RW RW RW RW RW RW RW RW RW Bit Functions of Control Status Register TMCSR bits 11 10 CSL1 CSLO Count clock SLect These bits are used to select the count clock Table 12 2 1 lists the clock sources that can be selected Table 12 2 1 CSL Bit Setting Clock Source Clock source machine clock 2 9 23 25 Reserved bits 9 8 7 MOD2 MOD1 MODO MODe These bits specify the operation mode Always set these bits to 0 bit 6 OUTE OUTput Enable Always set this bit to 0 bit 5 OUTL Always set this bit to 0 bit 4 RELD This is a reload enable bit Setting this bit to 1 e
146. 6 aX de RAS i NH CASL Upper address side CASH Loweraddressside 1 7 WE O Bus width 8 bits access half words Figure 4 17 20 Example 3 of Usual DRAM Read Cycle Timing Chart Q1 Q2 04 05 01 Q2 04 O5 BEES 4 A24 00 X X 0 row adr X 0coladr X X Y 1 row adr X 4H coladr X D31 24 G gt Gn i D23 16 RAS M CAS 7 P WE 3 178 4 17 11 Usual DRAM Write Cycles 4 17 Bus Timing This section provides usual DRAM write cycle timing charts Usual DRAM Write Cycle Timing Charts O Bus width 16 bits access half words Figure 4 17 21 Example 1 of Usual DRAM Write Cycle Timing Chart Q1 Q3 Q4 Q5 1 1CAS 2WE A24 00 X X X 0 row adr X 0 col adr X 031 24 X 0 X D23 16 X 1 X RAS X CAS WEL 2 2CAS 1WE A24 00 X X X 0 rowadr X 0 col adr X 031 24 X 0 X D23 16 X 1 ba RAS N CASL CASH ma WE 179 CHAPTER 4 BUS INTERFACE 180 O Bus width 16 bits access bytes Figure 4 17 22 Example 2 of Usual DRAM Write Cycle Timing Chart Q1 Q2 Q3 Q4 Q5 Q2 Q3 Q4 Q5
147. 6 bits D23 to D16 and WR1X cannot be used as l O ports Pin Maximum bus width 16 bits 8 bits DACKO to DACK2 and EOPO to EOP2 are output in external bus cycles The DMAC register specifies whether to output these signals The output time is the same as WROX to WR1X 165 CHAPTER 4 BUS INTERFACE 4 17 3 Read Cycles in Each Mode This section provides read cycle timing charts in each mode B Read Cycle Timing Charts 166 O Bus width 16 bits access half words Figure 4 17 3 Example 1 of Read Cycle Timing Chart BAT BA2 2 BAI BA2 J A24 00 X 0 X X 2 X D31 24 A d807 A 23 D23 16 RDX 7 O Bus width 16 bits access bytes Figure 4 17 4 Example 2 of Read Cycle Timing Chart BAI BA2 BAI BA2 BA BA2 BM BA BC 12 4 A2 00 X 0 X X 30 X X3 X 349 X u ee D23 16 Lx nx 7 X Invalid data input O Bus width 8 bits access words Figure 4 17 5 Example 3 of Read Cycle Timing Chart BA1 BA2 1 2 1 2 1 BA2 A24 00 X 0 D31 24 C405 023 16 7 1 3 X 2 X X i Hae
148. 8 4 4 ADD ADDN CMP LSL LSR and ASR instructions only id OP s5 u5 Ri 7 5 4 OP u8 rel8 dir reglist D 8 8 E OP SUB OP Ri 8 4 4 407 APPENDIX E Instructions 408 Table E 2 Instruction Formats OP rel11 APPENDIX E Instructions E 1 FR Series Instructions This section describes the FR series instructions in the following order FR Series Instructions Table E 1 1 Table E 1 2 Table E 1 3 Table E 1 4 Table E 1 5 Table E 1 6 Table E 1 7 Table E 1 8 Table E 1 9 Table E 1 10 Table E 1 11 Table E 1 12 Table E 1 13 Table 1 14 Table E 1 15 Table E 1 16 Table E 1 17 Table E 1 18 Table E 1 19 Table E 1 20 Addition and Subtraction Instructions Compare Operation Instructions Logical Operation Instructions Bit Operation Instructions Multiplication and Division Instructions Shift Instructions Immediate Value Setting or 16 32 Bit Immediate Value Transfer Instruction Memory Load Instructions Memory Store Instructions Interregister Transfer Instructions Standard Branch Without Delay Instructions Delayed Branch Instructions Other Instructions 20 Bit Standard Branch Macro Instructions 20 Bit Delayed Branch Macro Instructions 32 Bit Standard Branch Macro Instructions 32 Bit Delayed Branch Macro Instructions Direct Addressing Instructions Resource Instructions Coprocessor Control Instructions 409 APPENDIX E Instructions B Addition and Subtraction Instructions Table E 1 1 Add
149. 9 Figure 1 2 1 General Block Diagram of MB91F109 FR CPU RAM 2KB Bit Search Module DMAC 8ch DREQO DREQ1 DREQ2 DACKO DACK1 DACK2 EOPO EOP1 EOP2 32bit lt 16bit l bus 16bit Harvard 11 Princeton Bus Converter D31 D16 A24 A00 RDX WROX 1X any Gibis Bus Controller 32bit RASO RAS1 DRAM Controller CSOL CS1L CSOH CS1H DWOX DW1X FLASH ROM 254KB RAM 2KB R bus 16bit UART Sch 800 501 withBaudRate Timer Sco SC1 SC2 Bus Converter X0 X1 RSTX Clock Control Unit Watch Dog Timer INTO INT3 NMIX Interrupt Control Unit 10bitA D Converter 4ch Reload Timer 3 ch ANO AN3 AVCC AVRH 55 AVRL ATGX D bus 32bit Notes PWM Timer 4ch TRGO 3 Terminals are represented by the function some terminals are actually multiplexed When REALOS is used perform time management using an external interrupt or internal timer 1 3 Outside Dimensions 1 3 Outside Dimensions Figures 1 3 1 to 1 3 3 show the outside dimensions of the MB91F109 Outside Dimensions QFP 100 Figure 1 3 1 Outside Dimensions of FPT 100P M06 100 06 section length EIAJ code QFP100 P 1420 4 Plastic QFP with 100 pins Lead pitch 0 65 mm Package width x length Teen Lead shape Gull wing Sealing Plastic mold Flat terminal 0 80 mm Plastic QFP with 100 pins F PT
150. 91F109 and Two 16 Bit Output DRAMs 16 Bit Data Bus This LSI Area 4 DRAM Area4 RAS RASO Area4 CASL CSOL Area4 CASH CS0H 4 WE DWOX Area5 RAS RAS1 Area5CASL CS1L 5 CASH CS1H 5 WE DW1X Area 5 DRAM RDX A00 not A09 01 connected D31 16 158 4 17 Bus Timing 4 17 Bus Timing This section provides bus access timing charts used in each mode and explains bus access operation for the following items Usual bus access Wait cycle DRAM interfaceDRAM interface DRAM refresh External bus request Usual Bus Access The usual bus interface handles read cycles and write cycles in the same way as 2 clock cycles This manual represents the respective types of cycles as BA1 and 2 Basic read cycle Basic write cycle e Read cycle in each mode Write cycle in each mode Readand write combination cycle B Wait Cycles The wait cycles include automatic wait cycles specified by the WTC bit of the AMD register and external wait cycles using the RDY pin The wait cycles take over the previous cycle and repeat the BA1 cycle until the wait request is canceled Automatic wait cycle External wait cycle B DRAM Interface Chip select areas 4 and 5 can be used as DRAM spaces Set the DRME bit of AMD4 or AMD5 to control the operation by DMCR4 and DMCR5 The DRAM interface has the following three modes depending
151. A 5 Table A 6 Table B 1 Table B 2 Table C 1 Table C 2 Table C 3 Table C 4 Table C 5 Table E 1 Table E 2 Table E 1 1 Table E 1 2 Table E 1 3 Table E 1 4 Table E 1 5 Table E 1 6 Table E 1 7 Table E 1 8 Table E 1 9 Table E 1 10 Table E 1 11 Table E 1 12 Table E 1 13 Table E 1 14 Table E 1 15 Table E 1 16 Table E 1 17 Table E 1 18 Table E 1 19 Table E 1 20 VO Map 5 0 s nd nt ende tei e e E 376 377 Interrupt Vectors Ie ara sat RR Hui Pen Pe Pad e D edd DER RR eod 379 Interrupt Vectors 2 2 x credet epe eec ne Pec 380 Explanation of Terms Used in the Pin Status List 383 Pin Status for 16 bit External Bus Length and 2CA1WR Mode 384 Pin Status for 16 bit External Bus Length and 2CA1WR Mode 387 Pin Status in 8 bit External Bus Mode sse nnne nnne 390 Pin Status in Single Chip Mode enne nnns nnne ens nnne 393 Explanation of Addressing Mode Codes 22004 40 0 0 00 eene enne 405 Formats 2 riri ttr 407 Addition and Subtraction Instructions ssssssssssssssssesesee enne nennen 410 Compare Operation Instructions aaa aa ekaia a
152. AC FP SP Rj Register using direct addressing RO to R15 AC FP SP R13 Register using direct addressing R13 AC Ps Register using direct addressing Program status register Rs Register using direct addressing TBR RP SSP USP MDH MDL CRi Register using direct addressing CRO to CR15 Register using direct addressing CRO to CR15 4 Unsigned 4 bit immediate value 0 to 15 or 16 to 1 according to instruction types i8 Unsigned 8 bit immediate value 128 to 255 Note Values from 128 to 1 are handled as 128 to 255 i20 Unsigned 20 bit immediate value OX80000 to OXFFFFF Note Values from OX7FFFF to 1 are handled as OX7FFFF to OXFFFFF 132 Unsigned 32 bit immediate value OX80000000 to OXFFFFFFFF Note Values from 0 80000000 to 1 are handled as 0 80000000 to OXFFFFFFFF 55 Signed 5 bit immediate value 16 to 15 510 Signed 10 bit immediate value 512 to 508 multiple of 4 only u4 Unsigned 4 bit immediate value 0 to 15 u5 Unsigned 5 bit immediate value 0 to 31 u8 Unsigned 8 bit immediate value 0 to 255 u10 Unsigned 10 bit immediate value 0 to 1020 multiple of 4 only dir8 Unsigned 8 bit direct address 0 to OXFF dir9 Unsigned 9 bit direct address 0 to OX1FE multiple of 2 only dir10 Unsigned 10 bit direct address 0 to OX3FC multiple of 4 only label9 Signed 9 bit branch address 0X100 to OXFC multiple of 2 only label12 Signed 12 bit branch ad
153. AM 1Kbyte 357 CHAPTER 16 FLASH MEMORY Table 16 4 1 Sector Addresses Sector address Address range 000C0800 1h to OOODFFFC Dh MSB side 16 bits Corresponding bits bit 31 to 16 Sector capacity 63 Kbyte 000E0000 1h to OOOEFFFC Dh MSB side 16 bits bit 31 to 16 32 Kbyte 000F0000 1h to OOOF3FFC Dh MSB side 16 bits bit 31 to 16 8 Kbyte 000F4000 1h to 000F7FFC Dh MSB side 16 bits bit 31 to 16 8 Kbyte 000F8000 1h to OOOFFFFC Dh MSB side 16 bits bit 31 to 16 16 Kbyte bit 15 to 0 63 Kbyte 000C0802 3h to 000DFFFE Fh LSB side 16 bits 000E0002 3h to OOOEFFFE Fh LSB side 16 bits bit 15 to 0 32 Kbyte 000F0002 3h to OOOF3FFE Fh LSB side 16 bits bit 15 to 0 8 Kbyte 000F4002 3h to 000F7FFE Fh LSB side 16 bits bit 15 to 0 8 Kbyte 358 000F8002 3h to OOOFFFFE Fh LSB side 16 bits bit 15 to 0 16 Kbyte 16 5 Flash Memory Access Modes 16 5 Flash Memory Access Modes The following two types of access mode are available for the FR CPU ROM mode One word 32 bits can be read in one cycle but not written Programming mode Access to data with a length in words 32 bits is inhibited but writing data with a length in half words 16 bits is enabled B FR CPU ROM Mode 32 Bits Read only In this mode the flash memory serves as FR CPU internal ROM This mode enables to read one word 32 bits
154. B Rj Ri EORB Rj Ri BANDL u4 Ri BORL 04 Ri BEORL u4 Ri BANDH 04 Ri BORH 04 Ri BEORH u4 Ri Data in areas marked as Reserved or is undefined 378 APPENDIX B Interrupt Vectors APPENDIX B Interrupt Vectors Table B 1 and Table B 2 list the interrupt vectors The interrupt vector tables list causes for MB91F109 interrupts together with interrupt vector or interrupt control register assignments B Interrupt Vectors Table B 1 Interrupt Vectors 1 2 Interrupt No Interrupt Decimal Hexa level 1 decimal Cause for the interrupt Reset Offset TBR default address 2 000FFFFC Reserved for the system 000FFFF8 Reserved for the system OOOFFFF4 Reserved for the system 000FFFFO Reserved for the system 000FFFEC Reserved for the system 000FFFE8 Reserved for the system OOOFFFE4 Reserved for the system 000FFFEO Reserved for the system 000FFFDC o NI oa AJ wy Pp Reserved for the system OOOFFFD8 Reserved for the system OOOFFFD4 Reserved for the system 000FFFD0j N Reserved for the system 000FFFCC Reserved for the system 000FFFC8 A Undefined instruction exception OOOFFFC4 NMI request 000FFFCO s External interrupt 0 000FFFBC N External interrup
155. B5 DREQ2 CS1H PB6 DACK2 DW1X PB7 circuit format 1 5 Pin Functions Function RAS output of DRAM bank 0 CASL output of DRAM bank 0 CASH output of DRAM bank 0 WE output of DRAM bank 0 Low active RAS output of DRAM bank 1 CASL output of DRAM bank 1 CASH output of DRAM bank 1 WE output of DRAM bank 1 Low active See the description of the DRAM interface for more information EOP2 DMAC EOP output ch2 This function is valid when DMAC EOP output is enabled DREQ2 Input of DMA external transfer request This input is used from time to time when this pin is selected for the DMAC transfer cause Therefore it is needed to stop output by other functions except when such output is performed intentionally DACK2 Output of DMAC external transfer request acceptance ch2 This function is valid when the output of DMAC transfer request acceptance is enabled PBO 7 When each pin is not used for the corresponding purpose the pin can be used as a general purpose I O port Mode pins 0 to 2 Use these pins to set the basic MCU operation mode Connect these pins directly to Vcc or Vss Clock oscillator input Clock oscillator output External reset input Digital circuit power supply Be sure to connect the power supply to every VCC pin NMIX Nonmaskable interrupt NMI input Low active INTO PEO INT1 PE1 INTO 1 Input of external interrupt request This input is used f
156. BRQ P82 WR1X P85 D25 P31 D28 P34 D29 P35 D31 P37 A01 P41 A04 P44 A07 P47 CS3X PA3 EOP1 CS2X PA2 RASO PBO N C 03 A15 P57 08 P50 CHAPTER 1 OVERVIEW 1 5 Pin Functions Tables 1 5 1 to 1 5 5 lists the MB91F109 pin functions The numbers shown in the tables has nothing to do with the package pin numbers Since pins have different pin numbers among QFP LQFP and FBGA see Section 1 4 Pin Arrangement Diagrams Functions Table 1 5 1 Pin Functions 1 5 Pin name circuit Function format D16 P20 Bits 16 to 23 of external data bus D17 P21 When the external bus width is set to 8 bits or in D18 P22 single chip mode these pins can be used as D19 P23 general purpose I O ports P20 to P27 D20 P24 D21 P25 D22 P26 D23 P27 D24 P30 Bits 24 to 31 of external data bus D25 P31 When these pins are not used for the data bus they D26 P32 can be used as general purpose I O ports P30 to D27 P33 P37 D28 P34 D29 P35 D30 P36 D31 P37 00 40 Bits 00 to 15 of external address bus A01 P41 When these pins are not used for the address bus A02 P52 they can be used as general purpose I O ports P40 A03 P43 to P47 and P50 to P57 A04 P44 A05 P45 06 46 07 47 A08 P50 09 51 10 52 A11 P53 A12 P54 A13 P55 A14 P56 A15 P57 1 5 Pin Functions Table 1 5 1 Pin Functions 1 5 Pin name
157. C 1 CHC 1 Yes No DBLON 0 DBLON lt 0 Yes DBLACK 0 Yes No No VSTP 0 VSTP 0 Yes WAIT 100 uS SLCTO lt 1 CHC lt 0 lt Notes gt When making a PLL setting switch the clock to the divide by two clock in advance Since this model does not support the clock doubler function use the initial setting as is Restart the PLL if it is stopped Design software so that 100 microseconds or more are allowed until oscillation stabilizes after the PLL restarts Switch the PLL output tap to 25 MHz Switch the divide by two clock to the PLL clock The DBLON VSTP SLCTO bits can be set in any order 108 3 15 Example of PLL Clock Setting The peripheral operating frequency must not exceed 25 MHz Design software so that 100 microseconds or more are allowed until oscillation stabilizes after the PLL VCO restarts Do not allow cache on off to cause a wait time shortage Clock System Reference Diagram 12 5MHz Figure 3 15 2 Clock System Reference Diagram Input of oscillation B Example of Assembler Source n kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk PLL Sample Program kkkkkkkkkkkkkkkkkkkkkkkkkkkkkk
158. C Pin Control Register DATCR 330 bit 21 20 13 12 5 4 LSn1 LSnO Transfer request input detect level select Each of these bits selects the detection level of the corresponding external transfer request input pin DREQn as shown in Table 15 4 1 Table 15 4 1 Selection of Transfer Input Detection Levels Operation control function Detection of rising edge Detection of falling edge Detection of H level Detection of L level The values of these bits are undefined after resetting The bits can be both read and written When continuous transfer mode is used set the bits for H level or L level detection bit 19 11 3 AKSEn bit 18 10 2 AKDEn These bits specify the time when the transfer request acknowledgment output signal is to be generated from the corresponding output pin and specify whether to enable the output function of the corresponding transfer request acknowledgment output signal pin Table 15 4 2 Specification of Transfer Request Acknowledgment Output Operation control function Disables transfer request acknowledgment output Enables transfer request acknowledgment output Acknowledgement is output when transfer destination data is accessed Enables transfer request acknowledgment output Acknowledgement is output when transfer source and destination data is accessed These bits are initialized to 00 by resetting The bits can be both read and written
159. C transfer cause Therefore it is needed to stop output by other functions except when such output is performed intentionally PE4 5 General purpose I O ports 77 DACKO PE6 F DACKO Output of DMAC external transfer request acceptance chO This function is valid when the output of DMAC transfer request acceptance is enabled PE6 General purpose I O port This function is valid when the output of DMAC transfer request acceptance or DACKO output is disabled 1 5 Pin Functions Table 1 5 4 Pin Functions 4 5 Pin name circuit Function format 78 DACK1 PE7 F DACK1 Output of DMAC external transfer request acceptance ch1 This function is valid when the output of DMAC transfer request acceptance is enabled PE7 General purpose I O port This function is valid when the output of DMAC transfer request acceptance or DACK1 output is disabled 79 SIO TRGO PFO F 510 UARTO data input The input of each pin is used from time to TRGO External trigger time while input input of PWM timer operation is selected Therefore it is needed to stop output by other functions except when such output is performed intentionally PF1 General purpose I O port 80 SOO TRG1 PF1 F SOO UARTO data output This function is valid when UARTO data output is enabled TRG1 External trigger input of PWM timer This function is valid when PF1 and UARTO data output is disabled
160. CH MODULE 13 1 Overview of the Bit Search Module The bit search module searches the data written to the input register for 0 1 or a change point and returns the detected bit position Bit Search Module Registers Figure 13 1 1 shows the bit search module registers Figure 13 1 1 Bit Search Module Registers 31 0 Address 000003 BSDO 0 detection data register Address 000003 4 BSD1 1 detection data register Address 000003F8H BSDC Change point detection data register Address 000003FCH BSRR Detection result register Block Diagram of Bit Search Module Figure 13 1 2 is a block diagram of the bit search module Figure 13 1 2 Block Diagram of the Bit Search Module D BUS Address decoder Input latch Detection mode Y 1 detection data Bit search circuit 292 Search result 13 2 Bit Search Module Registers 13 2 Bit Search Module Registers The bit search module uses the following four registers e 0 detection data register BSDO e 1 detection data register BSD1 e Change point detection data register BSDC Detection result register BSRR O Detection Data Register BSDO 31 0 000003 0 Read write W Initial value Undefined The module detects 0 for the value written to this register The ini
161. CR3 ICR2 ICR1 ICRO ICR13 0000040 ICR4 ICR3 ICR2 ICR1 ICRO ICR14 Address 0000040FH ICR4 ICR3 ICR2 ICR1 ICRO ICR15 Address 00000410H ICR4 ICR3 ICR2 ICR1 ICRO ICR16 Address 0000041 1m ICR4 ICR3 ICR2 ICR1 ICRO ICR17 Address 000004124 ICR4 ICR3 ICR2 ICR1 ICRO ICR18 Address 000004134 ICR4 ICR3 ICR2 ICR1 ICRO ICR19 Address 000004144 ICR4 ICR3 ICR2 ICR1 ICRO ICR20 Address 000004154 ICR4 ICR3 ICR2 ICR1 ICRO ICR21 Address 000004164 ICR4 ICR3 ICR2 ICR1 ICRO ICR22 Address 000004174 ICR4 ICR3 ICR2 ICR1 ICRO ICR23 00000418 ICR4 ICR3 ICR2 ICR1 ICRO ICR24 00000419 ICR4 ICR3 ICR2 ICR1 ICRO ICR25 0000041 ICR4 ICR3 ICR2 ICR1 ICRO ICR26 Address 0000041BH ICR4 ICR3 ICR2 ICR1 ICRO ICR27 Address 0000041CxH ICR4 ICR3 ICR2 ICR1 ICRO ICR28 Address 0000041 DH ICR4 ICR3 ICR2 ICR1 ICRO ICR29 Address 0000041 Em ICR4 ICR3 ICR2 ICR1 ICRO ICR30 Address 0000041 Fu ICR4 ICR3 ICR2 ICR1 ICRO ICR31 R RW RW RW RW 225 CHAPTER 8 INTERRUPT CONTROLLER 226 00000420 00000421 00000422 00000423 00000424 00000425 00000426 00000427 00000428 00000429
162. Chart O Bus width 16 bits access half word read write Figure 4 17 14 Example of Automatic Wait Cycle Timing Chart BA1 BA1 BA2 BA1 BAI BA2 07 CLK 21 A24 00 L 0 1 2 3 031 16 RDX WROX 1X DACKO Explanation of operation When implementing automatic wait cycles set the WTC bit of the AMD register for each chip select area The above example is an example the WTC bits are set 001 to insert one wait bus cycle in the usual bus cycles In this case it follows that 2 usual clock bus cycles 1 wait clock cycle 3 clock bus cycles Up to 7 clock cycles of automatic wait usual bus cycles 9 clock cycles can be specified 171 CHAPTER 4 BUS INTERFACE 4 17 7 External Wait Cycles This section provides an external wait cycle timing chart External Wait Cycle Timing Chart O Bus width 16 bits access half words Figure 4 17 15 Example of External Wait Cycle Timing Chart BAi BAi BAI BA1 1 BA2 CLK 24 00 X 0 X Read 031 D31 16 RDX Write D31 16 X WROX 1X wait wait wait RDY RDY 5 509 gt Automatic Wait by RDY i wai K cycle gt Explanation of operation When
163. Decimal Reset 1 Reserved by the system Reserved by the system Reserved by the system Reserved by the system Reserved by the system INTE instruction Reserved by the system Reserved by the system Step trace trap Reserved by the system Undefined instruction exception NMI for user Maskable interrupt cause 0 Maskable interrupt cause 1 ae Maskable interrupt cause INT instruction Reserved by the system used for REALOS Reserved by the system used for REALOS Maskable interrupt cause INT instruction 1 Fixed address OOOFFFFCy is always used for the reset vector even when the TBR value is changed 2 See Appendix Interrupt Vector for the vector table for the MB91F109 61 CHAPTER 2 CPU 2 8 7 Multiple EIT Processing When multiple EIT events occur concurrently the CPU selects one EIT event accepts it executes the EIT sequence and then detects another EIT event It repeats this operation for all EIT events When no more acceptable EIT event is detected the CPU executes the instruction of the handler of the EIT event accepted last When multiple EIT events occur concurrently the execution order of the handlers of individual events is determined according to the following two factors Priority for EIT event acceptance Mode of masking other EIT events after one is accepted Priorit
164. ER 9 1 Overview of U TIMER 9 2 U TIMER Registers 9 3 U TIMER Operation 239 CHAPTER 9 U TIMER 9 1 Overview of U TIMER The U TIMER is a 16 bit timer that generates a UART baud rate Combining the chip operating frequency and U TIMER reload value can generate a desired baud rate Since a count underflow causes an interrupt the U TIMER can also be used as an interval timer The MB91F109 contains three channels of U TIMER When the U TIMER is used as an interval timer two channels 0 and 1 of U TIMER be cascaded to count up to 222 interval U TIMER Registers Figure 9 1 1 shows the U TIMER registers Figure 9 1 1 U TIMER Registers 15 8 7 0 UTIM R UTIMR W UTIMC R W B U TIMER Block Diagram Figure 9 1 2 is a U TIMER block diagram Figure 9 1 2 U TIMER Block Diagram 15 0 UTIMR reload register 15 load 0 UTIM timer clock underflow _ gt control Peripheral clock MUX f f to UART Channel 0 only underflow U TIMER1 240 9 2 U TIMER Registers 9 2 U TIMER Registers The following three U TIMER registers are used U TIMER UTIM e Reload register UTIMR U TIMER control register UTIMC E U TIMER UTIM The UTIM indicates the timer value Access it using a 16 bit transfer instruction 15 14 eee 2 1 0 UTM pe 0 Addre
165. ERO ERA 3 UART block 247 UART 246 UART clock 255 UART operation 255 UART 402224422 246 UART example for use 263 UART note ON 263 undefined instruction exception operation for 66 underflow operation 287 user interrupt NMI operation for 64 user stack pointer 37 NIC Td 37 usual DRAM interface read timing chart 173 usual DRAM interface write timing chart 175 usual DRAM read cycle timing chart 177 usual DRAM write cycle timing chart 179 U TIMER 241 U TIMER block 240 U TIMER control register UTIMC 241 U TIMER 240 ioe Attire e Deb 241 UTIMES esL 241 V variable allocation with initial value 396 Walt Cyclo itte iate etus 159 watchdog controller block diagram
166. FRE and RDRF Set Timing Mode 1 KO Soe ORE FRE RDRF Reception interrupt B interrupt Flag Set Timing for Data Reception in Mode 2 When the last data item D7 is detected after data reception transfer is completed the ORE and flags are set to issue an interrupt request to the CPU If ORE is active the SIDR data is invalid Figure 10 9 3 ORE and RDRF Set Timing Mode 2 Data ORE RDRF Reception interrupt 261 CHAPTER 10 UART Interrupt Flag Set Timing for Data Transmission in Mode 0 1 or 2 TDRE is cleared when data is written to the SODR register After the written data is transferred to the internal shift register and the SODR register is ready to accept the next item of write data TDRE is set again to issue an interrupt request to the CPU When 0 is written to TXE or RXE in mode 2 of the SCR register during transmission TDRE of the SSR register is set to 1 thereby stopping the transmission shifter and inhibiting UART transmit operation When a 0 is written to TXE or RXE in mode 2 of the SCR register during transmission data written to the SODR register before transmission is stopped is transmitted Figure 10 9 4 TDRE Set Timing Mode 0 or 1 Writing to SODR TDRE An interrupt request is issued to the CPU SO interrupt SO output ST Do 01 p2 D3 D4 ps pe 07 sp SP ST Do D1 D2 ps ST Starter bit DO to D7 Data bit S
167. HAPTER 8 INTERRUPT CONTROLLER 8 4 Hold Request Cancel Request Level Setting Register HRCL The HRCL register is used to set the interrupt level for issuing a hold request cancel request Configuration of Hold Request Cancel Request Level Setting Register HRCL The register configuration of the hold request cancel request level setting register HRCL is as follows bit7 Address 00000431 LVL4 LVL3 LVL2 LVL1 LVLO 11111 Initial value R RW RW RW RN B Bit Functions of Hold Request Cancel Request Level Setting Register HRCL bit4 to 0 LVL4 to 0 These bits specify the interrupt level for issuing a hold request cancel request to the bus master When an interrupt request having a level higher than the interrupt level set in this register is generated a hold request cancel request is issued to the bus master The LVL4 bit is fixed to 1 and cannot be set to 0 230 8 5 Priority Check 8 5 Priority Check IWhen multiple interrupt causes are generated simultaneously this module selects one having the highest priority and posts the interrupt level and number of the cause to the CPU NMI is given the highest priority among the interrupt causes handled by this module B Priority Check The criteria for checking the priority of interrupt causes are as follows 1 NMI 2 Cause that satisfies the following conditions Causesin an interrupt level ot
168. Initial value R1W RBW STR CKS1 CKSO 00 000 Access R W Access R W The timebase timer is a counter used for oscillation stabilization wait intervals It operates with a frequency that is one half of XO when CHC 1 is set by the gear control register GCR and with a frequency equal to the internal PLL oscillation frequency when CHC 0 For example when the PLL oscillation frequency is 25 MHz at CHC 0 one cycle equals 40 ns and 40 x 32 1280 ns equals one refresh interval The refresh interval is counted with the output from the timebase timer B Bit Functions of Refresh Control Register bit 13 to 8 REL RELoad value bits The REL is a register to set refresh intervals At read time the count of the refresh interval downward counter is read as is The DRAMs of areas 4 and 5 are refreshed at the same time with the interval indicated by the REL bit 7 R1W Refresh 1 Wait The R1W bit extends the first refresh cycle R1 by only one cycle 0 no wait initial value 1 wait bit 6 R3W Refresh 3 Wait The R3W bit extends the third refresh cycle by one cycle 0 no wait initial value 1 wait 130 4 11 Refresh Control Register RFCR bit 2 STR STaRt bit The STR bit controls or starts and stops the downward counter 0 STOP initial value 1 START When the STR is set the REL value is loaded into the downward counter When the REFE bit of the DMCR and the STR b
169. LE uidi b entier 37 memory load 413 mriemory map 2 2 24 430 memory map commen to FR series 45 memory store 414 mode code 5 405 mode elds 70 mode pln 69 mode MDO to 2 27 mode register 70 mode register MODR note on writing to 70 multiple PWM timer channel using 16 bit reload timer eaa i Dee Don ates 322 multiple PWM timer channel via software Startil1g 321 multiplication and division instruction 412 multiplication division result register MDH MDL 37 N NC pin treatment 27 NM lisse tt detto re ttr irri p Mead 233 NMI operation see 218 nonmaskable interrupt NMI 233 nstruction that can be placed in delay slot 50 o detection data register BSDO 293 one shot 317 operation 69 other instruction 417 outside dimension 112 9 outside dimension
170. MA transfer request from one channel DMA transfer requests from another channel are suspended until the current transfer ends When the DMAC detects DMA transfer requests from multiple channels which are active simultaneously these requests are accepted in the following priority order High ch 0 ch 1 gt ch 2 gt ch 3 gt ch 4 gt ch 5 gt ch 6 gt ch 7 low Even when two or more channels issue DMA transfer requests simultaneously DMA transfer is performed for only one channel After that bus control returns to the CPU before performing the DMA transfer for the next channel B When Using a Resource Interrupt Request as a DMA Transfer Request For performing a transfer by the the interrupt level in the interrupt controller must be set to the interrupt inhibition level When an interrupt is to be generated the DMAC operation enable bit in the DMAC must be set to disabled and the interrupt level must be set to an appropriate value B Suppression of DMA Transfer for an Interrupt with a Higher Priority If during DMA transfer in response to a DMA transfer request an interrupt request with a higher priority arrives the MB91F109 can stop the DMA transfer O HRCL register For stopping a DMA transfer operation in response to an interrupt request use the hold request cancel level register HRCL If the interrupt level for an interrupt request issued from a peripheral circuit is higher than that set in the HRCL the DMA tran
171. MDO bit 4 and 3 BW1 and 0 Bus Width bit BW1 BWO specify the bus width of area 0 Bus width 8 bits 16 bits Setting not possible Setting not possible lt Note gt The initial values of both BW1 and BWO are 0 however not register values but the MD1 and MDO pin level outputs are read at read time until writing to the MODR bit 2 to 0 WTC 2 to 0 Wait Cycle bit WTC2 to WTCO specify the number of wait cycles to be automatically inserted when the usual bus interface is running Number of inserted wait cycles WTC2 to WTCO of AMDO are reset to 111 so that seven wait cycles are automatically inserted at bus access time immediately after the reset is released 121 CHAPTER 4 BUS INTERFACE 122 lt Note gt Before writing to the MODR set the bus width equal to that set by the MD2 MD1 and MDO pins in BW1 and BWO of AMDO The bus width of area 0 is specified by the MD2 MD1 and MDO pins at reset time After setting the mode register MODR the bus width set in AMDO becomes valid MODR write RSTX reset 1 CS0 bus width MD2 MD1 MDO pins gt AMDO register Suppose that the width of area 0 is set to 16 bits by the MD2 MD1 and MDO pins and wiring to the MODR is performed without setting AMO with the bus width left as is As the initial value of BW1 BWO of AMDO is 00 the bus width changes to 8 bits thereby causing an error 4 6 Area Mode Regist
172. Masking Other Events 62 EIT Handler Execution Order 2 0 2222 4 63 Mode Pins and Setting Modes 69 Bus Mode Setting Bit and the Function 70 Watchdog Timer Cycles Specified by WT1 and 0 77 Oscillation Stabilization Wait Time Specified by OSC1 and OSCO 79 CPU Machine Clock omae d ten eb e a ve ee eerta 82 eee acte e e aue cde eame dvi e ade eels 83 Watchdog Timer Cycles Specified by WT1 and 0 85 Types of Operation in Standby Mode 2 2 240224 04 0 1 0 nennen nennen nennen 90 Operating Frequency Combinations Depending on whether the Clock Doubler Function is Enabled or Disabled 107 Correspondence between Chip Select Areas and Selectable Bus Interfaces 116 Page Size of DRAM Connected sssssssssssssseeeeeenee ennt tenens nnne 127 Combinations of Bus Widths Available in Areas 4 5 129 Mode Setting Using the Combination of Bits LE2 LE1 and LEQ _ 138 Relationship between Data Bus Widths and Control Signals 2 140 Functions an
173. Memory The address space is 32 bits long linearly Figure 2 6 1 shows an MB91F109 memory map 0000 0000 0000 0000 000F 000F Figure 2 6 1 MB91F109 Memory Map 0000H 0100 0200 0400 FFFF Direct addressing area Byte data Half word data Word data Direct addressing area Initial vector table area The following area in the address space is used for I O The addresses in this area can be directly specified for instruction operands The size of the direct addressing area varies depending on data length Byte data 8 bits 0 to OFF e Half word data 16 bits 0 to 1FF Word data 32 bits 0 to 3FFy O Initial vector table area The area ranging from 000FFCO0 to 000FFFFF is the EIT vector table initial area The vector table used for EIT processing can be mapped to desired addresses by rewriting the TBR The table is returned to these initial addresses when the TBR is reset 44 Memory Map Common to the FR Series 2 6 Memory Map The FR series defines the following memory map This memory map is common throughout the FR series regardless of types except in single chip mode Figure 2 6 2 shows the memory map common to the FR series Figure 2 6 2 Memory Map Common to the FR Series 00000000H 00000010H 00000100 00000200 00000400 00000800 00001000 6 00010000 00080000
174. OXCASL WEL DD WR1X CASH WEH cc WR1X CASH WEH 8 bit bus width Internal register External pin Control pin Internal register External pin Control pin address 0 1 address 0 1 D31 D31 031 D31 WROX CAS WE WROX CAS WE D Internal register External pin Control pin Internal register External pin Control pin address 2 3 address 2 3 D31 D31 D31 D31 CC DD WROX CAS WE WROX CAS WE D D 152 4 16 Relationship between Data Bus Widths and Control Signals Byte Access Bus width Big endian mode Little endian mode 16 bit bus width Internal register External pin Control pin Internal register External pin Control pin address 0 address 0 D31 D31 D31 D31 AA WROX CASL WEL AA WROX CASL WEL Internal register External pin Control pin Internal register External pin Control pin address 1 address 1 31 031 031 7 031 WR1X CASH WR1X CASH WEH Internal register External pin Control pin Internal register External pin Control pin address 2 address 2 D31 D31 D31 D31 WROX CASL WEL cq WROX CASL WEL Internal register External pin C
175. P Stop bit A D Address data multiplexer Figure 10 9 5 TDRE Set Timing Mode 2 Writing to SODR TDRE An interrupt request is issued to the CPU SO ff SO output D0 01 D2 D3 04 D5 D6 D7 00 D1 D2 D3 D4 05 D6 07 DO to D7 Data bit 262 10 10 Notes on Using the UART and Example for Using the UART 10 10 Notes on Using the UART and Example for Using the UART This section provides an example for use of the UART and notes on using the UART Notes on Using the UART Set the communication mode while UART operation is stopped Data transmitted during mode setting cannot be assured If the timing for writing to the serial output data register SODR matches the timing for requesting a receiver interrupt RDRF 1 during UART operation in synchronous transfer mode mode 2 the communication control circuit may stop To prevent this problem write to the SODR after data transfer or immediately after transmission begins Example for Use of the UART In mode 1 multiple slave CPUs are connected to one host CPU as shown in Figure 10 10 1 This resource supports only the communication interface on the host end Figure 10 10 1 Sample System Structure for Mode 1 Host CPU Slave CPU 0 Slave CPU 1 Communication begins with address data transfer by the host CPU Address data is indicated by the fact that the A D bit of the SCR register is 1 Address data is used to se
176. P65 P64 P63 P62 P61 P60 00000000 7 6 5 4 3 2 1 0 DDR7 Initial value Address 0006044 P70 7 6 5 4 3 2 1 0 vie DDR8 Initial value Address 00060BH a P85 P84 P83 P82 P81 P80 000000 7 6 5 4 3 2 1 0 1 DDRA Initial value Address 0006094 PA6 PA5 PA4 2 PA1 0000000 7 6 5 4 3 2 1 0 M DDRB Initial value Address 0006084 PB7 PB6 PB5 PB4 PB2 PB1 PBO 00000000s 7 6 5 4 3 2 1 0 9 DDRE Initial value Address 000002 PE6 5 PE4 2 PE1 PEO 00000000s 7 6 5 4 3 2 1 0 DDRF Initial value Address 000003 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PFO 000000005 204 Access W Access 5 4 Using External Pins as I O Ports 5 4 Using External Pins as I O Ports Table 5 4 1 lists the relationship between the initial value for each external pin and the register specifying whether to use the external pin as an I O port or control pin Single chip External bus indicated in the table mean that the function differs for the operation mode to be used 8 bits and 16 bits also mean that the pin function differs for each external bus width Pin numbers are the examples of QFP As these number
177. PA1 PAO 7 6 5 4 3 2 1 0 PDRB Initial value Address 000008 PB7 PB6 PBS PB4 PB3 PB2 PB1 PBO XXXXXXXX amp 7 6 5 4 3 2 1 0 PDRE Initial value Address 0000124 PE7 PE6 PES PE4 PES PE2 PE1 PEO XXXXXXXX amp 7 6 5 4 3 2 1 0 PDRF Initial value Address 0000134 6 PF5 PF4 PF2 PF1 PFO Access R W Access R W Access R W Access R W Access R W Access R W Access R W Access R W Access R W Access R W Access R W 203 CHAPTER 5 I O PORTS 5 3 Data Direction Register DDR The data direction registers DDR2 to DDRF control the I O direction of the corresponding I O ports in bit units Set 0 to perform input control and set 1 to perform output control Configuration of Data Direction Register DDR The data direction register DDR is configured as follows 7 6 5 4 3 2 1 0 DDR2 Initial value Address 0006014 P27 P26 P25 P24 P23 P22 P21 P20 00000000s 7 6 5 4 3 2 1 0 DDR3 Initial value Address 0006004 P37 P36 P35 P34 P33 P32 P31 P30 000000008 7 6 5 4 3 2 1 0 DDR4 Initial value Address 000607H P47 P46 P45 P44 P43 P42 P41 P40 00000000s 7 6 5 4 3 2 1 0 DDR5 Initial value Address 0006064 P57 P56 P55 P54 P53 P52 P51 P50 000000005 7 6 5 4 3 2 1 0 DDR6 Initial value Address 0006054 P67 P66
178. Q 236 B Hold 8 8 Example of Using the Hold Request Cancel Request Function HRCR Request Cancel Request Sequence O Example of interrupt routine Figure 8 8 2 Example of Timing for Hold Request Cancel Request Sequence Interrupt Level HRCL gt a CPU DHRQ HRQ HACK RUN Bus hold Interrupt processing Bus hold DMA transfer X Qo x Example of interrupt routine TD EU EN GPS D Incrementing PDRR _ A Clearing the interrupt cause 8 Decrementing PDRR 622500902 ih a X RET 0000 0001 2 0000 The interrupt level changes when an interrupt request is issued If the level is higher than that set in the HRCL register HRCR is activated for DMA thereby causing DMA to cancel the hold request and the CPU returns from the hold state and performs interrupt processing The interrupt routine increments PDRR 1 to clear the interrupt cause 2 thereby changing the interrupt level and rendering HRCR inactive Accordingly HRCR is inactivated to allow DMA to issue a hold request but the hold request is interrupted because PDRR is not 0 The hold request is transmitted to the CPU to allow DMA transfer again only after PDRR is decremented 3 O Example of multiple interrupt routine Figure 8 8 3 Example of Timing for Hold Request Cancel Request Sequence Interrupt Level HRCL gt a gt
179. RAM interface Double CAS DRAM usual DRAM interface Single CAS DRAM e Hyper DRAM High speed page mode Selection of 2CAS 1WE and 1CAS 2WE CBR refresh system Selfrefresh mode Output of RAS and CAS programmable waveforms 4 3 Bus Interface O Bus size specification A bus width can be optionally specified for each area by register setting A bus width set by pins MD2 MD1 and MDO at reset time is specified for area 0 After writing to the mode register MODR a bus size is specified by the value set in the AMDO register 117 CHAPTER 4 BUS INTERFACE 4 4 Area Select Register ASR and Area Mask Register AMR The area select registers ASR1 to ASR5 and area mask registers AMR1 to AMR5 specify the range of address space for chip select areas 1 to 5 Configuration of Area Select Register ASR and Area Mask Register AMR The area select register ASR and area mask register AMR are configured as shown below Area select registers ASR1 to ASR5 ASR1 Address 0000060CH A31 A30 A29 ASR2 Address 00000610 A31 A30 A29 ASR3 Address 00000614 A31 A30 A29 ASR4 Address 00000618 A31 A30 A29 ASR5 Address 0000061 A31 A30 A29 Address 0000060 A31 A30 A29 AMR2 Address 000006124 A31 A30 A29 Address 000006164 A31 A30 A29 Address 0000061
180. RMOVE DEST SRC DEST c SRC c DEST i SRC i void main void STRMOVE little_st normal_st Moreover as the member allocation for a structure is different for each compiler it may differ from that of another compiler In this a case the correct result cannot be acquired When the member allocations for structures differ do not allocate the corresponding structure variables to a little endian area Manipulating Data Other Than Character Arrays with a Character String Manipulation Function Character string manipulation functions provided by standard libraries perform processing in byte units Therefore the character string manipulation function does not produce the correct results for variables of types other than char unsigned char and signed char which are allocated to little endian areas Do not perform such operations Example of incorrect processing Transfer of word data by memcpy int big 0x01020304 Big endian area extern int little Little endian area memopy amp little amp big 4 Transfer by memcpy The result of the above transfer is rendered incorrect by word data transfer as follows Big endian area Little endian area cm e Te Te Is B Specifying the Option K Lib when Using a Character String Manipulation Function When the K lib option is specified the compiler performs inline expansion for various character string manipulation functions In this case these functions may employ p
181. RVIEW Table 1 5 2 Pin Functions 2 5 Pin name 1 O circuit Function format 47 WR1X P85 F re bitbas wath aitous wan mode be used as a port be used as a port Note WR1X is Hi Z while it is in reset state When it is used as a 16 bit bus attach a pull up resistor to the outside P84 or P85 When WROX or WR1X is not used the pin can be used as a general purpose port 48 CSOX PAO F Chip Select 0 output Low active 49 CS1X PA1 Chip Select 1 output Low active 50 CS2X PA2 Chip Select 2 output Low active PAO 1 or 2 When the pin is not used for the above purpose it can be used as a general purpose port 51 CS3X PA3 EOP1 F Chip Select 3 output Low active EOP1 DMAC EOP 1 output ch1 This function is valid when DMAC EOP output is enabled When CS3X and are not used the can be used as a general purpose I O port 52 CS4X PA4 F Chip Select 4 output Low active 53 CS5X PA5 Chip Select 5 output Low active PA4 or 5 When the pin is not used for the above purpose it can be used as a general purpose port 54 CLK PA6 F System clock output The pin outputs the same clock frequency as the external bus operating frequency PA6 When the pin is not used for this purpose it can be used as a general purpose I O port Table 1 5 3 Pin Functions 3 5 Pin name RASO PBO CSOL PB1 CSOH PB2 DWOX PBS3 RAS1 PBA EOP2 CS1L P
182. Request Cancel Request Function HRCR When the CPU is to perform priority processing during DMA transfer the DMA side must cancel the hold request and release the CPU from the hold state An example of an interrupt occurring for DMA to cancel the hold request and allow CPU priority operation is as follows B Control Registers O Hold request cancel request level register HRCL This module When an interrupt having a level higher than that set in the HRCL register occurs a hold request cancel request is issued to DMA Set the reference level for this operation O Interrupt control register ICR This module Set a level higher than that set in the HRCL register in the ICR corresponding to the interrupt cause used O Postpone DMA request register PDRR Clock controller The PDRR is used to temporarily suppress a hold request from DMA and prevent the CPU from returning to the hold state when the interrupt cause is cleared A hold request from DMA is transmitted to the CPU only when the value of this register is 0000g Increment the value of this register at the beginning of the interrupt routine and decrement it at the exit of the routine B Hardware Configuration A signal stream is shown below Figure 8 8 1 Example of Hardware Configuration for Using the Hold Request Cancel Request Function This module Clock controller DHRQ DMA hold request HRQ Hold request IRQ Interrupt request HRCR Hold request cancel request IR
183. SCR and CCR The undefined bits are all reserved When the register is read 0 is always read from these bits No data can be written to this register Program Status Register PS The configuration of the program status register PS is shown below 31 20 16 10 87 0 ILM SCR CCR O Condition code register CCR The configuration of the condition code register CCR is shown below 7 6 5 4 3 2 1 0 Initial value 15 2 00 bit 5 S Stack flag This bit specifies the stack pointer used as R15 0 Uses SSP as R15 The bit is automatically set to 0 when EIT occurs 1 Uses USP as R15 This bit is cleared to 0 by resetting Set the bit to 0 when the RETI instruction is executed bit 4 I Interrupt enable flag This bit enables or disables a user interrupt request 0 Disables user interrupts The bit is cleared to 0 when the INT instruction is executed The value before the bit is cleared is saved to the stack 1 Enables user interrupts The masking of user interrupt requests is controlled by the value held in the ILM This bit is cleared to 0 by resetting 39 CHAPTER 2 CPU bit 3 N Negative flag This bit indicates a sign applicable when the operation result is assumed to be an integer that is represented in two s complement 0 Indicates that the operation result is a positive value 1 Indicates that the opera
184. SMR SCKE 0 pin values are input to SCO during operation 1 SCO output PF3 SH TRG2 Pin values are always input 511 and TRG2 during operation PFA TRG3 SMR SOE 0 PF4 1 S01 output Pin values are always input to TRG3 during operation PF5 SI2 PCNL POEN 0 PF5 1 1 Pin values are always input to SI2 during operation PCNL POEN 0 PF5 1 OPCA2 SMR SOE 0 PF6 1 502 output PCNL POEN 0 PF6 1 OPCA2 208 5 4 Using External Pins as I O Ports Table 5 4 4 External Bus Functions to be Selected 4 4 Pin code Initial value Switch over register 74 17 95 94 7 16 96 46 18 43 68 93 209 CHAPTER 5 I O PORTS 210 CHAPTER6 EXTERNAL INTERRUPT NMI CONTROLLER This chapter explains the general outlines of the external interrupt NMI controller configuration functions of registers and operations of the external interrupt NMI controller 6 1 Overview of External Interrupt NMI Controller 6 2 Enable Interrupt Request Register ENIR 6 3 External Interrupt Request Register EIRR 6 4 External Level Register ELVR 6 5 External Interrupt Operation 6 6 External Interrupt Request Levels 6 7 Nonmaskable Interrupt NMI Operation 211 CHAPTER 6 EXTERNAL INTERRUPT NMI CONTROLLER 61 Overview of External Interrupt NMI Controller The external interrupt NMI
185. Sector erase timer Sector erase operation status After execution of the Sector Erase command sequence a sector erase wait period is entered Bit is 0 in this state and becomes 1 if the limit of the sector erase wait period is exceeded The data polling and toggle bits become valid after the execution of the first Ease Sector command sequence 16 7 Execution Status of the Automatic Algorithm Suppose that the data polling and toggle bit functions indicate that the erase algorithm is running If this flag is 1 in this case an internally controlled erase operation has started and succeeding command entries are ignored until the data polling or toggle bit indicates the end of the erase operation Only the input of a temporary erase stop code is accepted When this flag is 1 flash memory accepts another sector erase code entry In this case it is recommended to check the status of this flag by software before writing the succeeding sector erase code If this flag is 1 at the second time of status check the additional sector erase code may not be accepted When a read operation is performed during a temporary sector erase stop operation flash memory outputs 1 if the address indicated by the address signal is included in the sector that is subject to the erase operation If the address is not included in the sector that is subject to the erase operation flash memory outputs the data of bit 3 of the read value at the address indi
186. Status in 8 bit External Bus Mode Continued Pin name Function During sleep During stop Bus release Reset time BGRNT HIZX 0 HIZX 1 SCo Previous status Previous status Output Hi Z Previous status Output Hi Z OCPA3 retained retained Input fixed to 0 retained Input allowed for SH TRG2 all pins 501 TRG3 512 1 502 2 ATGX P when a general purpose port is specified F when the specified function is selected 1 Selfrefresh status is entered at selfrefresh start time When selfrefresh is cleared the previous value is retained 2 Handled when DRAM pin is set 392 Table C 5 Pin Status in Single Chip Mode Pin name Function During sleep APPENDIX C Pin Status for Each CPU Status During stop HIZX 0 HIZX 1 Reset time P20 to P27 Port Previous status retained P30 to P37 P40 to P47 P50 to P57 P60 to P67 P70 EOPO P Previous status retained F EOP output P80 Port Previous status retained P81 P82 P83 P84 P85 PAO PA1 to PA2 1 Previous status retained F EOP output PA4 to Port Previous status PA5 retained PA6 PBO PB1 PB2 PB3 PB4 EOP2 P Previous status retained F EOP output Previous status retained Output Hi Z Input fixed to 0 Output Hi Z Input allowed for all pins 393 APPENDIX C Pin Status for Each CPU S
187. Transfer data size byte 8bit Address increment decrement unit plus or minus 1 byte halfword 16bit plus or minus 2 byte word 32bit plus or minus 4 byte bits 3 2 WS1 WSO These bits specify the size of data to be transferred Table 15 5 3 Specification of Transfer Data Size Transfer data size byte halfword word Reserved 333 CHAPTER 15 DMAC bits 1 0 MOD1 MODO Transfer mode These bits specify the transfer mode Table 15 5 4 Transfer Mode Specification Operation mode Single block mode Burst mode Continuos transfer mode Reserved The continuous transfer mode can be used for channels 0 to 2 only Second Word of a Descriptor 31 0 SADR R W The second word contains the transfer source address The address is updated at every transfer operation based on the address update mode specified by the SCS1 and SCSO bits When the transfer data size is halfword specify an address consisting of a multiple of two When the transfer data size is a word specify an address consisting of a multiple of four B Third Word of a Descriptor 31 0 DADR R W The third word contains the transfer destination address The address is updated at every transfer operation based on the address update mode specified by the DCS1 and DCSO bits When the transfer data size is a halfword specify an address consisting of a multiple of two When the tran
188. Type A D Converter Block Diagram Figure 11 1 2 is an A D converter block diagram Figure 11 1 2 Block Diagram of the A D Converter AVR AVSS Internal voltage MPX generator ANO gt 2 _ 2 Successive AN3 gt 2 approximation 3 register B U I S Sample amp hold circuit Data register m 8 ADCR A D control register gt Trigger activation ADCS ATGX Timer activation TIMO internal connection Operating clock Reload timer channel 2 gt Prescaler Peripheral clock 269 CHAPTER 11 A D CONVERTER Successive approximation type 11 2 Control Status Register ADCS The control status register ADCS controls the A D converter and displays status information Do not rewrite the ADCS during A D conversion Do not use a Read Modify Write RMW instruction to access it Configuration of Control Status Register ADCS ADCS 15 14 13 12 11 10 9 8 0 0 0 0 The configuration of the control status register ADCS is shown below bit 0 0 0 0 Initial value RW RW RW RW RW RW R W lt Bit attribute P OS 560 xA 24002 ANS2 ANS1 ANSO 2 1 ANEO o 0 0 0 0 0 Initial value RW RW RW RW RW RW RW RW Bitattribute bit Bit Function of Con
189. WROX D23 to D16 are unused O Data bus widths and control signals in DRAM interface Figure 4 16 2 Data Bus Widths and Control Signals in DRAM Interface 16 bit bus width Data bus Control signal D31 CASL WEL CASH WEH D16 8 bit bus width Data bus AE D24 Control signal CAS WE D23 to D16 are unused Table 4 16 1 outlines the bus widths and control signals 139 CHAPTER 4 BUS INTERFACE Table 4 16 1 Relationship between Data Bus Widths and Control Signals Bus width 16 bit bus width 8 bit bus width Data bus 2CAS 1WE 1CAS 2WE 2CAS 1WE 1CAS 2WE D31 D24 D23 D16 140 4 16 Relationship between Data Bus Widths and Control Signals 4 16 1 Bus Access with Big Endians When external bus access is performed for areas not set by the little endian register LER those areas are handled as big endians The FR series usually employs big endians E Data Format The following shows the relationship between the internal register and external data bus for each data format O Word access during execution of LD and ST instructions Figure 4 16 3 Relationship between Internal Register and External Data Bus for Word Access Internal register External bus D31 D31 CC D23 D2 D15 Ms D07 O Half word access during execution of LDUH and STH instructions Figure 4 16 4 Relationship between Internal Register and External Data Bus for Half Word Access Internal r
190. When the written data is loaded to the transmission shifter and transmission begins the bit is set again to indicate that the next instance of transmission data can be written 0 Transmission data cannot be written 1 Transmission data can be written Initial value bit 2 reserved bit 1 RIE Receiver Interrupt Enable This bit controls receiver interrupts 0 Disable interrupts Initial value 1 Enable interrupts lt Note gt The causes of receiver interrupts include indication of normal data reception by RDRF in addition to the errors indicated by PE ORE and FRE bit 0 TIE Transmitter Interrupt Enable This bit controls transmitter interrupts 0 Disable interrupts Initial value 1 Enable interrupts lt Note gt Transmitter interrupts are caused by indicating transmission requests by TDRE 10 6 UART Operation 10 6 UART Operation UART has the following three operation modes which can be changed by setting a value in the SMR or SCR register e Asynchronous start stop normal mode e Asynchronous start stop multiprocessor mode CLK synchronous mode UART Operation Modes Table 10 6 1 summarizes the UART operation modes Stop bit length in asynchronous start stop mode can be specified only for transmission Stop bit length for data reception is always 1 bit The UART does not operate in a mode other than those listed below Table 10 6 1 UART Operation Modes Data length Operation m
191. X X X D31 24 X X X 2 xX D23 16 Y 1 X X 3 X WROX 3 7 Bus width 16 bits access bytes Figure 4 17 10 Example 3 of Write Cycle Timing Chart 1 BA2 BAI BA2 1 BA2 BAI BA j ro A24 00 0 j 1 j 2 j 3 031 24 X 0 X X X X A 2 X A X X D23 16 Y X A 1 X x X 3 WROX WRIX piss X Invalid data input 168 O Bus width 8 bits access half words Figure 4 17 11 Example 4 of Write Cycle Timing Chart 4 17 Bus Timing BA1 2 1 2 BAM 2 1 2 211 L A24 00 X 0 X X X 2 X 343 X 031 24 X 0 X X Xx 2 _ X D23 16 WROX Lo To boo T o ND WR1X O Bus width 8 bits access bytes Figure 4 17 12 Example 5 of Write Cycle Timing Chart BA 2 BA1 BA2 BAM BA2 BAM BA CK A24 00 X 0 X Y 1 Y Y 2 Y Y 3 Y 031 24 X 0 1 2 A A 3 X D23 16 WROX S P WR1X 169 CHAPTER 4 BUS INTERFACE 4 17 5 Read and Write Combination Cycles This section provides a read and write combination cycle timing chart
192. X iH X 3 X RAS CASL CASH WE RDX CS4X DACKO 2 X N 1 1 gt Half word access Half word access of upper address side lower address side Explanation of operation The output of A24 to 00 address 24 to address 00 is similar to that at read cycles D31 to D16 data 31 to data 16 represent write data to external memory and I O In write cycles write data is output from the Q1 cycle and set to High Z when the Q5 cycle ends For the 1CAS 2WE valid data is output while WEL corresponds to D31 to D24 and WEH corresponds toD23 to D16 For the 2CAS 1WE valid data is output while WE corresponds to D31 to D16 175 CHAPTER 4 BUS INTERFACE 176 In an 8 bit data bus width write data is output from D31 to D24 RAS is similar to that at read cycles CAS is also similar to that at read cycles WE is a write strobe signal to the DRAM For the 1CAS 2WE WEL represents WE of the upper address side 0 of lower 1 bit WEH represents WE of the lower address side 1 of lower 1 bit This signal is output in write cycles asserted at the rising edge of Q4 and negated at the rising edge of the cycle next to Q5 In write cycles RDX stays
193. abel9 BGE D label9 BLE D label9 BGT D label9 BLS D label9 BHI D label9 Theory of Operation of Branch Instructions with Delay Slots 48 A branch instruction causes the program to branch and execute the instruction at the branch destination after the instruction called the delay slot placed immediately after the branch instruction is executed Since a delay slot instruction is executed before branching the execution speed seems one cycle However when a valid instruction cannot be put at the delay slot the NOP instruction must be provided Example Instruction list ADD R1 R2 BRA D LABEL Branch instruction MOV R2 R3 Delayed slot Executed before branching LABEL ST R3 R4 Branch destination For a conditional branch instruction the instruction placed at the delay slot is executed whether the branch condition is satisfied or not For delayed branch instructions the execution order of some instructions seems to be reversed This is only applicable to PC updating Other operations such as register updating and referencing are executed in order of coding Concrete examples are shown below 2 7 Instruction Overview Ri that is referenced by the JMP D Ri CALL D Ghi instruction is not affected even when the instruction in the delay slot updates the Ri Example LDI 32 Label RO JMP D RO Branches to Label LDI 8 0 RO Does not affect the branch destination address O RP that is ref
194. after reset No little endian area exists Area 1 is handled as a little endian Areas 0 and 2 to 5 are handled as big endians Area 2 is handled as a little endian Areas 0 to 1 and 3 to 5 are handled as big endians Area 3 is handled as a little endian Areas 0 to 2 and 4 to 5 are handled as big endians Area 4 is handled as a little endian Areas 0 to 3 and 5 are handled as big endians Area 5 is handled as a little endian Areas 0 to 4 are handled as big endians lt Note gt Writing to the LER register can be performed only one time after it is reset 138 4 16 Relationship between Data Bus Widths and Control Signals 4 16 Relationship between Data Bus Widths and Control Signals Data bus control signals WROX WR1X CSOH CSOL CS1L CS1H DWOX and DW1X always correspond to data bus byte locations on a one to one basis regardless of big and little endians and data bus widths Relationship between Data Bus Widths and Control Signals The following outlines the byte locations of the data buses of this part number used in the specified data bus width and the control signals corresponding to those locations for each bus mode O Data bus widths and control signals for usual bus interface Figure 4 16 1 Data bus Widths and Control Signals in Usual Bus Interface 16 bit bus width Data bus Control signal D31 WROX WR1X D16 8 bit bus width Data bus Control signal 2 D24
195. ancel Request is Issued 235 Selection of UART Operation Modes 248 VART Operation Modes 255 Baud Rates and U TIMER Reload Values in Asynchronous Start Stop Mode 265 Baud Rates and U TIMER Reload Values CLK Synchronous Mode 265 Selecting the Causes for Starting the A D Converter 2 271 Selecting the A D Converter Operation Mode 272 Setting the A D Conversion Start Channel 2 2 2 4 2 273 Setting the A D Conversion End Channel 273 CSL Bit Setting Clock 284 Bit Positions and Returned Values 296 Selection of the Count Clock 305 PWM Output When 1 is Written to PGMS 305 Selection of Trigger Input Edge nennen nnns 305 Selection of Interrupt Causes enne nennen 306 Specification of the Polarity of the PWM Output and the Edge 306 Selection of Ch3 Trigger Input sse enne nennen nennen 312 Selection of Ch2 Trigger Input
196. anch instruction having the delay slot O Interrupt NMI No interrupt NMI is accepted between the delay slot and the execution of the branch instruction having the delay slot O Undefined instruction exception Even if an undefined instruction is placed in the delay slot no undefined instruction exception occurs The undefined instruction works as the NOP instruction 2 7 Instruction Overview 2 7 2 Branch Instructions without Delay Slots Instructions including branch instructions without delay slots are executed in order of coding Branch Instructions Without Delay Slots The instructions represented as follows execute branching without delay slots JMP Ri CALL label12 Ri RET BRA label9 BNO label9 BEQ label9 BNE label9 BC label9 BNC label9 BN label9 BP label9 BV label9 BNV label9 BLT label9 BGE label9 BLE label9 BGT label9 BLS label9 BHI label9 B Theory of Operation of Branch Instructions Without Delay Slots Instructions including branch instructions without delay slots are executed in order of coding The instruction provided immediately before the branch instruction is not executed before branching Example Instruction list ADD R1 R2 i BRA LABEL Branch instruction without a delay slot MOV R2 R3 Not executed LABEL ST R3 R4 Branch destination The number of execution cycles for a branch instruction without a delay slot is two cycles when it involves branching or one cycle when it does no
197. and their timing B Interrupt Figure 14 11 1 Causes of Interrupts and Their Timing PWM Output Normal Polarity Start trigger Upto2 5T Load Clock Count value X 0003 0002 0001 0000 0003 PWM A A Interrupt Effective edge Duty cycle matching Counter borrow A maximum of 2 5T T count clock cycle is required until the count value is loaded after detection of a start trigger 319 CHAPTER 14 PWM TIMER 14 12 Constant L or Constant Output from PWM Timer Figure 14 12 1 shows how the PWM timer can keep output at a low level Figure 14 12 2 shows how the PWM timer can keep output at a high level Constant L or Constant Output from PWM Timer O Example of keeping PWM output at a lower level Figure 14 12 1 Example of Keeping PWM Output at a Lower Level PWM i i i Decrease the duty An interrupt generated by a borrow causes 1 to be written to value gradually PGMS mask bit If an interrupt generated by borrow causes 0 to be written to PGMS mask bit PWM waveforms can be output with no whisker O Example of keeping PWM output at a high level Figure 14 12 2 Example of Keeping PWM Output at a High Level PWM Increase the duty value gradually gt 320 Dc An interrupt generated by a compare match causes the same
198. ard architecture in which the instruction bus and data bus are independent of each other The bus controller that controls the external bus has Princeton architecture consisting of a single bus The bus converter gives priority to the instruction and data accesses of the CPU to control accesses to the bus controller This control always optimizes the order of access to the external bus The bus converter has a two word write buffer to eliminate the CPU s bus wait time and a one word prefetch buffer for instruction fetch 2 3 Programming Model 2 3 Programming Model This section explains the CPU registers that are essential for programming The CPU registers are classified into the following two groups e General purpose registers Special registers General Purpose Registers Figure 2 3 1 shows the configuration of general purpose registers Figure 2 3 1 Configuration of general purpose registers 32 bits Initial value RO 3000000064 R1 R12 R13 A R14 F 3000000004 R 15 S P 0000 00004 B Special Registers Figure 2 3 2 shows the configuration of special registers 33 CHAPTER 2 CPU Figure 2 3 2 Configuration of special registers 32 bits Program counter PC Program status PS ILM SCR CCR Table base register TBR Return pointer RP System stack pointer SSP User stack pointer USP MDH Multiplication div
199. are indicates the address space as 0 When it is 1 care indicates the address space as 1 Don t care indicates the address space for both 0 and 1 that is irrespective of the value set in the ASR The following is an example of specifying each chip select area by combination of the ASR and AMR Example 1 When ASR1 00000000 00000011 and AMR1 00000000 00000000 are set the AMR1 bits corresponding to the ASR bits that are set to 1 0 and the address space of area 1 becomes 64 kilobytes as shown below 00000000 00000011 00000000 000000006 00030000 to 00000000 00000011 11111111 111111116 0003FFFF j Example 2 When ASR2 00001111 111111118 and AMR2 00000000 000000116 are set the ASR2 bits corresponding to the AMR2 bits that are set to 0 are 1 and O to indicate care while the ASR2 bits corresponding to the 2 bits that are set to 1 are 0 or 1 to indicate don t care Therefore the address space of area 2 becomes 256 kilobytes as shown below 00001111 11111100 00000000 00000000g 0000 to 00001111 11111111 11111111 111111116 OFFFFFFF j The address space of each of areas 1 to 5 can be optionally located in at least 64 kilobytes in a 4 gigabyte space using ASR1 to ASR5 and AMR1 to AMR5 When the area specified by these registers is accessed via the bus the corresponding chip select pins CSOX to CS5X are handled as L outputs Area 0 is allocat
200. ash memory MBM29LV20OT except for a part of the sector configuration and enables writing with a device external ROM writer When this memory is used as FR CPU internal ROM it becomes possible to read instructions and data in word units 32 bits in addition to features equivalent to the features of the MBH29LV200 This enables high speed device operation Along with this manual refer to the MBM29LV200T 200B 10 12 15 Data Sheet B Outline of Flash Memory The employed flash memory is an internal 254 kilobyte flash memory operated at 3 V The following features are implemented by combining flash memory macros and FR CPU interface circuits O Features for use as CPU memory for storing programs and data Accessibility through 32 bit bus when used as ROM Allowing read write and erase automatic program algorithm by the CPU O Features of a single flash memory product equivalent to MBM29LV200T Allowing read or write automatic program algorithm aly by a ROM writer 1 Automatic program algorithm embedded algorithm B Flash Memory Registers Figure 16 1 1 shows the flash memory register Figure 16 1 1 Flash Memory Registers bit 7 0 0007 0 FSTR Flash memory status register 352 16 1 Outline of Flash Memory Execution Status of the Automatic Algorithm When the automatic algorithm is started in CPU programming mode its operation status can be checked with the internal Busy or Ready signal RDY BUSYX The leve
201. at H CS4X and CS5X are output from the rising edge of the Q1 cycle DACKO to DACK2 and EOPO to EOP2 are output in external bus cycles Whether to output these signals is determined by settings in the DMAC register The output time is the same as CAS 4 17 Bus Timing 4 17 10 Usual DRAM Read Cycles This section provides usual DRAM read cycle timing charts Usual DRAM Read Cycle Timing Charts O Bus width 16 bits access half words Figure 4 17 18 Example 1 of Usual DRAM Read Cycle Timing Chart Qi Q2 04 Q5 CLK 1 1CAS 2WE A24 00 X X X40 row adr X 0 col adr X D31 24 _ 023 16 GH RAS MW CAS WEL WEH 2 2CASAWE A24 00 X X 0 row adr X 0 col adr X D31 24 _ D23 16 Gn RAS MW CASL CASH WE 177 CHAPTER 4 BUS INTERFACE O Bus width 16 bits access bytes Figure 4 17 19 Example 2 of Usual DRAM Read Cycle Timing Chart Qi Q2 Q3 Q4 Q5 Q1 Q2 QS Q4 Q5 1 1CAS 2WE A24 00 X X X40 rowad X col adr X X rowadr X 1 col adr X D31 24 Ho gt XXL D23 16 AX Ue nes RAS 271 CAS WEL WEH 2 2CAS 1WE A24 00 X X X40 rowad X 0 col adr X X 4 rowadr X 1 col adr X D31 24 HO AK E D23 1
202. ation Modes 276 In single conversion mode the A D converter sequentially converts the analog inputs specified by the ANS and ANE bits of the ADCS register and stops operation after converting the analog input from the end channel specified by the ANE bits If the start and end channels are the same ANS ANE the analog input from only one channel is converted Single conversion mode In single mode analog input set by the ANS bit and ANE bit of ADCS is converted in order When the conversion of the end channel set by the ANE bit is completed the A D converter stops its operation If the start channel and the end channel are the same ANS ANE one channel conversion is adopted Example ANS 000 ANE 011 Start gt ANO gt AN1 gt AN2 gt AN3 gt End ANS 010 ANE 010 Start gt AN2 gt End Continuous conversion mode In continuous conversion mode the A D converter sequentially converts the analog inputs specified by the ANS and ANE bits of the ADCS register When conversion is finished up to the end channel specified by the ANE bits the converter returns to the ANS analog input and continues A D conversion If the start and end channels are the same ANS ANE conversion of the analog input from only one channel is repeated Example ANS 000 ANE 011 Start gt gt AN1 gt AN2 gt AN3 gt ANO gt iteration ANS 010 ANE 010 Start gt AN2 gt AN2 g
203. ation clocks When gear control is set the CLK frequency is lowered according to the gear ratio A24 to 00 address 24 to address 00 output the address of the first byte location specified in word half word or byte access in read cycles from the beginning BA1 of bus cycles In the above example word access is performed in a 16 bit bus width Therefore the address lower 2 bits 0 of the upper 16 bits in the word access is output in the first bus cycle and of A24 00 represents the lower 2 bits of an address of D31 16 represents read data byte addresses represents read data fetch times DACKO and represent DMAC bus cycles the address lower 2 bits 2 of the lower 16 bits is output in the second bus cycle D31 to D16 data 31 to data 16 represent read data from external memory and I O In read cycles D31 to D16 are read at the rising edge of RDX In read cycles all data from D31 to D16 is read at the rising edge of RDX regardless of the bus width and word half word and byte access Whether the fetched data is valid is determined inside the chip RDX represents read strobe signals on the external data bus that are asserted at the falling edge of BA1 and negated at the falling edge of BA2 In read cycles WROX and WR1X are negated 4 17 Bus Timing Output of CSOX to CS5X area chip select signals is asserted from the beginning BA1 of bus cycles that is at the same time
204. ayed interrupt Writing 0 clears the cause of the delayed interrupt This bit is the same as the interrupt source flag for general interrupts Clear the bit in the interrupt routine and change the task 222 CHAPTER8 INTERRUPT CONTROLLER This chapter provides an overview of the interrupt controller and explains the register configuration and functions and the operations of the interrupt controller The chapter also explains the hold request cancel request function using examples 8 1 Overview of Interrupt Controller 8 2 Interrupt Controller Block Diagram 8 3 Interrupt Control Register ICR 8 4 Hold Request Cancel Request Level Setting Register HRCL 8 5 Priority Check 8 6 Returning from Standby Mode Stop Sleep 8 7 Hold Request Cancel Request 8 8 Example of Using the Hold Request Cancel Request Function HRCR 223 CHAPTER 8 INTERRUPT CONTROLLER 81 Overview of Interrupt Controller The interrupt controller accepts interrupts and performs arbitration over them B Interrupt Controller Hardware Configuration The interrupt controller consists of the following ICR register Interrupt priority check circuit Interrupt level and number vector generator Hold request cancel request generator B Major Interrupt Controller Functions The major functions of the interrupt controller are as follows 224 Detection of NMl interrupt requests Priority check based on the level or number Transmission of t
205. bit ensure that the RDY bit is set to 1 O Detailed operation One half word 16 bits can be read from the flash memory area in one cycle Depending on the read operation two cycles can be required for reading a half word when 1 wait cycle is included The automatic algorithm can be started by writing a command to flash memory When the automatic algorithm starts data can be written to or erased from flash memory 359 CHAPTER 16 FLASH MEMORY For details on the automatic algorithm see Section 16 6 Starting the Automatic Algorithm O Restrictions Address assignment and endians in this mode differ from those for writing with the ROM writer This mode inhibits reading data in words 32 bits 360 16 6 Starting the Automatic Algorithm 16 6 Starting the Automatic Algorithm For writing data to or erasing data from flash memory start the automatic algorithm stored in flash memory Command Operation Command sequence Read Reset At the start of the automatic algorithm one to six half words 16 bits are written This data is called the command If the address and data to be written are invalid or are written in an incorrect sequence the flash memory is reset to read mode Table 16 6 1 lists the commands of the automatic algorithm Table 16 6 1 Commands Access First write cycle Second write cycle Third write cycle Fourth write or Fifth read cycle Sixth write cycle count read cycle Address
206. bit 17 9 1 EPSEn 15 4 DMAC Pin Control Register DATCR bit 16 8 0 EPDEn These bits specifies the time when the transfer end output signal is to be generated from the corresponding output pin and also specify whether to enable the output function of the corresponding transfer end output signal pin Table 15 4 3 Specification of Transfer End Output Operation control function Disables transfer end output Enables transfer end output Transfer end is output when transfer destination data is accessed Transfer completion output enabled output when accessing the transfer source data access Enables transfer end output Transfer end is output when transfer source and destination data is accessed These bits are initialized to 00 by resetting The bits can be both read and written 331 CHAPTER 15 DMAC 15 5 Descriptor Register in RAM This descriptor register has the setup information for the corresponding channel in DMA transfer mode The descriptor register has a 12 byte area for each channel that is allocated to the memory address specified by DPDP See Table 15 2 1 Channel descriptor addresses for the first address of the descriptor for each channel B First Word of a Descriptor The structure of the first word of a descriptor is shown below 31 16 DMACT R W 15 14 13 12 11 10 9 8 R W 7 6 5 4 3 1 0 R W R W R W 2 50 R W R W R W R W R W Initial value undefined bit
207. bit can be used to check whether operation has actually been changed This model does not support the clock doubler function 82 3 6 Gear Control Register GCR DBLAK Internal external operating frequency Operating at 1 1 Initial value Operating at 2 1 bit 12 DBLON This bit specifies the clock doubler operation mode This bit is initialized by resetting This model does not support the clock doubler function Operating at 1 1 Initial value Operating at 2 1 bit 11 10 PCK1 0 These bits specify the gear cycle of peripherals These bits and the cycles selected by the bits have the relationships shown in Table 3 6 2 These bits are initialized by resetting Table 3 6 2 Peripheral Machine Clock Peripheral machine clock source oscillation input frequency from X0 PLL x1 PLL x 1 2 PLL x 1 4 PLL x 1 8 Source oscillation x 1 2 Source oscillation x 1 2 x 1 2 0 Source oscillation x 1 2 x 1 4 1 1 Source oscillation x 1 2 x 1 8 Initial value PLL PLL oscillation frequency Source oscillation Input frequency from When the CPU clock frequency is higher than 25 MHz set the peripheral clock frequency to less than half of the CPU clock frequency The maximum peripheral clock frequency is 25 MHz Note To change both the CPU and peripheral gears temporarily set both systems to the same gear and then set each system to a desired gear W
208. bit selects the polarity of PWM output This bit can be combined with bit 9 PGMS as shown below Table 14 3 5 Specification of the Polarity of the PWM Output and the Edge PWM output Normal polarity Initial value Inverse polarity Output fixed to L Output fixed to H 14 3 Control Status Register PCNH PCNL Polarity After Duty cycle matching resetting Counter borrow Normal Output of L polarity Inverse Output of H polarity 307 CHAPTER 14 PWM TIMER 14 4 PWM Cycle Setting Register PCSR The PWM cycle setting register PCSR is used to set a cycle This register has a buffer A borrow occurring in the counter triggers a transfer from the buffer PWM Cycle Setting Register PCSR 308 The configuration of the PWM cycle setting register PCSR is shown below PCSR bit 15 14 13 12 11 10 9 8 Address chO 0000 2 ch2 0000 2 ch3 0000 7 6 5 4 3 2 1 0 Attribute Write only Initial value Undefined After the cycle setting register is initialized or rewritten write to the duty cycle setting register Use a 16 bit data instruction to access the cycle setting register 14 5 PWM Duty Cycle Setting Register PDUT 14 5 PWM Duty Cycle Setting Register PDUT The PWM duty cycle setting register PDUT is used to set a duty cycle This register has a buffer A borrow occurring in the counter triggers a transfer from the buffer PWM Dut
209. cade Mode U TIMER channels 0 and 1 can be used in cascade mode Figure 9 3 1 shows an example of cascade mode in which UTIMR channel 0 is set to 0100 and UTIMR channel 1 is set to 0002 Figure 9 3 1 Example of Using U TIMER Channels 0 and 1 in Cascade Mode LILILILTLILJILILILILILJILILILILILILI LI UTIM ch 1 01 X 00 X 02 X 01 X 00 X 02 X 01 X 00 X 02 X 01 X 00 X 02 X 01 X 00 X 02 X 01 X 00 X 02 X 01 X 00 X Jc recep UTIM 0002 X 0001 X 0000 X 0100 f f 0 243 CHAPTER 9 U TIMER 244 CHAPTER 10 UART This chapter provides an overview of the UART and explains the register configuration functions and the operations of the UART 10 1 Overview of UART 10 2 Serial Mode Register SMR 10 3 Serial Control Register SCR 10 4 Serial Input Data Register SIDR and Serial Output Data Register SODR 10 5 Serial Status Register SSR 10 6 UART Operation 10 7 Asynchronous Start Stop Mode 10 8 CLK Synchronous Mode 10 9 UART Interrupt Occurrence and Flag Setting Timing 10 10 Notes on Using the UART and Example for Using the UART 10 11 Setting Examples of Baud Rates and U TIMER Reload Values 245 CHAPTER 10 UART 10 1 Overview of UART The UART is a serial I O port used to implement asynchronous start stop communication or CLK synchronous communication The MB91F109 contains three UART channels UART Cha
210. cated by the address signal bit 2 TOGGL2 Toggle bit Sector erase operation status Together with toggle bit 6 this toggle bit is used to indicate whether flash memory is subject to automatic erase operation or temporary erase stop operation If data is read consecutively from a sector that is subject to erasing during an automatic erase operation bit 2 toggles If data is consecutively read from a sector that is subject to a temporary erase stop operation when flash memory is in temporary erase stop and read mode bit 2 toggles also If addresses are read consecutively from a sector not subject to a temporary erase stop operation when flash memory is in temporary erase stop and write mode bit 2 becomes 1 Unlike bit 2 bit 6 toggles only in usual write and erase or temporary erase stop and write operations For example bit 2 and bit 6 are used together to detect a temporary erase stop and read mode bit 2 toggles but bit 6 does not Bit 2 is also used to detect sectors that are subject to erase operations If data is read from a sector that is subject to an erase operation for the flash memory bit 2 toggles 367 CHAPTER 16 FLASH MEMORY 368 APPENDIX The appendices provide more details and programming references concerning the I O maps interrupt vectors pin statuses in CPU states precautions on using the little endian area and instructions A Maps B Interrupt Vectors C Pin Status for Each CPU Status
211. ceeding as above 297 CHAPTER 13 BIT SEARCH MODULE 298 CHAPTER 14 PWM This chapter provides an overview of the PWM timer and explains the register configuration and functions and the operations of the PWM timer 14 1 Overview of PWM Timer 14 2 PWM Timer Block Diagram 14 3 Control Status Register PCNH PCNL 14 4 PWM Cycle Setting Register PCSR 14 5 PWM Duty Cycle Setting Register PDUT 14 6 PWM Timer Register PTMR 14 7 General Control Register 1 GCN1 14 8 General Control Register 2 GCN2 14 9 PWM Operation 14 10 One shot Operation 14 11 Interrupts 14 12 Constant L or Constant Output from PWM Timer 14 13 Starting Multiple PWM Timer Channels 299 CHAPTER 14 PWM TIMER 14 1 Overview of PWM Timer The PWM timer can efficiently output accurate PWM waveforms The MB91F109 contains four channels of PWM timer Each channel consists of a 16 bit counter a 16 bit data register with a cycle setting buffer a 16 bit compare register with a duty cycle setting buffer and a pin controller Characteristics of PWM Timer 300 The count clock for the 16 bit counter can be selected from the following four types Internal clock 6 4 6 16 6 64 The counter value can be initialized to FFFFj by resetting or a counter borrow PWM output is enabled through each channel Registers Cycle setting register Data register for reloading containing a buffer Duty cycle setting regist
212. channel 2 and then channel 3 These bits are initialized to 000 when the register is reset 274 11 3 Data Register ADCR 11 3 Data Register ADCR The data register ADCR is used to store a digital value that is the conversion result Configuration of Data Register ADCR The configuration of the data register ADCR is shown below bit 15 14 11 10 13 12 9 8 ADCR Mies 9 8 0 0 0 0 0 0 X X lt hlnitial value R R R R R R R R lt Bitattribute bit 7 6 5 4 3 2 1 0 x ae X X X X X X X X lt Initial value R R R R R R R R lt Bitattribute The value stored in this register is updated whenever one cycle of conversion is completed Normally the value converted last is stored The value of this register is undefined when the register is reset Reading the high order bits 10 to 15 results in 0 The conversion data protection function is supported See Section 11 5 Conversion Data Protection Function for this function 275 CHAPTER 11 A D CONVERTER Successive approximation type 11 4 A D Converter Operation The A D converter operates in successive approximation mode and features a 10 bit resolution The A D converter has only one register 16 bits to store the conversion results Therefore the data register ADCR is updated whenever conversion is completed For performing continuous conversion DMA transfer should be used A D Converter Oper
213. ck transfer mode DMA transfer is performed twice for a single DREQ In continuous transfer mode DMA transfer is performed even if DREQ is canceled To prevent this select one of the following countermeasures Use DREQs in edge detection mode valid in block mode only Setthe transfer destination address in the external area to generate a DACK during access to the transfer destination Set descriptors in external memory unless both transfer source and destination addresses are fixed 341 CHAPTER 15 DMAC 15 9 DMAC Timing Charts This section provides the following DMAC timing charts Timing charts for the descriptor access block e Timing charts for the data transfer block e Transfer stop timing charts in continuous transfer mode Transfer termination timing charts Codes Used in the Timing Charts Table 15 9 1 Codes Used in the Timing Charts Meaning Descriptor No 0 Bit 31 to bit 16 of descriptor No 0 Bit 15 to bit 0 of descriptor No 0 Descriptor No 1 Bit 31 to bit 16 of descriptor No 1 Bit 15 to bit 0 of descriptor No 1 Descriptor No 2 Bit 31 to bit 16 of descriptor No 2 Bit 15 to bit 0 of descriptor No 2 Descriptor No 1 or No 2 determined by SCS1 and SCSO and DCS1 and 50 Bits 31 to 16 of Descriptor No 1 or 2 Bit 15 to bit 0 of descriptor No 1 or No 2 Transfer source Bits 31 to 16 of transfer source Bits 15 to 0
214. controller is a block that controls an external interrupt request input to NMIX or INTO to INT3 The levels of interrupt requests to be detected can be selected from H L and the rising and falling edges excluding NMI B External Interrupt NMI Controller Registers Figure 6 1 1 shows the external interrupt NMI controller registers Figure 6 1 1 External Interrupt NMI Controller Registers bit 7 6 5 4 3 2 1 0 EN6 ENS EN3 EN2 ENO an interrupt request register bit 15 14 18 12 11 10 9 8 ER7 ER6 ERS ER4 2 ER1 ERO im interrupt request register bit 7 6 5 4 3 2 1 0 LB3 LB2 LA2 LB1 LA1 LBO LAO External level register ELVR B External Interrupt NMI Controller Block Diagram Figure 6 1 2 is an external interrupt NMI controller block diagram Figure 6 1 2 External Interrupt NMI Controller Block Diagram R BUS 9 gt Enable interrupt request register Interrupt 9 Edge detection 5 request L 9 Gate 4 5 zu F F cireuit ee INTO to 3 NMIX lt _ 8 s External interrupt request register External level register 212 6 2 Enable Interrupt Request Register ENIR 6 2 Enable Interrupt Request Register The enable interrupt request register ENIR is used to mask the output of an external interrupt request B Enable Int
215. converter 1 Restarting the A D converter in stopped state may lead to loss of the stored conversion data 279 CHAPTER 11 A D CONVERTER Successive approximation type 11 6 Notes on Using the A D Converter This section provides notes on using the A D converter Notes on Using the A D Converter O Using an external trigger or internal timer to start the A D converter The A D start cause bits STS1 and STSO of the ADCS register specify whether an external trigger or the internal timer is used to start the A D converter In this case set the external trigger or internal timer input value at the inactive side Setting it on the active side causes malfunction When setting STS1 and STSO set the ATGX and reload timer as follows ATGX 1 input and reload timer channel 2 0 output Other Notes on Using the A D Converter If the external impedance is higher than the specified value analog input values cannot be sampled within the specified sampling time and accordingly normal conversion results cannot be obtained 280 CHAPTER 12 16 BIT RELOAD TIMER This chapter provides an overview of the 16 bit reload timer and explains the register configuration and functions and operations of the 16 bit reload timer 12 1 Overview of 16 Bit Reload Timer 12 2 Control Status Register TMCSR 12 3 16 Bit Timer Register TMR and 16 bit Reload Register TMRLR 12 4 Operation of 16 Bit Reload Timer 12 5 Count
216. corresponding column address is output After a read cycle ends at least one idle clock cycle is inserted so as to prevent conflicts between the external data buses DACKO to DACK2 and EOPO to EOP2 are output at the same time as CAS 4 17 Bus Timing 4 17 18 Hyper DRAM Interface Write This section provides a hyper DRAM interface write timing chart Hyper DRAM Interface Write Timing chart O Bus width 16 bits access words Figure 4 17 33 Example of Hyper DRAM Interface Write Timing Chart Q1 Q2 Q3 Q4HW Q4HW Q4HW Q4HW Q1 Q2 Q3 Q4HW CLK 2 2CASAWE A24 00 X X X row adr Xco Xco Xco X X X rowad Xco X D31 24 X XW XW x X D23 16 X w XW XW XW X w X RAS d E Es 53 CASL CASH 7 WE i i RDX Dacko EOPO l 1 1 1 r r 1 1 Explanation of operation Column addresses and write data are output in Q4HW cycles CAS is asserted at the falling edge of Q4HW and negated at the falling edge of Q4HW WE including WEL and WEH is asserted at the rising edge of the Q4HW cycle and negated when Q4HW ends 189 CHAPTER 4 BUS INTERFACE 4 17 19 Hyper DRAM Interface This section provides a hyper DRAM interface timing chart Hyper DRAM In
217. ction 3 12 Reset source hold circuit 3 13 DMA suppression 3 14 Clock doubler function 3 15 Example of PLL Clock Setting 73 CHAPTER 3 CLOCK GENERATOR AND CONTROLLER 31 Outline of Clock Generator and Controller The clock generator and controller are the modules that have the following functions e CPU clock generation including the gear function Peripheral clock generation including the gear function Reset generation and cause retention e Standby function Suppression of DMA request Built in PLL frequency multiplier circuit Registers of Clock Generator and Controller Figure 3 1 1 shows the registers of the clock generator and controller Figure 3 1 1 Clock Generator and Controller Registers 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 RSRR WTCR STCR PDRR CTBR GCR WPR PCTR 74 Clock Generator and Controller Block Diagram 3 1 Outline of Clock Generator and Controller Figure 3 1 2 is a block diagram of the clock generator and controller Figure 3 1 2 Block Diagram of the Clock Generator and Controller Qcu mz X0 X1 Internal interrupt GCR register Selector circuit 1 1 2 Peripheral E PCTR register Stop sleep controller Internal reset CPU hold permission STCR register gt CPU clock Internal gt Internal bus clock External bus clock clock
218. ctive CNTE 1 Figure 12 4 1 is a counter start and operation timing chart Time T peripheral clock machine cycle is required from when a counter start trigger is input to when the reload register data is loaded to the counter Figure 12 4 1 Counter Start and Operation Timing Count clock Counter ri Reload data x 1 24 X 1 Data loading CNTE register TRG register Underflow Operation An underflow occurs when the counter value changes from 0000 to FFFFy That is an underflow occurs at a count of reload register value 1 If the RELD bit of the control register is 1 when an underflow occurs the value in the reload register is loaded to the counter and the counter continues counting When the RELD bit is 0 the counter stops at FFFFy When an underflow occurs the UF bit of the control register is set and an interrupt request is issued when the INTE bit is 1 Figure 12 4 2 is a timing chart for underflow operation timing 287 CHAPTER 12 16 BIT RELOAD TIMER Figure 12 4 2 Underflow Operation Timing Count clock EN Counter K 0000m X Reload data x 1 X 1 Data loading Underflow setting RELD 1 Count clock Counter x 0000m x Underflow set RELD 0 288 12 5 Counter States 12 5 Counter Stat
219. d Bus Widths of DRAM Control Pins sssssssseeeeneeeeeeneneneen enn 155 Page Size Select Bits e yi te ede de aci D nn tapenade dude vade ea 156 External Bus Functions to be Selected 1 4 sss 205 External Bus Functions to be Selected 2 4 sse 206 External Bus Functions to be Selected 3 4 207 External Bus Functions to be Selected 4 4 sse 209 External Interrupt Request 215 Table 8 3 1 Table 8 5 1 Table 8 5 2 Table 8 7 1 Table 10 2 1 Table 10 6 1 Table 10 11 1 Table 10 11 2 Table 11 2 1 Table 11 2 2 Table 11 2 3 Table 11 2 4 Table 12 2 1 Table 13 3 1 Table 14 3 1 Table 14 3 2 Table 14 3 3 Table 14 3 4 Table 14 3 5 Table 14 7 1 Table 14 7 2 Table 14 7 3 Table 14 7 4 Table 15 2 1 Table 15 4 1 Table 15 4 2 Table 15 4 3 Table 15 5 1 Table 15 5 2 Table 15 5 3 Table 15 5 4 Table 15 9 1 Table 16 4 1 Table 16 6 1 Table 16 7 1 Table A 1 Table A 2 Table A 3 xviii Correspondences between the Interrupt Level Setting Bits and Interrupt Levels 229 Relationships among Interrupt Causes Numbers and Levels 1 2 231 Relationships among Interrupt Causes Numbers and Levels 2 2 232 Settings for the Interrupt Levels for which a Hold Request C
220. d Interrupt Module 220 7 2 Delayed Interrupt Control Register DICR 221 7 3 Operation of Delayed Interrupt Module 222 CHAPTER 8 INTERRUPT CONTROLLER 223 8 1 Overview of Interrupt Controller 224 8 2 Interrupt Controller Block Diagram 227 8 3 Interrupt Control Register ICR 228 8 4 Hold Request Cancel Request Level Setting Register 230 825 Priority 231 8 6 Returning from the Standby Mode Stop Sleep 234 8 7 Hold Request Cancel Request 235 8 8 Example of Using the Hold Request Cancel Request Function 236 CHAPTER 9 239 Overview of TIMER 240 9 2 USTIMER ROgISters re hte Pt 241 0 3 node ex HR via law E 243 CHAPTER 10 UART
221. damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy fire protection and prevention of over current levels and other abnormal operating conditions If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan the prior authorization by Japanese government should be required for export of those products from Japan 1999 FUJITSU LIMITED Printed in Japan How to Read This Manual Description Format of this Manual Major terms used in this manual are explained below Term Meaning 16 bit wide bus used for internal instructions Since the FR series uses an internal Harvard architecture independent buses are used for instructions and data A bus converter is connected to the I BUS Internal 32 bit wide data bus Internal resources are connected to the D BUS Internal multiplex bus The C BUS is connected to the I BUS and D BUS via a switch An external interface module is connected to the C BUS Data and instructions are multiplexed in the external data bus Internal 16 bit wide data bus The R BUS is connected to the D BUS via an adapter Various I O ports the clock generator and interrupt controller are connected to the R BUS Since the R BUS is 16 bits wide in which addresses and data are multiplexed it takes twice as
222. de format 257 data transferred in CLK synchronous mode format Gee dene ete egt 258 debugger emulator and monitor 402 debugger 402 dala Slot tec e eee 53 delay slot branch instruction with 48 delayed interrupt control register DICR bit function of 221 delayed interrupt control register DICR configuration 221 delayed interrupt module block diagram 220 delayed interrupt module register 220 delayed branch instruction 416 delayed branch macro instruction 20 bit 419 delayed branch macro instruction 32 bit 421 descriptor access 343 INDEX descriptor first word 332 descriptor second word 334 descriptor third word 334 detection data register 0 BSDO 293 detection data register 1 BSD1 293 detection of error not found 401 detection result register BSRR 294 detection er rere ree Qs 295 detectlon ertet rrr
223. det pedes 413 initial value allocating variable with 396 initial vector table 44 initiallization re trees 258 initialization by power on 28 initialization by resetting 68 input of external reset 26 input of source oscillation at power on 27 input pin treatment of unused 26 instruction 407 instruction overview 46 instruction type 407 instruction NOW to read 403 INT instruction operation 65 INTE instruction operation 65 interchannel priority 339 internal 31 internal clock 287 internal memory external transfer from 341 internal 255 internal timer or external trigger to start A D converter 280 interregister transfer instruction 414 nicum 319 interrupt cause clearing
224. dress 0X800 to OX7FC multiple of 2 only label20 Signed 20 bit branch address 0X80000 to OX7FFFF label32 Signed 32 bit branch address 0 80000000 to OX7FFFFFFF Ri Register using indirect addressing RO to R15 AC FP and SP Hj Register using indirect addressing RO to R15 AC FP and SP 405 APPENDIX E Instructions 406 Table E 1 Explanation of Addressing Mode Codes R13 Rj Register using relative and indirect addressing Rj RO to R15 AC FP and SP R14 disp10 Register using relative and indirect addressing disp10 0 200 to OX1FC multiple of 4 only R14 disp9 Register using relative and indirect addressing disp9 0X100 to OXFE multiple of 2 only R14 disp8 Register using relative and indirect addressing disp8 0 80 to OX7F R15 udisp6 Register using relative and indirect addressing udisp6 0 to 60 multiple of 4 only Ri Register using indirect addressing with postincrement RO to R15 AC FP and SP R13 Register using indirect addressing with postincrement R13 AC SP Stack pop SP Stack push reglist Register list APPENDIX E Instructions Instruction Formats Table E 2 Instruction Formats Instruction format MSB LSB 16bit A OP Rj Ri 8 4 4 B OP i8 08 Ri 4 8 4 4 4 Ri
225. dress Choice between 2CAS 1WE and 2WE 1CAS DMAC DMA controller Eight channels Transfer cause External terminal or internal resource interrupt request Transfer sequence Step transfer or block transfer Burst transfer or continuous transfer Transfer data length Selectable from 8 16 and 32 bits A temporary stop is enabled by an NMl interrupt request O UART Independent three channels Full duplex double buffer Data length 7 to 9 bits no parity or 6 to 8 bits with parity Choice between asynchronous start stop synchronization communication and clock asynchronous communication Multiprocessor mode Built in 16 bit timer U Timer as a baud rate generator which can generate a desired baud rates An external clock can be used as a transfer clock Error detection Parity error frame error and overrun O A D converter successive approximation conversion type 10 bit resolution 4 channels Successive approximation conversion type 5 6 us at 25 MHz Built in sample and hold circuit Conversion mode Selectable from single conversion scan conversion and repeat CHAPTER 1 OVERVIEW conversion Starting Selectable from software external trigger and internal timer O Reload timer 16 bit timer Three channels Internal clock 2 clock cycle resolution Selectable from 2 8 and 32 frequency division mode O Other interval timers e 16 bit timer Three channels U Timer PWM timer Four channels
226. e Reserved 69 CHAPTER 2 CPU Mode Data Data that the CPU writes at 0000 07FF after resetting is called mode data The mode register MODR exists at 0000 07FF After mode data is set to this register the CPU operates based on the mode set to the register Mode data can be written to the mode register only once after resetting The mode set to the register is validated immediately after it is set B Mode Register MODR Figure 2 10 1 shows the configuration of the mode register MODR Figure 2 10 1 Mode Register Configuration Initial value Access MODR address 0000 07 M1 MO XXXXXXXX XQ Bus mode setting bits O Bus mode setting bits M1 MO These bits specify the bus mode that becomes valid after completion of writing to the mode register Table 2 10 2 summarizes the functions that can be specified by combinations of these bits Table 2 10 2 Bus Mode Setting Bit and the Function Function Remarks Single chip mode Internal ROM external bus mode External ROM external bus mode Reserved lt Note gt Set only 10 for a model that has no internal ROM O Other bits Always write 0 to these bits Notes on Writing to the Mode Register MODR 70 Before writing to the MODR be sure to set AMDO to AMD5 to decide the bus width of each chip select CS area The MODR has no bits used to
227. e The assembler calculates and sets values in the dir8 dir9 and dir10 fields as follows dir8 gt dir dir9 2 gt dir dir10 4 gt dir dir 8 dir9 and dir10 are unsigned Resource Instructions Table E 1 19 Resource Instructions Mnemonic Operation Remarks LDRES Ri u4 BC a Ri gt u4 resource 4 Channel number Ri 4 STRES 04 Ri BD a u4 resource gt Ri u4 Channel number Ri 4 422 APPENDIX E Instructions Coprocessor Control Instructions Table E 1 20 Coprocessor Control Instructions Mnemonic Operation Remarks COPOP u4 u8 CRj CRi Operation indication COPLD u4 u8 Rj CRi Rj gt CRi COPST u4 u8 CRj Ri gt Ri COPSV u4 u8 CRj Ri gt Ri No error trap Notes CRi CRij CRO CR1 CR2 CR3 CRA4 CR5 CR6 CR7 CR8 CR9 CR10 CR1 1 CR12 CR13 CR14 CR15 u4 Channel specification u8 Command specification Asthis device type does not have coprocessors these instructions cannot be used 423 APPENDIX E Instructions 424 INDEX INDEX The index follows on the next page This is listed in alphabetic order 425 INDEX Index Numerics O detection 00 00 11 295 16 31 bit immediate value transfer or immediate value setting 413 16 8 bit data data transfer block for 345 16 bit bus width 142 1
228. e RS1E bit controls the RAS1 output When this bit is reset the output is inhibited In this device type because the RAS1 pin also serves as the DMAC EOP2 output it is controlled together with the EPSE2 and EPDE2 bits of the DMAC control register DATCR as shown below Port initial value RAS1 output EOP2 output EOP2 output EOP2 output bit 0 RSOE The RSOE bit controls the RASO output When this bit is reset the output is inhibited 0 Inhibits output initial value 1 Permits output 137 CHAPTER 4 BUS INTERFACE 4 15 Little Endian Register LER When bus access by the MB91F109 is performed the whole area is usually composed of big endians However setting the little endian register LER makes it possible to handle one of areas 1 to 5 as a little endian area This register is supported for all bus modes independently of the usual time sharing and DRAM interfaces However area 0 is outside the little endian areas Configuration of Little Endian Register LER The little endian register LER is configured as follows LER 7 6 5 4 3 2 1 0 Initial value Access Address 0000 07 LE2 LE1 LEO 000 Bit Functions of Little Endian Register LER As shown in Table 4 15 1 the LE2 LE1 and LEO bits are combined to specify little endian areas Table 4 15 1 Mode Setting Using the Combination of Bits LE2 LE1 and LEO Initial value
229. e et x Phe ere 370 APPENDIX B ree Eo eet ene ED ru o ER ined 379 APPENDIX C Pin Status for Each CPU Status 383 APPENDIX D Notes on Using Little Endian Areas 395 0 1 lt C Gompiler f6C9 TT io oerte oe pao de pue edo ee do ue a a ede eed 396 D 2 Assembler fsm911 ince tdt tne en etit iei decet d m teen 399 D 3 Binker fink91T 401 D 4 Debuggers sim911 911 and 911 402 APPENDIX Instr ctioris si2 vide ei eati Reset cn P Pa e ees 403 E FReSeries Instructions egentium e dedic ded ven Da d eR aee cen n dcus 409 INDEX m 425 xi FIGURES Figure 1 2 1 Figure 1 3 1 Figure 1 3 2 Figure 1 3 3 Figure 1 4 1 Figure 1 4 2 Figure 1 4 3 Figure 1 7 1 Figure 1 8 1 Figure 1 8 2 Figure 2 2 1 Figure 2 2 2 Figure 2 3 1 Figure 2 3 2 Figure 2 3 3 Figure 2 3 4 Figure 2 4 1 Figure 2 4 2 Figure 2 6 1 Figure 2 6 2 Figure 2 8 1 Figure 2 8 2 Figure 2 10 1 Figure 3 1 1 Figure 3 1 2 Figure 3 9 1 Figure 3 9 2 Figure 3 10 1 Figure 3 10 2 Figure 3 10 3 Figure 3 11 1 Figure 3 11 2 Figure 3 11 3 Figure 3 12 1 Figure 3 13 1 xii General Block Diagram of 1 109
230. e invalid bit 14 Reserved This bit is reserved The value read from this bit undefined bit 13 WDOG When 1 the bit indicates that the reset that occurred previously was a watchdog reset bit 12 ERST When 1 the bit indicates that the reset that occurred previously was a reset caused by the external reset pin bit 11 SRST When 1 the bit indicates that the reset that occurred previously was a reset caused by a software reset request bit 10 Reserved This bit is reserved The value read from this bit undefined 76 3 2 Reset Reason Resister RSRR and Watchdog Cycle Control Register WTCR bit 09 08 WT1 0 These bits specify the cycle of the watchdog timer The bits and the cycles selected by the bits have the relationships shown in Table 3 2 1 These bits are initialized when the entire register is reset Table 3 2 1 Watchdog Timer Cycles Specified by WT1 WTO Minimum WPR write interval required to suppress watchdog resetting 215 Initial value Time from last 5AH write to WPR to occurrence of watchdog resetting 0x2 t0 9x 216 217 x 217 to 9x 218 6x22 ox 21 to 9 x 220 ox 2 x 2 to x 2 9 is twice as large as XO when GCR CHC is 1 and is the cycle of PLL oscillation frequency when CHC is O 77 CHAPTER 3 CLOCK GENERATOR AND CONTROLLER 3 3 Standby Control Register STCR The standby control register STCR is used t
231. e is no memory area specification command indicating little endian areas Memory manipulation commands and instructions to be executed are handled as if they applied to big endian areas B Emulator and Monitor Debuggers 402 When little endian areas are accessed with the following commands an abnormal value is assumed set memory show memory enter examine set watch command When floating point data single double is handled the specified value cannot be set or displayed search memory command This command cannot search for half word and word data with the specified value line or reverse assemble including reverse assemble display of source window Normal instruction codes cannot be specified or displayed do not specify instruction codes in little endian areas call show call command When a stack area is set in a little endian area an abnormality occurs do not specify stack areas in little endian areas APPENDIX E Instructions APPENDIX E Instructions This section lists the instructions for the FR series Before the instructions are listed the following items are explained How to read instructions e Addressing mode codes Instruction formats How to Read Instructions Mnemonic Operation Remarks ADD Rj Rj A AG 1 CCCC Ri Rj gt Rj ADD 55 Rj A4 1 CCCC Ri s5 gt Ri Y Y Y Y Y Y Y 1 Indicates the instruction names An asterisk indicates extended or a
232. e pulse PWM operation Initial value One shot operation 304 14 3 Control Status Register PCNH PCNL bit 12 RTRG Restart enable bit This bit enables or disables restart by a software trigger or trigger input Disable restart Initial value Enable restart bits 11 10 CKS1 CKSO Counter clock select bit These bits select the counter clock for the 16 bit decrementing counter Table 14 3 1 Selection of the Count Clock CKS1 CKSO Cycle Initial value 4 16 64 Peripheral machine clock bit 9 PGMS PWM output mask selection bit Setting this bit to 1 can mask the PWM timer so that it outputs only 0 or 1 regardless of the mode cycle or duty cycle settings Table 14 3 2 PWM Output When 1 is Written to PGMS Normal polarity Output of L Inverse polarity Output of H To maintain output at a high level in normal polarity mode or at a low level in inverse polarity mode write the same value to the cycle setting and duty cycle setting registers thereby inverting the output of the above mask values bit 8 Reserved bits 7 6 EGS1 SGSO Trigger input edge select bits These bits select the edge applicable to the start source selected by general control register 1 In any edge mode setting the software trigger bit to 1 enables the software trigger Table 14 3 3 Selection of Trigger Input Edge Edge selection Invalid initial value
233. e size 256 1CAS 2WE with wait CBR refresh Area 5 AMD5 16 bits DRAM page size 512 2CAS 1WE without wait CBR refresh Other buses Refresh RFCR without wait 1 8 setting External pin EPCRO external RDY reception arbitration by BRQ and BGRNTX External pin DSCR DRAM pin setting Little endian LER area 2 Also observe the following notes Pins MD2 MD1 and MDO 001 and external vector is in 16 bit mode Before setting the mode register MODR set area 0 to the same bus width Set area 1 to area 5 such that overlapping does not occur Program Example for External Bus Operation 196 For explanation this program writes to the byte register in bytes and the half word register in half words Program example Each register setting init epcr Idi 20 Oxffff r0 External pin setting External RDY wait bus arbitration by BRQ and BGRNTX 01 20 0x628 r1 epcrO register address setting sth r0 r1 Write to epcrO register init dscr Idi 8 O0xff r0 DRAM pin setting RAS CAS WE Idi 20 0x625 r1 dscr register address setting init amdO init amd1 init amd32 init amd4 init amd5 init dmcr4 init dmcr5 init rfcr stb ldi 8 Idi 20 stb ldi 8 Idi 20 stb ldi 8 Idi 20 stb Idi 8 Idi 20 stb Idi 8 Idi 20 stb Idi 20 01 20 sth Idi 20 01 20 sth 11 20 r0 r1 0x08 r0 0x620 r1 r0 r1 0x0a r0 20x621 r1
234. e value in the PS register The initial value after resetting is undefined When the DIVOS instruction is executed the dividend and divisor are referenced and set Execution of the DIVOU instruction forcibly clears the bits 40 2 3 Programming Model bit 8 T Step trace trap flag This flag specifies whether to enable step trace trap 0 Disables step trace trap 1 Enables step trace trap Setting the bit to 1 inhibits all user NMIs and user interrupts The flag is cleared to 0 by resetting The step trace trap function is used by an emulator It cannot be used in user programs while it is used by the emulator O Interrupt level mask register ILM The configuration of the interrupt level mask register ILM is as follows 20 19 18 17 16 Initial value ILM4 ILM3 ILM2 ILM1 ILMO 011115 The ILM register holds an interrupt level mask value The value held by the ILM register is used for level masking Of the interrupt requests input to the CPU only those with higher interrupt levels than the level indicated by the ILM are accepted The level values range in descending order of highness from 0 00000g to 31 111118 The values that can be set from a program are limited When the original value is in the range from 16 to 31 a new value that can be set must be in the same range i e from 16 to 31 If an instruction that sets a value from 0 to 15 is executed the specified value 16 is r
235. ecutes instructions until the priority check block outputs the check result The same operations are performed for returning from the sleep state In the sleep state the register in this module can be accessed using DMAC lt Notes gt NMI request also causes a return from the stop state For an interrupt cause that should not trigger a return from the stop or sleep state use the corresponding peripheral control register to inhibit the output of the interrupt request Since the signal for requesting a return from the standby mode is the output of a simple logical sum of all interrupt causes the interrupt level set in the ICR is not used To perform DMA transfer in the sleep state make settings in the DMA side to ensure that no interrupt request is posted to this module and that a return from the sleep state does not occur accidentally 234 8 7 Hold Request Cancel Request 8 7 Hold Request Cancel Request For processing a high priority interrupt while the CPU is in hold state cancellation of the hold request must be requested from the source for the hold request The interrupt level used to determine whether to issue a cancel request must be set in the HRCL register Criteria for Determining Whether to Issue a Hold Request Cancel Request When an interrupt cause having a higher level than that set in the HRCL register is generated a hold request cancel request is issued e Interrupt level set in the HRCL r
236. ed 0 Inhibits output 1 Permits output initial value When the external bus mode is used the COEO bit performs no I O port control for the CSOX pin Always set this bit to 1 134 4 13 External Pin Control Register 1 EPCR1 4 13 External Pin Control Register 1 EPCR1 External pin control register 1 EPCR1 controls address signal output B Configuration of External Pin Control Register 1 EPCR1 External pin control register 1 EPCR1 is configured as follows 15 14 13 12 11 10 9 8 Initial value 1 AE24 1 Address 0000 062 _ 0 Initial value AE23 AE22 AE21 AE20 AE19 AE18 AE17 AE16 11111111 Bit Functions of External Pin Control Register 1 EPCR1 bit 8 to 0 AE24 to AE16 Address output Enable 24 to 16 The AE24 to AE16 bits specify whether to output the corresponding addresses When the output is inhibited the register can be used as O port 0 Inhibits output 1 Permits output initial value AE24 to AE16 are reset to 1FF Access W Access W 135 CHAPTER 4 BUS INTERFACE 4 14 DRAM Signal Control Register DSCR The DRAM signal control register DSCR controls the output of each DRAM control signal When the output is inhibited this register can be used as I O port Configuration of DRAM Signal Control Register DSCR The DRAM signal control register DSCR is configured as fo
237. ed because the CPU fetches instructions and accesses data thereby creating bus contention 344 15 9 DMAC Timing Charts 15 9 2 Timing Charts of Data Transfer Block This section shows timing charts of the data transfer block Data Transfer Block for 16 Bit or 8 Bit Data O Transfer source area external transfer destination area external A CLK DREQn Addr pin 2 Xs XD AS XS XD AS XD Data pin Cs XD eS XD eS XD _ gt D i iium SE ap Me ee ee WRnX DACK O Transfer source area external transfer destination area external RAM A CLK JSUUUUUUUUUUUUUUUUUUUUUU DREQn Geo ee En Addr pin 20 XS X XS AS X XS S S S S Data pin RDXD er WRnX DACK _ EOP 345 CHAPTER 15 DMAC O Transfer source area internal RAM transfer destination area external A CLK 8 a tret lg ag YE gg BE DREQn OOS 2 227 Addr pin Data pin RDXD i WRox DACK N RM 346 15 9 DMAC Timing Charts 15 9 3 Transfer Stop Timing Charts in Continuous Transfer Mode This section shows transfer stop timing charts in continuous transfer mode Transfer Stop in Continuous Transfer Mode When Either Address is Unchanged for 16 Bit or 8 Bit Data O Transfer source area external transfer destination area external CLK Se EE Ep
238. ed to a space other than the areas specified by ASR1 to ASR5 1 to AMR5 When these registers are reset an area other than 00010000 and 0005FFFF is allocated by the initial values of ASR1 to ASR5 and AMR1 to AMR5 Note Set chip select areas such that overlapping does not occur 119 CHAPTER 4 BUS INTERFACE 120 Figure 4 4 1 shows a map of the areas set in the 64 kilobytes by initial values during reset and a map of the areas set in Examples 1 and 2 Initial value 000000004 000100004 000200004 00030000 00040000 00050000 00060000 Figure 4 4 1 Sample Maps of the Chip Select Areas Area 0 Area 1 Area 2 Area 3 Area 4 Area 5 Area 0 Values set in Examples 1 and 2 00000000H 00030000H 00040000H OFFCO000H 100000004 FFFFFFFF Area 0 Area 1 Area 0 Area 2 Area 0 4 5 Area Mode Register 0 AMDO 4 5 Area Mode Register 0 AMDO Area mode register 0 AMDO specifies the operation mode of chip select area 0 area other that those specified by ASR1 to ASR5 and AMR1 to AMR5 At reset time area 0 is selected B Configuration of Area Mode Register 0 AMDO Area mode register 0 AMDO is configured as follows AMDO Initial value Access Address 0000 0620H BW1 BWO WTC2 WTC1 WTCO 00111H R W Bit Functions of Area Mode Register 0 A
239. eed page mode The hyper DRAM interface starts from the Q1 to Q3 cycle as with the usual DRAM interface When the Q4 cycle is entered the CAS signal is controlled for one cycle and a read write operation is performed This manual represents the Q4 cycle for a read operation by Q4HR and Q4HW for a write operation Note that the page size 1CAS 2WE and 2CAS A WE setting and Q1 wait cycle are similar to those of the usual DRAM interface 4 17 Bus Timing Hyper DRAM interface Read Hyper DRAM interface Write Hyper DRAM interface DRAM Refresh CAS before RAS CBR refresh e Automatic wait cycle of CBR refresh Selfrefresh External Bus Request Bus control release Bus control acquisition 161 CHAPTER 4 BUS INTERFACE 4 17 1 Basic Read Cycle This section provides a chart of the basic read cycle timing Basic Read Cycle Timing Chart O Bus width 16 bits access words CSO area access CLK A24 00 D31 24 D23 16 RDX WROX WR1X CSOX CS1X CS2X CS3X 54 55 DACKO 162 Figure 4 17 1 Example of Basic Read Cycle Timing Chart BA1 BA2 BAI BA2 X wo X 2 i Xo X e X dm E NE 8 Bec pe en Half word access Half word access of upper address of lower address side side Explanation of operation CLK outputs external bus oper
240. egister gt Interrupt level after priority check gt A cancel request is issued Interrupt level set in the HRCL register lt Anterrupt level after priority check gt No cancel request is issued A cancel request remains valid and DMA transfer remains suppressed unless the interrupt cause triggering the cancel request is cleared To prevent this problem clear the corresponding interrupt cause Interrupt Levels for which a Hold Request Cancel Request is Available The values that can be set in the HRCL register range from 10000 to 11111g as with the ICR register When 111118 is set a cancel request is issued for every interrupt level When 10000 is set a cancel request is issued only for NMI Table 8 7 1 lists the settings for the interrupt levels for which a hold request cancel request is issued Table 8 7 1 Settings for the Interrupt Levels for which a Hold Request Cancel Request is Issued HRCL register Interrupt levels for which a hold request cancel request is issued NMI only NMI and interrupt level 16 NMI and interrupt levels 16 and 17 NMI and interrupt levels 16 to 30 initial value After the HRCL register is reset hold requests for all interrupt levels are canceled In this situation DMA transfer is not performed if interrupts occur and so set the HRCL register value should be set to the appropriate value 235 CHAPTER 8 INTERRUPT CONTROLLER 8 8 Example of Using the Hold
241. egister External bus D31 D31 J fm j D23 D15 a D23 D07 BB 141 CHAPTER 4 BUS INTERFACE O Byte access during execution of LDUB and STB instructions Figure 4 16 5 Relationship between Internal Register and External Data Bus for Byte Access a Lower bits of output address 0 Lower bits of output address 1 Internal register External bus Internal register External bus D31 D31 D31 D31 H D23 D23 D23 D15 D07 BB Data Bus Width The following shows the relationship between the internal register and external data bus for each data bus width O 16 bit bus width Figure 4 16 6 Relationship between Internal Register and External Data Bus for 16 bit Bus Width Internal register External bus Lower part of the output address gt 00 10 D31 D31 AA Read Write AA CC D23 lt gt BB DD D15 CC D07 DD 142 4 16 Relationship between Data Bus Widths and Control Signals O 8 bit bus width Figure 4 16 7 Relationship between Internal Register and External Data Bus for 8 bit Bus Width Internal register External bus Lower part of the output address gt 00 01 1 0 1 1 D31 Read Write D31 D23 BB D15 CC 007 DD External Bus Access Figure 4 16 8 and Figure 4 16 9 show external bus access in a 16 bit or 8 bit bus width in words half words and bytes These figures also show the following items Access byte location Program address a
242. eleased from sleep state The sleep state is cleared even if the interrupt level is set to interrupt inhibition level When the DMA transfer operation ends the CPU resumes execution of the next instruction after that during which sleep state was entered When performing a transfer operation while the CPU is in sleep state ensure through the design of the program that the CPU checks the appropriate conditions and enters again sleep state if required sleep_ mode Idi 50h rO Set SLEP bit Idi 481h r1 STCR address stb r0 r0 Enter sleep mode Determine the cause the CPU woke up We assume here that an external interrupt has released the sleep state Idi address r0 Idi compared data r1 Idub Qr rO and rO r1 beq sleep mode Control proceeds to the next processing step only when a specific address contains a specific value If another cause was responsible for example if the CPU was released from sleep state because of a DMA transfer operation after UART reception sleep state is entered again B Transfer to DMC Internal Register Do not specify a DMAC internal register as a transfer destination address B Continuous Transfer In continuous transfer mode write back to the descriptor may occur even during a transfer depending on the internal bus buffer status of the device In this case the transfer operation 340 15 8 Notes on DMAC itself continues External Transfer from Internal Memory In blo
243. en between them If the first A54 is followed by something other than the first A54 is ignored Therefore A5y must be written again B Timebase Timer The timebase timer is used to supply clock pulses to the watchdog timer and is used also as the oscillation stabilization wait timer The operating clock is double the XO when the GCR CHC is 1 or the cycle of the PLL oscillation frequency when the GCR CHC is 0 The value of this timebase timer is set in the RFCR and used as the count clock for the count value for DRAM refresh Figure 3 11 3 Timebase Timer Counter 1 27 1 22 129 e ee ee je qup 1 22 1 2 100 3 12 Reset Source Hold Circuit 3 12 Reset Source Hold Circuit The reset source hold circuit holds the source of previous resetting Reading the circuit clears all flags to 0 Once a source flag is set it is not cleared unless the circuit is read Block Diagram of Reset Source Hold Circuit Figure 3 12 1 is a block diagram of the reset source hold circuit Figure 3 12 1 Block Diagram of Reset Source Hold Circuit Internal bus From power on cell RSTX input circuit RSTX pin Initialized cl c by reading Watchdog reset detection circuit 07 2 Setting for Reset Source Holding No special settings are required to use the reset source hold function Provide an instruction to read the
244. en it is read it indicates that the corresponding pin has an external interrupt request Writing O to a bit of the register clears the flip flop of the interrupt request corresponding to the bit Writing 1 to the register is ignored When the register is read in read modify write mode 1 is always read Users cannot read or write the NMI flag 214 6 4 External Level Register ELVR 6 44 External Level Register ELVR The external level register ELVR selects the request detection mode B External Level Register ELVR The configuration of the external level register ELVR is shown below ELVR f 6 Initial value 5 4 2 1 0 Address 00009914 LA3 00000000 The external level register ELVR selects the request detection mode Two bits each are assigned to INTO to INT3 and defined as shown in Table 6 4 1 Access RAN Suppose the level is selected for the request detection mode If input is in the active level even after each EIRR bit is cleared the corresponding bit is set again Table 6 4 1 External Interrupt Request Mode Request detection mode 0 0 L level 0 1 H level 1 0 Rising edge 1 1 Falling edge NMI is always detected at its falling edge except when it stops When it stops it is detected at the L level 215 CHAPTER 6 EXTERNAL INTERRUPT NMI CONTROLLER 6 5 External Interrupt Operation After the external level register and enable interrupt request register are
245. er Compare register containing a buffer Transfer from the buffer is triggered by a counter borrow Pin control The pin is set to 1 when duty cycles match Priority The pin is reset to 0 when a counter borrow occurs Because the constant output level mode is supported output can be maintained at a low or high level e Polarity specification is enabled The following events can be selected as causes for interrupt requests PWM timer activation e Occurrence of counter borrow cycle matching e Occurrence of duty cycle matching e Occurrence of counter borrow cycle matching or duty cycle matching An interrupt request thus caused can start DMA transfer Software or another interval timer can activate multiple channels simultaneously Restarting during operation is also enabled 14 1 Overview of PWM Timer PWM Timer Registers Figure 14 1 1 shows the PWM timer registers Figure 14 1 1 PWM Timer Registers Address 15 0 000000DC R W General control register 1 000000DF 4 R W General control register 2 000000 0 R channel 0 timer register 000000 2 W channel 0 cycle setting register 000000 4 channel 0 duty setting register 000000 6 R W channel 0 control status register 000000 8 R channel 1 timer register 000000 W channel 1 cycle setting register 000000 W channel 1 duty cycle setting register 000000 R W channel 1 control status register 000000 0 R channel 2 timer
246. er 1 AMD1 4 6 Area Mode Register 1 AMD1 Area mode register 1 AMD1 specifies the operation mode of chip select area 1 area specified by ASR1 and AMR Configuration of Area Mode Register 1 AMD1 Area mode register 1 AMD1 is configured as follows AMD1 Initial value Access Address 0000 06214 MPX BW1 BWO WTC2 WTC1 WTCO 0 00000 R W Bit Functions of Area Mode Register 1 AMD1 bit 7 MPX MultiPlex bit The MPX bit controls the time sharing I O interface for address data input output This device type does not support employing a time sharing I O bus Set this bit to 0 bit 4 and 3 BW1 and 0 Bus Width bit BW1 and BWO specify the bus width of area 1 Bus width 8 bits 16 bits Setting disabled Reserved bit 2 to 0 WTC 2 to 0 Wait Cycle bit The WTC bits specify the number of wait cycles to be automatically inserted when the usual bus interface is operating Their operation is similar to WTC2 to WTCO of AMDO however they are reset to 000 and the number of wait cycles to be inserted becomes 0 123 CHAPTER 4 BUS INTERFACE 4 7 Area Mode Register 32 AMD32 Area mode register 32 AMD32 controls the operation mode of chip select area 2 area specified by ASR2 and AMR2 and chip select area 3 area specified by ASR3 and AMR3 These areas are accessed only via the usual bus and do not allow the use of special DRAM interfaces
247. er States 281 CHAPTER 12 16 BIT RELOAD TIMER 12 1 Overview of 16 bit Reload Timer The 16 bit reload timer consists of a 16 bit decrementing counter 16 bit reload register internal count clock pulse generation prescaler and control register An input clock can be selected from three types of internal clock frequencies machine clock frequency divided by 2 8 or 32 An interrupt can be used to start DMA transfer The MB91F109 contains three channels of 16 bit reload timer The channel 2 output of the reload timer is connected to the A D converter inside the LSI chip Therefore A D conversion can be started periodically as specified in the reload register 16 Bit Reload Timer Registers Figure 12 1 1 shows the 16 bit reload timer registers Figure 12 1 1 16 Bit Reload Timer Registers 14 11 10 EXERESES 32 register 15 0 TMR 15 0 TMRLR 282 12 1 Overview of 16 bit Reload Timer 16 Bit Reload Timer Block Diagram 2 Figure 12 1 2 is a 16 bit reload timer block diagram Figure 12 1 2 16 Bit Reload Timer Block Diagram 16 a 16 bit reload register 8 Reload lt T7 RELD K 16 bit decrementing counter UF OUTE OUTL 2 6 5 5 5 5555
248. erenced by the RET D instruction is not affected even when the instruction in the delay slot updates the RP Example RET D Branches to the address indicated by the RP that is set previously MOV R8 RP Does not affect the return operation O The flag that is referenced by the Bcc D rel instruction is not affected by the instruction in the delay slot Example ADD 1 RO Changes the flag BC D Overflow Branches according to the execution result of the above instruction ANDCCR 0 Updates the flag which is not referenced by the above branch instruction O When RP is referenced by the instruction in the delay slot of the CALL D instruction the data updated by the CALL D instruction is read Example CALL D Label Updates RP and branches MOV RP RO Transfers the RP the execution result of the above CALL D instruction 49 CHAPTER 2 CPU Resirictions on Branch Instructions with Delay Slots 50 O Instructions that can be placed in delay slots An instruction that can be executed in the delay slot must satisfy all of the following conditions e One cycle instruction Non branch instruction Instruction whose operation is not affected even when the execution order changes One cycle instruction is an instruction for which 1 a b c or d is indicated in the cycle count column in the list of instructions O Step trace trap No step trace trap is generated between the delay slot and the execution of the br
249. errupt Request Register The configuration of the enable interrupt request register ENIR is shown below ENIR d 3 0 Initial value Access The enable interrupt request register ENIR is used to mask the output of an external interrupt request The output of the interrupt requests corresponding to the register bits set to 1 is enabled ENO enables INTO and the requests are output to the interrupt controller The pins corresponding to the bits set to 0 retain interrupt causes but issue no request to the interrupt controller For this device writing to bits EN4 to EN7 has no effect Write 0 to these bits No mask bits are provided for nonmaskable interrupts NMI 213 CHAPTER 6 EXTERNAL INTERRUPT NMI CONTROLLER 6 3 External Interrupt Request Register EIRR When the external interrupt request register EIRR is read it indicates that there are external interrupt requests When it is written the flip flops indicating these requests are cleared External Interrupt Request Register EIRR The configuration of the external interrupt request register EIRR is shown below ER 15 14 1 11 1 9 Initial value Access 3 12 0 9 Address 0000944 ER7 ER5 ER2 ERO 00000000 R W When the external interrupt request register EIRR is read it indicates that there are external interrupt requests When it is written the flip flops indicating these requests are cleared If a bit of the register is 1 wh
250. erved When connecting a DRAM shift the address to be output by this LSI such that it matches the bus width to be used The following is an example of a DRAM connection using an x 8 bit 256 page size for 8 bit and 16 bit data buses When the 16 bit data bus is used one bit of the LSB area of each output address is left unconnected O 8 bit data bus using 1 DRAM Figure 4 16 18 Example of Connection between MB91F109 and One 8 bit Output DRAM 8 Bit Data Bus 156 COLUMN Address ROW Address External pin 1 DRAM This LSI 07 06 05 04 02 01 00 07 06 05 04 03 02 01 00 8 D07 00 RAS CAS WE D31 24 4 16 Relationship between Data Bus Widths and Control Signals O 16 bit data bus using 2 DRAMs Figure 4 16 19 Example of Connection between MB91F109 and Two 8 Bit Output DRAMs 16 Bit Data COLUMN Address ROW Address External pin 2 DRAMs Bus This LSI Not connected A08 A07 A06 A05 A04 A03 A02 A01 A00 A07 A06 A05 A04 A03 A02 A01 A00 x8 D07 00 A07 06 A05 A04 A03 02 A01 A00 x8 D07 00 RAS CASL WE RAS CAS WEL D31 24 RAS CASH WE RAS CAS WEH D23 16 Values in parentheses are for 1CAS 2WE 157 CHAPTER 4 BUS INTERFACE Connection Example of DRAM Device DRAM 2CAS 1WE page size 512 x 16 bit product Bus width 16 bits Number of banks 2 areas 4 and 5 Figure 4 16 20 Example of Connection between MB
251. es The states of the counter are determined by the CNTE bit of the control register and the internal Wait signal as follows CNTE 0 Wait 1 Stop state CNTE 1 Wait 1 Wait state start trigger wait state CNTE 1 Wait 0 Run state Figure 12 5 1 is a state transition diagram Counter States RESET CNTE 0 Figure 12 5 1 Counter States Transition gt State transition by hardware gt State transition by register access STOP CNTE 0 WAIT 1 Counter Holds the value at a stop Immediately after resetting this value is undefined CNTE 0 CNTE 1 CNTE 1 TRG 0 TRG 1 WAIT CNTE 1 WAIT 1 RUN CNTE 1 WAIT 0 36 Counter Holds the value at a stop The value is undefined immediately RELD UF Operae after resetting until loading TRG 1 TRG 1 LOAD CNTE 1 WAIT 0 Loading is completed The contents of the reload register are loaded to the counter 289 CHAPTER 12 16 BIT RELOAD TIMER 290 CHAPTER 13 BIT SEARCH MODULE This chapter provides an overview of the bit search module It explains the register configuration functions operations and the save restore processing of the bit search module 13 1 Overview of the Bit Search Module 13 2 Bit Search Module Registers 13 3 Bit Search Module Operation and Save Restore Processing 291 CHAPTER 13 BIT SEAR
252. et RSTX 0 SRST bit of STCR register 0 Watchdog timer reset Power on reset Mapping Addresses of Programs Used to Put Systems into Stop or Sleep State Place programs which are used to put clock systems into stop or sleep state into C bus ROM or external memory address areas Do not place them in C bus RAM 91 CHAPTER 3 CLOCK GENERATOR AND CONTROLLER 3 10 1 Stop State This section provides information on transition to and returning from the stop state Figure 3 10 1 shows a stop controller block diagram Stop Controller Block Diagram Figure 3 10 1 Stop Controller Block Diagram Stop state transition request signal Stop signal Internal bus 5 CPU clock gt CPU clock o g generation o 3 e o 9 Internal interrupt 8 E pmternal gt Internal bus clock 5 Internal reset 5 generation 5 Interna 5 Internal DMA clock 2 DMA clock 9 77 External bus clock amp generation 3 CPU hold enabled Y t CPU hold request T gt Internal peripheral clock clock Stop state generation 4 indication signal Clock stop Clock release request signal request signal Transition to Stop State O Transition to the stop state using an instruction Write 1 to bit 7 of the STCR register to cause a transition to the stop state A stop request is issued and when the CPU no longer uses the internal bus t
253. eturned When the original value is in the range from 0 to 15 a desired value from 0 to 31 can be set The register is cleared to 15 011115 by resetting 41 CHAPTER 2 CPU 2 44 Data Structure FR series data is mapped as follows e Bit ordering Little endian e Byte ordering Big endian Bit Ordering The FR series uses little endian for bit ordering Figure 2 4 1 shows data mapping in bit ordering mode Figure 2 4 1 Data Mapping in Bit Ordering Mode bit 31 29 27 25 23 21 19 17 15 1311 9 7 5 8 1 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 0 MSB LSB Byte Ordering The FR series uses big endian for byte ordering Figure 2 4 2 shows data mapping in byte ordering mode Figure 2 4 2 Data Mapping in Byte Ordering Mode MSB LSB Memory bit31 23 15 T 0 10101010 11001100 11111111 00010001 A B Address n 10101010 Address n 1 11001100 Address 2 11111111 Address n 3 00010001 42 2 5 Word Alignment 2 5 Word Alignment Since instructions and data are accessed in bytes mapping addresses vary depending on instruction length or data width Program Access A program running in the FR series must be placed at an address consisting of a multiple of two Bit 0 of the program counter PC is set to 0 when the
254. evious value allowed for value retained value retained retained all pins rae Caon Executed when During refresh Operation during PB3 DWOX DRAM pin is 1 DRAM terminal set setting PB4 RAS1 EOP2 Previous value retained PB5 CS1L DREQ2 Previous value retained PB6 CS1H DACK2 Previous value retained PB7 DW1X ANO to ANO 3 Previous status Previous status AN3 retained retained PEO to INTO INT2 Input Input PE2 possible possible PE3 INT3 SC2 Previous status retained PE4 to DREQO PE5 DREQ1 PE6 to DACKO PE7 DACK1 PFO 510 TRGO PF1 500 TRG1 PF2 SCO OCPA3 PF3 51 TRG2 388 APPENDIX C Pin Status for Each CPU Status Table C 3 Pin Status for 16 bit External Bus Length and 2CA1WR Mode Continued Pin name Function During sleep Previous status retained During stop HIZX 0 HIZX 1 Previous status Output Hi Z retained Input fixed to 0 Bus release BGRNT Previous status retained Reset time Output Hi Z Input allowed for all pins P when a general purpose port is specified F when the specified function is selected 1 Selfrefresh status is entered at selfrefresh start time When selfrefresh is cleared the previous value is retained 389 APPENDIX C Pin Status for Each CPU Status Table C 4 Pin Status in 8 bit External Bus Mode Pin name P20 to P27 Function During sleep Previous status retained During stop HIZX 0 Previous
255. ew of the A D converter explains the register configuration and functions and operations of the A D converter Chapter 12 16 bit Reload Timer Chapter 12 provides an overview of the 16 bit reload timer explains the register configuration and functions and operations of the 16 bit reload timer Chapter 13 Bit Search Module Chapter 13 provides an overview of the bit search module explains the register configuration and functions and operations and save restore processing of the bit search module Chapter 14 PWM Timer Chapter 14 provides an overview of the PWM timer explains the register configuration and functions and operations of the PWM timer Chapter 15 DMAC Chapter 15 provides an overview of the DMAC explains the register configuration and functions and operations of the DMAC Chapter 16 Flash Memory Chapter 16 explains the flash memory functions and operations The chapter provides information on using the flash memory from the FR CPU For information on using the flash memory from the ROM writer refer to the user s guide for the ROM writer Appendix The appendix provides information on I O maps interrupt vectors terminal states in each CPU status notes on using the little endian area and a listing of instructions It includes details of these types of information that are not covered by the text that can be referenced for programming The contents of this document are subject to change without no
256. f Automatic Wait Cycle Timing Chart 171 Example of External Wait Cycle Timing Chart 0444 172 Example of Usual DRAM Interface Read Timing Chart sse 173 Example of Usual DRAM Interface Write Timing Chart 175 Example 1 of Usual DRAM Read Cycle Timing 177 Example 2 of Usual DRAM Read Cycle Timing 178 Example of Usual DRAM Read Cycle Timing 178 Example 1 of Usual DRAM Write Cycle Timing Chart sene 179 Example 2 of Usual DRAM Write Cycle Timing 2 180 Example of Usual DRAM Write Cycle Timing 180 Example of Automatic Wait Cycle Timing Chart in Usual DRAM Interface 181 Example 1 of DRAM Interface Timing Chart in High Speed Page Mode 182 Example 2 of DRAM Interface Timing Chart in High Speed Page Mode 182 Example of DRAM Interface Timing Chart in High Speed Page Mode 183 Example 4 of DRAM Interface Timing Chart in High Speed Page Mode 184 Example of Single DRAM Interface Read Timing Chart 185 Example of Single DRAM Interface Write Timing Chart 186 Example of Single DRAM Interface Timing 187
257. g data and commands to the flash memory becomes valid and the automatic algorithm can be started However data from flash memory is read in 16 bit access mode during which flash memory cannot be used as program memory because 32 bit access is inhibited When overwriting this bit ensure that the RDY bit has caused a stop of the automatic algorithm write erase When the RDY bit is 0 the value of this bit cannot be changed This bit is initialized to during a reset Read and write operations are enabled 0 inhibits writing to the flash memory and enables 32 bit read operations ROM mode this is the initial value 1 enables writing to flash memory and inhibits 32 bit read operations programming mode bit 4 RDY ReaDY The RDY bit indicates the operation status of the automatic algorithm write erase When this bit is 0 the automatic algorithm is executing a write or erase operation and another Write or Erase command cannot be accepted Data also cannot be read from an address in flash memory Reading this bit indicates the status of flash memory For details see Section 16 7 Execution Status of the Automatic Algorithm This bit is initialized to 0 during a reset Read and write operations are enabled 0 Writing or erasing is in progress flash memory is not ready to accept a new Read Write or Erase command 1 Flash memory is ready to accept a new Read Write or Erase command bit 3 to 1 reserved bit
258. g the smallest interrupt number is selected 3 The interrupt level of the selected interrupt request is compared with the level mask value indicated by the ILM When the interrupt level equals or exceeds the level mask value the interrupt request is masked and not accepted When the interrupt level is less than the level mask value proceed to step 4 4 If the flag is 0 when the selected interrupt request is a maskable interrupt the interrupt request is masked and not accepted If the flag is 1 proceed to step 5 When the selected interrupt request is an NMI proceed to step 5 regardless of the flag value 5 If the above conditions are satisfied the interrupt request is accepted at the end of processing of the current instruction If a user interrupt NMI request is accepted when an EIT request is detected the CPU using the interrupt number corresponding to the accepted interrupt request operates as follows The parentheses in Operation represent the address indicated by the register 2 8 EIT Exception Interrupt and Trap Operation SSP 4 gt SSP PS gt SSP SSP 4 gt SSP Next instruction address gt SSP Interrupt level of accepted request gt ILM 0 gt S flag TBR vector offset of accepted interrupt request gt PC Before executing the first instruction of the handler after the end of an interrupt sequence the CPU detects another EIT If another acceptable EIT i
259. generation gt Peripheral circuit DMA clock DMA suppression DMA request Power on reset circuit gt PDRR register RSTX pin gt Internal peripheral clock Status gt Stop state transition control gt Sleep state circuit Watchdog controller gt register RSRR register WPR register Reset generation F F Watchdog F F Count clock gt CPU hold request gt Internal reset 75 CHAPTER 3 CLOCK GENERATOR AND CONTROLLER 3 2 Reset Reason Resister RSRR and Watchdog Cycle Control Register WTCR The reset reason register RSRR holds the type of the reset event that occurred and the watchdog cycle control register WTCR specifies the cycle of the watchdog timer Configuration of Reset Reason Register RSRR and Watchdog Cycle Conirol Register WTCR The configuration of the reset reason register RSRR and watchdog cycle control register WTCR is shown below 15 14 13 12 11 10 09 08 After power on Initial value Access RSRR R WTCR W B Bit Functions of the Reset Reason Register RSRR and Watchdog Cycle Control Register WTCR bit 15 PONR When 1 the bit indicates that the reset that occurred previously was a power on reset It also indicates that the other bits of this register ar
260. gister SCR controls the transfer protocol used for serial communication Configuration of Serial Control Register SSR The configuration of the serial control register SCR is shown below 40 000022 DEBES en ee 000007005 RW RW RW RW RW W RW RW Bit Function of Serial Control Register SSR bit 7 PEN Parity Enable This bit specifies whether to add a parity bit for data communication in serial communication mode 0 Add no parity bit Initial value 1 Add a parity bit lt Note gt A parity bit can be added only in normal mode mode 0 for asynchronous start stop communication No parity bit can be added in multiprocessor mode mode 1 or CLK synchronous communication mode mode 2 bit 6 P Parity This bit specifies whether to use even or odd parity when a parity bit is added for data communication 0 Even parity Initial value 1 Odd parity bit 5 SBL Stop Bit Length This bit specifies the number of stop bits used as a frame end mark in asynchronous start stop communication mode 0 One stop bit Initial value 1 Two stop bits bit 4 CL Character Length This bit specifies the number of bits data length for a single transmitted frame 0 7 bit data Initial value 1 8 bit data 250 10 3 Serial Control Register SCR lt Note gt Seven bit data can be used only in normal mode mode 0 for asynchronous start stop communication Use eight bit data in multiprocessor
261. gister Transfer Instructions Mnemonic Type OP Cycle NZVC Operation Remarks Transfer between general purpose registers Rs special register Rs special register Special register Rs TBR RP USP SSP MDH MDL 414 APPENDIX E Instructions B Standard Branch Without Delay Instructions Table E 1 11 Standard Branch Without Delay Instructions Mnemonic Operation Remarks Ri Ri gt PC label12 PC 2 gt RP PC 2 label12 PC 2 gt PC Ri PC 2 gt RP Ri gt PC RP gt PC SSP 4 PS gt SSP SSP 4 PC 2 gt SSP 0 gt I flag 0 gt S flag TBR 0x3FC u8x4 gt PC SSP 4 PS gt SSP SSP 4 PC 2 gt SSP 0 gt S flag TBR 0x3D8 gt PC For the emulator R15 gt PC R15 4 R15 gt PS R15 label9 PC 2 label9 PC 2 gt PC label9 Nonbranch label9 if Z 1 then PC 2 label9 PC 2 gt PC 1 s Z 0 t s C 1 1 s C 0 s N s N 0 s V s V 0 s V xor N 1 s V xor N 0 S V xor or Z S V xor N or Z 0 s C or Z s C or Z 0 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 Notes The number of cycles item 2 1 means 2 cycles for branch and 1 for nonbranch The assembler calculates and sets values in the rel11 and rel8 fields of the hardware specifications as follows label 2 PC 2 2 gt rel11 labe
262. ground level An I O port and resource I O are multiplexed as shown like xxxx Pxx at most pins listed above If the port conflicts with resource output at this type of pin the resource output is given priority 21 CHAPTER 1 OVERVIEW 1 6 Circuit Format Tables 1 6 1 and 1 6 2 shows I O circuit formats B 1 0 Circuit Format Table 1 6 1 circuit format 1 2 Classification Circuit format STANDBY Remarks For 50 MHz Oscillation feedback transistor About 1 MQ Standby control P channel transistor N channel transistor Diffused resistor F Digital input CMOS level hysteresis input No standby control Pull up resistance About 50 kQ 22 Control signal Mode input Diffused resistor CMOS level input High voltage control enabled for flash test 1 6 I O Circuit Format Table 1 6 1 circuit format 1 2 Classification Circuit format Remarks CMOS level hysteresis input Wr standby control P channel transistor N channel transistor 77T Digital input Table 1 6 2 circuit format 1 2 Classification Circuit format Remarks e CMOS level output Standby control I Digital output Diffused resistor I Digital output Digital input e CMOS level output e CMOS level hysteresis input Digital output Standby control Diffused resistor I Digital output Digital input Analog input I Digital output
263. gure 4 17 35 Example of CAS before RAS CBR Refresh Timing Chart Q4 Q5 R1 R2 R3 R4 ide Q1 Q2 Q3 A24 00X col adr K X row adr D31 16 ED Explanation of operation When executing CBR refresh set the REFE bit of DMCR4 and DMCR5 and the STR bit of the RFCR This manual represent the CBR cycle by R1 to R4 CAS is asserted at the falling edge of the R2 cycle and negated at the falling edge of the R4 cycle RAS is asserted at the rising edge of the R3 cycle and negated at the falling edge of the idle cycle next to R4 WE is negated in the CBR cycle For the 1CAS 2WE CAS is output for the 2CAS 1WE both CASL and CASH are output at the time describe above The priority of CRB refresh is higher than that of DRAM bus access During DRAM access for example during word access in an 8 bit bus width four times of bus access are required In this case even if a refresh request is detected from the first to third bus access the refresh is not executed until the fourth bus cycle ends CBR refresh is always executed when the last access cycle ends DRAM access at the end of CBR refresh always starts from the Q1 cycle that indicates the start of that access and data output starts with the row address even if the next bus access is within a page CBR refresh is executed periodically even under t
264. hanian Eaa 410 Logical Operation 411 Bit Operation Instructions 411 Multiplication and Division 412 Shift im ee rere bd at 412 Immediate Value Setting 16 32 Bit Immediate Value Transfer Instruction 413 Memory Load Instructions OUT o Cp ER Eie 413 Memory Store Instructions 0 414 Interregister Transfer 414 Standard Branch Without Delay Instructions sse 415 Delayed Branch Instructions 7 416 Other InstrUctions ped die Pee equ e dare ee dd dp eg nuce 417 20 Bit Standard Branch Macro Instructions sees 418 20 Bit Delayed Branch Macro 419 32 Bit Standard Branch Macro Instructions essen nennen 420 32 Bit Delayed Branch Macro Instructions 421 Direct Addressing Instr ctlons cttm t ene tuique tar 422 Resource Instructions aa tenes rentre nnns nnns 422 Coprocessor Control Instructions 423
265. hart for clock selection 3 9 Gear Function Figure 3 9 2 Clock Selection Timing Chart Source clock CPU clock a CPU clock b Peripheral clock a Peripheral clock b CHC CCK value 01 X00 PCK value 00 Blocks That Use the Peripheral Clock The blocks listed below use the peripheral clock which can be set by the gear function as the operating clock Calculate the operation time based on the frequency division ratio set to bits PCKO and PCK1 of the GCR register of the clock generator Clock generator Interrupt controller e Ports Dto F U TIMER channels 0 1 2 UART channels 0 1 2 A D converter 16 bit reload timer channels 0 1 2 External interrupt NMI controller Delayed interrupt module PWM timer 89 CHAPTER 3 CLOCK GENERATOR AND CONTROLLER 3 10 Standby Mode Low Power Consumption Mechanism The standby mode implies the stop state and sleep state Outline of Stop State In the stop state all internal clocks and the operation of the oscillation circuit are stopped so as to minimize power consumption Proceed as follows to shift to the stop state Using an instruction to write to the standby control register STCR Perform one of the following to return to the operating state Interrupt request limited t
266. he CPU 227 CHAPTER 8 INTERRUPT CONTROLLER 8 3 Interrupt Control Register ICR One interrupt control register is provided for each type of interrupt input and is used to set the interrupt level of the corresponding interrupt request Configuration of Interrupt Control Register ICR The configuration of the interrupt control register ICR is shown below bit7 ICR4 ICR3 ICR2 ICR1 ICRO 11111 Initial value R RW RW RW RW B Bit Functions of Intefrupt Control Register ICR bit 4 to 0 ICR 4 to 0 These are the interrupt level setting bits that are used to specify the interrupt level of the corresponding interrupt request When the interrupt level specified by this register equals or exceeds the level mask value set in the CPU ILM register the CPU masks the interrupt request When the register is reset the bits are initialized to 11111p Table 8 3 1 summarizes the correspondence between the interrupt level setting bits and the interrupt levels 228 8 3 Interrupt Control Register ICR Table 8 3 1 Correspondences between the Interrupt Level Setting Bits and Interrupt Levels Interrupt level System reserved NMI Highest level that can be set High Low Interrupt prohibited ICR4 is fixed to 1 and cannot be set to O 229 C
267. he clocks are stopped in the following order CPU clock gt internal bus clock gt internal DMA clock gt internal peripheral clock The oscillation circuit stops when the internal peripheral clock stops lt Notes gt 92 Proceed as follows to cause a transition to the stop state using an instruction Before writing to the STCR set the same value in CCK1 CCKO and PCK1 PCKO of the GCR to match the CPU clock and peripheral clock gear ratios Do not cause a transition to the stop state while the GCR CHC bit is 0 operating with PLL Before causing a transition to the stop state always set the GCR CHC bit to 1 divide by two frequency system to change the clock At least six consecutive NOP instructions must be provided immediately after writing to the STCR 3 10 Standby Mode Low Power Consumption Mechanism Example of setting the maximum gear speed LDI 20 GCR RO LDI 8 0000001 1b R1 CHC 1 CPU Peripheral gear ratio STB R1 RO DBLON 0 loop BTSTH 0010b RO loop Wait until DBLAK becomes 0 10 20 STCR RO LDI 8 10010000b R1 STOP 1 STB R1 RO NOP NOP NOP Returning from the Stop State An interrupt or resetting can be used to return from the stop state O Return by way of an interrupt When the interrupt enable bit which is one of the peripheral functions is on a peripheral interrupt can be caused to return from the stop state
268. he flip flop is cleared Figure 6 6 2 Input of an Interrupt Cause in Interrupt Enable Mode and a Request Issued to the Interrupt Controller H level Input of interrupt Interrupt request to the interrupt controller Clearing the interrupt cause flip flop deactivates the signal 217 CHAPTER 6 EXTERNAL INTERRUPT NMI CONTROLLER 6 7 Nonmaskable Interrupt NMI Operation NMI is the interrupt with the highest priority among other user interrupts It can only be masked during the period from immediately after a reset to the completion of the ILM setting NMI Operation NMI is accepted as follows Normal state Falling edge Stop state L level NMI can be used to cancel the stop state When the L level is input in the stop state the stop state is canceled and the oscillation stabilization time is spent If the NMIX pin receives the H level within the oscillation stabilization time the NMI cause is lost and NMI processing is not performed after the operation restarts When NMI processing is desired after the stop state is canceled keep the NMIX pin at the L level and return it to the H level within the NMI processing routine The NMI request detection block has an NMI bit which is set by an NMI request and can be cleared only when the NMI interrupt itself is received or during a reset The NMI bit cannot be read or written Figure 6 7 1 shows the NMI request detection bl
269. he following conditions Usual bus access other DRAM access is performed The external bus is released BGRNTX is L The CPU is sleeping 191 CHAPTER 4 BUS INTERFACE Automatic Wait Cycle of CBR Refresh Figure 4 17 36 Example of Timing Chart of CBR Refresh Automatic Wait Cycle R1 RIW R2 R3W R4 idle CLK RAS N CAS i i wait wait Explanation of operation When inserting a CBR refresh automatic wait cycle set the R3W bit of the RFCR B Selfrefresh Figure 4 17 37 Example of Selfrefresh Timing Chart SR1 SR2 SR3 SR3 SR3 idle CLK SLFR bit RAS ON CAS i Explanation of operation Set the SLFR bit of DMCR4 or DMCRS5 to 1 to start selfrefresh and set 0 to release it When the selfrefresh ends at least seven idle cycles are inserted n this manual selfrefresh is represented by SR1 to SR3 192 4 17 Bus Timing 4 17 21 External Bus Request This section provides external bus request timing charts Bus Control Release Figure 4 17 38 Example of Bus Control Release Timing Chart CLK A24 00 X 50 1 high Z D31 16 3 0 1 high Z RDX high 7 BRQ BGRNTX 1 cycle Explanation of operation When performing bus arbitration by
270. he interrupt level of the cause selected as the result of checking to the CPU Transmission of the interrupt number of the cause selected as the result of checking to the CPU Indication of return from stop state in accordance with NMl interrupt Issuance of a hold request cancel request to the bus master 8 1 Overview of Interrupt Controller B Interrupt Controller Registers Figure 8 1 1 shows the interrupt controller registers Figure 8 1 1 Interrupt Controller Registers 1 2 bit7 6 5 4 3 2 1 0 Address 000004004 ICR4 ICR3 ICR2 ICR1 ICRO ICROO Address 00000401 m ICR4 ICR3 ICR2 ICR1 ICRO ICRO1 Address 000004024 ICR4 ICR3 ICR2 ICR1 ICRO ICRO2 Address 000004034 ICR4 ICR3 ICR2 ICR1 ICRO ICRO3 Address 000004044 ICR4 ICR3 ICR2 ICR1 ICRO ICRO4 Address 000004054 ICR4 ICR3 ICR2 ICR1 ICRO ICRO5 Address 000004064 ICR4 ICR3 ICR2 ICR1 ICRO ICRO6 Address 000004074 ICR4 ICR3 ICR2 ICR1 ICRO ICRO7 Address 000004084 ICR4 ICR3 ICR2 ICR1 ICRO ICRO8 Address 000004094 ICR4 ICR3 ICR2 ICR1 ICRO ICRO9 Address 0000040A4 ICR4 ICR3 ICR2 ICR1 ICRO ICR10 Address 0000040BH ICR4 ICR3 ICR2 ICR1 ICRO ICR11 Address 0000040CH ICR4 ICR3 ICR2 ICR1 ICRO ICR12 Address 0000040DH ICR4 I
271. hen the gear settings of both CPU and peripherals are the same before changing or the gear of only one side will be changed or when both will be set to the same gear the gear s can be set directly to the desired value 83 CHAPTER 3 CLOCK GENERATOR AND CONTROLLER 84 When the clock doubler is set to ON the CPU gear is fixed regardless of the GCR value and therefore the gear can also be set directly to the desired value Example of programming Idi 0x484 r1 Idi 0x0d 0 stb rO r1 CPU Peripheral 1 8 ldi 0x484 ri Idi ro stb rO r1 CPU 1 8 Peripheral 1 8 Temporarily set to the same ratio Idi 0xc5 ro stb rO ri CPU 1 8 Peripheral Set to the desired ratio bit 09 Reserved bit Always write 1 to this bit bit 08 CHC This bit selects the source of the reference clock This bit is initialized by resetting While the VSTP bit of the PCTR register is 1 an attempt to write 0 to this bit is ignored Clock source Using two divisions of the oscillation circuit as the reference clock initial value Using the oscillation output from PLL as the reference clock lt Note gt When the system shifts to stop mode while the VSTP bit of the PCTR is 0 PLL stops oscillation but VSTP remains 0 When the system returns from the stop mode because of an external interrupt about 100 microseconds are required in addition to the oscillation stabilization wait time set in STCR OSC1 and OSCO before PLL osci
272. her than 31 interrupt inhibited for level 31 Causesin the lowest interrupt level Among these causes one with the smallest interrupt number Table 8 5 1 summarizes the relationships among interrupt causes numbers and levels Table 8 5 1 Relationships among Interrupt Causes Numbers and Levels 1 2 Cause of interrupt NMI request Interrupt number Decimal Hexadecimal Interrupt level 15 Fy fixed Offset TBR default address 000FFFCO External interrupt O ICROO 000FFFBC External interrupt 1 ICRO1 000FFFB8 External interrupt 2 ICRO2 OOOFFFB4 External interrupt 3 ICROS 000FFFBO UART 0 reception complete ICRO4 000FFFAC UART 1 reception complete ICRO5 OOOFFFA8 UART 2 reception complete ICRO6 OOOFFFA4 UART 0 transmission complete ICRO7 000FFFAQ UART 1 transmission complete ICRO8 000FFF9C UART 2 transmission complete ICRO9 000FFF98 DMAC 0 end error ICR10 000FFF94 DMAC 1 end error ICR11 000FFF90 231 CHAPTER 8 INTERRUPT CONTROLLER Table 8 5 1 Relationships among Interrupt Causes Numbers and Levels 1 2 Cause of interrupt DMAC 2 end error Interrupt number Decimal Hexadecimal Interrupt level TBR default address 000 DMAC 3 end error 000FFF88 DMAC 4 end error 000FFF84
273. his bit bit 13 INTE INTerrupt Enable This bit specifies whether to enable issuing interrupt request at the end of conversion 0 Disable interrupts 1 Enable interrupts Set this bit to 1 for starting DMA transfer by issuing an interrupt The bit is initialized to 0 when the register is reset bit 12 PAUS A D converter PAUSe This bit is set when A D conversion stops There is only one register that can contain the A D conversion result When A D conversion is performed continuously previously stored data is lost unless the conversion result is transferred by DMA This bit is provided to prevent storing the following converted data items until the current data in the data register is transferred by DMA A D conversion is stopped during this period A D conversion resumes after DMA transfer is finished This bit is effective only when DMA is used See Section 11 5 Conversion Data Protection Function for more information The bit is cleared when the register is reset bit 11 10 STS1 STSO STart Source select These bits are cleared when the register is reset The bits are used to select the cause for starting the A D converter Table 11 2 1 Selecting the Causes for Starting the A D Converter A D converter started by 0 0 Software 0 1 External pin trigger signal or software 1 0 Timer or software 1 1 External pin trigger signal timer or software In a mode for which multiple trigger causes appl
274. ic e teer n RE e id rescindere be 58 2 8 5 Table Base Register TBR seii NN 59 2 8 6 Vector Table end od eed eec eei Pina so ie ebat tI E Rede ERE HERE de es 60 2 8 7 Multiple EIT Processing use 62 2 8 8 EMT Operation osi ee ite tr id nete tue 64 2 9 IRESEL SCQUCMCS asics eh e dte ds C ates 68 2 10 Operation Mode e de deat ex Ew dv dude ie cv E der vea 69 CHAPTER3 CLOCK GENERATOR AND CONTROLLER 73 3 1 Outline of Clock Generator and Controller essen 74 3 2 Reset Reason Resister RSRR and Watchdog Cycle Control Register WTCR 76 3 3 Standby Control Register STCR 78 3 4 DMA Request Suppression Register 80 3 5 Timebase Timer Clear Register 024 0000 00000 enne 81 3 6 Gear Control Register eed e ed eb tes eines 82 3 7 Watchdog Timer Reset Delay Register 85 3 8 Control Register POTR reete tec P 86 vii Be Ho Ma gt You sae MEE T 87 3 10 Standby Mode Low Power Consumption
275. iguration of 270 control status register PCNH PCHL bit function 304 control status register PCHL configuration 304 control status register TMCSR bit function of 284 control status register TMCSR configuration of 284 conversion data protection function 278 convert and stop 277 coprocessor control instruction 423 Coprocessor error trap 67 coprocessor nonexistent trap 67 counter state 2 cei 289 GPU d 31 CPU architecture characteristic of 30 CPU status pin status for each 384 crystal oscillation 27 D data access 43 399 data bus width 142 149 data bus width and control signal relationship between 139 data direction register DDR configuration of 204 data fOFmal ier eie 141 147 data register ADCR configuration of 275 data register change point detection BSDC 294 data transfer block for 16 8 bit data 345 data transferred in asynchronous start stop mo
276. igure 4 16 17 Figure 4 16 18 Figure 4 16 19 Figure 4 16 20 Figure 4 17 1 Figure 4 17 2 Figure 4 17 3 Figure 4 17 4 Figure 4 17 5 Figure 4 17 6 Figure 4 17 7 Figure 4 17 8 Figure 4 17 9 Figure 4 17 10 Figure 4 17 11 Example of PLL Clock 108 Clock System Reference Diagram sess nennen nennen trennen nens 109 Bus Interface Registers ESERE aiai 113 Bus Interface Block Diagram 114 Example of Setting Chip Select 115 Sample Maps of the Chip Select Areas 22 2 1 0 120 Data bus Widths and Control Signals in Usual Bus Interface 139 Data Bus Widths and Control Signals in DRAM Interface 139 Relationship between Internal Register and External Data Bus for Word Access 141 Relationship between Internal Register and External Data Bus for Half Word Access 141 Relationship between Internal Register and External Data Bus for Byte Access 142 Relationship between Internal Register and External Data Bus for 16 bit Bus Width 142 Relationship between Internal Register and External Data Bus for 8 bit Bus Width 143 External Bus Access
277. in which no restart is enabled during operation Continuous conversion mode in which no restart is enabled during operation Single conversion mode Continuous conversion mode Convert and stop mode Convert and stop mode in which no restart is enabled during operation A D conversion is performed continuously from the ANS2 to ANSO setting channels to the ANE2 to ANEO setting channels and stops after one cycle of operation A D conversion is performed from the ANS2 to ANSO setting channels to the ANE2 to ANEO setting channels and is repeated A D conversion is performed from the ANS2 to ANSO setting channels to the ANE2 to ANEO setting channels in such a mode that A D conversion stops when conversion for one channel is finished A D conversion is restarted by the specified start cause These bits are initialized to 00 by a reset 272 11 2 Control Status Register ADCS Note A D conversion that is started in continuous conversion mode or convert and stop mode continues until the BUSY bit stops it Writing to the BUSY bit stops A D conversion No restart is enabled in single conversion continuous conversion or convert and stop mode applies to all start causes including the timer external trigger signal and software bit 5 4 3 ANS2 ANS1 ANSO ANalog Start channel set These bits are used to set the A D conversion start channel When started the A D converter begins A D convers
278. ing Previous value retained Previous value retained Previous value retained Previous status retained Output Hi Z Input allowed for all pins 385 APPENDIX C Pin Status for Each CPU Status Table C 2 Pin Status for 16 bit External Bus Length and 2CA1WR Mode Continued Pin name Function 386 During sleep Previous status retained During stop HIZX 0 HIZX 1 Previous status Output Hi Z retained Input fixed to 0 Bus release BGRNT Previous status retained Reset time Output Hi Z Input allowed for all pins P when general purpose port is specified F when the specified function is selected 1 Selfrefresh status is entered at selfrefresh start time When selfrefresh is cleared the previous value is retained Table C 3 Pin Status for 16 bit External Bus Length and 2CA1WR Mode Pin name P20 to P27 Function During sleep Output retained or Hi Z APPENDIX C Pin Status for Each CPU Status During stop HIZX 0 Output retained or Hi Z Output retained Address output Output retained Address output P60 to P67 P Previous status retained F Address output P Previous status retained F Address output Previous status retained Previous status retained P Previous status retained F RDY input P F Previous status retained BGRNTX P Previous sta
279. ing during a write operation the toggle bit toggles for about 2 us and stops to toggle without overwriting If all selected sectors are write protected the toggle bit toggles for about 100 us and the system returns to the read mode without changing data Temporary sector erase stop status When a read operation is performed during a temporary sector erase stop operation flash memory outputs 1 if the address indicated by the address signal is included in the sector in erase state If the address is not included in the sector in erase state flash memory outputs the data of bit 6 of the read value at the address indicated by the address signal bit 5 TLOVER Time limit over Automatic write erase operation status Bit 5 indicates by becoming 1 that execution of the automatic algorithm has exceeded the time limit internal pulse count specified in flash memory In other words when this flag outputs 1 while the automatic algorithm is running this indicates that a write or erase operation failed If an attempt is made to write to a nonblank area without erasing the data of that area bit 5 also indicates that the attempt failed In this case the data of bit 7 data polling is undefined and bit 6 toggle bit continues to toggle If the time limit is exceeded in this status bit 5 is set to 1 Note that in this case flash memory is not defective but is used incorrectly If this state is entered perform a Reset bit 3 SETIMR
280. ing of conversion 277 CHAPTER 11 A D CONVERTER Successive approximation type 11 5 Conversion Data Protection Function The A D converter of the MB91F109 has a conversion data protection function that features continuous conversion using DMAC and securing multiple data items Conversion Data Protection Function 278 The A D converter has only one conversion data register That means that in continuous conversion mode new conversion data overwrites the previously stored data in the register each time one cycle of A D conversion is finished The A D converter has a function to prevent this problem If the previously stored data has not been transferred to memory using the DMAC when conversion is finished the A D converter refrains from storing new conversion data in the register and stops instead The A D converter is released from the stop state after previous data is transferred to memory in DMA transfer mode If previous data has already been transferred when current conversion is finished the A D converter continues conversion without stopping lt Notes gt The conversion data protection function is affected by the ADCS INT and INTE bits The function works only when interrupts are enabled INTE 1 The function does not work when interrupts are disabled INTE 0 and conversion data overwrites the register successively and previous data is lost if A D conversion is performed continuously If DMA transfer is n
281. interrupt request is masked and not accepted if the following condition is satisfied Interrupt level held by the cause is greater than or equal to Level mask value 55 CHAPTER 2 CPU 2 8 2 Interrupt Control Register ICR The interrupt control register which is provided in the interrupt controller is used to set the level for each interrupt request The ICR is divided to correspond to individual interrupt causes The ICR is mapped in the I O address space and accessed from the CPU via the bus Configuration of Interrupt Control Register ICR The configuration of the interrupt control register ICR is shown below 7 6 5 4 3 2 1 0 ICR4 ICR3 ICR2 ICR1 ICRO Initial value 11111 R R W R W R W R W B Bit Functions of Interrupt Control Register ICR bit 4 ICR4 This bit is always 1 bit 3 to 0 ICR3 to 0 These four bits correspond to the four low order bits of the interrupt level of the corresponding interrupt cause The bits can be read and written The bits together with bit 4 enable the ICR to specify a value in the range from 16 to 31 B interrupt Control Register ICR Mapping Table 2 8 2 Assignments of interrupt causes and interrupt vectors Table 2 8 2 Assignments of Interrupt Causes and Interrupt Vectors Interrupt Interrupt control register Corresponding interrupt vector cause Number Address Number Address Hexadecimal Decimal 00000400 TBR 3BCy 0
282. ion with the channel selected by these bits Table 11 2 3 Setting the A D Conversion Start Channel Start channel ANO 1 AN2 AN3 Reserved Reserved Reserved Reserved When read these bits indicates the channel over which A D conversion is being performed When read while the A D converter is stopped in convert and stop mode the bits indicate the channel over which A D conversion has been previously completed These bits are initialized to 000 when the register is reset bit2 1 0 ANE2 ANE1 ANEO ANalog End channel set These bits are used to set the A D conversion end channel Table 11 2 4 Setting the A D Conversion End Channel ANE2 ANE1 ANEO End channel 0 0 0 ANO 0 0 1 AN1 0 1 0 AN2 0 1 1 AN3 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved 273 CHAPTER 11 A D CONVERTER Successive approximation type If the same channel as that set by ANS2 to ANSO is set only one channel is subjected to A D conversion single conversion mode After A D conversion is finished over the channel set by these bits in continuous conversion or convert and stop mode the A D converter returns to the start channel set by ANS2 to ANSO When setting the channels observe the rule that ANE equals or exceeds ANS Example ANS sets channel 1 and ANE sets channel 3 in single conversion mode A D conversion is performed from channel 1 to
283. is not to be resumed use the DMA suppression function after the cause of the interrupt is resolved by the DMA transfer interrupt processing routine The DMA suppression function is activated by writing a value other than 0 to the DMA suppression register and is deactivated by writing 0 to the register DMA Suppression Circuit Block Diagram Figure 3 13 1 is a block diagram of the DMA suppression circuit Figure 3 13 1 DMA Suppression Circuit Block Diagram Internal bus DMA request Setting for DMA Suppression The DMA suppression function is used mainly in the interrupt processing routine In the interrupt processing routing the function increments the value in the DMA suppression register by one before the interrupt cause is cleared thereby preventing DMA transfer thereafter When the interrupt processing is finished the function decrements the register value by one before control returns from the interrupt processing routine In the case of multiple interrupts decrementing the value by one does not clear the value in the DMA suppression register and so DMA transfer remains suppressed In the case of a single interrupt decrementing the value by one clears the register value and so DMA requests are soon enabled 103 CHAPTER 3 CLOCK GENERATOR AND CONTROLLER 104 Example INT ENTRY LDI 20 PDRR R10 LD RI10 R1 ADD 1 R1 ST R1 R10 LDI 20 stint REG R10 LDI 8 10H R1 ST R1 R10 in
284. is outside of the range in 1 and includes an external reference symbol an instruction is created as follows LDI 32 label32 Ri JMP D Ri Reference 3 Bcc32 D 1 When label32 PC 2 is from 0x100 to 0xfe an instruction is created as follows Bcc D label9 421 APPENDIX E Instructions 2 When label32 PC 2 is outside of the range in 1 and includes an external reference symbol an instruction is created as follows Bxcc false xcc Counter condition of cc LDI 32 label32 Ri JMP D Ri false Direct Addressing Instructions Table E 1 18 Direct Addressing Instructions Mnemonic Operation Remarks DMOV dir10 R13 DMOV R13 dir10 DMOV dir10 R13 DMOV R13 dir10 DMOV dir10 R15 DMOV R15 dir10 DMOVH dir9 R13 DMOVH R13 dir9 DMOVH dir9 R13 DMOVH R13 dir9 DMOVB dir8 R13 DMOVB R13 dir8 DMOVB dir8 R13 DMOVB R13 dir8 dir10 gt R13 Word R13 gt dir10 Word dir10 gt R13 R13 4 Word R13 gt dir10 R13 4 Word R15 4 R15 gt dir10 Word R15 gt dir10 R15 4 Word dir9 gt R13 Half word R13 gt dir9 Half word dir9 gt R13 R13 2 Half word R13 gt dir9 R13 2 Half word dir8 gt R13 Byte R13 gt dir8 Byte dir8 gt R13 R13 Byte R13 gt dir8 R13 Byte Place NOP after the DMOV instruction that specifies R13 as the transfer source Not
285. ision result register MDL 34 2 3 Programming Model 2 3 1 General Purpose Registers Registers RO to R15 are general purpose registers They are used as accumulators for various types of operation or memory access pointers General Purpose Registers Figure 2 3 3 shows the configuration of general purpose registers Figure 2 3 3 Configuration of General Purpose Registers 32 bits Initial value RO XXXX R1 R12 R13 A R14 F XXXX R15 5 0000 0000H Of 16 registers the following registers are provided for special applications with some instructions being enhanced R13 Virtual accumulator R14 Frame pointer e R15 Stack pointer The initial values of RO to R14 after resetting are undefined The initial value of R15 is 00000000 SSP value 35 CHAPTER 2 CPU 2 3 2 Special Registers The special registers are used for special purposes They are the program counter PC program status PS table base register TBR return pointer RP system stack pointer SSP user stack pointer USP and multiplication division result register MDH MDL Special Registers Figure 2 3 4 shows the configuration of special registers Figure 2 3 4 Configuration of Special Registers Initial value Program counter PC XXXX XXXX4 undefined Program status PS Table base
286. it are set to 1 the CRB refresh operation is performed bit 1 and 0 CKS ClocK Select bit The CKS bits select a clock source for the downward counter The downward counter uses the divide by 32 output of the timebase timer as a clock CKS1 CKSO Source clock Maximum number of clocks initial value 26 REL5 0 6 bits x 32 divide by 32 output 2048 value 0 8 26 REL5 0 6 bits x 32 divide by 32 output x 8 16384 reserved reserved 131 CHAPTER 4 BUS INTERFACE 4 12 External Pin Control Register 0 EPCRO External pin control register 0 EPCRO controls the output of each signal When output is permitted this register outputs a desired timing signal in each bus mode When the input is valid it receives an input signal from the outside When output is inhibited or the input is invalid the register be used as an 1 0 port B Configuration of External Pin Control Register 0 EPCRO External pin control register 0 EPCRO is configured as follows 15 14 13 12 11 10 9 8 EPCRO Initial value Access Address 0000 06284 WRE RDXE RDYE BRE 1100 W 7 6 5 4 3 2 1 0 Initial value Access COE5 4 COE3 COE2 COE1 COEO 1111111 W Bit Functions of External Pin Control Register 0 EPCRO bit 11 WRE WRite pulse output Enable bit The WRE bit specifies whether to output the WROX to WR1X write pulses When this bit is rese
287. ition and Subtraction Instructions Mnemonic ADD Rij Ri ADD 55 Ri ADD i4 Ri ADD2 i4 Ri Operation Ri Rj Ri Ri s5 gt Ri Ri extu i4 gt Ri Ri extu i4 gt Ri Remarks Upper 1 bit is read as a code by the assembler Zero expansion Negative expansion ADDC Rj Ri Ri Rj gt Ri Addition with carry over ADDN Rj Ri ADDN s5 Ri ADDN 4 Ri ADDN2 i4 Ri O oo Ri Rj gt Ri Ri s5 gt Ri Ri extu i4 gt Ri Ri extu i4 gt Ri Upper 1 bit is read as a code by the assembler Zero expansion Negative expansion SUB Ajj Ri Rj gt Ri SUBC Rj Ri gt gt OOO Ri Rj c gt Ri Subtraction with carry over SUBN Rj Ri Compare Operation Instructions Table E 1 2 Compare Operation Instructions Mnemonic Ajj Ri CMP 455 Ri 14 Ri 2 14 Ri 410 gt Ri Rj gt Ri Operation Ri Rj 55 Ri extu i4 Ri extu i4 Remarks Upper 1 bit is read as a code by the assembler Zero expansion Negative expansion APPENDIX E Instructions Logical Operation Instructions Table E 1 3 Logical Operation Instructions Mnemonic Rj Ri Rj Rj Rj Operation Remarks Word Word Half word Byte Rj Ri Rj Rj Rj Word Word Half word Byte
288. kkkkkkkkkkkkkkkkkkkkkkkkkkkkkk Load Setting Idi 20 Idi 20 Idi 8 Idi 8 Idub Idub st stilm and beq bra CHC_0 borl Data GCR RO PCTR R1 GCR_MASK R2 PCTR_MASK R3 R0 R4 R1 R5 PS R15 0x0 R4 R2 CHC 0 CHC_1 0001B r0 GCR_MASK 0000 0001 b PCTR_MASK 0000 1000 b read GCR register read PCTR register push processor status disable interrupt to 1 2 clock r0 GCR register Input of divide by two clock DBLON CPU 1 2 1 DBLACK Input of PLL clock 0 m Peripheral PLL i 50MHz SLCT1 0 GCR register 0 1 VSTP 1 2 0 0 STAND BY 25MHz PCTR register 1 2 12 5MHz 109 CHAPTER 3 CLOCK GENERATOR AND CONTROLLER CHC_1 call VCO_RUN PLL_SET_END Id R15 PS pop processor status VCO Setting VCO_RUN st R3 R15 push R3 ldi 8 PCTR_MASK R3 PCTR MASK 20000 1000 b and R5 R3 PTCR gt VSTP 1 beq 10005 END if VSTP 0 return bandi 0111B r1 set VSTP 0 st R2 R15 push R2 for Loop counter 19 20 R2 wait 100 uS WAIT 100US 100us 160 5 6 25 2 7 100 2BC cycle add2 1 R2 2BCh 2 15Eh if cache on bne WAIT 100US 10005 END R15 R2 Pop R2 Id R15 R3 Pop R3 ret 110 CHAPTER4 BUS INTERFACE This chapter explains the basic items of the external bus interface register configuration and functions bus operations and bus timing and provides bus operation program samp
289. l of this signal can be read from the RDY bit of the flash memory status register When the RDY bit is 0 the automatic algorithm performs a write or read and another Read or Erase command cannot be accepted Data cannot be read from a flash memory address either Data read when the RDY bit is 0 determines the setting of a hardware sequence flag indicating flash memory status see Section 16 6 Starting the Automatic Algorithm B Interrupt Control When the automatic algorithm sequence ends an interrupt request can be issued to the CPU thereby making it possible to quickly recognize the end of an automatic algorithm sequence that has continued for an extended period The RDYINT and INTE bits of the flash memory status register control the interrupt at the end of the automatic algorithm The RDYINT bit is an interrupt flag set at the end of the automatic algorithm When the rising edge of the internal Ready or Busy signal RDY BUSYX from 0 to 1 is detected the interrupt flag is set to 1 When the INTE bit is 1 and the RDYINT bit is set an interrupt request is output to the CPU When canceling the interrupt request set the RDYINT or INTE bit to O B Writing by ROM Writer This flash memory enables writing by a device external ROM writer During writing by a device external ROM writer the pin functions equivalent to the functions of the single flash memory MBM29LV200 are assigned to the external pins
290. l9 PC 2 2 gt rel8 Label12 and label9 are signed When RETI is executed the S flag must be 0 415 APPENDIX E Instructions B Delayed Branch Instructions Table E 1 12 Delayed Branch Instructions Mnemonic Operation Remarks JMP D Ri gt PC CALL D label12 PC 4 gt RP PC 2 label12 PC 2 gt PC CALL D Ri PC 4 gt RP Ri gt PC RET D RP gt PC BRA D label9 PC 2 label9 PC 2 gt PC BNO D label9 Nonbranch BEQ D label9 if Z 1 then PC 2 label9 PC 2 gt PC BNE D label9 BC D label9 BNC D label9 BN D label9 BP D label9 BV D label9 BNV D label9 BLT D label9 BGE D label9 BLE D label9 BGT D label9 BLS D label9 BHED label9 s Z 0 s C s C 0 s N s N 0 s V s V 0 s V xor N s V xor N 0 s V xor N or Z s V xor N or Z 0 s C or Z s C or Z 0 Notes The assembler calculates and sets values in the rel11 and rel8 fields of the hardware specification as follows label12 PC 2 2 gt rel11 label9 PC 2 2 gt rel8 Label12 and label9 are signed The next instruction delay slot is executed before delayed branch is executed All 1 cycle instructions including the b c and d cycle instructions can be placed in the delay slot Instructions of two or more cycles cannot be placed 416 APPENDIX E Instructions Other Instructions Table E 1 13 Other Instructions Mnem
291. lect the target slave CPU so that the host CPU can start to communicate with it Normal data is sent when the A D bit of the SCR register is 0 Figure 10 10 2 shows a flowchart for this operation Since the parity check function cannot be used in this mode set the PEN bit of the SCR register to 0 263 CHAPTER 10 UART 264 Figure 10 10 2 Communication Flowchart for Mode 1 Host CPU Set transfer mode to 1 Set address data in DO to D7 to select the slave CPU and set A D to 1 then transfer one byte Set 0 in A D Enable the receive operation Communication with slave CPU 5 the communication finished Communicate wit another slave CP Disable the receive operation END 10 11 Setting Examples of Baud Rates and U TIMER Reload Values 10 11 Setting Examples of Baud Rates and U TIMER Reload Values Tables 10 11 1 and 10 11 2 are sample settings for baud rates and U TIMER reload values The frequencies in the tables indicate peripheral machine clock frequencies UCC1 indicates the value to set in the UCC1 bit of the U TIMER control register UTIMC A hyphen in the tables indicate that the corresponding value cannot be used because the error exceeds plus or minus 1 Sample Settings for Baud Rates and U TIMER Reload Values O Asynchronous start stop mode Table 10 11 1 Baud Rates and U TIMER Reload Values in Asynchronous Start Stop Mode Baud ra
292. les 4 1 Outline of Bus Interface 4 2 Chip Select Area 4 3 Bus Interface 4 4 Area Select Register ASR and Area Mask Register AMR 4 5 Area Mode Register 0 AMDO 4 6 Area Mode Register 1 AMD1 4 7 Area Mode Register 32 AMD32 4 8 Area Mode Register 4 AMD4 4 9 Area Mode Register 5 AMD5 4 10 DRAM Control Register 4 5 DMCR4 5 4 11 Refresh Control Register RFCR 4 12 External Pin Control Register 0 EPCRO 4 13 External Pin Control Register 1 EPCR1 4 14 DRAM Signal Control Register DSCR 4 15 Little Endian Register LER 4 16 Relationship between Data Bus Widths and Control Signals 4 17 Bus Timing 4 18 Internal Clock Multiplication Clock Doubler 4 19 Program Example for External Bus Operation 111 CHAPTER 4 BUS INTERFACE 4 1 Outline of Bus Interface The bus interface controls the interface between external memory and I O B Features of the Bus Interface 112 25 bit 32 megabytes address output 6 independent banks to be set by chip select function Capable of setting a bank an optional location in at least 64 kilobytes in the logical address space Capable of setting six 32 megabyte areas with address and chip select pins Capable of setting a 16 bit or 8 bit bus width for each chip select area Inserting programmable automatic memory wait 7 or less cycles Support of DRAM interface types of DRAM interface Double CAS DRAM usual DRAM interface Single CAS DRAM Hyper
293. level mask for 55 interval timer other 4 K K lib option specifying when using character string manipulation function 397 L L or H output from PWM 320 latchup 26 level mask for 55 linear 4 gigabyte memory space 30 little endian area allocating stack to 398 little endian register LER bit function of 138 little endian register LER configuration of 138 little endian outline 147 load ANG store tte hire ng 46 logical operation and bit manipulation 47 logical operation instruction 411 low power 30 LQFP 100 outside dimension 8 LQFP 100 pin arrangement 11 M manipulating data other than character array with character string munipulation function 397 mapping address of program used to put system into stop or sleep 91 MB91F109 memory 44 MB91F109 general block diagram of 6 MDEH MB
294. llation stabilizes Therefore do not set this bit to 0 before that See Section 3 10 1 Stop state for the procedure on returning from the stop mode and internal operation 3 7 Watchdog Timer Reset Delay Register WPR 3 7 Watchdog Timer Reset Delay Register WPR The watchdog timer reset delay register WPR clears the flip flop for the watchdog timer This register can be used to delay watchdog timer resets Configuration of Watchdog Timer Reset Delay Register WPR The configuration of the watchdog timer reset delay register WPR is shown below 07 06 05 04 03 02 01 00 Initial value Access Bit Functions of Watchdog Timer Reset Delay Register WPR Bits 07 to 00 D7 to DO When A54 and 5 are written successively to this register the flip flop for the watchdog timer is cleared to 0 immediately after is written to delay the watchdog timer reset The value read from this register is undefined There are no restrictions on the time between Ady and but the watchdog timer is reset if the writing of both data items is not finished within the time shown in Table 3 7 1 Because the flip flop is automatically cleared during the stop sleep or hold state the watchdog timer reset is delayed automatically when these conditions occur Table 3 7 1 Watchdog Timer Cycles Specified by WT1 and WTO Minimum WPR write interval Time from last 5AH writing to WPR required to suppress the to watchdog timer reset
295. llows 7 6 5 4 3 2 1 0 DSCR Initial value Access Address 0000 0625 DW1E DWOE C1HE COHE COLE RS1E RSOE 00000000 WwW Bit Functions of DRAM Signal Control Register DSCR bit 7 DW1E The DW1E bit controls the DW1X output When this bit is reset the output is inhibited 0 Inhibits output initial value 1 Permits output bit 6 DWOE The DWOE bit controls the DWOX output When this bit is reset the output is inhibited 0 Inhibits output initial value 1 Permits output bit 5 C1HE The C1HE bit controls the CS1H output When this bit is reset the output is inhibited In this device type because the CS1H pin also serves as the DMAC DACK2 output it is controlled together with the AKSE2 and AKDE2 bits of the DMAC control register DATCR as shown below Port initial value C1HE output DACK output DACK output DACK output bit 4 C1LE The C1LE bit controls the CS1L output When this bit is reset the output is inhibited 0 Inhibits output initial value 1 Permits output 136 4 14 DRAM Signal Control Register DSCR bit 3 COHE The COHE bit controls the CSOH output When this bit is reset the output is inhibited 0 Inhibits output initial value 1 Permits output bit 2 COLE The COLE bit controls the CSOL output When this bit is reset the output is inhibited 0 Inhibits output initial value 1 Permits output bit 1 RS1E Th
296. lt in module of the MB91F109 that implements direct memory access DMA B DMAC Characteristics Eight channels Three modes Single block transfer burst transfer and continuous transfer Transfers from the total address area to the total address area Transfer frequency of up to 65 536 pulses Transfer end interrupt function Transfer address increment decrement selectable by software Three external transfer request input pins three external transfer request acknowledgment output pins and three external transfer end output pins B DMAC Registers Figure 15 1 1 shows the DMAC registers 324 Figure 15 1 1 DMAC Registers Inside DMAC DMAC internal registers 31 0 oco Je oma oce Joe On RAM DMA descriptors 31 0 DPDP DPDP 4 0CH descriptor 15 1 Overview of DMAC B DMAC Block Diagram Figure 15 1 2 is a DMAC block diagram Figure 15 1 2 DMAC Block Diagram Edge level DACKO0 2 DREQO 2 detection circuit 2 Sequencer Interrupt request Internal resource transfer request Data buffer Switcher DPDP DACSR DATCR bi Mode Data bus BLK DEC BLK INC DEC 325 CHAPTER 15 DMAC 15 2 DMAC Parameter Descriptor Pointer DPDP The DMAC parameter descriptor pointer DPDP is an internal register of the DMAC and is used to store the first address of the DMAC descriptor table in RAM DPDP bits 6 to 0 are always 0 and the first address of the descript
297. m ere ettet et tef 4 clock doubler function disabling 105 clock doubler function 105 clock doubler function note on enabling or Nee ee es 106 clock generator and controller block diagram 75 clock generator and controller register of 74 clock system reference diagram 109 clock how to 194 code used in timing 342 command operation 361 communication end 259 communication start 259 compare operation instruction 410 condition code register 39 connection to external device example of 146 150 continuous conversion mode 276 continuous transfer 340 continuous transfer mode 336 continuous transfer mode for 16 8 bit data transfer stop in both address are unchanged 348 INDEX continuous transfer mode for 16 8 bit data transfer stop in either address is unchanged 347 control register esee 236 control status register ADCS bit function of 270 control status register ADCS conf
298. mode mode 1 or CLK synchronous communication mode mode 2 bit 3 A D Address Data This bit specifies the data format of frames that are transmitted in multiprocessor mode mode 1 for asynchronous start stop communication 0 Data frame Initial value 1 Address frame bit 2 REC Receive Error Clear Setting this bit to 0 clears the error flags PE ORE and FRE of the SSR register Operations for setting this bit to 1 are invalid The value read from the bit is always 1 bit 1 RXE Receiver Enable This bit controls UART receive operation 0 Disable UART receive operation Initial value 1 Enable UART receive operation lt Note gt If the UART receive operation is disabled during reception processing while data is input to the reception shift register the receive operation is stopped when the reception of the current frame is completed and the received data is stored in the receive data buffer SIDR register bit 0 TXE Transmitter Enable This bit controls UART transmit operation 0 Disable UART transmit operation Initial value 1 Enable UART transmit operation lt Note gt If the UART transmit operation is disabled during transmission processing while data is output from the transmit register the transmit operation is stopped when no data is left in the transmission data buffer SODR register 251 CHAPTER 10 UART 10 4 Serial Input Data Register SIDR and Serial Output Data Register SODR
299. n name Function During sleep P Previous status retained F CLK output During stop HIZX 0 P F Previous status retained P Previous status retained F Previous value retained 2 Same as left during refresh 1 P Previous status retained F Previous value retained P Previous status retained F Previous value retained P Previous status retained F Previous value retained 2 Same as left during refresh 1 P Previous status retained F Previous value retained P Previous status retained F Previous value retained P Previous status retained F Previous value retained 2 Same as left during refresh 1 0 3 0 2 5 2 DREQO DREQ1 DACKO DACK1 510 TRGO 500 TRG1 Previous status retained HIZX 1 Output Hi Z Input fixed to 0 Input possible Input possible Previous status retained Bus release BGRNT CLK Output Reset time CLK Output P Previous status retained F Previous value retained 2 Previous status retained Previous value retained Previous value retained Previous status retained Previous value retained Previous status retained Output Hi Z Input allowed for all pins 391 APPENDIX C Pin Status for Each CPU Status Table C 4 Pin
300. nables the reload mode When the counter value underflows from 00004 to FFFFy in reload mode the value in the reload register is loaded to the counter and the counter continues counting When the counter value underflows 0000 to FFFFy while the bit is 0 the counter stops counting 284 12 2 Control Status Register TMCSR bit 3 INTE This is an interrupt enable bit When the UF bit changes to 1 while this bit is 1 an interrupt request is issued No interrupt request is issued while this bit is 0 bit 2 UF This is a timer interrupt request flag which is set to 1 when the counter value underflows 0000 to FFFFy Setting the bit to 0 clears the flag Setting the bit to 1 has no effect A Read Modify Write instruction reads 1 from this bit bit 1 CNTE This is a timer count enable bit Setting this bit to 1 makes the timer wait for a start trigger signal Setting the bit to 0 stops the counter bit 0 TRG This is a software trigger bit Setting the bit to 1 activates the software trigger which loads the value in the reload register to the counter to start counting Setting the bit to 0 has no effect A read instruction always reads from this bit The trigger input by this register works only when CNTE is 1 Nothing occurs when CNTE is 0 285 CHAPTER 12 16 BIT RELOAD TIMER 12 3 16 Bit Timer Register and 16 Bit Reload Register TMRLR The 16 bit timer register TMR i
301. nchanged For example if an internal peripheral component with an output is operating this output is not inhibited In case of an output to a port this output is retained The previous status is retained The output status immediately before this mode is entered is output unchanged Inputs are not inhibited either and are processed accordingly 383 APPENDIX C Pin Status for Each CPU Status Pin Status for Each CPU Status Table C 2 Pin Status for 16 bit External Bus Length and 2CA1WR Mode Pin name P20 to P27 Function During sleep Output retained or Hi Z During stop HIZX 0 Output retained or Hi Z Output retained Address output Output retained Address output P60 to P67 P Previous status retained F Address output P Previous status retained F Address output Previous status retained Previous status retained P Previous status retained F RDY input P F Previous status retained BGRNTX P Previous status retained F H output P F Previous status retained P Previous status retained F BRQ input P F Previous status retained Previous status retained Previous status retained P Previous status retained F H output P F Previous status retained Previous status retained H output P Previous status retained F CS output P Same as left F H output P Previous status retained
302. ncludes an external reference symbol an instruction is created as follows Bxcc false xcc is the exclusion condition of cc LDI 32 label32 Ri JMP false B 32 Bit Delayed Branch Macro Instructions Table E 1 17 32 Bit Delayed Branch Macro Instructions Mnemonic Operation Remarks CALL32 D label32 Ri Next instruction address 2 gt RP Ri Temporary register See Reference 1 label32 PC BRA32 D label32 Ri label32 gt PC Ri Temporary register See Reference 2 BEQ32 D label32 Ri if Z 1 then label32 gt PC Ri Temporary register See Reference 3 BNE32 D label32 Ri t s Z 0 BC32 D label32 Ri 1 s C BNC32 D label32 Ri 1 5 0 BN32 D label32 Ri t s N 1 BP32 D label32 Ri t s N 0 BV32 D label32 Ri t s V BNV32 D label32 Ri t s V 0 BLT32 D label32 Ri t S V xor N BGE32 D label32 Ri S V xor N 0 BLE32 D label32 Ri 1 S V xor or Z 1 BGT32 D label32 Ri 1 S V xor or Z 0 BLS32 D label32 Ri 1 s C or Z BHI32 D label32 Ri 1 s C or Z 0 Reference 1 CALL32 D 1 When label32 PC 2 is from 0x800 to 0x7fe an instruction is created as follows CALL D label12 2 When label32 PC 2 is outside of the range in 1 and includes an external reference symbol an instruction is created as follows LDI 32 label32 Ri CALL D Ri Reference 2 BRA32 D 1 When label32 PC 2 is from 0x100 to 0xfe an instruction is created as follows BRA D label9 2 When label32 PC 2
303. nd output address Bus access count lt Note gt Because the MB91F109 detects no misalignment even if the lower 2 bits of the address specified by the program for word access are 00 01 10 or 11 the lower 2 bits of the output address are set to 00 When these bits are 00 or 01 in half word access they are set to 00 and when the bits are 10 or 11 they are set to 10 143 CHAPTER 4 BUS INTERFACE O 16 bit bus width Figure 4 16 8 External Bus Access for 16 bit Bus Width A Word access PA1 PA0 00 b PA1 PA0 01 c PA1 PA0 10 d 1 0 11 gt 1 Output 1 0 00 gt 1 Output A1 A0 00 1 Output A1 A0 00 gt 1 Output A1 A0 00 2 Output A1 A0 10 2 Output 1 0 10 2 Output A1 A0 10 2 Output 1 0 10 MSB LSB 16bit B Half word access PA1 PA0 00 b PA1 PA0 01 c 1 10 d PA1 PA0 11 1 Output 1 0 00 gt 1 Output A1 A0 00 1 Output A1 A0210 gt 1 Output A1 A0 10 C Byte access PA1 PA0 00 b PA1 PA0 01 PA1 PA0 10 d PA1 PA0 11 1 Output 1 0 00 gt 1 Output A1 A0201 1 Output A1 A0210 gt 1 Output A1 A0 11 1 E 01 11 PA1 PAO Lower 2 bits of address specified by program Output A1 A0 Lower 2 bits of output address First byte location of output address Data byte location for access 1 to 2 Bus access count 144
304. ns at L unless a nonpage access or refresh cycle occurs The Q1 and Q4 wait cycles can also be set in the high speed page mode where the Q4 Q4W and Q5 cycles are repeated Usual DRAM interface Read Usual DRAM interface Write Usual DRAM read cycle Usual DRAM write cycle Automatic wait cycle in usual DRAM interface DRAM interface in high speed page mode Single DRAM interface The single DRAM interface handles a CAS access as one clock cycle by setting 0 in the DSAS bit of DMCR4 and DCMR5 1 in the HYPR bit When using this mode set 1 in the PAGE bit of DMCR4 and DMCR5 to enable the high speed page mode The single DRAM interface starts from the Q1 to Q2 cycle as with the usual DRAM interface When the Q4 cycle is entered the CAS signal is controlled for one cycle and a read write operation is performed This manual represents the Q4 cycle for a read operation by Q4SR and by Q4SW for a write operation Note that the page size 1CAS 2WE and 2CAS 1WE setting and Q1 wait cycle are similar to those of the usual DRAM interface Single DRAM interface Read Single DRAM interface Write Single DRAM interface Hyper DRAM interface The hyper DRAM interface handles a CAS access as one clock cycle and fetches an address before data in a read cycle thereby providing high speed DRAM access by setting 1 in the DSAS and HYPR bits of DMCR4 and DMCR5 Also set 1 in the PAGE bit to enable the high sp
305. nsfer request source enable interrupt requests and disable interrupts in the ICR of the interrupt controller The program sets the target DOEn bit of the DACSR to 1 This completes the setting for DMA Upon detection of a DMA transfer request input the DMAC requests bus control right from the CPU When the bus control right is transferred from the CPU the DMAC accesses three words of information of the descriptor through the bus While decrementing DMACT the DMAC performs a transfer based on the information stored in the descriptor as many times as specified by DMACT The DMAC outputs a transfer request acknowledgment signal during data transfer if external transfer request input is used When the decremented DMACT reaches 0 the DMAC outputs a transfer end signal during data transfer The DMAC increments or decrements SADR or DADR and writes the result together with the DMACT value back to the descriptor The DMAC returns the bus control right to the CPU The DMAC sets DACSR DEDn to 1 and causes an interrupt to the CPU if interrupts have been enabled The number of minimum required cycles per transfer is shown below on the assumption that the descriptor is stored in built in RAM data is transferred between external busses and the data length is counted in bytes When both transfer source and destination addresses are fixed 6 5 x n cycles When either the transfer source or destination addres
306. nterrupt request These bits are initialized to 0 by resetting These bits can be both read and written bit 28 24 20 16 12 8 4 0 DOEn DMA Operation Enable Each of these bits specifies whether to enable DMA transfer in the corresponding channel n 0 Disable DMA transfer 1 Enable DMA transfer DOEn is cleared when DMA transfer in the corresponding channel is completed If there are simultaneous attempts to clear DOEn because of the completion of transfer respectively a bus write operation setting has priority These bits are initialized to 0 by resetting These bits can be both read and written 15 4 DMAC Pin Control Register DATCR 15 4 DMAC Pin Control Register DATCR The DMAC pin control register DATCR is an internal register of the DMAC and is used to control the external transfer request input pins external transfer request acknowledgment output pins and external transfer end output pins Configuration of DMAC Pin Control Register DATCR The configuration of the DMAC pin control register DATCR is shown below 00000208H 23 22 21 20 19 18 17 16 LT Tue Tues eroe RW RW RW RW RW RW 15 14 13 12 11 10 9 tsn isto AKSE akoer rset EPDET RW RW RW RW RW RW G EN 3 2 1 0 RW RW RW RW RW RW Initial value B 0000 0000 0000 329 CHAPTER 15 DMAC B Bit Functions of DMA
307. o control standby operation and specify the oscillation stabilization wait time Configuration of Standby Control Register STCR The configuration of standby control register STCR is shown below 07 06 05 04 03 02 01 00 Initial value Access Bit Functions of the Standby Control Register STCR bit 07 STOP Writing 1 to this bit puts the system in a stopped state in which the internal peripheral clock internal CPU clock and oscillation are stopped bit 06 SLEP Writing 1 to this bit puts the system in sleep state in which the internal CPU clock is stopped If 1 is written to both bits 7 and 6 bit 7 is given priority and therefore the system is put ina stopped state bit 05 HIZX Putting the system in a stopped state with 1 written to this bit sets the device pins at high impedance bit 04 SRST Writing O to this bit generates a software reset request bit 03 02 OSC1 0 These bits specify the oscillation stabilization wait time The bits and the wait time selected by the bits have the relationships shown in Table 3 3 1 These bits are initialized by power on reset but are not affected by any other reset causes 78 3 3 Standby Control Register STCR Table 3 3 1 Oscillation Stabilization Wait Time Specified by OSC1 and OSCO Oscillation stabilization wait time 215 217 9 219 221 Initial value is twice as large as XO when CHC is 1 and is
308. o the peripherals that permit an interrupt request to occur even in the stop state Applying the L level to the RSTX pin Since all internal clocks are stopped in the stop state internal peripherals other than those that cause an interrupt to return remain stopped B Outline of Sleep State In the sleep state the CPU clock and internal bus clock are stopped Power consumption when CPU operation is not required can be suppressed to a certain degree Proceed as follows to transit to the sleep state Usingan instruction to write to the standby control register STCR Perform one of the following to to return to the operating state Interrupt request e Issue a reset cause Since the internal DMA clock and peripheral clock operate in the sleep state the sleep state can be canceled by causing an interrupt from any of the internal peripherals that use one of the two clock sources B Types of Operation in Standby Mode Table 3 10 1 lists the types of operations performed in standby mode Table 3 10 1 Types of Operation in Standby Mode Operating status Cancel method Internal clock DMA peripheral Transition Oscillator condition Peripheral CPU internal bus Active Active 90 Y Operating X Stopped 3 10 Standby Mode Low Power Consumption Mechanism When STCR HIZX is 0 the previous state is held Setting HIZX to 1 puts the pin to Hi Z lt Note gt Res
309. ock Figure 6 7 1 NMI Request Detection Block NMI request Q SX Detection of NMIX canceling the stop state EE falling edge 218 uk STOP clear RST interrupt acknowledge lt Note gt Since the interrupt cause is automatically cleared when NMI is accepted DMA cannot be controlled When the NMI is accepted DMA is retransferred and when DMA transfer is finished NMI processing is performed CHAPTER7 DELAYED INTERRUPT MODULE This chapter provides an overview of the delayed interrupt module and explains the register configuration and functions and the operations of the delayed interrupt module 7 1 Overview of Delayed Interrupt Module 7 2 Delayed Interrupt Control Register DICR 7 3 Operation of Delayed Interrupt Module 219 CHAPTER 7 DELAYED INTERRUPT MODULE 71 Overview of Delayed Interrupt Module The delayed interrupt module causes an interrupt for changing a task Software can use this module to issue or cancel an interrupt request to the CPU Delayed Interrupt Module Register Figure 7 1 1 shows the delayed interrupt module register Figure 7 1 1 Delayed Interrupt Module Register bit7 6 5 4 3 2 1 0 Address 00000430H DLYI DICR B Delayed Interrupt Module Block Diagram Figure 7 1 2 is a delayed interrupt module block diagram Figure 7 1 2 Delayed Interrupt Module Block Diagram
310. ode Stop bit length Asynchronous start stop normal 1 bit or 2 bits mode Asynchronous start stop multiprocessor mode CLK synchronous mode UART Clock Selection O Internal timer When the U TIMER is selected while CSO is set to 0 the baud rate is determined by the reload value set for the U TIMER The baud rate is calculated as follows e Asynchronous start stop 6 16 x p e CLK synchronous 9 Peripheral machine clock frequency B Cycle set by the U TIMER 2n 2 or 2 3 where n is a reload value The baud rate for transmission in asynchronous start stop mode can range from 1 to 1 of the determined baud rate 255 CHAPTER 10 UART O External clock When the external clock is selected with 1 set in CSO the baud rate is determined as follows f is the external clock frequency e Asynchronous start stop 1 16 CLK synchronous f f can be up to 3 125 MHz 256 10 7 Asynchronous Start Stop Mode 10 7 Asynchronous Start Stop Mode The UART handles data of only NRZ nonreturn to zero format Data transfer begins with a start bit L level data for the specified number of data bits in LSB first mode and ends with a stop bit H level data When the external clock is selected always input the clock signal Format of Data Transferred in Asynchronous Start Stop Mode Figure 10 7 1 shows the format of data transferred in asynchronous start stop mode
311. of the MB91F109 Pin Arrangements QFP 100 Figure 1 4 1 QFP 100 Pin Arrangements isp ELE lt 58 5000565 Oon dungso0Q0Ebro naor amp p Li LU e e cOL i Sate oogorco amp lt lt lt lt lt gt gt lt lt 0000 0 XQO LO QN Q O O O O O CO OO CO CO CO CO CO CO PB2 CSOH PB3 DWOX EOP2 PB4 RAS1 DREQ2 PB5 CS1L DACK2 PB6 CS1H PB7 DW1X VCC PA6 CLK 5 55 4 54 EOP1 PA3 CS3X PA2 CS2X PA1 CS1X 0 50 VCC RSTX VSS MDO MD1 MD2 P80 RDY P81 BGRNTX P82 BRQ P83 RDX P84 WROX P85 WR1X P20 D16 P21 D17 P22 D18 O MB91F109 VIEW 100 06 vss 43 P23 D19 Loy 31 P24 D20 32 P25 D21 33 P26 D22 34 P27 D23 35 P30 D24 36 P31 D25 37 P32 D26 38 P33 D27 39 P34 D28 C 40 P35 D29 Ly 41 P36 D30 42 P37 D31 44 P40 A00 45 vcc C 46 P41 A01 47 42 02 48 P43 A03 C 49 P44 A04 50 10 SOO PF1 TRG1 SIO PFO TRGO ANS AN2 AN1 ANO AVSS AVRL AVRH AVCC 24 70 A23 P67 A22 P66 VSS A21 P65 A20 P64 A19 P63 A18 P62 A17 P61 A16 P60 A15 P57 A14 P56 A13 P55 A12 P54 A11 P53 A1
312. of the device and the FR CPU stops operation In CPU mode address line connections are changed and the mapping in the memory area changes For details refer to the specification of the corresponding ROM writer 353 CHAPTER 16 FLASH MEMORY 16 2 Block Diagram of Flash Memory Figure 16 2 1 is a block diagram of the flash memory Block Diagram of Flash Memory Figure 16 2 1 Block diagram of the Flash Memory Rising edge detection RDY BUSYX Flash memory 2Mbit 254K x 8 127K x 16 Control signal generation FA18 0 0115 0 0031 0 t g 5 INTE RDYINT Address buffer Data buffer 5 2 8 CD31 0 a FR C bus instruction data 354 16 3 Flash Memory Status Register FSTR 16 3 Flash Memory Status Register FSTR The flash memory status register FSTR indicates the operation status of the flash memory This register also controls interrupts to the CPU and writing to the flash memory Only the CPU can access this register Even if a writer is provided it cannot access this register Do not access this register with Read Modify Write instructions B Flash Memory Status Register FSTR The flash memory status register FSTR has the following structure bit during byte access initial value 0 O Undefined Undefined Undefined Undefined 0 Read Write RW RW R W R R W bit 7 INTE INTerrupt Enable The INTE bit controls inter
313. of transfer source Transfer destination Bit 31 to bit 16 of the transfer destination Bit 15 to bit O of the transfer source 342 15 9 DMAC Timing Charts 15 9 4 Timing Charts of the Descriptor Access Block This section shows timing charts of the descriptor access block Descriptor Access Block O Required pin input mode level descriptor address external A Be pO Fpl Og yO a Dg ES DREQn a es RICE S RR Adar pin Data pin 2H S RDXD es ee WI WRnX DACK pM EOP SSS ub O Required pin input mode level descriptor address internal A Interan KB CLK JUUUUUUUUUUUUUUUUUUUUUU DREQn eo ee Addr pin LXX 5__ Data pin lt 5 RDXD WRnX DACK 343 CHAPTER 15 DMAC O Required pin input mode edge descriptor address external A CLK WAL Aer Lee Eee Le Lae DREQn SS a Addr pin Data pin RDXD LTS WRnX ae DACK LTT EOP 1 0 ED O Required pin input mode edge descriptor address internal A CLK LAL LLL DREQn _ a X X XLXs Data pin lt 5 RDXD ST LH WRnX 4 lt Note gt The section from when a DREQn is generated to when the DMAC operation starts shows the case where the DMAC operation starts first The DMAC operation may be delay
314. on the information stored in the descriptor The DMAC outputs a transfer request acknowledgment signal during data transfer When decremented DMACT reaches 0 the DMAC outputs a transfer end signal during data transfer If the DMACT value is not 0 and a DMA request from a peripheral device remains the DMAC repeats step 6 via step 8 depending on the bus status When the DMACT value is 0 or the DMA requests from peripheral devices are canceled the DMAC increments or decrements SADR or DADR and writes the result together with the DMACT value back to the descriptor The DMAC returns the bus control right to the CPU 10 If the DMACT value is 0 the DMAC sets DACSR DEDn to 1 and causes an interrupt to the CPU if interrupts have been enabled The number of minimum required cycles per transfer is shown below on the assumption that the descriptor is stored in built in RAM data is transferred between external busses and the data length is counted in bytes When both transfer source and destination addresses are fixed 6 5 x n cycles When either the transfer source or destination are fixed 7 5 x n cycles When both transfer source and destination addresses are incremented or decremented 8 5 x n cycles 15 6 DMAC Transfer Modes Burst Transfer Mode 1 2 The initialization routine sets the descriptor The program initializes the DMA transfer request source To use the internal peripheral circuit as the tra
315. onic NOP Operation Remains unchanged Remarks ANDCCR u8 ORCCR u8 CCR 8 gt CCR CCR or u8 gt CCR u8 i8 gt ILM ILM immediate value setting ADDSP 510 1 R15 510 ADD SP instruction EXTSB Ri EXTUB Ri EXTSH Ri EXTUH Ri mmmm oO Code expansion 8 gt 32 bits Zero expansion 8 gt 32 bits Code expansion 16 gt 32 bits Zero expansion 16 gt 32 bits reglist reglist reglist 2 R15 gt reglist R15 increment R15 gt reglist R15 increment R15 gt reglist R15 increment Multiple load RO R7 Multiple load R8 R15 Multiple load RO R15 reglist reglist reglist 3 R15 decrement reglist gt R15 R15 decrement Reglist gt R15 R15 decrement reglist gt R15 Multiple store RO R7 Multiple store R8 R15 Multiple store RO R15 u10 4 R14 gt R15 4 R15 4 R14 R15 u10 R15 Entrance processing of function R14 4 gt R15 Exit processing of function R15 4 gt R14 Hj Ri Ri gt TEMP For semaphore management Rj gt Ri TEMP gt Rj 1 assembler converts 510 to 58 by calculating s10 4 then sets the value 58 S10 is signed 2 If a register from RO to R7 is specified reglist LDMO is created If a register from R8 to R15 is specified in reglist LDM1 is created Both LDMO and LDM1 may
316. ontrol Status Register PCNH PCNL The control status register PCNH PCNL is used to control the PWM timer or indicate the timer status Note that the register has a bit that cannot be rewritten during PWM timer operation Configuration of Control Status Registers PCNL The configuration of the control status register PCNH PCNL is shown below PCNH bit 15 14 13 12 11 10 9 8 Address 0 0000 6 1 0000 CNTE STGR MDSE RTRG CKS1 CKSO PGMS ch2 0000 ch3 0000 6 R W5 RW 4 R W3 R W2 R W1 R W 0 0 0 0 0 0 0 2 lt Initial value lt x x x x Attribute Rewriting enabled disabled during operation PCNL bit Address chO 0000 7 ch 0000 EGS1 EGSO IREN IRQF IRS1 IRSO OSEL ch2 0000F74 2 ch3 0000 RW RW RW RW RW RAW RW RW lt Attribute 0 0 0 0 0 0 0 0 lt Initial value x x lt Rewriting enabled disabled during operation Bit Functions of Conirol Status Registers PCNH PCNL bit 15 CNTE Timer enable bit This bit enables or disables the 16 bit decrementing counter Disable Initial value Enable bit 14 STGR Software trigger bit Setting this bit to 1 enables a software trigger A read instruction always reads 0 from this bit bit 13 MDSE Mode select bit This bit selects PWM operation that outputs continuous pulses or one shot operation that outputs a singl
317. ontrol pin Internal register External pin Control pin address 3 address 3 D31 D31 D31 D31 WR1X CASH WEH 153 CHAPTER 4 BUS INTERFACE Bus width Big endian mode Little endian mode 8 bit bus width Internal register External pin Control pin Internal register External pin Control pin address 0 address 0 D31 D31 D31 D31 AA WROX CAS WE AA WROXCAS WE D2 D2 Internal register External pin Control pin Internal register External pin Control pin address 1 address 1 D31 D31 D31 D31 BB WROXCAS WE BB WROX CAS WE D2 D2 Internal register External pin Control pin Internal register External pin Control pin address 2 address 2 D31 D31 D31 D31 cc WROX CAS WE WROX CAS WE D2 D2 Internal register External pin Control pin Internal register External pin Control pin address 3 address 3 D31 D31 D31 D31 DD WROX CAS WE DD WROX CAS WE D2 D2 154 4 16 Relationship between Data Bus Widths and Control Signals 4 16 4 DRAM Relationships This section explains the DRAM relationships DRAM Control Pins Table 4 16 2 lists the relationship between the pin functions and bus widths used in the DRAM interface Table
318. or that can be set is 128 bytes DMAC Parameter Descriptor Pointer DPDP The structure of the DMAC parameter descriptor pointer DPDP is shown below 31 7 6 0 ooooo200 00000 This register is not initialized by resetting The register can be read and written Use a 32 bit transfer instruction to access the register Ae Initial value 0000000 Initial value Undefined Each descriptor that specifies the operation mode of each channel is placed at the address specified by the DPDP Table 15 2 1 lists the addresses at which individual descriptors are placed Table 15 2 1 Channel Descriptor Addresses DMA Descriptor address channel DPDP 0 00H DMA channel Descriptor address DPDP 48 30H DPDP 12 OCH DPDP 24 18CH DPDP 72 48H DPDP 36 24H 326 DPDP 60 3CH DPDP 84 54H 15 3 DMAC Control Status Register DACSR 15 3 DMAC Control Status Register DACSR The DMAC control status register DACSR is an internal register of the DMAC that specifies control status information on the entire DMAC B Configuration of DMAC Control Status Register DACSR The configuration of the DMAC control status register DACSR is shown below 31 30 00000204H 29 28 27 26 25 R W R W R W R W R W R W R W R W 24 23 22 21 20 19 18 17 16 R W R W R W R W R W R W R W R W 15 14 13 12 11 10 8 R W R W R W 9 IE2 R W R W R W R W
319. orarily Stop Erase and Restart Erase commands can be entered with any address When a Temporarily Stop Erase command is entered during sector erase operation the flash memory needs a maximum of 20 us to stop the erase operation When flash memory enters temporary erase stop mode a Ready or Busy signal is output bit 7 outputs 1 and bit 6 stops to toggle For checking whether the erase operation has stopped enter the address of the sector whose data is being erased and read the values of bit 6 and bit 7 At this time another Temporarily Stop Erase command entry is ignored When the erase operation stops flash memory enters the temporary erase stop and read mode Data reading is enabled in this mode for sectors that are not subject to temporary erase Other than that there is no difference from the standard read operation In this mode bit 2 toggles for consecutive reading operations from sectors subject to temporary erase stop see Hardware sequence flag in Section 16 7 Execution Status of the Automatic Algorithm After the temporary erase stop and read mode is entered the user can write to flash memory by writing a Write command sequence The write mode in this case is the temporary erase stop and write mode In this mode data write operations become valid for sectors that are not subject to temporary erase stop Other than that there is no difference from the standard byte writing operation In this mode bit 2 toggles for consecuti
320. ormed during temporary sector erase stop flash memory outputs 1 if the address indicated by the address signal is included in the sector in erase state If the address is not included in the sector in erase state flash memory outputs the data of bit 7 of the read value at the address indicated by the address signal For checking whether a sector is in temporary sector erase stop state and when determining which sector is in erase state read toggle bit 6 which is described later Note When the automatic algorithm approaches the end of its operation bit 7 data polling asynchronously varies during a read operation which means that flash memory outputs operation status information to bit 7 and then outputs the determined data When flash memory terminates the automatic algorithm or bit 7 is outputting the determined data the data of the other bits is undefined The data of the other bits is read during the execution of consecutive read operations bit 6 TOGGLE Toggle bit Automatic write erase operation status When consecutive read operations are performed during the execution of the automatic write or erase algorithm flash memory outputs the 1 and O toggle results to bit 6 When the automatic write or erase algorithm ends bit 6 stops to toggle for a consecutive read and outputs valid data The toggle bit becomes valid after the last write cycle of each command sequence If a write target sector is protected from overwrit
321. ot used when interrupts are enabled INTE 1 the INT bit is not cleared and therefore the data protection function works and puts the A D converter in the stopped state In this case clearing the INT bit in the interrupt sequence releases the A D converter from the stopped state If interrupts are disabled while the A D converter pauses in DMA operation mode the A D converter works and may update the data register before previous data is transferred Restarting the A D converter in stopped state may lead to loosing the held data Figure 11 5 1 shows the Workflow of the data protection function when DMA transfer is used 11 5 Conversion Data Protection Function Figure 11 5 1 Workflow of the Data Protection Function when DMA Transfer is Used Set DMAC V Start of continuous A D conversion End of cycle of conversion V Store conversion data in data register The workflow for A D converter termination is omitted V End of 2nd cycle of conversion 5 Store conversion data in data register Y _ End of third conversion v Continue End of last Start DMAC Stop A D converte gt iemlporarily lt YES NO Start DMAC Start DMAC conversion End and transfer DMAC end interrupt routine V Stop A D
322. otes Asserting starting the start bit UTST in the stop state automatically causes reloading Asserting the clear bit UTCR and start bit UTST simultaneously in the stop state clears the counter to 0 and causes an underflow at the following count down Asserting the clear bit UTCR during operation clears the counter to 0 and may cause short whisker like pulses in the output waveforms which may result in a UART or high order U TIMER malfunction in cascade mode When the output clock is used do not assert the clear bit during operation If 0 or 1 is set the low order reload register U TIMER in cascade mode the timer does not count normally 9 3 U TIMER Operation 9 3 U TIMER Operation This section explains how to calculate the U TIMER baud rate and also explains the cascade mode B Calculating the Baud Rate The UART uses the underflow flip flop f f in the figure of the corresponding U TIMER U TIMERx gt UARTx x 0 1 2 as the baud rate clock source O Asynchronous start stop mode The UART uses the U TIMER output by dividing it by 16 n UTIMR Reload value bps m2 x 16 UCC1 0 Peripheral machine clock frequency variable with the gear oe UCC1 1 2n 3 X 16 O CLK synchronous mode UTIMR Reload value bps _ ses UCC1 0 2 2 Peripheral machine clock frequency variable with the gear bps m ant UCC1 1 2 3 Cas
323. peration in sleep mode 340 double type and long double type using 397 DRAM control 155 DRAM control register 4 5 DMCR4 5 bit function of 127 DRAM control register 4 5 DMCR4 5 configuration 127 DRAM device connection example 158 DRAM 3 116 159 DRAM interface timing chart in high speed page 0 182 428 DRAM interface 160 DRAM interface single 160 DRAM interface 160 DRAM refresh 161 DRAM signal control register DSCR bit function Of cere rent 136 DRAM signal control register DSCR configuration 136 EIT Cause c efe oO RAPERE 52 EIT characteristic 52 EIT event acceptance priority for 62 EIT vector table 60 note iue ie Wee a ware 53 EIT return 52 emulator and monitor debuggers 402 enable interrupt request register ENIR 213 enhanced I O operation instruction 30 enhanced interrupt processing function 30 OLASC CHIP pe 362 error 2 42 2
324. pulation functions Specifying the option K lib when using a character string manipulation function Using the types double and long double Allocating a stack to a little endian area Allocating Variables with Initial Values Variables with initial values cannot be allocated to little endian areas The compiler has no function for creating the initial values of little endians While variables can be allocated to little endian areas their initial values cannot be set during assignment Set the initial values at the beginning of the program Example When setting an initial value for the variable little_data of the little endian area extern int little_data void little_init void little data Initial value void main void little init B Assigning Structures by Referencing Other Structures 396 When assigning structures by referencing other structures the compiler selects the optimum transfer method and performs a transfer for each byte half word and word If a structure is defined by referencing a structure variable allocated to a little endian area and another allocated to a non little endian area the correct result is not obtained Assign each structure member individually Example When assigning a structure to the structure variable little st in the little endian area struct tag char c int i normal st extern struct tag little st APPENDIX D Notes on Using Little Endian Areas define ST
325. puts pulses continuously PWM Operation Upon detection of a start trigger the PWM timer outputs pulses continuously The cycle of output pulses can be controlled by changing the PCSR value and the duty ratio can be controlled by changing the PDUT value After writing data to the PCSR write to the PDUT lt Note gt When the external TRG input is selected for the start trigger input pulses with a pulse width that equals or exceeds the following minimum pulse width Pulse width Two machine cycles or more When pulses that do not satisfy the condition above are input ensure that they are recognized as effective pulses Since this model has no filter function for external TRG input add a filter to the external input as required Figure 14 9 1 shows a timing chart for PWM operation performed while trigger restart is disabled Figure 14 9 2 shows a timing chart for PWM operation performed while trigger restart is enabled 315 CHAPTER 14 PWM TIMER O Trigger restart disabled Figure 14 9 1 PWM Operation Timing Chart Trigger Restart Disabled trigger is ignored A rising edge is detected A Start trigger m n 0 PWM T Count clock cycle T m 1 PCSR value n PDUT value O Trigger restart disabled Figure 14 9 2 PWM Operation Timing Chart Trigger Restart Enabled A rising edge is detected PWM operation is restarted by a trigger
326. r7 r8 r1 r9 r2 110 r3 r11 r8 r4 r9 5 r10 6 r11 r7 CS5 address within the page CS5 address outside of the page CS1 data word load CS2 data half word load CS4 data word load CSA data byte load CS4 data word store CS5 data half word store CS5 data word store CS5 data byte store 199 CHAPTER 4 BUS INTERFACE 200 5 I O PORTS This chapter outlines the I O ports and explains the register configuration and the requirements for using external pins as I O pins 5 1 Outline of I O Ports 5 2 Port Data Register PDR 5 3 Data Direction Register DDR 5 4 Using External Pins as I O Ports 201 CHAPTER 5 I O PORTS 51 Outline of I O Ports When a resource is not allowed to use the corresponding pin as an I O the MB91F109 allows the pin to be used as I O port B Basic Block Diagram of I O Ports Figure 5 1 1 shows the basic I O port configuration Figure 5 1 1 Basic I O Port Block Diagram Data Bus Resource input 0 9 PDR read 0 PDR 2 Resource output 1 Resource output permission DDR PDR Port Data Register DDR Data Direction Register B I O Port Registers I O ports are composed of a port data register PDR and a data direction register DDR O Input mode DDR 0 PDR read Reads the outp
327. racteristics Full duplex double buffer Support of both asynchronous start stop and CLK synchronous communication Support of multiprocessor mode Fully programmable baud rate Any baud rate can be set using the built in timer See Section 9 3 U TIMER Operation Support for setting any baud rate using external clocks Error detection function parity errors framing errors and overrun code for transfer signal e Support for starting DMA transfer by an interrupt UART Registers Figure 10 1 1 shows the UART registers Figure 10 1 1 UART Registers 15 8 7 0 SMR R W SIDR R SODR W R W 7 6 5 4 3 2 1 0 Serial input data oe etal output D7 D6 D5 D4 D3 D2 D1 DO data register SIDR SODR SIDR SODR 7 6 5 4 3 2 1 0 PE FRE TDRE RIE TIE register 7 6 5 4 3 2 1 0 Serial mode register 7 6 5 4 3 2 1 0 SBL CL AD REC RXE TXE ca register 246 UART Block Diagram Figure 10 1 2 is a UART block diagram Control From U TIMER gt External clock signal Clock selection circuit Figure 10 1 2 UART Block Diagram 10 1 Overview of UART Reception interrupt to CPU Transmission clock SC clock Transmision interrupt Reception clock Reception control circuit Start bit SI received data detection circuit Reception
328. ransmission begins the TDRE flag is set again so that the next instance of transmission data can be written If the TIE bit bit 0 of the same SSR register has been set to 1 a transmitter interrupt occurs in the CPU and a request to write transmission data to the SODR register is issued The TDRE flag is cleared when data is written to the SODR register 257 CHAPTER 10 UART 10 8 CLK Synchronous Mode The UART handles only data of NRZ nonreturn to zero format Figure 10 8 1 shows the relationship between the transmission reception clock and the data Format of Data Transferred in CLK Synchronous Mode Figure 10 8 1 Format of Data Transferred in CLK Synchronous Mode Mode 2 SODR write Mark SC RXE TXE 51 50 oe LSB NSB ers Mode 2 The transferred data item is 01001101 When CSO is set to 0 to select U TIMER output transmitting data automatically generates synchronizing clock pulses for receiving data When the external clock is selected clock pulses of exactly one byte must be supplied after ensuring that there is data in the transmission data buffer SODR register of the UART on the transmitting end The TDRE flag is 0 The mark level before and after transmission must also be ensured The data length can only be eight bits and no parity bit can be added Since no start and stop bits are used only overrun errors are detected O Initialization The values
329. rap occurs when a coprocessor instruction that uses the coprocessor is executed afterwards No coprocessor is installed in this product Operation SSP 4 gt SSP PS gt SSP SSP 4 gt SSP Next instruction address gt SSP 0 gt S flag TBR 3DC gt Operation for Instruction The RETI instruction is used to return from the EIT processing routine Operation R15 PC R15 4 gt R15 R15 gt PS R15 4 gt R15 The RETI instruction must be executed while the S flag is 0 67 CHAPTER 2 CPU 2 9 Reset Sequence This section explains CPU resetting Causes of Resetting The causes of resetting are as follows Input from an external reset pin Software reset by manipulation of the SRST bit of standby control register STCR Expiration of watchdog timer Power on reset E Initialization by Resetting When a cause for resetting occurs the CPU is initialized O Releasing from the external reset pin or software reset The pin is set to the predetermined state Each resource in the device is put in the reset state The control register is initialized to the predetermined value The lowest gear is selected for the clock frequency B Reset Sequence After the cause of resetting is cleared the CPU executes the following reset sequence e 000FFFFCj gt PC Note After the CPU is reset the operation mode is defined in details using the mode register
330. re 4 18 1 shows example of a 2X clock timing chart Figure 4 18 2 shows an example of a 1X clock timing chart Figure 4 18 1 Example of Timing Chart for 2X Clock BW 16bit Access Word Read Internal clock Internal instruction address Internal instruction CLK output External address bus External data bus External RDX External fetch instruction fetch Prefetch 194 Figure 4 18 2 Example of Timing for 1X Clock BW 16bit Access Word Read Internal clock Internal instruction address Internal instruction CLK output External address bus External data bus External RDX 4 18 Internal Clock Multiplication Clock Doubler XN External fetch instruction fetch Prefetch 195 CHAPTER 4 BUS INTERFACE 4 19 Program Example for External Bus Operation This section provides a simple program example for external bus operation Program Specification Examples for External Bus Operation Register settings are as follows Areas Area 0 AMDO 16 bits usual bus automatic wait 0 Area 1 AMD1 16 bits usual bus automatic wait 2 Area 2 AMD32 16 bits usual bus automatic wait 1 Area 3 AMD32 16 bits usual bus automatic wait 1 Area 4 AMD4 16 bits DRAM pag
331. red gear ratio for peripheral clock control can be set by setting the PCK1 and PCKO bits of the same register to the desired values 87 CHAPTER 3 CLOCK GENERATOR AND CONTROLLER 88 Example LDI 20 LDI 8 STB LDI 8 STB LDI 8 STB LDI 8 STB LDI 8 STB GCR R2 11111110b R1 R1 R2 01111010b R1 R1 R2 00111010b R1 R1 R2 001 10010b R1 R1 R2 10110010b R1 R1 R2 CCK 11 PCK 11 CHC 0 CPU clock 1 8f Peripheral clock 1 8f f direct 01 10 0 CPU clock 1 2f Peripheral clock 1 4f f direct CCK 00 PCK 10 CHC 0 CPU clock f Peripheral clock 1 4f f direct CCK 00 PCK 00 CHC 0 CPU clock f Peripheral clock f f direct CCK 10 PCK 00 CHC 0 CPU clock 1 4f Peripheral clock f f direct The output from the divide by two frequency circuit can be selected as the source clock by setting the CHC bit of the gear control register to 1 Setting the CHC bit to 0 selects the clock having the same cycle as the clock generated from the oscillation circuit Since the source clock is changed the CPU and peripheral systems change simultaneously Example LDI 8 LDI 20 STB LDI 8 STB LDI 8 STB 01110001b R1 GCR R2 R1 R2 00110011b R1 R1 R2 00110010b R1 R1 R2 CCK 01 PCK 00 CHC 1 CPU clock 1 2f Peripheral clock f f 1 2xtal CCK 00 PCK 00 CHC 1 CPU clock f Peripheral clock f f 1 2xtal CCK 00 PCK 00 CHC 0 CPU clock f Peripheral clock f f direct Figure 3 9 2 is a timing c
332. register 000000 2 W channel 2 cycle setting register 000000 4 W channel 2 duty cycle setting register 000000 6 channel 2 control status register 000000 8 R channel 3 timer register 000000 W channel 3 cycle setting register 000000FCH W channel 3 duty cycle setting register 000000 R W channel 3 control status register 301 CHAPTER 14 PWM TIMER 14 2 PWM Timer Block Diagram Figure 14 2 1 is a general block diagram of the PWM timer Figure 14 2 2 is a block diagram of a single PWM timer channel General Block Diagram of PWM Timer 302 Figure 14 2 1 General Block Diagram of PWM Timer 16 bit reload TRG input PWM timer timer chO cho 16 bit reload timer ch1 TRG input PWM timer ch1 General control register 2 source selection TRG input PWM timer ch2 General control register 1 External TRGs 0 to 3 TRG input PWM timer ch3 PWMO PWM1 PWM2 PWM3 14 2 PWM Timer Block Diagram Block Diagram of Single PWM Timer Channel Figure 14 2 2 Block Diagram of Single PWM Timer Channel PCSR PDUT Prescaler cmp ck Load 16 bit decrementing counter Start Borrow PPG mask Peripheral clock Inverse bit Enable _ IRQ Edge detection interrupt selection TRG input Software trigger 303 CHAPTER 14 PWM TIMER 14 3 C
333. register TBR 000F FC00n Return pointer RP XXXX XXXX amp 4 undefined System stack pointer 0000 0000 User stack pointer USP XXXX undefined Multiplication division MO A result register MDL XXXX XXXXu_ undefined O Program counter PC The program counter indicates the address of the program being executed Bit 0 is set to 0 when the PC is updated according to instruction execution Bit 0 may be set to 1 only when an odd numbered address is specified for the branch destination address Even at this event bit 0 is invalid and an instruction must be put at an address consisting of a multiple of two The initial value after resetting is undefined 36 2 3 Programming Model O Program status PS The program status register holds the program status in three parts CCR SCR and ILM See Section 2 3 3 for more information The undefined bits are all reserved When the register is read 0 is always read from these bits No data can be written to this register O Table base register TBR The table base register holds the first address of the vector table used for EIT processing The initial value after resetting is OOOFFCOOw O Return pointer RP The return pointer register holds the address to which control returns from a subroutine When the CALL instruction is executed the PC value is transferred to the RP When the RET instruction is executed the RP value is transferred to the PC The ini
334. rei Re SX ae eade 193 4 18 Internal Clock Multiplication Clock Doubler sssseseeeeeneennmenene nnne nnne 194 4 19 Program Example for External Bus Operation ssssssssssseseeeeeeee enne nnns 196 CHAPTERS WO PORTS 2224 E Esau n eva to nua Ca aR wesssevecevacecenst 201 but O POrts acte e ne cH 202 52 PortiData Register PDR uiu ppt e rir ek e EE buit eerta 203 5 3 Data Direction Register DDR 204 5 4 Using External Pins as I O Ports ssssssssssssssssseseeeeneee nnne senem innen 205 CHAPTER6 EXTERNAL INTERRUPT NMI CONTROLLER 211 6 1 Overview of External Interrupt NMI Controller sese enne 212 6 2 Enable Interrupt Request Register 213 6 3 External Interrupt Request Register EIRR 214 6 4 External Level Register nennen nennen nnne nnn 215 6 5 External Interrupt Operation nennen nnne nnn 216 6 6 External Interrupt Request Levels 217 6 7 Nonmaskable Interrupt NMI 218 CHAPTER 7 DELAYED INTERRUPT MODULE 219 7 1 Overview of Delaye
335. reset source register and an instruction to branch to the appropriate program at the beginning of the program to be placed at the reset entry address 101 CHAPTER 3 CLOCK GENERATOR AND CONTROLLER Example RESET ENTRY 0 20 RSRR R10 LDI 8 10000000B R2 LDUB R10 R1 GET VALUE INTO R1 MOV Ri R10 R10 USED AS A TEMPORARY REGISTER AND R2 R10 WAS PONR RESET BNE PONR RESET LSR 1 R2 POINT NEXT BIT MOV R1 R10 R10 USED AS A TEMPORARY REGISTER AND R2 R10 WAS HARDWARE STANDBY RESET BNE HSTB RESET LSR 1 R2 POINT NEXT BIT MOV R1 R10 R10 USED AS A TEMPORARY REGISTER AND R2 R10 WAS WATCH DOG RESET BNE WDOG RESET lt Notes gt When the PONR bit is 1 assume that the contents of the other bits are undefined When it is required to check reset sources place a power on reset check instruction at the beginning Check instructions other than the instruction for power on reset checking can be placed anywhere Priorities are determined in the order of placement 102 3 13 DMA Suppression 3 13 DMA Suppression If an interrupt with a higher priority occurs during DMA transfer the FR series interrupts DMA transfer and branches to the corresponding interrupt routine This feature remains effective as long as an interrupt request continues When the interrupt cause is cleared the suppression feature is canceled and DMA transfer resumes in the interrupt processing routine It a DMA transfer
336. returning 96 sleep state transition 95 source oscillation at power on input of 27 special register 33 36 SSBP iis aie itur ebd dp beds 37 standard branch without delay instruction 415 standard branch macro instruction 20 bit 418 standard branch macro instruction 32 bit 420 standby control register STCR bit function of 78 standby control register STCR configuration of 78 431 INDEX standby mode stop or sleep state returning 234 standby mode state transition 98 standby mode type of operation 90 starting multiple PWM timer channel using 16 bit reload timer eter 322 starting multiple PWM timer channel via software 321 St p trace trap tette teris 50 step trace trap operation 2 66 stop controller block diagram 92 stop erase temporary 363 stop or sleep state mapping address of program used to put system into 91 stop state outline 90 stop state returning from 93 216 Stop state transition 40
337. riority When transition to the sleep state has been caused by a C bus RAM program do not use an interrupt but reset instead to return from the sleep state 97 CHAPTER 3 CLOCK GENERATOR AND CONTROLLER 3 10 3 Standby Mode State Transition Figure 3 10 3 is a standby mode state transition diagram B Standby Mode State Transition Figure 3 10 3 Standby Mode State Transition Power on Oscillation stabilization wait reset state Oscillation stabilization wait state Reset state Stop state Run state Sleep state 4 STCR register SLEP 1 5 Input of interrupt or NMI 6 STCR register STOP 1 End of oscillation stabilization wait time Cancel of reset state Input of reset E 2 3 98 3 11 Watchdog Function 3 11 Watchdog Function The watchdog function detects program crashes If A54 and 5A are not written to the watchdog reset postpone register within the specified time due to a program crash the watchdog timer issues a watchdog reset request Watchdog Controller Block Diagram Figure 3 11 1 is a watchdog controller block diagram Figure 3 11 1 Watchdog Timer Block Diagram Internal bus Timebase timer Timebase timer frequency division output Reset state transition request signal WTx Timebase timer frequency division setec output Edge sense
338. rocessing in half word or word units to optimize processing Therefore the processing for little endian areas is executed incorrectly When processing a little endian area using a character string manipulation function do not specify the option K lib Also do not specify the option 04 and K speed which include the option K lib B Using the Types Double and Long Double When variables of the types double and long double are accessed the upper and lower word are accessed respectively Therefore if double and long double type variables allocated to little endian areas are accessed the correct result cannot be acquired Variables of the same type allocated to little endian areas can be assigned to each other As a result of optimization however these assigned variables may be replaced with constants 397 APPENDIX D Notes on Using Little Endian Areas Do not allocate double and long double type variables to little endian areas Example of incorrect processing Transfer of double type data double big 1 0 Big endian area extern int little Little endian area little big Transfer of double type data The execution result of the above transfer is rendered incorrect by the transfer of double type data as follows Big endian area Little endian area 5 meinen m Tm m Allocating a Stack to Little Endian Area If some part or the
339. rom time to time while the corresponding external interrupt is enabled Therefore it is needed to stop output by other functions except when such output is performed intentionally PEO 1 General purpose I O ports CHAPTER 1 OVERVIEW Table 1 5 3 Pin Functions 3 5 Pin name circuit Function format INT2 SC1 PE2 INT2 Input of external interrupt request This input is used from time to time while the corresponding external interrupt is enabled Therefore it is needed to stop output by other functions except when such output is performed intentionally SC1 UART1 clock I O Clock output can be used when UART1 clock output is enabled PE2 General purpose I O port This function is valid when UART1 clock output is disabled INT3 SC2 PE3 INT3 Input of external interrupt request This input is used from time to time while the corresponding external interrupt is enabled Therefore it is needed to stop output by other functions except when such output is performed intentionally SC2 UART2 clock I O Clock output can be used when UART2 clock output is enabled General purpose I O port This function is valid when UART2 clock output is disabled Table 1 5 4 Pin Functions 4 5 Pin name I O circuit Function format 75 DREQO PE4 F DREQO 1 Input of DMA external transfer request 76 DREQ1 PE5 This input is used from time to time when this pin is selected for the DMA
340. ronous mode Reserved Note In CLK asynchronous multiprocessor mode mode 1 multiple slave CPUs are connected to one host CPU This resource cannot recognize the format of received data and thus supports only the master in multiprocessor mode Since the parity check function cannot be used set PEN of the SCR register to 0 bit 5 4 reserved Always set these bits to 1 bit 3 CSO Clock Select This bit selects the UART operating clock 0 Built in timer U TIMER Initial value 1 External clock bit 2 reserved Always set this bit to 0 248 10 2 Serial Mode Register SMR bit 1 SCKE SCLK Enable When communication is performed in CLK synchronous mode mode 2 this bit specifies whether to use the SC pin as clock input pin or a clock output pin Set this bit to in CLK asynchronous mode or external clock mode 0 Clock input pin initial value 1 Clock output pin lt Note gt To use the SC pin as a clock input pin set the CSO bit in advance to 1 to select the external clock bit 0 SOE Serial Output Enable There is an external pin SO that is also designed to be used for a general purpose I O port pin This bit specifies whether to use the external pin SO as a serial output pin or an I O port pin 0 General purpose I O port pin initial value 1 Serial data output pin SO 249 CHAPTER 10 UART 10 3 Serial Control Register SCR The serial control re
341. ror This device supports no parity function Be sure to set this bit to 0 Bus Width Combinations Table 4 10 2 lists the combinations of bus widths available in areas 4 and 5 Table 4 10 2 Combinations of Bus Widths Available in Areas 4 and 5 Combination Usual 16 8 bits Usual 16 8 bits Usual 16 8 bits DRAM 16 bits C W 0 1 Usual 16 8 bits DRAM 8 bits C W 0 1 DRAM 16 bits C W 0 1 Usual 16 8 bits DRAM 16 bits C W 0 1 DRAM 16 bits C W 0 1 DRAM 16 bits C W 0 1 DRAM 8 bits C W 0 1 DRAM 8 bits C W 0 1 Usual 16 8 bits DRAM 8 bits C W 0 1 DRAM 16 bits C W 0 1 NI oa AJ Wy DRAM 8 bits C W 0 1 DRAM 8 bits C W 0 1 129 CHAPTER 4 BUS INTERFACE 4 11 Refresh Control Register RFCR The refresh control register RFCR controls the CBR CAS before RAS refresh operation when the DRAM interface is used This register has a 6 bit downward counter that uses the divide by 32 output of a timebase timer as a clock source and specifies a refresh interval by controlling its reload value by the RFCR Configuration of Refresh Control Register RFCR The refresh control register RFCR is configured as follows 15 14 13 12 11 10 9 8 Initial value RFCR REL5 4 REL3 REL2 REL1 RELO XXXXXX Address 0000 0626m 7 6 5 4 3 2 1 0
342. rrupt levels ILM is not changed either 54 2 8 EIT Exception Interrupt and Trap Flag The flag specifies whether to enable or disable interrupts It is provided at bit 4 of PS register CCR Disables interrupts The bit is cleared to 0 when the INT instruction is executed The value before the bit is cleared is saved to the stack Enables interrupts The masking of interrupt requests is controlled by the value held in the ILM Interrupt Level Mask Register ILM ILM is a part of the PS register bits 16 to 20 that holds an interrupt level mask value Of the interrupt requests input to the CPU only those with higher interrupt levels than the level indicated by the ILM are accepted The level values range in descending order from 0 000005 to 31 111118 The values that can be set from a program are limited When the original value is in the range from 16 to 31 a new value that can be set must be in the same range i e from 16 to 31 If an instruction that sets a value from 0 to 15 is executed the specified value 16 is returned When the original value is in the range from 0 to 15 a desired value from 0 to 31 can be set Note Use the SETILM instruction to set the level to the ILM register Level Mask for Interrupt NMI When an NMI or interrupt request is issued the interrupt level see Table 2 8 1 of the interrupt cause is compared with the level mask value indicated by the ILM The
343. rupts generated by the termination of the automatic algorithm in flash memory for a write erase operation etc This bit is initialized to 0 during a reset Read and write operations are enabled 0 disables issuing interrupts at termination of the automatic algorithm This is the initial value 1 enables issuing interrupts at termination of the automatic algorithm bit 6 RDYINT ReaDY INTerrupt The PDYINT bit is set to 1 when the automatic algorithm for a write erase operation etc in flash memory terminates When bit 7 INT 2 1 enables interrupt output and this bit bit 6 is set to 1 an interrupt request for terminating the automatic algorithm is generated After a reset the bit is initialized 0 Read Write operations for this bit are enabled However only write operations with the value 0 are valid even when a write operation attempts to set 1 the value of this bit remains unchanged Cause for clearing Clear is performed by writing 0 through an instruction Cause for setting The bit is set by termination of the automatic algorithm when the rising edge of the RDY BUSYX signal is detected bit 5 WE Write Enable The WE bit controls writing data and commands to the flash memory in CPU mode When this bit is 0 writing data and commands to the flash memory becomes invalid Data from flash memory is read in 32 bit access mode 355 CHAPTER 16 FLASH MEMORY 356 When this bit is 1 writin
344. rystal oscillator or ceramic oscillator and bypass capacitor to the ground are located as near to one another as possible Also prevent the wiring of these components from crossing the wiring of other components wherever possible Such PC board artwork that places the ground around the XO and X1 pins is strongly recommended for stable operation O Treatment of NC pin Be sure to keep the NC pin open O Mode pins MDO to MD2 Connect the mode pins directly to Vcc or Vss To prevent malfunction by noise minimize the pattern length between each mode pin and Vcc or Vss on the PC board and also minimize impedance for pattern connection O At power on When power is turned on be sure to begin by putting the RSTX pin in the L level and secure the time for at least five cycles of the internal operating clock after the power supply reaches the Vcc level Put the RSTX pin in the H level only after that O Pin conditions at power on The pin conditions at power on are unstable When power is turned on oscillation begins and the circuits are initialized O Input of source oscillation at power on When power is turned on be sure to input clock signals until the oscillation stabilization wait flag is reset 27 CHAPTER 1 OVERVIEW O Initialization by power on reset Devices contain registers that are initialized only by power on reset To initialize these registers turn the power off and turn it on again to execute power on resetting O Recovery
345. s UTIMR 25 UCC1 1 gt Generation cycle 2n 3 53 cycles UTIMR 60 UCC1 0 gt Generation cycle 2n 2 122 cycles When U TIMER is used as an interval timer set UCC1 to 0 bits 6 5 Reserved bit 4 UTIE U TIMER Interrupt Enable UTIE specifies whether to enable an interrupt when the U TIMER underflows 1 Disable initial value 0 Enable bit 3 UNDR UNDeR flow flag UNDR indicates that the U TIMER has underflowed An underflow interrupt occurs when UNDR is set while 1 is set in UTIE Resetting the register or writing to the bit clears UNDR When the register is read by a read modify write instruction 1 is always read from the bit An attempt to write 1 to UNDR is ignored bit 2 CLKS clock select CLKS is a cascade specification bit for U TIMER channels 0 and 1 0 Use the peripheral clock 9 as the clock source Initial value 1 Use the underflow signal of channel 1 for the source clock timing of U TIMER channel 0 f f in the block diagram CLKS is valid only for channel 0 Always set CLKS to 0 for channel 1 bit 1 UTST U TIMER STart UTST is the operation enable bit for the U TIMER 0 Stop Writing to this bit stops the U TIMER even during operation Initial value 1 Run Writing 1 to this bit during operation continues operation bit 0 UTCR UTIMER CleaR Writing to UTCR clears the U TIMER to 0000 also clears the flip flop to 0 1 is always read from this bit N
346. s is the LSB side data for little endians In word access all 4 bytes in the word are binary inverted 00 gt 11 01 gt 10 10 gt 01 11 gt 00 Half word access The MSB side byte data which corresponds to address 00 of big endians is the LSB side byte data for little endians In half word access all locations of 2 bytes in a half word are exchanged for those having an opposite value o gt 1 1 gt 0 Byte access Same for both big and little endians The data bus control signals used in a 16 8 bit bus width are the same for both big and little endians The following shows the relationship between the internal register and external data bus in each data format Word access during execution of LD and ST instructions Figure 4 16 11 Relationship between Internal Register and External Data Bus for Word Access Internal register External bus D31 p D23 D15 1 D07 DD 147 CHAPTER 4 BUS INTERFACE Half word access during execution of LDUH and STH instructions Figure 4 16 12 Relationship between Internal Register and External Data Bus for Half word Access Internal register External bus D31 D31 g D23 D07 BB O Byte access during execution of LDUB and STB instructions Figure 4 16 13 Relationship between Internal Register and External Data Bus for Byte Access a Lower bits of output address 0 Lower bits of output address 1 Internal register
347. s usual tte tette iir ends 159 bus control acquisition 193 bus control 193 bus converter 32 bits 16 32 bus converter Harvard Princeton 32 b s interface i5 ie eei 2 bus interface register 113 bus interface block diagram of 114 bus interface feature 112 b s 09 eR eain 69 bus size specification 117 bus width combination 129 byte 5 11222 142 148 153 byte ordering 42 CAS before RAS CBR refresh 191 cascade 243 CBR refresh automatic wait cycle of 192 change point 296 change point detection data register BSDC 294 characteristic iiiter 2 characteristic of CPU architecture 30 chip select area and bus interface 116 chip select area setting 115 CLK synchronous 243 265 CLK synchronous mode format of data transferred 258 clocK corittol
348. s 31 to 16 DMACT Transfer count These bits specify the number of times DMA transfer is to be performed When 0000H is specified DMA transfer is performed 65 536 times The value is decremented by 1 each time DMA transfer is performed bits 15 to 12 Reserved bits 11 to 8 BLK Block size specification These bits specify the size of blocks to be transferred in single block transfer mode When 0 is specified a block size of 16 is assumed Specify 1 for single transfer bits 7 6 5 51 5 50 Transfer source address update mode 332 15 5 Descriptor Register in RAM bits 5 4 DCS1 DCSO Transfer destination address update mode These bits specify the mode in which the transfer source or destination address is updated each time DMA transfer is performed Table 15 5 1 lists the available combinations of these bits Table 15 5 1 Specification of Transfer Source or Destination Address Update Modes Transfer destination address Transfer source address Increment Increment Increment Decrement Increment Do not update Decrement Increment Decrement Decrement Decrement Do not update Do not update Increment Do not update Decrement Do not update Do not update Reserved The unit in which an address is incremented or decremented in address update mode varies depending on the specified transfer data size as shown below Table 15 5 2 Address Increment Decrement Unit
349. s detected the CPU proceeds to an EIT processing sequence Operation for INT Instruction The operation for the INT u8 instruction is shown below The CPU branches to the interrupt handler of the vector indicated by u8 Operation SSP 4 gt SSP PS gt SSP SSP 4 gt SSP PC 2 gt SSP 0 gt I flag 0 gt S flag TBR 3FC 4 x u8 gt PC Operation for INTE Instruction The operation for the INTE instruction is shown below The CPU branches to the interrupt handler of the vector with vector number 9 Operation SSP 4 gt SSP PS gt SSP SSP 4 gt SSP PC 2 gt SSP 00100 gt ILM 0 gt S flag TBR 3D8 gt PC Do not use the INTE instruction in an INTE instruction or step trace trap processing routine No INTE EIT occurs during step execution 65 CHAPTER 2 CPU Operation for After the T flag in the PS SCR is set to enable the step trace function a trap occurs every time an instruction is executed resulting in a break A step trace trap is detected under the following conditions T flag 1 Instruction other than a delayed branch instruction During execution of something other than the INTE instruction or step trace trap processing routine If the above conditions are met a break occurs at the end of the current instruction operation Operation SSP 4 gt SSP PS gt SSP SSP 4 gt SSP Nex
350. s differ between LQFP and FBGA see Section 1 4 Pin Assignments Selection of External Pin Function I O Port or Control Pin Table 5 4 1 External Bus Functions to be Selected 1 4 28 to 35 Pin code P20 to P27 D16 to D23 Initial value P20 to P27 Switch over register Function automatically switches according to the mode set by MDO to MD2 AMDO to AMD5 and MO to M1 Single chip P20 to P27 8 bits P20 toP27 16 bits D16 to D23 36 to 42 44 P30 to P37 D24 to D31 P30 to P37 Function automatically switches according to the mode set by to MD2 and MO to M1 Single chip P30 to P37 External bus D24 to D31 45 47 to 61 P40 to P47 P50 to P57 00 to A15 P40 to P47 P50 to P57 Function automatically switches according to the mode set by MDO to 2 and MO to M1 Single chip P40 to P47 P50 to P57 External bus 00 to A15 62 to 67 69 70 P60 to P67 A16 to A23 P60 to P67 EPCR1 AE16 to AE23 bits 0 P60 to P67 1 A16 to A23 71 P70 A24 EOPO EPCR1 AE24 bit and DATCR EPSEO and EPDEO bits 24 EPSEO EPDEO 000 70 100 A24 Others EOPO P80 RDY EPCRO RDYE bit 0 P80 1 RDY 205 CHAPTER 5 I O PORTS Table 5 4 1 External Bus Functions to be Selected 1 4 Pin code P81 BGRNTX Initial value Switch over register EPCRO BRE bit 0 P81 1 BGRNTX P82 BRQ
351. s is fixed 7 5 x n cycles When both transfer source and destination addresses are incremented or decremented 8 5 x n cycles 337 CHAPTER 15 DMAC 15 7 Output of Transfer Request Acknowledgment and Transfer End signals Channels 0 1 and 2 have a function that outputs transfer request acknowledgment and transfer end signals from the corresponding pins When a transfer request input from the pin is received and DMA transfer is performed the DMAC outputs a transfer request acknowledgment signal When the transfer request input from the pin is received DMA transfer is performed When the DMACT counter is reset to 0 the transfer is ended and the DMAC outputs a transfer end signal E Output of Transfer Request Acknowledgment Signal The transfer request acknowledgment signal is an active low pulse to be output after access to transfer data The AKSn and AKDn bits of the DATCR specify whether to output the signal synchronously with access to the transfer source or destination or both E Output of Transfer End Signal The transfer end signal is an active low pulse to be output after access to the last transfer data The EPSn and EPDn bits of the DATCR specify whether to output the signal synchronously with access to the transfer source or destination or both 338 15 8 Notes on DMAC 15 8 Notes on DMAC This section provides notes on using the DMAC Interchannel Priority Order Once the DMAC starts with a D
352. s of a sector are erased the other cells remain intact In these operations flash memory does not have to be controlled externally The automatic sector erase operation starts from the end of the 50 us time out period after the last Sector Erase command is written When bit 7 is set to 1 see Hardware sequence flag in Section 16 7 Execution Status of the Automatic Algorithm the automatic sector erase operation ends and flash memory returns to the read mode At this time other commands are ignored The data polling function is enabled for any sector address in which data has been erased The time required for erasing the data of multiple sectors can be expressed as follows time for sector erase time for sector write preprogram x number of erased sectors Temporarily Stop Erase The Temporarily Stop Erase command temporarily stops the automatic algorithm in flash memory when the user is erasing the data of a sector thereby making it possible to write data to and read data from the other sectors This command is valid only during the sector erase operation and ignored during chip erase and write operations The Temporarily Stop Erase command BOH is valid only during the sector erase operation including the sector erase time out period When this command is entered within the time out period waiting for time out ends and the erase operation is suspended The erase operation is restarted when a Restart Erase command was written Temp
353. s the CLK clock waveform of external bus operation enable bit 0 Inhibits output 1 Permits output initial value At a reset this bit is set to 1 enabling CLK output bit 5 COE5 Chip select Output Enable 5 The COE5 bit controls the CS5X output When this bit is reset output is permitted 0 Inhibits output 1 Permits output initial value bit 4 COE4 Chip select Output Enable 4 The COE4 bit controls the CS4X When this bit is reset output is permitted 0 Inhibits output 1 Permits output initial value bit 3 COE 3 Chip select Output Enable 3 The bit controls the CS3X output When this bit is reset output is permitted In this device type because the CS3X pin also serves as the DMAC EOP1 output it is controlled together with the EPSE1 and EPDE1 bits of the DMAC control register DATCR as shown below Port CS3X output initial value EOP1 output EOP1 output EOP1 output bit 2 COE2 Chip select Output Enable 2 The COE2 bit controls the CS2X output When this bit is reset output is permitted 0 Inhibits output 1 Permits output initial value bit 1 COE1 Chip select Output Enable 1 The COE1 bit controls the CS1X output When this bit is reset output is permitted 0 Inhibits output 1 Permits output initial value 133 CHAPTER 4 BUS INTERFACE bit 0 COEO Chip select Output Enable 0 The COEO bit controls the CSOX output When this bit is reset output is permitt
354. s used to read the count value of the 16 bit timer The 16 bit reload register TMRLR stores the initial count value B 16 Bit Timer Register TMR 15 0 TMR Address 00002 0000324 00003EH R R R R bee R R R R R Initial value x x x x Zr x x x x x The 16 bit timer register is used to read the count value of the 16 bit timer The initial value is undefined Always use a 16 bit data transfer instruction to read the register 16 Bit Reload Register TMRLR 0 TMRLR 05 000028 000030 00003 WwW sek W Initial value x x x x EE x x x x x The 16 bit reload register TMRLR holds the initial count value The initial value is undefined Always use a 16 bit data transfer instruction to write to this register 286 12 4 Operation of 16 Bit Reload Timer 12 4 Operation of 16 Bit Reload Timer The 16 bit reload timer performs the following two types of operation e Internal clock operation Underflow operation B internal Clock Operation When a frequency division clock of the internal clock is used to run the timer a machine clock frequency divided by 2 8 or 32 can be selected as the clock source To make the counter start counting immediately when counting is enabled set both the CNTE and TRG bits of the control status register to 1 The trigger input by the TRG bit is always effective regardless of the operation mode when the timer is a
355. s written The value read from this register is undefined There is no restriction on the time interval between 5 and 5A writing Note Clearing the timebase timer using this register temporarily changes the oscillation stabilization wait time watchdog cycle and cycles of the peripherals using the time base 81 CHAPTER 3 CLOCK GENERATOR AND CONTROLLER 3 6 Gear Control Register GCR The gear control register GCR controls the gear functions of the CPU and peripheral clocks Configuration of the Gear Control Register GCR The configuration of the gear control register GCR is shown below Initial value Access Bit Functions of the Gear Control Register GCR bit 15 14 CCK1 0 These bits specify the CPU gear cycle The bits and the cycles selected by the bits have the relationships shown in Table 3 6 1 These bits are initialized by resetting Table 3 6 1 CPU Machine Clock CPU machine clock PLL x 1 PLL x 1 2 PLL x 1 4 PLL x 1 8 Source oscillation x 1 2 Source oscillation x 1 2 x 1 2 Source oscillation x 1 2 x 1 4 Source oscillation x 1 2 x 1 8 Initial value PLL PLL oscillation frequency Source oscillation Input frequency from XO bit 13 DBLAK This bit indicates the clock doubler operation mode Since the bit is read only a write attempt is ignored This bit is initialized by resetting Bus frequency switching involves a time lag This
356. seseeeeeeeen nennen nnne nnne nnne ens 278 11 6 Notes on Using the A D Converter 280 CHAPTER 12 16 BIT RELOAD TIMER 35e ian eee cu cep noto tau noua ann nana an es pa nen cR e eara annua ayuu 281 12 1 Overview of 16 bit Reload Timer 282 12 2 Control Status Register 2 0 424 1 00000000 284 12 3 16 Bit Timer Register and 16 Bit Reload Register 286 12 4 Operation of 16 Bit Reload Timer 02201 0 0 1 00 287 125 Counter State EE 289 CHAPTER 13 BIT SEARCH MODULE 2 2 291 13 1 Overview of the Bit Search Module 292 13 2 Bit Search Module Registers 293 13 3 Bit Search Module Operation and Save Restore Processing 2 295 14 299 14 1 Overview of PWM 300 14 2 PWM Timer Block Diagram ito ne et e tee texte 302 14 3 Control Status Register PCNH
357. set the request set in the ELVR register is input to the corresponding pin This module then issues an interrupt request signal to the interrupt controller External Interrupt Operation If multiple interrupt requests are issued to the interrupt controller their priorities are checked If the priority of the interrupt request issued by this resource is the highest an interrupt occurs Figure 6 5 1 shows external interrupt operation Figure 6 5 1 External Interrupt Operation External interrupt Interrupt controller CPU Resource request ELVR Ll ICR v IL a ENR ICR xx ILM Gase Sl Returning from Stop State When an external interrupt is used to return from the stop state in clock stop mode select the H level for the input request Selecting the L level may result in a malfunction The edge request cannot be used to return from the stop state in clock stop mode External Interrupt Operation Procedure To set the registers used for external interrupts proceed as follows 1 Disable the applicable bit of the interrupt enable register 2 Set the applicable bit of the interrupt level register 3 Clear the applicable bit of the interrupt request register 4 Enable the applicable bit of the interrupt enable register The settings in 3 and 4 can be performed simultaneously using 16 bit data When se
358. sfer data size is a word specify an address consisting of a multiple of four 334 15 6 DMAC Transfer Modes 15 6 DMAC Transfer Modes The DMAC supports the following three transfer modes This section explains the operation in these modes e Single block transfer mode e Continuous transfer mode e Burst transfer mode B Single Block Transfer Mode 1 2 9 The initialization routine sets the descriptor The program initializes the DMA transfer request source To use the internal peripheral circuit as the transfer request source enable interrupt requests and disable interrupts in the ICR of the interrupt controller The program sets the target DOEn bit of the DACSR to 1 This completes the setting for DMA Upon detection of a DMA transfer request input the DMAC requests bus control right from the CPU When the bus control right is transferred from the CPU the DMAC accesses three words of information of the descriptor through the bus While decrementing DMACT the DMAC performs a transfer based on the information stored in the descriptor as many times as specified by BLK or until DMACT reaches 0 The DMAC outputs a transfer request acknowledgment signal during data transfer if external transfer request input is used When decremented DMACT reaches 0 the DMAC outputs a transfer end signal during data transfer The DMAC clears the transfer request input The DMAC increments or decremen
359. sfer operation by the DMAC is suppressed If the DMA transfer operation is already in progress it stops at this point in time and releases bus control to the CPU All DMA transfer requests generated in DMA transfer request wait state are suspended When the HRCL is reset to the lowest level 31 the DMA transfer operation is suppressed for every interrupt request For continuing DMA transfer even if an interrupt request is issued the HRCL register must be set to the appropriate value 339 CHAPTER 15 DMAC register The suppression function for DMA transfer operation specified via the HRCL register is valid only when an interrupt request with higher priority is active Therefore if the interrupt request is cleared by the interrupt handler program suppression of the DMA transfer operation via the HRCL register is canceled and the CPU may lose bus control The PDRR register in the clock control unit is used to clear an interrupt request receive another request and suppress the DMA transfer operation When it is set to a value other than 0 DMA transfer is suppressed For releasing the suppression of DMA transfer set the PDRR to 0 DMA Transfer Operation in Sleep Mode When the CPU is in sleep state and a DMA transfer request is issued from an internal resource the DMAC performs a DMA transfer operation As the DMA transfer request signal from the internal resource serves as an interrupt request signal the CPU is r
360. ss 0000 0078 b15 b14 b2 b1 50 chi Address 0000 00704 MM ch2 Address 0000 0080m R Access 5 0 initial value Reload register UTIMR The UTIMR stores the value to be reloaded to the UTIM when the UTIM underflows Access it using a 16 bit transfer instruction UTIMR ee s chO Address 0000 0078m b15 b14 b2 b bO cht Address 0000 007 ch2 Address 0000 00888 Ww Access 0 initial value B U TIMER Control Register UTIMC The UTIMC controls the U TIMER operation 7 6 5 4 3 2 1 0 UTIMC 0 Address 0000 007BH UCC1 UTIE UNDR CLKS UTST JUTCR chi Address 0000 007Fu ch2 Address 0000 00834 R W R W R W R W R W R W Access 0 2 0 0 0 0 1 Initial value bit 7 UCC1 U timer Count Control 1 The UCC1 bit controls the U TIMER coun Normal operation ting method 2n 2 initial value 1 mode n Value set in UTIMR Cycle of clock output to UART 2n 3 241 CHAPTER 9 U TIMER 242 In addition to a normal 2 n 1 cycle clock an odd frequency clock can be set for the UART Setting 1 in UCC1 generates 2n 3 cycle clock pulses Example of setting UTIMR 5 UCC1 0 gt Generation cycle 2n 2 12 cycle
361. ssembler instructions that were added to the standard CPU specifications 2 Codes indicating the addressing modes that can be specified in operands Foran explanation of codes see Addressing mode codes 3 Indicates instruction formats 4 Operation codes are indicated by hexadecimal numbers 5 Indicates the number of machine cycles a Indicates memory access cycles that may be extended by the Ready function b Indicates memory access cycles that may be extended by the Ready function When the next instruction references a register subject to the LD operation interlock occurs increasing the number of execution cycles by 1 c When the next instruction is a Read or Write instruction for the R15 SSP or USP or is an instruction of format A interlock occurs and the number of execution cycles increases by 1 to 2 d When the next instruction references the MDH MDL interlock occurs and the number of execution cycles increases to 2 codes a b c and d indicate a minimum of 1 cycle 403 APPENDIX E Instructions 6 Indicates flag changes Flag change Changes Does not change Cleared Set 7 Indicates the operation for the instruction 404 Flag meaning Negative flag Zero flag Overflow flag Carry flag APPENDIX E Instructions Addressing Mode Codes Table E 1 Explanation of Addressing Mode Codes Code Meaning Ri Register using direct addressing RO toR15
362. supported Furthermore the 32 x 32 bits and 16 x 16 bits multiply instructions and 32 32 bits step divide instructions are available The FR series also supports immediate transfer instructions which allow immediate data to be set in registers and inter register transfer instructions Every arithmetic operation instruction executes using the general purpose registers and multiplication division registers in the CPU Load and store Load or store instructions are used to read data from external memory or write data to it They are also used to read data from the peripheral circuits I O inside the chip or write data to it Load and store instructions each use three types of access data length byte half word and word The FR series supports not only general register indirect memory addressing but also for some instructions register indirect memory addressing with displacement or with register increment decrement Branch The branch instruction group includes branch call interrupt and recovery instructions There are two types of branch instructions One has a delay slot and one does not They can be used most suitably for applications For more information on the branch instructions see Sections 2 7 1 Branch instructions with delay slot and 2 7 2 Branch instructions without delay slot 2 7 Instruction Overview O Logical operation and bit manipulation A logical operation instruction can execute AND OR or EOR
363. t 2 gt iteration 11 4 A D Converter Operation In continuous conversion mode the A D converter continues conversion until the BUSY bit is set to 0 Writing to the BUSY bit forcibly terminates A D conversion Note that forced termination interrupts conversion in progress When conversion is forcibly terminated the data register contains previously converted data Convert and stop mode In convert and stop mode the A D converter sequentially converts the analog inputs specified by the ANS and ANE bits of the ADCS register and stops whenever conversion of the analog input from one channel is completed The converter restarts conversion at the next start cause When conversion is completed up to the end channel specified by the ANE bits the converter returns to the ANS analog input and continues A D conversion If the start and end channels are the same ANS ANE conversion of the analog input from only one channel is repeated Example ANS 000 ANE 011 Start gt ANO stop gt start gt AN1 gt stop gt start gt AN2 stop gt start gt ANS gt stop gt start gt gt iteration ANS 010 ANE 010 Start gt AN2 gt stop gt start gt AN2 gt stop gt start gt AN2 gt iteration Only the start causes set by the STS1 and STSO bits are applicable to the above operation Convert and stop mode can be used to synchronize the beginn
364. t Sector Erase command is written As already mentioned multiple Sector Erase commands can be accepted during the six bus cycles of the writing operation During the command sequence Sector Erase commands 30H for sectors whose contents are to be erased simultaneously are written consecutively to the addresses for these sectors The sector erase operation itself starts from the end of the time out period of 50 us after the last Sector Erase command is written When the contents of multiple sectors are erased simultaneously the subsequent Sector Erase commands must be input within the 50 us time out period to ensure that they are accepted For checking whether the succeeding Sector Erase command is valid read bit 3 see Hardware sequence flag in Section 16 7 Execution Status of the Automatic Algorithm 16 6 Starting the Automatic Algorithm During the time out period any command other than Sector Erase and Temporarily Stop Erase is reset at read time and the preceding command sequence is ignored In the case of the Temporary Stop Erase command the contends of the sector are erased again and the erase operation is completed Any combination and number from 0 to 6 of sector addresses can be entered in the sector erase buffers The user does not have to write to flash memory before the sector erase operation Flash memory automatically writes to all cells in a sector whose data is automatically erased preprogram When the content
365. t Stack 2 2 reed druck ide patere i ear 58 Example of Multiple EIT Processing 2 63 Mode Register Configuration sssssssssssssssssseseeeeene nennen nennen nennen enses 70 Clock Generator and Controller Registers seen 74 Block Diagram of the Clock Generator and Controller 2 2 4 240 75 Gear Controller Block 87 Clock Selection Timing Chart 0 2224 0 0100 89 Stop Controller Block Diagram 92 Sleep Controller Block Diagram 95 Standby Mode State Transition sse nennen nennen nennen 98 Watchdog Timer Block 99 Watchdog Timer Operating Timing 040 1100000 enne nennen 100 Timebase Timer Counter 0 110000 100 Block Diagram of Reset Source Hold Circuit 2 101 DMA Suppression Circuit Block Diagram 103 Figure 3 15 1 Figure 3 15 2 Figure 4 1 1 Figure 4 1 2 Figure 4 2 1 Figure 4 4 1 Figure 4 16 1 Figure 4 16 2 Figure 4 16 3 Figure 4 16 4 Figure 4 16 5 Figure 4 16 6 Figure 4 16 7 Figure 4 16 8 Figure 4 16 9 Figure 4 16 10 Figure 4 16 11 Figure 4 16 12 Figure 4 16 13 Figure 4 16 14 Figure 4 16 15 Figure 4 16 16 F
366. t gt u4 gt Ri Ri gt gt u4 16 gt Ri Logical shift APPENDIX E Instructions Immediate Value Setting or 16 32 Bit Immediate Value Transfer Instruction Table E 1 7 Immediate Value Setting or 16 32 Bit Immediate Value Transfer Instruction Mnemonic LDI 32 132 Ri LDI 20 i20 Ri LDE8 i8 Ri LDI i8 i20 i32 Ri Operation i32 gt Ri Remarks i20 gt Ri Upper 12 bits are zero expanded i8 gt Ri Upper 24 bits are zero i8 i20 i32 gt Ri expanded When the immediate value is an absolute value the assembler automatically selects i8 i20 or i32 If the immediate value includes a relative value or external reference symbol i32 is selected Memory Load Instructions Table E 1 8 Memory Load Instructions Mnemonic Chi Ri R13 Rj Ri R14 disp10 Ri R15 udisp6 Ri R15 R15 Rs R15 PS Operation Rj gt Ri R13 Rj gt Ri R14 disp10 gt Ri R15 udisp6 gt Ri R15 gt Ri R15 4 R15 gt Rs R15 4 R15 gt PS R15 4 Remarks Rs special register Ri R13 Rj Ri R14 disp9 Ri Rj gt Ri R13 Rj gt Ri Zero expansion Zero expansion Zero expansion Ri Q R13 Rj Ri R14 disp8 Ri Rj gt Ri R13 Rj gt Ri R14 disp9 gt Ri R14 disp8 gt Ri Special register
367. t output is permitted 0 Inhibits output 1 Permits output initial value This device type supports no I O port control for the WROX to WR1X pins by the WRE bit Always set this bit to 1 Even if the WRE bit is set to 1 the write pulse pin can be used as an I O port according to the bus width set by the AMD For example the WR1X pulse is not output 8 bit mode and the corresponding pin can be used as an I O port bit 10 RDXE ReaDX pulse output Enable bit The RDXE bit specifies whether to output RDX read pulses When this bit is reset output is permitted 0 Inhibits output setting not possible 1 Permits output initial value When the external bus mode is used the RDXE bit performs no I O port control for the RDX pin Always set this bit to 1 bit 9 RDYE ReaDY input Enable bit The RDYE bit controls the RDY input as described below When this bit is reset the input becomes invalid 0 Invalidates RDY input initial value 1 Validates RDY input 132 4 12 External Pin Control Register 0 EPCRO bit 8 BRE Bus Request Enable bit The BRE bit controls the BRQ and BGRNTX signals as described below When this bit is reset the BRQ input becomes invalid and the BGRNTX output is inhibited 0 Validates BRQ input and inhibits BGRNTX output corresponding pins function as I O ports initial value 1 Validates BRQ input and permits BGRNTX output bit 6 CKE Clock output Enable bit The CKE bit i
368. t 1 000FFFB8 External interrupt 2 OOOFFFB4 External interrupt 3 000FFFBO N 0 reception completion 000FFFAC N UART 1 reception completion 000FFFA8 379 APPENDIX Interrupt Vectors Table B 1 Interrupt Vectors 1 2 Cause for the interrupt UART 2 reception completion Interrupt No Decimal Hexa decimal Interrupt level 1 Offset TBR default address 2 OOOFFFA4 UART 0 send completion 000FFFAQ UART 1 send completion 000FFF9C UART 2 send completion 000FFF98 DMAC 0 end error 000FFF94 DMAC 1 end error 000FFF90 DMAC 2 end error 000FFF8C DMAC 3 end error 000FFF88 DMAC 4 end error 000FFF84 DMAC 5 end error 000FFF80 DMAC 6 end error 000FFF7C DMAC 7 end error 000FFF78j A D serial 000FFF74 Reload timer 0 000FFF70 Reload timer 1 000FFF6C Reload timer 2 Table B 2 Interrupt Vectors 2 2 Interrupt cause PWM 0 Interrupt number Decimal Hexa decimal Interrupt level 1 Offset 000FFF68 TBR default address 2 000FFF64 PWM 1 000FFF60 PWM 2 000FFF5C PWM 3 000FFF58 U TIMER 0 000FFF54 U TIMER 1 000FFF50 U TIMER 2 000FFF4C FLASH memory 000FFF48
369. t instruction address gt SSP 00100 gt ILM 0 gt S flag TBR 3CCy gt PC After the T flag in the PS SCR is set to enable the step trace function user NMIs and user interrupts are inhibited No INTE EIT occurs either E Operation for Undefined instruction Exception If an instruction is found undefined during instruction decoding an undefined instruction exception occurs An undefined instruction exception occurs under the following conditions The instruction is found undefined during instruction decoding The instruction is provided at a location other than a delay slot not immediately after a delayed branch instruction If the above conditions are met an undefined instruction exception occurs and results in a break Operation SSP 4 gt SSP PS gt SSP SSP 4 gt SSP PC gt SSP 0 gt S flag TBR 3C4 gt PC The address of the instruction that detected the undefined instruction exception is saved to the PC 2 8 EIT Exception Interrupt and Trap Coprocessor Nonexistent Trap If a coprocessor instruction that attempts to use a coprocessor that is not installed is executed a coprocessor nonexistent trap occurs Operation SSP 4 gt SSP PS gt SSP SSP 4 gt SSP Next instruction address gt SSP 0 gt S flag TBR 3E0 gt PC Coprocessor Error Trap If an error occurs while a coprocessor is used a coprocessor error t
370. t involve branching Since no dummy instruction is placed in the delay slot the instruction coding efficiency is better than that of a branch instruction with a delay slot containing a NOP instruction Selecting an operation with a delay slot when an effective instruction can be placed in the delay slot and selecting an operation without a delay slot otherwise can satisfy both execution speeds and coding efficiency 51 CHAPTER 2 CPU 2 8 EIT Exception Interrupt and Trap EIT indicates that the program being executed is interrupted by an event and another program is executed EIT is a generic name coined from the words exception interrupt and trap An exception is an event that occurs in connection with the context of the current execution Program execution resumes from the instruction that has caused an exception An interrupt is an event that occurs regardless of the context of the current execution The event is caused by hardware A trap is an event that occurs in connection with the context of the current execution Some traps such as a system call are indicated by a program Execution resumes from the instruction following the one that caused a trap EIT Characteristics Support of multiple concurrent interrupts Interrupt level mask function The user can use 15 levels Trap instruction INT EIT for emulator activation hardware and software B EIT Causes The EIT causes are as follows Reset Userin
371. tatus Table C 5 Pin Status in Single Chip Mode Continued Pin name Function During sleep Previous status retained During stop P Previous status retained F DACK output Port Previous status retained ANO 3 INTO INT2 INT3 5 2 DREQO DREQ1 DACKO DACK1 510 TRGO 500 TRG1 SCO 511 TRG2 501 TRG3 512 1 502 2 394 ATGX Previous status retained HIZX 0 HIZX 1 Input possible Input possible Reset time Output 2 All pins Input possible P when a general purpose port is specified F when the specified function is selected APPENDIX D Notes on Using Little Endian Areas APPENDIX Notes on Using Little Endian Areas This section contains notes on using little endian areas for each item below D 1 C Compiler fcc91 1 D 2 Assembler fasm91 1 D 3 Linker flnk911 D 4 Debugger sim911 eml1911 mon911 395 APPENDIX D Notes on Using Little Endian Areas D 1 C Compiler fcc911 When the operations described below are performed for little endian areas from programs in C the results of the respective operations may be rendered uncertain Allocating variables with initial values Assigning structures by referencing other structures Manipulating data other than character arrays with character string mani
372. te 12 5 MHz 1200 833 33 650 UCC1 0 520 0 1 0 324 UCC1 1 259 UCC1 1 2400 416 67 324 UCC1 1 259 UCC1 1 162 0 1 0 129 UCC1 0 4800 208 33 162 0 1 0 129 0 1 0 80 UCC1 1 64 UCC1 0 9600 104 17 80 UCC1 1 64 UCC1 0 39 UCC1 1 31 UCC1 1 19200 52 08 39 UCC1 1 31 UCC1 1 19 1 1 38400 26 04 19 UCC1 1 12 UCC1 1 57600 17 36 12 UCC1 1 i 10400 96 15 74 UCC1 0 59 UCC1 0 36 UCC1 1 29 UCC1 0 31250 32 00 24 UCC1 0 19 UCC1 0 11 UCC1 1 9 UCC1 0 62500 16 00 11 UCC1 1 9 UCC1 0 4 UCC1 0 O CLK synchronous mode Table 10 11 2 Baud Rates and U TIMER Reload Values in CLK Synchronous Mode Baud rate 49 UCC1 0 39 UCC1 0 12 5 MHz 24 UCC1 0 19 UCC1 0 24 UCC1 0 19 UCC1 0 11 UCC1 1 9 UCC1 0 11 UCC1 1 9 UCC1 0 1 The error exceeds plus or minus 1 5 UCC1 0 4 UCC1 0 CHAPTER 10 UART 266 CHAPTER 11 A D CONVERTER Successive approximation type This chapter provides an overview of the A D converter and explains the register configuration and functions and the operations of the A D converter 11 1 Overview of A D Converter Successive Approximation Type 11 2 Control Status Register ADCS 11 3 Data Register ADCR 11 4 A D Converter Operation 11 5 Conversion Data Protection Function 11 6 Notes on Using the A D Converter 267 CHAPTER
373. terface Timing Chart O Combination of hyper DRAM and basic bus cycle CS switch over Figure 4 17 34 Example of Hyper DRAM Interface Timing Chart BA1 BA2 Q1 Q2 Q3 Q4HR Q4HR Q4HW Q4HR Q4HR CLK A24 00 52 bus X X X rowad X coladr Xco Xco X D31 24 X Write Read X Write X Read 023 16 X Write XRead X Write X Read CS2X CS4X CS5X RDX WROX CS4 RAS CS4 CASL CS4 CASH CS4 WE CS5 RAS CS5 CASL CS5 CASH CS5 WE 52 3 54 Hyper DRAM read CS5 Hyper DRAM write read Explanation of operation When bus cycle starts from a high speed page RDX in a read cycle goes down to L from the falling edge of Q4HR and is negated when the Q4HR cycle ends In a write cycle it goes down to L from the rising edge of WE including WEL and WEH Q4HW and is negated when the Q4HW cycle ends CS4X and CS5X change at the same time as the output address When bus cycle starts from a high speed page they change from the Q4HR and Q4HW cycles as with the column address 190 4 17 Bus Timing 4 17 20 DRAM Refresh This section provides DRAM refresh timing charts CAS before RAS CBR Refresh CLK RAS CAS WE Fi
374. terrupt internal resource external interrupt NMI Delayed interrupt Undefined instruction exception Trap instruction INT Trap instruction INTE Step trace trap Coprocessor nonexistent trap e Coprocessor error trap Return from EIT Use the following instruction to return from EIT instruction 52 2 8 EIT Exception Interrupt and Trap Note on EIT O Delay slot The delay slot of a branch instruction has restrictions on EIT See Section 2 7 Instruction Overview for details of the restrictions 53 CHAPTER 2 CPU 2 81 EIT Interrupt Levels The EIT interrupt levels range from 0 to 31 which are managed using five bits B Interrupt Levels Table 2 8 1 summarizes the assignments of the EIT interrupt levels Table 2 8 1 Interrupt Level Level Remarks Decimal Reserved by the system Reserved by the system When the original value of ILM is one from 16 to 31 no value within this range can be set in ILM by a program INTE instruction Step trace trap Reserved by the system Reserved by the system NMI for the user Interrupt When ILM is set user interrupts are inhibited Interrupt Interrupt When ICR is set interrupts are inhibited Operation can be performed on levels 16 to 31 Undefined instruction exceptions coprocessor nonexistent traps coprocessor error traps and INT instructions are not affected by inte
375. terrupt execute routine LDI 20 PDRR R10 LD R10 R1 ADD2 1 R1 ST R1 R10 RETI Note GET PDRR VALUE INTO R1 PDRR PDRR 1 DMA disabled int occurred with int REG example int flag 10h CLEAR int REQ but still DMA disabled PDRR VALUE INTO R1 PDRR PDRR 1 DMA may be enabled Since the register consists of four bits the DMA suppression function cannot be used for more than 15 concurrent interrupts Always give a DMA task a priority that is at least 15 levels higher than that of other interrupts 3 14 Clock Doubler Function 3 14 Clock Doubler Function As the internal operating frequency goes higher the external bus timing normally becomes more complicated To prevent this the ratio of the external bus frequency to the internal operating frequency can be adjusted to 1 to 2 1 2 This model does not support this function Enabling the Clock Doubler Function The clock doubler function is enabled by setting the GCR DBLON bit to 1 When DBLON is set to 1 the system waits for all C BUS accesses to be finished and then switches the external bus clock Thus there is a small time lag before the switching is completed but the timing for switching can be determined by the GCR DBLAK value When the clock doubler function is enabled the CPU clock gear becomes 1 1 regardless of the GCR setting This device permits a frequency up to double the oscillation to be set as the external bus operating
376. the latter case however the respective data item is read as 0 in reset or read mode A data item 0 can be changed to 1 only after an erase operation Erase Chip The Erase Chip command sequence erase all sectors simultaneously is executed in six access cycles First two unlock cycles are executed then a Setup command is written After two more unlock cycles the Erase Chip command is entered During the Erase Chip command sequence the user does not have to write to flash memory before the erase operation When the automatic erase algorithm is executed flash memory checks cell states by writing a pattern of zeros before automatically erasing the contents of all cells preprogram In this operation flash memory does not have to be controlled externally The automatic erase operation starts with the write operation of the command sequence and ends when bit 7 is set to 1 where flash memory returns to the read mode The chip erase time can be expressed as follows time for sector erase x number of all sectors time for writing to the chip preprogram Sector Erase The Sector Erase command sequence is executed in six access cycles First two unlock cycles are executed then a Setup command is written After two more unlock cycles the Sector Erase command is entered in the sixth cycle for starting the sector erase operation The next Sector Erase command can be accepted within a time out period of 50 us after the las
377. the rising edge of WE including WEL and WEH Q4SW and is negated when the Q4SW cycle ends e CS4X and CS5X change at the same time as the output address When bus cycle starts from a high speed page they change from the Q4SR and Q4SW cycles as with the column address 187 CHAPTER 4 BUS INTERFACE 4 17 17 Hyper DRAM Interface Read This section provides a hyper DRAM interface timing chart Hyper DRAM Interface Read Timing Chart O Bus width 16 bits access words Figure 4 17 32 Example of Hyper DRAM Interface Read Timing Chart Q1 Q2 Q3 Q4HR Q4HR Q4HR Q4HR Q4HR Idle Q1 Q3 us 1 45 ul 1 1CAS 2WE A24 00 X X X XXcolQ Xcol2 Xcol4 Xcol6 X X X D31 24 eaa T Rende D23 16 Read1 Read3 Read5 1Read7 RS t E NE RUNE DNE INE CAS 1 I1 nog WEL i i d WR mu E E RDX P DACKO d E Ligh os High n Tm ace gt Outside page speed speed speed speed page page page page 188 Explanation of operation Column addresses are output in Q4HR cycles CAS is asserted at the falling edge of Q4HR and negated at the rising edge of Q4HR D31 to D16 are fetched at the falling edge of CAS to be output in the Q4HR cycle next to that in which the
378. tial value after resetting is undefined O System stack pointer SSP SSP stands for system stack pointer When the S flag is 0 the SSP functions as R15 The SSP can be specified explicitly It can also be used as a stack pointer to specify the stack for saving the PS and PC when EIT occurs The initial value after resetting is 00000000 O User stack pointer USP USP stands for user stack pointer When the S flag is 1 the USP functions as R15 The USP can be specified explicitly The initial value after resetting is undefined The USP cannot be used for the RETI instruction O Multiplication division result register MDH MDL The MDH and MDL are each 32 bits long The initial value after resetting is undefined Multiplication When 32 bit data is multiplied by 32 bit data the resultant 64 bit data is stored in the multiplication division result register as follows e MDH 32 high order bits MDL 32 low order bits The result of multiplying 16 bits by 16 bits is stored as follows e MDH Undefined MDL Resultant 32 bit data 37 CHAPTER 2 CPU Division When calculation begins a dividend is stored in the MDL The result of division by the DIVOS DIVOU DIV1 DIV2 DIV3 or DIV4S instruction is stored in the MDL and MDH as follows MDH Remainder MDL Quotient 38 2 3 Programming Model 2 3 3 Program Status Register PS The program status register holds the program status in three parts ILM
379. tial value after resetting is undefined The value read from this register is undefined Use a 32 bit data transfer instruction for data transfer do not use 8 bit and 16 bit data transfer instructions 1 Detection Data Register BSD1 31 0 000003 4 Read write R W Initial value gt Undefined Use a 32 bit data transfer instruction for data transfer do not use 8 bit and 16 bit data transfer instructions O Write The module detects 1 for the value written to this register 293 CHAPTER 13 BIT SEARCH MODULE O Read Data saved for the internal status of the bit search module is read from this register When the interrupt handler uses the bit search module the register is used to save the current status and restore it Even when data is written to the O detection or change point detection data register the original data can be saved and restored only by using the 1 detection data register The initial value after resetting is undefined Change Point Detection Data Register BSDC 31 0 000003 8 Read write Initial value Undefined The module detects a change point for the value written to this register The initial value after resetting is undefined The value read from this register is undefined Use a 32 bit data transfer instruction for data transfer do not use 8 bit and 16 bit data transfer instructions Detection Result Register BSRR 31 0
380. tice Customers are advised to consult with FUJITSU sales representatives before ordering The information and circuit diagrams in this document are presented as examples of semiconductor device applications and are not intended to be incorporated in devices for actual use Also FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams The contents of this document may not be reproduced or copied without the permission of FUJITSU LIMITED FUJITSU semiconductor devices are intended for use in standard applications computers office automation and other office equipments industrial communications and measurement equipments personal or household devices etc CAUTION Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage or where extremely high levels of reliability are demanded such as aerospace systems atomic energy controls sea floor repeaters vehicle operating controls medical devices for life support etc are requested to consult with FUJITSU sales representatives before such use The company will not be responsible for damages arising from such use without prior approval Any semiconductor devices have inherently a certain rate of failure You must protect against injury
381. tion result is a negative value The initial value after resetting is undefined bit 2 Z Zero flag This bit indicates whether the operation result is 0 0 Indicates that the operation result is a value other than 0 1 Indicates that the operation result is 0 The initial value after resetting is undefined bit 1 V Overflow flag This bit assumes that the operands used for operation are each an integer represented in two s complement and indicates whether an overflow occurred as the result of operation 0 Indicates that no overflow occurred as the result of operation 1 Indicates that an overflow occurred as the result of operation The initial value after resetting is undefined bit 0 C Carry flag This bit indicates whether carry from the most significant bit or borrow occurred during operation 0 Indicates that no carry and borrow occurred 1 Indicates that carry or borrow occurred The initial value after resetting is undefined O System condition code register SCR The configuration of the system condition code register SCR is as follows 10 9 8 Initial value D1 T XX0e bit 10 9 D1 DO Step division flag These bits hold intermediate data during execution of step division They must not be changed during execution of step division When other processing is performed during execution of step division continued operation for step division is guaranteed by saving and restoring th
382. trol Status Register ADCS 270 bit 15 BUSY BUSY flag and stop Read This bit indicates whether the A D converter is operating The bit is set when A D conversion begins and is cleared when the conversion is finished Write Setting this bit to 0 during A D conversion forcibly stops the operation The bit is used for forced termination in continuous conversion or convert and stop mode The bit indicating information on operation cannot be set to 1 An RMW instruction reads 1 from the bit In single mode the bit is cleared when A D conversion is finished In continuous conversion or convert and stop mode the bit is not cleared until it is set to 0 to forcibly terminate A D conversion The bit is initialized to 0 when the register is reset Do not perform forced termination and software activation simultaneously BUSY 0 STRT 1 bit 14 INT INTerrupt Data indication bit This bit is set when conversion data has been written to the ADCR When the bit is set while INTE bit 13 is 1 an interrupt request occurs and DMA starts if the start of DMA transfer has been selected Setting the bit to 1 has no effect Setting 0 or issuing the clear signal from the DMAC clears the bit 11 2 Control Status Register ADCS lt Note gt Set the bit to 0 for clearing it while A D conversion is stopped The bit is initialized to 0 when the register is reset A Read Modify Write instruction reads 1 from t
383. ts SADR or DADR and writes the result together with the DMACT value back to the descriptor The DMAC returns the bus control right to the CPU 10 If the DMACT value is 0 the DMAC sets DACSR DEDn to 1 and causes an interrupt to the CPU if interrupts have been enabled The number of minimum required cycles per transfer is shown below on the assumption that the descriptor is stored in built in RAM data is transferred between external busses and the data length is counted in bytes When both transfer source and destination addresses are fixed 6 5 x BLK cycles When one of the transfer source and destination addresses is fixed 7 5 x BLK cycles When both transfer source and destination addresses are incremented or decremented 8 5 x BLK cycles 335 CHAPTER 15 DMAC Continuous Transfer Mode 336 1 2 9 The initialization routine sets the descriptor The program initializes the DMA transfer request source Set the external transfer request input pin to the H level or L level detection mode The program sets the target DOEn bit of the DACSR to 1 This completes the setting for DMA Upon detection of a DMA transfer request input the DMAC requests bus control right from the CPU When the bus control right is transferred from the CPU the DMAC accesses three words of information of the descriptor through the bus While decrementing DMACT the DMAC performs a transfer only once based
384. tting the registers in this module disable the interrupt enable register in advance Also clear the interrupt request register before enabling the interrupt enable register to prevent an interrupt from occurring inadvertently when registers are set or when interrupts are enabled 216 6 6 External Interrupt Request Levels 6 6 External Interrupt Request Levels When an edge is selected for the interrupt request mode a pulse width of at least three machine cycles peripheral clock machine cycles is required to detect an edge When a level is selected for the interrupt request mode an external request that has been input may be canceled later though the request issued to the interrupt controller remains active because an interrupt cause hold circuit exists inside The interrupt request register must be cleared to cancel the request issued to the interrupt controller External Interrupt Request Levels Figure 6 6 1 shows how the interrupt cause hold circuit is cleared when a level is selected for the interrupt request mode Figure 6 6 2 shows the input of an interrupt cause in interrupt enable mode and a request issued to the interrupt controller Figure 6 6 1 Clearing the Interrupt Cause Hold Circuit at Level Setting for the Interrupt Request Mode Input of interrupt gt HENA y Cause F F gt Enable gate To the interrupt cause hold circuit controller The cause is held until t
385. tus retained F H output P F Previous status retained P Previous status retained F BRQ input P F Previous status retained Previous status retained Previous status retained P Previous status retained F H output P F Previous status retained Previous status retained H output P Previous status retained F CS output P Same as left F H output P Previous status retained F CS EOP output P Same as left F H output Previous status retained P Previous status retained F CS output P Same as left F H output HIZX 1 Output Hi Z Input fixed to 0 Bus release BGRNT Output Hi Z Reset time P Previous status retained F RDY input L output BRQ input H output H output L output H output 387 APPENDIX C Pin Status for Each CPU Status Table C 3 Pin Status for 16 bit External Bus Length and 2CA1WR Mode Continued Pin name Function During sleep During stop Bus release Reset time BGRNT HIZX 0 HIZX 1 PA6 CLK P Previous P F Previous Output Hi Z CLK Output CLK status retained status retained Input fixed to 0 Output F CLK output PBO RASO P Previous P Previous P Previous Output Hi Z status retained status retained status retained Input PB1 CSOL F Previous F Previous F Pr
386. uction 1 Instruction 2 Instruction 3 Instruction 4 Instruction 5 ee Gee a eee de e WB MA WB EX MA WB ID EX MA WB IF ID EX MA WB IF ID EX MA WB Instruction 6 Instructions are always executed in order That is instruction A that is put into the pipeline before instruction B always reaches the write back stage before instruction B Instructions are normally executed at a rate of one instruction per cycle However a load store instruction involving memory wait branch instruction without a delay slot or multiple cycle instruction requires multiple cycles to complete execution The instruction execution speed is also slowed down when instruction supply takes time 32 bits lt gt 16 bits bus converter The 32 bits lt gt 16 bits bus converter interfaces between the D BUS that allows high speed 32 bit wide access and R BUS that allows 16 bit wide access lt thus enables the CPU to access data in the internal peripheral circuits Upon receipt of a 32 bit wide access from the CPU the bus converter converts it into two 16 bit wide accesses to implement access to the R BUS Some internal peripheral circuits have restrictions on access width Harvard Princeton bus converter The Harvard Princeton bus converter coordinates the instruction access and data access of the CPU to implement smooth interfacing with the external bus The CPU has Harv
387. uctions which are compliant with high level language instructions Register interlock function which eases assembler coding Branch instruction with delay slot which reduces overheads in branch processing Built in adder supported in the instruction level Signed 32 bit addition 5 cycles Signed 16 bit addition 3 cycles Interrupt PC PS saving 6 cycles 16 priority levels O Bus interface Operating frequency Up to 25 MHz internal 25 MHz external bus 25 bit address bus 32 megabyte address space 16 bit address output 8 bit or 16 bit data input and output Basic bus cycle 2 clock cycles Chip Select output that can be set in 64 kilobytes minimum 6 lines Interface support for each type of memory DRAM interface areas 4 and 5 1 1 MB91F109 Characteristics Automatic wait cycle Any number of cycles 0 to 7 can be set for each area Unused data and address terminals can be used as 1 ports Support for little endian mode selecting one of areas 1 to 5 DRAM interface 2 bank independent control areas 4 and 5 Double CAS DRAM normal DRAM interface single CAS DRAM and hyper DRAM Basic bus cycle Five cycles in normal mode Two cycle access is enabled in high speed page mode Programmable waveform Automatic 1 cycle wait can be inserted into RAS or CAS DRAM refresh CBRrefresh The interval can be set as desired using the 6 bit timer Self refresh mode Support for 8 9 10 or 12 line column ad
388. used for I O This area is called the direct addressing area The addresses in this area can be directly specified for instruction operands The direct addressing area varies depending on the size of accessed data as follows e Byte data access 0 to OFFy e Half word data access 0 to 1FFy e Word data access 0 to 3FFy 25 CHAPTER 1 OVERVIEW 1 8 Handling of Devices This section provides notes on using devices Device Handling Latchup prevention If voltage higher than Vcc or lower than Vss is applied to a CMOS IC input or output pin or if voltage exceeding the rating is applied between Vcc and Vss latchup may be caused Latchup rapidly increases supply current and may cause thermal damage to the device To prevent such damage do not to let voltage exceed the maximum rated voltage Also do not to let the analog power supply exceed the digital power supply O Treatment of unused input pin Leaving an unused input pin open may cause a malfunction To avoid this malfunction pull it up or push it down O Input of external reset signal To ensure that the device is completely reset when the L level is input to the RSTX pin the L level input to the RSTX pin must continue for at least five machine cycles O Note on using an external clock When an external clock is used use the pin unless otherwise specified and supply a negative phase clock to the X1 pin simultaneously Do not use STOP mode oscillation stop mode
389. ut level of the corresponding external pin PDRwrite Writes a value to the PDR O Output mode DDR 1 PDR read Reads the PDR value PDR write Outputs the PDR value to the corresponding pin 202 5 2 Port Data Register PDR 5 2 Port Data Register PDR The port data registers PDR2 to PDRF are I O port I O data registers The corresponding data direction registers DDR2 to DDRF perform control B Configuration of Port Data Register PDR The port data register PDR is configured as follows 7 6 5 4 3 2 1 0 PDR2 Initial value Address 000001 P27 P26 P25 P24 P23 P22 P21 P20 XXXXXXXX amp 7 6 5 4 3 2 1 0 PDR3 Initial value Address 000000 P37 P36 P35 P34 P33 P32 P31 P30 7 6 5 4 3 2 1 0 PDR4 Initial value Address 0000074 P47 P46 P45 P44 P43 P42 P41 P40 7 6 5 4 3 2 1 0 PDR5 Initial value Address 000006 P57 P56 P55 P54 P53 P52 P51 P50 7 6 5 4 3 2 1 0 PDR6 Initial value Address 000005 P67 P66 P65 P64 P63 P62 P61 P60 XXXXXXXX amp 7 6 5 4 3 2 1 0 PDR7 Initial value Address 0000041 P70 Xs 7 6 5 4 3 2 1 0 PDR8 Initial value Address 00000BH P85 P84 P83 P82 P81 P80 7 6 5 4 3 2 1 0 PDRA Initial value Address 000009 PA6 PAS PA4 PA2
390. ve reading operations from sectors that are subject to temporary erase stop The temporary erase stop bit bit 6 can be used to detect this operation Note that bit 6 can be read from any address but bit 7 must be read from write addresses To restart the sector erase operation a Restart Erase command 30H must be entered Another Restart Erase command entry is ignored in this case On the other hand a Temporarily Stop Erase command can be entered after flash memory restarts the erase operation 363 CHAPTER 16 FLASH MEMORY 16 7 Execution Status of the Automatic Algorithm This flash memory has two hardware components for performing a Write or Erase sequence in the automatic algorithm These components indicate the internal operation status of flash memory and the completion of operations to external components One is a Ready Busy signal and the other is a hardware sequence flag Ready Busy Signal RDY BUSYX The flash memory uses the Ready Busy signal in addition to the hardware sequence flag to indicate whether the internal automatic algorithm is running The Ready Busy signal is transmitted to the flash memory interface circuit where it can be read via the RDY bit of the flash memory status register An interrupt signal can also be generated for the CPU at the rising edge of this Ready Busy signal see Section 16 1 Outline of Flash Memory When the value of the RDY bit is 0 the flash memory is executing a write
391. ven by adding an offset value specified for each TBR and EIT factor becomes a vector address 3 When using the REALOS or FR use the 0x40 and 0x41 interrupts for system codes APPENDIX Interrupt Vectors Reference The area 1 kilobyte after the address indicated by the TBR is a vector address for EIT Each vector is 4 bytes in size The relationship between the vector number and vector address is as follows vetadr TBR vctofs 3FCp 4 x vct vctadr Vector address vctofs Vector offset vct Vector number 382 APPENDIX C Pin Status for Each CPU Status APPENDIX C Pin Status for Each CPU Status Table C 1 explains the terms used in the pin status list Table C 2 to Table C 5 list the pin status for each CPU status Note that the pin status at reset differs between the external bus mode and single chip mode Explanation of Terms Used in the Pin Status List The terms used in the pin status list are explained below Table C 1 Explanation of Terms Used in the Pin Status List Term Explanation Input possible Input functions are ready to use Input fixed to 0 External inputs are blocked out and the value 0 is transmitted internally from the input gate near the pin Output Hi Z Pin drive transistors are put in drive inhibited status and their pins are put in high impedance status Output retained The output status immediately before this mode is entered is output u
392. whole area of a stack is allocated to a little endian area the result of the subsequent operation may be rendered invalid 398 APPENDIX D Notes on Using Little Endian Areas D 2 Assembler fsm911 The following two items require caution when using little endian areas during programming in FR series Assembler Sections Data Access B Sections Little endian areas are allocated primarily for data exchange data with little endian type CPUs Therefore define little endian areas as data sections that store no initial value If a little endian area is specified as data section storing a code or initial stack value the result of an access by the MB91F109 cannot be guaranteed Example Correct definition of endian area as a section SECTION Little Area DATA ALIGN 4 Little Word RES W 1 Little Half RES H 1 Little Byte RES B 1 B Data Access When accessing data in a little endian area the data value can be coded independently of the endian area However specify a size matching the size of the data when accessing the data of the little endian area Example LDI LDI LDI LDI LDI LDI 0x01020304 rO Little_Word r1 0x0102 r2 zLittle Half r3 80x01 r4 Little_Byte r5 399 APPENDIX D Notes on Using Little Endian Areas 32 bit data is accessed with a ST or LD instruction ST r0 r1 16 bit data is accessed with a STH or LDH instruction STH r2 r3
393. word half word or byte access in write cycles from the beginning BA1 of bus cycles In the above example word access is performed in an 8 bit bus width Therefore the address of the first byte the lower side of the address 0 in the word access is first output The following three addresses are then sequentially output 1 1 byte from the first byte 2 2 bytes from the first byte and 3 3 bytes from the first byte D31 to D16 data 31 to data 16 represent write data to I O In write cycles write data is output from the beginning BA1 of bus cycles and set to High Z at the end end of BA2 of bus cycles As the above example has an 8 bit data bus width write data is output from D31 to D24 In write cycles RDX is negated WROX and WR1X are write strobe signals on the external data bus that are asserted at the falling edge of BA1 and negated at the falling edge of BA2 D31 to D24 and D23 to D16 are asserted depending on the corresponding data buses WROX and WR1X respectively As the above example has an 8 bit data bus width only WROX is asserted When chip select areas 0 to 5 have a maximum bus width of 8 bits that is when all of the 4 17 Bus Timing specified areas are 8 bits wide D23 to D16 automatically become I O ports which are set to High Z The above example shows the case where D23 016 WR1X are used as ports If the bus width of at least one of chip select areas 0 to 5 is set to 1
394. word units The write operation is performed in four cycles of bus operation The command sequence has two unlock cycles which are followed by a Write Setup command and a write data cycle Writing to memory starts in the last write cycle After an automatic write algorithm command sequence was executed it becomes unnecessary to control the flash memory externally The flash memory itself internally generates write pulses to check the margin of the cells to which data is written The data polling function compares bit 7 of the original data with bit 7 of the written data and if these bits are the same the automatic write operation ends see Hardware sequence flag in Section 16 7 Execution Status of the Automatic Algorithm The automatic write operation then returns to the read mode and accepts no more write addresses After that the flash memory requests the next valid address In this manner the data polling function indicates a write operation in memory During a write operation all commands written to the flash memory are ignored If a hardware reset starts during write operation the data at the address for writing may become invalid Writing operations can be performed in any address sequence and outside of sector boundaries However write operations cannot change a data item 0 to 1 If a O is overwritten with a 1 the data polling algorithm either determines that the elements are defective or that 1 has been written In
395. ws the use of the DRAM interface Configuration of Area Mode Register 4 AMD4 Area mode register 4 AMD4 is configured as follows AMD4 d B 5 4 3 2 1 0 Initial value Access Address 0000 06234 DRME BW1 WTC2WTC1 WTCO 0 00000 R W Bit Functions of Area Mode Register 4 AMD4 bit 7 DRME DRaM Enable bit The DRME bit selects the usual bus interface or DRAM interface for area 4 0 Usual bus interface 1 DRAM interface When the DRAM interface is used more details must be specified via the DMCR DRAM control register which is described later bit 4 and 3 BW1 and 0 Bus Width bit BW1 and BWO specify the bus width of area 4 These bits have functions similar to those of the BW bits of other AMD registers When the DRAM interface is used the bus width specified by these bits is also valid Bus width 8 bits 16 bits Setting disabled Reserved bit 2 to 0 WTC 2 to 0 Wait Cycle bit WTC2 to WTCO specify the number of wait cycles to be automatically inserted when area 4 is accessed via memory These bits have functions similar to those of the WTC bits of other AMD registers By resetting the bits to 000 the number of wait cycles to be inserted automatically becomes 0 When the DRAM interface is used because wait cycles are controlled by the DMCR WTC2 to WTCO become invalid 125 CHAPTER 4 BUS INTERFACE 4 9 Area Mode Register 5 AMD5
396. y OCPA1 PWM timer output This function is valid when PWM timer output is enabled PF5 General purpose I O port SO2 OCPA2 PF6 502 UART2 data output This function is valid when UART2 data output is enabled OCPA2 PWM timer output This function is valid when PWM timer output is enabled PF6 General purpose I O port This function is valid when UART2 data output is disabled OCPAO PF7 ATGX PWM timer output This function is valid when PWM timer output is enabled PF7 General purpose I O port This function is valid when PWM timer output is disabled ATGX External trigger input for A D converter This input is used from time to time when this pin is selected for the A D start cause Therefore it is needed to stop output by other functions except when such output is performed intentionally ANO to AN3 ANO 3 A D converter analog input 20 VCC power supply for A D converter Table 1 5 5 Pin Functions 5 5 Pin name circuit format 1 5 Pin Functions Function Reference voltage of A D converter high potential side Always turn the pin on or off while the voltage equal to AVRH or higher is applied to VCC AVSS AVRL A D converter VSS power supply and reference voltage low potential side VCC Digital circuit power supply Be sure to connect the power supply to every VCC pin Note Digital circuit
397. y the A D converter is activated by the first cause Since the specified start mode becomes effective soon after the bit setting is changed be careful when changing the bit setting during A D conversion 271 CHAPTER 11 A D CONVERTER Successive approximation type lt Notes gt The external pin trigger signal is detected on the falling edge If the bit setting is changed to select an external trigger mode while the external trigger input level is low the A D converter may start In timer start mode reload timer channel 2 is selected If the bit setting is changed to select a timer start mode while the reload timer output level is high the A D converter may start bit 9 STRT STaRT Setting this bit to 1 starts the A D converter To restart the A D converter set the bit again to 1 Setting the bit to 1 in convert and stop mode does not start the A D converter with the operating function The bit is cleared when the register is reset Do not perform forced termination and start by software simultaneously BUSY 0 STRT 1 A Read Modify Write instruction reads O from this bit bit 8 Bit 8 is a test bit Set this bit to 0 in write mode bit 7 6 MD1 MDO A D converter MoDe set Select the operating mode Table 11 2 2 Selecting the A D Converter Operation Mode Operation mode Single conversion mode in which restart in any mode is enabled during operation Single conversion mode
398. y Cycle Setting Register PDUT The configuration of the PWM duty cycle setting register PDUT is shown below PDUT bit 15 14 13 12 11 10 9 8 Address chO 0000 4 ch2 0000 4 ch3 0000 7 6 5 4 3 2 1 0 Attribute Write only Initial value gt Undefined When the same value is set in the cycle setting register and duty cycle setting register output is kept at a high level in normal polarity mode or output is kept at a low level in inverse polarity mode To ensure stable PWM output set values that make PCSR smaller than PDUT Use a 16 bit data instruction to access the cycle setting register 309 CHAPTER 14 PWM TIMER 14 6 PWM Timer Register PTMR The PWM timer register PTMR is used to read the value of the 16 bit decrementing counter B PWM Timer Register PTMR 310 The configuration of the PWM timer register PTMR is shown below PTMR bit 15 14 13 12 11 10 9 8 Address chO 0000 0 ch2 0000 ch3 0000 8 7 6 5 4 3 2 1 0 Attribute Read only Initial value Use a 16 bit data instruction to access the cycle setting register 14 7 General Control Register 1 GCN1 14 7 General Control Register 1 GCN1 The general control register 1 GCN1 is used to select the source of PWM timer trigger input Configuration of General Control Register 1 GCN1 The configuration of the general control register 1 GCN1 is shown below GCN1 bit 15 14 13 12 11 1
399. y for EIT Event Acceptance The priority for EIT event acceptance is the order in which an EIT event to be accepted for an EIT sequence is selected In the EIT sequence PS and PC are saved PC is updated as needed and the other EIT events are masked The handler of an EIT event accepted earlier is not always executed first Table 2 8 4 lists the priority levels for acceptance of individual EIT events Table 2 8 4 Priority for EIT Event Acceptance and Masking Other Events Acceptance EIT event priority Reset Masking other events The other events are discarded Undefined instruction exception Cancel INT instruction flag 0 Coprocessor nonexistent trap Coprocessor error trap None User interrupt ILM Level of accepted event NMI for user ILM 15 Step trace trap ILM 4 INTE instruction ILM 4 After an EIT event is accepted and mask processing is performed for other events the handlers of the concurrent EIT events are executed in the order shown in Table 2 8 5 62 2 8 EIT Exception Interrupt and Trap Table 2 8 5 EIT Handler Execution Order Handler execution order Reset 1 Undefined instruction exception Step trace trap 2 INTE instruction 2 NMI for user INT instruction User interrupt Coprocessor nonexistent trap Coprocessor error trap 4 other EIT events discarded 2 The

Fujitsu MB91F109 FR30 User's Manual

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