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Fujitsu MB91401 User's Manual

1. 60000000000000000000 T WVUTRPNMLKJHGFEDCBA 010 004 Stand off Dimensions in mm inches Note The values in parentheses are reference values mM OO Prelminary MB91 401 2004 11 12 MB91401 FUJITSU LIMITED For further information please contact Japan FUJITSU LIMITED Marketing Division Electronic Devices Shinjuku Dai Ichi Seimei Bldg 7 1 Nishishinjuku 2 chome Shinjuku ku Tokyo 163 0721 Japan Tel 81 3 5322 3353 Fax 81 3 5322 3386 htip edevice fujitsu com North and South America FUJITSU MICROELECTRONICS AMERICA INC 1250 E Arques Avenue M S 333 Sunnyvale CA 94088 3470 U S A Tel 1 408 737 5600 Fax 1 408 737 5999 http www fma fujitsu com Europe FUJITSU MICROELECTRONICS EUROPE GmbH Am Siebenstein 6 10 D 63303 Dreieich Buchschlag Germany Tel 49 6103 690 0 Fax 49 6103 690 122 http www fme fujitsu com Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD 05 08 151 Lorong Chuan New Tech Park Singapore 556741 Tel 65 6281 0770 Fax 65 6281 0220 http www fmal fujitsu com Korea FUJITSU MICROELECTRONICS KOREA LTD 1702 KOSMO TOWER 1002 Daechi Dong Kangnam Gu Seoul 135 280 Korea Tel 82 2 3484 7100 Fax 82 2 3484 7111 http www fmk fujitsu com 2004 FUJITSU LIMITED Printed in Japan Prelminary 2004 11 12 _
2. code area D bus RAM Set neither stack area nor the vector table on the instruction RAM The following operations may be performed when the instruction immediately followed by a DIVOU DIVOS instruction is a halted by a user interrupt or NMI b single stepped or c breaks in response to a data event or emulator menu 1 The D0 and D1 flags are updated in advance 2 An EIT handling routine user interrupt NMI or emulator is executed 3 Upon returning from the EIT the DIVOU DIVOS instruction is executed and the DO and D1 flags are updated to the same values as in 1 The following operations are performed when the ORCCR STILM MOVRi and PS instructions are executed 1 The PS register is updated in advance 2 Executing of EIT processing routine user interrupt e NMI 8 Upon returning from the EIT the above instructions are executed and the PS register is updated to the same value as in 1 Since some instructions manipulate the PS register earlier the following exceptions may cause the interrupt handler to break or the PS flag to update its display setting when the debugger is being used As the micro controller is designed to carry out reprocessing correctly upon returning from such an EIT event in either case it performs operations before and after the EIT as specified 1 When a user interrupt and NMI are accepted or b step is executed or c break is done by the data event or the menu of the emul
3. gt o Digital input D input D input Differential input Full D output USB I O Full D output Low D output Low D output Direction Speed Continued 17 MB91401 Prelminary 2004 11 12 Continued Circuit Remarks gt Digital input CMOS level input o Digital input m Digital output Digital output Oscillation output Control 18 e With pull up CMOS level input e Value of pull up resistance approx 33 Typ CMOS level output Oscillation circuit Prelminary 2004 11 12 MB91 401 HANDLING DEVICES Preventing Latch up When a voltage that is higher than and a voltage that is lower than Vss are impressed to the input terminal and the output terminal in CMOS IC or the voltage that exceeds ratings between to Vss is impressed the latch up phenomenon might be caused If latch up occurs the supply current increases rapidly sometimes resulting in thermal breakdown of the device Use meticulous care not to let any voltage exceed the maximum rating during device operation Separation of power supply pattern Analog APLL at the following is installed in this 51 The power supply for VCO and for digital is separated in LSI so that the oscillation characteristic of APLL may rece
4. FUJITSU SEMICONDUCTOR Prelminary DATA SHEET 2004 11 12 32 Bit Proprietary Microcontroller LSI Network Security System MB91401 DESCRIPTION The MB91401 is a network security LSI incorporating a Fujitsu s 32 bit FR family RISC microcontroller with 10 100Base T MAC Controller encryption function and authentication function The LSI contains an encryption authentication hardware accelerator that boosts the LSI s performance for encryption and authentication commu nication IKE IPsec SSL to be demanded further The MAC controller has a packet filtering function that reduces the load on the CPU for an increasing amount of packet processing In addition the board has the External interface for high speed data communication with various external hosts USB ports as general purpose interfaces and various card interfaces FEATURES e Encryption and authentication processing by hardware accelerator function The LSI performs processing five times faster than by the conventional combination of encryption authentication hardware macros and software or about 400 times faster than by software only In addition CPU processing load factor to be involved in the encryption and the authentication processing can be decreased to 1 5 or less Also the 151 uses the embedded accelerator to execute that public key encryption algorithm about 100 times faster than by software processing which generally puts an extrem
5. Chip select output pins 3 bit chip select signal pin Output the L level when accessing to external memory Read strobe output pin Read strobing signal pin Output the L level when read accessing Write strobing output pins Write strobing signal pin Output the L level when write accessing Memory clock output pin Clock for peripheral resources pin 10 External RDY input pin When the external bus is not completed the bus cycle can be extended by inputting 0 Prelminary 2004 11 12 MB91401 ETHERNET MAC CONTROLLER 17 pin Pin name Polarity Circuit Function application Clock input for reception pin MII sync signal during reception The frequency is 2 5 MHz at 10 Mbps and 25 MHz at 100 Mbps Receive error input pin It is recognized that there is an error in the reception packet when 1 is input from the PHY device at receiving Receive data valid input pin It is recognized that receive data is effective Career sense input pin The state that the reception or the transmission is done is recognized Receive data input pins 4 bit data input from PHY device Collision detection input pin When TXEN signal is active and 1 the collision is recognized The collision is not recognized without these conditions Clock input for transfer pin It becomes synchronous of MII when transmitting The frequency is 2 5 MHz at 10
6. half word data access 0 1 word data access 0 3FFH Memory The memory space of the macro consists of the following areas Direct Addressing Areas 1 0 Refer to I O Map vO RAM 4 KB and its mirror Access disallowed area D bus RAM 8 KByte External area 0000 0000H 0000 0400H 0001 0000H 0002 0000H 0003 F800H 0004 0000H FFFF FFFFH Prelminary 2004 11 12 MB91401 GENERAL PURPOSE REGISTERS 32 bits RO R1 R12 R13 R14 R15 XXXX XXXXH XXXX XXXXH 0000 0000H Initial Value Registers RO to R15 are general purpose registers The registers are used as the accumulator and memory access pointers for CPU operations Of these 16 registers the registers listed below are intended for special applications for which some instructions are enhanced R13 Virtual accumulator R14 frame pointer R15 Stack pointer The initial values of RO to R14 after a reset are indeterminate R15 is initialized to 00000000 SSP value 31 MB91 401 Prelminary 2004 11 12 MODE SETTINGS The FR family uses the mode pins MDI2 to MDIO and the mode register MODR to set the operation mode Mode Pins Three mode pins MDI 2 MDI 1 and MDI 0 are used to specify a mode vector fetch or test mode Mode pins R v r name eset vecto MDI2 to MDIO access area 000 Reserved external ROM
7. 0000 021Cu 00000000 00000000 R W 00000000 00000000 0000 0220 DMACA4 00000000 00000000 R W 0000000 XXXXXXXX 0000 0224u 00000000 00000000 R W 00000000 00000000 0000 0228 to 0000 023Cu Reserved 0000 0240 0000 0244 to 0000 0300 DMACR R W 0XX00000 XXXXXXXX Reserved 0000 0304 ISIZE RAN Instruction Cache Continued 35 MB91401 Prelminary 2004 11 12 36 Address 0000_0308H to 0000 Register Reserved 0000 4 R W 0 000000 Instruction Cache 0000 03 8 to 0000 0 Reserved 0000_03F0H 0000_03F4H BSD0 XXXXXXXX XXXXXXXX BSD1 XXXXXXXX XXXXXXXX W XXXXXXXX R W XXXXXXXX XXXXXXXX 0000_03F8x BSDC XXXXXXXX XXXXXXXX W XXXXXXXX 0000_ BSRR XXXXXXXX XXXXXXXX R XXXXXXXX XXXXXXXX Bit Search Module 0000_0400 to 0000_043CH Reserved 0000_0440 ICROO R W 241411 ICRO1 R W 241011 ICR02 RAN 11111 ICROS R W 11111 0000_0444 ICRO4 R W 11111 ICRO5 R W 11111 ICR06 R W 11111 ICR07 R W 11111 0000 0448 ICROB R W 221111 ICRO9 R W 11111 ICR10 RAN 11111 ICR11 R W dH 0000 044 ICR12 R W
8. 63 62 61 60 128127126125 185 184 183 182 8233231 0 Q AJOJN TOP VIEW SUB240W 2122 214215 159 160 161 162 98 99 1001101 lt m 9 Z Z X gt 2 29 30 31 32 signal 204 lines PLLVDD 1 line 199 PLLVSS 1 line 197 VDDI 12 lines 195 200 203 207 211 215 1219 223 227 231 235 239 VDDE 9 lines 83 196 202 208 214 220 226 232 238 VSS 16lins 1 19 37 55 193 198 201 205 209 213 217 225 229 233 237 Prelminary 2004 11 12 MB91401 PIN NUMBER TABLE Pin Number Pin name Pin Number Pin name Pin Number Pin name Pin Number Pin name UDP EXD11 SDA CFWEX EXD14 USBINS ICS0 CFCE1X CFIORDX CFCD2X UCLKSEL UDM CFRESET TDI CFA1 CFWAITX CFREGX UCLK48 5 N C CFA0 TMS XINI CFA8 CFOEX CFCE2X CFA3 PLLBYPAS CFIOWRX OSCEB CFA2 TESTO CFA6 BREAKI VDDE CLKSEL PLLVSS TRST VSS MDIO PLLVDD PLLSETO TEST1 VDDE PLL
9. Pulse width tcffwp CFWEX CFIOWRX CDWEX CFIOWRX CFD Setup time 1195 cED15 to CFD0 CDWEX CFIOWRX CFD Hold time tcfdhZ 15 to tcfwc tcfads i CFA10 to CFAO tcfceds CFCE2X CFCE1X tcffwp CFWEX CFIOWRX tcfds gt CFD15 to CFD0 gt tefdhz CFOEX CFIORDX Prelminary MB91 401 2004 11 12 ORDERING INFORMATION 240 pin plastic 69 70 MB91401 PACKAGE DIMENSION Prelminary 2004 11 12 240 pin plastic BGA 240P M01 10 00 0 10 394 004 SQ Note The actual shape of coners may differ from the dimension 240 0 30 0 10 INDEX AREA 1999 FUJITSU LIMITED 82400015 20 2 240 012 004 0 05 002 41 13 6020 044 50 0 50 020 height lt 90 D ooooooooooooooooooo D D OOOOOOOO000000000000 D D D 9090959 0000 D INDEX OOOO D D D ooooooooooooooooooo D
10. Address 0580 0000 Reserved Register RESET R W XXXXXXXX XXXXXX00 MACRORR W R 00000000 00000001 CARDSR R W 00000000 00000000 0580 0004 CARDIMR R W 00000000 00000000 CARDISR R 00000000 00000000 0580 00084 USBPLLRP R W 00000000 00000000 Chip Register 43 Prelminary MB91401 2004 11 12 aaa 44 E INTERRUPT VECTOR Interrupt source Reset Interrupt number Hexa Decimal decimal Interrupt level Address of TBR default Mode vector 000FFFF8u System reserved 000FFFF4u System reserved System reserved System reserved 000 OOOFFFE8x System reserved OOOFFFE4n Coprocessor absent trap OOOFFFEOn Coprocessor error trap OOOFFFDCu INTE instruction 000FFFD8u Instruction break exception Operand break trap 000 4 000FFFDOu Step trace trap OOOFFFCCu NMI request tool OOOFFFC8x Undefined instruction exception OOOFFFC4n NMI request Fu fixed OOOFFFCOn Ethernet MAC IF Authentication macro ICROO 000FFFBCu OOOFFFB8n IPSec Accelerator Code macro EX IF GPIO 000FFFBOu USB PC CARD IF OOOFFFACH External interrupt 5 000 8 External interrupt 6 External interrupt 7 4 Reload timer 0
11. EXD EXCSX to Data Setup time texcsds EXCSX EXD EXWRX L Pulse width texwp EXRDX EXD EXD Setup time texds EXRDX EXD 11 EXD Hold time texdh EXRDX EXD 0 EXA EXCSX EXWRX EXD15 to EXDO EXRDX i texwp e thv is 40 2 63 MB91 401 Prelminary 2004 11 12 64 9 USB interface Parameter i Remarks Input clock UCLK48 2500ppm accuracy RISE Time UDP UDM 4 2 Fall Time UDP UDM 4 2 Differential Rise and Fall Timing Matching Driver Output Resistance tzdrv UDP UDM tutfrim UDP UDM tucyc UCLK48 UDP 90 90 tutfr tutff UDM 1 The AC characteristics of the USB interface conform to USB Specification Revision 1 1 2 lt Driver Characteristics TFR TFF TFRFM gt These items specify the differential data signal rise trise and fall tfall times These are defined as the times between 10 to 90 of the output signal voltage For the full speed buffer trise and tfall are specified such that the tr tf ratio falls within 10 to minimize RFI radiation 3 lt Driver Characteristics ZDRV gt USB full speed connection is performed via a shielded twisted pair cable at a characteristic impedance of 90 15 The USB Standard stipulates that the USB driver s output impedance must be within the range of 28 Q to 44Q The USB Standard al
12. Using UCLK48 13 MB91401 Prelminary 2004 11 12 14 CARD F 41 pin Pin name Polarity Circuit Function application CF data input output pins data status command signal pin to CompactFlash card side CF address 10 to 0 output pins Address output CFA10 to pins to CompactFlash card side CF card enable output pin Byte access output pin to CompactFlash card side Note Supported for access to CFD7 to CFDO When L level is output odd number byte access of the word is shown CF card enable output pin Byte access output pin to CompactFlash card side Note Supported for access to CFD7 to CFDO When L level is output at word access even number byte access of the word is shown When the byte is accessed the even number byte and odd number byte access become possible because and CFCE2X are combined and used by it CF Attribute Common switching output pin Attribute Common switching output pin to CompactFlash card side H Common Memory select L Attribute Memory select Card connection detect input pin CFCD2X Checking connection pin of the socket and CompactFlash card It is shown that the CompactFlash card was connected when this signal and CFCD1X are both input by 0 Continued Prelminary 2004 11 12 MB91401 Continued Pin name Pin 10 Function application Card connection detect inpu
13. 000FFF9Cu Reload timer 1 000FFF98u Reload timer 2 000FFF94u UARTO Reception completed OOOFFF90n UART1 Reception completed 000FFF8Cu 000FFF88H RX completed UART1 RX completed 000FFF84u DMACO end error Ethernet MAC IF 000FFF80u 000FFF7Cu end error External IF DMAC2 end error USB OOOFFF 78x Continued Prelminary 2004 11 12 MB91 401 I U a l nterruptnumber Interrupt Address of TBR i Hexa level Decimal Hexa default Interrupt source end error 000FFF74H end error 000FFF70u System reserved System reserved 000 6 000FFF68H System reserved 000FFF64H System reserved 000FFF60H System reserved 000FFF5Cu System reserved 000FFF58H System reserved System reserved 000FFF54H 000FFF50H System reserved 000FFF4CH U TIMER0 000FFF48H U TIMER1 44 timer overflow 000FFF40H System reserved System reserved 000FFF3CH 000FFF38H System reserved 000 4 System reserved 000FFF30H System reserved 000FFF2CH System reserved 000FFF28H System reserved System reserved 000FFF24H 000FFF20H System reserved OOOFFF1Cx System reserved OOOFFF 18x System reserved OOOFFF14n System reserved
14. 0054 0000 R W 00000000 Reload Timer 1 0000 0058 TMRLR2 W TMR2 XXXXXXXX R XXXXXXXX 0000_005CH 34 TMCSR2 0000 R W 00000000 Reload Timer 2 Continued Prelminary 2004 11 12 Address 0000 0060 Register MB91401 5580 RW 00001 00 SIDRO R W XXXXXXXX SCRO R W 00000100 SMRO R W 00 0 0 UARTO 0000 0064 UTIMO R 00000000 UTIMRO W 00000000 DRCLO W UTIMCO R W 0 00001 U TIMERO 0000 0068 5581 R W 00001 00 SIDR1 R W XXXXXXXX SCR1 RAN 00000100 SMR1 R W 00 0 0 UART1 0000 0048 0000 0070 to 0000 01 UTIM1 R UTIMR1 W DRCL1 W UTIMC1 R W U TIMER1 00000000 00000000 0 00001 Reserved 0000 0200 00000000 00000000 R W 00000000 XXXXXXXX 0000 0204 DMACBO 00000000 00000000 R W 00000000 00000000 0000 0208 DMACA1 00000000 00000000 R W 00000000 XXXXXXXX 0000 020 00000000 00000000 R W 00000000 00000000 0000 0210 DMACA2 00000000 00000000 R W 00000000 0000 0214u DMACB2 00000000 00000000 R W 00000000 00000000 0000 0218 00000000 00000000 R W 0000000 XXXXXXXX
15. NMI request tool To prevent the malfunction because of the noise problem of DSU pin when ICE is unconnected the following programs are added to the interrupt handler by the cause flag which is only set by the break request from ICE ICE can be used even if this program is added Location to added The following interrupt handler Interrupt resource NMI request tool Interrupt number 13 decimal OD hexadecimal Offset TBR is default address 000FFFC8u Additional program STM RO R1 LDI 00 RO 00 is address of the break resource register LDI 0 STB R1 Clear the break resource register LDM RO R1 Trace mode If the trace mode is set to Full trace mode during debug in full trace mode built in FIFO is used as output buffer the trace memory of the main body of ICE is used and the trace data lost is not occurred the electric current is increased and D busDMA access may be lost Also the trace data lost may be occurred To take the measures do not set full trace mode Simultaneous generation of a software break and a user interrupt NMI When a software break and a user interrupt NMI occur simultaneously the emulator debugger may react as follows The debugger stops pointing to a location other than the programmed breakpoints The halted program is not re executed correctly When these problems are occurred not only the software break the hardware break
16. OOOFFF10n System reserved 000 System reserved 000FFF08H System reserved 000FFF04H Delay interrupt source bit 000 System reserved Used by REALOS 000FFEFCu System reserved Used REALOS OOOFFEF8n System reserved OOOFFEF4n System reserved 000 45 Prelminary 2004 11 12 MB91401 Continued Interrupt number Interrupt source System reserved Hexa Decimal decimal Interrupt level Address of TBR default 000 System reserved System reserved OOOFFEE8x 000FFEE4u System reserved System reserved 000FFEDCH System reserved 000FFED8H System reserved 000 4 System reserved System reserved OOOFFEDOn System reserved 000FFEC8H System reserved 000 System reserved OOOFFECOn Used by INT instruction 2 NMI Non Maskable Interrupt NMls have the highest priority among the interrupt sources handled by this module OOOFFEBCu to 000FFC00H is always selected whenever other types of interrupt sources occur at the same time f an NMI occurs the interrupt controller passes the information to the CPU Interrupt level 15 011115 Interrupt number 15 00011118 NMI detection are set and detected by the
17. TXCLK MDIO EXTERNAL IF EXCS USB IF CARD IF IF TXD3 to TXDO TXEN RXCLK RXER RXD3 to RXDO RXDV RXCRS COL MDCLK X EXA EX EXWRX DREQRX DREQTX EXIS16 USBINS UCLK48 UCLKSEL UDP UDM CFD15 to CFDO CFA10 to CFAO CFCE2X CFCE1X CFREGX CFCD2X CFCD1X CFVS1X CFRDY CFIREQ CFWAITX CFWEX CFIORDX CFIOWRX SDA SCL EXD15 to EXD0 GPIO7 to GPIO0 16 RDX k k k 0 LE SAND Prelminary 2004 11 12 MB91401 SYSTEM 9 pin Pin name Polarity Circuit Function application Clock input pin Input pin of clock generated in clock generator 10 MHz to 50 MHz frequency can be input INITXI Reset input pin This pin inputs a signal to initialize the LSI When turning on the power supply apply 0 to the pin until the clock signal input to the CLKIN pin becomes stable All built in registers and external pins are initialized and the built in PLL is stopped when 0 is asserted to INITXI NMI input pin Non Maskable Interrupt signal External interrupt input pins These pins input an external interrupt request signal For external interrupt detection set the ENIR EIRR and ELVR registers of the FR core OSCILLATOR 3 pin Pin name Polarity Circuit Mode pins These pins determine the opera
18. capacitance load Leaving the output pin that way for an extended period of time degrades the device Use meticulous care in using the device not to exceed the absolute maximum rating About Mode MDI2 to MDIO VPD pin and Test TEST3 to TESTO pin Connect these pins directly to VDDE or VSS To prevent the device from entering test mode accidentally due to noise minimize the lengths of the patterns between individual mode pins and VDDE or VSS on the PC board as possible and connect them with as low an impedance as possible About power supply pins In products with multiple VDDE VDDI or VSS pins the pins of the same potential are internally connected in the device to avoid abnormal operations including latch up However you must connect the pins to external power supply and a ground line to lower the electro magnetic emission level to prevent abnormal operation strobe signals caused by the rise in the ground level and to conform to the total output current rating The power pins should be connected to VDDE VDDI and VSS of this device at the lowest possible impedance from the current supply source It is also advisable to connect a ceramic bypass capacitor of approximately 0 1 uF between VDDE and VSS and between VDDI and VSS near this device Crystal Oscillator Circuit Noise near the OSCEA terminal may cause the MB91401 to malfunction Design the circuit board so that OSCEA terminal OSCEB terminal and the crystal oscillator and the bypa
19. communication and with mass sending and receiving FIFO that achieves a large amount of data sending and receiving Host functions include processing of data stored in a 3 KByte receive buffer and a 1 5 KByte transmit buffer and stopping of data reception when the buffers become full This enables communication control even during data transmission and reception thereby improving commu nication efficiency while reducing the CPU load 8 16 bit data port Equipped with sending and receiving data port control function Transfer rate 133 Mbps Max e General Purpose IO GPIO The interruption can be generated in the I O port in eight bits according to changing the input signal Moreover the I O setting can be done in each bit Memory Interface It is possible to connect it with an external memory e USB Function Controller It can not operate as host USB For USB FUNCTION Rev2 0FS Double Buffer Specification Continued Prelminary MB91 401 2004 11 12 E U a Continued CARD Interface CompactFlash The CompactFlash interface is a memory and I O mode correspondence It corresponds to the I O of data such as not only the memory card but also the communication cards lC Interface Master slave sending and receiving For standard mode 100 Kbps MB91 401 Prelminary 2004 11 12 W PIN ASSIGNMENT INDEX 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
20. in the address 0000_07FFu in the mode register of the FR family Register 7 6 5 4 3 2 1 0 Initial Value MODR WTH1 WTHO wr wrt Operation mode setting bits bit7 to bit2 Reserved bit Be sure to set this bit to 000000 Setting them to any other value may result in an unpredictable operation 32 Prelminary 2004 11 12 91 401 bit1 bit0 WTHO Bus width setting bits These bits specify the bus width The value of the bits is set in the DBW1 and bits in CSO area Set these bits to a value other than 11 8 bit bus width External bus mode 16 bit bus width External bus mode 32 bit bus width External bus mode Operation mode In the operation mode there are a bus mode and an access mode Bus mode Access mode 32 bit bus width External ROM 16 bit bus width bus 8 bit bus width Bus mode In bus mode the operations of internal ROM and the external access functions are controlled according to the mode setting pins MD2 to MD0 and the values of mode data Although the FR71 architecture supports this bus mode this macro cannot use the single chip or internal ROM external bus mode but can use the external ROM external bus mode only Access mode Access mode indicates the mode that controls the external data bus width and is specified by the WTH1 WTHO bits and the DBW1 DBWO
21. level that becomes the standard of the holding request withdrawal demand generation to 10000 in the FR core For the hold request cancel request occurs regardless of the HRCL register setting When the encryption authentication accelerator is used therefore NMI input may cause encryption authentication to fail to result correctly In that case the correspondence said that it will execute the encryption authentication processing under execution again is necessary Prelminary MB91 401 2004 11 12 e Notes as device Treatment of Unused Input Pins It causes the malfunction that the unused input terminal is made open and do the processing such as 1 stack or 0 stacks About Mode pins MDI2 to MDIO Connect these pins with the input buffer by 1 to 1 to prevent the malfunction by the noise and connect directly to VDD or VSS outside of ASIC Operation at start up Specify set initialization reset INIT with the terminal INITXI when you turn on the power supply Moreover connect L level input to the terminal INITXI until the input clock is steady About watch dog timer The watchdog timer function of this macro monitors a program to check whether it delays a reset within a certain period of time If the program runs out of control and fails to delay the reset the watchdog timer function resets the CPU Therefore it keeps operating until reset is specified when the watchdog timer function is made effective once Except
22. of EXD 0 8 bit Note EXD15 to EXD8 are enabled 1 16 bit DREQRX External reception data request output pin Recordable data to reception FIFO is shown DREQTX 12 External transfer data request output pin It is shown that there are data in transmission register and transmission FIFO Prelminary MB91 401 2004 11 12 E a USB IF 5 pin Pinname Pinno Polarity WO Function application USB data D differential pin signal pin on the plus side of the USB data Use the LSI with 25 Q to 30 Q 27 Q recommended external series load resistors 1 5 kO pull up resistors and about 100 resistors Input 0 when the USB macro is unused USB data D differential pin signal pin on the minus side of the USB data Use the LSI with 25 Q to 30 Q 27 Q recommended external series load resistors 1 5 kO pull up resistors and about 100 resistors Input 0 when the USB macro is unused USB insert input pin USB socket input detection pin Be sure to input 0 when not using USB macro 48 MHz input external clock input pin This pin inputs an external 48 MHz clock signal The USB macro operates based on this clock Input the clock with high accuracy as not only LSI but also a device more than 2500 ppm Input 0 when the USB macro is un used USB clock select pin Clock select pin using for USB macro 0 Using internal clock 1
23. 0 Unit Reserved 0000_0640 ASRO 00000000 R W 00000000 ACRO 1111 00 R W 00000000 0000 0644 XXXXXXXX R W XXXXXXXX ACR1 XXXXXXXX R W XXXXXXXX 0000 0648 ASR2 XXXXXXXX R W XXXXXXXX ACR2 XXXXXXXX R W XXXXXXXX 0000 064 ASR3 XXXXXXXX R W XXXXXXXX ACR3 XXXXXXXX R W XXXXXXXX 0000_0650 XXXXXXXX R W XXXXXXXX ACR4 XXXXXXXX R W XXXXXXXX 0000_0654 ASR5 XXXXXXXX R W XXXXXXXX ACR5 XXXXXXXX R W XXXXXXXX 0000 0658 ASR6 XXXXXXXX R W XXXXXXXX ACR6 XXXXXXXX R W XXXXXXXX 0000 065 ASR7 XXXXXXXX R W XXXXXXXX ACR7 XXXXXXXX R W XXXXXXXX Memory IF 0000 0660 AWR0 01111111 R W 11111111 XXXXXXXX R W XXXXXXXX 0000 0664 AWR2 XXXXXXXX R W XXXXXXXX AWR3 XXXXXXXX R W XXXXXXXX 0000 0668 AWRA XXXXXXXX R W XXXXXXXX AWR5 XXXXXXXX R W XXXXXXXX 0000 066 0000 0670 AWR6 XXXXXXXX MCRA XXXXXXXX R W XXXXXXXX MCRB XXXXXXXX AWR7 XXXXXXXX R W XXXXXXXX 0000 0674 0000 0678 IOWRO RAN XXXXXXXX IOWR1 RAN XXXXXXXX IOWR2 RAN XXXXXXXX Continued 37 MB91401 Prelminary 2004 11 12 38 Continued Address 0000 067 Register 0000 0680 CSER RAN 000000
24. 0000000 ADR R W 1XXXXXXX 010F 0004 010F 00084 to Address 0110 0000 0110 0004 DAR R W XXXXXXXX Reserved Register BC2R R W 00XX0000 Block 0 DLCRO 0X000000 DLCR4 00000010 1 DLCR1 R W 00000000 DLCR5 01000001 2 DLCR2 00000000 DLCR6 10000000 3 DLCR3 R W 00000000 DLCR7 00000000 LAN controller 0110 0008 DLCRS R W 00000000 DLCRS R W 00000000 DLCR10 R W 00000000 DLCR11 R W 00000000 0110 000 0110 0008 DLCR12 RAN 00000000 MAR8 R W 00000000 DLCR13 RAN 00000000 00000000 MAR10 R W 00000000 MAR11 R W 00000000 0110 000 MAR12 R W 00000000 MAR13 R W 00000000 MAR14 R W 00000000 MAR15 R W 00000000 0110_0008H 0110 000 BMPR12 00000000 10 00000000 BMPR14 00000000 00000111 gt 2 0110 0010 BMPR8 00000000 00000000 00000000 00000000 0110 0014 0110 0018 FILTER_CMD R W XXXXXXXX FILTER_STATUS R XXXXXXXX 0110_001 FILTER_DATA R W XXXXXXXX 0110 0020 FL_CONTROL R W XXXXXXXX 0110 0024 FL_SUBNET R W XXXXXXXX Continued 39 MB91 401 Prelminary 2004 11 12 Continued Register Address SMI_CMD R W 00000000 00000000 SMI_CMD_ST 0110 002 R W 00
25. 01 CHER R W XXXXXXX1 TCR R W 00000000 0000 0684 00XXXXXX RCR 00XXXXXX Memory IF 0000 0688 to 0000 1 An initial value is a different register at the reset level The display is the one at the INIT level Reserved 2 An initial value is a different register at the reset level The display is due to the INIT level by INITX 3 initial value is set by the WTH bit of the mode vector Address 0000 1000 Register XXXXXXXX XXXXXXXX R W XXXXXXXX XXXXXXXX 0000 1004 0000 1008 DMADAO XXXXXXXX DMASA1 XXXXXXXX XXXXXXXX R W XXXXXXXX XXXXXXXX R W XXXXXXXX XXXXXXXX 0000 100 XXXXXXXX XXXXXXXX R W XXXXXXXX 0000 1010 DMASA2 XXXXXXXX XXXXXXXX R W XXXXXXXX XXXXXXXX 0000 1014 DMADA2 XXXXXXXX XXXXXXXX R W XXXXXXXX 0000 1018 DMASA3 XXXXXXXX XXXXXXXX R W XXXXXXXX XXXXXXXX 0000_101CH 0000_1020 DMADA3 XXXXXXXX DMASA4 XXXXXXXX XXXXXXXX R W XXXXXXXX R W XXXXXXXX 0000 10241 DMADA4 XXXXXXXX R W XXXXXXXX XXXXXXXX 0000_1028 to 0000_FFFCH Reserved Prelminary 2004 11 12 MB91401 Address 010 0000 Register BSR R 00000000 BCR R W 00000000 CCR R W 1
26. 11111 ICR13 R W 11111 ICR14 R W 11111 ICR15 R W 11111 0000_0450 ICR16 RAN 11111 ICR17 R W 11111 ICR18 R W 11111 ICR19 R W 11111 0000 0454 ICR20 R W 11111 ICR21 R W ICR22 RAN 11111 ICR23 R W 11111 0000 0458 ICR24 R W 11111 ICR25 R W 11111 ICR26 RAN 11111 ICR27 R W 211111 0000 045 ICR28 RAN 11111 ICR29 R W 11111 ICR30 RAN 11111 ICR31 R W 11111 0000_0460 0000_0464 ICR32 RAN 11111 ICR36 R W 11111 ICR33 R W 11111 ICR37 R W 11111 ICR34 R W 11111 ICR38 RAW 11111 ICR35 R W 11111 ICR39 R W 11111 0000 0468 ICR40 R W 11111 ICR41 R W 11111 ICR42 R W 11111 ICR43 R W 11111 Interrupt Control Unit Continued Prelminary 2004 11 12 EE Continued Address 0000_046CH Register MB91401 ICR44 R W 11111 ICR45 R W 11111 ICR46 R W 11111 ICR47 R W 11111 Interrupt Control Unit 0000_0470 to 0000_047CH Reserved 0000_0480 RSRR R W 10000000 STCR RW 00110011 2 TBCR R W CTBR R W XXXXXXXX Clock Control 0000 0484 0000 0488 to 0000_063FH Access disallowed WPR W XXXXXXXX DIVR0 RAW 00000011 DIVR1 R W 0000000
27. Mbps and 25 MHz at 100 Mbps Transfer enable output pin It is shown that effective data is on the TXD bus It is output synchronizing with TXCLK Transfer data output pins 4 bit data bus sent to the PHY device It is output synchronizing with TXCLK SMI clock output pin SMI IF clock pin Connect to SMI clock input pin of PHY device SMI data input output pin Connect to SMI data of PHY device 11 MB91401 Prelminary 2004 11 12 EXTERNAL 23 pin Pin name Polarity yo Circuit Function application External chip select input pin Chip select input pin from external host EXA External address input pin Address input pin from external host 0 Register select 1 FIFO data select EXD15 EXD14 EXD13 EXD12 EXD11 EXD10 EXD9 EXD8 External data input output pins The I O terminal of data bus bit of bit15 to bit8 with an external host EXD7 GPIO7 EXD6 GPIO6 EXD5 GPIO5 EXD4 GPIO4 EXD3 GPIO3 EXD2 GPIO2 EXD1 GPIO1 EXDO GPIOO External data GPIO input output pins The I O terminal of data bus bit of bit7 to bitO with an external host Note When EXIS16 0 input it becomes the terminal of GPIO7 to GPIOO EXRDX External read strobing input pin Read strove input pin from external host External write strobing input pin Write strove input pin from external host EXIS16 External data bus width select input pin Bit width select pin
28. Mount resistance near the terminal of MB91401 21 MB91 401 Prelminary 2004 11 12 e Precaution when designing When evaluation MCU on the user system is operated in the state that the emulator is not connected should be treated as follow each input terminal of evaluation MCU connected with the emulator interface on the user system Therefore note that the switch circuit etc might become necessary in the user system when you design The terminal processing in each emulator interface is shown as follows Pin treatment of emulator interface DSU 3 Evaluation MCU terminal name Pin treatment RST To be connected the RST terminal with the reset output circuit in the user system Emulator interface wiring regulations Signal line name Wiring regulations ICLK The total wiring length of each signal From evaluation MCU pin to the ICS2 to ICS0 emulator interface connector pin is made within 50 mm ICD3 to ICD0 The difference of the total wiring length of each signal makes within 2 BREAKI and the total wiring length of ICLK is the shortest e Wire the pattern with capacity more than the ratings current e Each power supply and GND may cause a short circuit or reverse connec UVcc U 222 tion in between by wrong connection of a probe Insert protection circuit such as fuse into each power supply pattern to safeguard it GND e Connect directly with a power supply system pattern s
29. Rights Reserved The contents of this document are subject to change without notice Customers are advised to consult with FUJITSU sales representatives before ordering The information such as descriptions of function and application circuit examples in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device Fujitsu does not warrant proper operation of the device with respect to use based on such information When you develop equipment incorporating the device based on such information you must assume any responsibility arising out of such use of the information Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information Any information in this document including descriptions of function and schematic diagrams shall not be construed as license of the use or exercise of any intellectual property right such as patent right or copyright or any other right of Fujitsu or any third party or does Fujitsu warrant non infringement of any third party s intellectual property right or other right by using such information Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein The products described in this document are designed developed and manufactured as contemplated for general use including with
30. SET1 INITXI OSCC VSS TCK NMIX PLLS VDDI TXDO D13 D11 MDIO RXDO D16 D14 vss TXCLK D19 D22 VDDE RXD2 D21 D25 VDDI RXCLK D24 D29 EXD3 GPIO3 EXIS16 D28 D31 vss EXCSX D30 TXD2 CFVS1X EXDO GPIOO TXD1 TXD3 VDDI EXD4 GPIO4 RXD1 RXDV VDDE EXD7 GPIO7 RXER COL VSS EXD10 RXD3 DREQRX CFVCC3EX VSS RXCRS DREQTX VDDI EXD12 EXA EXWRX 4 EXD13 EXRDX EXD2 GPIO2 vss CFCD1X EXD1 GPIO1 EXD6 GPIO6 VDDE SCL EXD5 GPIO5 EXD9 VDDI CFRDY EXD8 EXD15 CFD6 MB91401 PIN DESCRIPTION Prelminary 2004 11 12 SYSTEM XINI INITXI NMIX INT7 to INT5 MDI2 to MDIO OSCILLATOR OSCEA OSCC OSCEB PLL CONTROL PLLS PLLSET1 PLLSETO PLLBYPAS CLKSEL ICE ICS2 to 1250 ICLK ICD3 to ICDO JTAG TCK TRST TMS TDI TDO TEST VPD TESTS to TESTO UART SIN1 SINO SOUT1 SOUTO SCK1 SCKO MEMORY IF A23 to AO D31 to DO RDX WRX3 to CSX0 CSX1 CSX6 RDY MCLKO G G i alma a nn wn NNN Ra MB91401 Signal line Power Supply GND N C 196 pin 39 pin 5 pin BGA 240P M01 ETHERNET MAC CONTROLLER
31. VDDE 0 3 V at power on 3 The maximum output current is the peak value for a single pin 150 4 The average output current is the average current for a single pin over a period of 100 ms 5 The total average output current is the average current for all pins over a period of 100 ms WARNING Semiconductor devices can be permanently damaged by application of stress voltage current temperature etc in excess of absolute maximum ratings Do not exceed these ratings Notes Apply equal potential to all of the pins Apply equal potential to all of the VDDI pins e Fix all of the VSS pins at 0 V Leave N C pins open 47 48 MB91401 2 Recommended Operating Conditions Parameter Prelminary 2004 11 12 VSS PLLVSS 0 V 3 0 Internal 1 65 Analog power supply voltage PLLVDD VSS 3 0 Operating temperature Ta 10 WARNING The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device All of the device s electrical characteristics are warranted when the device is operated within these ranges Always use semiconductor devices within their recommended operating condition ranges Operation outside these ranges may adversely affect reliability and could result in device failure No warranty is made wi
32. XXXXXX DATA R W 00000000 00000000 POLLINTVL R W 00000000 00000000 ADD 0110 0028 0110 0030 0110 0034 0110 00384 R W 00000XXX SMI CONTROL 0110 003 R W 111XXXXX STATUS R XXXXXXXX SMI_INTENABLE 0110 0044 R W OXXXXXXX SMI_MDCDIV 0110 0048 R W 01011XXX The attribute is different according to the bit 0110 0040 40 Prelminary 2004 11 12 MB91401 Address 0114 0000 Register EXIFRXDR R 00000000 00000000 00000000 00000000 0114 0004 EXIFTXDR W 00000000 00000000 00000000 00000000 0114 0008 00000000 00000000 0114 000 0114 0010 EXIFTXRIW 00000000 00000000 EXIFCR W 00000000 0XXXXXXX External IF 0114 0014 EXIFSRIR 00000000 00 0114 0018 EXIFRXSR R 00000000 00000000 00000000 00000000 0114 001 EXIFTXSR R 00000000 00000000 00000000 00000000 0114 0020 PIOCR R W 00000000 0114 0024u Address 0500 0 PIODR R W Connecting destination Register IR R W 00000000 DR R W Reserved 1000001 1 RR R W 00000000 0501 0000 to 0501_07 AMR Attribute Memory Area window 0 Compact FLASH IF 0501_1000 to 0501 17 Common Memory Area window 1 41 42 MB91401 rs A
33. an ICE is connected JTAG 5 pin Pin name Circuit Emulator data pins These pins serve as the emulator data bus when an ICE is connected Function application JTAG test clock pin Note Please input 1 when unused JTAG test reset pin Note Please input O when unused TAP controller mode select pin Note Please input 1 when unused JTAG test data input pin JTAG test serial data input pin Note Please input 1 when unused TEST 5 pin Pin name Circuit JTAG test data output pin JTAG test serial data output pin Function application Mode pin Input O to this pin Test pin Input 0000 to this pin Note Don t set other than above description Prelminary 2004 11 12 MB91401 UART 6 pin Pin name Polarity Circuit Function application Serial data input pins Serial data input pin of UART built in FR core Serial data output pins Serial data output pin of UART built in FR core MEMORY F 66 Pin name Polarity Circuit Serial clock I O pins Serial clock input output pin of UART built in FR core Function application Address output pins 24 bits address signal pin Continued MB91401 Prelminary 2004 11 12 Continued Pin name Polarity Circuit Function application Data input output pins 32 bits data input output signal pin
34. ator in the instruction immediately before the instruction of DIVOU DIVOS the following operation might be done 1 The DO and D1 flags are updated in advance 2 An EIT handling routine user interrupt NMI or emulator is executed 1 Upon returning from the EIT the DIVOU DIVOS instruction is executed and the DO and D1 flags are updated to the same values as in 3 2 When ORCCR STILM MOV Ri and PS each instruction is executed to permit interrupt with the user interrupt and the NMI factor generated the following operation is done 1 The PS register is updated in advance 2 The EIT processing routine user interrupt NMI or emulator is executed 8 Upon returning from the EIT the above instructions are executed and the PS register is updated to the same value as in 1 Do not access the data to the cache memory at the control register of the instruction cash and RAM mode immediately before the instruction of RETI f one of the instructions listed below is executed the SSP or USP value is not used as the R15 value and as a result an incorrect value is written to memory Only ten following kinds of instructions that specify R15 as Ri correspond AND R15 Rj R15 Rj ANDB R15 Rj OR R15 Rj R15 ORB R15 EOR R15 Rj EORH R15 Rj EORB R15 Rj R15 As for R15 there realities When R15 is accessed from the program SSP or USP is accessed by the
35. bits within to ACR7 Area Configuration Registers Bus mode The FR family has three bus modes described below Please refer to MEMORY SPACE for details 33 MB91401 Prelminary 2004 11 12 B I O MAP This shows the location of the various peripheral resource registers in the memory space How to read the table Reserved Address Register 0000 0000 asss n Read Write attribute Initial value after a reset at address 4n 2 column 1 is positioned on the MSB side of data Note Initial values of register bits are represented as follows Initial Value 1 0 lnitial Value 0 X Initial Value X Access prohibited in reserved area Register Address 0000 0000 to 0000_003CH Ext Int Register name First column register at address 4n second column register Left most register address When accessing it by word the register of Reserved 0000_0040 EIRR R W 00000000 ENIR R W 00000000 ELVR 00000000 R W 00000000 Ext Int 0000 0044u HRCL R W DICR R W 0 0 11111 DLYI I unit 0000 0048 TMRLRO W XXXXXXXX TMRO XXXXXXXX R XXXXXXXX 0000 004 TMCSRO 0000 R W 00000000 Reload Timer 0 0000 0050 TMRLR1 W TMR1 XXXXXXXX R XXXXXXXX 0000
36. current los is the maximum current that flows when the output pin is connected to or Vss within the maximum rating The current is the short circuit current per differential output pin As the USB I O buffer is a differential output the short circuit current should be considered for both of the output pins Monitor the short circuit current L level H output Short circuited at GND level 3 State Enable L H level 3 State Enable L Short circuited at VDDE level H output Monitor the short circuit current 2 About Measurement Z leakage current 7 gt Input leakage current 1 is measured with the USB I O buffer in the high impedance state when the or Vss voltage is applied to the bidirectional pin P d Monitor the leakage current Z output 0 V VDD level applied to output pin 3 State Enable H Prelminary MB91 401 2004 11 12 USB Specification Revision 1 1 Parameter Input Levels High driven Low Diffential Input Sensitivity Differential Common Mode Range Output Levels High driven Low Output Signal Crossover Voltage Terminations Bus Pull up Resistor on Upstream Port 1 5 5 Termination Voltage Upstream Port Pull up 1 Input Levels The switching threshold voltage of the USB I O buffer s single end receiver is set within t
37. ddress 0540 0000 Register FIFO0out R XXXXXXXX XXXXXXXX FIFO0in W XXXXXXXX XXXXXXXX 0540 0004 FIFO1 R XXXXXXXX XXXXXXXX FIFO2 W XXXXXXXX XXXXXXXX 0540_0008H FIFO3 W XXXXXXXX XXXXXXXX 0540 000 to 0540 001 0540 0020 Reserved CONT1 R W XXXXX0XX XXX00000 0540 0024u CONT2 R W XXXXXXXX XXX00000 CONT3 R W XXXXXXXX XXX00000 0540 0028 CONTA R W XXXXXXXX XXX00000 CONTS R W XXXXXXXX_XXXXOOXX 0540 002 CONTS R W XXXXXXXX_XXXXOOXX CONT7 R W XXXXXXXX XXX00000 0540 0030 CONT8 R W XXXXXXXX_XXX00000 CONT9 R W XXXXXXXX_OXXX0000 0540 0034 CONT10 RAN XXXX0000_X000000X TTSIZE R W 00010001 00010001 0540 0038 TRSIZE R W 00010001 00010001 0540 003 to 0540_003FH Reserved 0540 0040 RSIZEO R XXXXXXXX XXXX0000 0540 0044u RSIZE1 R XXXXXXXX X0000000 Prelminary 2004 11 12 0540 0048 to 0540 005 Reserved 0540 0060 ST1 R W XXXXXX00 00000000 0540 0064u Continued MB91401 Prelminary 2004 11 12 Continued Address 0540 0068 Register ST2 R XXXXXXXX X0000000 ST3 R W XXXXXXXX XXX00000 0540 006 ST4 R XXXXX000 00000000 ST5 R W 00000 0540 0070 to 0540 007 Reserved 0540 007 0540 0080 to 0540
38. ely heavy load microcontrollers Continued PACKAGE 244 pin plastic FBGA 240 01 FUJITSU MB91 401 Prelminary 2004 11 12 Ww For DES ECB DES CBC 3DES ECB 3DES CBC mode For MD5 SHA 1 HMAC MD5 HMAC SHA 1 mode DH group for 1 MODP 768 bit 2 1024 bit For the encryption authentication macros a software library is available by contacting the Fujitsu sales repre sentative as required Encryption function DES 3DES Method to encrypt and to decrypt plaintext in 64 bits with code and decoding key to 56 bits 3DES is repeated three times The key can be set by 168 bits or less Packet filtering function The internal feature for L3 L4 packet filtering lets specific data pass or halts them based on address IP MAC address settings Moreover the function multicast address filter function to receive the data is provided in case of the multicast address registered besides my address too IEEE 802 3 compliant 10 100M MAC MII interface for full duplex half duplex SMI interface for PHY device control Note The filtering function of layer 3 4 mount on hardware This feature determines whether to pass or discard packets when this layer 3 network layer IP addresses or layer 4 transport layer TCP UDP port numbers match conditions Outside interface with telecommunication facility EXTERNAL INTERFACE MB91401 is equipped it with the register for the
39. external interrupt NMI controller This module only generates an interrupt level interrupt number and MHALTI upon NMI request Suppressing DMA transfer upon NMI request When an NMI request occurs the MHALTI bit in the HRCL register is set to 1 suppressing DMA transfer To permit DMA transfer clear the MHALTI bit to 0 at the end of the NMI routine 46 Prelminary 2004 11 12 ELECTRICAL CHARACTERISTICS 1 Absolute Maximum Ratings Parameter Power supply 91401 Remarks VSS 4 0 VSS 2 5 Analog power supply voltage PLLVDD VSS 4 0 Input voltage Vi VDDE 0 3 Output voltage Vo VDDE 0 3 L level maximum output current T B D L level average output current loLav T B D L level total maximum output current lot T B D L level total average output cur rent T B D H level maximum output current T B D H level average output current T B D H level total maximum output current T B D H level total average output cur rent T B D Power consumption Pp T B D Operating temperature Ta 70 Storage temperature 1 This parameter is based VSS PLLVSS 0 V 2 Note that analog power supply voltage and input voltage do not exceed
40. he range from 0 8 V to mn 2 0 V TTL input standard For Viu and the LSI has some hysteresis to reduce noise susceptibility 2 Input Levels A differential receiver is used to receive USB differential data signals The differential receiver has a differential input sensitivity of 200 mV when the differential data input falls within the range from 0 8 V to 2 5 V with respect to the local ground reference level The above voltage range is referred to as common mode input voltage range 1 0 0 2 Minimum operating input sensitivity V 0 8 2 5 Common mode input voltage V 3 Output Levels The output driving performance levels of the driver are 0 3 V or less to 3 6 V 1 5 kO load in the low state and 2 8 V or more to ground 1 5 load in the high state 51 Prelminary MB91 401 2004 11 12 4 lt Output Levels Vcrs gt The cross voltage of the external differential output signals D and D falls within the range from 1 3 V to 2 0 V Vcrs standard range Max 1 3 V 5 lt Terminations gt indicates the pull up voltage at the upstream port 52 Prelminary 2004 11 12 MB91401 4 AC Characteristics The following measurement conditions depending on the supply voltage apply to the MB91401 unless otherwise specified e AC measureme
41. ionally the reset postponement is automatically done under the condition that the program execution of CPU stops Refer to the paragraph of the function explanation of the watchdog timer for the condition of applying to this exception There is a possibility that watchdog reset is not generated when entering the above mentioned state by the reckless driving of the system In that case please specify reset INIT from external INITX terminal Restrictions Clock control block Secure the clock stability waiting time at L input to INITXI When entering the standby mode use the following sequences after using the synchronous standby mode TBCR set at the bit8 SYNCS bit of timebase counter control register LDI of standby RO Value of standby is write data to STCR LDI STCR R12 STCR is address 481H of STCR STB QR12 Write to standby control register LDUB QR12 RO STCR read for synchronous standby LDUB QR12 RO Dummy re read of STCR NOP NOP NOP NOP NOP In addition set the I flag and the ILM and ICR registers to branch to an interrupt handler when the interrupt handler triggers the microcontroller to return from the standby mode Please do not do the following when the monitor debugger is used Please do not set the break point to the above mentioned instruction row MB91 401 Prelminary 2004 11 12 The instruction fetch is not done from D bus and does
42. ive the influence of power supply variation Therefore the power supply is recommended to be separated also on the mounting base e Separation of power supply pattern recommended Take measures to reduce impedance for example by using as wide a power pattern as possible The recommendation example is shown as follows For two power supplies for digital and for VCO It is advisable to provide a digital power supply a and VCO power supply b and connect them to the 1515 equivalents respectively Figure For 2 power supply for digital and for VCO VDD for digital PLLVDD for veal PLLVSS VSS For the common power supply To share a single power supply for digital and VCO uses it is advisable to separate the output into the digital and VCO wiring patternsand connect them to the LSI 19 20 Prelminary MB91 401 2004 11 12 Figure When you share the power for digital and for VCO VDD for digital PLLVDD for VCO PLLVSS VSS Treatment of the unused pins Leaving unused input pins open results in a malfunction so process the pull up or pull down Treatment of OPEN pins Be sure to use open pins in open state Treatment of output pins A large current may flow to an output pin left connected to the power supply another output pin or to a high
43. lay time tchwrh 10 WRX0 9 Data delay time tchdv D31 to DO tcycp 2 7 RDX delay time tchrdl RDX RDX delay time tchrdh RDX Data setup tdsrh D31 to D0 Data hold trhdx D31 to D0 Note tcycp is external memory clock cycle period tcycp MCLKO tchav U 23 10 ichcsl tchcsh CSX2 to CSX0 4 tchwrh WRX3 to WRX0 D31 to DO d RDX D31 to D0 55 Prelminary 91 401 2004 11 12 4 Parameter Symbol Typical timing Unit Min Max RDY setup trdys MCLKO T 19 RDY hold trdyh RDY MCLKO T 1 MCLKO RDY 56 Prelminary 2004 11 12 5 UART Parameter Serial clock cycle time SCK1 SCK0 SCLK J gt SOUT delay time SOUT1 SOUTO Valid SIN gt SCLK T SCLK T gt valid SIN hold time SIN1 SINO SIN1 SINO Conditions Internal shift clock mode 91401 Remarks 8 x timcycp 80 60 Serial clock H Pulse Width SCK1 SCK0 Serial clock L Pulse Width SCK1 SCKO SCLK J 5 SOUT delay time SOUT1 SOUTO Valid SIN SCLK T SIN1 SINO SCLK T gt valid SIN hold time Note timcycp is operational clock period of peripheral module built in FR70E core SIN1 SIN0 External shift c
44. lock mode 4 x timcycp 4 x timcycp 57 MB91 401 Prelminary 2004 11 12 Internal shift clock mode tscyc SCK1 SCK0 SOUT1 SOUTO tshix tivsh 8 e External shift clock mode tslsh tshsl SCK1 SCK0 tslov 58 Prelminary 2004 11 12 MB91 401 6 interface Parameter i Typical timing Remarks TXEN delay time tdel_txen TXEN TXD delay time tdel_txd TXD3 to TXD0 RXDV setup time tsu_rxdv RXDV RXSV Hold Time thd_rxdv RXDV RXD setup time tsu_rxd RXD3 to RXD0 RXD Hold Time thd_rxdv RXD3 to RXD0 RXERsetup time tsu_rxer RXER RXER Hold Time thd_rxer RXER e Transmission TXCLK tdel txen TXEN TXD3 to TXDO X TXCLK tdel txen TXEN TXD3 to TXDO 1 tdel 59 60 Prelminary MB91 401 2004 11 12 _ e Reception RXCLK thd_rxdv RXDV ey i thd_rxdv RXD3 to RXDO tsu_rxd RXCLK thd rxdv L tsu rxdv RXDV tsu_rxd RXD3 to RXDO v Xin ij 0 rxdv RXCLK tSU_rxer tsu rxer habueris Prelminary 2004 11 12 91 401 7 i
45. mode vector External Bus width is set by the mode data Remarks User circuit test FR stops with clock signal supplied Reserved Reserved Reserved Reserved 111 Reserved Setting MDI2 to MDI0 to 010 USRTEST is set to 1 and the device operates in the user circuit test mode The FR71 core is suspended in the user circuit test mode while SYSCLK and MCLKO are operating The reserved modes include the FR71 core test mode In this case the signal at the FRTEST pin becomes 1 and enters the FR71 core test mode If the FRTEST pin 1 that circuit configuration is required which allows the separately defined pins of the FR71 core to be controlled and monitored from the outside of the chip e Mode Register MODR The data written to the mode register MODR by hardware using a mode vector fetch is called mode data When this register is set by hardware the CPU operates in the operation mode corresponding to the register setting The mode register is set only by an INIT level reset cause The user program cannot access this register However as an exception when the macro shifts to emulation mode by INTE instruction or shifts to emulation mode by a break at a debug using ICE this register is mapped at 0000_07FDnu Select this function when using ICE perform the mode data setting before the program loading by writing a appropriate value to this register Note No data is existed
46. n a basic wave and the over tone characteristic of the oscillator of the 20 MHz to 30 MHz belt Note These reference values are standards The constant changes according to the characteristic of the quartz vibrator used Therefore we will recommend the initial evaluation that uses the evaluation sample to the decision of the circuit constant Please contact FUJITSU representatives about the evaluation sample e Notes when encryption authentication accelarator is used When using the encryption authentication installed in this LSI it is necessary to the following notes 32 bit data bus The encryption authentication accelerator fetches data from the area storing data to be subject to encryption authentication and encrypts or authenticates the data without CPU intervention In the encryption processing write is done in the area where it wants to store the data after the encryption is processed MB91401 encryption authentication accelerator At the storage destination of encryption authentication processing data Holding request withdrawal demand function OFF When accessing to the storage destination of encryption authentication processing data the encryption authen tication accelerator should hold an internal bus of this LSI Therefore when the encryption authentication accelerator are used it should be set that the holding request withdrawal doesn t demand Please set the HRCL register that sets the interrupt
47. nt condition Input Output e Load condition VIH VIL VOL OV OV 1 Clock Parameter i Conditions Fclkcyc External clock Remarks Oscillation Internal operating clock frequency FR70E peripheral module Polkin Internal operating clock frequency USBC Fusop Internal operating clock frequency PC IF Fi2op External memory clock frequency The clock frequency must be set to over 25 MHz for the Ethernet MAC interface to perform 100 Base communication Fclkcyc XINI OSCEA OSCEB 53 MB91 401 Prelminary 2004 11 12 2 Parameter i Conditions Remarks After power At unusing PLL supply amp input clock At using of PLL PLL reset input time PLLS stabilization At using of PLL Reset input time tcp is internal CPU clock cycle period for module trstl tprstl gt PLLS 54 Prelminary 2004 11 12 MB91 401 3 55 Parameter i Typical timing Remarks Address delay time tchav A23 to A0 2 7 CSX delay time 5 CSX2 to CSX0 tcycp 2 7 CSX delay time tchcsh CSX2 to CSX0 2 7 delay time tchwrl WRX3 to WRX0 9 de
48. nterface Parameter typical timing Remarks MDIO setup time tsu_mdio MDIO Hold Time thd_mdio MDIO delay time tdel_mdio MDIO switching time IN OUT tdel turnon MDIO switching time OUT IN tdel turnoff MDCLK _ L 80 9 maio tsu mdio thd_mdio MDIO INPUT MDCLK tdel_mdio i r itdel_mdio MDIO OUTPUT MDCLK Input Mode 2 3 Output Mode INPUT OUTPUT tdel_turnon MDCLK o MDIO Output Mode Input Mode OUTPUT gt INPUT turnoff 61 MB91401 Prelminary 2004 11 12 8 External IF e Read access Parameter EX Read Cycle time EXA to Data Valid EXCSX to Data Valid texrc EXA EXCSX ns texadv EXA EXD ns texcsdv EXCSX EXD ns EXRDX to Data Out Enable texdoe EXRDX EXD 5 x tcp ns EXRDX H to High Z texdhz EXRDX EXD 5xtcp 8 ns Note tcp is internal CPU and operational clock period for peripheral module EXA EXCSX EXWRX EXRDX EXD15 to EXDO texrc texadv gt i texcsdv 1 lt texdhz 62 Prelminary 2004 11 12 e Write access Value Parameter Symbol Min Max EX Write Cycle time texwc EXA EXCSX MB91401 Remarks EXA to Data Setup time texads EXA
49. out limitation ordinary industrial use general office use personal use and household use but are not designed developed and manufactured as contemplated 1 for use accompanying fatal risks or dangers that unless extremely high safety is secured could have a serious effect to the public and could lead directly to death personal injury severe physical damage or other loss 1 nuclear reaction control in nuclear facility aircraft flight control air traffic control mass transport control medical life support system missile launch control in weapon system or 2 for use requiring extremely high reliability submersible repeater and artificial satellite Please note that Fujitsu will not be liable against you and or any third party for any claims or damages arising in connection with above mentioned uses of the products Any semiconductor devices have an inherent chance of failure You must protect against injury damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy fire protection and prevention of over current levels and other abnormal operating conditions If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan the prior authorization by Japanese government will be required for export of those products from Japan
50. should also be used Do not set the break to the corresponding location when using monitor debugger Prelminary 2004 11 12 MB91 401 BLOCK DIAGRAM Crystal Unit CLKIN USB CLK 48 MHz Serial 2ch INT NMI Authentication macro LAN controller IPsec Accelerator 10 100 Ethernet pom Accelerator Controller PHY DES 3DES HMAC MD5 SHA1 USB Function USB IF Rev2 0FS DH CARD IF CompactFlash IF External IF gt PC IF gt Bus GPIO TP L3 L4 Filtering Ext IF PORT MB91401 FR core CPU U Timer UART Timer Interrupt controller DMAC Bit search External interrupt Memory IF Data RAM Cache Bus controller Peripheral resources LAN External GPIO Card Encryption Authentication USB Peripheral resource is connected to bus of bus controller 29 MB91401 Prelminary 2004 11 12 30 MEMORY SPACE Memory space The FR family has 4 GByte of logical addresses 232 address which can be linearly accessed by the CPU Direct Addressing Areas The following address space areas are used as areas These areas are called direct addressing areas in which the address of an operand can be specified directly during an instruction The direct addressing area varies as shown below depending on the size of access data byte data access 0
51. so stipulates that a discrete serial resistor Rs must be added to have balance while satisfying the above standard The output impedance of the USB 1 buffer on this LSI is about 3 0 to 190 Serial resistor Rs to be added must be 25 to 30 Q 27 Q recommended Capacitor CL of 50 pF must be added as well Prelminary 2004 11 12 MB91401 TxD TxD 3 State Notes Full speed Buffer 28 Q to 44 Equiv Imped 28 Q to 44 Q Equiv Imped e Driver output impedance 3 Q to 19 Q e Rs series resistance 25 Q to 30 Q e Add a series resistor of preferably 27 65 66 MB91 401 Prelminary 2004 11 12 10 interface e Input timing specification Parameter i O i Remarks SDA input setup time ts2sdai SDA input hold time th2sdai SCL cycle time tcscli SCL input H pulse time twhscli SCL input L pulse time twiscli SCL input setup time ts2scli SCL input hold time th2scli Initial Value bus standards STOP START RESTART SDA input ts2scli ith2scli i ts2sdai th2sdai 2 238280 01 ith2scli I EN E SCL input tcscli twhscli twlscli Output timing specification Parameter i i Remarks SCL output cycle time tcsclo SCL output H Pulse Time twhsclo SCL output L Pulse Time twisclo SCL output setup time ts2sclo SCL output hold
52. ss capacitor to ground are located as close to the device as possible It is strongly recommended to design the PC board artwork with the OSCEA terminal and OSCEB terminal surrounded by ground plane because stable operation can be expected with such a layout Prelminary 2004 11 12 MB91 401 CONNECTED SPECIFICATION MB91401 AND ICE Recommended type and circuit configuration of the emulator interface connector mounting on the user system attention when designing and wiring regulation are shown When the flat cable is used the combination of the connectors with housing should be selected Recommended type FPC cable FH10A 30S 1SH Maker Hirose Electric Co Ltd With latch e Circuit composition Please put the dumping resistance 15 Q in the series in the ICLK terminal signal because of the stability of operation when connecting it with ICE Resistance must be mounted near the terminal ICLK of this LSI when you design the printed wiring board Emulator interface connector MCU for evaluation MB2198 0 and MB2197 01 side 91401 UVcc Vcc 15 053 ICLK W ICLK ICS2 to ICS0 ICS2 to ICS0 ICD3 to ICD0 ICD3 to ICD0 BREAKI I BREAKI RST xRSTIN FR Reset output circuit Vss 1 Use the line inter connect to flow the rating current or more 2 The change circuit might become necessary and refer to Precaution when designing 3
53. state of S flag of the PS register Please specify general registers other than R15 when ten above mentioned instructions are described by the assembler Prelminary MB91 401 2004 11 12 iii e External bus interface When the bus width of the area set up as little endian is 32 bit confine to word 32 bit access when accessing the relevant area When enabling prefetch to the area set to the Little endian give the access to the corresponding area as word 32 bits access limitation In the byte and the half word access it is not possible to access it correctly e DMA Do not transfer DMA to instruction RAM Bit Search Module BSDO BSD1 and the BDSC register are only the word accesses Prelminary MB91 401 2004 11 12 _ NOTES OF DEBUG Step execution of RETI instruction In an environment where interrupts frequently occur during single step execution only the relevant interrupt processing routines are executed repeatedly during single step execution of the RETI instruction This will prevent the main routine and low interrupt level programs from being executed Do not execute step of RETI instruction for escape When the relevant interrupt routine no longer requires being debugged disable the relevant interrupt and perform debugging Operand break Do not set the access which is used for area including the address of system stack pointer to the target of data event break Interrupt handler to
54. t pin CFCD1X Checking connection pin of the socket and CompactFlash card It is shown that the CompactFlash card was connected when this signal and CFCD2X are both input by 0 CF side GND input pin GND level detection pin from CompactFlash side The 0 input to the pin assumes that the CompactFlash card can operate at 3 3 V setting the CFVCCSEX pin to the L level CFRDY CFIREQ CF ready input pin memory card Ready input pin from CompactFlash memory card side 1 Ready 0 Busy CF interrupt I O card Interrupt request pin of CompactFlash I O card It is shown the interrupt request was done from the I O card when input to this signal by O Nega Cycle wait input pin during CF execution Cycle wait input pin from CompactFlash card side 0 It is shown that there is a wait demand at the cycle under execution 1 It is shown that there is wait demand at the cycle under execution CF3 3 V power enable output pin Outputs L level when the CompactFlash card is operable at 3 3 V 234 il The output signal enables 3 3 volt power supply to the CompactFlash card The pin outputs L level only when the CFVS1X pin detects 0 otherwise the pin outputs H Posi CF reset output pin CFRESET 184 OUT Reset output pin to CompactFlash card side tive aL CompactFlash is reset at H output Nega CF read strobe output pin CFOEX 127 29 OUT Read s
55. th respect to uses operating conditions or combinations not represented on the data sheet Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand Prelminary 2004 11 12 MB91 401 3 DC Characteristics Other than USB VSS PLLVSS Parameter i Conditions H level input voltage L level input voltage H level output 3 0 V voltage 4 0 L level output 3 0 voltage 4 0 mA 3 6 V Vss lt Vi lt VSS 0 3 VDDE 0 5 Input leak current TCK TRST TMS TDI TDO CFCD2X CFCD1X CFVS1X CFRDY CFWAITX Pull up resistance Pull down resistance VDDE Voo 1 8 V Power supply 3 3 V current VDDI 50 Without power supply Input capacitance 49 50 MB91 401 Prelminary 2004 11 12 USB VSS PLLVSS 0 V Parameter Symbol Pin Conditions Remarks H level output 100 VDDE 0 2 voltage L level output lo 100 level output 0 4 V current L level output 0 4 V current output short circuit current Input leak current 1 About the output short circuit current Output short circuit
56. time th2sclo SDA output hold time th2sdao For value m refer to Section 7 5 2 3 Clock Control Register CCR in the Interface Specifications PCLK indicates 2 interface operating clock frequency STOP START RESTART SDA output o7 05 ps Dt DO Ack ts2sclo th2sclo 5219 th2sclo T gt et SCL output 0 tcsclo twhsclo IWiscio Prelminary 2004 11 12 MB91401 11 Card IF e Read access Parameter CFA10 to CFA0 CFCE2X CFCE1X CFA10 to CFD15 to CFD0 CFCE2X CFCE1X CFD15 to CFD0 CFOEX CFIORDX to Data Out CFOEX CFIORDX Enable CFD15 to CFDO CFOEX CFIORDX CFD15 to CFDO CF Read Cycle time tcfrc CFA to Data Valid tcfadv CFCEX to Data Valid tcfcedv CFIORDX H to High Z tcfdhz tcfrc lt gt i tcfadv CFCE2X CFCE1X CFWEX CFIORDX tcfdhz 15 67 68 MB91401 e Write access CF Write Cycle time tcfwc CFA10 to CFAO CFCE2X CFCE1X Prelminary 2004 11 12 Remarks CFA10 to CFA to Data Setup time tcfads CFD15 to CFDO CFCE2X CFCE1X CFCEX to Data Setup time tcfceds CFD15 to CFWEX CFIOWRX L
57. tion mode of the LSI Always set this bit to 001 Function application Crystal oscillation input pin Input pin of crystal oscillation cell Crystal oscillation control input pin Oscillation control pin of crystal oscillation cell 0 Oscillation 1 Oscillation stop PLL CONTROL 5 pin Pin name PLLS Polarity Circuit Crystal oscillation output pin Output pin of crystal oscillation cell Function application PLL through mode reset switching input pin 0 PLL through mode oscillation stop 1 PLL oscillation mode PLLSET1 Input clock division ratio select input pin 0 Input clock direct 1 Input clock divided by 2 PLLSETO Division ratio select input to PLL FB pin 0 Two dividing frequency is input to the terminal FB 1 Four dividing frequency is input to the terminal FB PLLBYPAS PLL bypass select input pin 0 PLL used 1 PLL unused CLKSEL Input clock switching input pin 0 XINI External clock 1 Built in OSC generating clock MB91401 Prelminary 2004 11 12 ICE 9 pin Pin name Circuit Function application Emulator break request pin This pin inputs the emulator break request when an ICE is connected Emulator chip status pins These pins output the emulator status when an ICE is connected Emulator clock pin This pin serves as the emulator clock pin when
58. trove output pin to CompactFlash card memory tive mode and Attribute memory area CF register write output pin Write clock output pin to CompactFlash register write CFWEX 62 OUT and Card Configuration Register area The register write is executed at the rising edge from L to read strobing output et tive BUT Read strove output pin to CompactFlash card I O mode Nega CFIO write strobing output pin 199 Our Write strove output pin to CompactFlash card I O mode 15 MB91 401 Prelminary 2004 11 12 IF 2 pin Pin name Polarity ircuit Function application Serial data line input output pin 2 bus data I O pin Serial clock line input output pin bus clock I O pin Power Supply GND 39 pin Pin name Polarity Circuit Function application PLLVDD APLL dedicated power supply pin This is 1 8 V power supply PLLVSS APLL dedicated GND Pin 3 3 V power supply pin 1 8 V power supply pin GND Pin 16 Prelminary MB91 401 2004 11 12 E a CIRCUIT With pull down CMOS level output CMOS level input Value of pull down resistance approx 33 Typ gt gt Digital input m Digital output CMOS level output Digital output CMOS level input
59. uch as grandopran e Reference document Please match and refer to the following manual for the connection with ICE DSU FR Emulator MB2198 01 Hardware Manual FR20 30 series MB2197 01 Hardware Manual 22 Prelminary 2004 11 12 MB91 401 JTAG The JTAG function is installed this LSI Note that the terminal INITXI should be input in L when using JTAG Notes when quartz vibrator is mounted The crystal oscillation circuit built into this LSI operates by the following compositions MB91401 OSCC OSCEA OSCEB nr Installation when over tone oscillates Itl Quartz vibrator L Ci C2 e Pin description Pin name Function Oscillation control terminal of crystal oscillation cell OSC Input terminal of crystal oscillation cell OSC Output terminal of crystal oscillation cell OSC When is input the OSCEA OSCEB oscillate at the natural frequency of the crystal oscillator and propagated into the LSI e Circuit constant on external substrate Circuit constants Description C1 C2 C3 External load capacity L Inductance Rr Dumping resistance addition if necessary 23 MB91 401 Prelminary 2004 11 12 24 e Reference Value to 30 MHz 5 pF to 33 pF None None None 20 MHz to 50 MHz 5 pF to 15 pF 10 nF approx 1 uH approx None It is necessary to add C3 L depending o

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