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Fujitsu F2MC-8L F202RA User's Manual

1. 271 12 5 Interrupt of A D Converter 272 12 6 Operations of A D Converter Functions 273 12 7 Notes on Using A D Converter nentes 275 12 8 Program Example for A D Converter ssssssssssssseseseeee eene nens nnne renis 277 CHAPTER MART 279 IEEE wu quaa HM M 280 19 2 Configuration of DART inito te dude Urt Deep det ex ua Ere oe Sa TE Rue ea a tech 284 13 9 Pins oL UART cse rre tee tte nut oin e eme Ert i nce o ps vet eine rent i e a res n 287 13 4 Registers O UART i uicit tu bed te CU ERE M nete ete Ede Pe Rua Ex eed re 289 13 4 1 Serial Mode Control Register 290 13 4 2 Serial Rate Control Register enne nne 292 13 4 3 Serial Status and Data Register SSD sse nennen 294 13 4 4 Serial Input Data Register SIDR sssessssssssssesee eee entente nennen 297 13 4 5 Serial Output Data Register SODR ssssssssssssesseeee nennen sinn 298 13 4 6 Clock Divider Selection Register sese 299 13 4 7 Serial Switch Register SSEL
2. 350 16 3 1 Data Setting Registers WRDRO and WRDR1 sssssssssssseseee eee 351 16 3 2 Higher Address Set Registers WRARHO and WRARH1 352 16 3 8 Lower Address Set Registers WRARLO and WRARL1 353 16 3 4 Address Comparison EN Register WREN nnne 354 16 3 5 Data Test Set Register WROR sse enne 355 16 4 Operations of the Wild Register Functions sssssssssssseseeeeeeenneen nnne 356 CHAPTER 17 FLASH MEMORY 522i iiteiscici cites pua idu uGvd nan citada rius 357 17 1 Overview of Flash Memory ccceccceceeeeceeeeeeeeeecaaeeeeaaeeceeaeeseaaaeseeeeecaaaeseeaeeesaeeeeeaaeesseeeeesaeesennees 358 17 2 Flash Memory Control Status Register FMCS 359 17 3 Starting the Flash Memory Automatic Algorithm sess 361 17 4 Confirming the Automatic Algorithm Execution State sssssssssssseeeeene 362 17 4 Data Polling Flag DQ7 Aereas eie reete tei te ieu dte s eed ide 363 17 4 2 Toggle Bit Flag DQO iiie e ern ote i ACE Ye nn LORI Ra Oe Rx secu 364 17 4 8 Timing Limit Exceeded Flag DQ5 sssssssssssesseeeeen eene nnne nnne 365 17 4 4 Toggle Bit 2 Flag
3. 215 9 4 3 12 bit PPG Control Register RCR23 216 9 4 4 12 bit PPG Control Register 4 RCR24 218 9 5 Operations of 12 bit PPG Timer Functions enne nennen nnns 219 9 6 Notes on Using 12 bit PPG Timer 221 9 7 Program Example for 12 bit PPG Timer ssssssssssssssseseeeeee entente nnne ens 223 vii CHAPTER 10 EXTERNAL INTERRUPT CIRCUIT 1 EDGE seu 225 10 1 Overview of External Interrupt Circuit 1 essent nennen nennen nens 226 10 2 Configuration of External Interrupt Circuit 1 227 10 3 Pins of External Interrupt Circuit 1 rns 229 10 4 Registers of External Interrupt Circuit 1 essen nennen nennen 231 10 4 1 External Interrupt Control Register 1 EIC1 232 10 4 2 External Interrupt Control Register 2 1 2 235 10 5 Interrupt of External Interrupt Circuit 1 ennemis 237 10 6 Operations of External Interrupt Circuit 1 essen nnne 239 10 7 Program Example for External Interrupt Circuit 1 sse 241 CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT 2 LEVEL 243 11 1 Overview of External I
4. 96 4 5 2 Operations of Port 5 Functions nnns nnne nnne nnns 98 4 6 100 4 6 1 Registers of Port 6 PDR6 DDR6 PULO 103 4 6 2 Operations of Port 6 Functions ssssssssssssseeeseeeeneen nennen nennen 105 4 7 a re i eben einst to ted ai eese 107 4 7 1 Registers of Port 7 PDR7 DDR7 PUL7 nnnm enne E 109 4 7 2 Operations of Port 7 F nctlons reete etd ee dene 111 4 8 Programming Example of Port ssssssssssssseseeseneneneee nennen senten etnies 113 CHAPTER 5 TIME BASE TIMER nsise anon no auk rana unda paar acu cd nnb tu ndn er an an pina 115 5 1 Overview of Time base Timer ssssssssssssssesss esent nsn nnne en ness nanne nnt 116 5 2 Configuration of Time base Timer 118 5 3 Time base Timer Control Register TBTO sssssssssssssseeeneeeere enne nennen 119 5 4 Interrupt ot l ime base Timer e ehe bee deti eee anes 121 5 5 Operations of Time base Timer Functions sssssssssssseeseeeeeeen nennen nennen 122 5 6 Notes on Using Time base Timer 12
5. 324 Block Diagram for 8 bit Serial I O Pins 318 Block Diagram of 8 bit Serial I O 315 Interrupt at Serial I O Operation 324 Notes on Using 8 bit Serial I O 333 Pins of 8 bit Serial 317 Registers of 8 bit Serial I O 319 Serial I O Function eee cece seen eee eees 314 When Bidirectional Serial I O Operation is Performed DM 334 Serial Input Operation at Serial Input Completion 328 Program Example for 8 bit Serial Input 337 Serial Input Operation 327 Serial Input Data Register Serial Input Data Register SIDR 297 Serial Mode Control Register Serial Mode Control Register SMC 290 Serial Mode Register Serial Mode Register SMR 320 Serial Output Operation at Serial Output Completion 326 Program Example for 8 bit Serial Output 336 Serial Output 325 Serial Output Data Register Serial Output Data Register SODR 298 Serial Rate Control Register Serial Rate Control Register SRC 292 Serial Status and Data Register Serial Status and Data Register SSD 294 Serial Switch Serial Switch eei eert
6. EI2 sL21 5120 EIE x 0 0 0 x x pes Re Ee Ee E PEN TE 0 x Used bit Unused bit Set 0 When the polarity of an edge or edges of a signal input from one of the external interrupt pins 1 INTIO to INT12 matches the selected edge polarity for the pin stored in the appropriate external interrupt control register BICI EIC2 SLOO to SL21 one of the external interrupt request flag bits EIC1 EIC2 EIRO to EIR2 corresponding to the pin is set to 1 239 CHAPTER 10 EXTERNAL INTERRUPT CIRCUIT 1 EDGE Figure 10 6 2 shows the operation when an external interrupt is input to the INT10 pin Figure 10 6 2 Operation of External Interrupt 1 INT10 Pulse waveform input to INT10 pin M Cleared when EIEO bit Cleared by Interrupt request flag bit is is set program cleared by the program EIRO bit EIEO bit 5101 bit SLOO bit IRQO OR detection Rising edge Falling edge Both edges Note Even when the pin is used as an external interrupt input pin the pin state can be read directly from the port data register PDR3 240 CHAPTER 10 EXTERNAL INTERRUPT CIRCUIT 1 EDGE 10 7 Program Example for External Interrupt Circuit 1 An example of programming external interrupt circuit 1 is given below External Interrupt Circuit 1 Programming Example Processing specification External interrupt circuit 1 detects the risin
7. 129 Branch Branch Instructions eceeeecseeeeeeeeeaeeneeeeeeeees 397 Buzzer Output Block Diagram of the Buzzer Output 341 Block Diagram of the Pin Related to the Buzzer O T fete nena inc 342 Buzzer Output Function ee 340 Program Example for Buzzer Output 345 Buzzer Register Buzzer Register BZCR sess 343 BZCR Buzzer Register BZCR esses 343 C Cancellation Cancellation of Standby Mode by an Interrupt A exe 70 Capture Function Operation 193 Capture Control Register Capture Control Register TCCR 171 Capture Data Registers Capture Data Registers H and L TCPH and TCPL M 182 Capture Timer Counter Registers of 8 16 bit Capture Timer Counter 170 CCR Configuration of the Condition Code Register CCR HP 29 Changing Edge Polarity Selection Exercise Caution when Changing Edge Polarity Selection etcetera 238 Choice Choice of the Transfer Clock Rate 281 Circuit Association between the Interrupt Enable Bits for External Interrupt Circuit 2 and the External Interrupt Pins 248 Block Diagram of Circuitry Terminating at the Pins Associated with External Interrupt
8. pull up OFF P02 pull up OFF P01 pull up OFF POO pull up OFF pull up ON P02 pull up ON P01 pull up ON POO pull up ON PULO7 PULO6 PULO5 9 pull up OFF P06 pull up OFF Pos pull up OFF pull up OFF P07 pull up ON P06 pull up ON P05 pull up ON P04 pull up ON R W Readable Writable C Initial value 81 CHAPTER 4 I O PORTS 4 2 2 Operations of Port 0 Functions This section describes the operation of port 0 B Operation of Port 0 Operation in output port mode When 1 is written to a bit of the DDRO register the bit corresponding to a pin of port O the pin functions as an output port In output port mode the output transistor operation is enabled and the output latch data is output to the pin Once data has been written into the PDRO register the written data is held in the output latch and output to the pin as it is The value state of the pin can be read by reading the PDRO register Operation in input port mode When is written to a bit of the DDRO register the bit corresponding to a pin of port 0 the pin functions as an input port In input port mode the output transistor is OFF and the pin status is Hi Z Once data has been written into the PDRO register the written data is held in the output latch but is not output to the pin The value state of the pin can be read by reading the PDRO register Operation in external int
9. Readable and Writable Unused Undefined 350 CHAPTER 16 WILD REGISTER FUNCTION 16 3 1 Data Setting Registers WRDRO and WRDR 1 The data setting registers WRDRO and WRDR1 are registers where the correct data used by the wild register function is set m Data Setting Register WRDR Figure 16 3 2 Data Setting Register WRDR Address bit7 bit5 bit4 bit3 bit2 bit bitO Initial value WRDRO 00424 RD07 90000000 R W R W R W R W R W R W R W R W WRDR1 00454 XXXXXXXXB R W R W R W R W R W R W R W R W R W Readable and Writable X Undefined Table 16 3 1 Functions of Data Setting Register WRDR 1 byte registers that store the data at the address assigned by WRARL and WRARH The data will be effective at the addresses WRARL and WRARH corresponding to the individual wild register numbers Note The WRDR register is readable only when the WREN register address comparison EN register is set 351 CHAPTER 16 WILD REGISTER FUNCTION 16 3 2 Higher Address Set Registers WRARHO and WRARH1 The higher address set registers VRARHO and WRARH 1 are registers where the higher byte of addresses to be corrected by the wild register function are set m Higher Address Set Register WRARH Figure 16 3 3 Higher Address Set Register WRARH Address bit7 bit6 bit5 bit4 bit3 bit2 bit bito Initial value WRARHO 0040 H B R W R W R W R W R W R W R W R W WR
10. 289 UPC Clock Divider Selection Register UPC 299 V Vector Table 8 bit Serial I O Interrupt Register and Vector Tablette teet is 324 Register and Vector Table Related to 8 16 bit Capture Timer Counter of Interrupts 184 Register and Vector Table Related to Interrupts from Time base Timer 121 Register and Vector Table Related to the Interrupt of the A D 272 Register and Vector Table Related to the Interrupts of an 8 bit PWM Timer 147 Register Associated with Interrupt Generation by External Interrupt Circuit 1 and Vector Table ossi dee tee deus 238 Register Associated with Interrupt Generation by External Interrupt Circuit 2 and Vector Tables tete nde 253 UART Interrupt Related Registers and Vector Table Addit68868 tecti deri amete 303 Vector Table Area Vector Table Area Address FFCOy to FFFFy 24 W Watchdog Control Register Watchdog Control Register WDTC 130 Watchdog Timer Block Diagram of Watchdog Timer 129 Notes on Using Watchdog Timer 132 Operations of Watchdog Timer 131 Programming Examples of Watchdog Timer TREE 133 Software Reset Watchdog Timer Reset 373 Watchdog Timer Function 128 WDTC Watchdog Control Register WDTC
11. entente tentent snnt 301 13 5 eise dae tea miae ttes A 303 13 6 Operations of UART Functions t vett itte a a ra Yee dat atus 304 13 6 1 Transmission Operations Operating Mode 0 1 2 and 3 306 13 6 2 Reception Operations Operating Mode 0 1 or 3 307 13 6 3 Reception Operations Operating Mode 2 Only 309 13 7 Program Example for UART 311 CHAPTER 14 8 BIT SERIAL WO once an aiana 313 14 1 Overview of 8 Bit Serial l O sssssssssssessssssssseeee nennen nnne enn ten 314 14 2 Configuration of 8 Bit Serial V O nennen 315 14 3 Pins of 8 Bit Serial l O ict tice tutes E ee Dd ep dated oe due Das ETE a UR ee bd 317 14 4 Registers of 8 Bit Serial W O 2 titt tetti aara AAAA RE 319 14 4 1 Serial Mode Register nensi trennen sineret 320 14 4 2 Serial Data Register SDR sssssssssssssssssssee 323 14 5 Interrupt of 8 Bit Serial l O ssssesssssssssesesssseseesee entente nnne nens 324 14 6 Operations o
12. CHAPTER 9 12 BIT PPG TIMER 9 2 Configuration of 12 bit PPG Timer Circuit The 12 bit PPG timer comprises the following seven blocks Count clock selector 12 bit counter e Comparator 12 bit PPG control register 1 RCR21 12 bit PPG control register 2 RCR22 12 bit PPG control register 3 RCR23 12 bit PPG control register 4 RCR24 m Block Diagram of 12 bit PPG Timer Figure 9 2 1 Block Diagram of 12 bit PPG Timer Internal data bus RCR21 COCO Y 4 3 xsci1i Hscto HSC9 HSC7 Hsce RCR22 L LL J Compare value for H width 12 bit counter s P37 BZ PPG pin T Compare value for cycle period Eq pq SCL9 sci 5017 ScLe RCR24 1t INST E ee RcEN 5015 scra 5 5 1 2 sc1 scuo Internal data bus tinst Instruction cycle 209 CHAPTER 9 12 BIT PPG TIMER Count clock selector This selector circuit selects one of four types of internal count clocks as the count up clock for a 12 bit counter 12 bit counter The 12 bit counter executes a count up operation based on the count clock selected by the count clock selector This counter may be cleared according to the value of the output enable bit of the RCR23 register RCR23 RCEN 0 Comparator The comparator maintains outputs at until a count by the 12 bit counter has been synchronized with the value of the r
13. 244 Functions of I O Ports 76 Functions of Port 0 Registers 80 Functions of Port 3 Registers 86 Functions of Port 5 Registers 96 Functions of Port 6 Registers 103 Functions of Port 7 Registers 109 Functions of the Dedicated Register 27 Functions of UART rrisnin ninsi 280 G Gears Gears Clock Speed Switching Function 58 General purpose Register Configuration of the General purpose Registers P 32 Features of the General purpose Registers 33 General purpose Register Area General purpose Register Area Address 0100y to 24 H Halfway Stop Operation in Standby Mode and at Halfway Stop 197 Hardware Reset Input of a Hardware Reset RST 373 Hardware Sequence Hardware Sequence 1 362 High voltage High voltage supply on RST pin applicable to MB89F202RA only HT 358 Higher Address Set Register Higher Address Set Register WRARH 352 How to How to disable the Flash Security Feature 372 How to enable the Flash Security Feature 372 8 bit Serial I O Interrupt Register and Vector Table T n 324 Bloc
14. 84 m Block Diagram of Port 3 CHAPTER 4 I O PORTS Figure 4 3 1 Block Diagram of Port 3 E li i mene bos Sup External interrupt occurring Input to i I peripheral In Hysteresis input fo CMOS input Internal data bus PDR read read when read modify write is performed PDR write DDR write Stop mode from Ba SPL 1 Pull u resistor a Output occurring P sab from peripheral i Output latch Stop mode SPL 1 Note PUL read PUL write Because the value states of the pins are always input to the external interrupt circuit when a pin is used as a normal I O port the operation of the external interrupt circuit corresponding to the pin must be inhibited See CHAPTER 10 EXTERNAL INTERRUPT CIRCUIT 1 EDGE m Registers PDR3 DDR3 and PUL3 of Port The registers PDR3 DDR3 and PUL3 are associated with port 3 The bits of these registers correspond to the pins of port 3 in one to one correspondence Table 4 3 2 tabulates the correspondence between the pins and the bits of port 3 registers Table 4 3 2 Correspondence between the Pins and the Bits of Port 3 Registers Bits of associated registers and corresponding pins PDR3 DDR3 PUL3 Pin corresponding to bit 85 CHAPTER 4 I O PORTS 4 3 1 Registers of Port 3 PDR3 DDR3 PUL3 This section describes the registers associated with port 3 m Functions of Port 3 Registers
15. 95 CHAPTER 4 I O PORTS 4 5 1 Registers of Port 5 PDR5 DDR5 PUL5 This section describes the registers associated with port 5 m Functions of Port 5 Registers 96 Port 5 data register PDR5 The PDRS register indicates the state of pins For a pin set to function as an output port the same value 0 or 1 as held by the output latch can be read from this register If the pin is set to function as an input port however its output latch value cannot be read from the register Note When a bit manipulation instruction SETB CLRB is executed the output latch values not the value states of the pins are read thus output latch values excepting those for bits to be manipulated do not change Port 5 data direction register DDR5 A bit of the DDR5 register sets the I O direction of the pin corresponding to the bit When the bit of the DDR5 register is set to 1 the pin functions as an output port When the bit is set to 0 the pin functions as an input port Setting the output from a peripheral enable If a peripheral with an output pin is used set the output enable bit of the peripheral enable As it is apparent from the block diagram the pin in this mode serves output from the peripheral thereby superseding its general purpose port function Because the output from the peripheral has priority the values set on the PDR5 and DDR5 registers for the output pin used for the peripheral
16. Carry flag C When a carry from bit7 or a borrow to bit7 occurs as a result of an arithmetic operation the carry flag is set to 1 Otherwise the carry flag is cleared with 0 The shift instruction causes the value to be shifted out 29 CHAPTER 3 CPU Figure 3 2 3 shows how the shift commands change the carry flag Figure 3 2 3 Change of the Carrier Flag by the Shift Commands Shiftto the left ROLC Shift to the right RORC bit bit bit gt hi0 ft Note The condition code register is part of the program status register PS and thus is not allowed to access only the condition code register It is uncommon to fetch and use only some of the flag bits directly Normally branch instructions such as BNZ or decimal adjustment instructions such as DAA and DAS use them indirectly The initial values of these flags specified after the reset operation are undefined Bits for Controlling Acceptance of Interrupts Interrupt enable flag 1 When this flag is 1 interrupts are allowed and the CPU accepts interrupts When this flag is 0 interrupts are prohibited and the CPU does not accept interrupts The initial value of the interrupt enable flag after the reset operation is 0 Normally the SETI instruction sets the interrupt enable flag to 1 and the CLRI instruction sets it to 0
17. Port 7 data register PDR7 Port 7 data direction register DDR7 Port 7 pull up setting register R W Readable and Writable W Write only X Undefined PUL7 1 DDRO and DDR3 cannot be used for bit manipulation instructions 2 DDR6 is not used in MB89F202 F202RA 77 CHAPTER 4 I O PORTS 4 2 Port 0 Port 0 is a general purpose I O port and may also serve as peripheral inputs The pins of this port can be used for peripherals or normal port function that can be selected according to the setting of a bit corresponding to the pin on a specific register This section mainly explains the general purpose I O function of the port This section also describes the structure pins and associated registers of port 0 and provides a block diagram of pins B Structure of Port 0 Port 0 comprises the following four elements e General purpose I O pins external interrupt 2 and analog input pins POO INT20 AN4 to PO7 INT27 Port 0 data register PDRO e Port 0 data direction register DDRO e Port 0 pull up setting register PULO m Pins of Port 0 Port 0 has eight general purpose I O pins When used as input pins at the same time these pins can be also used as external interrupt input pins Table 4 2 1 lists the pins of port 0 Table 4 2 1 Pins of Port 0 Peripherals for which a pin Input and output form Circuit may serve Input Output type Pin name Function general
18. eee 36 Configuration of the Register Bank Pointer RP 31 Configuration of the Reset Flag Register RSFR MEI 45 Configuration of the System Clock Control Register SYCC P M 56 Data Setting Register WRDR 351 Dedicated Register Configuration 27 External Interrupt 2 Flag Register EIF2 252 External Interrupt Circuit 2 Control Register EIE2 250 External Interrupt Control Register 1 EIC1 232 External Interrupt Control Register 2 EIC2 Lees ERR RR 235 Features of the General purpose Registers 33 Flash Memory Control Status Register FMCS 359 Flash Memory Register eese 358 Functions of Port 0 Registers 80 Functions of Port 3 Registers 86 Functions of Port 5 Registers 96 Functions of Port 6 Registers 103 Functions of Port 7 Registers 109 Functions of the Dedicated Register 27 General purpose Register Area Address 0100y to O1FFp 24 Higher Address Set Register WRARH 352 Lower Address Set Register WRARL 353 Operation Order of the Wild Register Function Y EX E a 356 PWM Compare Register
19. 47 Function of the External Reset Pin 47 Influence from a Reset of Contents in RAM 49 Input of a Hardware Reset RST 373 Overview of the Reset Operation 48 Setting the Read Reset State 368 Software Reset Watchdog Timer Reset 373 State of Reset Waiting for Stabilization of Oscillation Liege eae andae ead datae roa 49 States of Pins during 50 Reset Flag Register Configuration of the Reset Flag Register RSFR vaste a deae 45 Reset Sources Reset SOUIC6S seite 43 Reset Sources and Oscillation Stabilization Wait TIME ziii erede eee 44 Reset Waiting State of Reset Waiting for Stabilization of Oscillation 49 Configuration of the Register Bank Pointer RP UTD 31 RSFR Configuration of the Reset Flag Register RSFR 45 RST Input of a Hardware Reset RST 373 RST pin High voltage supply on RST pin applicable to MB89F202RA only DT 358 S SDR Serial Data Register SDR 323 Serial Data Register Serial Data Register SDR 323 Serial Function Switching Serial Function Switching ees 314 Serial 8 bit Serial I O Interrupt Register and Vector Table S a a o
20. CPU This chapter describes the functions and operations of the CPU 3 1 Memory Space 3 2 Dedicated Register 3 3 General Purpose Registers 3 4 Interrupts 3 5 Reset 3 6 Clock 3 7 Standby Mode Low Power Consumption Mode 3 8 Memory Access Mode 21 CHAPTER 3 CPU 3 1 Memory Space The MB89202 F202RA series has 64 KB memory space that consists of the I O area RAM area ROM area and external area Part of the memory space is applied for specific use such as general purpose registers or a vector table m Configuration of Memory Space 1 0 area address 0000 to 007F The control registers and data registers for built in peripheral functions are assigned The I O area is assigned as part of the memory space thus access to the I O area can be obtained in the same manner as access to memory Also direct addressing provides high speed access RAM area Static RAM is equipped as the internal data area The size of internal RAM depends on the model Direct addressing allows high speed access to an area from 80g to FFy Some models restrict the usable range of the area 100g to 1FFy can be used as the general purpose register area If a reset occurs while data is being written into RAM the data being written cannot be guaranteed ROM area ROM is equipped as the internal program area The size of internal ROM depends on the model FFCOg to FFFFy are usable as a vector table or another feature
21. OUT write 264 CHAPTER 12 A D CONVERTER 12 4 Registers of A D Converter Figure 12 4 1 shows the registers related to the A D converter m Registers Related to the A D Converter Figure 12 4 1 Registers Related to the A D Converter ADC1 A D control register 1 Address bit7 bit6 bit5 bit4 bit3 bit2 bit bito Initial value 00300 ANS2 ANS1 ANSOo AD AbMV RESVO AD 0000000B RW RW RW RW R RW RW ADC2 A D control register 2 Address bit7 bit6 bit5 bit4 bit3 bit2 bit bito Initial value 00314 RESV4 RESV3 ADCK ADIE REsva EXT RESV1 00000018 RW RW RW RW RW RW RW ADDH A D data register H Address bit7 bit6 bit5 bit4 biti bito Initial value 0032H R R ADDL A D data register L Address bit7 bit bit4 bit bit bito Initial value T T T I T T L oooecs R R R R R R R R ADEN A D enable register Address bit7 bit6 bit bito Initial value 0034H ADE7 ADE6 ADE5 ADE4 ADES ADE2 ADE1 ADEO 00000000B RW RW RW RW RW RW RW RW Read only Unused R W Readable Writable R X Undefined 265 CHAPTER 12 A D CONVERTER 12 4 1 A D Control Register 1 ADC1 A D control register 1 ADC1 is used to set the enabling and disabling functions of the A D converter select an analog input and check the status B A D Control Register 1 ADC1 Figure 12 4 2 A D Control Register 1 ADC1 Address bit7
22. Set 0 To set the 16 bit capture mode set the TCS12 TCS11 and TCS10 bits of the timer 1 control register TCR1 to 111g In the 16 bit mode timers are controlled by the timer control register TCRO The higher 8 bits of the number of detected events are stored in the capture data register H TCPH and the lower 8 bits are stored in the capture data register L TCPL For operation in the 16 bit mode see operation in the 8 bit mode CHAPTER 8 8 16 BIT CAPTURE TIMER COUNTER 8 9 8 16 bit Capture Timer Counter Operation in Each Mode This section describes the operation of the 8 16 bit capture timer counter when it switches to the sleep or stop mode or when a halfway stop request is issued during the operation of the interval timer or counter function B Operation in Standby Mode and at Halfway Stop Figure 8 9 1 shows the counter value states if the 8 16 bit capture timer counter switches to the sleep or stop mode or when a halfway stop request is issued when the interval timer or counter function is in operation at timer O operation When the counter switches to the stop mode it retains the value and stops If the stop mode is released by an external interrupt the counter starts its operation at the retained value and so the first interval time and external clock count are incorrect When the stop mode is released the 8 16 bit capture timer counter must be initialized When the counter is temporarily stopped
23. 22 CHAPTER 3 CPU m Memory Map Figure 3 1 1 Memory Map MB89V201 MB89202 MB89F202 F202RA RAM 512 bytes RAM 512 bytes RAM 512 bytes x x 2 ge 2 D D o rai ra Not available Not available Not available External EPROM ads ROM 16 KB Flash 16 KB 23 CHAPTER 3 CPU 3 1 1 Specific purpose Areas In addition to the I O area the general purpose register area and vector table area are available as areas for specific applications General purpose Register Area Address 0100 to 01FF This area is used for 8 bit arithmetic operations and transfer Supplementary registers are provided Since this area is allocated to a part of the RAM area it can also be used as normal RAM When this area is used as a general purpose register it can be accessed faster using shorter instructions by general purpose register addressing For details see Section 3 2 2 Register Bank Pointer RP and Section 3 3 General Purpose Registers m Vector Table Area Address FFCO to FFFF This area is used as vector tables of the vector call instructions interrupts and reset This area is allocated to the highest ranges of the ROM area and the start address of the corresponding processing routine is set to the address of each vector table Table 3 1 1 provides the reference addresses in the vector table that correspond to the vector instructions interrupts and reset For de
24. 367 CHAPTER 17 FLASH MEMORY 17 5 1 Setting The Read Reset State This section describes the procedure for issuing the Read Reset command to set the flash memory to the read reset state B Setting the Read Reset State 368 The flash memory can be set to the read reset state by sending the Read Reset command in the command sequence table see Table 17 3 1 in Section 17 3 Starting the Flash Memory Automatic Algorithm continuously to the target sector in the flash memory The Read Reset command has two types of command sequences that execute the first and third bus operations However there are no essential differences between these command sequences The read reset state is the initial state of the flash memory When the power is turned on and when a command terminates normally the flash memory is set to the read reset state In the read reset state other commands wait for input In the read reset state data is read by regular read access As with the mask ROM program access from the CPU is enabled The Read Reset command is not required to read data by a regular read The Read Reset command is mainly used to initialize the automatic algorithm in such cases as when a command does not terminate normally 17 5 2 CHAPTER 17 FLASH MEMORY Writing Data This section describes the procedure for issuing the Write command to write data to the flash memory Figure 17 5 1 shows an example of the flash memory write proc
25. Even when the pin is used as an external interrupt input pin the pin state can be read directly from the port 0 data register PDRO 255 CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT 2 LEVEL 11 7 Program Example for External Interrupt Circuit 2 An example of programming external interrupt circuit 2 is given below m Program Example for External Interrupt Circuit 2 Processing specification The external interrupt circuit 2 detects an L level signal input to the POO INT20 AN4 pin and generates an interrupt Coding example DDRO EQU 0001H ADEN EQU 0034H EIE2 EQU 0036H EIF2 EQU 0037H Address of the port data direction register Address of the A D enable register Address of the external interrupt 2 control register Address of the external interrupt 2 flag register IF20 EQU EIF2 0 Definition of the external interrupt request flag bit ILR3 EQU 007DH Address of the interrupt level setting register INT_V DSEG ABS ORG OFFE6H IRQA DW WARI INT_V ENDS DATA SEGMENT Interrupt vector setting CSEG CODE SEGMENT Stack pointer SP is assumed to have been initialized o E e Disable interrupts CLRB IF20 MOV ILR2 211111110B Clear external interrupt request flag Set interrupt level to 2 MOV DDRO0 400000000B Set pin INT20 AN4 to serve inputs only MOV ADEN 00000000B Set pin INT20 ANA to enable external interrupt inputs MOV EIE2 400000001B Enable external interrupt inputs to pin INT2
26. H lower 8 bit comparison value Comparator data latch 2 higher 8 bit comparison value Load TDRO lower 8 bit setting value 88 344 TDR1 higher 8 bit setting value 134 124 Data setting 12344 TIFO o Clear by program Avalue can be set according to any timing When the counter is started or when a match is detected the data register setting value is loaded to the comparator data latch In this case the counter is cleared Note Confirm the validity of the values set in the counter operating in 16 bit mode 192 CHAPTER 8 8 16 BIT CAPTURE TIMER COUNTER 8 8 Functions of Operations of Capture Functions This section describes the capture function operation of the 8 16 bit capture timer counter m Capture Function Operation 8 bit mode To operate the capture function in the 8 bit mode the function must be set as shown in Figure 8 8 1 Figure 8 8 1 Setting of Capture Function in 8 bit Mode bit7 bit6 bit5 bit4 bit3 bit2 bit bito TCCR LSettingofavalue x other than 00 x x x L Setting of a value other x than 111 TIFO TFCRO TOIEN CINV TCS02 TCS01 TCS00 TSTRO L Setting of a value other than 111 qom poem qp X x TCPL Number of detected events Used bit x Unused bit Set 0 The 8 bit capture mode is allowed by the capture mode enable edge detectio
27. 4PC 393 APPENDIX B Overview of the Instructions Note At byte transfer operation to A the automatic transfer to T is represented by TL lt AL The operands in a multiple operand instruction are stored in the order in which they are indicated in MNEMONIC B Operation Instructions Table B 4 2 List of Operation Instructions 1 4 MNEMONIC ADDC A Ri ADDC A 48 ADDC A dir ADDC A IX off ADDC A EP Operation A A 8 A A A X 0ff C 4A EP C OP CODE ADDCW A ADDC A SUBC A Ri SUBC A d8 SUBC A dir 4A T C AL AL TL C A Ri C A d8 C A amp A dir C SUBC A IX off SUBC A SUBCW A SUBC A INC Ri A amp A IX off C A amp XA BP C A AL amp TL AL C Ri R 1 INCW EP INCW IX INCW A DEC Ri DECW EP 1 IX 1 1 1 Ri 0 1 lt 1 394 DECW IX DECW A MULU A DIVU A 1X 1 A amp XA 1 A HAL x TL A T AL MOD XT Table B 4 2 List of Operation Instructions 2 4 MNEMONIC Operation OP CODE d8 dir EP IX off TL AL T A A d8 A dir A EP DX off A Ri decimal adjust for addition dec
28. 86 Port 3 data register PDR3 The PDR3 register indicates the state of the pins For a pin set to function as an output port the same value 0 or 1 as held by the output latch can be read from this register If the pin is set to function as an input port however its output latch value cannot be read from the register Note When a bit manipulation instruction SETB CLRB is executed the output latch values not the value states of the pins are read thus output latch values excepting those for bits to be manipulated do not change Port 3 data direction register DDR3 The DDR3 register sets the I O direction of each pin per bit When a bit of the DDR3 corresponding to a pin of port 3 is set to 1 the pin functions as an output port When the bit is set to 0 the pin functions as an input port Note Because the DDR3 register is write only bit manipulation instructions SETB CLRB do not apply Setting a port pin to serve external interrupts If a pin of port 3 is used as an external interrupt input pin enable the external interrupt circuit operation and set the pin to function as an input port When the pin is set in this mode its output latch value has no significance Setting the output from a peripheral enable If a peripheral with an output pin is used set the output enable bit of the peripheral enable Because the output from the peripheral has priority the values set on the PDR3 a
29. 91 Registers of Port 5 95 Registers PDRO DDRO and PULO of Port 0 79 Registers PDR3 DDR3 PUL3 of Port 3 85 Registers PDR6 DDR6 PUL6 of Port 6 102 Registers PDR7 DDR7 and PUL7 of Port 7 108 Peripheral Function Interrupt Requests from Peripheral Functions ENG 34 Pin Pin Associated with the 12 bit PPG Timer 211 Pin Related to 8 bit PWM Timer 141 Pins Associated with External Interrupt Circuit 1 Mace x Lu cct EE LA I Ind 229 Pins Associated with External Interrupt Circuit 2 rH EIN 246 Pins of 8 16 bit Capture Timer Counter 168 Pins of 8 bit Serial I O esses 317 Pins Of Port Oo nd adieu de Seda dado a 78 Pins OF POT a cei redeo e ea ipee 84 Pins OF 90 PINS OFRON 94 Pins of Port 6 100 Pins OBbBOtt 7 dide pho atra ipn 107 Pins Related to the A D Converter 263 Pin Assignment Pin Assignment of DIP 32P MO0O96 8 Pin Assignment of FPT 34P MO3 9 Pin Function Pin Functions Description 12 Pin States Pin States in Each Operation Mode 402 Port Functions of W O Ports eese 76 T O Port Programming Exam
30. 9Perations R Read only Unused Undefined 45 CHAPTER 3 CPU Table 3 5 3 Explanation of Functions of Each Bit in the Reset Flag Register RSFR Bit name Description PONR Power on reset flag bit is set to this bit when power on reset occurs is set to this bit after power is turned on This bit is cleared with 0 after being read Writing a value to this bit has no significance ERST External reset flag bit is set to this bit when external reset occurs is set to this bit while other reset flags are maintained when all other reset flags have been set before the external reset flag is set This bit is cleared with 0 after being read Writing a value to this bit has no significance WDOG Watchdog reset flag bit is set to this bit when watchdog reset occurs is set to this bit while other reset flags are maintained when all other reset flags have been set before the watchdog reset flag is set This bit is cleared with 0 after being read Writing a value to this bit has no significance SFTR Software reset flag bit is set to this bit when software reset occurs is set to this bit while other reset flags are maintained when all other reset flags have been set before the software reset flag is set This bit is cleared with 0 after being read Writing a value to this bit has no significance Unused bits The values read out are undefined W
31. Count by counter Cycle period setting RCR23 24 SCLO to SCL11 H width setting RCR21 22 HSCO to HSC11 000u Cycle period 1 H width C2 lt gt PPG output pulse waveform Lm Eq o o 1 If internal count clock cycle period is 2 4 16 or 256 tinst cycle period compare value for cycle period multiplied by the count clock cycle period 2 If internal count clock cycle period is 2 4 16 or 256 tinst width compare value for the width multiplied by the count clock cycle period 220 9 6 CHAPTER 9 12 BIT PPG TIMER Notes on Using 12 bit PPG Timer This section provides notes on using the 12 bit PPG timer B Notes on Using 12 bit PPG Timer Output pin changeover The P37 BZ PPG pin shares functions of a general purpose port and a 12 bit PPG output Because its buzzer output BZ function precedes the 12 bit PPG output function if buzzer outputs are enabled it functions as the buzzer output BZ pin even if PPG outputs are enabled by the RCR23 RCEN bit To use it as the 12 bit PPG output PPG pin turn the buzzer outputs OFF Limitation of H width setting Using the H width setting bits of the 12 bit PPG control registers 1 and 2 RCR21 HSC5 to HSCO and RCR22 HSC11 to HSC6 set a value that falls within the range of 000000000001 to 111111111111g 001g to If 000g is set level outputs are delivered through PPG pin Furthermore set the value
32. EP HA Ri lt OP CODE A d8 A dir A IX off A ext A A A EP A Ri dir d8 IX off 48 EP d8 d8 A dir IX off ext lt A EP Ri dir 48 IX off 48 EP 48 MOV Ri d8 MOVW dir A MOVW IX off A MOVW ext A MOVW A Ri 48 dir AH dir 1 IX off AH IX off 1 ext HAH ext 1 EP EP 1 392 MOVW A MOVW A d16 EP A 416 MNEMONIC MOVW A dir A IX off A ext Table B 4 1 List of Transfer Instructions 2 2 Operation AH AL eXdir 1 AH x IX off AL X AH ext AL lt 1 OP CODE A QA A EP A EP EP 416 IX A X A AL A 1 AH x EP AL EP 1 EP 416 IX AA MOVW MOVW SP A MOVW A SP MOV A T MOVW A T A X SP SP CCA XT A 4TH A 1 MOVW 16 MOVW 5 MOVW 5 MOVW SP 416 SWAP IX 416 A XPS PS A SP 416 AL SETB dir b CLRB dir b XCH A T XCHW A T XCHW A EP dir b 1 dir b 0 AL XTL T A XEP XCHW A IX XCHW A SP MOVW A PC XIX lt
33. Output Serial data output allowance bit 0 P31 UO SO is used as a general purpose port P31 P31 UO SO is used as a serial data output pin Shift clock output allowance bit P30 UCK SCK is used as a general purpose port P30 or the shift clock input pin SCK P30 UCK SCK is used as the shift clock output pin Interrupt request allowance bit Interrupt request output is prohibited Interrupt request output is allowed Interrupt request flag bit At write E has This bit is cleared 1 Serial transfer has already Remains unchanged This bit does not terminated affect other bits R W Readable and Writable 55 Initial value 320 CHAPTER 14 8 BIT SERIAL I O Table 14 4 1 Explanation of Functions of Each Bit in Serial Mode Register SMR 1 2 Bit name Function SIOF Interrupt request flag bit When 8 bit serial data is input or output during serial I O operation this bit is set to 1 When this bit and the interrupt request allowance bit SIOB are 1 an interrupt request is output Setting this bit to 0 clears it while setting it to 1 does not affect this bit or implement any changes SIOE Interrupt request allowance bit This bit is used to allow and prohibit interrupt request output to the CPU When this bit and the interrupt request allowance bit SIOF are 1 an interrupt request is output SCKE Shift clock output a
34. R W Readable Writable 1 Unused 25 Initial value 235 CHAPTER 10 EXTERNAL INTERRUPT CIRCUIT 1 EDGE Table 10 4 2 Explanation of Functions of Each Bit in External Interrupt Control Register 2 EIC2 Bit name Function Bit value is undefined when being read Unused bits Written value does not affect other operations When a signal with an edge or edges corresponding to edge polarity selected by edge polarity selection bits 2 SL21 SL20 is input to the EIR2 INT12 external interrupt pin this bit is set to 1 External interrupt When this bit and interrupt request enable bit 2 EIE2 are 1 the request flag bit 2 interrupt request is output Writing 0 clears this bit and writing 1 does not affect this bit no change These bits are used to select the polarity of an edge or edges of a signal pulse that triggers an interrupt when the signal is input to the INT12 external interrupt pin When these bits provide a value of 005 edge detection is not SL21 SL20 Edge polarity selection bits 2 performed and interrupt requests are not generated These bits may specify 015g indicating a rising edge 10g a falling edge or 11g both edges to be detected Note If edge is selected while edge detection is OFF edge detection may be performed unconditionally Always clear EIR2 bit after selecting an edge This bit enables or disables interrupt request outputs to the CPU When this b
35. RW RW RW RW RW RW R W Serial data output enable bit Clock output enable bit General purpose port or clock input pin for UART 8 bit serial I O UART clock output pin Synchronization mode selection bit Synchronous transfer mode Asynchronous transfer mode Operating mode selection bits Operating Data written With i With parit mode PEN Oy PEN 1 0 0 7 bits 6 bits 1 a 78s 1 0 2 8 1 bits 1 3 9 bits 8 bits Stop bit length selection bit Parity enable bit Parity disabled Parity enabled TD8 TP in the SSD register allows choice of even odd R W Readable Writable Unused Initial value 290 CHAPTER 13 UART Table 13 4 1 Explanation of Functions of Each Bit in the Serial Mode Control Register SMC Bit name Description PEN Parity enable bit This bit selects whether the parity bit is to be added at transmission and detected at reception when serial data is input output SBL Stop bit length selection bit This bit selects the stop bit length for data to be transmitted Note When data is received only the first bit of stop bits is detected and the second and later bits are ignored MCI Operating mode selection bits These bits specify operating mode data length There are 7 types of data length selectable in combination with a parity bit SMDE Synchronization mode selection bit
36. 110 4 7 2 CHAPTER 4 I O PORTS Operations of Port 7 Functions This section describes the operation of port 7 B Operation of Port 7 Operation in output port mode When 1 is written for a bit of the DDR7 register the bit corresponding to a pin of port 7 the pin functions as an output port In output port mode the output transistor operation is enabled and the output latch data is output to the pin Once data has been written into the PDR7 register the written data is held in the output latch and output to the pin as it is The value state of the pin can be read by reading the PDR7 register Operation in input port mode When 0 is written for a bit of the DDR7 register the bit corresponding to a pin of port 7 the pin functions as an input port In input port mode the output transistor is OFF and the pin status is Hi Z Once data has been written into the PDR7 register the written data is held in the output latch but is not output to the pin The value state of the pin can be read by reading the PDR7 register Operation when a reset is performed When the CPU is reset the bits of the DDR7 register are initialized to 0 Thus all output transistors become OFF and the pins become Hi Z However CPU resets do not initialize the PDR7 register If a pin is used as an output port after the reset reinitialize the PDR7 register to contain new output data in the bit position corresponding to the
37. 130 Wild Register Block Diagram of the Wild Register Function EET 349 Operation Order of the Wild Register Function EET HE ERE VETE 356 Registers Related to the Wild Register Function 350 Wild Register Addresses List 356 Wild Register Applicable Addresses 348 Wild Register Function eese 348 WRARH Higher Address Set Register WRARH 352 INDEX WRARL Lower Address Set Register WRARL 353 WRDR Data Setting Register WRDR 351 WREN Address Comparison EN Register WREN 354 Write Automatic Write Erase 364 365 366 Detailed Explanation of Flash Memory Write Erase NE E 367 bu 363 Writing Notes on Writing Data 369 Wnting Data eet 369 Writing to the Flash 369 Writing to Erasing Flash Memory 358 Writing Data Witing Data iis eiie terere trit 369 417 INDEX 418 CM25 10153 2E FUJITSU SEMICONDUCTOR CONTROLLER MANUAL F MC 8L 8 BIT MICROCONTROLLER MB89202 F202RA Series HARDWARE MANUAL February 2008 the second edition Published FUJITSU LIMITED Electronic Devices Edited Strategic Business Development Dept
38. R6 RO 32 banks on the RAM area R7 For details on the general purpose register area on each model see Section 3 1 1 Specific purpose Areas 32 CHAPTER 3 CPU Features of the General purpose Registers The general purpose registers have the following features e High speed access with short instructions general purpose register addressing Register banks in blocks that allow data to be easily conserved and partitioned in the unit of function The general purpose registers allow specific register banks to be statically assigned with the interrupt processing routine or vector call CALLV 0 to 7 processing routine For example it can be used such that the fourth register bank is always used for the second interrupt For interrupts unless data in a specific register bank that corresponds to an interrupt processing is incorrectly overwritten by another routine simply specifying the specific register bank at the beginning of the interrupt processing routine stores the data contained in the general purpose registers before interruption This feature allows data in general purpose registers to avoid being put in the stack and allows interrupts to be handled efficiently at high speed For subroutine calls in addition to conservation of data in general purpose registers the register banks can implement re entrant programs reloadable programs with variable addresses unfixed that are usually created using the index reg
39. Set non parity the number of stop bits 1 and operating 311 CHAPTER 13 UART 312 mode 1 Set asynchronous mode enable clock output and serial data output MOV SRC 00011101B Select the dedicated baud rate generator and set the baud rate 375 bps Disable the transmission interrupt request and enable the MOV SSD 00001000B reception interrupt request MOV A SSD Required before transmission TDRE 1 enables transmission Clear error flags Write the data to be transmitted 13 MOV A SIDR MOV SODR 13H SETI Enable instruction Interrupt processing routine PUSHW A Save A and T XCHW PUSHW A MOV A SSD Read the data to be transmitted then clears the input data flag MOV A SIDR User defined process POPW A Restore A and T XCHW POPW A RETI ENDS END CHAPTER 14 8 BIT SERIAL I O This chapter describes the functions and operation of the 8 bit serial I O 14 1 Overview of 8 Bit Serial I O 14 2 Configuration of 8 Bit Serial I O 14 3 Pins of 8 Bit Serial I O 14 4 Registers of 8 Bit Serial I O 14 5 Interrupt of 8 Bit Serial I O 14 6 Operations of Serial Output Functions 14 7 Operations of Serial Input Functions 14 8 8 Bit Serial I O Operation in Each Mode 14 9 Notes on Using 8 Bit Serial I O 14 10 Example of 8 Bit Serial I O Connection 14 11 Program Example for 8 Bit Serial I O 313 CHAPTER 14 8 BIT SERIAL I
40. TDRE Transmission interrupt Sent to the transmission shift register Sent to the transmission shift register Data transmitted 7 STOP START 306 CHAPTER 13 UART 13 6 2 Reception Operations Operating Mode 0 1 or 3 When data is received at the serial data input pin the internal reception shift register converts it from serial to parallel If the data is correctly transmitted up to the stop bit s data in the internal shift register is transferred to the SIDR register then 1 is set to the RDRF bit m Reception Operations Operating Mode 0 1 or 3 If an overrun error or framing error occurs the received data is not transmitted to the SIDR register but the ORFE bit is set to 1 Either of the RDRF bit and ORFE bit goes on when the final stop bit is detected after data is fully received If the reception interrupt is enabled SSD RIE 1 an interrupt request to the CPU IRQ6 is generated When the RDRF bit goes on the received data has been transmitted to the SIDR register In operating mode 2 when the bit is 1 bit or bit is 1 and reception interrupt pin is 1 the mode 2 UART reception interrupt request is output to the CPU Note In operating mode 1 the parity bit is read as data in the 7th bit Set up the program so that the 7th bit is not read Figure 13 6 4 Figure 13 6 5 and Figure 13 6 6 show the reception operations when parity is not used and
41. Table A 1 I O Map 4 4 Register abbreviation Register name Read write Initial value Vacancy Port 0 pull up set register 00000000 Port 3 pull up set register 00000000 Port 5 pull up set register Prohibited area Flash memory control status register Prohibited area Interrupt level set register 1 11111111 Interrupt level set register 2 11111111 Interrupt level set register 3 11111111 Interrupt level set register 4 11111111 Interrupt test register Inhibited Explanation on read write R W Readable and Writable R Read only W Write only Explanation on initial value 0 The initial value of this bit is 0 1 The initial value of this bit is 1 X The initial value of this bit is undefined No used in MB89F202 F202RA Note Do not use the prohibited areas 379 APPENDIX B Overview of the Instructions APPENDIX B Overview of the Instructions This section describes the instructions used for the F2MC 8L Overview of the Instructions of the F2MC 8L The F MC 8L has 140 kinds of 1 byte machine instructions actually the map is 256 bytes An instruction and succeeding operands make an instruction code Figure B 1 shows the correspondence between the instruction codes and instruction map Figure B 1 Correspondence between Instruction Codes and Instruction Map 0 to 2 bytes are provided depending on the i
42. eiie eere 121 Interrupts while Interval Timer Functions are Enabled tease 147 Interval Timer Function 116 162 Interval Timer Function Operation 185 Interval Timer Functions Functions to Output the Square Wave 136 Operations of Interval Timer Function Time base Timer 122 Operations of the Interval Timer Functions 148 Program Example of Interval Timer Function HU 200 Program Example of Interval Timer Functions ER 157 410 L Level Detection Functions of External Interrupt Circuit 2 Level 244 Lower Address Set Register Lower Address Set Register WRARL 353 M Mask Mask Options 400 MB89202 F202RA Block Diagram of MB89202 F202RA Series 7 Features of MB89202 F202RA Series 2 MB89202 F202RA Series Models 4 Memory Access Operations for Selecting Memory Access Mode 72 Memory tte 23 Memory Space Configuration of Memory 22 Mode Cancellation of Standby Mode by an Interrupt 70 Diagram for State Transition in Standby Mode 68 Mode 72 Mode Fetch iuter ine ete inb Di settin
43. external interrupt input 20 ETE purpose I O analog input 4 PO1 general external interrupt input 21 POI INT21 AN5 purpose I O analog input 5 Analog CMOS P02 general external interrupt input 22 hysteresis purpose I O analog input 6 P03 general external interrupt input 23 purpose I O analog input 7 PO3 INT23 AN7 P04 general PO4 INT24 purpose I O external interrupt input 24 POS INT25 POS general external interrupt input 25 purpose I O CMOS P06 general hysteresis P06 INT26 purpose I O external interrupt input 26 P07 general P07 INT27 purpose I O external interrupt input 27 For circuit type see Section 1 7 Pin Functions Description and 1 8 I O Circuit Types For pin operation when used as analog input see CHAPTER 12 A D CONVERTER 78 CHAPTER 4 I O PORTS m Block Diagram of Port 0 Figure 4 2 1 Block Diagram of Port 0 A D converter A D converter channel select enable bit i43 A D input occurring iconverter s lt analog input From external interrupt enable External interrupt LL Stop mode 41 SPL 1 External ia No A D input PDR read o gt a S s o c o 2 Pull up PDR read 1 when read modify write is resistor performed PDR write DDR write Sto
44. to clear Interrupt level bits IL1 and ILO These bits indicate the level of an interrupt the CPU is accepting then it is compared with the values in the interrupt level setting registers ILRI to 4 which is specified as the level of interrupt requests of peripheral functions IRQO to IRQF When the interrupt enable flag is turned on I 1 and if an interrupt is requested with an interrupt level value lower than that of these bits the CPU accepts the interrupt Table 3 2 1 provides interrupt level intensities The initial value of the interrupt level specified after the reset operation is 115 Table 3 2 1 Interrupt Levels Interrupt level Intensity Low no interrupts allowed Note When the CPU is not handling an interrupt handling the main program the interrupt level bits IL1 and ILO are normally set to 115 For details on interrupts see Section 3 4 Interrupts 30 CHAPTER 3 CPU 3 2 2 Register Bank Pointer RP The register bank pointer RP is the upper 8 bits of the program status register PS The register bank pointer indicates the general purpose register bank address being used and the address is converted to the actual address in general purpose register addressing m Configuration of the Register Bank Pointer RP Figure 3 2 4 shows the configuration of the register bank pointer Figure 3 2 4 Configuration of Register Bank Pointer bitiS biti4 bitl3 biti2
45. 0 Disables data to be written into erased from flash memory 1 Enables data to be written into erased from flash memory RDYINT Flash memory operation state indication bit 0 Data is being written erased 1 Data writing erasing has been completed An interrupt request is generated gt INTE Causing an interrupt to the CPU to be generated bit tnst Instruction cycle 0 Enables an interrupt when data writing erasing is completed Readable Writable 1 Disables an interrupt when data writing erasing is completed Read only Initial value 359 CHAPTER 17 FLASH MEMORY Table 17 2 1 Explanation of Functions of Each Bit in the Flash Memory Control Status Register FMCS Bit name Description INTE Causing an interrupt to the CPU to be generated bit Bit causing an interrupt IRQB to the CPU to be generated when writing into or erasing from flash memory is completed An interrupt IRQB to the CPU is generated when both the INTE bit and RDYINT bit are 1 If the INTE bit is O no interrupt is generated RDYINT Flash memory operation state indication bit Bit for indicating operation status of flash memory This bit is set to 1 when writing into or erasing from flash memory is completed After data has been written into or erased from flash memory and this bit has been set to 1 subsequent data can be written into or erased from flash memory Writing 0 clears this bit with 0 while if 1 is written
46. 1 however the interrupt request occurs immediately 8 bit Serial I O Interrupt Register and Vector Table Table 14 5 1 8 bit Serial I O Interrupt Register and Vector Table Interrupt level setting register Vector table address Interrupt name Register Setting bit IRQC 007Eg LCO bit0 FFE2q FFE3g For interrupt operation see Section 3 4 2 Steps in the Interrupt Operation 324 CHAPTER 14 8 BIT SERIAL I O 14 6 Operations of Serial Output Functions In the 8 bit serial I O 8 bit serial output operation synchronized with a shift clock is possible B Serial Output Operation Serial output operation is divided into serial output operation using an internal shift clock and serial output operation by using the external shift clock When serial I O operation is allowed serial data is input in the SDR and at the same time the contents of the SDR are output to the serial data output pin SO Serial output operation via internal shift clock Serial output operation using the internal shift clock requires the settings shown in Figure 14 6 1 Figure 14 6 1 Settings Required for Serial Output Operation using Internal Shift Clock bi7 bite bib bit bito SMR SIOF SIOE CKS1 CKSO 9 1 1 VLL 1 Other than 11 9 SDR Transmission data setting SSEL SSEL 1 Used bit 1 Set When serial output operation is started the contents of the SDR
47. 1 the counter is incremented at the rising edge These bits are used to select the count clocks to be supplied to the counter Select one clock from the seven internal clocks and one external clock TCS02 TCS01 TCS00 When these bits are 111p the external clock is input In this case timer 0 can Clock source selection operate as the counter function bits Note When external clock input is selected TCS02 TCS01 TCS00 1115 the P33 EC pin must be set in the input port This bit is used to start and stop the counter When this bit is set to 1 the counter is cleared and incremented according to TSTRO the selected count clock When this bit is set to 0 the counter stops its Timer start bit operation When the timer is started TSTRO 0 21 in the 16 bit mode the counters of both timer 0 and timer 1 are cleared Note When using only timer 0 of the 8 16 bit capture timer counter in the 8 bit mode set a value other than 111g in the count clock selection bits TCS12 TCS11 TCS10 of the timer 1 control register TCR1 Using timer 0 with setting value TCS12 TCS11 TCS10 111g results in a malfunction 174 CHAPTER 8 8 16 BIT CAPTURE TIMER COUNTER 8 4 3 Timer 1 Control Register TCR1 The timer 1 control register TCR1 is used to select functions allow and prohibit operation control interrupts and check interrupt states in timer 1 for the 8 bit mode of the 8 16 bit capture timer counter When
48. COMR 145 PWM Control Register CNTR 143 413 INDEX 414 Register and Vector Table Related to 8 16 bit Capture Timer Counter of Interrupts 184 Register and Vector Table Related to Interrupts from Time base 121 Register and Vector Table Related to the Interrupt of the A D 272 Register and Vector Table Related to the Interrupts of an 8 bit PWM 147 Register Associated with Interrupt Generation by External Interrupt Circuit 1 and Vector Table Register Associated with Interrupt Generation by External Interrupt Circuit 2 and Vector 213 Registers Associated with External Interrupt Circuit 1 EE 231 Registers Associated with External Interrupt Circuit 2 Be tese a tasse de Mese 249 Registers of 8 16 bit Capture Timer Counter EE 170 Registers of 8 bit Serial I O 319 Registers of Port 91 Registers of Port 5 95 Registers PDRO DDRO and PULO of Port 0 79 Registers PDR3 DDR3 and PUL3 of Port 3 85 Registers PDR6 DDR6 PUL6 of Port 6 102 Registers PDR7 DDR7 and PUL7 of Port 7 108 Registers Related to the 8 bit PWM Timer 142 Registers Related to the A D Converter 265 Register
49. Figure 7 9 1 Error until the Count Operation is Started Counter value 3s Count clock Error Cycle of 00H Activating the counter Notes on setting by a program While interval timer functions or PWM timer functions are enabled CNTR 1 do not change the count clock cycle CNTR P1 PO If the user wants to switch between the interval timer function and the PWM timer function CNTR P TX proceed when the counter is stopped CNTR 0 interrupts are disabled CNTR TIE 0 and interrupt requests are cleared CNTR TIR 0 When the interrupt request flag bit CNTR TIR is 1 and the bit to enable an interrupt request is enabled CNTR TIE 1 recovery from interrupt handling is no longer possible The TIR bit must be cleared When the counter value matches the COMR register value concurrently with the counter stop CNTR TPE 0 the TIR bit is not set Depending on how to set TPE P TX and OE the PWM output waveform varies as shown below Be careful when using a program to set TPE P TX and OE 1 When TPE P TX and OE are set at the same time 155 CHAPTER 7 8 BIT PWM TIMER MOV CNTR 11001010B Starts PWM operations internal clocks and count operations Enables the PWM output 1 4 instruction cycle Depending on the port T state x Executing the instruction to enable PWM output 2 When OE is set after TPE and P TX are set MOV CNTR 11001000B St
50. In the read operation in the timer counter mode counter values are read m Capture Data Registers H and L TCPH and TCPL The number of events detected in the capture mode is stored in TCPH and TCPL Data cannot be written to these registers because the registers are read only Figure 8 4 8 shows the bit structures of capture data registers H and L Figure 8 4 8 Bit Structures of Capture Data Registers H and L TCPH and TCPL Address bit7 bits bit4 bit3 bit2 biti bito Initial value TeH owe T T T T R R R R R R R R Tope T 1 T T beoe R R R R R R R R R Read only X Undefined 182 8 5 CHAPTER 8 8 16 BIT CAPTURE TIMER COUNTER 8 16 bit Capture Timer Counter of Interrupts The 8 16 bit capture timer counter generates an interrupt if the values set in a data register match those set in the counter when the interval timer or counter is operating The interrupt level is IRQ3 when generated by the 8 16 bit capture timer counter When the capture is in operation and a capture edge is detected IRQ4 is generated m 8 16 bit Capture Timer Counter of Interrupts Table 8 5 1 shows the interrupt request flag bit interrupt flag clear bit interrupt request enable bit and the cause of the 8 16 bit capture timer counter interruption Table 8 5 1 Interrupt Control Bits and the Cause of the 8 16 bit Capture Timer Counter Interrupt 8 bit mode 16 bit mode Capture mode Timer 0 Timer
51. L level input to the external interrupt pin continues as it is even if the IF20 bit is cleared with external interrupt inputs to the pin remaining enabled the IF20 bit is immediately set to 1 again Disable external interrupt inputs to the pin or remove the cause of the external interrupt as required Notes When enabling interrupts to the CPU following a release from the reset state clear the IF20 bit in advance L level inputs to external interrupt pins INT20 to INT27 trigger external interrupt circuit 2 to generate the same interrupt request IRQA Thus when an external interrupt input is detected it is necessary to identify the pin at which the input occurs by reading the port 0 data register PDRO before the input changes to H level Only external interrupt circuits 1 and 2 can execute a release from the stop mode by an interrupt Register Associated with Interrupt Generation by External Interrupt Circuit 2 and Vector Table Table 11 5 1 Register Associated with Interrupt Generation by External Interrupt Circuit 2 and Vector Table Interrupt level setting register Vector table address Interrupt designation Register Bit for setting level IRQA ILR3 007Dp LAI bit5 LAO bit4 FFE74 For interrupt operation see Section 3 4 2 Steps in the Interrupt Operation 253 CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT 2 LEVEL 11 6 Operations of External Interrupt Circuit 2 External interrupt circuit 2 de
52. Registers PDR6 DDR6 and PUL6 of Port 6 ETT 102 Structure of Port 6 sss 100 Port 7 Block Diagram of Port 7 108 Functions of Port 7 Registers 109 Operation of Port 7 111 Pins of Port Reine ea dra 107 Registers PDR7 DDR7 and PUL7 of Port 7 108 otr cture of Port ts 107 PPG Timer Block Diagram of Circuitry Terminating at the Pin Associated with the 12 bit PPG Timer neds 212 Precautions Precautions on Handling Devices 18 Precautions when Selecting a Model 6 Program Access Program Access to Flash Memory 373 Program Example Program Example for 12 bit PPG Timer 223 Program Example for 8 bit Serial Input 337 Program Example for 8 bit Serial Output 336 Program Example for Buzzer Output 345 Program Example for External Interrupt Circuit 2 EYE 256 Program Example for 311 Program Example of Counter Function 202 Program Example of Interval Timer Function 200 Program Example of Interval Timer Functions EET 157 Program Example of PWM Timer Functions 159 Program Example of A D Conversion Functions 277 Programming EPROM Programming EPROM with Evaluation Chip Programming Exam
53. Time base timer overflow end of oscillation stabilization wait time 11 External reset input oa c 68 CHAPTER 3 CPU Transition to and cancellation of clock mode non standby mode Table 3 7 3 Transition to and Cancellation of Clock Mode State transition Transition conditions Transition to active mode after power on reset 9 End of oscillation stabilization wait time output of time base timer 1 Cancellation of reset input Reset in RUN mode 2 External reset software reset or watchdog reset Transition to and cancellation of standby mode Table 3 7 4 Transition to and Cancellation of Standby Mode State transition Transition conditions Transition to sleep mode 3 STBC SLP 1 Cancellation of sleep mode 6 Interrupt each type 4 External reset Transition to stop mode 5 STBC STP 1 Cancellation of stop mode Note 7 External interrupt 8 End of oscillation stabilization wait time output of the time base timer 10 External reset 11 External reset during oscillation stabilization wait In standby mode the CPU and watchdog timer stop Thus software and watchdog resets do not occur 69 CHAPTER 3 CPU 3 7 6 Notes on Standby Mode Even if the standby control register STBC sets standby mode transition to standby mode is not allowed when a peripheral function generates an interrupt request When an interrupt causes a return f
54. Timer 0 Data Register 178 Timer 1 Control Register Timer 1 Control Register TCR1 175 Timer 1 Data Register Timer 1 Data Register TDR1 180 Timer Output Control Register Timer Output Control Register TCR2 177 Instruction Cycle 57 Transfer Transfer Instructions seeeeeneee 392 Transfer Clock Rate Choice of the Transfer Clock Rate 281 Transferred Data Format Transferred Data Format sese 304 Transition Diagram for State Transition in Standby Mode SN costs nete cepe se dag 68 416 Transition to Standby Mode and Interrupt 70 Transmission Transmission Interrupt eeeeeeeeeeees 303 Transmission Operations Transmission Operations in Operating Mode is Nodo oT 306 U UART Block Diagram of the UART relating Pins 288 Block Diagram of 284 Functions of 280 Program Example for 311 UART Relating Pins 0 0 0 287 UART relating Registers 289 UART Interrupt Related Registers UART Interrupt Related Registers and Vector Table AdGdtesses 303 UART relating Registers UART relating Registers
55. clock speed switching gears and setting in standby mode sleep stop To peripheral functions a divided frequency output of the free run counter operating with the clock for peripheral circuits is provided However the divided frequency output of the time base timer operating with 1 2 frequency of the oscillation frequency is not affected by the gear Figure 3 6 1 shows the clock supply map 51 CHAPTER 3 CPU Figure 3 6 1 Clock Supply Map Oscillation circuit 3 Fou 1 2 frequency Stop mode Clock controller 1 4 frequency E 1 8 frequency O 1 16 H O 1 64 frequency Q Sleep stop oscillation stabilization wait Oscillation control Supplied to CPU Ttinst Supplied to peripheral circuits Ttinst 2 Free run counter Oscillation frequency Instruction cycle Not affected by the gear 1 Watchdog timer 8 16 bit capture timer counter 18 bit PWM timer 4 Continuous conversion ontinuous conversion Conversion comparison UART prescaler 12 bit PPG 2 External interrupt 1 2 External interrupt 2 1 Oscillation stabilization wait time 3 8 PWM pin 8 A D converter 00 50 pin UI SI pin PPG pin INT1 pin INT2 pin The gear affects the operating speed or other settings The time base timer stops when the oscillation frequency clock halts Output of the time base timer is selectable when the A D converte
56. eri 230 Block Diagram of Circuitry Terminating at the Pins Associated with External Interrupt Circuit 2 Lo edt edith annee eunte epa 247 Block Diagram of Clock Controller 54 Block Diagram of External Interrupt Circuit 1 DEM TE 227 Block Diagram of External Interrupt Circuit 2 245 Block Diagram of External Reset Pin 47 Block Diagram of MB89202 F202RA Series 7 Block Diagram of Port 0 79 Block Diagram of Port 3 85 Block Diagram of Port 4 91 Block Diagram of Port 5 95 Block Diagram of Port 6 101 Block Diagram of Port 7 108 Block Diagram of the A D Converter 261 Block Diagram of the Buzzer Output 341 Block Diagram of the Pin Related to the 8 bit PWM hing E 141 Block Diagram of the Pin Related to the Buzzer npn 342 Block Diagram of the Pins Related to the A D CODVEI c 264 Block Diagram of the UART relating Pins TTE 288 405 INDEX Block Diagram of the Wild Register Function ordi 349 Block Diagram of Time base Timer 118 Block Diagram of UART 284 Block Diagram of Watchdog Timer
57. instruction 00 indicates that it becomes 00 TL TH AH Indicates whether the instruction changes the corresponding flags If is shown in this column the instruction changes the corresponding flags N Z V C Indicates the instruction code If the appropriate instruction occupies multiple codes they are listed under the following rule Example 48 to 4F means the serial numbers from 48 to 4F OP CODE 382 B 1 Addressing For the F2MC 8L the following 10 kinds of addressing modes are supported e Direct addressing e Extended addressing e Bit direct addressing Index addressing Pointer addressing e General purpose register addressing Immediate addressing e Vector addressing e Relative addressing Inherent addressing m Explanation on Addressing Direct addressing The addressing which is indicated by dir in the instructions list is used for accessing the area from 00004 to O0FFg In this addressing the higher one byte of the address is 005 Specify the lower one byte with the operand Figure B 1 1 shows an example Figure B 1 1 Example of Direct Addressing MOV 12H A 001 2H ss a aaa Extended Addressing The addressing which is indicated by ext in the instructions list is used for accessing the entire area of 64 KB In this addressing specify the higher one byte of the address with the first operand and the lower one byte with the second operand Fig
58. interrupt pin can be read directly from the port data register PDR3 When signal with an edge or edges corresponding to edge polarity selected by edge polarity selection bits SLO1 SLOO is input to INT10 external interrupt pin this bit is set to 1 When this bit and interrupt request enable bit 0 EIEO are 1 the interrupt request is output Writing 0 clears this bit and writing 1 does not affect this bit 5101 SLOO Edge polarity selection bits 0 These bits are used to select the polarity of an edge or edges of a signal pulse that triggers an interrupt when the signal is input to the INT10 external interrupt pin When these bits provide a value of 005 edge detection is not performed and interrupt requests are not generated These bits may specify 01g indicating a rising edge 10g a falling edge or 11g both edges to be detected Note If edge is selected when edge detection is OFF edge detection may be performed unconditionally Always clear the EIRO bit after selecting an edge 233 CHAPTER 10 EXTERNAL INTERRUPT CIRCUIT 1 EDGE Table 10 4 1 Explanation of Functions of Each Bit in External Interrupt Control Register 1 EIC1 2 2 Bit name Function This bit enables or disables interrupt request outputs to the CPU When this bit and external interrupt request flag bit 0 EIRO are 1 the interrupt request is output Notes EIE0 When using the external interrupt pin write 0 for
59. nigro eT T AE E TT 34 3 4 1 Interrupt Level Setting Registers ILR1 to ILR4 36 3 4 2 Steps in the Interrupt Operation nennen neret nnns nnne nens 37 3 4 3 MUItIDIG guo 39 3 4 4 Interrupt Processing Time nen nene 40 3 4 5 Stack Operation at Interrupt Processing ssssssssssseeeeeeneen nennen nnns 41 3 4 6 Stack Area for Interrupt Processing 2 ener nnne nens 42 3 5 pe 43 3 5 1 Reset Flag Register RSFR ssssssssssssessesesenene nennen nnne entes 45 3 5 2 External Reset Pin eee deed de ben Le etes pee dade ace Enea EE Eden eo Eee Pe T ds 47 3 5 3 REM 48 3 5 4 State of Each Reset eene devel ie dee ae a de ted 50 3 6 ih atre Det EDU Ae cedet ers 51 3 6 1 Clock Generatore s oc heb dot otc tnt tL Piu dec eite 53 3 6 2 Glock Gontroller siet tta 54 3 6 3 System Clock Control Register SYCO sss nennen nennen nens 56 3 6 4 Glock Moda oan ater feb eet Hp utt ect 58 3 6 5 Oscillation Stabilization Wait Time 60 3 7 Standby Mode Low Power Consum
60. pin and then set the corresponding bit of the DDR7 register so that the pin will function as an output port Operation in stop mode When the pin state setting bit of the standby control register STBC SPL is 1 and when the stop mode is entered the output transistor is turned OFF and the pin becomes Hi Z because the output transistor is forcibly turned OFF without respect to the value existing on the DDR7 register in the bit position corresponding to the pin Input remains fixed to prevent leaks by input open 111 CHAPTER 4 I O PORTS Table 4 7 4 summarizes the operating modes of the pins of port 7 Table 4 7 4 Operating Modes of Pins of Port 7 Pinname Normal operation sleep stop SPL 0 Stop SPL 1 Note When the pull up resistor is selected by using the pull up setting register the pin state will be H level instead of Hi Z in stop mode SPL 1 During a reset however the pull up is invalid with the pin remaining at Hi Z 112 CHAPTER 4 I O PORTS 4 8 Programming Example of I O Port This section provides an example of programming with I O ports m I O Port Programming Example Processing specification Ports 0 and 3 are used to light all seven segments of LED eight segments if the decimal point is included Pin POO is connected to the anode common pin of LED and pins P30 to P37 are connected to the pins of the segments Figure 4 8 1 provides an example of the pins and the 8 s
61. serve outputs from peripherals and external interrupt inputs SPL Pin state setting bit of standby control register STBC SPL Hi Z High impedance Note Hi Z External interrupt input At a reset When the pull up resistor is selected by using the pull up setting register the pin state will be H level instead of Hi Z in stop mode SPL 1 During a reset however the pull up is invalid with the pin remaining at Hi Z 89 CHAPTER 4 I O PORTS 4 4 Port 4 Port 4 is a type of I O port that is switched between CMOS push pull and N ch open drain and may also serve analog inputs Each pin of this port can be used for peripherals or normal port function that can be selected according to the setting of the bit corresponding to the pin on a specific register This section explains the I O port function of CMOS push pull N ch open drain type This section also describes port 4 concerning to the structure pins a block diagram of pins and associated registers m Structure of Port 4 Port 4 comprises the following four elements Port 4 has four I O pins of CMOS push pull N ch open drain Type of I O pins that are switched between CMOS push pull and N ch open drain and analog input pins PA40 ANO to P43 AN3 Port 4 data register PDR4 Port 4 data direction register DDR4 Port 4 output format setting register OUT4 B Pins of Port 4 These pins can also be used as analog input pins Those pins
62. the SODR register is transferred to the internal transmission shift register When next data becomes writable the bit is set to 1 then an interrupt request to the CPU IRQ5 is generated if the transmission interrupt is enabled SSD TIE 1 m Reception Interrupt When operating mode is 0 1 or 3 When data is correctly input up to the stop bit the RDRF bit is set to 1 If an overrun error or framing error occurs the ORFE bit is set to 1 These bits are set when a stop bit is detected If the reception interrupt is enabled SSD RIE 1 an interrupt request to the CPU IRQO is generated When operating mode is 2 For both RDRF and ORFE data is received or transmitted with the final data bit D8 set to 1 these flags go on when the stop bit at the end is detected However when the framing error occurs the flag goes on regardless of the final data bit An interrupt request to the CPU is generated when the flag goes on and the input data becomes 1 m UART Interrupt Related Registers and Vector Table Addresses Table 13 5 1 provides the registers relating to the UART interrupts and vector table addresses For details of the interrupt operation see Section 3 4 2 Steps in the Interrupt Operation Table 13 5 1 UART Interrupt Related Registers and Vector Table Addresses Interrupt level setting register Vector table address Interrupt name Register Upper digits Lower digits ILR2 007Cy L51 bit3 L
63. 1 2 or 3 Figure 13 6 2 Operating Mode 0 1 2 or 3 bit7 bit6 bit5 bit4 bit3 bit2 bit Pen SBL mci mco SMDE SCKE soe 0 cr csi cso nc2 nct ROO RDRF ORFE TORE RIE _ TDe TP RDB RP Stores received data Writes data to be transmitted 0 Used bit Set 0 For MC1 and MCO set 00g in mode 0 01g in mode 1 10g in mode 2 and 118 in mode 3 305 CHAPTER 13 UART 13 6 1 Transmission Operations Operating Mode 0 1 2 and 3 When writing data to be transmitted into the SODR register after reading the SSD register sends the data written into the SODR register to the transmission shift register parallel serial conversion then starts The data converted is output at the serial data output pin from the lowest bit in sequence with LSB first When the next data becomes writable 1 is set to the TDRE bit then an interrupt request to the CPU is generated if the transmission interrupt is allowed SSD TIE 1 B Transmission Operations in Operating Mode is 0 1 2 or 3 Figure 13 6 3 shows the transmission operations when operating mode is 1 parity is not used and the number of stop bits is 1 Figure 13 6 3 Transmission Operations in Operating Mode 0 1 2 or 3 SSD read SODR write interrupt processing routine Transmission buffer full
64. 1 EIC1 Figure 10 4 2 External Interrupt Control Register 1 EIC1 Address bit7 bit6 bits bit3 bit2 biti Initial value 00244 EIR1 SL11 5110 EIE1 EIRO SLO1 SLOO EIEO 00000000 RW R W RW RW RW RW RW RW Interrupt request enable bit 0 Disables interrupt request outputs Enables interrupt request outputs Edge polarity selection bits 0 EUN Edge detection OFF Rising edge Falling edge Boih edges External interrupt request flag bit 0 When being read When being written EN nal input with specified edge detected 3 This bit is cleared 1 Signal input with specified edge No change does not affect other or edges detected operations Interrupt request enable bit 1 Disables interrupt request outputs Enables interrupt request outputs Edge polarity selection bits 1 Edge detection OFF Rising edge Falling edge Both edges External interrupt request flag bit 1 When being read When being written Signal input with specified edge This bit is cleared or edges not detected Signal input with specified edge change does not affect other or edges detected operations R W Readable Writable Initial value 232 CHAPTER 10 EXTERNAL INTERRUPT CIRCUIT 1 EDGE Table 10 4 1 Explanation of Functions of Each Bit in External Interrupt Control Register 1 EIC1 1 2 Bit name Function EIRI External interrupt request f
65. 12 bit PPG Timer Figure 9 3 1 Block Diagram of Circuitry Terminating at the P37 BZ PPG Pin lt Stop mode SPL 1 _ Pull up resistor i read Output from ripheral eun bud I peripheral when id modify write is im iperformed Output latch bad scs PDR write o ss ss c x c P37 BZ PPG PEELE Stop mode SPL 1 PUL read gt PUL PUL write Notes Ifthe ON setting of the pull up resistor is selected by the pull up setting register the pin state will be the level pull up state in stop mode SPL 1 Because buzzer outputs to the P37 BZ PPG pin precede 12 bit PPG outputs to this pin if the pin is used as the PPG pin turn the buzzer outputs off and set the RCEN bit such that PPG outputs are enabled 212 CHAPTER 9 12 BIT PPG TIMER 9 4 Registers of 12 bit PPG Timer This section describes the registers associated with the 12 bit PPG timer m Registers Associated with 12 bit PPG Timer Figure 9 4 1 Registers Associated with 12 bit PPG Timer RCR21 12 bit PPG control register 1 Address bit7 bits bit4 bit3 bit2 bit bit0 Initial value 00144 000000008 RW RW RW RW RN RW RW RW RCR22 12 bit PPG control register 2 Address _ bit7 bit6 bit bit4 bit3 bit2 bit1 bito Initial value 00154 HSC11 HSCtol HSC9 HSC8 HsC7 HSC6 RW RW RW RW RW RW RCR23 12 bit PPG control
66. 143 CHAPTER 7 8 BIT PWM TIMER Table 7 4 1 Explanation of the Functions of Each Bit in the PWM Control Register CNTR Bit name Function This bit is used to select the interval timer operation P TX 0 or PWM timer P TX operation P TX z 1 Bit to select the Note operation mode Before writing into this bit stop the counter operation 0 disable an interrupt TIE 0 and clear the interrupt request flag bit TIR 0 The value during a read is undetermined Unused bit A write does not affect operations This bit is used to select the count clock of the interval timer functions or PWM timer functions P1 PO One of three types of internal count clock or the output of the 8 16 bit capture Bits to select the clock timer or counter can be selected Note When the counter is operating 1 do not switch P1 and PO This bit is used to start and stop the interval timer functions or PWM timer functions To start the count operation write 1 to this bit When 0 is written to this bit the counter is cleared setting 00g and then stopped TPE Bit to enable the counter operation While the internal timer functions are enabled When the counter value matches the PWM compare register COMR value 1 is set to this bit TIR When this bit and the bit to enable an interrupt request TIE are 1 an interrupt Interrupt request flag bit request to the CPU is output While the PWM timer
67. 1526 to 11 9 64tINST 12207 to 95 4 381 5 t0 3 8 16 bit capture 48828 to 381 5 i 391k to 3k timer counter 12207 to 95 4 tmsr Instruction cycle The system clock control register SYCC selects the maximum clock speed CS1 and CS0 115 1 instruction cycle 4 in active mode Figure 13 1 4 shows an example of calculating the baud rate when the PWM timer is selected Figure 13 1 4 Example of Calculating the Baud Rate when the PWM Timer is Selected Clock gear X Input clock select bit selected PWM Compare paster 1 P1 0 P0 0 COME 16 P1 0 P0 1 Value specified in the CR 0 1 x Value of baud rate 64 P1 1 P0 0 compare register 1 2 XCR CR 1 6 8 16 timer P1 1 P0 1 The value of the baud rate is determined by the clock input specified in the clock dividing rate register CS1 and CSO The clock input is determined with an external clock PWM timer For calculation see Table 13 1 3 and Table 13 1 4 When an external clock is selected Foy 12 5 MHz 1 49kbps 1 28 us min x 16 CR 0 When the PWM timer is selected Foy 12 5 MHz 1 98kbps 0 32 us 4 x 1 P1 0 P0 0 x 1 COMR 0 x 2x 16 CR 0 1 24414 bps 0 32 us 4 x 1 P1 0 P0 0 x 1 COMR 0 x 2x 64 CR 1 283 CHAPTER 13 UART 13 2 Configuration of UART UART consists of the following ten registers and components Serial mode control register SMC Serial rate control register SR
68. 5 4 3 2 1 0 Serial output data SOOO OO X Shift clock 0 1 2 3 4 5 6 7 SIOF bit Transfer start Interrupt request Automatic clear at transfer end B Operation at Serial Output Completion At the rising edge of the shift clock for serial data of the 8th bit the interrupt request flag bit SMR SIOF is set to 1 and the serial I O start bit SMR SST is set cleared to 326 CHAPTER 14 8 BIT SERIAL I O 14 7 Operations of Serial Input Functions In the 8 bit serial I O 8 bit serial input operation synchronized with a shift clock is possible Serial Input Operation Serial input operation is divided into serial input operation with an internal shift clock and serial input operation with an external shift clock When serial I O operation is allowed serial data is input in the SDR and at the same time the contents of the SDR are output to the serial data output pin SO Serial input operation using internal shift clock Serial input operation with the internal shift clock requires the settings shown in Figure 14 7 1 Figure 14 7 1 Settings Required for Serial Input Operation using Internal Shift Clock bit7 bit6 bit5 bit4 bit3 bit2 bit bitO SMR Ny 1 x 1 Other than 11 9 SDR Reception data storage DDRS3 SSEL Used bit Unused bit When serial input operation is started the value of the serial data input pin SI is captured and held in t
69. 74 CHAPTER 4 PORTS This chapter describes the functions and operations of ports 4 1 Overview of I O Ports 4 2 Porto 4 3 Port 3 4 4 Port 4 4 5 Port 5 4 6 Port 6 4 7 Port 7 4 8 Programming Example of I O Port 75 CHAPTER 4 I O PORTS 4 1 Overview of I O Ports Six I O ports comprising 26 pins are available as general purpose I O ports parallel I O ports These ports also serve peripherals as I O pins for specific peripheral functions m Functions of I O Ports The I O ports function to output data from the CPU to I O pins via their port data register PDR and send signals input to I O pins to the CPU For some ports the I O direction of I O pins can be set by optionally setting the bits of the port data direction register DDR with the bits corresponding to the pins The functions of the ports and peripherals for which the ports may serve are summarized below Port 0 General purpose I O port may also serve peripherals external interrupt 2 and analog input pins Port 3 General purpose I O port may also serve peripherals 12 bit PPG external interrupt 1 UART 8 bit serial I O 8 16 bit timers and buzzer output pin e Port 4 General purpose I O port of a type switched between CMOS push pull and N ch open drain may also serve peripherals analog input pins Port 5 General purpose I O port may also serve peripherals 8 bit PWM pin Port 6 General purpose I O port for MB
70. 8 us 4 Foy x 2 5 PR2 0 PR1 1 PRO 0 x 1 CS12CSOz1 x 1 synchronous x 1 RC2 RC1 RCO0 0 x 1 synchronous Table 13 1 3 provides an example of the baud rates selectable when an external clock is used Table 13 1 3 Transfer Cycles and Transfer Rates Selectable for an External Clock Asynchronous transfer mode Synchronous transfer mode Divider for baud rate Transfer cycle Transfer rate bps Divider for baud rate Transfer cycle Transfer rate bps CR 0 16 256 Foy or more 48828 or less CR 1 64 1024 Fey or more 12207 or less 16 Fcg or more The minimum value of Foy specified for 12 5 MHz is external clock cycle 16 Foy 1 28 Foy Oscillation frequency 7781 k or less Figure 13 1 3 Example of Calculating the Baud Rate when an External Clock is Selected 282 1 Value of baud rate Fou Oscillation frequency External clock input xx CR Eis min 8 2 CR 1 64 CHAPTER 13 UART Table 13 1 4 provides an example of the baud rates selectable when the 8 bit PWM timer is used Table 13 1 4 Transfer Cycles and Transfer Rates Selectable for the 8 bit PWM Timer PWM timer Asynchronous transfer mode Synchronous transfer mode count clock cycle Divider for clock Transfer rate bps Divider for clock Transfer rate bps 97656 to 763 781k to 6 1k 24414 to 191 6103 to 47 8 16tyyst 48828 to 381 5 1526 to 11 9
71. APPENDIX E Pin State of the MB89202 F202RA Series 402 UNDE 403 Main changes in this edition Page Changes For details refer to main body The followings product name is changed MB89202 MB89202 F202RA The followings term is changed source oscillation oscillation frequency 1 3 Differences between Models Notes is changed The followings sentence is deleted e At turning on the power when the device is used without inputting the external reset select reset output supported and power on reset supported by mask option The followings package is changed in Table 1 3 1 FPT 34P M03 FPT 32P M03 1 7 Pin Functions RST pin in Table 1 7 1 is changed 2 Precautions on Handling Devices 3 1 1 Specific purpose Areas 3 5 Reset 3 6 3 System Clock Control Register S YCC External pull up for the External Reset Pin RST of MB89F202 F202RA is changed The summary is changed Bl General purpose Register Area address 0100y to 01FFp is changed Bi Vector Table Area Address FFCOg to FFFF is changed Power on reset is changed Note is deleted Figure 3 6 5 is changed Table 3 6 1 is changed 6 3 Watchdog Control Register WDTC Figure 6 3 1 is changed 8 6 Explanation of Operations of Interval Timer Functions 8 bit mode is
72. BIT PPG TIMER 9 5 Operations of 12 bit PPG Timer Functions The 12 bit PPG timer can be used as a 12 bit PPG because the output pulse cycle period and H pulse width can be set separately m Example of Operations of 12 bit PPG Timer Functions To operate the 12 bit PPG timer the bits of the registers must be set as shown in Figure 9 5 1 Figure 9 5 1 Setting 12 bit PPG Timer bit7 bit6 bit5 bit4 bit3 bit2 bit bitO RCR21 RCK 9 9 RCR22 Hsct1 Hscio HSC7 HSC6 RCR23 SCL5 ScL4 scLs ScL2 ScL1 SCLO 1 RCR24 1SCL11 SCL10 SCL9 SCL8 SCL7 SCL6 Used bit 1 Set 1 When 12 bit PPG outputs are enabled the 12 bit counter starts counting from 000g in synchronization with the selected count clock and the PPG pin is maintained at H level until a count by the counter is synchronized with the compare value for the width The PPG pin is then maintained at L level until a count by the counter is synchronized with the compare value for the cycle period At this time the 12 bit counter is cleared and restarts counting from 000p Because the width and cycle period can be set separately the timer can be used as a 12 bit PPG 219 CHAPTER 9 12 BIT PPG TIMER Figure 9 5 2 illustrates the operation of the 12 bit PPG timer Figure 9 5 2 Operation of 12 bit PPG Timer
73. BZCR BZ2 BZ1 BZ0 0005 the P37 BZ PPG pin automatically works as the BZ pin regardless of the value of output latch Even if the PPG output has been enabled it works as the BZ pin that has higher priority m Block Diagram of the Pin Related to the Buzzer Output Figure 15 3 1 Block Diagram of Pin Related to Buzzer Output Stop mode SPL 1 Pull up resistor PDR read MU EE Peripheral output i Peripheral output enable PDR read At read modify write PDR write Pss EEE E Pin P37 BZ PPG o 5 a E E o g DDR write Stop mode SPL 1 PUL read PUL write Note If pull up resistor supported is specified by the pull up setting register the state of the pin in stop mode SPL 1 is not Hi Z but level pull up state During a reset however the pull up is disabled and the state is Hi Z 342 CHAPTER 15 BUZZER OUTPUT 15 4 Buzzer Register BZCR The buzzer register BZCR is used to select an output frequency of the buzzer and also serves as the buzzer output enable m Buzzer Register BZCR Figure 15 4 1 Buzzer Register BZCR Address bit7 bit bits bit4 bit3 bit2 biti bitd Initial value orsu 1I 1 823 SZ 829 RAN R W RW BZ2 21 BZO Buzzer selection bits Fcu 12 5 MHz Works as a general purpose output port P37 or the 12 bit PPG output PPG 1 Outputs 213 1 526 kHz
74. Bits to be set High order Low order IRQ9 ILR3 007Dg L91 bit3 L90 bit2 FFE8g FFE9 See Section 3 4 2 Steps in the Interrupt Operation for interrupt operations 147 CHAPTER 7 8 BIT PWM TIMER 7 6 Operations of the Interval Timer Functions This section describes the operations of the interval timer functions of an 8 bit PWM timer B Operations of the Interval Timer Functions 148 To make an 8 bit PWM timer operate as an interval timer set registers as shown in Figure 7 6 1 Figure 7 6 1 Setting Interval Timer Functions bit7 bit6 bit5 bit4 bit3 bit2 bit1 bitO CNTR Pt Po Pe Oe TE 0 1 6 6 COMR Set an interval compare value Used bit 1 Set 1 Set When the counter is activated the counter is incremented from 00g at the start up of the selected count clock When the counter value matches the value set in the COMR register comparison value the timer inverts the level of the PWM pin clears the counter sets the interrupt request flag bit CNTR TIR 1 and starts incrementing again from 00g at the next start up of the count clock Figure 7 6 2 shows the operations of an 8 bit PWM timer CHAPTER 7 8 BIT PWM TIMER Figure 7 6 2 Operations of an 8 bit PWM Timer Counter value Comparison value FFH Comparison value 80H FFH 80H lt gt i Timer cycle Change of the value FFu 804 COMR value Clear in
75. Circuit 1 Block Diagram of Circuitry Terminating at the Pins Associated with External Interrupt Circuit 2 247 Block Diagram of External Interrupt Circuit 1 227 Block Diagram of External Interrupt Circuit 2 HQ 245 406 External Interrupt Circuit 1 Programming Example 241 Functions of External Interrupt Circuit 1 226 Functions of External Interrupt Circuit 2 Level 244 V O Circuit Types nente 14 Interrupt during the Operation of External Interrupt Circuit catene 237 Interrupt during the Operation of External Interrupt Circuit 2 niii retenue 253 Operation of External Interrupt Circuit 1 239 Operation of External Interrupt Circuit 2 254 Pins Associated with External Interrupt Circuit 1 229 Pins Associated with External Interrupt Circuit 2 246 Program Example for External Interrupt Circuit 2 256 Register Associated with Interrupt Generation by External Interrupt Circuit 1 and Vector Table itt t emet eee 238 Register Associated with Interrupt Generation by External Interrupt Circuit 2 and Vector Table ien 253 Registers Associated with External Interrupt Circuit 1 TERES 231 Registers Associated with External Interrupt Circuit 2 DIDIT 249 Ci
76. Configuration of the Buzzer Output The buzzer output consists of the following two blocks e Buzzer output selector e Buzzer register BZCR m Block Diagram of the Buzzer Output Figure 15 2 1 Block Diagram of Buzzer Output Internal data bus ez Buzzer enable signal Selector Buzzer output output From time base timer selector P37 BZ PPG Fop Oscillation frequency Buzzer output selector The buzzer output selector is a circuit for selecting one of the four frequencies square waves output from the time base timer The buzzer register BZCR sets it Buzzer register BZCR The buzzer register BZCR is a register for setting the buzzer output frequency and enable the buzzer output When the BZCR register sets an output frequency other than 000p the buzzer output is enabled so that the P37 BZ PPG pin automatically becomes the buzzer output BZ pin Even if the PPG pin has been enabled the BZ pin has higher priority 341 CHAPTER 15 BUZZER OUTPUT 15 3 Pin of the Buzzer Output The pin related to the buzzer output is P37 BZ PPG m P37 BZ PPG Pin The P37 BZ PPG pin works as a general purpose I O P37 pin output pin for the buzzer output BZ or output pin for the 12 bit PPG PPG e BZ pin The BZ pin outputs the square wave for the buzzer of the frequency having been specified for the BZ pin When a buzzer output frequency is specified other than
77. FC36y from FFy to B5g Table 16 4 1 Operation Order of Wild Register Operation Operation example Address FC36y data FFy WRARLO 36y WRARHO FCgy Set an address of the wild register correspondence area to the address set register Set the correction data to the data setting register WRDRO B5g Set 1 to the address comparison ENOO bit WREN O0lg When address FC36y is accessed The wild register works at the time of address matching l Data B54 m Wild Register Addresses List Table 16 4 2 lists the addresses corresponding to the wild register numbers Table 16 4 2 Wild Register Addresses List Higher address Lower address Data Register name Address Register name Address Register name Address WRARHO WRARLO WRARHI WRARLI 356 CHAPTER 17 FLASH MEMORY This chapter describes the functions and operation of the 128K bit flash memory The following three methods are available for writing data to and erasing data from the flash memory 1 Parallel programmer 2 Writing erasing data using a serial programmer 3 Executing programs to write erase data This chapter explains Executing programs to write erase data Note Auser must create a serial programmer for writing 17 1 Overview of Flash Memory 17 2 Flash Memory Control Status Register FMCS 17 3 Starting the Flash Memory Automatic Algorithm 17 4 Confirming the Automatic Algorithm Execution Sta
78. H to 5 2 9 8 bit mode I TCR1 TSTR1 resto Testi Tosi2 THEN TFCR1 TIF1 166 Port output enable TimerO Timer1 output selection TET Tee TCR2 CHAPTER 8 8 16 BIT CAPTURE TIMER COUNTER Count clock selectors 0 1 Circuits that select input clocks In timer 0 for the 8 bit mode or in the 16 bit mode count clock selector 0 1 can select seven internal clocks and one external clock In timer 1 for the 8 bit mode the selector can select only seven internal clocks Counter circuits 0 1 Counter circuit 0 and counter circuit 1 each consist of an 8 bit counter a comparator a comparator data latch and data registers TDRO TDR1 The 8 bit counter is incremented according to the selected count clock and clock edge rising falling The comparator compares the counter value with the comparator data latch value When these values match the counter is cleared and the data register value is set in loaded to the comparator data latch In the 8 bit mode counter circuits 0 and 1 operate independently as timer 0 and timer 1 respectively In the 16 bit mode counter circuits 0 and 1 operate as the 16 bit counter in which counter circuit O is concatenated as lower 8 bits and counter circuit is concatenated as higher 8 bits Square wave output control circuit When the comparator detects that the counter value matches the comparator data latch value in the 8 or 16 bit
79. O 14 1 Overview of 8 Bit Serial I O The 8 bit serial I O has a function that serially transfers 8 bit data in synchronization with a shift clock It can select one shift clock from three internal shift clocks and one external shift clock It can also select LSB first or MSB first as the data shift direction m Serial I O Function The 8 bit serial I O function serially inputs and outputs 8 bit data in synchronization with a shift clock e Converts 8 bit parallel data to 8 bit serial data and outputs it Also inputs 8 bit serial data converts the data to 8 bit parallel data and stores it Can select one shift clock from three internal shift clocks and one external shift clock Cancontrol shift clock input output and output internal shift clocks Canselect LSB first or MSB first as the data shift direction Table 14 1 1 Shift Clock Cycle and Transfer Rate Transfer rate Shift clock Clock cycle Frequency Hz Foy 12 5MHz At maximum speed 1562 5 kbps Internal shift clock output StunsT V Str 390 6 kbps 32tINST 1 32 97 66 kbps External shift clock input 2tinst lower 1 24 or lower DC to 1562 5 kbps Foy Oscillation frequency tsr Instruction cycle When the highest speed clock of a general mode is selected with the system clock control register SYCC CS1 and CSO bits of SYCC 115g 1 instruction cycle 4 Foy Serial Function
80. P32 UI SI This port functions as the general purpose I O port P32 serial data input pin UD or 8 bit serial data input pin SI When using this pin as the UART serial data input pin set this pin as the input port by using the corresponding port direction register DDR3 bit2 0 287 CHAPTER 13 UART m Block Diagram of the UART relating Pins Figure 13 3 1 Block Diagram of UART relating Pins Stop mode PDR read Resource output SPL 1 m Resource iPull up resistor i MN output Resource enable X N output allowed IPDR read At read modify write Pin P30 UCK SCK P31 UO SO DDR write P32 UI SI Stop mode SPL 1 o 2 a S o o 2 PUL read PUL write When use of the pull up resistor is selected in the pull up setting register the pin status does not become Hi Z but H level pull up state in stop mode SPL 1 However the pull up resistor is not applied during reset accordingly the pin status becomes Hi Z 288 CHAPTER 13 UART 13 4 Registers of UART Figure 13 4 1 shows the UART relating registers m UART relating Registers Figure 13 4 1 UART relating Registers SMC serial mode control register Address bit7 bit6 bit5 bit4 bit3 bit2 bit bito Initial value 00284 SMDE SCKE SOE 00000 008 R W R W R W R W R W R W R W SRC serial rate control register Address bit7 bit6 bit5 bit4 bit3 bi
81. P34 TO INT1O 1P40 ANO to 1P43 AN3 CMOS I O port Bo Ae N ch OD 2 512 or 256 bytes RAM 12 bit PPG F2MC 8L CPU P37 BZ PPG Other pins F Buzzer output Wild register CMOS I O port Large current drive type Check section 3 1 Memory Space CHAPTER 1 OVERVIEW 1 5 Pin Assignment Figure 1 5 1 and Figure 1 5 2 show the pin assignment of the MB89202 F202RA series m Pin Assignment of DIP 32P M06 Figure 1 5 1 Pin Assignment of DIP 32P M06 PO4 INT24 PO5 INT25 PO6 INT26 PO7 INT27 P60 P61 OOA Vss P37 BZ PPG P36 INT12 P35 INT11 P34 TO INT10 P33 EC Large current drive type Vcc PO3 INT23 AN7 P02 INT22 AN6 PO1 INT21 AN5 POO INT20 AN4 P43 AN3 P42 AN2 P41 AN1 P40 ANO P72 P71 P70 P50 PWM P30 UCK SCK P31 UO SO P32 UI SI m Pin Assignment of FPT 34P M03 CHAPTER 1 OVERVIEW Figure 1 5 2 Pin Assignment of FPT 34P M03 PO4 INT24 POS INT25 PO6 INT26 PO7 INT27 P60 P61 RST X0 1 Vss P37 BZ PPG P36 INT12 P35 INT11 P34 TO INT10 P33 EC N C C Voc POS INT23 AN7 Large current drive type Note N C Do not use because it is connected internally PO2 INT22 AN6 PO1 I
82. PR1 1 PRO 0 PR2 0 PR1 0 PRO 0 Divider for baud rate Asynchronous Synchronous Asynchronous Synchronous multiplier n transfer transfer transfer transfer 83 12019 0 8 1 25M 33 30048 0 32 3 1M 166 6010 1 6 625k 67 15024 0 64 1 6M 333 3005 3 2 313k 133 7512 1 28 781k 666 1503 6 4 156k 266 3756 2 56 391k 1331 751 12 8 78k 532 1878 5 12 195k 2662 375 25 6 39k 1065 939 10 24 98k 13 78125 1 6 625k 5 12 195k 0 64 1 6M 102 9766 12 8 78k 41 24k 5 12 195k 281 CHAPTER 13 UART 1 Value of baud rate Figure 13 1 2 Example of Calculating the Baud Rate Clock gear selected 4 8 16 64 Notes Clock divider selected PR2 PR1 PRO Divided by 1 2 2 5 3 4 0r5 Baud rate selected RC2 RC1 RCO Divided by 1 2 4 8 16 or 32 Synchronous asynchronous mode selected SMDE Divided by 1 or 13 Note When RC2 is 1 and RC1 is 1 the divider is 1 Clock rate CR Divided by 1 or 8 The baud rate is specified using the clock gear register CS1 and CSO clock divider registers PR2 and PRO or baud rate selection registers RC2 RC1 and RCO For the example of calculating the baud rate see Table 13 1 2 Asynchronous transfer mode 1 12019bps 0 8 us 4 Foy 2 5 PR2 0 PR1 1 PRO 0 x 1 CS12CSOz1 x 8 asynchronous x 1 RC2 RC1 RCO0 0 x 13 asynchronous Synchronous transfer mode 1 1 25Mbps 0
83. This bit specifies synchronous transfer or asynchronous transfer mode When this bit is 0 synchronous transfer mode is set When this is 1 asynchronous transfer mode is set Unused bit The value read out from this bit is undefined Writing a value into this bit does not affect any operations SCKE Clock output enable bit This bit controls I O of the serial clock When this bit is 0 P30 UCK SCK pin functions as the serial clock input pin When this bit is 1 it functions as the serial clock output pin Notes When the UCK pin functions as the serial clock input pin SCKE 0 set the P30 UCK SCK pin as the input port Also select the external clock using the clock input selection bit SRC CS1 and CSO 005p When the UCK pin is set as the serial clock output pin SCKE 1 select a clock other than the external clock SRC CS1 and CSO must not be 005 Note When the UCK pin is specified as the serial clock output SCKE 1 it functions as the UCK output pin regardless of the state of the general purpose port P30 SOE Serial data output enable bit When this bit is 0 the P31 UO SO pin functions as a general purpose port P31 When this bit is 1 it functions as the serial data output pin UO Note When serial data output is enabled SOE 1 the pin functions as the UO pin regardless of the state of the general purpose port P31 291 CHAPTER 13 UART 13 4 2 Serial Rate
84. and the count clock cycle is set to 2tpygp 8 bit mode operation the interval time of timer 0 and the square wave frequency output from the TO pin when the interval timer function is operated continuously without modifying the TDRO register value are calculated from the following expressions However the values calculated from these expressions are valid when the highest speed clock of the normal mode CS1 CSO 11g 1 instruction cycle 4 is selected according to the system clock control register SYCC Interval time 2 x x TDRO 1 register value 1 8 12 5 MHz x 221 1 142 1 us Output frequency Fcu 2 x 8 x TDRO 1 register value 1 12 5 MHz 16 x 221 1 3 53 kHz 164 CHAPTER 8 8 16 BIT CAPTURE TIMER COUNTER Counter Function The counter function counts the falling edges of the external clocks input to the P33 EC external pin The 8 16 bit capture timer counter can operate independently because the EC pin acts as an external clock input pin Only timer 0 can select the external clock The counter function operates using timer 0 with the 8 bit mode or with the 16 bit mode The counter function counts the number of edges of the external clocks selected by the count clock selection bit CINV of the timer 0 control register TCRO When the number of edges equals the setting value the counter function generates an interrupt request and inverts the output level of the square wave outpu
85. and to manage the interrupt Interrupt request sample wait time Generation of an interrupt request is checked by sampling an interrupt request at the last cycle of each instruction Therefore the CPU cannot identify an interrupt request while it is executing an instruction The wait time becomes maximum when an interrupt request is generated immediately after the CPU executes the DIVU instruction 21 instruction cycles with the longest instruction cycle Interrupt handling time After accepting an interrupt the CPU needs 9 instruction cycles for interrupt processing preparation to e Save the values in the program counter PC and program status PS Set the address at the beginning of the interrupt processing routine interrupt vector into the PC e Update the interrupt level bits PS CCR IL1 and ILO in the program status PS Figure 3 4 4 shows the interrupt processing time Figure 3 4 4 Interrupt Processing Time Execution of Int Interrupt processing CPU performs gt lt general instruction nterrupt handing routine Interrupt wait _ Interrupt request Interrupt handling time time sample wait time 9 instruction cycles T Interrupt request is generated lt gt Last instruction in which an interrupt is sampled When an interrupt request is generated immediately after the DIVU instruction having the longest instruction cycle 21 instruction cycles 30 instruction cycles 21 instructions 9 i
86. are output to the SO pin in synchronization with the falling edge of the selected internal shift clock In this case the transfer destination serial input side must be in the external shift clock input wait state 325 CHAPTER 14 8 BIT SERIAL I O Serial output operation using external shift clock Serial output operation with the external shift clock requires the settings shown in Figure 14 6 2 Figure 14 6 2 Settings Required for Serial Output Operation using External Shift Clock bi7 5 bi2 smR sioe SckE SOE Bos SST 0 1 1 1 1 sR Transmissiondataseting Used bit Unused bit Set 0 Set 1 When serial output operation is allowed the contents of the SDR are output to the SO pin in synchronization with the falling edge of the external shift clock When serial operation is completed immediately reset the SDR set it again then allow serial output operation SMR SST 1 to prepare for the output of the next data When the remote serial input operation rising edge is completed and the 8 bit serial I O enters the idle state state in which it waits for the output of the next data set the external shift clock to a high level Figure 14 6 3 shows 8 bit serial output operation Figure 14 6 3 8 bit Serial Output Operation For LSB first bit7 bite bit5 bit4 bit3 bit2 bit1 bito SO pin SDR 7 6
87. bit6 bitb bit4 bit3 bit2 bit bitO Initial value RW RW RW RW R RW R W A D conversion activation bit This bit is enabled only when software is activated ADC2 EXT 0 Always 0 for at reading 0 A D conversion functions are not activated 1 A D conversion functions are activated Reserved bit Not changed This does not affect others Not changed This does not affect others Converting flag bit Not during conversion During conversion Interrupt request flag bit During read During write SU has notbesn This bit is cleared Conversion has been Not changed This does not completed affect others ANSO Analog input channel selection bits 90 ANO pin PA0 ANO o 1 AN pin P41 AN1 3 j ANZpi PAJANZ O 13 1 AN3pin P43 AN3 1 1 1 o AN4 pin POO INT20 AN4 1 ANS pin PO1 INT21 AN5 AN6 pin PO2 INT22 ANG AN7 POS INT23 AN7 R W Readable Writable R Read only Initial value 266 CHAPTER 12 A D CONVERTER Table 12 4 1 Explanation of Functions of Each Bit in the Bits in A D Control Register 1 ADC1 Bit name Function Unused bit The value during read is not determined e Write does not affect operations ANS2 ANSI ANSO Analog input channel selection bits This bit is used to select which pin to be used as an analog input from ANO to ANT When software is activated ADC2 EXT 0 this bit can be rewritt
88. capture timer counter x 1 channel When timer 0 or a 16 bit counter is operating event counting operation by external clock input and square wave output are supported Transfer data length 6 7 or 8 bits 8 bits length LSB first MSB first selectability One clock selectable from four operation clocks one external shift clock three internal shift clocks 2 tts 8 tins 32 tjs T 12 bit PPG timer Output frequency Pulse width and cycle are selectable External interrupt 1 wake up 3 channels interrupt vector request flag and request output enable Edge selectability selectable from rising edge falling edge and both edge modes Also available for wake up from stop or sleep Edge detection is also available in stop mode External interrupt 2 wake up 8 inputs 1 channel L level interrupt and input enable are independent Also available for wake up from stop or sleep Level detection is also available in stop mode 10 bit A D converter 10 bit resolution x 8 channels A D conversion function Conversion time 38 Continuous activation by 8 16 bit capture timer counter output or time base timer output Wild register Note 8 bit x 2 The oscillation is 12 5 MHz unless another condition such as the main clock maximum speed the clock cycle value or conversion time is stated CHAPTER 1 OVERVIEW 1 3 Differences between Models This section describes the precautions to be
89. changed The followings sentence is deleted The initial value of the square wave output is L level The square wave output is initialized by writing 0 to the TSTR bit of the timer control register TCR 12 3 Pins of A D Converter B Block Diagram of the Pins Related to the A D Converter is changed Note is deleted 13 6 2 Reception Operations Operating Mode 0 1 or 3 B Reception Operations Operating Mode 0 1 or 3 is changed Note is changed xi Page Changes For details refer to main body 13 6 3 Reception B Reception Operations Operating Mode 2 Only is changed Operations Operating Note is changed Mode 2 Only 17 1 Overview of Flash B High voltage supply on RST pin applicable to MB89F202RA only is added Memory 17 5 2 Writing Data Figure 17 5 1 is changed F555 E554 B 4 F MC 8L Table B 4 2 is changed Instructions List No 22 DECW A is changed The vertical lines marked in the left side of the page show the changes Xii CHAPTER 1 OVERVIEW This chapter describes the features and basic specification of the MB89202 F202RA series 1 1 Features of MB89202 F202RA Series 1 2 MB89202 F202RA Series Product Lineup 1 3 Differences between Models 1 4 Block Diagram of MB89202 F202RA Series 1 5 Pin Assignment 1 6 Package Dimensions 1 7 Pin Functions Description 1 8 I O Circuit Types CHAPTER 1 OVERVIEW 1 1 Features o
90. clear at transfer end B Operation at Serial Input Completion At the rising edge of the shift clock for the serial data of the 8th bit the interrupt request flag bit SMR SIOF is set to 1 and the serial I O start bit SMR SST is set cleared to 328 CHAPTER 14 8 BIT SERIAL I O 14 8 8 Serial I O Operation in Each Mode This section describes the operation of the 8 bit serial I O if the 8 bit serial I O switches to sleep or stop mode or a stop request is issued when it is in operation m When the Internal Shift Clock is Used 8 bit serial I O operation in sleep mode In sleep mode as shown in Figure 14 8 1 the 8 bit serial I O continues data transfer without stopping the serial I O operation Figure 14 8 1 8 bit Serial I O Operation in Sleep Mode Internal Shift Clock v VI AS AS AS AS AS ASA SST bit Clear via program SIOF bit 3 i Interrupt request SO pin output Sleep mode SLP bit m STBC register Sleep mode release via IRQC 38 bit serial I O operation in stop mode In stop mode as shown in Figure 14 8 2 the 8 bit serial I O stops the serial I O operation and suspends data transfer After stop mode has been released reinitialize the 8 bit serial I O because operation is resumed halfway 329 CHAPTER 14 8 BIT SERIAL I O Figure 14 8 2 8 bit Serial I O Operation in Stop Mode Internal Shift Clock SCK output Seri Oscillation stab
91. cycle period and width of output pulse waveforms and can also be used as a remote control transmission frequency generator or 12 bit PPG m Functions of 12 bit PPG Timer The timer generates a frequency for remote control and outputs signals to a PPG pin The timer is capable of setting a cycle period and width of output pulse waveforms separately The timer enables the selection of a count clock from four types of internal clocks The timer can generate a frequency in a range from twice to 2 1 times as fast as the counter clock Table 9 1 1 lists the ranges in which the output pulse cycle period and H width are variable Table 9 1 1 Ranges in which the Output Pulse Cycle Period and Width are Variable Internal count clock cycle period Output pulse cycle period Output pulse H width 4tinst to 8190tinst 2tINST to 8188tINST StINST to 16380tiNsT 4tinst to 16376tjNsT tsr Instruction cycle to be affected by a gear function Note An example of calculating the output pulse cycle period and H width as executed by a 12 bit PPG function is given below When an oscillation Fcp of 12 5 MHz and a count clock cycle period of 2 are set and if Compare value for cycle period 011110g 30 clock period Compare value for width 001010 10 clock width Then H width and the cycle period of output pulse waveforms are calculated as given below These calculations are obtained p
92. edge detection When this bit is 1 at write the capture edge detection flag is cleared When flag clear bit 0 the capture edge detection flag is not affected remains unchanged CPIEN This bit is used to allow and prohibit interrupt request output to the CPU Capture interrupt request An interrupt request is output when this bit and the capture edge detection flag enable bit bit CPIF are 1 CCMSK The counter state when a capture match is detected is set Counter clear mask bit When this bit is 0 the counter is cleared When this bit is 1 the counter is at capture operation not cleared TCMSK The counter state when a compare edge is detected is set Compare match counter When this bit is 0 the counter is cleared When this bit is 1 the counter is clear mask bit not cleared These bits are used to allow and prohibit the capture function and select EDGS1 and EDGSO capture edges Capture mode enable When using the 8 16 bit capture timer counter in the capture mode set these edge detection selection bits to a value other than 00g bits When the edge set by these bits is input the capture edge detection flag bit CPIF is set to 1 Even if this bit is set to 0 or 1 the operation is not affected The value RESV Reserved bit previously written becomes the read value 172 CHAPTER 8 8 16 BIT CAPTURE TIMER COUNTER 8 4 2 Timer 0 Control Register TCRO The timer 0 cont
93. elements e General purpose I O pins external interrupt 1 input pins and input output pins for peripherals P30 UCK SCK to P37 BZ PPG e Port 3 data register PDR3 e Port 3 data direction register DDR3 Port 3 pull up setting register PUL3 m Pins of Port 3 Port 3 has eight CMOS I O pins These pins can be used as both input pins and external interrupt input pins at the same time These pins cannot be used as a general purpose I O port when being used for peripherals Table 4 3 1 lists the pins of port 3 Table 4 3 1 Pins of Port 3 Input and output form Circuit Input Output type Pin name Function Peripherals for which the pin may serve P30 general purpose UART clock I O CMOS P30 UCKISCK 8 bit serial I O clock hysteresis P31 general purpose UART data output FSTIDOISO Uo 8 bit serial I O data output CMOS P32 general purpose UART data input CMOS P32 UI SI VO 8 bit serial I O data input hysteresis P33 general purpose P33 EC Uo 8 16 bit timer and counter clock inputs P34 general purpose 8 16 bit timer and counter timer outputs ETON TG Uo External interrupt input 10 CMOS hysteresis P35 general purpose P35 INT11 yo External interrupt input 11 P36 general purpose P36 INT 12 yO External interrupt input 12 P37 general purpose Buzzer output P37 BZ PPG UO 12 bit PPG output For circuit type see 1 7 Pin Functions Description
94. external interrupt request flag bit of the external interrupt 2 flag register EIF2 Interrupt request An interrupt request is generated if the state of one of the above external interrupt pins is L IRQA 244 CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT 2 LEVEL 11 2 Configuration of External Interrupt Circuit 2 The external interrupt circuit 2 comprises the following three blocks Interrupt request generating circuit e External interrupt 2 control register EIE2 e External interrupt 2 flag register EIF2 m Block Diagram of External Interrupt Circuit 2 Figure 11 2 1 Block Diagram of External Interrupt Circuit 2 External interrupt 2 control register EIE2 External interrupt 2 flag register EIF2 IF20 20 4 PO1 INT21 AN5 PO4 INT24 i External interrupt XM request POS INT25 IRQA P06 INT26 P07 INT27 Interrupt request generating circuit The interrupt request generating circuit generates an interrupt request signal in accordance with the signal input to one of the external interrupt pins INT20 to INT27 and the contents of an external interrupt input enable bit External interrupt 2 control register EIE2 The external interrupt input enable bits IE20 to IE27 enable or disable L level input from the external interrupt pins with each bit corresponding to a pin External interrupt 2 flag register EIF2 The external interrupt request flag bit IF2
95. extra pointer is handled as the memory address for accessing data The initial value of the extra pointer specified after the reset operation is undefined Stack pointer SP The stack pointer is a 16 bit register that stores an address that is used to call an interrupt or subroutine or to which a stack recovery instruction makes a reference While a program is being executed the value of the stack pointer indicates the address of the latest data put in the stack The initial value of the stack pointer specified after the reset operation is undefined Program status PS register The program status is a 16 bit control register The upper 8 bits of the program status register is the register bank pointer RP used to indicate the address of a general purpose register bank The lower 8 bits are the condition code register CCR that composes flags for indicating the CPU status Because these 8 bit registers comprise the program status register they cannot be accessed Only instructions MOVW A PS and MOVW PS A access the program status register Note For details on how to use the dedicated register see the F MC 8L 89600 Series Programming Manual CHAPTER 3 CPU 3 2 1 Condition Code Register CCR The condition code register CCR is the lower 8 bits of the program status register PS The condition code register consists of bits C V Z N and H for indicating the results of arithmetic operations or data to be transfe
96. flag is turned on CCR I 1 Put the values in the program counter PC and program status PS in the stack fetch the start address of the interrupt processing routine from the interrupt vector table concerned change the value of the interrupt level bits in the condition code register CCR IL1 and ILO to the value of the interrupt level accepted and then start the interrupt processing routine Finally restore the values of the program counter PC and program status PS put into the stack with the RETI instruction then execute an instruction following the instruction executed immediately before the interruption Standby mode low power consumption mode is cancelled by an interrupt For details see Section 3 7 Standby Mode Low Power Consumption Mode Notes 38 An interrupt request flag bit for a peripheral function is not automatically cleared even if the interrupt request is accepted Therefore it is necessary to clear the bit using a program in the interrupt processing routine by writing 0 into the interrupt request flag bit normally Clearing an interrupt request flag bit at the beginning of the interrupt processing routine allows the peripheral function that generated the interrupt to re generate an interrupt set an interrupt request flag bit again while the interrupt processing routine is being executed However the re generated interrupt is normally accepted after the interrupt processing routine ends its cu
97. flash memory or else the flash memory may become malfunction 361 CHAPTER 17 FLASH MEMORY 17 4 Confirming the Automatic Algorithm Execution State Because the write erase flow of the flash memory is controlled using the automatic algorithm the flash memory has hardware for posting its internal operating state and completion of operation This automatic algorithm enables confirmation of the operating state of the built in flash memory using the following hardware sequence flags m Hardware Sequence Flags 362 The hardware sequence flags are configured from the five bit output of DQ7 DQ6 DQ5 and DQ2 The functions of these bits are those of the data polling flag DQ7 toggle bit flag DQ6 timing limit exceeded flag DQ5 and toggle bit2 flag DQ2 The hardware sequence flags can therefore be used to confirm that writing or chip sector erase has been completed or that erase code write is valid The hardware sequence flags can be accessed by read accessing the addresses of the target sectors in the flash memory after setting of the command sequence see Table 17 3 1 in Section 17 3 Starting the Flash Memory Automatic Algorithm Table 17 4 1 lists the bit assignments of the hardware sequence flags Table 17 4 1 Bit Assignments of Hardware Sequence Flags Hardware sequence flag To determine whether automatic writing or chip sector erase is being executed the hardware sequence flags can be checked or the sta
98. functions are enabled an interrupt request does not occur When this bit is written it is cleared setting 0 Writing 1 does not affect this bit in any way When this bit is 0 the P50 PWM pin is used as a general purpose port P50 OE When the bit is 1 it is used as a dedicated pin PWM Bit to control the output When the interval timer functions are enabled the square wave is output to the pin PWM pin When the PWM timer functions are enabled the PWM wave is output to the PWM pin TIE This bit is used to enable and disable the output of an interrupt request to the CPU Bit to enable an interrupt When this bit and the interrupt request flag bit TIR are both 1 an interrupt request request is output 144 CHAPTER 7 8 BIT PWM TIMER 7 4 2 PWM Compare Register COMR The PWM compare register COMR is used to set an interval while the internal timer functions are enabled In addition the register becomes the H level width of a pulse while the PWM timer functions are enabled m PWM Compare Register COMR Figure 7 4 3 shows the bit configuration of a PWM compare register Because this register is a write only register an instruction to operate bits cannot be used Figure 7 4 3 PWM Compare Register COMR Address pit7 bit6 5 bit4 bit3 bit2 bit bitO Initial value W W W W W W W W W Write only X Undefined While the interval timer is operating Specify an interval in
99. into this bit it is ignored This bit is set to 1 upon the termination of the flash memory automatic algorithm see Section 17 3 Starting the Flash Memory Automatic Algorithm The read modifier write RMW command always reads 1 from this bit WE Write enable bit RDY ReaDY bit Bit for write enabling flash memory areas When this bit is set to 1 a write instruction performed after a command sequence for a section from C000 to see Section 17 3 Starting the Flash Memory Automatic Algorithm is issued writes data into a flash memory area When this bit is set to 0 no write erase signals are generated This bit is used to start a command for writing data into or erasing data from flash memory It is recommended that this bit be set to 0 to prevent data from being incorrectly written into flash memory whenever there is no data to be written or erased Bit for status checking for writing data into or erasing data from flash memory No data can be written into or erased from flash memory while this bit is 0 However a read command reset command and suspend commands such as the sector erase suspend command can be accepted while this bit is 0 Unused bits Note The RDYINT and RDY bits cannot be changed at the same time Create a program so that decisions are Reading Writing for these bits have no effect made using one or the other of these bits Automatic algorithm Ter
100. is reset the bits of the PDR4 register are initialized to 1 Thus the output transistors become OFF input port mode and the pins become Hi Z Operation in stop mode When the pin state setting bit of the standby control register STBC SPL is set to 1 and when the stop mode is entered the pin becomes Hi Z because the output transistor is turned OFF regardless of the value existing on the DDR4 register in the bit position corresponding to the pin Input remains fixed to prevent leaks by input open Table 4 4 4 summarizes the operating modes of the pins of port 4 Table 4 4 4 Operating Modes of Pins of Port 4 Pinname Normal operation Normal operation sleep stop SPL 0 stop Normal operation sleep stop SPL 0 0 Stop SPL 1 P40 ANO to P43 AN3 ELLE purpose I O port may also serve I O BEEN for peripherals SPL Pin state setting bit of standby control register STBC SPL Hi Z High impedance 93 CHAPTER 4 I O PORTS 4 5 Port 5 Port 5 is a general purpose I O port and may also serve the input output for peripherals The pins of this port can be used for peripherals or normal port function that can be selected according to the setting of the bit corresponding to the pin on a specific register This section explains the general purpose I O function of the port This section also describes port 5 concerning to the structure pins a block diagram of pins and associated registers B Stru
101. mode an interrupt request is generated In this case if square wave output is allowed the corresponding output control circuit inverts the output of the square wave output pin Timer 0 1 data registers TDRO TDR1 and TDR are used to set the data to be compared with each 8 bit counter value at write Timer 0 1 control registers TCRO TCR1 TCRO and 1 are used to select functions allow and prohibit operations control interrupts and check interrupt states 8 16 bit capture timer counter interrupt IRQ3 If the interrupt request output is allowed when the counter value equals the value set in the data register in the interval timer or counter function an IRQ3 interrupt request is generated In timer 0 for the 8 bit mode or in the 16 bit mode the interrupt request output is allowed when TCRO TOIEN 1 In timer 1 for the 8 bit mode the interrupt request output is allowed when TCR1 1 8 16 bit capture counter interrupt IRQ4 If the interrupt request output is allowed each time a capture input edge is detected an IRQ4 interrupt request is generated In timer 0 for the 8 bit mode or in the 16 bit mode the interrupt request output is allowed when TCCR TCEN 1 Capture data registers TCPL TCPH TCPL and TCPH store the number of events detected in the capture mode When capture data is read in the timer mode the counter value is also read Timer output control register TCR2 T
102. not change this bit state and does not affect other operations Note The external interrupt enable bits of the external interrupt 2 control register EIE2 IE20 to IE27 may disable external interrupt inputs Interrupt requests continue to be generated and issued to the CPU until the IF20 bit is cleared to 0 IF20 External interrupt request flag bit 252 CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT 2 LEVEL 11 5 Interrupt of External Interrupt Circuit 2 An L level input signal input to one of the external interrupt pins triggers external interrupt circuit 2 to generate an interrupt m interrupt during the Operation of External Interrupt Circuit 2 When an L level signal is input to one of the external interrupt pins for which interrupt inputs are enabled the external interrupt request flag bit EIF2 IF20 is set to 1 and external interrupt circuit 2 generates and issues an interrupt request IRQA to the CPU Write 0 for the IF20 bit within the interrupt processing routine thus clearing the interrupt request When the external interrupt request flag bit IF20 is set to 1 external interrupt circuit 2 generates the interrupt request even if external interrupt inputs to the pin are set to disabled by the bit corresponding to the pin among the interrupt enable bits IE20 to IE27 of the external interrupt 2 control register EIE2 until the IF20 bit is cleared Therefore the IF20 bit must always be cleared If the
103. of data direction register 3 Address of serial mode register Address of serial data register Address of serial UART selection register Defines the interrupt request flag bit Defines the serial I O transfer start bit Address of interrupt request setting register 4 DATA SEGMENT Sets an interrupt vector CODE SEGMENT The stack pointer SP etc is already initialized Sets the P30 SCK and P32 SI pins to input Disables interrupts Stops serial I O transfer Sets the interrupt level to 1 337 CHAPTER 14 8 BIT SERIAL I O 338 MOV SMR 01001100B MOV SSEL 00000001B SETB SST f SETI Interrupt processing routine WARI CLRB SIOF PUSHW XCHW A T PUSHW A MOV A SDR SST SETB User processing POPW XCHW POPW RETI ENDS A A T Clears the interrupt request flag allows the interrupt request output sets shift clock input SCK prohibits serial data output SO selects the external shift clock and sets LSB first Selects the 8 bit serial I O Allows serial I O transfer Enables interrupts Clears the interrupt request flag Reads transfer data Allows serial I O transfer CHAPTER 15 BUZZER OUTPUT This chapter describes the functions and operation of the buzzer output 15 1 Overview of the Buzzer Output 15 2 Configuration of the Buzzer Output 15 8 Pin of the Buzzer Output 15 4 Buzzer Register BZCR 15 5 Program Example for Buzzer Output 339 CHAPTER 15 BUZZE
104. of the H width so as to be smaller than the value given by the cycle period setting bits of 12 bit PPG control registers 3 and 4 RCR23 SCL5 to SCLO and RCR24 SCL11 to SCL6 If the H width 15 equal to or greater than the cycle period H level outputs are always delivered through the PPG pin Resolution When the cycle period is set at 111111111111 FFFp a maximum width resolution of 1 4095 is obtained This resolution is reduced as the cycle period setting becomes smaller and limited to a minimum of 1 2 when the cycle period is set at 0000000000105 0021 Setting change during operation The width setting bits RCR21 HSC5 to HSCO and RCR22 HSCI11 to HSC6 and the cycle period setting bits RCR23 SCL5 to SCLO and RCR24 SCL11 to SCL6 are compared with the 12 bit counter for generating a frequency of 12 bit PPG waveforms If the set values given by these bits are changed to smaller values during the operation of the counter a counter overflow occurs which may extend the cycle period until synchronization with a count by the counter is detected again Similarly this may extend the H width until synchronization with a count by the counter is detected in the next cycle cycle period Figure 9 6 1 illustrates setting change during the operation of the 12 bit PPG timer 221 CHAPTER 9 12 BIT PPG TIMER Figure 9 6 1 Setting Change during 12 bit PPG Timer Operation Count by counter Overflow Cycle per
105. operation Figure 8 10 1 Error Occurring until the Count Operation is Started Counter value 0 1 cycle Count 0 Error cycle lt gt Counter start 198 Using only timer 0 in 8 bit mode When using only timer 0 of the 8 16 bit capture timer counter in the 8 bit mode set a value other than 111g in the count clock selection bits TCS12 TCS11 TCS10 of the timer 1 control register TCR1 Using timer 0 without setting 111 results in a malfunction Note on setting by program When using the 8 16 bit capture timer counter in the 16 bit mode set the count clock selection bits TCS12 TCS11 TCS10 of TCRI to 1115 Before using the counter values when the counter is in operation with 16 bit mode be sure to read the counter values twice and confirm that the values are valid Even if square wave output is initialized when the timer is in operation TCRO TSTRO 1 the output value is not modified The output state is initialized when the timer operation stops When the interrupt request flag bits TCCR CPIF TCRO TIFO TCR1 TIF1 are 1 and the interrupt request enable bits are allowed TCCR CPIEN TCRO TOIEN and TCR1 TITEN 1 return from an interrupt is impossible In this case clear the interrupt request flag bits TCCR CFCLR 1 TCRO TFCRO and TCR1 TFCRI 1 CHAPTER 8 8 16 BIT CAPTURE TIMER COUNTER When the counter operation stops according to the timer start bits TCRO TSTRO
106. ovpklv html CHAPTER 1 OVERVIEW m Package Dimension of FPT 34P M03 Figure 1 6 2 Package Dimension of FPT 34P M03 34 pin plastic SSOP Lead pitch 0 65 mm Package width x 6 10 x 11 00 mm package length Lead shape Gullwing Sealing method Plastic mold Mounting height 1 45 mm MAX Code P SSOP34 6 1x11 0 65 Reference FPT 34P M03 34 pin plastic SSOP Note 1 FPT 34P M03 Note 2 Note 3 Note 4 1 Resin protrusion Each side 0 15 006 Max 2 These dimensions do not include resin protrusion Pins width and pins thickness include plating thickness Pins width do not include tie bar cutting remainder 111 00 0 10 433 004 B pipa 0 17 0 08 007 001 HHHHEHHR AHHH AHHH S A Deme 6 10 0 10 8 10 0 20 m INDEX 240 004 319 008 1 2655 Mounting height C049 709 i oY i 0 25 010 HuHHuHHadHHEHHHH2HHHHEdd r A i Ova pi 0 65 0265 o 008 t 0 2495 6 0 10 004 009 0 50 0 20 0 1050 10 0203 008 004 004 0 60 0 15 Stand off U U 024 006 Tec ech cee ep ne ee 5 0 10 004 Dimension
107. pin can be read directly from the port 0 data register PDRO For pins INT20 to INT23 furthermore write 0 into A D enable register ADEN in the bits corresponding to the pins to use the pins for external interrupt inputs 251 CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT 2 LEVEL 11 4 2 External Interrupt 2 Flag Register EIF2 The external interrupt 2 flag register EIF2 is used to hold the interrupt state by flagging an interrupt request flag when a level interrupt is detected and then clearing the flag m External Interrupt 2 Flag Register EIF2 Figure 11 4 3 External Interrupt 2 Flag Register EIF2 Address 7 bit6 bits bit4 bit2 biti bito Initial value SS REESE ELT R W External interrupt request flag bit When being read When being written No interrupt request L level not detected R W Readable Writable z usan Interrupt request is generated No change in the bit does not L level detected affect other operations E Initial value This bit is cleared Table 11 4 3 Explanation of Functions of Each Bit in External Interrupt 2 Flag Register EIF2 Bit value is undefined when being read Unused bits The written value does not affect other operations When an L level signal is input to one of the external interrupt pins INT20 to INT27 for which external interrupt inputs are enabled this bit is set to 1 Writing 0 clears this bit and writing 1 does
108. port The value state of the pin is always input to the peripheral except during stop mode The value state of the pin can be read by reading the PDR3 register regardless of whether or not the peripheral is using the input pin 88 Operation when a reset is performed CHAPTER 4 I O PORTS When the CPU is reset the bits of the DDR3 register are initialized to 0 at which time the output transistors become OFF input port mode and the pins become Hi Z However CPU resets do not initialize the PDR3 register If a pin is used as an output port after the reset reinitialize the PDR3 register to contain new output data in the bit position corresponding to the pin and then set the corresponding bit of the DDR3 register so that the pin will function as an output port Operation in stop mode When the pin state setting bit of the standby control register STBC SPL is set to 1 and when the stop mode is entered the pin becomes Hi Z because the output transistor is turned OFF regardless of the value existing on the DDR3 register in the bit position corresponding to the pin Table 4 3 4 summarizes the operating modes of the pins of port 3 Table 4 3 4 Operating Modes of Pins of Port 3 Pin name P30 UCK SCK to P33 EC P37 BZ PPG Normal operation sleep stop SPL 0 General purpose I O port may also serve I O for peripherals Stop SPL 1 P34 TO INT 10 to P36 INT12 General purpose I O port may also
109. pull up not MB89F202 F202RA At an output pull up resistor P ch of approximately 50 kQ 5 0 V not available for MB89F202 F202RA N ch open drain reset output Hysteresis input High voltage input tolerable in MB90F202RA Table 1 8 1 I O Circuit Types 2 2 Circuit Input enable 4 D Port Input enable 59 Resource CHAPTER 1 OVERVIEW Remarks CMOS output CMOS input Hysteresis input Resource input Pull up resistor optional E 1 Input enable CMOS output CMOS input Pull up resistor optional P70 to P72 are large current drive type Ji CC Open drain control L Analog input Ho A D enable TIT Input enable CMOS output CMOS input Analog input N ch open drain output available P40 to P43 are large current drive type N ch 77 ju Resource Analog input Input enable Input enable A D enable CMOS output CMOS input Hysteresis input Resource input Analog input Input enable 1 DH Port CMOS input CHAPTER 1 OVERVIEW CHAPTER 2 HANDLING DEVICES This chapter describes the precautions to be taken when handling general purpose one chip microcontrollers 2 1 Precautions on Handling Devices CHAPTER 2 HANDLING DEVICES 2 1 Precautions on Handling Devices This section des
110. register 1 Address of A D control register 2 Address of A D data register H Address of A D data register L Enables the A D input pin Defines the ANO analog input Enables the ANO analog input Defines the interrupt request flag bit Defines the conversion in progress flag bit Defines the bit for activating A D conversion software activation Defines the bit for enabling continuous activation CODE SEGMENT Sets the PA0 ANO pin to the analog input Disables interrupts Enables the ANO pin Disables continuous activation Loop for verifying that the A D converter is stopped Selects analog input channel 0 ANO clears the interrupt request flag does not perform software activation Disables the interrupt request output selects A D conversion functions and selects software activation Enables interrupts Activates software Loop for waiting for completion of A D conversion at about 12 2 us 12 5 MHz Clears the interrupt request flag 277 CHAPTER 12 A D CONVERTER MOV A ADDL Reads A D conversion data low order 8 bits MOV A ADDH Reads A D conversion data high order 2 bits ENDS END 278 CHAPTER 13 UAHT This chapter describes the functions and operations of UART 13 1 Overview of UART 13 2 Configuration of UART 18 3 Pins of UART 13 4 Registers of UART 13 5 Interrupt of UART 13 6 Operations of UART Functions 13 7 Program Example for UART 279 CHAPTER 13 UART 13 1 Ove
111. remain unchanged The initial value specified after the reset operation is undefined 27 CHAPTER 3 CPU 28 Temporary Accumulator T The temporary accumulator is an auxiliary 16 bit arithmetic operation register It handles arithmetic operations using data in the accumulator When arithmetic operations in the accumulator A are handled in word units 16 bits data in the temporary accumulator is handled in word units Otherwise it is handled in byte units 8 bits When arithmetic operations are handled in byte units only the lower 8 bits TL in the temporary accumulator are used the upper 8 bits TH are not used When an MOV instruction is used to transfer data into the accumulator A data stored in the accumulator is automatically transferred to the temporary accumulator before it is transferred For data transfer in byte units the upper 8 bits of the temporary accumulator TH does not change The initial value of the temporary accumulator specified after the reset operation is undefined Index register IX The index register is a 16 bit register that stores an index address The index register is used together with a 1 byte offset 128 to 127 It generates a memory address for accessing data by adding a sign extended offset to the index address The initial value of the index register specified after the reset operation is undefined e Extra pointer EP The extra pointer is 16 bit register Data in the
112. the function and operation of an external interrupt circuit 2 level 11 1 Overview of External Interrupt Circuit 2 11 2 Configuration of External Interrupt Circuit 2 11 3 Pins of External Interrupt Circuit 2 11 4 Registers of External Interrupt Circuit 2 11 5 Interrupt of External Interrupt Circuit 2 11 6 Operations of External Interrupt Circuit 2 11 7 Program Example for External Interrupt Circuit 2 243 CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT 2 LEVEL 11 1 Overview of External Interrupt Circuit 2 External interrupt circuit 2 detects the predetermined level of a signal input to any of the eight external interrupt pins and generates and issues an interrupt request to the CPU m Functions of External Interrupt Circuit 2 Level Detection External interrupt circuit 2 functions to detect an L level signal input to any of the external interrupt pins and generate and issue an interrupt request to the CPU thereby enabling recovery from standby mode and a transition to normal operating state main clock operation mode e External interrupt pins Eight pins POO INT20 AN4 to PO3 INT23 ANT7 PO4 INT24 to PO7 INT27 e External interrupt triggering Input of an L level signal to one of the above external interrupt pins triggers an external interrupt Interrupt control An external interrupt 2 control register EIE2 enables or disables external interrupt inputs Interrupt flag Detection of the L level is indicated by an
113. the register to which the value compared with the counter value is to be set When the settings written to this register match the counter value the counter is cleared and 1 is set to the interrupt request flag bit CNTR TIR 1 If a value is written to the COMR register while the counter is operating the value takes effect at the next cycle after detection of a match Note The settings of the COMR register while the interval timer is operating can be calculated using the following formula The gear function however affects the instruction cycle COMR register value interval count clock cycle x instruction cycle 1 145 CHAPTER 7 8 BIT PWM TIMER While the PWM timer is operating Specify the H level width of a pulse in the register to which the value that is compared with the counter value is to be set Until the settings written to this register match the counter value H is output from the PWM pin When a match is found L is output until the counter value overflows If a value is written to the COMR register while the counter is operating the value takes effect at the next cycle after overflow Note The settings and cycle of the COMR register while the PWM timer is operating can be calculated using the following formula The gear function however affects the instruction cycle COMR register value duty ratio 96 x 256 PWM wave cycle count clock cycle x instruction cycle x 256 146 C
114. the stack area due to multiple interrupts or subroutine calls make arrangements so that the stack area does not overlap with the data area and general purpose register area containing other data CHAPTER 3 CPU 3 5 Reset There are four sources of reset e External reset Software reset e Watchdog reset Power on reset Oscillation stabilization wait time is not applied in some operating modes when a reset occurs or in some option settings m Reset Sources Table 3 5 1 Reset Sources Reset source Reset condition External reset The external reset pin is L level Q is written into the software reset bit in the standby control register STBC Software reset RST Watchdog reset The watchdog timer overflows Power on reset Power is turned on External reset External reset occurs when L level is input to the external reset pin RST When the reset pin becomes H level the external reset 1s cancelled For external reset when power is turned on or in stop mode the reset operation is performed after oscillation stabilization wait time is up or the external reset is cancelled The external reset pin functions as the reset output pin in accordance with option settings Software reset Software reset generates a 4 instruction cycle reset by writing into the software reset bit in the standby control register STBC RST Software reset does not wait until oscillation stabilization wai
115. the timer 1 value in the 8 bit mode of the 8 16 bit capture timer counter or the interval timer value interval timer function or counter value counter function of the higher 8 bits in the 16 bit mode Timer 1 Data Register TDR1 The values set in this register are compared with those set in the counter Figure 8 4 7 shows the bit structure of timer 1 data register TDR1 Figure 8 4 7 Timer 1 Data Register TDR1 Address bit7 bit6 bit5 bit4 bit2 bit bit0 Initial value RAW RW RW RW RW RW RW RW R W Readable Writable X Undefined 8 bit mode timer 1 The values set in this register are compared with those set in the counter When the interval timer function is used an interval timer value is set When the counter function is used the count value to be detected is set The values in TDRI are reset in loaded to the comparator data latch when they match the values in the counter or when the count operation is started The values written to TDR1 when the counter is operating become valid from the next cycle after match detection Note The values set in TDR1 when the interval timer is operating can be calculated from the expression shown below However the instruction cycle is affected by the clock mode and gear function Values set in TDR1 interval time count clock cycle x instruction cycle 1 180 CHAPTER 8 8 16 BIT CAPTURE TIMER COUNTER 16 bit mode The values in TDR1 are comp
116. to control the output pin is set to the dedicated pin CNTR OE 1 the P50 PWM pin automatically functions as an output pin regardless of the value of the port 5 data direction register DDRS 610 and as the PWM pin m Block Diagram of the Pin Related to the 8 bit PWM Timer Figure 7 3 1 Block Diagram of the Pin Related to the 8 bit PWM Timer Cpe Stop mode SPL 1 Pull up resistor PDR read E M EA Resource output Resource i outputis enabled PDR read At read modity write Output latch PDR write P50 PWM 2 a 5 c E E DDR write Stop mode SPL 1 DDR read PUL read PUL write 141 CHAPTER 7 8 BIT PWM TIMER 7 4 Registers of 8 bit PWM Timer This section describes the registers related to the 8 bit PWM timer m Registers Related to the 8 bit PWM Timer 142 Figure 7 4 1 Registers Related to the 8 bit PWM Timer CNTR PWM control register Address bit7 bit6 bit5 bit4 bit3 bit2 biti bitO Initial value 00224 P TX ee 0 000000 R W RAV RW RW RW RW COMR PWM compare register Address bit7 bit6 bit5 bit4 bit3 bit2 bit bito Initial value Lf T T T T T T xxx W W W Readable Writable W _ Write only Unused Undefined Note Because the PWM compare register COMR is a write only register an instruction to operate bits cannot be used CHAPTER 7 8 BIT PWM TIMER 7 4 1 PWM Control Register CN
117. to the BZ pin Outputs 212 3 052 kHz to the BZ pin Outputs 211 6 104 kHz to the BZ pin Outputs 210 12 21 kHz to the BZ pin 1 Aala lt j Readable Writable Unused Initial value Oscillation frequency 872 Bzi 20_ ft oe 343 CHAPTER 15 BUZZER OUTPUT Table 15 4 1 Functions of Each Bit in Buzzer Register BZCR Bit name Function Undefined at read Unused bits No effect on the operation at write Select a buzzer output and enable the output If 000g is set to these bits the buzzer output is disabled and the pin works as a general purpose port P37 or as the 12 bit PPG output PPG With the BZ2 BZ1 and BZO exception of 0005 the pin becomes the buzzer pin B zzerselection its and outputs a square wave Even if the pin has been functioning as the 12 bit PPG output setting a value other than 000g causes the pin to work as the BZ pin prior to its operation as the PPG pin For the buzzer output four kinds of time base timer divided cycle outputs are supplied 344 CHAPTER 15 BUZZER OUTPUT 15 5 Program Example for Buzzer Output This section shows an program example for buzzer output m Program Example for Buzzer Output Processing specificatio n Suppose that the buzzer output of 3 052 kHz is output to the BZ pin and then the buzzer output is cut off If is selected when the
118. used for recovery from stop mode set the edge polarity selection bits to 00g and the interrupt enable bits to 0 Notes When edge detection OFF is selected and set with edge polarity selection bits the occurring input is held as is before entry to the internal edge detecting circuit If edge is selected during the edge detection OFF state edge detection may be performed unconditionally with the external interrupt request flag bit set to 1 When interrupts are set enabled EIC1 EIC2 EIEO to EIE2 1 after the release from the reset state clear the appropriate external interrupt request flag bit EIRO to EIR2 0 at the same time If the external interrupt request flag bit is 1 with the interrupt request enable bit containing a value indicating enable state a return from the interrupt processing is not possible Always clear the external interrupt request flag bit within the interrupt processing routine For edge selection during the edge detection OFF state specify an edge or edges when interrupt request outputs are disabled and then clear the external interrupt request flag bit Regardless of the value of the appropriate interrupt request enable bit EIEO to EIE2 the external interrupt request flag bit is set to 1 whenever edge polarity matching is detected Only external interrupt circuits 1 and 2 can execute a release from stop mode by an interrupt With the external interrupt request flag bit being set to 1 when the i
119. 0 is used to hold or clear an interrupt request signal Trigger causing external interrupt circuit 2 to generate an interrupt e IRQA When an L level signal is input to any of the external interrupt pins INT20 to INT27 and the external interrupt input enable bit corresponding to the pin is 1 external interrupt circuit 2 generates an interrupt request 245 CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT 2 LEVEL 11 3 Pins of External Interrupt Circuit 2 This section describes the pins associated with external interrupt circuit 2 and illustrates a block diagram of circuitry terminating at the pins with reference to the registers and interrupt triggering Pins Associated with External Interrupt Circuit 2 The pins associated with external interrupt circuit 2 are eight external interrupt pins P00 INT20 AN4 to P03 INT23 AN7 These external interrupt pins function as external interrupt input pins hysteresis input and as the pins of the general purpose I O port and analog inputs The POO INT20 AN4 to PO3 INT23 ANT pins function as external interrupt input pins INT20 to INT23 if set to function as an input port by the corresponding bits of the port 0 data direction register DDRO if set to be enabled for external interrupt inputs ADEN 0 by the corresponding bits of the A D enable register ADEN and if external interrupt inputs are enabled EIE2 IE20 to IE27 1 by the external interrupt 2 control register EIE2 When set
120. 0 ANA SETI Enable interrupts Interrupt processing routine WARI MOV EIE2 00000000B Disable external interrupt inputs to pin INT20 AN4 CLRB IF20 Clear external interrupt request flag 256 CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT 2 LEVEL PUSHW A XCHW PUSHW User processing POPW A XCHW POPW A RETI ENDS END 257 CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT 2 LEVEL 258 CHAPTER 12 A D CONVERTER This chapter describes the functions and operations of the A D converter 12 1 Overview of A D Converter 12 2 Configuration of A D Converter 12 3 Pins of A D Converter 12 4 Registers of A D Converter 12 5 Interrupt of A D Converter 12 6 Operations of A D Converter Functions 12 7 Notes on Using A D Converter 12 8 Program Example for A D Converter 259 CHAPTER 12 A D CONVERTER 12 1 Overview of A D Converter An A D converter which is of a 10 bit successive approximation type selects an input signal from eight channel analog inputs The A D converter can be activated with software an internal clock or the output of an 8 16 bit capture timer counter 16 bit mode m A D Conversion Functions 260 These functions convert the analog voltage input voltage input from an analog input to 10 bit digital values Ananalog input can be selected from eight channels The conversion speed
121. 0 and TSTR1 0 and the interrupt source occurs at the same time the interrupt request flag bits TCRO TIFO and TCRI TIF1 are not set In the capture mode no external clock can be selected set the count clock bits TCS12 TCS11 and 1 TCS10 to a value other than 1115 Note on using interrupts If the compare register value is 0000g or 00g the 8 16 bit capture timer counter cannot generate interrupts For this reason when using interrupts set a value greater than or equal to 0001 or Oly The 8 16 bit capture timer counter cannot generate interrupts if the capture counter function detects the 0000y or 00g width 199 CHAPTER 8 8 16 BIT CAPTURE TIMER COUNTER 8 11 Program Example for 8 16 bit Capture Timer Counter This section provides program examples of the 8 16 bit capture timer counter m Program Example of Interval Timer Function Processing specifications Inthe 8 bit mode only timer 0 is used to generate a 20 ms interval timer interrupt When the interval time has elapsed the square wave to be inverted is output to the TO pin At 12 5 MHz oscillation Fey value whose interval time becomes 20 ms at the maximum gear speed 1 instruction cycle 4 Fcp is shown below The count clock is 256tiysr of the internal count clock TDRO value 20 ms 256 x 4 12 5 MHz 1 244 F4y Coding example TCCR EQU TCR EQU TCRO EQU TCR2 EQU TDRI EQU TDRO EQU T
122. 1 Specifying procedure Specify when ordering Specify by part number masking Selection of initial value of main clock Selectable Fixed to 218 Foy Fixed to 2 8 Foy oscillation settling time with Foy 12 5 MHz 01 2 Fc Approx 1 31 ms 10 2 7 Approx 10 5 ms 11 218 Approx 21 0 ms Reset pin output Selectable With reset output With reset output With reset output Without reset output Power on reset selection Selectable With power on reset With power on reset With power on reset Without power on reset Foy Main clock scillation frequency Initial value to which the oscillation settling time bit SYCC WT1 WTO in the system clock control register is set 400 APPENDIX D Programming EPROM with Evaluation Chip This section describes how to program EPROM with evaluation chip m Programming EPROM with Evaluation Chip EPROM for use 32 Kbyte EPROM equivalent to MBM27C256A DIP 28 Figure D 1 Memory Map of the Evaluation Chip In normal operation Corresponding address on mode the ROM programmer 0000u 0080 RAM 512bytes 0280u Unavailable 8000H gt 00004 Program area Program area PROM 32Kbytes PROM 32Kbytes Programming EPROM 1 Make the MBM27C256 equivalent setting for the EPROM programmer 2 Load the program data to the area from 0000 to 7FFFy of the EPROM programmer 3 Program the area from 0000 to 7 with the EPROM prog
123. 1 Timer 0 timer 1 d or ameng timer 1 Interrupt request flag bit TCRO TIFO TCR1 TIF1 TCRO TIFO TCCR CPIF Interrupt flag clear bit TCRO TFCRO TCRI TFCR1 TCRO TFCRO TCCR CFCLR Interrupt request enable bit TCRO TOIEN TCR1 THEN TCRO TOIEN TCCR CPIEN Interrupt cause The values in TDRO match those in the 8 bit counter The values in TDR1 match those in the 8 bit counter The values in TDRO and 1 match those in the 16 bit counter A capture edge is detected In the 8 bit mode timer and timer 1 independently generats the interrupt request for 8 16 bit capture timer counter In the 16 bit mode timer O generates the interrupt request All basic operations are the same Timer 0 interrupt operation in the 8 bit mode is explained here Timer 0 interrupt operation in the 8 bit mode The counter value is incremented according to the selected count clock starting at 005 When the counter value matches the value set in the comparator data latch timer 0 data register TDRO corresponding to the timer 0 data register the compare match detection flag bit TCRO TIFO is set to 1 In this case when the interrupt request flag bit is allowed when TCRO TOIEN 1 timer 0 generates an interrupt request IRQ3 to the CPU Set the TFCRO bit to 1 and clear the interrupt request with the interrupt processing routine When the counter value matches the value set in
124. 4 5 7 Program Example for Time base Timer sse nennen enn 125 CHAPTER S WATCHDOG TIMER 127 6 1 Overview of Watchdog Timer 128 6 2 Configuration of Watchdog Timer sssssssssssssseseseneee nennen nnn nennen 129 6 3 Watchdog Control Register WDTC 130 6 4 Operations of Watchdog Timer Functions ssssssssssssseseeeeeeen nennen nennen 131 6 5 Notes on Using Watchdog Timer a 132 6 6 Program Example for Watchdog Timer ERSS 133 vi CHAPTER 8 BITPWM TIMER uiuis canet aids pu Ev nea cuis nan ada rcv in eva og urb 135 7 1 Overview of 8 bit PWM Timer 136 7 2 Configuration of 8 bit PWM Timer tenentes 139 7 3 Pin of 8 bit PWM TIMET ien eee SUID 141 7 4 Registers of 8 bit PWM Timer 142 7 4 1 PWM Control Register CNTR nennen sinn nennen 143 7 4 2 PWM Compare Register sessi nnns 145 7 5 Interrupt 8 0 PYM ein Dette eere Dee e eee eset Costi ds 147 7 6 Opera
125. 4 2 3 Functions of Port 0 Registers Register When being When being written Address Initial value name read Output latch of 0 is set and Pin state is 5 L level is output to the pin L level Port 0 data in output port mode XXXXXXXXpg register PDRO Output latch of 1 is set and Pin state is MS level is output to the pin H level in output port mode Output transistor operation is disabled and the pin is set Port 0 data Read to serve as an input pin direction prohibited 000000005 register DDRO write only Output transistor operation is enabled and the pin is set to serve as output pin R W Readable Writable W Write only X Undefined Port 0 pull up setting register PULO The bits of the pull up setting register correspond to the pins of port 0 in one to one correspondence When the pull up resistor is selected by using the pull up setting register the pin will be at H level pull up state instead of Hi Z during stop SPL 1 During a reset however the pull up is invalid and the pin remains at Hi Z Figure 4 2 2 shows the pull up resistor settings assigned to the values of the bits of the port 0 pull up register Figure 4 2 2 Pull up Resistor Settings PULO Address bit bits bit3 bit2 biti bito Initial value 00704 Puto7 eutoe PuLos Putos PuLos Putoz Puto Putoo 000000008 RW RW RW RW RW RW RW RW
126. 4 Oscillation e 17 stabilization scm wri Wro Csi cso System clock control register SYCC FcH Oscillation frequency tnst Instruction cycle CHAPTER 3 CPU Oscillator Oscillation circuit that halts oscillation in stop mode System clock selector Selects one of four frequency divided source clocks to be supplied to the clock control circuit Clock controller Controls the operating clock supplied to the CPU and peripheral circuits according to the active RUN mode and standby mode sleep stop It also stops supply of the clock to the CPU until the clock supply stop signal for the oscillation stabilization wait time selector is cancelled Oscillation stabilization wait time selector Selects one of three oscillation stabilization wait time periods generated by the time base timer according to the standby mode or a reset then outputs the clock supply stop signal to the CPU by using the selected time period System clock control register SYCC Selects the clock speed and oscillation stabilization wait time setting then checks the clock state Standby control register STBC Controls transition from active RUN mode to standby mode pin state settings at stop mode and software reset 55 CHAPTER 3 CPU 3 6 3 System Clock Control Register SYCC The system clock control register SYCC manages clock settings such as selection of the clock speed and oscillation stabilization wai
127. 50 bit2 FFFO FFFlg ILR2 007C gy L61 bit5 L60 bit4 FFEEq 303 CHAPTER 13 UART 13 6 Operations of UART Functions UART supports four types of operating mode Mode 0 mode 1 and mode 3 are general serial transfer mode in which any data length can be selected in the range of 6 bits with parity used to 9 bits without parity used See Table 13 1 1 Transferred Data Format UART can handle data in the NRZ Non Return to Zero format only Data to be transferred always begins with the start bit L level specified number of data bits are transferred with LSB first then data transfer is ended with the stop bit H level Figure 13 6 1 shows the relationship between the transmit receive clock and transferred received data when operating mode 0 without parity used two stop bits synchronous transfer mode and transferred data 01001101 8 bits are specified Note that Figure 13 6 1 does not apply to the relationship between the serial clock and serial I O signal in asynchronous transfer mode Figure 13 6 1 Transferred Data Format Transmit receive clock SJUUU UU UU UL Lae Data to be transmitted received Ee ep OO START LSB MSB STOP STOP 304 CHAPTER 13 UART m Theory of Operation for Operating Mode 0 1 2 and 3 In operating mode 0 1 2 or 3 operates as a general serial communication function Figure 13 6 2 shows the settings required in UART operating mode 0
128. 6 bit5 bit4 bits bit bitt bit0 Initial value Iss R W SSEL Serial switch bit Sets UART R le Writabl 0 Sets UART O RAN Readable ileal 1 Sets 8 bit serial VO i Unused Initial value Table 13 4 5 Description of the Serial Switch Register SSEL Bits Bit name Description The values read out from these bits are undefined Unused bits Writing values to these bits does not affect any operations SSEL When this bit is 0 UART is used Serial switch bit When this bit is 1 8 bit serial I O is used 301 CHAPTER 13 UART Figure 13 4 10 Block Diagram of Serial Switch Register Internal data bus 8 bit serial I O Selector H Pin P30 UCK SCK Q O Pin P31 UO SO P Selector 302 CHAPTER 13 UART 13 5 Interrupt of UART UART supports the interrupt related error flag bit ORFE received data flag bit RDRF and transmitted data flag bit TDRE and the following interrupt sources When received data is sent from the reception shift register to the serial input data register SIDR Reception interrupt When transmitted data is sent from the serial output data register SODR to the transmission shift register Transmission interrupt Transmission Interrupt When the SSD register is read and the output data is written into the SODR register the data written into
129. 89F202 F202RA P61 P60 are input port e Port 7 General purpose I O port Table 4 1 1 lists the functions of the ports and Table 4 1 2 lists the register of ports Table 4 1 1 Functions of Ports Output Pin name form POO INT20 Hysteresis ANA to CMOS PO7 INT27 analog CMOS push pull P30 UCK SCK to P37 BZ PPG CMOS hysteresis CMOS CMOS push pull analog or N ch open drain P40 ANO to P43 AN3 CMOS CMOS hysteresis push pull CMOS CMOS push pull hysteresis or N ch open drain CMOS 76 Table 4 1 2 Registers of Ports Register name Port 0 data register PDRO Read Write Address CHAPTER 4 I O PORTS Initial value XXXXXXXXp Port 0 data direction register DDRO 000000005 Port 0 pull up setting register PULO 000000005 Port 3 data register PDR3 XXXXXXXXp Port 3 data direction register DDR3 000000005 Port 3 pull up setting register PUL3 000000005 Port 4 data register PDR4 CODD Port 4 data direction register DDR4 0000p Port 4 output form setting register OUT4 Port 5 data register PDR5 Port 5 data direction register DDR5 Port 5 pull up setting register PULS Port 6 data register PDR6 2 Port 6 data direction register DDR6 Port 6 pull up setting register PUL6
130. A 1234 2 7 A6H 34n 384 General purpose Register Addressing The addressing which is indicated by Ri in the instructions list is used for accessing the register bank of the general purpose register area In this addressing the higher one byte of the address is fixed to 01 The lower one byte is generated from the contents of RP register bank pointer and the lower three bits of the operation code The address is then accessed Figure B 1 6 shows an example Figure B 1 6 Example of General purpose Register Addressing MOV A R 6 RP o1 01 os gt 564 a ae Nr Immediate Addressing The addressing which is indicated by d8 in the instructions list is used when immediate data is required In this addressing the operand directly becomes the immediate data The specification of byte word is determined using the operation code Figure B 1 7 shows an example Figure B 1 7 Example of Immediate Addressing MOV A 56H LLL aja Vector Addressing The addressing which is indicated by vct in the instructions list is used for branching to a subroutine registered in the table In this addressing the operation code includes the vct information with the addresses generated on the basis of the correspondence with the contents of Table B 1 1 Table B 1 1 Vector Table Address Corresponding to vct Vector table address Jump destination higher address lower address FFCOg FF
131. AL I O 14 4 Registers of 8 Bit Serial I O Figure 14 4 1 shows 8 bit serial I O registers m Registers of 8 bit Serial I O Figure 14 4 1 8 bit Serial I O Registers SMR serial mode register Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bito Initial value 00394 000000008 R W R W R W R W R W R W R W R W SDR serial data register Address bit7 bit6 bit5 bit4 bit3 bit2 biti bitO Initial value C T T T T T T T J xxx R W R W R W R W R W R W R W R W R W Readable and Writable X Undefined Note When using a bit manipulation instruction make sure that the SST bit is 0 319 CHAPTER 14 8 BIT SERIAL I O 14 4 4 Serial Mode Register SMR The serial mode register SMR is used to allow and prohibit 8 bit serial I O operation select a shift clock set a transfer direction control interrupts and check interrupt states m Serial Mode Register SMR Figure 14 4 2 Serial Mode Register SMR Address bit7 bit6 bits bit4 bit3 bit2 bitO Initial value 00391 000000008 RAN R W RW RW RW RW RW RW Serial I O transfer start bit At read At write Serial I O transfer is stopped pirea osier is stopped or Serial I O transfer is in progress Serial I O transfer is started or allowed Transfer direction selection bit LSB first serial I O transfer starts at the lowest bit 1 MSB first serial I O transfer starts at the highest bit SCK pin Output Output
132. AM Before After written written MOVW 0081H A A 1234H 16 bit Operand Storage State When 16 bits are specified for operands in instructions upper bytes are also stored in addresses close to operation codes instructions and lower bytes are stored in the following addresses Operands that indicate memory addresses and 16 bit immediate data are handled in the same manner as stated above Figure 3 1 3 shows the locations of 16 bit data in instructions Figure 3 1 3 Location of 16 bit Data in Instructions Example MOV A 5678H Extend address MOV W A 1234H 16 bit immediate data lt b Processed through assembler XX XX 60 56 78 Extend address E4 12 34 16 bit immediate data 16 bit Data Storage State in Stack The upper byte of data for a 16 bit register put in the stack due to an interrupt is also stored with a lower address 26 3 2 Dedicated Register CHAPTER 3 CPU The dedicated register in the CPU consists of a program counter PC two arithmetic operation registers A and T three address pointers IX EP and SP and program status PS register The size of each register is 16 bits m Dedicated Register Configuration The dedicated register in the CPU consists of seven 16 bit registers Some registers allow only the lower 8 bits to be used Figure 3 2 1 shows the configuration of the dedicated register Initial value FFFDu Undefined Undefined Undefi
133. ARH1 0043 H XXXXXXXX R W R W R W R W R W R W R W R W R W Readable and Writable X Undefined Table 16 3 2 Functions of Higher Address Set Register WRARH WRARHO 1 byte registers that specify the higher addresses of memory being assigned They specify the addresses corresponding to the individual WRARHI wild register numbers 352 CHAPTER 16 WILD REGISTER FUNCTION 16 3 3 Lower Address Set Registers WRARLO and WRARL1 The lower address set registers WRARLO WRARL1 are registers where the lower byte of addresses to be corrected by the wild register function are set B Lower Address Set Register WRARL Figure 16 3 4 Lower Address Set Register WRARL Address bit7 bit6 bit5 bit4 bit3 bit2 bit bito Initial value WRARLO 00414 XXXXXXXX B R W R W R W R W R W R W R W R W WRARL1 0044 R W R W R W R W R W R W R W R W R W Readable and Writable X Undefined Table 16 3 3 Functions of Lower Address Set Register WRARL 1 byte registers that specify the lower addresses of memory being assigned They specify the addresses corresponding to the individual wild register numbers 353 CHAPTER 16 WILD REGISTER FUNCTION 16 3 4 A Address Comparison EN Register WREN The address comparison EN register WREN is a register that enables the operation of wild register function for the individual wild register numbers m Address Comparison EN Register WREN F
134. Bit Manipulation Instructions AO to A7 to AF MNEMONIC CLRB dir b SETB dir b Address bus 1 dir address dir address N42 Data bus Dir Data Data Next operation m Read Destination at Execution of a Bit Manipulation Instruction For some I O ports and interrupt request flag bits the read destination for read modify write is different from that for ordinary read O port at bit manipulation For some I O ports the value of the I O pin is read at ordinary read meanwhile the value of output latch is read at bit manipulation This is to prevent the other bits of the output latch from being accidentally changed regardless of the I O direction and pin state Interrupt request flag bit at bit manipulation The interrupt request flag bits work as flag bits for confirming an interrupt request at ordinary read meanwhile 1 is always read at bit manipulation This is to prevent the interrupt request flag bits from being written as 0 and accidentally clearing the flags at bit manipulation for another bit 391 APPENDIX B Overview of the Instructions B 4 F MC 8L Instructions List Table B 4 1 to Table B 4 4 list the instructions used by the F2MC 8L m Transfer Instructions Table B 4 1 List of Transfer Instructions 1 2 MNEMONIC MOV dir A MOV IX off A MOV ext A MOV EP A MOV Ri A Operation dir A A ext HA
135. Bit name Description Unused bits The values read out from these bits are undefined Writing values into these bits does not affect any operation PREN UART prescaler operation enable bit Enables disables operation of the prescaler that creates the UART reference clock by dividing the oscillation frequency When this bit is 1 the UART prescaler supplies the reference clock that corresponds to the frequency selected using the oscillation frequency selection bit to the baud rate generator When this bit is 0 the prescaler does not operate thus the internal baud rate generator cannot be used for data transfer or data receive purposes PR2 PRI PRO Clock divider selection bits Note The UART prescaler supplies to the internal baud rate generator the reference clock that corresponds to the divider selected using these bits The inside of UART is initialized when it is in synchronization transfer mode asynchronous transfer mode external clock mode or internal clock mode with the clock from the prescaler Therefore turn on the PREN bit PREN 1 to enable operation of the prescaler before using the UART functions 300 CHAPTER 13 UART 13 4 7 Serial Switch Register SSEL The serial switch register SSEL switches the P30 UCK SCK P31 UO SO and P32 UI SI pins between UART and 8 bit serial I O B Serial Switch Register SSEL Figure 13 4 9 Serial Switch Register SSEL Address bit7 bit
136. C Serial status and data register SSD Serial input data register SIDR Serial output data register SODR e Baud rate generator e Reception control circuit e Transmission control circuit e Clock divider selection register UPC UART prescaler Block Diagram of UART Figure 13 2 1 Block Diagram of UART Control bus Reception interrupt Received S byte counter detection circuit Transmission P30 UCK SCK clock Reception control Baud rate generator UART interrupt Transmission control circuit RIE Transmission interrupt TIE Transmitted byte counter Parity IRQ6 IRQ5 P31 UO SO Pin UART prescaler PREN Shift register Clock divider selection Serial input data register register SIDR UPC J Internal data bus Reception clock PR2 1 0 Completion of receipt of P32 UI SI m Pin i 2 Serial mode control register SMC Serial rate control register 284 Shift register y Serial output data register SODR gt Serial status and data register TP RP Control bus CHAPTER 13 UART Serial mode control register SMC The SMC register controls UART operating mode This register specifies the parity setting stop bit length operating mode data length and synchronous asynchronous mode and enables disables UART serial clock output and serial data output Serial rate control regist
137. CR2 is used to allow and prohibit square wave output and select timer 0 output timer 1 output 167 CHAPTER 8 8 16 BIT CAPTURE TIMER COUNTER 8 3 Pins of 8 16 bit Capture Timer Counter This section provides pins of 8 16 bit capture timer counter and a block diagram for these pins Pins of 8 16 bit Capture Timer Counter 8 16 bit capture timer counter pins include P33 EC and P34 TO INT10 e P33 EC The P33 EC pin shares functions of the general purpose I O port P33 and the external clock for the timer or capture input pin EC EC When external clock input is selected TCRO TCS02 TCSO1 TCSOO 111 in timer 0 for the 8 bit mode or in the 16 bit mode the clocks input to this pin are counted In the capture function this pin is also used as an input pin When using this pin as the EC pin set O in the port data 3 direction register DDR3 bit3 and set the output transistor to OFF to enable the EC pin to be used as an input port P34 TO INT10 pin The P34 TO INT 10 pin shares functions of the general purpose I O port P34 and the square wave output pin for the timer TO It also shares a function of the input pin for external interrupt 1 INT 10 TO In timer 0 or 1 switching allowed for the 8 bit mode or in the 16 bit mode a square wave is output from this pin If square wave output is enabled TCR2 PEN 1 the P34 TO INT10 pin automatically functions as an output pin without reference to the port 3 direc
138. Clg FFC2 FFC3y FFC4g FFC5g FFC6q FFC7g FFC8j FFC9j FFCBy FFCCy FFCDy FFCE 385 APPENDIX B Overview of the Instructions Figure B 1 8 shows an example Figure B 1 8 Example of Vector Addressing CALLV 5 Conversion gt F F C PC FE DCH Relative Addressing The addressing which is indicated by rel in the instructions list is used for branching to the area of 128 bytes before or after the PC program counter In this addressing the contents of the operand with a sign are added to the PC The results are then stored in the PC Figure B 1 9 shows an example Figure B 1 9 Example of Relative Addressing BNE FEH 9ABC FFFE Old Pc 9 A B 5 New PC 9 AB In this example the control jumps to the address holding the operation code of BNE causing an endless loop Inherent addressing This addressing which has no operand in the instructions list is used for performing an operation determined on the basis of the operation code In this addressing the operations differ depending on the instructions Figure B 1 10 shows an example Figure B 1 10 Example of Inherent Addressing NOP old PC New PC 386 B 2 Special Instructions This section describes the special instructions other than addressing m Special Instructions JMP By this instruction the control branches to PC
139. Control Register SRC The serial rate control register SRC controls the data transfer rate baud rate in asynchronous transfer mode The SRC selects the input clock and sets the transfer rate for the dedicated baud rate generator Serial Rate Control Register SRC 292 Address Figure 13 4 3 Serial Rate Control Register SRC bit bit6 bit5 bit3 bit2 biti bit0 Initial value RW RW RAW RW RW RW R W em Readable Writable Unused Initial value E RC2 RC1 RCO Baud rate selection bits Asynchronous us baud Synchronous us baud 0 0 1 _ 1646 0 1101 aaxsoo 32819 ee ee ptf ott aeos 2563 ptt 1r o 1 6625 pif 1 wov6o 287 Clock input selection bits 51 CSO Clock input CR bit Clock frequency divider NEUEM divider EE Synchronous External clock 1 PWMtimer output 9 6 o 1 68 Ex Dedicated baud 0 1 rate generator 1 Clock rate input selection bit CR J Effective only in asynchronous transfer mode SMC SMDE 1 0 1 16 of the clock input 1 64 of the clock input However when the dedicated baud rate generator is used CS1 and CSO 11g it is fixed at 1 8 CHAPTER 13 UART Table 13 4 2 Explanation of Functions of Each Bit in the Serial Rate Control Register SRC Bit name Description Unu
140. DE SEGMENT The stack pointer SP and others are assumed to have been initialized CLRI Disabling interrupts CLRB TPE Stopping the counter operation MOV ILR3 11110111B Setting the interrupt level level 1 MOV COMR 0F4H Comparison value with the counter value interval MOV CNTR 00101011B Enabling the output of the PWM Interval timer operation selection of 64 Starting the counter operation and enabling the output of interrupt requests SETI Enabling interrupts jM Interrupt program WARII CLRB TIR Clearing the interrupt request flag PUSHW A XCHW A T Saving A and T PUSHW A 157 CHAPTER 7 8 BIT PWM TIMER User processing POPW A XCHW A T Restoring A and T POPW A RETI ENDS 158 m Program Example of PWM Timer Functions Processing specifications CHAPTER 7 8 BIT PWM TIMER APWM wave with a duty ratio of 50 is generated The duty ratio is then changed to 25 Nointerrupt occurs When the count clock is 16 tjs of an internal count clock the cycle of the PWM wave is 16 x 4 12 5 MHz x 256 1 3107 ms which occurs when the top speed of the gear one instruction cycle 4 is obtained at an oscillation frequency of 12 5 MHz The COMR register value with a duty ratio of 5096 is shown below COMR register value 50 100 x 256 128 08045 Coding example CNTR EQU COMR EQU TPE EQU MOV 0022H 0023H CNTR 3 TP
141. DQ2 ssssssssssssssseseeeeee nenne 366 17 5 Detailed Explanation of Writing to Erasing Flash Memory 367 17 5 4 Setting The Read Reset State sse eee nennen nentes nennen 368 17 5 2 Writing Data uiuere ecd Re eee dee ee Pe PR ple dee EcL ee ee Dag 369 17 5 3 Erasing All Data Erasing Chips trito epe eoctr e tete EE EE HE GADNA HERE 371 17 6 Flash Security Feature 372 17 7 Notes on using Flash Memory ce eee ae A AGA TAAA 373 APPENDIX e 375 APPENDIX A Map i tt ine Pei t ttt teftes t tete ko iba citate Patet Cft det ote 376 APPENDIX B Overview of the Instructions 380 BM Addressing eene ea rote ea o rere 383 B 2 Special IMStruCtiOns ise e Ier aeg eee det id ib ena Lp deme Pere Ue er etr eny id 387 Bit Manipulation Instructions SETB and CLRB 391 B 4 F MC 8L Instructions List oerte emet Dog Gotta cuin ufo 392 B 5v Instructions Map teat er dele e qu BI d iim nie Ente fete eed ee brio 399 APPENDIX C Mask Options een feed epit dieta hee es 400 APPENDIX D Programming EPROM with Evaluation 401
142. DRO bit5 0 P05 2 1 25 0 POG INT26 INT26 EIE2 IE26 1 DDRO bit6 0 P06 2 1 26 0 PO7 INT27 INT27 EIE2 IE27 1 DDRO bit7 0 P07 EIE2 IE27 0 246 CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT 2 LEVEL m Block Diagram of Circuitry Terminating at the Pins Associated with External Interrupt Circuit 2 Figure 11 3 1 Block Diagram of Circuitry Terminating at the Pins Associated with External Interrupt Circuit 2 A D converter channel select enable bit To A D converter s analog input INT20 INT21 INT22 INT23 INT24 INT25 INT26 INT27 PDR read PDR read when read modify write is performed e ia 4 c c PUL write SPL Pin status setting bit of standby control register STBC Note 20 4 1 21 5 2 22 6 _ POS INT23 AN7 From external interrupt enable Stop mode SPL 1 PO4 INT24 i43 POS INT25 P06 INT26 P0O7 INT27 Pull up resistor POO INT20 AN4 P01 INT21 AN5 PO2 INT22 AN6 PO3 INT23 AN7 PO4 INT24 P07 INT27 When the ON setting of the pull up resistor is selected by the pull up setting register the pin state will be level pull up state rather than Hi Z during stop mode SPL 1 During a reset however the pull up is invalid and the pin remains at Hi Z 247 CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT 2 LEVEL Association between the Interrup
143. E COMR 80H CNTR 10011010B COMR 40H Address of the PWM control register Address of the PWM compare register Defining the bit to enable the counter operation CODE SEGMENT Stopping the counter operation Specification of the H level width of a pulse 5096 duty ratio PWM timer operation selection of 16 Starting the counter operation clearing the interrupt request flag Enabling the output of the PWM pin disabling the output of interrupt requests Changing the duty ratio to 25 Takes effect at the next cycle of the PWM wave 159 CHAPTER 7 8 BIT PWM TIMER 160 CHAPTER 8 8 16 BIT CAPTURE TIMER COUNTER This chapter describes the functions and operation of the 8 16 bit capture timer counter 8 1 Overview of 8 16 bit Capture Timer Counter 8 2 Configuration of 8 16 bit Capture Timer Counter 8 3 Pins of 8 16 bit Capture Timer Counter 8 4 Registers of 8 16 bit Capture Timer Counter 8 5 8 16 bit Capture Timer Counter of Interrupts 8 6 Explanation of Operations of Interval Timer Functions 8 7 Operation of Counter Functions 8 8 Functions of Operations of Capture Functions 8 9 8 16 bit Capture Timer Counter Operation in Each Mode 8 10 Notes on Using 8 16 bit Capture Timer Counter 8 11 Program Example for 8 16 bit Capture Timer Counter 161 CHAPTER 8 8 16 BIT CAPTURE TIMER COUNTER 8 1 Overview of 8 16 bit Capture Timer Counter The 8 16 bit capture timer counter consists of tw
144. EICI EIC2 Interrupt flag Detection of specified edge or edges is indicated by an external interrupt request flag bit of external interrupt 1 control registers 1 and 2 EIC1 EIC2 Interrupt request An interrupt request is generated according to the pin at which the input of the signal triggering an external interrupt is detected IRQO IRQ1 IRQ2 CHAPTER 10 EXTERNAL INTERRUPT CIRCUIT 1 EDGE 10 2 Configuration of External Interrupt Circuit 1 External interrupt circuit 1 comprises the following two blocks e Edge detecting circuits 0 to 2 e External interrupt control 1 registers 1 2 EIC1 EIC2 m Block Diagram of External Interrupt Circuit 1 Figure 10 2 1 Block Diagram of External Interrupt Circuit 1 EIC1 EIC2 P34 TO INT10 Edge detecting circuit 1 Edge detecting circuit 0 Selector Selector P35 INT 114 External interrupt 1 control register 1 EIR1 SL11 SL10 EIE1 EIRO 5101 5100 EIEO pu EIC1 Interrupt request IRQO Interrupt request IRQ1 P36 INT12 Internal data bus Edge detecting circuit 2 elector E External interrupt 1 control register2 EiR2 5121 5120 EIE2 EIC2 Interrupt request IRQ2 227 CHAPTER 10 EXTERNAL INTERRUPT CIRCUIT 1 EDGE Edge detecting circuits When the edge polarity of a signal input to one of the pins INT10 to INT12 for external interrupt circuit 1 matches the selected edge polarity for t
145. FUJITSU SEMICONDUCTOR CONTROLLER MANUAL CM25 10153 2E F MC 8L 8 BIT MICROCONTROLLER MB89202 F202RA Series HARDWARE MANUAL FUJITSU F MC 8L 8 BIT MICROCONTROLLER MB89202 F202RA Series HARDWARE MANUAL Be sure to refer to the Check Sheet for the latest cautions on development Check Sheet is seen at the following support page URL http www fujitsu com global services microelectronics product micom support index html Check Sheet lists the minimal requirement items to be checked to prevent problems beforehand in system development FUJITSU LIMITED PREFACE B Purpose of This Manual and Intended Reader B Trademark The MB89202 F202RA series was developed as one of the general purpose products of the F MC 8L family which contains original 8 bit one chip microcontrollers for use with ASICs application specific ICs The MB89202 F202RA series can be used in a wide range of products from consumer products to industrial products This manual explains the functions and operations of the MB89202 F202RA series for product development The F MC 8L Programming Manual contains details of the programming instructions Note F2MC an abbreviation for FUJITSU Flexible Microcontroller is a registered trademark of FUJITSU LIMITED The company names and brand names herein are the trademarks or registered trademarks of their respective owners B Structure of This Manual This manual consists of
146. HAPTER 7 8 BIT PWM TIMER 7 5 Interrupt of 8 bit PWM Timer An interrupt factor of an 8 bit PWM timer can be a match between the counter value and the PWM compare register value while interval timer functions are operating While the PWM timer functions are enabled an interrupt request does not occur m Interrupts while Interval Timer Functions are Enabled When the counter value is incremented from 00g using the selected count clock and matches the PWM compare register COMR value 1 is set to the corresponding interrupt request flag bit CNTR TIR At this time if the bit to enable an interrupt request is enabled CNTR TIE 1 an interrupt request IRQ9 to the CPU occurs Write 0 to the TIR bit using the interrupt handling routine to clear the interrupt request The TIR bit is set to 1 when the counter value matches the settings regardless of the value of the TIE bit Note When a match is found between the counter value and the COMR register value concurrently with the stop of the counter CNTR TPE z 0 the TIR bit is not set When the TIR bit is 1 if the TIE bit is changed from disabled to enabled changed from 0 to 1 an interrupt request occurs immediately m Register and Vector Table Related to the Interrupts of an 8 bit PWM Timer Table 7 5 1 Register and Vector Table Related to the Interrupts of an 8 bit PWM Timer Interrupt level setting register Address of vector table Interrupt name Register
147. IFO EQU ILRI EQU INT_V DSEG ORG IRQD DW ENDS CSEG CLRI MOV MOV MOV MOV 200 0019H 001AH 001BH 0020H 001CH 001DH TCRO 7 007BH ABS OFFFOH WARI ILR1 10111111B TCRO 01001010B TCR1 01000010B TDRO F4H Address of capture control register Address of timer 1 control register Address of timer 0 control register Address of timer output control register Address of timer 1 data register Address of timer 0 data register Defines the timer 0 interrupt request flag bit Address of interrupt request setting register DATA SEGMENT Sets an interrupt vector CODE SEGMENT The stack pointer SP etc is already initialized Disables the interrupt Sets the interrupt level to 2 Clears the timer 0 interrupt request flag increments the counter at a rising edge selects 256tpys7 and stops the operation Clears the timer 1 interrupt request flag prohibits interrupt request output sets a mode other than the 16 bit mode and stops the operation Sets the value interval time to be compared with the counter value MOV TCR2 00000010B MOV TCRO 10101011B SETI CLRB TIFO PUSHW A XCHW A T PUSHW A User processing POPW A XCHW A T POPW A RETI ENDS END CHAPTER 8 8 16 BIT CAPTURE TIMER COUNTER Outputs a square wave TO from the P34 pin Allows timer 0 interrupt request output clears the counter and starts the timer Enables the CPU interrupt Clears the int
148. Interrupt of the A D 272 Register and Vector Table Related to the Interrupts of an 8 bit PWM 147 Register Associated with Interrupt Generation by External Interrupt Circuit 1 and Vector Register Associated with Interrupt Generation by External Interrupt Circuit 2 and Vector Table ede eet eee 253 Registers Associated with External Interrupt Circuit 1 RR 231 Registers Associated with External Interrupt Circuit 2 edo eda dais ai perdue deviled ds 249 Stack Area for Interrupt Processing 42 Stack Operation at the Beginning of Interrupt Processing 41 Stack Operation at the End of Interrupt Processing P 41 Steps in the Interrupt Operation 37 Transition to Standby Mode and Interrupt 70 Transmission Interrupt eese 303 UART Interrupt Related Registers and Vector Table Addresses tete 303 Interrupt Enable Bits Association between the Interrupt Enable Bits for External Interrupt Circuit 2 and the External Interrupt Pins eeeeeeeeeees 248 Interrupt Level Setting Registers Configuration of the Interrupt Level Setting Registers ILRI to 36 Interrupt Requests Interrupt Requests from Peripheral Functions 34 Interval Timer Interrupts when the Interval Timer Function is Enabled
149. L read PUL write Note Pull up resistor P34 TO INT10 P35 INT11 P36 INT12 When the ON setting of the pull up resistor is selected by the pull up setting register the pin state will be H level pull up state rather than Hi Z during stop mode SPL 1 During a reset however the pull up is invalid and the pin remains at Hi Z CHAPTER 10 EXTERNAL INTERRUPT CIRCUIT 1 EDGE 10 4 Registers of External Interrupt Circuit 1 This section describes the registers associated with external interrupt circuit 1 m Registers Associated with External Interrupt Circuit 1 Figure 10 4 1 Registers Associated with External Interrupt Circuit 1 EIC1 External interrupt 1 control register 1 Address bit bit6 bith bit4 bit3 2 bit Initial value 0024 EIR1 EIRO 5101 5100 EIEO 000000008 RW RW RW RW RW RW RW RW _ INT11 INT10 EIC2 External interrupt 1 control register 2 Address X bit7 bit6 bit5 bit4 bit3 bit2 bit1 bitO Initial value 05 ElR2 5121 5120 2 0000 R W RW RW INT12 R W Readable Writable Unused 231 CHAPTER 10 EXTERNAL INTERRUPT CIRCUIT 1 EDGE 10 4 4 External Interrupt Control Register 1 EIC1 External interrupt control register 1 EIC1 comprises bits for edge polarity selection and interrupt control for the INT10 and INT11 external interrupt pins External Interrupt Control Register
150. M P 309 Serial Input 327 Serial Output 325 Stack Operation at the Beginning of Interrupt ProCesstigs entere elim 41 Stack Operation at the End of Interrupt Processing 41 Steps in the Interrupt 37 Theory of Operation for Operating Mode 0 1 2 and 3 305 Transmission Operations in Operating Mode is 0 1 2 306 When Bidirectional Serial I O Operation is Performed CITED 334 Operation Order Operation Order of the Wild Register Function ERE 356 Oscillation Stabilization Wait Time Oscillation Stabilization Time and Time base Timer Interr pts 121 Oscillation Stabilization Wait Time 60 71 Reset Sources and Oscillation Stabilization Wait Time 44 Other Other Instructions eeeeeeeeneeenen ne 398 ONES SP RO Tm 372 OUT Registers of Port 4 91 Overview Overview of the Instructions of the FFMC 8L Miet E LUTEA alo ue Re 380 Overview of the Reset 48 411 INDEX P P37 BZ PPG P37 BZ PPG Pin 342 Package Dimension Package Dimension of 32 6 10 Package Dimension of FPT 34P MO3 11 PDR Registers of Port 4
151. NT21 AN5 POO INT20 AN4 P43 AN3 P42 AN2 PAT AN1 P40 ANO 72 71 P70 N C P50 PWM P30 UCK SCK P31 UO SO P32 UI SI CHAPTER 1 OVERVIEW 1 6 Package Dimensions Two different packages are available for MB89202 F202RA series Figure 1 6 1 and Figure 1 6 2 show package dimensions m Package Dimension of DIP 32P M06 Figure 1 6 1 Package Dimension of DIP 32P M06 32 pin plastic SH DIP Lead pitch 1 778 mm Low space 10 16 mm Sealing method Plastic mold DIP 32P M06 a 32 pin plastic SH DIP DIP 32P M06 28 00 822 1 102 ore DOOM TI INDEX D Note 1 These dimensions do not include resin protrusion Note 2 Pins width and pins thickness include plating thickness 10 16 400 2003 FUJITSU LIMITED 032018S c 1 N 8 89 0 25 ur 350 010 A LL A 2 1 02 02 040 ons 4 707028 1 0 51 020 185 tos MIN 0 20 3 30 030 130202 VoM V Y T V u V 0 2755 E 01 103 1 778 070 0 48 212 D 212 1251022502010 01920 Dimensions in mm inches Note The values in parentheses are reference values Please confirm the latest Package dimension by following URL http edevice fujitsu com fj DATAS HEET ef
152. O operation in stop mode In stop mode as shown in Figure 14 8 5 the 8 bit serial I O stops the serial I O operation and suspends data transfer After stop mode has been released a transfer destination error occurs because operation is resumed halfway In this case initialize the 8 bit serial I O Figure 14 8 5 8 bit Serial I O Operation in Stop Mode External Shift Clock Clock for the next data 7 Oscillation stabilization t wait time Clear via Stop mode request program Interrupt request SO pin output Stop mode Transfer error occurrence STP bit 7 STBC register Stop mode release via external interrupt 331 CHAPTER 14 8 BIT SERIAL I O 8 bit serial I O operation at issuance of stop request during operation As shown in Figure 14 8 6 if operation is stopped SMR SST 0 during data transfer the 8 bit serial I O stops data transfer and clears the shift clock counter For this reason the transfer destination must also be initialized If serial output is in operation set the SDR again before restarting the 8 bit serial I O In this case when the external clock is input the SO pin output changes Figure 14 8 6 8 bit Serial I O Operation at Issuance of Stop Request during Operation External Shift Clock SCK input Clock for the next data SST bit SIOF bit SO pin output 332 CHAPTER 14 8 BIT SERIAL I O 14 9 Notes on Using 8 Bit Serial I O This section provides notes
153. PTER 14 8 BIT SERIAL I O 14 41 Program Example for 8 Bit Serial I O This section provides program example for 8 bit serial I O m Program Example for 8 bit Serial Output Processing Specifications The 8 bit serial output program outputs 8 bit serial data 555 from the SO pin of the 8 bit serial I O When serial I O transfer terminates an interrupt occurs The program resets transfer data with the interrupt processing routine and outputs it continuously The program operates in accordance with the internal shift clock This clock is output from the SCK pin If the shift clock is 32t ys7 when the maximum gear speed 1 instruction cycle 4 Fcp at the 12 5 MHz oscillation Fcp the transfer rate and interrupt cycle are as follows Transfer rate 12 5 MHz 4 32 97 7 kbps interrupt cycle 8 x 32 x 4 10 MHz 81 92 us Coding example SMR EQU 0039H SDR EQU 003AH SSEL EQU 003BH SIOF EQU SMR 7 SST EQU SMR 0 ILR4 EQU 007EH INTV DSEG ABS ORG OFFE2H Address of serial mode register Address of serial data register Address of serial UART selection register Defines the interrupt request flag bit Defines the serial I O transfer start bit Address of interrupt request setting register 4 DATA SEGMENT IRQC DW WARI Sets an interrupt vector INT_V ENDS i Main program CSEG CODE SEGMENT The stack pointer SP etc are alrea
154. R OUTPUT 15 1 Overview of the Buzzer Output For the buzzer output four kinds of output frequencies square waves can be selected The buzzer output may be used for the confirmation tone of key input and other tones m Buzzer Output Function 340 The buzzer output function is a function for outputting a signal square wave used for tones such as a confirmation tone For the buzzer output it is selectable whether to output one of four output frequencies or to disable the output As the buzzer output four kinds of divided frequency outputs are supplied from the time base timer Note The time base timer supplies clock for the buzzer output Therefore buzzer output will be affected when time base timer is cleared Table 15 1 1 lists the four kinds of output frequencies square waves specifiable for the buzzer output Table 15 1 1 Output Frequencies Clock supplier Buzzer output Square wave output at 12 5 MHz Fcp 2 1 526 kHz Fop 2 3 052 kHz time base timer Fcp 2 6 104 kHz 2 9 12 21 kHz Fox Oscillation frequency Note Calculation example of an output frequency If time base timer output 219 is selected in the buzzer register BZCR BZ2 1 BZ1 0 and BZO 0 and the oscillation Fcp is 12 5 MHz the output frequency being output from the BZ pin is calculated as follows Output frequency 210 12 5 MHz 1024 12 21 kHz CHAPTER 15 BUZZER OUTPUT 15 2
155. RF If the reception interrupt request is allowed the reception interrupt is generated When the RDRF bit has been checked in interrupt processing or the program and the received data has been stored into this register read the contents in this register after reading the SSD register then clear the RDRF flag When operating mode is 2 For both RDRF and ORFE these flags go on when data is fully transmitted or received with the final data bit D8 set to 1 and the stop bit at the end is detected However when the framing error occurs the flag goes on regardless of the final data bit An interrupt request to the CPU is generated when the flag goes on and the interrupt request is allowed 297 CHAPTER 13 UART 13 4 5 Serial Output Data Register SODR The serial output data register SODR sends out transmits serial data Serial Output Data Register SODR Figure 13 4 7 shows the configuration of the serial output data register bits Figure 13 4 7 Serial Output Data Register SODR Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bito Initial value om T T ot T TF ooo W W W W Write only X Undefined When transmission is enabled writing data to be transmitted into this register after reading the SSD register sends the data to be transmitted to the transmission shift register converts it into the serial format then outputs it from the serial data output pin UO pin When the tra
156. Serial status and data register 00100 1X Serial input data register XXXXXXXX Serial output data register XXXXXXXX Clock divided cycle selection register 0010 Vacancy A D control register 1 0000000 A D control register 2 0000001 A D data register H A D data register L XXXXXXXX 377 APPENDIX A I O Map Table A 1 I O Map 3 4 Address Register abbreviation Register name A D enable register Read write Initial value 00000000 Vacancy External interrupt 2 control register 1 00000000 External interrupt 2 control register 2 Vacancy Serial mode register 00000000 Serial data register XXXXXXXX Serial function switching register Vacancy WRARHO Higher address set register XXXXXXXX WRARLO Lower address set register 0 XXXXXXXX WRDRO Data setting register 0 XXXXXXXX WRARHI Higher address set register 1 XXXXXXXX WRARLI Lower address set register 1 XXXXXXXX WRDRI Data setting register 1 XXXXXXXX WREN Address comparison EN register WROR Wild register data test register Vacancy Port 6 data register Port 6 data direction register Port 6 pull up set register Port 7 data register 378 Port 7 data direction register Port 7 pull up set register
157. Sets timer 1 to 16 bit mode Clears the timer 0 interrupt request flag allows interrupt request output selects an external clock clears the counter starts the operation and increments the counter at a rising edge Enables a CPU interrupt Reads 16 bits from TDR1 and TDRO Reads 16 bits from TDR1 and and stores the old value in the T register Executes double read check and compares A with T Match and return XCHW A T INCW A CMPW A BNE READ 16 RET CLRB TIFO PUSHW A XCHW A T PUSHW A User processing POPW A XCHW A T POPW A RETI ENDS END CHAPTER 8 8 16 BIT CAPTURE TIMER COUNTER Old value 1 Jumps to re read when a mismatch is detected Restarts the count operation and begins counting 10 000 pulses Clears the interrupt request flag 203 CHAPTER 8 8 16 BIT CAPTURE TIMER COUNTER 204 CHAPTER 9 12 BIT PPG TIMER This chapter describes the functions and operation of a 12 bit PPG timer 9 1 Overview of 12 bit PPG Timer 9 2 Configuration of 12 bit PPG Timer Circuit 9 3 Pin of 12 bit PPG Timer 9 4 Registers of 12 bit PPG Timer 9 5 Operations of 12 bit PPG Timer Functions 9 6 Notes on Using 12 bit PPG Timer 9 7 Program Example for 12 bit PPG Timer 205 CHAPTER 9 12 BIT PPG TIMER 9 1 Overview of 12 bit PPG Timer The 12 bit PPG timer is a 12 bit binary counter enabling the selection of one of four types of internal count clocks The timer is capable of setting a
158. Switching The 8 bit serial I O and UART cannot be used simultaneously because they use the same pin For this reason the serial function switching circuit must be used to switch the 8 bit serial I O and UART For more information on the serial function switching circuit see Section 13 4 7 Serial Switch Register SSEL Selecting the 8 bit serial I O with this serial function switching circuit enables P30 UCK SCK to be used as the serial clock I O pin SCK of the serial I O and P31 UO SO to be used as the data output pin SO This selection also enables P32 UI SI to be used as the data input pin SI Note This chapter describes pin function switching and the register function etc on the assumption that the 8 bit serial I O is selected with the serial function switching circuit 314 CHAPTER 14 8 BIT SERIAL I O 14 2 Configuration of 8 Bit Serial I O Each 8 bit serial I O channel consists of the following four blocks e Shift clock control circuit Shift clock counter Serial data register SDR Serial mode register SMR m Block Diagram of 8 bit Serial I O Figure 14 2 1 Block Diagram of 8 bit Serial I O Internal data bus MSB first LSB first Shift direction gt gt Serial data register SDR D7 to DO P31 UO SO Output buffer Output allowance 2t inst 8t INST 32t INST Serial mode register SMR Overflow P30 UCK SCK Interrupt request IRQC Output buffer Shift clo
159. TBR 0 When the interval timer bit overflows the overflow interrupt request flag bit is set to 1 In other words interrupts are generated at specified intervals starting from when the counter is cleared Operations of Clock Supply Function The time base timer is often used to make oscillation stabilization wait time The oscillation stabilization time is measured from when the time base timer counter is cleared to when the oscillation stabilization bit overflows One of three oscillation stabilization time can be selected by the oscillation stabilization time selection bits of the system clock control register SYCC WT1 WTO The time base timer supplies clocks to the watchdog timer and A D converter Clearing the time base timer counter affects the operation of continuous activation cycles In addition when the time base timer is cleared the counter in the watchdog timer is also cleared B Operations of Time base Timer Figure 5 5 2 shows the operation of the time base timer when power on reset occurs sleep mode is entered while the interval timer function is being performed in normal mode stop mode is entered acounter clear request is generated In stop mode the time base timer is cleared and stops operating When returning from stop mode the time base timer counts the oscillation stabilization time 122 CHAPTER 5 TIME BASE TIMER Figure 5 5 2 Operations of Time base Timer Counter value 1FFFFF
160. TR The PWM control register CNTR is used to select the operation mode interval timer operation or PWM timer operation of the 8 bit PWM timer switch the resolution of the PWM timer functions and select the count clock m PWM Control Register CNTR Figure 7 4 2 PWM Control Register CNTR Address bit7 bit6 bits bit4 bit3 bit2 biti bito Initial value 0022H Pi PO TIR OE TIE 0 000000 R W R W R W R W R W R W RW 1 TIE Bit to enable an interrupt request 0 Disables interrupt request output Enables interrupt request output Bit to control the output pin Used as the general purpose port P50 Used as the output pin for the interval timer or PWM timer PWM Interrupt request flag bit Read The interval timer used The PWM timer used Write The counter value does not Clears this bit match the settings Not changed The counter value matches Not changed Does the settings not affect other settings Bit to enable the counter operation Stops the counter operation Starts the counter operation Bits to select a clock 1 tinst Internal count 16 tinst clock 64 tet Outputs an 8 16 bit capture timer counter Bit to select the operation mode Operates as the interval timer Operates as the PWM timer tnst Instruction cycle R W Readable Writable J Initial value
161. TSTRO 0 it retains its value and stops If the subsequent operation is continued TSTRO 1 the count value is cleared and the counter is restarted Figure 8 9 1 Counter Operation in Standby Mode and at Halfway Stop Counter value Value set in data register Start Match Match Counter clear TSTRO bit Clear by program TIFO bit TO pin register Sleep release by IRQ3 St STP bit LL po STBC register External interrupt When the pin state specification bit SPL of the standby control register STBC is 1 and the TO pin is not pulled up the TO pin in the stop mode becomes Hi Z When the pin state specification bit SPL is 0 the value immediately before the 8 16 bit capture timer counter switches to the stop mode is retained 197 CHAPTER 8 8 16 BIT CAPTURE TIMER COUNTER 8 10 Notes on Using 8 16 bit Capture Timer Counter This section provides notes on using the 8 16 bit capture timer counter m Notes on Using the 8 16 bit Capture Timer Counter e Error The start of the 8 16 bit capture timer counter by a program is asynchronous with the start of the counter incremented by the selected count clock and therefore the error a time difference continues until the counter value matches the set data Such a time difference may shorten the total count duration by a maximum of one count clock cycle Figure 8 10 1 shows the error a time difference that prolongs the actual start of count
162. U 3 4 1 Interrupt Level Setting Registers ILR1 to ILR4 For the interrupt level setting registers ILR1 2 3 and 4 16 two bit data items corresponding to interrupt requests sent from peripheral functions are assigned Interrupt levels can be specified in these 2 bits interrupt level setting bits m Configuration of the Interrupt Level Setting Registers ILR1 to ILR4 Figure 3 4 1 Configuration of Interrupt Level Setting Register Register Address bit bit6 bit5 bit4 bit3 bit2 bitO Initial value ILR1 007BH 1 L10 1111 11118 ILR2 007C 007D ILR4 007E W Write only For each interrupt request 2 bits of the interrupt level setting registers are assigned The values specified in the interrupt level setting registers are the intensities for processing the interrupts interrupt levels 1 to 3 Interrupt level setting bits are compared with interrupt level bits in the condition code register CCR IL1 and ILO When interrupt level 3 is specified the CPU does not accept interrupt requests Table 3 4 2 provides the relationship between interrupt level setting bits and interrupt levels Table 3 4 2 Relationship between Interrupt Level Setting Bits and Interrupt Levels LO1 to LF1 LOO to LFO Requested interrupt level Priority 0 0 High 0 1 i 1 0 2 1 1 3 Low no interrupt Notes When the main program is being executed the int
163. URE TIMER COUNTER 8 6 Explanation of Operations of Interval Timer Functions This section describes the interval timer function operation of the 8 16 bit capture timer counter m interval Timer Function Operation 8 bit mode To operate timer as the interval timer function in the 8 bit mode the function must be set as shown in Figure 8 6 1 Figure 8 6 1 Setting of Interval Timer Function Timer 0 bit7 bite bit5 bit4 bit3 bit2 bit bitO TCCR x x x x x L Settingofoo x x x x L Setting of a value x other than 111 9 9 9 9 L Setting of a value 9 other than 111 e TSEL TDRO Setting of interval time Used bit x Unused bit To operate timer 1 as the interval timer function in the 8 bit mode the function must be set as shown in Figure 8 6 2 185 CHAPTER 8 8 16 BIT CAPTURE TIMER COUNTER 186 Figure 8 6 2 Setting of Interval Timer Function Timer 1 bit7 bite bit5 bit4 bit3 bit2 bit bitO TCCR x x x x x Settingof 00 x mri TECRi TCS12 TCS11 TCS10 TSTR1 L Setting of a value 4 9 9 9 other than 111 9 L Setting of a value J a other than 111 5 rs amp TDR1 Setting of interval time Used bit x Unused bit When the counter is activated in the 8 bit mode increment begins at the rising or falling edge of the selected clock starting at 00g When the counter value matc
164. a Serial Status and Data Register SSD Figure 13 4 4 Serial Status and Data Register SSD Address bit7 bit6 bits bit4 bit3 bit2 biti Initial value 002AH RDRF ORFE TDRE TIE RIE TD8 TP RD8 RP 00100 1Xg R R RW RW RW RW R LO Bit 8 receiving data parity bit Parity used Parity not used SMC PEN 1 SMC PEN 0 Detects odd parity Bit 8 receiving data Detects even parity Bit 8 transmitting data parity bit Parity used Parity not used SMC PEN 1 SMC PEN 0 Adds odd parity Adds even parity RIE Reception interrupt request enable bit Disables output of reception interrupt requests Enables output of reception interrupt requests Sets bit 8 transmitting data Transmission interrupt request enable bit 0 Disables output of transmission interrupt requests 1 Enables output of transmission interrupt requests TDRE Transmitted data flag bit Data to be transmitted included 1 Data to be transmitted not included RDRF ORFE Received data flag bit Overrun Framing error flag bit o 1 Framingeror 1 0 Normal data 1 1 Overrun error previous data remaining Readable Writable Read only Unused Undefined Initial value Effective only when data length is 9 bits SMC MC1 and MCO 10g and 118 operating mode is 2 or 3 294 CHAPTER 13 UART Table 13 4 3 Explanation of Fu
165. access only the register bank pointer 31 CHAPTER 3 CPU 3 3 General Purpose Registers The general purpose registers are memory blocks Eight 8 bits comprise a bank The register bank pointer RP specifies a register bank Although up to 32 banks can be used some banks can be expanded onto external RAM if the capacity of internal RAM is not sufficient for all 32 banks The general purpose registers are effective for processing interrupts vector calls or subroutine calls m Configuration of the General purpose Registers e Each general purpose register consists of 8 bits The general purpose registers are placed in the register banks at the general purpose register area on RAM One bank contains eight registers RO to R7 and up to 32 banks can be used However some models restrict the number of usable banks when only internal RAM is used The register bank pointer RP specifies the register bank being used The lower three bits of an operation code indicate general purpose register 0 RO to general purpose register 7 R7 Figure 3 3 1 shows the configuration of the register banks Figure 3 3 1 Configuration of Register Bank RO m RP 00000 8 Bank 1 The number of usable banks RP 00001 8 is dependent on the size of the usable RAM area Bank 2 to Bank 30 RO RP 11111 rey mJ o Address at the top of the register banks 0100 8 x upper 5 bits of RP R
166. ad When being written Address Initial value Output latch of 0 is set and L level is output to the pin in output port mode Pin state is L level Port 7 data register PDR7 Output latch of 1 is set and H level is output to the pin in output port mode Pin state is H level Output transistor operation Input port is disabled and the pin is set Port 7 data to serve as an input pin direction register DDR7 Output transistor operation Output port is enabled and the pin is set to serve as output pin R W Readable and Writable X Undefined 109 CHAPTER 4 I O PORTS Port 7 pull up setting register PUL7 The bits of the pull up setting register correspond to the pins of port 7 in one to one correspondence When the pull up resistor is selected by using the pull up setting register the pin will be at H level pull up state instead of Hi Z during stop SPL 1 During a reset however the pull up is invalid and the pin remains at Hi Z Figure 4 7 2 shows the pull up resistor settings assigned to the values of the bits of the port 7 pull up register Figure 4 7 2 Pull up Resistor Settings PUL7 Address bit7 bit6 bit5 bit4 bits bit2 biti bito Initial value gt ES oso RW R W EN 1 Puu2 PUL71 R W Readable Writable P72 pull up OFF P71 pull up OFF P70 pull up OFF E Initial value P72 pull up ON P71 pull up ON P70 pull up ON
167. al Output 336 A A D Control Register A D Control Register 1 ADCI 266 A D Control Register 2 ADC2 268 A D Conversion A D Conversion Functions 260 Interrupt when A D Conversion Functions are Enabled neut et ls iae Pg 272 Operations of A D Conversion Functions 274 Program Example of the A D Conversion Functions nn 277 A D Converter Activating the A D Converter Functions 273 Block Diagram of the A D 261 Block Diagram of the Pins Related to the A D CONVELED qnt 264 Notes on Using the A D Converter 275 Pins Related to the A D Converter 263 Register and Vector Table Related to the Interrupt of the A D Converter 272 Registers Related to the A D Converter 265 A D Data Register A D Data Register ADDH and ADDL 270 A D Enable Register A D Enable Register ADEN 271 Abstract ADSUACE eee S Read Tir hee S 372 Activating Activating the A D Converter Functions 273 Active Mode Operations in Active Mode 59 ADC A D Control Register 1 ADCI 266 A D Control Register 2 ADC2 268 ADDH and ADDL A D Data Register ADDH and ADDL 270 Address Comparison EN Register Address Compariso
168. am for peripheral functions specify interrupt levels in the interrupt level setting registers ILR1 to ILR4 concerned then start up the peripheral functions Interrupt levels 1 2 and 3 can be specified Level 1 is the highest level and level 2 is the second highest level Level 3 prohibits interrupts from the peripheral functions to which it is assigned Q Run the main program For a multiple interrupt run the interrupt processing routine When a peripheral function generates a source of an interrupt the interrupt request flag bit for peripheral function request F F is set to 1 If the interrupt request enable bit for a peripheral function is turned on enable F F 1 at that time an interrupt request is output to the interrupt controller 37 CHAPTER 3 CPU e The interrupt controller is always monitoring interrupt requests from peripheral functions The interrupt controller notifies the CPU of the highest interrupt level interrupt among levels corresponding to interrupt requests currently generated If different requests are made with the same interrupt level the interrupt controller also determines their priorities The CPU checks the value in the interrupt enable flag CCR I when the priority of the interrupt level that is received is higher the level value is lower than the level specified in the interrupt level bits in the condition code register CCR IL1 and ILO The CPU then accepts the interrupt when the enable
169. apter describes the functions and operation of the 8 bit serial I O CHAPTER 15 BUZZER OUTPUT This chapter describes the functions and operation of the buzzer output CHAPTER 16 WILD REGISTER FUNCTIONS This chapter describes the functions and operation of the wild registers CHAPTER 17 FLASH MEMORY This chapter describes the functions and operation of the flash memory APPENDIX This appendix shows the I O map and instructions list The contents of this document are subject to change without notice Customers are advised to consult with sales representatives before ordering The information such as descriptions of function and application circuit examples in this document are presented solely for the purpose of reference to show examples of operations and uses of FUJITSU semiconductor device FUJITSU does not warrant proper operation of the device with respect to use based on such information When you develop equipment incorporating the device based on such information you must assume any responsibility arising out of such use of the information FUJITSU assumes no liability for any damages whatsoever arising out of the use of the information Any information in this document including descriptions of function and schematic diagrams shall not be construed as license of the use or exercise of any intellectual property right such as patent right or copyright or any other right of FUJITSU or any third party or does FUJITSU warrant non infringe
170. apture Timer Counter Pins 169 Block Diagram of 8 16 bit Capture Timer Counter eeeseeeeeee 166 404 Notes on Using the 8 16 bit Capture Timer Counter eee 198 Pins of 8 16 bit Capture Timer Counter 168 Register and Vector Table Related to 8 16 bit Capture Timer Counter of Interrupts 184 Registers of 8 16 bit Capture Timer Counter TENA 170 8 bit PWM Timer Block Diagram of an 8 bit PWM Timer 139 Block Diagram of the Pin Related to the 8 bit PVM bin TEE PEDEM 141 Notes on Using 8 bit PWM Timer 155 Operations of the 8 bit PWM Timer Functions UE 150 Pin Related to the 8 bit PWM Timer 141 Register and Vector Table Related to the Interrupts of an 8 bit PWM Timer 147 Registers Related to the 8 bit PWM Timer 142 8 bit Serial I O Block Diagram for 8 bit Serial I O Pins 318 Block Diagram of 8 bit Serial I O 315 Notes on Using 8 bit Serial I O 333 Pins of 8 bit Serial 1 317 Registers of 8 bit Serial I O 319 8 bit Serial I O Interrupt Register 8 bit Serial I O Interrupt Register and Vector Table E 324 8 bit Serial Input Program Example for 8 bit Serial Input 337 8 bit Serial Output Program Example for 8 bit Seri
171. ardless of clock mode Note For details on pin states in standby mode see APPENDIX E Pin State of the MB89202 F202RA Series 63 CHAPTER 3 CPU 3 7 2 Sleep Mode This section describes sleep mode B Operations Relating to Sleep Mode 64 Transition to sleep mode In sleep mode the operating clock for CPU is stopped Although the CPU stops storing data in the registers and RAM used immediately before transition to sleep mode peripheral functions excepting the watchdog timer continue to operate Writing 1 to the sleep bit in the standby control register STBC SLP results in a transition to sleep mode Any attempt to write 1 into the SLP bit while an interrupt request is being generated fails transition to sleep mode cannot be made and instructions are processed continuously Even after the interrupt is processed completely transition to sleep mode is not possible Cancellation of sleep mode Sleep mode is cancelled by a reset or interrupt from a peripheral function Pin states are initialized by the reset operation When an interrupt request with an interrupt level higher than 11g is generated in a peripheral function or external interrupt circuit in sleep mode sleep mode is cancelled regardless of the CPU interrupt enable flag CCR I or interrupt level bits CCR IL1 and ILO When sleep mode is cancelled a normal interrupt operation is performed and if interrupts are acceptable interrupt pr
172. ared with the counter values in the higher 8 bits of the 16 bit timer When the interval timer function is used the higher 8 bits of the interval time are set When the counter function is used the higher 8 bits of the count value to be detected are set The values in TDR1 are loaded to the higher 8 bits of the comparator data latch when matching the counter values of the 16 bit timer or when the count operation is started The values written to TDR1 when the 16 bit counter is operating become valid after match detection In the 16 bit mode the count operation is controlled by the timer 0 control register TCRO Note The values set in and TDR1 when the interval function is used can be calculated from the expression shown below However the instruction cycle is affected by the clock mode and gear function 16 bit data value interval time count clock cycle x instruction cycle 1 The higher 8 bits of the 16 bit data value are set in TDR1 and the lower 8 bits are set in 181 CHAPTER 8 8 16 BIT CAPTURE TIMER COUNTER 8 4 7 Capture Data Registers H and L TCPH and TCPL The capture data register H TCPH stores the number of events of the higher 8 bits in the 16 bit capture mode of the 8 16 bit capture timer counter The capture data register L TCPL stores the number of events in the 8 bit capture mode of the 8 16 bit capture timer counter or the number of events of the lower 8 bits in the 16 bit capture mode
173. arts PWM operations internal clocks and count operations T Check MOV CNTR 11001010B Enables PWM output Uses the general purpose port Check H Depending on the port state ERU N Executing the instruction to enable the PWM output 156 CHAPTER 7 8 BIT PWM TIMER 7 10 Program Example for PWM Timer This section describes program examples of an 8 bit PWM timer m Program Example of Interval Timer Functions Processing specifications 5msinterval timer interrupts occur repeatedly The square waveform that inverts at an interval is output to the P50 PWM pin The following expression yields the COMR register value for which the interval is about 5 ms when the top speed of the gear one instruction cycle 4 is obtained at an oscillation frequency of 12 5 MHz The count clock is 64 tips of the internal count clock COMR register value 5 ms 64 x 4 12 5 MHz 1 244 1 4 Coding example CNTR EQU 0022H Address of the PWM control register COMR EQU 0023H Address of the PWM compare register TPE EQU CNTR 3 Defining the bit to enable the counter operation TIR EQU CNTR 2 Defining the interrupt request flag bit ILR3 EQU 007D Address of the register to set the interrupt level INTV DSEG ABS DATA SEGMENT ORG OFFF8H IRQ9 DW WARII Setting the interrupt vector INTV ENDS i em Main program CSEG CO
174. ated with port 4 E Functions of Port 4 Registers Port 4 data register The PDR4 register indicates the state of the pins For a pin set to function as an output port the same value O or 1 as held by the output latch can be read from this register If the pin is set to function as an input port however its output latch value cannot be read from the register Note When a bit manipulation instruction SETB CLRB is executed the output latch values not the value states of the pins are read thus output latch values excepting those for bits to be manipulated do not change Table 4 4 3 lists the functions of the port 4 registers Table 4 4 3 Functions of Port 4 Registers Initial value Register name When being read When being written Address Output latch of 0 is set and Pin state is L level L level is output to the pin in output port mode Port 4 data N ch open register drain type PDR4 Output latch of 1 is set and the pin in output port mode XXXXp Pin state is set at Hi Z is level CMOS Output latch of 1 is set and push pull H level is output to the pin type in output port mode The pin is set to function as Port 4 Input port pin input pin with output data transistor operation disabled direction register The pin is set to function as DDR4 Output port pin output pin with output transistor operation enabled Port 4 N ch open drain type Ou
175. ays 0 The compare match detection flag is cleared Compare match detection flag bit 9 compare match has occurred A compare match occurred 173 CHAPTER 8 8 16 BIT CAPTURE TIMER COUNTER Table 8 4 2 Explanation of Functions of Each Bit in Timer 0 Control Register TCRO Bit name Function 8 bit mode When the counter value of timer 0 matches the value comparator data latch set in the timer 0 data register TDRO this bit is set to 1 16 bit mode When the counter value of timer 0 matches the value set in TDRO and the counter value of timer 1 matches the value set in TDR1 this bit is set to 1 An interrupt request is output when this bit and the interrupt request enable bit TOIEN are 1 TIFO Compare match detection flag bit TFCRO This bit is used to clear the compare match detection flag bit TIFO When this Compare match bit is set to 1 the compare match detection flag is cleared The flag is not detection flag clear bit affected even if this bit is set to 0 TOIEN This bit is used to allow and prohibit interrupt request output to the CPU Interrupt request enable An interrupt request is output when this bit and the interrupt request enable bit bit TOIEN are 1 This bit is used to select whether to increment the counter at the rising or CINV falling edge of a clock When this bit is the counter is incremented at the Count clock selection bit falling edge of the clock When
176. bit SCKE is 1 a shift clock is output from the UCK SCK pin When these bits are 11g the external clock is selected When the P30 UCK SCK pin is set as the shift clock input pin a shift clock is input from the UCK SCK pin when the SCKE bit and bitO of the DDR3 are 0 321 CHAPTER 14 8 BIT SERIAL I O Table 14 4 1 Explanation of Functions of Each Bit in Serial Mode Register SMR 2 2 Bit name Function This bit is used to select whether to transfer serial data starting at the lowest bit LSB first BDS 0 or the highest bit MSB first BDS 1 When this BDS bit is set to 0 serial data is transferred starting at the lowest bit When it is Transfer direction set to 1 serial data is transferred starting at the highest bit selection bit Note If this bit is rewritten after serial data has been written to the SDR to replace higher data with lower data the data in the SDR becomes invalid This bit is used to control serial I O transfer start and allowance It can also be used to judge whether serial I O transfer terminated If this bit is set to 1 when the internal shift clock is selected when the CKS1 and CKSO bits are not 11 the shift clock counter is cleared and serial I O transfer is started If this bit is set to 1 when the external shift clock is selected when the CKS1 and CKSO bits are 115 serial I O transfer is allowed and the shift SST clock counter is cleared The transfer side enters the
177. bit is 0 the value immediately before the move to the stop mode is held 153 CHAPTER 7 8 BIT PWM TIMER While PWM timer functions are enabled Figure 7 8 2 Operation in the Standby Mode and during Suspension while PWM Timer Functions are Enabled PWM pin PWM waveform The level immediately before stop TPE bit is held Stopping Restarting operation operation SLP bit STBC register Release of sleep by something other than IRQ9 IRQ9 does Stop not occur lt gt STP bit L STBC register gt lt Time to wait for oscillation stabilization Release of stop by an external interrupt When the bit to specify the pin state STBC SPL of the standby control register is 1 and the PWM pin is not pulled up the PWM pin in the stop mode is Hi Z When the SPL bit is 0 the value immediately before the move to the stop mode is held 154 CHAPTER 7 8 BIT PWM TIMER 7 9 Notes on Using 8 bit PWM Timer This section provides notes on using 8 bit PWM timer m Notes on Using 8 bit PWM Timer e Error The activation of the counter by a program does not synchronize the start of an increment by the selected count clock Therefore as an error until a match between the counter value and the PWM compare register COMR value is detected the time may be shortened by up to one cycle of the count clock cycle Figure 7 9 1 shows an error until the count operation is started
178. bit4 of the port data direction Interrupt request register DDR3 so that the pin serves inputs only Write 0 for bit of the timer enable bit 0 output control register TCR2 for the 8 16 bit capture timer counter to set the port input function on Regardless of the interrupt request enable bit state the state of the external interrupt pin can be read directly from the port data register PDR3 234 CHAPTER 10 EXTERNAL INTERRUPT CIRCUIT 1 EDGE 10 4 2 External Interrupt Control Register 2 EIC2 As with external interrupt control register 1 EIC1 external interrupt control register 2 EIC2 comprises bits for edge polarity selection and interrupt control for the INT12 external interrupt pin External Interrupt Control Register 2 EIC2 Figure 10 4 3 External Interrupt Control Register 2 EIC2 Address bit7 bit6 bits bit4 bits bit2 biti bitO Initial value 0054 5121 00008 RAN RW RW RW EIE2 Interrupt request enable bit 2 Disables interrupt request outputs Enables interrupt request outputs SL21 SL20 Edge polarity selection bits 2 Edge detection OFF o 1 Risingedge FIRS External interrupt request flag bit 2 When being read When being written Signal input with specified edge um or sages nol detected 3 This bit is cleared 1 Signal input with specified edge No change not affecting other or edges detected operation
179. bitti bitlO bits bit bit6 bits bits bit biti bito RP initial value Im r re u nol z v Xxxx X Undefined The register bank pointer indicates the address of the register bank being used Figure 3 2 5 shows the rule of conversion from the register bank pointer bits to the actual address Figure 3 2 5 Rule of Conversion from the RP Bits to the Actual Address RP upper bits Lower bits of operation code 1 LRA R3 R2 RI RO bl b Xd dX e 4 X 4 d 4 Jj generated Aib Ai4 A13 A12 11 10 Address The register bank pointer specifies a memory block register bank used as a general purpose register in the RAM area There are 32 register banks Setting a value from 0 to 31 in the upper five bits of the register bank pointer specifies a register bank One register bank contains eight 8 bit general purpose registers that are selected with the lower 3 bits of an operation code The register bank pointer allows a range of 0100y to 01 maximum to be used as the general purpose register area However some models restrict the usable range when only internal RAM is used The initial value of the register bank pointer specified after the reset operation is undefined Note Be sure to set up the register bank pointer RP before using general purpose registers The register bank pointer is part of the program status register PS and thus is not allowed to
180. capacitor with about 0 1 uF be added externally to the analog input Figure 12 7 1 Equivalent Circuit of Analog Input MB89202 F202RA series Sample hold circuit Converter Selecting an analog channel After activation of A D conversion close 16 instruction cycles Notes on setting using a program When A D conversion functions are enabled the values in the ADDH and ADDL registers are held without being changed until the activation of A D conversion However once A D conversion is activated the values in the ADDH and ADDL registers become undefined immediately When A D conversion functions are enabled do not reselect an analog input channel ADC1 ANS3 to ANSO Especially during continuous activation disable continuous activation ADC2 EXT 0 and wait for the conversion in progress flag bit ADC1 ADMV to be 0 for reselection The A D converter is stopped via a reset and activation of the stop mode and all registers are initialized When the interrupt request flag bit ADC1 ADI is 1 and an interrupt request is enabled ADC2 ADIE 1 recovery from interrupt handling is no longer possible Be sure to clear the ADI bit Note When A D conversion is completed if the next conversion is reactivated the interrupt request flag bit ADC1 ADI is not set 275 CHAPTER 12 A D CONVERTER Notes on interrupt requests If A D conversion is reactivated ADC1 AD 1 and terminated at the same time the int
181. chronous asynchronous 1 bit or 2 bits 9 bits Synchronous asynchronous bit or 2 bits Only one bit is allowed for the stop bit length when data is received The second bit is ignored even if it is received 280 CHAPTER 13 UART m Serial Switch UART and 8 bit serial I O use the same pins thus they cannot be simultaneously used The serial switch circuit needs be used to select either of them When is selected using the serial switch P30 UCK SCK is used as the UART serial clock I O pin UCK P31 UO SO is used as UART data output pin UO and P32 UI SI is used as the UART data input pin UI Note In this chapter the pin function switch and register functions are explained on the presupposition that UART is selected using the serial switch circuit B Choice of the Transfer Clock Rate Figure 13 1 1 Baud Rate Generator and Serial Clock Generator PR2 to PRO RC2 to RCO CS1 CSO SMDE UART prescaler When RC2 and RC1 1 the divider is 1 even in asynchronous mode PWM output UCK tinst Instruction cycle Example of the baud rates selectable when the dedicated baud rate generator is used Table 13 1 2 lists the baud rates selectable when the dedicated baud rate generator is used Table 13 1 2 Transfer Cycles and Transfer Rates Available for the Dedicated Baud Rate Generator when Fey 12 5 MHz Transfer rate us baud Clock divider 2 5 Clock divider 1 PR2 0
182. ciated with External Interrupt Circuit 2 247 Block Diagram of External Interrupt Circuit 1 Dm DR Em TER 227 Block Diagram of External Interrupt Circuit 2 245 Functions of External Interrupt Circuit 1 226 407 INDEX Functions of External Interrupt Circuit 2 Level 244 Interrupt during the Operation of External Interrupt Carcuit been 237 Interrupt during the Operation of External Interrupt CUCU 2 ERES 253 Operation of External Interrupt Circuit 1 239 Operation of External Interrupt Circuit 2 254 Pins Associated with External Interrupt Circuit 1 Register Associated with Interrupt Generation by External Interrupt Circuit 1 and Vector Register Associated with Interrupt Generation by External Interrupt Circuit 2 and Vector External Interrupt 2 Flag Register External Interrupt 2 Flag Register EIF2 252 External Interrupt Circuit External Interrupt Circuit 1 Programming Example External Interrupt Circuit 2 Control Register External Interrupt Circuit 2 Control Register EIE2 DEREN n ert AT 250 External Interrupt Control Register External Interrupt Control Register 1 EIC1 eh e ouf ker e t dL eu 232 External Interrupt Control Register 2 EIC2 rm 235 External Reset Block Diagram of External Reset Pin 47 Function of the External Reset P
183. cillation stabilization time Pa Approximately 20 97 ms 116 CHAPTER 5 TIME BASE TIMER Table 5 1 2 Clock Cycles Supplied by Time base Timer 2 2 Clock supplied to Clock cycle Remarks Watchdog timer 22208 Approximately 335 5 ms Watchdog timer count up clock A D converter Foy Approximately 20 5 us Continuous activation clock Fox Oscillation frequency The values enclosed in parentheses are time intervals when the oscillation frequency is 12 5 MHz Note Because oscillation cycles vary immediately after oscillation starts the oscillation stabilization wait time is listed for reference 117 CHAPTER 5 TIME BASE TIMER 5 2 Configuration of Time base Timer The time base timer consists of the following four function blocks Time base counter Counter clear circuit Interval timer selector Time base timer control register TBTC m Block Diagram of Time base Timer Figure 5 2 1 Block Diagram of Time base Timer A D converter To watchdog timer Time base timer coun x2 x21 x2 5 x216 x2 7 Clearing watchdog timer 4 OF OF l dida es Counter Interval timer Starting stop mode C ear selector in normal mode circuit IRQ7 time base timer interrupt OF Overflow Fcu Oscillation frequency Time base
184. ck counter tinst Instruction cycle 315 CHAPTER 14 8 BIT SERIAL I O 316 e Shift clock control circuit As a shift clock of the shift clock control circuit one of three internal clocks and one external clock is selected Selecting an internal clock enables the shift clock to be output to the SCK pin Selecting an external clock enables the clock to be input from the SCK pin to act as the shift clock The shift clock control circuit shifts the SDR in accordance with this shift clock and outputs the shifted out value to the SO pin It also captures the data input from the SI pin while shifting it to the SDR e Shift clock counter The shift clock counter counts the number of times the SDR was shifted using the shift clock When 8 bit shift is completed the counter overflows When the counter overflows the serial I O transfer start bit of the SMR SST 0 is cleared and the interrupt request flag bit SIOF 1 is set When serial transfer stops SST 0 the counter stops its count It is cleared when serial transfer is started SST 1 Serial data register SDR The SDR retains transfer data The data written to the SDR is converted to serial data and output Serial input is converted to parallel data and stored Serial mode register SMR The SMR is a serial I O control register It is used to allow and prohibit serial I O operation select shift clocks and set a transfer shift direction It is also used to con
185. cribes the precautions to be taken when handling the power supply voltage pins and other device items Precautions on Handling Devices Ensure that the voltage does not exceed the maximum ratings Preventing latch up A latch up may occur if a voltage higher than Vcc or lower than Vss is applied to input or output pins other than middle or high level resistant pins or if voltage exceeding the rated value is applied between Vcc and Vss When a latch up occurs the supply current increases rapidly occasionally resulting in overheating Therefore ensure that the voltage does not exceed the maximum ratings when using the microcontrollers Stabilize the supply voltage as much as possible Although the specified Vcc supply voltage operating range is assured a sudden change in the supply voltage within the specified range may result in a malfunction The following stabilization guidelines are recommended The Vcc ripple P P value at the supply frequency 50 Hz to 60 Hz should be less than 10 of the typical Vcc value and the transient fluctuation rate should be less than 0 1 V ms at the time of momentary fluctuation when switching the power supply Handling unused input pins Leaving unused input pins open may result in a malfunction or equipment damage due to a latch up Therefore set these pins to pull up or pull down via resistors of 2 or higher Handling the N C pins Ensure that the N C internally co
186. cture of Port 5 Port 5 comprises the following four elements e General purpose I O pins P50 PWM e Port 5 data register PDR5 e Port 5 data direction register DDR5 Port 5 pull up setting register PUL5 m Pins of Port 5 Port 5 has one CMOS I O pin Table 4 5 1 provides information on the pin of port 5 Table 4 5 1 Pin of Port 5 Input and output Peripherals for which the form Circuit pin may serve type Pin name Function P50 PWM P50 general PWM 8 bit PWM timer CMOS CMOS E purpose I O output For circuit type see Section 1 7 Pin Functions Description and 1 8 I O Circuit Types 94 CHAPTER 4 I O PORTS m Block Diagram of Port 5 Figure 4 5 1 Block Diagram of Port 5 lt Stop mode SPL 1 Pull up resistor PDR read lt PDR read oe when read modify write is performed gt Output latch PDR write D DDR write 7 3 a amp g s 5 c 2 Stop mode SPL 1 DDR read E GEN PUL read gt PUL PUL write m Registers of Port 5 The registers PDR5 DDR5 and PULS are associated with port 5 One of the bits of these registers corresponds to one pin of port 5 Table 4 5 2 tabulates the correspondence between the pin and a bit of the port 5 registers Table 4 5 2 Correspondence between the Pin and a Bit of the Port 5 Registers Bits of associated registers and corresponding pins PDR5 DDR5 PUL5 Pin corresponding to bit
187. data 295 CHAPTER 13 UART B Receiving Status Figure 13 4 5 shows the states receiving status of serial input data obtained from the received data flag bit RDRF and error flag bit ORFE Figure 13 4 5 Receiving Status 0 0 Noda Lo 1 1 Normal data Overrun error previous data remaining Initial value 296 CHAPTER 13 UART 13 4 4 Serial Input Data Register SIDR The serial input data register SIDR is for inputting receiving serial data Serial Input Data Register SIDR Figure 13 4 6 shows the configuration of the serial input data register bits Figure 13 4 6 Serial Input Data Register SIDR Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bitO Initial value T T I LL oww R R R R R R R R R Read only X Undefined The SIDR stores received data The serial data input pin UI pin receives serial data signals the shift register converts them then this register stores them When operating mode is 0 1 or 3 For both the RDRF Received data flag bit and ORFE Overrun framing error flag bit these flags go on and an interrupt request to the CPU is generated when data is fully transmitted or received then the stop bit at the end is detected When the is active the data received is transmitted to the SIDR When the received data is correctly stored in this register 1 is set for the received data flag bit RD
188. date et 180 8 4 7 Capture Data Registers H L TCPH TCPL 182 8 5 8 16 bit Capture Timer Counter of Interrupts sssssssssssseseeeeen ennemis 183 8 6 Explanation of Operations of Interval Timer Functions ssssssssseeseeeeennens 185 8 7 Operation of Counter Functions sssssssssssssssesss esee 189 8 8 Functions of Operations of Capture Functions sess 193 8 9 8 16 bit Capture Timer Counter Operation in Each Mode 197 8 10 Notes on Using 8 16 bit Capture Timer Counter ssssssssssssesseeeeeeneeen nnns 198 8 11 Program Example for 8 16 bit Capture Timer Counter sse 200 CHAPTER 9 12 BIT PPG TIMER 2 pni scia n caa nua ne ep ae Crac Ceca nura Ex ura 205 9 1 Overview of 12 bit PPG Timer sssssssssssssssseseeee 206 9 2 Configuration of 12 bit PPG Timer Circuit essent 209 9 3 Pin of 12 bit PPG Timer nite eb n Teneo p Ee Pen UE pae 211 9 4 Registers of 12 bit PPG Timer nennen nennen trn nensi snnt nennen snnt nnns 213 9 4 1 12 bit PPG Control Register 1 RCR21 214 9 4 2 12 bit PPG Control Register 2 22
189. dy initialized CLRI Disables interrupts CLRB SST Stops serial I O transfer MOV ILR4 11111101B MOV SDR 55H MOV SMR 01111000B Sets the interrupt level to 1 Sets transfer data 55H Clears the interrupt request flag allows the interrupt request output shift clock output SCK and serial data output SO selects 32tINST and sets LSB first Selects the 8 bit serial I O Starts serial I O transfer MOV SSEL 00000001B SETB SST SETI Enables interrupts 336 CLRB PUSHW XCHW PUSHW MOV SETB SIOF A A T A SDR 55H SST User processing POPW XCHW POPW RETI ENDS A A T E Program Example for 8 bit Serial Input Processing specifications CHAPTER 14 8 BIT SERIAL I O Clears the interrupt request flag Saves A and T Resets transfer data 55 Starts serial I O transfer Returns A and T The 8 bit serial input program inputs 8 bit serial data from the SI pin of the 8 bit serial I O When serial T O transfer terminates an interrupt occurs The program reads transfer data with the interrupt processing routine and inputs it continuously The program uses the external shift clock to be input from the SCK pin Coding example DDR3 SMR EQU EQU EQU EQU EQU EQU EQU DSEG ORG MOV CLRI CLRB MOV 000DH 0039H 003AH 003BH SMR 7 SMR 0 007EH ABS OFFE2H WARI DDR3 00000000B SST ILR4 11111101B Address
190. e H width and the contents of these bits and the HSC6 to HSC11 bits of the RCR22 register are compared with a count by the counter HSCS to HSCO H width setting bits 214 CHAPTER 9 12 BIT PPG TIMER 9 4 2 12 bit PPG Control Register 2 RCR22 The 12 bit PPG control register 2 comprises bits for setting the H width of 12 bit PPG pulse waveforms 12 bit PPG Control Register 2 RCR22 Figure 9 4 3 12 bit PPG Control Register 2 RCR22 Address 7 bit6 bit5 bit bit3 bit2 bit1 bito Initial value RAN RW RW RW RW RW HSC11 to HSC6 H width setting bits XXXXXX Compare value for the width of 12 bit PPG outputs R W Readable Writable Unused Table 9 4 2 Explanation of Functions of Each Bit in 12 bit PPG Control Register 2 RCR22 Bit name Function Bit value is undefined when being read Unused bits e Written value does not affect other operations These bits are used to set the number of counts corresponding to the H width of 12 bit PPG timer outputs the compare value for the H width and the contents of these bits and the HSCO to HSCS bits of the RCR21 register are compared with a count by the counter HSC11 to HSC6 H width setting bits 215 CHAPTER 9 12 BIT PPG TIMER 9 4 3 12 bit PPG Control Register 3 RCR23 The 12 bit PPG control register 3 comprises a bit for enabling 12 bit PPG waveform outputs and bits for setting a cycle period o
191. e SPL 1 During a reset however the pull up is invalid with the pin remaining at Hi Z 106 CHAPTER 4 I O PORTS 4 7 Port 7 Port 7 is a general purpose I O port This section describes the port function when operating as general purpose I O port This section also describes the port structure pins the pin block diagram associated registers of port 7 B Structure of Port 7 Port 7 comprises the following four elements e General purpose I O pin P70 to P72 e Port 7 data register PDR7 Port 7 data direction register DDR7 Port 7 pull up setting register PUL7 m Pins of Port 7 Port 7 has 3 CMOS I O pin Table 4 7 1 lists the pins of port 7 Table 4 7 1 Pins of Port 7 Input and output form Circuit Port name Function t Output ype P70 to P72 General purpose I O CMOS CMOS For circuit type see Section 1 7 Pin Functions Description and 1 8 I O Circuit Types 107 CHAPTER 4 I O PORTS m Block Diagram of Port 7 Figure 4 7 1 Block Diagram of Port 7 Stop mode SPL 1 Pull up resistor PDR read PDR read T when read modify write is performed e 2 a o o g Output latch PDR write DDR write Stop mode SPL 1 DDR read PUL read PUL write m Registers PDR7 DDR7 and PUL7 of Port 7 Registers PDR7 DDR7 and PUL7 are associated with port 7 The bits of these registers correspond to the pins of port 7 in one to o
192. e eaae a lotes 281 Serial Switch Register Serial Switch Register SSEL 301 Setting Setting the Read Reset State 368 SIDR Serial Input Data Register SIDR 297 Single chip Mode Single chip Mode ssseeeeeeeeeeee 72 Sleep Mode Operations Related to Sleep Mode 64 SMC Serial Mode Control Register SMC 290 SMR Serial Mode Register SMR 320 SODR Serial Output Data Register SODR 298 Software Reset Software Reset Watchdog Timer Reset 373 Special Instructions Special Instructions 387 Square Wave Interval Timer Functions Functions to Output the Square 136 SRC Serial Rate Control Register SRC 292 SSD Serial Status and Data Register SSD 294 SSEL Serial Switch Register SSEL 301 INDEX Stabilization of Oscillation State of Reset Waiting for Stabilization of Oscillation DIT 49 Stack 16 bit Data Storage State in Stack 26 Stack Area Stack Area for Interrupt Processing 42 Stack Operation Stack Operation at the Beginning of Interrupt PrOCesSIng in cde menor 41 Stack Operation at the End of Interrupt Processing 41 Sta
193. e flash memory m Erasing All Data Erasing Chips All data can be erased from the flash memory by sending the Chip Erase command in the command sequence table see Table 17 3 1 in Section 17 3 Starting the Flash Memory Automatic Algorithm continuously to the target sector in the flash memory The Chip Erase command is executed in six bus operations When writing of the sixth cycle is completed the chip erase operation is started For chip erase the user need not write to the flash memory before erasing During execution of the automatic erase algorithm the flash memory writes 0 for verification before all of the cells are erased automatically 371 CHAPTER 17 FLASH MEMORY 17 6 Flash Security Feature Flash security feature provides possibilities to protect the content of the flash memory from being read from external Abstract By writing the protection code of Oly to the predefined flash security address of the flash memory access to the flash memory is restricted Once the flash memory is protected unlock the security function can only be done by performing the chip erase operation Otherwise read write access of the flash memory from the external pins is not possible This function is suitable for applications requiring security of self containing data stored in the flash memory Table 17 6 1 Flash Security Address Flash Memory Size Flash Security Address MB89F202 F202RA 16 Kbyte FFFC m How to enable
194. e in which TCMSK is used Figure 8 7 2 Counter Function Operation in External Clock Mode EC TSTRO 1 TDRO TCMSK 0 Compare latch Counter clear TCMSK 1 Compare latch Counter clear TIFO 190 CHAPTER 8 8 16 BIT CAPTURE TIMER COUNTER 16 bit mode To operate timer 0 as the counter function in the 16 bit mode the function must be set as shown in Figure 8 7 3 Figure 8 7 3 Setting of Counter Function in 16 bit Mode bit7 bit6 bit5 bit4 bit3 bit2 bit1 DDRS3 X X X X 0 X x x TCCR x x x x Settingof00 x 1 TFCRI THEN TCS12 TCS11 TCS10 TSTRI X X x 1 1 1 x TCRO 1 1 1 Tere e y Jp EN SEL Setting of the higher 8 bits of the counter value to be compared Setting of the lower 8 bits of the counter value to be compared Higher 8 bits of the number of detected events Lower 8 bits of the number of detected events Used bit Unused bit Set 0 Set 1 Counter function operation in the 16 bit mode is the same as interval timer function operation in the 16 bit mode except that the external clock is used instead of the internal clock Figure 8 7 4 shows counter function operation in 16 bit mode 191 CHAPTER 8 8 16 BIT CAPTURE TIMER COUNTER Figure 8 7 4 Counter Function Operation in 16 bit Mode External clock Counter clear TSTRO bits Counter value 0000 0002 000345 Comparator data latch 1 88
195. e lower eight bits of accumulator by TL the lower eight bits of the temporary accumulator without a sign and stores the results in 16 bits length to A The contents of T temporary accumulator remain as they are For the operation the contents of AH the higher eight bits of accumulator and TH the higher eight bits of temporary accumulator before the execution are not used Take care when using a branch based on the result of multiplication because the flags were not changed Figure B 2 3 shows an overview Figure B 2 3 MULU A Before execution After execution a 55784 a 1860s e DIVUA This instruction divides T of 16 bits by AL of 8 bits without a sign stores the results in 8 bits to AL and stores the remainder of 8 bits to TL Both AH and TH become 0 For the operation the contents of AH before execution are not used If the results exceed 8 bits they are not guaranteed Also the fact that the results exceeded 8 bits is not indicated So when using data units that may cause this type of situation judge them in advance Take care when using a branch based on the result of division because the flags were not changed Figure B 2 4 shows an overview Figure 2 4 DIVU A Before execution After execution D 18 XCHW A PC This instruction replaces the contents of A and the contents of PC resulting in a branch to the addre
196. e pin becomes Hi Z because the output transistor is forcibly turned OFF without respect to the value existing on the DDRO register in the bit position corresponding to the pin Input remains fixed to prevent leaks by input open Table 4 2 4 summarizes the operating modes of the pins of port 0 Table 4 2 4 Operating Modes of Pins of Port 0 Pin name Normal operation sleep stop SPL 0 Stop SPL 1 At a reset POO INT20 AN4 S General purpose I O port may also serve external interrupt inputs or analog inputs PO3 INT23 AN7 Hi Z P04 INT24 External interrupt input General purpose I O port may also serve to A P external interrupt inputs PO7 INT27 SPL Pin state setting bit of standby control register STBC SPL Hi Z High impedance Note When the pull up resistor is selected by using the pull up setting register the pin state will be H level instead of Hi Z in stop mode SPL 1 During a reset however the pull up is invalid with the pin remaining at Hi Z 83 CHAPTER 4 I O PORTS 4 3 Port 3 Port 3 is a general purpose I O port and may also serve as input pins for external interrupts as well as input and output pins for peripherals This section mainly explains the general purpose I O function of the port This section also describes port 3 concerning to the structure pins a block diagram of pins and associated registers Structure of Port 3 Port 3 comprises the following four
197. e timer 0 as the counter function in the 8 bit mode the function must be set as shown in Figure 8 7 1 Figure 8 7 1 Setting of Counter Function in 8 bit Mode bit7 bit6 bit5 bit4 bit3 bit2 bit x x x x L Settingof00 x TFCRT TIIEN TCS12 TCS11 TCS10 TSTR1 x x x L Sig ot value d x other than 111 TCSO0 1 1 1 qe e ENIERB X X Number of detected events Setting of the counter value to be compared Used bit Unused bit Set 0 Set 1 Counter function operation in the 8 bit mode is the same as interval timer function timer 0 in 8 bit mode operation except that the external clock is used instead of the internal clock The number of events can be known by reading the capture data register TCPL A specific number of events can be known by the event count detection function 189 CHAPTER 8 8 16 BIT CAPTURE TIMER COUNTER Detection of the number of events In the external clock mode counter clear can be prohibited by the compare match counter clear mask bit TCMSK of the capture control register TCCR when a match is detected Setting the compare match counter clear mask bit to 1 enables the event count detection function to be used In this case a compare match does not cause data to be re loaded to the compare latch To update the compare latch value stop and restart the timer Figure 8 7 2 shows counter function operation in the external clock mod
198. ed in the ADDH register The low order 8 bits of 10 bit A D data are stored in the ADDL register The ADDH and ADDL registers have the following function e For A D conversion function these registers store the results of A D conversion A D control register 1 ADC1 This register is used to enable and disable functions select an analog input check statuses and control interrupts A D control register 2 ADC2 This register is used to select an input clock enable and disable interrupts select functions and perform other activities Interrupts of the A D converter When the set conditions are satisfied at the completion of A D conversion for IRQ8 if an interrupt request output is enabled ADC2 ADIE 1 an interrupt request occurs 262 CHAPTER 12 A D CONVERTER 12 3 Pins of A D Converter This section describes the pins related to the A D converter and shows a block diagram of the pins related to the A D converter m Pins Related to the A D Converter The pins related to the A D converter are PO3 INT23 AN7 to POO INT20 AN4 and P43 ANG to P40 ANO pins P03 INT23 AN7 to POO INT20 AN4 and P43 AN3 to P40 ANO PO3 INT23 AN7 to POO INT20 AN4 and P43 AN3 to P40 ANO pins can be used as general purpose I O ports P03 to and P43 to P40 and as analog inputs AN7 to ANO AN7 to AN0 When A D conversion functions are used input the analog voltage to be converted to these pins To enable a p
199. edure m Writing Data The data write automatic algorithm of the flash memory can be started by sending the Write command in the command sequence table see Table 17 3 1 in Section 17 3 Starting the Flash Memory Automatic Algorithm continuously to the flash memory When data write to the target address is completed in the fourth cycle the automatic algorithm and automatic write are started B Specifying Addresses Writing can be done in any order of addresses However the Write command writes only data of one byte for each execution Notes on Writing Data Writing cannot return data 0 to data 1 When data 1 is written to data 0 the data polling algorithm DQ7 or toggle operation DQ6 does not terminate and the flash memory elements are determined to be faulty If the time prescribed for writing is thus exceeded the timing limit exceeded flag DQ5 is determined to be an error Otherwise the data is viewed as if dummy data 1 had been written However when data is read in the read reset state the data remains 0 Data 0 can be set to data 1 only by erase operations commands are ignored during execution of the automatic write algorithm If a hardware reset is started during writing the data of the written addresses will be unpredictable m Writing to the Flash Memory Figure 17 5 1 is an example of the procedure for writing to the flash memory The hardware sequence flags see Section 17 4 Confirming the Automatic Algori
200. efined when read Writing values into these bits does not affect operation WT1 WTO Oscillation stabilization wait time selection bits Used to select an oscillation stabilization wait time setting When external interrupt causes a return from stop mode to active mode the oscillation stabilization wait time setting selected by these bits is applied The initial values of these bits are determined by options Therefore when an oscillation stabilization wait time setting is to be applied for a reset it is selected by options Note Change values in these bits after confirming that the clock is not waiting for stabilization of oscillation using the SCM bit Unused bit This bit is always 1 when read Note Specify 1 CS1 CSO Clock speed selection bits m Instruction Cycle Used to select the clock speed in active mode One of four operating clock speeds gears can be specified for the CPU and peripheral functions However these bits do not affect the operating clock for the time base timer For instruction cycles minimum instruction run time a 1 4 1 8 1 16 or 1 64 frequency can be selected using the clock speed selection bits CS1 and CS0 In active mode when the oscillation frequency Fcp is 12 5 MHz the instruction cycle for the maximum speed SYCC CS1 and CSO 11g is 4 about 0 32 us 57 CHAPTER 3 CPU 3 6 4 Clock Mode The clock speed is switched by select
201. efore the mode transition SPL Pin state spacification bit of the standby control register STBC 402 INDEX INDEX The index follows on the next page This is listed in alphabetic order 403 INDEX Index Numerics 12 bit PPG 12 bit PPG Function sese 207 12 bit PPG Control Register 12 bit PPG Control Register 1 RCR21 214 12 bit PPG Control Register 2 RCR22 215 12 bit PPG Control Register 3 RCR23 216 12 bit PPG Control Register 4 RCR24 218 12 bit PPG Timer Block Diagram of 12 bit PPG Timer 209 Block Diagram of Circuitry Terminating at the Pin Associated with the 12 bit PPG Timer IA 212 Example of Operations of 12 bit PPG Timer Functions 219 Functions of 12 bit PPG Timer 206 Notes on Using 12 bit PPG Timer 221 Pin Associated with the 12 bit PPG Timer 211 Program Example for 12 bit PPG Timer 223 Registers Associated with 12 bit PPG Timer 213 16 bit Data Storage State 16 bit Data Storage State in Stack 26 16 bit Data Storage State on RAM 26 16 bit Operand Storage State 16 bit Operand Storage State 26 8 16 bit Capture Timer Counter 8 16 bit Capture Timer Counter of Interrupts lr HAN 183 Block Diagram for 8 16 bit C
202. egister containing the compare value for H width The comparator then maintains outputs at L until a count by the counter is synchronized with the value of the register containing the set cycle period At this time the 12 bit counter is cleared and restarts to count from 00g 12 bit PPG control registers 1 RCR21 and 2 RCR22 These registers comprise bits for count clock selection and bits for setting a compare value for the H width 12 bit PPG control registers RCR23 and 4 RCR24 These registers comprise a bit for specifying whether to enable or disable the 12 bit PPG output and bits for setting a compare value for the cycle period 210 CHAPTER 9 12 BIT PPG TIMER 9 3 Pin of 12 bit PPG Timer This section describes the pin associated with the 12 bit PPG timer and illustrates a block diagram of circuitry terminating at the pin Pin Associated with the 12 bit PPG Timer The pin associated with the 12 bit PPG timer is P37 BZ PPG pin P37 BZ PPG pin This pin functions as a CMOS type P37 general purpose I O port further functioning as 12 bit PPG timer output PPG PPG By setting the output enable bit of the appropriate 12 bit PPG control register RCR23 RCEN to 1 the pin functions as the PPG output pin through which the set cycle period and H width of PPG pulse waveforms are output 211 CHAPTER 9 12 BIT PPG TIMER m Block Diagram of Circuitry Terminating at the Pin Associated with the
203. egment LED connected Figure 4 8 1 Example of the Pins and the 8 segment LED Connected MB89202 V201 F202 F202RA 113 CHAPTER 4 I O PORTS 114 Coding example PDRO EQU DDRO EQU PDR3 EQU DDR3 EQU PDRO 0 PDR3 11111111B DDRO 11111111B DDR3 11111111B Address of port 0 data register Address of port 0 data direction register Address of port 3 data register Address of port 3 data direction register CODE SEGMENT Set POO at L level Set all pins of port 3 at H level Set POO to function as an output port by coding XXXXXXXIB Set all bits of DDR3 such that all pins of port 3 function as an output port CHAPTER 5 TIME BASE TIMER This chapter describes the functions and operations of the time base timer 5 1 Overview of Time base Timer 5 2 Configuration of Time base Timer 5 3 Time base Timer Control Register TBTC 5 4 Interrupt of Time base Timer 5 5 Operations of Time base Timer Functions 5 6 Notes on Using Time base Timer 5 7 Program Example for Time base Timer 115 CHAPTER 5 TIME BASE TIMER 5 1 Overview of Time base Timer The time base timer functions as an interval timer The time base timer is a 21 bit free run counter that counts up in synchronization with the internal count clock at the oscillation frequency divided by 2 The timer also has an interval timer function to select one of four time intervals In addition it provides timer output for oscillation stabilizati
204. ellation of stop mode Stop mode is cancelled by a reset or external interrupt When reset occurs in stop mode the reset operation is performed after oscillation stabilization wait time pin states are initialized by the reset operation When an interrupt request with an interrupt level higher than 11g is generated in an external interrupt circuit in stop mode stop mode is cancelled regardless of the CPU interrupt enable flag CCR I or interrupt level bits CCR IL1 and ILO When stop mode is cancelled and oscillation stabilization wait time has expired a normal interrupt operation is performed Then if interrupts are acceptable interrupt processing is performed Otherwise an instruction following the instruction immediately before transition to stop mode is managed When an external interrupt cancels stop mode part of the peripheral functions are restarted with data stored before the beginning of sleep mode Therefore the initial interval of the interval timer and other similar settings are rendered unknown The peripheral functions must be initialized after returning from stop mode Note Among interrupts only an interrupt request from the external interrupt circuit cancels the stop mode 65 CHAPTER 3 CPU 3 7 4 Standby Control Register STBC The standby control register STBC controls transition to sleep stop modes pin state settings in stop mode and software reset m Standby Control Register STBC Fig
205. en concurrently with the activation of A D conversion AD 1 Note Pins not used as analog inputs can be used as general purpose ports ADI Interrupt request flag bit When A D conversion functions are enabled When A D conversion is completed 1 is set to this bit When this bit and the bit for enabling an interrupt request ADC2 ADIE are 1 an interrupt request is output At write this bit is cleared with 0 When 1 is set to this bit nothing is changed or affected by this ADMV Convertion flag bit This bit indicates that A D conversion is being performed when A D conversion functions are enabled During conversion comparison this bit is set to 1 Note This bit is read only The written value is ignored and nothing is affected by the value RESVO Reserved bit The value during read is not determined Write does not affect operations AD A D conversion activation bit This bit is used to activate A D conversion functions with software In the state where continuous activation is not performed ADC2 EXT 0 when 1 is set to this bit A D conversion functions are activated Notes Even if 0 is written to this bit the operation of A D conversion functions cannot be stopped The read value is always 0 During continuous activation this bit is ignored 267 CHAPTER 12 A D CONVERTER 12 4 2 A D Control Register 2 ADC2 A D control register 2 ADC2 is used
206. ent pins Writing 1 to an appropriate ADEN register bit enables analog input A D Enable Register ADEN Figure 12 4 5 shows the bit configuration of the A D enable register Figure 12 4 5 A D Enable Register ADEN Address bit7 bit6 bits bit4 bits bit2 biti bit0 Initial value 0034y 000000008 RAN RW RAN RW R W RAN RW R W ADE7 to ADEO A D input bits 0 Port input 1 Analog input R W Readable Writable EJ Initial value An A D input port can be used as a general purpose I O port The ADEN register is used to select the port that corresponds to the analog input Set 1 to the corresponding bit in the ADEN register for the port to be used for analog input This prevents the DC pass when the middle level voltage is applied to the A D input port When this register is to be used as the A D input port do not select the bit that indicates use of a pull up resistor from the pull up setting register 271 CHAPTER 12 A D CONVERTER 125 Interrupt of A D Converter A factor for an interrupt of the A D converter is the following e Completion of conversion when A D conversion functions are enabled m interrupt when A D Conversion Functions are Enabled When A D conversion is completed the interrupt request flag bit ADC1 ADI is set to 1 At this time if the bit for enabling an interrupt request is enabled ADC2 ADIE 1 an interrupt request to the CPU IRQ8 occurs Write 0 to the ADI bit using the routi
207. er SRC The SRC register controls the UART data transfer speed baud rate This register selects the input clock and specifies the transfer rate to be applied when the baud rate generator is used Serial status and data register SSD The SSD register indicates UART transmitting receiving status status in an error parity received or data received at bit8 This register also enables disables interrupts or specifies and confirms parity transmitted or data transmitted with bit8 Serial input data register SIDR The SIDR register stores received data Serial input is converted then stored into this register However the most significant bit of 9 bit data is stored in the SSD RD8 RP bit Serial output data register SODR The SODR register specifies data to be transmitted Data written into this register is converted to serial format then output The most significant bit of 9 bit data is set in the SSD TD8 TP bit Clock generator The clock generator generates the transmit receive clock in accordance with the dedicated baud rate generator external clock and 8 bit PWM timer output Reception control circuit The reception control circuit consists of the received byte counter start bit detection circuit and received parity handling circuit The received byte counter takes count of received data When a unit of data that corresponds to the specified data length is fully received an interrupt request is generated The
208. er the written data is held in the output latch but is not output to the pin The value state of the pin can be read by reading the PDR6 register Operation when a reset is performed When the CPU is reset the bits of the DDR6 register are initialized to 0 Thus all output transistors become OFF and the pins become Hi Z However CPU resets do not initialize the PDR6 register If a pin is used as an output port after the reset reinitialize the PDR6 register to contain new output data in the bit position corresponding to the pin and then set the corresponding bit of the DDR6 register so that the pin will function as an output port Operation in stop mode When the pin state setting bit of the standby control register STBC SPL is 1 and when the stop mode is entered the output transistor is turned OFF and the pin becomes Hi Z because the output transistor is forcibly turned OFF without respect to the value existing on the DDR6 register in the bit position corresponding to the pin Input remains fixed to prevent leaks by input open Table 4 6 4 summarizes the operating modes of the pins of port 6 105 CHAPTER 4 I O PORTS Table 4 6 4 Operating Modes of Pins of Port 6 Pinname Normal operation sleep stop SPL 0 Stop SPL 1 P60 P61 General purpose I O port Note When the pull up resistor is selected by using the pull up setting register the pin state will be H level instead of Hi Z in stop mod
209. er is turned on Therefore the time base timer makes oscillation stabilization wait time after the resonator starts operating The appropriate oscillation stabilization time must be selected according to the type of resonator connected to the resonator clock generator See Section 3 6 1 Clock Generator Notes on peripheral functions the time base timer supplies to the clock When entering the modes in which oscillation stops the counter is cleared and the time base timer stops operating The clock from the time base timer may have a shorter level period or longer L level period up to half the clock cycle when the counter of the time base timer is cleared because the clock starts operating from the initial state The clock for the watchdog timer also starts operating from the initial state but the watchdog timer operates at a normal cycle because the watchdog timer counter is cleared at the same time 124 CHAPTER 5 TIME BASE TIMER 5 7 Program Example for Time base Timer Programming examples for the time base timer are shown below m Programming Examples for Time base Timer Processing specification Repeatedly generate an interval timer interrupt at intervals of oP fae Fox oscillation frequency The time interval is approximately 21 0 ms operating at 12 5 MHz Coding examples TBTC TBOF ILR2 INT V IRQ7 EQU 0000AH Address of time base timer control register EQU TBTC 7 Definiti
210. erations in Active Mode In active RUN mode the oscillator is generating a clock The CPU time base timer and other peripheral circuits operate using the clock In active mode all clock speeds except the time base timer clock speed can be changed using gears In active mode specifying standby mode results in a transition to sleep mode or stop mode Operations always start in RUN mode after a reset any type Operating modes are cancelled by a reset Note Do not rewrite the values in the oscillation stabilization wait time selection bits SYCC WT1 and WTO while the clock is waiting for stabilization of oscillation Using the system clock monitor bits change the values in these bits after checking that SYCC SCM is 1 59 CHAPTER 3 CPU 3 6 5 Oscillation Stabilization Wait Time Oscillation stabilization wait time is to be applied when power is turned on to start the clock in RUN mode while the clock is stopped in stop mode B Oscillation Stabilization Wait Time A ceramic or crystal resonator normally requires several or several tens of milli seconds from oscillation start to oscillation stabilization at a specific cycle oscillation frequency Thus CPU operation must be prohibited immediately after the start of oscillation and the clock is to be supplied to the CPU when oscillation is stable following the expiration of oscillation stabilization wait time The period during which oscillation becomes stable
211. ernal Interrupt Circuit 2 Control Register EIE2 Address bit7 bit6 0036H IE20 000000008 R W RW bits bit4 bits bit2 bit RAN RW RW RW RW RW IE27 to IE20 External interrupt request enable bits 0 Disables external interrupt request outputs 1 Enables external interrupt request outputs R W Readable Writable E Initial value Table 11 4 1 Correspondence between the Bits of the External Interrupt 2 Control Register Register 250 EIE2 and the External Interrupt Pins Bit name External interrupt pin CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT 2 LEVEL Table 11 4 2 Functions of the Bits of the External Interrupt 2 Control Register EIE2 Bit name Function IE27 to IE20 External interrupt input enable bits These bits enable or disable the interrupt inputs to external interrupt pins INT20 to INT27 When one of these bits is set to 1 the corresponding external interrupt pin functions as an external interrupt input pin and accepts external interrupt inputs When the bit is set to 0 the corresponding pin functions as a general purpose port but does not accept external interrupt inputs Notes When using a pin as an external interrupt pin write 0 in the port 0 data direction register DDRO in the bit corresponding to the pin so that the pin serves inputs only Regardless of the external interrupt input enable bit state the state of the external interrupt
212. errupt circuit 1 and illustrates a block diagram of circuitry terminating at the pins with reference to the registers and external interrupt triggering m Pins Associated with External Interrupt Circuit 1 The pins associated with external interrupt circuit 1 are the P34 TO INTIO to P36 INTI2 pins P34 TO INT10 pin This pin functions as a general purpose I O dedicated port and may also serve 8 16 bit capture timer outputs TO and external interrupt inputs hysteresis inputs INT10 If the timer 1 control register TCRO disables 8 16 bit capture timer outputs and by the port data direction register DDR3 the pin is set to function as an input port only The pin can also function as an external interrupt input pin INT10 When external interrupt 1 control register 1 EIC1 sets edge detection to OFF however no external interrupt requests are generated and when interrupt request outputs are disabled no interrupt requests are output The pin state can be read directly from the port data register PDR3 at any time P35 INT11 and P36 INT12 pins These pins function as a general purpose I O dedicated port P35 P36 and may also serve external interrupt inputs hysteresis inputs INT11 INT12 If by the port data direction register DDR3 these pins are set to function as an input port only they also function as external interrupt input pins INT11 INT12 When external interrupt 1 control registers 1 and 2 EIC2
213. errupt input mode Set a bit of the DDRO register to 0 the bit corresponding to a pin of port 0 that is to serve as an external interrupt input pin to set the pin to function as an input port The value state of the pin can be read by reading the PDRO register regardless of whether external interrupt inputs or interrupt request outputs are enabled or disabled Operation in analog input mode To use a pin of port 0 as analog input and to inhibit output transistor operation set the bit corresponding to the analog input pin to 0 on the DDRO register The value state of the pin can be read by reading the PDRO register Set the bit of the ADEN register of the A D converter to 1 the bit corresponding to the analog input pin in use Operation when a reset is performed When the CPU is reset the bits of the DDRO register are initialized to 0 Thus all output transistors become OFF and the pins become Hi Z However CPU resets do not initialize the PDRO register If a pin is used as an output port after the reset reinitialize the PDRO register to contain new output data in the bit position corresponding to the pin and then set the corresponding bit of the DDRO register so that the pin will function as an output port 82 CHAPTER 4 I O PORTS Operation in stop mode When the pin state setting bit of the standby control register STBC SPL is 1 and when the stop mode is entered the output transistor is turned OFF and th
214. errupt level bits in the condition code register CCR IL1 and ILO are normally set to 115 e The ILRI to registers are write only enabled and thus the bit manipulation instructions SETB and CLRB cannot be used 36 CHAPTER 3 CPU 3 4 2 Steps in the Interrupt Operation When an interrupt request is generated in a peripheral function the interrupt controller notifies the CPU of its interrupt level If the CPU can accept an interrupt the CPU temporarily stops the program that is handling and starts the interrupt processing routine B Steps in the Interrupt Operation The steps for processing an interrupt are occurrence of a source of an interrupt in a peripheral function designation of the interrupt request flag bit request F F check on the interrupt request enable bit enable F F check on the interrupt level ILRI 2 3 or 4 and CCR IL1 and ILO check on another request with the same level and check on the interrupt enable flag CCR I Figure 3 4 2 shows the steps in the interrupt operation Figure 3 4 2 Steps in the Interrupt Operation Interrupt processing routine Update of IL Request cleared Initial setting Interrupt for interrupt processing Execution of main program 2 e 2 E gt I Peripheral oo D After a reset all interrupt requests are prohibited Initialize the peripheral functions that generate interrupts using a initialization progr
215. errupt request flag bit ADC1 ADI is not set Conversion time Changing the oscillation frequency or clock speed gear functions affects the conversion speed of A D conversion functions Input clock of continuous activation The output of an 8 16 bit capture timer counter is affected by gear functions The output of a time base timer is not affected by gear functions Clearing a time base timer affects cycles Since the output of an 8 16 bit capture timer counter is the output of the 16 bit mode the 8 bit mode cannot be used 276 CHAPTER 12 A D CONVERTER 12 8 Program Example for A D Converter This section shows a program example of the 10 bit A D converter m Program Example of the A D Conversion Functions Processing specifications The analog voltage to be applied to the ANO pin is converted to digital voltage through software activation In this example completion of conversion is detected in a loop in the program without using interrupts Coding example PDR4 EQU ADCI EQU ADC2 EQU ADDH EQU ADDL EQU ADEN EQU ANO EQU ADEO EQU ADI EQU ADMV EQU AD EQU EXT EQU CSEG SETB CLRI SETB CLRB AD WAIT BBS MOV MOV SETI SETB AD CONV BBS CLRB 000FH 0030H 0031H 0032H 0033H 0034H PDR4 0 ADEN 0 ADC1 3 ADCI 2 ADCI 0 ADC2 1 ANO ADEO EXT ADMV AD WAIT ADC1 00000000B ADC2 00000001B AD ADMV AD_CONV ADI Address of port 4 data register 4 Address of A D control
216. errupt request flag 201 CHAPTER 8 8 16 BIT CAPTURE TIMER COUNTER m Program Example of Counter Function 202 Processing specifications In the 16 bit mode timer 0 and timer 1 are used to generate an interrupt whenever the external clock to be input to the EC pin is counted 5 000 times 138855 The sample program for reading the 16 bit counter value when the counter is in operation is shown below READ 16 Coding example DDR3 TCCR TCRI TCRO TDRI TDRO TIFO ILRI INT_V IRQD READ 16 MOV CLRI MOV MOV MOV MOV MOV MOVW MOVW CMPW BEQ 000DH 0019H 001AH 001BH 001CH 001DH TCRO 7 007CH ABS OFFFOH WARI DDR3 00000000B ILR1 210111111B TDRO 088H TDR1 013H TCR1 200001110B TCRO0 201101111B A TDRI A TDRI A RET16 Address of port 3 direction register Address of capture control register Address of timer control register Address of timer 0 control register Address of timer data register Address of timer 0 data register Defines the timer 0 interrupt request flag bit Address of interrupt level setting register 2 DATA SEGMENT Sets the interrupt vector CODE SEGMENT The stack pointer SP etc is already initialized Sets the EC pin to input Disables the interrupt Sets the interrupt level to 2 Sets the counter value and the lower 8 bits of the compare value Sets the counter value and the higher 8 bits of the compare value
217. erval 1 x A FcH x register value 1 4 12 5 MHz x 221 1 71 0 us Output frequency FcH 1 x 8 x register value 1 12 5 MHz 8 x 221 1 7 04 kHz m PWM Timer Functions The PWM timer functions have an 8 bit resolution and can control the level width and L level width of one cycle Because the resolution is 1 256 a pulse can be output at a duty ratio of 0 to 99 6 The frequency of the PWM wave can be selected from four types The low pass filter can be connected to the output and used as the D A converter Table 7 1 2 shows the frequency of the PWM wave that can be set by PWM timer functions Figure 7 1 1 is a configuration example of the D A converter Table 7 1 2 Frequencies of the PWM Wave that can be Set by the PWM Timer Functions Internal clock Output of an 8 16 bit capture timer counter 2 to DIU NET to Count clock cycle 14 18 2 INST 2 EINST 14 18 PWM wave cycle 22 26 2 tmsT 2 INST tsr Instruction cycle Affected by the clock mode and others tgx r Output frequency of an 8 16 bit capture timer 137 CHAPTER 7 8 BIT PWM TIMER Figure 7 1 1 Configuration Example of the D A Converter with the PWM Output and a Low Pass Filter PWM output Analog output Va PWM pin R Analog output waveform um Relationship between analog output voltage and PWM output waveform Va Vcc TH T Tr represents the a
218. es incorporates two bytes for each register Control circuit part This part compares the data held in the address set registers and the actual data on the address bus If it detects a match it sets the data in the data setting register to the data bus The control circuit part can control the operation by the address comparison EN register 349 CHAPTER 16 WILD REGISTER FUNCTION 16 3 Registers of the Wild Register Function Figure 16 3 1 shows the registers related to the wild register function m Registers Related to the Wild Register Function Figure 16 3 1 Registers Related to Wild Register Function WRDRO WRDR1 Data setting register Address bit7 bit6 bit5 bit4 bit3 bit2 bit bito Initial value 00424 000 XXXXXXXX p 004544 R W R W R W R W R W R W R W R W WRARHO WRARH1 Higher address set register Address bit7 bit6 bit5 bit4 bit3 bit2 biti bito Initial value 00401 RAO8 XXXXXXXX p 0043 R W R W R W R W R W R W R W R W WRARLO WRARL1 Lower address set register Address bit7 bit6 bit5 bit4 bit3 bit2 bit bito Initial value 0041H XXXXXXXX p 0044H R W R W R W R W R W R W R W R W WREN Address comparison EN register Address bit7 bit6 bit5 bit4 bit3 bit2 bit bito Initial value 0464 enon ENDO R W R W WROR Data test set register Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bitO Initial value 0474 RESVt RESVO R W R W
219. essing for the Products with and without a Step down Circuit Product name MB89V201 MB89202 Operating voltage 27 V to 5 5 V 2 2 V to 5 5 V Step down circuit Not contained Not contained MB89F202 F202RA 3 5 V to 5 5 V Contained These products use the same internal resources However the operation sequence after power on reset depends on whether a product contains a step down circuit Figure 2 1 1 shows the sequence of operations after the power on reset for each model CHAPTER 2 HANDLING DEVICES 20 Figure 2 1 1 Operation Sequences after Power on Reset between Product Types Power supply Vcc Step down circuit stabilization time 217 Oscillation stabilization wait time 218 CPU operation of product with a step down circuit MB89F202 F202RA i i Oscillation stabilization iwait time 2 8 Foy CPU operation of product without a step down circuit MB89202 and MB89V201 Start of CPU operation of Start of the CPU operation of product without a step down product with a step down circuit reset vector circuit reset vector FcH Main oscillation frequency As shown in Figure 2 1 1 the start of CPU operation of a product with a step down circuit is slower than that of the product without a step down circuit This is because time is required for the step down circuit to stabilize prior to normal operation of the step down circuit CHAPTER 3
220. et a value that falls within the range of 000000000010 to 111111111111 Because buzzer outputs to the P37 BZ PPG pin precede 12 bit PPG outputs to this pin if the pin is used as the PPG pin turn the buzzer outputs off and set the RCEN bit such that PPG outputs are enabled 217 CHAPTER 9 12 BIT PPG TIMER 9 4 4 12 bit PPG Control Register 4 RCR24 The 12 bit PPG control register 4 comprises bits for setting a cycle period of 12 bit PPG waveform outputs 12 bit PPG Control Register 4 RCR24 Figure 9 4 5 12 bit PPG Control Register 4 RCR24 Address bit7 bit6 bit5 bit4 bit3 bit2 bit bito Initial value RW RW RW RW RW RW SCL11 to SCL6 Cycle period setting bits Compare value for the cycle period of 12 bit PPG outputs R W Readable Writable Unused Table 9 4 4 Explanation of Functions of Each Bit in 12 bit PPG Control Register 4 RCR24 Bit name Function e Bit value is undefined when being read Unused bits Written value does not affect other operations These bits are used to set the number of counts corresponding to the cycle period of 12 bit PPG waveform outputs the compare value for cycle period and the contents SCL11 to SCL6 of these bits and the SCLO to SCLS bits of RCR23 are compared with a count by the Cycle period counter setting bits Note Set a value that falls within the range of 0000000000105 to 111111111111 002 to 218 CHAPTER 9 12
221. etected However when the framing error occurs the flag goes on regardless of the final data bit An interrupt request to the CPU is generated when the flag goes on and interrupt request is enabled If the reception interrupt is enabled SSD RIE 1 an interrupt request to the CPU IRQ5 is generated When the RDRF bit goes on the received data is transmitted to the SIDR register Figure 13 6 7 to Figure 13 6 9 show the reception operations when parity is not used and the number of stop bits is 1 in operating mode 2 Figure 13 6 7 Reception Operations in Operating Mode 2 START Reception interrupt Figure 13 6 8 Operations in Operating Mode 2 when the Overrun Error Occurs START 0 RDRF 1 reception buffer full ORFE Reception interrupt 309 CHAPTER 13 UART 310 RDRF 0 ORFE Reception interrupt Figure 13 6 9 Operations in Operating Mode 2 when the Framing Error Occurs ISTART 0 Note After initialization is cancelled due to a reset time for 11 shift clock cycles is required to initialize the internal controller Therefore be sure to enable the UART prescaler operation PREN 1 using the oscillation frequency register after a reset CHAPTER 13 UART 13 7 Program Example for UART This section provides program example for UART m Program Example for UART Program specifications Coding example Serial data transfer is implemented using the UART communication functions T
222. external interrupt 1 The resource is a hysteresis input General purpose CMOS I O ports This pin also serves as the buzzer output pin or the 12 bit PPG output pin 20 General purpose CMOS I O ports This pin also serves as the 8 bit PWM timer output pin 24 to 27 General purpose CMOS I O ports These pins can also be used as N ch open drain ports These pins also serve as 10 bit A D converter analog input pins 21 to 23 23 to 25 General purpose CMOS I O ports 32 34 Power supply pin 10 10 Power GND pin 16 17 MB89F202 F202RA Capacitance pin for regulating the power supply Connect an external ceramic capacitor of about 0 1 uF MB89202 This pin is not internally connected It is unnecessary to connect a capacitor DIP 32P M06 2 FPT 34P M03 Internally connected pins Be sure to leave it open CHAPTER 1 OVERVIEW 1 8 Circuit Types Table 1 8 1 describes the I O circuit types The letters in the circuit column shown in Table 1 8 1 correspond to the letters in the circuit type column shown in Table 1 7 1 Circuit Types Table 1 8 1 I O Circuit Types 1 2 Circuit Remarks At an oscillation feedback resistance of approximately 500 Input enable Port Resource CMOS output Hysteresis input Pull up resistor optional available for P ch with
223. external reset is cancelled after oscillation stabilization wait time has expired Software reset and Active tode The reset operation is performed following the generation of a 4 watchdog reset instruction cycle reset When power is The reset operation is performed after power is turned on and Power on reset Sew E wer turned on oscillation stabilization wait time has expired External reset in active mode does not apply oscillation stabilization wait time The reset operation is performed after cancellation of external reset 44 CHAPTER 3 CPU 3 5 1 Reset Flag Register RSFR The reset flag register RSFR allows confirmation of the source for a generated reset m Configuration of the Reset Flag Register RSFR Figure 3 5 1 Configuration of Reset Flag Register RSFR Address pit7 bit6 bit5 bit4 bit bit bito Initial value 000En R R R R Software reset flag bit When written Does not affect 1 The source is software reset Operations Watchdog reset flag bit WDOG When writen not affect The source is watchdog reset operations External reset flag bit When written Does not affect The source is external reset operations Power on reset flag bit PONR Whenread When written read When Whenread When written P Doesnotaffect The source is power on reset
224. external shift clock Serial I O transfer start bit input wait state When serial I O transfer terminates this bit is set cleared to 0 and the SIOF bit is set to 1 If this bit is set to 0 during serial I O transfer SST 1 serial I O transfer is suspended When serial I O transfer is suspended it is necessary to reset the SDR of the data output side and restart data input side transfer clear the shift clock counter 322 CHAPTER 14 8 BIT SERIAL I O 14 4 2 Serial Data Register SDR The serial data register SDR retains 8 bit serial I O transfer data The SDR functions as a transmission data register at serial output operation It functions as a reception data register at serial input operation Serial Data Register SDR Figure 14 4 3 shows the bit structure of the SDR Figure 14 4 3 Serial Data Register SDR Address bit7 bit6 bit5 bit4 bit3 bit2 bit bitO Initial value R W R W R W R W R W R W R W R W R W Readable and Writable X Undefined At serial output operation The SDR functions as a transmission data register at serial output operation When serial I O transfer is started SMR SST 1 the 8 bit serial data written to the SDR is transferred Transmission data does not remain in the SDR because it is shifted out via serial I O transfer At serial input operation The SDR functions as a reception data register When serial I O transfer is started SMR SST 1 the serial
225. f MB89202 F202RA Series The MB89202 F202RA series contains general purpose single chip microcontrollers that incorporate a full range of peripheral functions such as A D converter UART PWM timer PPG capture timer counter and external interrupts as well as a compact instruction set m Features of MB89202 F202RA Series F MC 8L CPU core Instruction set most suitable for controllers Multiplication and division instruction e 16 bit operation Branch instruction by bit test e Bit operation instruction and others 4 system timers e 8 16 bit capture timer counter 8 bit capture timer counter 8 bit timer or 16 bit capture timer counter 8 bit PWM timer also available as an interval timer e 21 bit time base timer e Watchdog timer 10 bit A D converter 10 bit A D x 8 channels e Activation by 8 16 bit capture timer counter output is possible Programmable pulse generator PPG e Pulse width and cycle are software selectable 12 bit PPG UART 6 7 or 8 transfer data length 8 bit serial I O e Available when switched from UART LSB first MSB first selectability External interrupts e External interrupt 1 edge detection x 3 pins has three independent inputs and can be used for wake up from low power consumption mode The edge detection can be selected from rising edge falling edge and both edge modes CHAPTER 1 OVERVIEW e External interrupt 2 level detection x 8 pins 1 chan
226. f Serial Output Functions ssssssssssssssseseeeee entente renis 325 14 7 Operations of Serial Input Functions nennen nennen nens nnns enne 327 14 8 8 Bit Serial I O Operation in Each Mode 329 14 9 Notes on Using 8 Bit Serial l Q ien ie rte e ipt Sede Reveal Erie et Heo ha thea 333 14 10 Example of 8 Bit Serial l O Connection ssssssssssssseseeeeeneen enne nennen 334 14 11 Program Example for 8 Bit Serial l O essen nnne 336 CHAPTER 15 BUZZER OUTPUT 339 15 1 Overview of the Buzzer Output sen nnne 340 15 2 Configuration of the Buzzer Output sse eene nnne nsn nennen nnne renis 341 15 3 Pinrofthe Buzzer rece ava e dore ege Le de urbane ae ae 342 15 4 Buzzer Register BZCR sse nennen enter inns nennen 343 15 5 Program Example for Buzzer Output ssssssssssssesseseeneee nennen tenerent nennen nnns enne 345 CHAPTER 16 WILD REGISTER FUNCTION eeeeeeeeeeeeeee nennen nnn nennen 347 16 1 Overview of the Wild Register Function essssssssssseeee eene nennen eren 348 16 2 Configuration of the Wild Register Function sssssssssseseseeeenennen nennen nene 349 16 3 Registers of the Wild Register Function
227. f outputs 12 bit PPG Control Register 3 RCR23 Figure 9 4 4 12 bit PPG Control Register 3 RCR23 Address bit7 bit6 bit5 4 bit3 bit bito Initial value R W RW RW RW RW RW RW SCL5 to SCLO Cycle period setting bits Compare value for the cycle period of 12 bit PPG output Output enable bit Output disabled counter cleared Output enabled with count operation starting R W Readable Writable Unused Initial value 216 CHAPTER 9 12 BIT PPG TIMER Table 9 4 3 Explanation of Functions of Each Bit in 12 bit PPG Control Register 3 RCR23 Bit name Function RCEN Output enable bit When this bit is 0 the P37 BZ PPG pin functions as a general purpose port P37 when the bit is 1 the pin functions as a 12 bit PPG output pin PPG When is written for this bit the counter is cleared and its operation stops when is written the count operation starts Even if PPG outputs are enabled by this bit setting buzzer outputs if enabled have priority Unused bit Bit value is undefined when being read e Written value does not affect other operations SCL5 to SCLO Cycle period setting bits Note These bits are used to set the number of counts corresponding to the cycle period of 12 bit PPG waveform outputs the compare value for the cycle period and the contents of these bits and the SCL6 to SCL11 bits of RCR24 are compared with a count by the counter Note S
228. functions Because the output level of the pin P50 PWM pin can be inverted for each interrupt the square wave of any frequency can also be output Aninterval timer operation from the cycle of the count clock to 25 times cycle is possible The count clock can be selected from four types Table 7 1 1 shows the range of intervals and square wave output Table 7 1 1 Range of Intervals and Square Wave Output Count clock cycle Interval Square wave output Hz lt st to 1 2tinst to 1 2 Internal count clock I uwsr 2 iysr to 2r 1 25 to 1 2 tpi 2ttNsT 2tinst to OM 1 220 to 1 One 8 16 bit timer count clock tsr Instruction cycle Affected by the clock mode and others text Output cycle of an 8 16 bit capture timer 136 CHAPTER 7 8 BIT PWM TIMER Note Calculation example of intervals and square wave frequency The following expression is the interval when the count clock cycle is set to 1 and when oscillation frequency Foy of 12 5 MHz and a PWM compare register COMR value of DDy 221 are set Another expression is the frequency of the square wave output from the PWM pin that is operated continuously without changing the COMR register value However the values are true when the maximum speed clock of the normal mode is selected CS1 CSO 11g 1 instruction cycle 4 Fcp with the system clock control register SYCC Int
229. g 49 Notes on Setting Standby Mode 70 Operation in Standby Mode and at Halfway Stop E 197 Operations for Selecting Memory Access Mode TP 72 Operations in Active Mode 59 Operations in Each Clock Mode 58 Operations in Standby Mode 63 Operations in the Standby Mode and at a Suspension En IRE 152 Operations Related to Sleep Mode 64 Operations Related to Stop Mode 65 Pin States in Each Operation Mode 402 Reception Operations Operating Mode 0 1 or 3 PME 307 Reception Operations Operating Mode 2 Only 309 Single chip Mode sse 72 States of Pins after the CPU Reads the Mode Data n DP REN 50 Theory of Operation for Operating Mode 0 1 2 and 3 TET 305 Transition to Standby Mode and Interrupt 70 Transmission Operations in Operating Mode is OM 208 t euet 306 Multiple Interrupts Multiple Interrupts 39 N Notes Notes on Setting Standby Mode 70 Notes on Using 12 bit PPG Timer 221 Notes on Using 8 bit PWM Timer 155 Notes on Using 8 bit Serial I O 333 Notes on Using the 8 16 bit Capture Timer Counter 198 Notes on Using the A D Converter 275 Notes on U
230. g edge of a pulse input to the INT10 pin and generates an interrupt Coding example DDR3 EICI TCR2 ILR1 EIRO 5101 5100 EIEO INT V IRQI EQU EQU EQU EQU CLRB PUSHW XCHW 000DH 0024H 0020H 007BH EIC1 3 EIC1 2 EIC1 1 EIC1 0 ABS OFFFAH WARI TCR2 00000000B DDR3 00000000B ILR1 11111110B 5101 5100 EIEO EIEO A A T Address of port data direction register DDR External interrupt control register 1 Address of 8 16 bit capture timer output control register Setting of interrupt level setting register 1 Definition of external interrupt request flag bit Definition of edge polarity selection bits Definition of edge polarity selection bits Definition of interrupt request enable bit DATA SEGMENT Interrupt vector INT1 setting CODE SEGMENT Stack pointer SP is assumed to have been initialized Disable interrupts Clear external interrupt request flag Set pin P34 TO INTI10O to serve port inputs Set P34 to serve inputs only Set interrupt level at 2 Select rising edge Clear external interrupt request flag Enable interrupt request outputs Enable interrupts Clear external interrupt request flag INTO 241 CHAPTER 10 EXTERNAL INTERRUPT CIRCUIT 1 EDGE PUSHW User processing POPW A XCHW A T POPW A RETI ENDS END 242 CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT 2 LEVEL This chapter describes
231. g register the pin state will be H level pull up state instead of Hi Z during stop SPL 1 During a reset however the pull up is invalid and the pin remains at Hi Z Figure 4 3 2 shows the pull up resistor settings assigned to the values of the bits of the port 3 pull up register Figure 4 3 2 Pull up Setting Register PUL3 Address bit7 bit6 bit5 bit4 bit3 bit2 bit bitO Initial value 0071n puta rutas eutss eutsa Pucso eutse Pusr eut 000000006 R W R W R W R W R W RW RW PUL33 PUL32 PUL31 P33 pull up OFF P32 pull up OFF P31 pull up OFF P30 pull up OFF P33 pull up P32 pull up ON P31 pull up ON P30 pull up ON 0 P37 pull up OFF P36 pull up OFF P35 pull up OFF P34 pull up OFF P37 pull up ON P36 pull up ON P35 pull up ON P34 pull up ON R W Readable and Writable Initial value 87 CHAPTER 4 I O PORTS 4 3 2 Operations of Port 3 Functions This section describes the operation of port 3 B Operation of Port Operation in output port mode When 1 is written for a bit of the DDR3 register the bit corresponding to a pin of port 3 the pin functions as an output port In output port mode output transistor operation is enabled and output latch data is output to the pin Once data has been written into the PDR3 register the written data is held in the output latch and output to the pin as it is The value state of the
232. have no significance regardless of the value output from the peripheral and the output enabled Table 4 5 3 lists the functions of the port 5 registers Table 4 5 3 Functions of Port 5 Registers Register name Port 5 data When being read Pin state is L level When being written Output latch of 0 is set and L level is output to the pin in output port mode register PDR5 Pin state is H level Output latch of 1 is set and the pin in output port mode is set at Hi Z Read Write CHAPTER 4 I O PORTS Address Initial value Port 5 data direction Input port pin The pin is set to function as an input pin with output transistor operation disabled register DDR5 Output port pin R W Readable Writable X Undefined The pin is set to function as an output pin with output transistor operation enabled Port 5 pull up setting register PUL5 When the ON setting of the pull up resistor is selected by using the pull up setting register the pin state will be level pull up state instead of Hi Z during stop SPL 1 During a reset however the pull up is invalid and the pin remains at Hi Z Figure 4 5 2 Pull up Setting Register PUL5 Address bit bit6 bits bit4 bit3 biti bitO 0724 1 1 gt Puso R W Initial value 0 P50 pull up OFF P50 pull up ON R W Readable Writable Unu
233. he SDR in synchronization with the rising edge of the selected internal shift clock In this case the SDR of the transfer destination serial output side must already be set and the transfer destination must be in the external shift clock input wait state 327 CHAPTER 14 8 BIT SERIAL I O Serial input operation using external shift clock Serial input operation with the external shift clock requires the settings shown in Figure 14 7 2 Figure 14 7 2 Settings Required for Serial Input Operation using External Shift Clock bit7 bite bit5 bit4 bit3 bit2 bit bitO SMR SIOF SIOE SCKE SOE CKS1 CKSO BDS SST 9 0 x 1 1 9 1 SDR Reception data storage DDR3 Used bit Unused bit When serial input operation is allowed the value of the SI pin is captured and held in the SDR in synchronization with the rising edge of the external shift clock When serial input is completed immediately read the SDR and allow serial input operation SMR SST 1 to prepare for the input of the next data In this case when the 8 bit serial I O is idle state in which it is waiting for the output of the next data keep the external shift clock at a level Figure 14 7 3 shows 8 bit serial input operation Figure 14 7 3 8 bit Serial Input Operation For MSB first bit7 bit6 bit5 bit4 bit3 bit2 bit1 bitO pin SDR 05 a C3 C3 C9 SIOF bit Transfer start Interrupt request SST bit Automatic
234. he P30 UCK SCK P31 UO SO and P32 UI SI pins are used for communication The transfer rate is set to 300 bps using the internal baud rate generator 13g is transmitted from the UO pin and data is received by interrupts The baud rate is the oscillation frequency Foy 12 5 MHz at the maximum gear speed 1 instruction cycle 4 The clock divider is 2 5 1 375 bps 8320 tjs PDR3 DDR3 SSEL SMC SRC SSD EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU DSEG ORG CLRI MOV MOV MOV MOV MOV 000CH 000DH 003BH 0028H 0029H 002AH 002BH 002BH 002CH 007CH ABS OFFEEH WARD WARII ILR2 11101011B UPC 11111010B SSEL 00000000B DDR3 00000000B SMC 01011011B Port data register address Port direction register address Serial selection register address Serial mode control register address Serial rate control register address Serial status and data register address Serial input data register address Serial output data register address Clock divider selection register address Interrupt level setting register address DATA SEGMENT Reception interrupt vector setting Transmission interrupt vector setting CODE SEGMENT The stack pointer SP and related components have to be initialized Disable interrupts Set an interrupt level level 1 Allow operation with the clock whose frequency is divided by 2 5 Select UART Set the UI pin as the input pin
235. he pin stored in either the 1 or EIC2 registers in the appropriate bit position SLOO to SL21 one of the external interrupt request flag bits EIRO to EIR2 corresponding to the pin is set to 1 External interrupt 1 control registers EIC1 EIC2 The and EIC2 registers comprise bits for edge selection for enabling or disabling interrupt requests and for confirming an interrupt request Triggers that cause external interrupt circuit 1 to generate an interrupt request IRQO When a signal with an edge or edges corresponding to the selected edge polarity is input to the INT10 pin for external interrupt circuit 1 if interrupt request outputs are enabled EICI EIEO 1 external interrupt circuit 1 generates an IRQO interrupt request e RQI When a signal with an edge or edges corresponding to the selected edge polarity is input to the INT11 pin for external interrupt circuit 1 if interrupt request outputs are enabled EICI EIEI 1 external interrupt circuit 1 generates an IRQI interrupt request e RQ2 When a signal with an edge or edges corresponding to the selected edge polarity is input to the INT12 pin for external interrupt circuit 1 if interrupt request outputs are enabled EIC2 EIE2 1 external interrupt circuit 1 generates an IRQ2 interrupt request 228 CHAPTER 10 EXTERNAL INTERRUPT CIRCUIT 1 EDGE 10 3 Pins of External Interrupt Circuit 1 This section describes the pins associated with external int
236. he vector table via the vector addressing This instruction is one byte so using it for the frequently used subroutines enables the entire program size to be smaller Figure B 2 7 shows the overview Figure B 2 7 Executing Example of CALLV 3 Before execution After execution PC sp iam Hea se 323 12324 12324 1233H 1233H FFC6H FFC6H FFC7H FFC7H When this instruction is executed the contents of the PC to be saved in the stack area are not the address holding the operation code of this instruction Instead they comprise the address holding the next instruction In Figure B 2 7 therefore the value saved in the stack 12324 and 1233 is the same as the address holding the operation code next to vet return address i e 56794 390 B 3 Bit Manipulation Instructions SETB and CLRB Some registers of peripheral functions have bits that perform a read operation different from ordinary read for a bit manipulation instruction m Read modify write Operation The bit manipulation instructions can set 1 SETB to the specified bit in a register or RAM or clear it to 0 CLRB Because the CPU handles the data in 8 bits however it actually reads the 8 bit data modifies the specified bit and then writes it back to the original address This series of operations is called read modify write operation Table B 3 1 shows the bus operation at bit manipulation instructions Table B 3 1 Bus Operation at
237. hes the value set in the data register comparator data latch the interrupt request bit TCRO TIFO or TCR1 TIF1 of the timer 0 control register is set to 1 and the count operation is started at 00g If the counter value matches the value set in the data register when timer 0 is being used the output of the square wave output control circuit toggles When square wave output is allowed TCR2 PEN and timer 0 is set to output selection TCR2 TSEL 0 a square wave is output from the timer output pin TO If the counter value matches the value set in the data register when timer 1 is being used the output of the square wave output control circuit toggles When square wave output is allowed TCR2 PEN and timer 1 is set to output selection TCR2 TSEL 1 a square wave is output from the timer output pin TO Figure 8 6 3 shows interval timer function operation in the 8 bit mode CHAPTER 8 8 16 BIT CAPTURE TIMER COUNTER Figure 8 6 3 Interval Timer Function Operation in 8 bit Mode Timer 0 Comparison Counter value Comparison value H i TDRO value 0 gt 1 TDRO Clear by program value TIFO bit H Start Match Match Match Counter clear 2 JA JL TSTRO bit TO pin EE T If the data register is rewritten when the counter is in operation the interval timer function becomes valid from the next cycle When timer 0 is started or when a match is detected the c
238. i Initial value 0019H CPIF CFCLR CPIEN CCMSK TCMSK EDGS EDGSO RESV 000000006 R RW RW RW RW RW RW RW Capture input selection bit Operation is not affected at all Selection of both falling and rising edges Compare match counter clear mask bit The counter is cleared per compare match The counter is not cleared at compare match CCMSK Counter clear mask bit at capture operation The counter is cleared when a capture edge is detected The counter is not cleared when a capture edge is detected CPIEN Capture interrupt request enable bit 0 Capture interrupt request output is prohibited Capture interrupt request output is allowed Capture edge detection flag clear bit Not affected at read always The capture edge detection flag is cleared Capture edge detection flag bit 0 No capture edge was detected A capture edge was detected R W Readable Writable R Read only E Initial value 171 CHAPTER 8 8 16 BIT CAPTURE TIMER COUNTER Table 8 4 1 Explanation of Functions of Each Bit in Capture Control Register TCCR Bit name Function This bit is set to 1 when the edge specified by EDGS1 and EDGSO is detected An interrupt request is output when this bit and the capture interrupt request enable bit CPIEN are 1 CPIF Capture edge detection flag bit CFCLR This bit is used to clear the capture edge detection flag Capture
239. iew of External Interrupt Circuit 1 10 2 Configuration of External Interrupt Circuit 1 10 3 Pins of External Interrupt Circuit 1 10 4 Registers of External Interrupt Circuit 1 10 5 Interrupt of External Interrupt Circuit 1 10 6 Operations of External Interrupt Circuit 1 10 7 Program Example for External Interrupt Circuit 1 225 CHAPTER 10 EXTERNAL INTERRUPT CIRCUIT 1 EDGE 10 1 Overview of External Interrupt Circuit 1 External interrupt circuit 1 detects a predetermined edge or edges of a signal input to any of three external interrupt pins and then generates and issues an interrupt request to the CPU m Functions of External Interrupt Circuit 1 The external interrupt circuit 1 functions to detect an optionally selected edge or edges of a signal input to 226 any of the external interrupt pins and then generate and issue an interrupt request to the CPU This interrupt ensures recovery from standby mode and enables transition to a normal operating state main clock operation mode External interrupt pins Three pins P34 TO INT10 to P36 INT 12 External interrupt triggering Input of a signal with an optionally selected edge or edges rising and or falling edges to one of the above external interrupt pins triggers an external interrupt Interrupt control Interrupt request outputs are enabled or disabled according to the content of an interrupt request enable bit of external interrupt 1 control registers 1 and 2
240. igure 16 3 5 Address Comparison EN Register WREN Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bitO Initial value wren enor ENO oog R W R W R W Readable and Writable Unused Table 16 3 4 Explanation of Functions of Each Bit in Address Comparison EN Register WREN Bit name Function Undefined at read Unused bits No effect to the operation at write When this bit is 0 the corresponding wild register function does not work When this bit is 1 the wild register function is enabled If there is a match with the address held in WRARHI and WRARL 1 the value of WRDRI instead of ROM is output to the internal bus When this bit is 0 the corresponding wild register function does not work When this bit is 1 the wild register function is enabled If there is a match with the address held in WRARHO and WRARLO the value of WRDRO instead of ROM is output to the internal bus 354 CHAPTER 16 WILD REGISTER FUNCTION 16 3 5 Data Test Set Register WROR A test register Do not access this register 355 CHAPTER 16 WILD REGISTER FUNCTION 16 4 Operations of the Wild Register Functions This section describes the operation order of the wild register B Operation Order of the Wild Register Function Table 16 4 1 describes the operation order of the wild register In the operation example column it corrects data at address
241. ilization wait time lear via program Stop mode request Clear via progra SIOF bit Interrupt request SO pin output Stop mode STP bit 22 register a Stop mode release via external interrupt 38 bit serial I O operation at issuance of stop request during operation As shown in Figure 14 8 3 if operation is stopped SMR SST 0 during data transfer the 8 bit serial I O stops data transfer and clears the shift clock counter For this reason the transfer destination must also be initialized If serial output is in operation set the SDR again before restarting the 8 bit serial I O Figure 14 8 3 8 bit Serial I O Operation at Issuance of Stop Request during Operation Internal Shift Clock 330 SCK output SST bit 2d Operation stop Restart SIOF bit SDR register resetting SO pin output CHAPTER 14 8 BIT SERIAL I O m When the External Shift Clock is Used 8 bit serial I O operation in sleep mode In sleep mode as shown in Figure 14 8 4 the 8 bit serial I O continues data transfer without stopping the serial I O operation Figure 14 8 4 8 bit Serial I O Operation in Sleep Mode External Shift Clock gt Clock for the next data sxnt LILI LI LI LI LILI LIS Transfer stop state SST bit Clear via program SIOF bit Interrupt request SO pin output gt Sleep mode STBC register Sleep mode release via IRQC 8 bit serial I
242. imal adjust for subtraction A AL v TL A AL v d8 395 APPENDIX B Overview of the Instructions Table B 4 2 List of Operation Instructions 3 4 MNEMONIC XOR A IX off XOR A Ri Operation AL Y IX off OP CODE AND A d8 AND A dir AND A EP AND A IX off AND A Ri A AL Ad8 lt AL IX off OR A d8 OR A EP OR A IX off lt AL IX off 396 OR A Ri CMP dir d8 A AL v Ri dir d8 MNEMONIC CMP EP d8 CMP IX off d8 CMP Ri d8 Table B 4 2 List of Operation Instructions 4 4 Operation EP d8 48 Ri d8 OP CODE INCW SP DECW SP m Branch Instructions MNEMONIC BZ BEQ rel BNZ BNE rel BC BLO rel BNC BHS rel BN rel SP SP 1 SP amp XSP 1 Table B 4 3 List of Branch Instructions Operation if Z 1 then PC lt PC rel if Z 0 then PC lt PC rel if C 1 then PC lt PC rel if C 0 then PC lt PC rel if 1 then PC PC rel OP CODE BBC dir b rel BBS dir b rel if N 0 then PC lt PC rel if VW N 1 then PC PC rel if V V 0 then PC PC rel if dir b 0 then PC lt PC rel if dir b 1 then PC PC rel JMP GA JMP ext CALLV vct PC A lt ext vector call CALL ext subrout
243. imer 1 Interval Time and Square Wave Output Range in 8 bit Mode Count clock cycle Internal count clock 2tINST Interval time 9 2tinst 0 2 Square wave output range Hz 1 tsr to 1 C tins AtiNsT 2 10 2 tsT to 2 1 tsr to 1 16tiINsT 4 12 2 tinst to 2 1 25 lt to 1 2Ptgiep 64tinst 6 14 2 tinst to 2 1 2 trygq to 1 2 tiysr 128 7 15 2 tsrT to 2 256tINST 8 16 2 tinst to 2 tINsT 1 tsr to 1 QU tsr 51 2tINST 9 17 2 tnst to 2 1 Ite to 1 2 yg CHAPTER 8 8 16 BIT CAPTURE TIMER COUNTER Table 8 1 3 Interval Time and Square Wave Output Range in 16 bit Mode Count clock cycle Interval time Square wave output range Hz 2tINST to DU ENSE 1 2 lt to 1 2 ies Internal count clock pig ae to 2 eR 1 to 1 bo 2 to 1 xp to 1 CP iso Z tINST to 2 ited 1 21 to 1 ten External clock to 2 text 1 to 1 2 tay tiNsT Instruction cycle this cycle is affected by the clock mode etc External clock cycle 1tgy greater than or equal to 4tjsT Note Example of calculating interval time and square wave frequency If the oscillation Fcp is set to 12 5 MHz the timer 0 data register value is set to DDy 221
244. in 47 External Shift Clock When the External Shift Clock is Used 331 F F MC 8L Overview of the Instructions of the F7MC 8L 380 Features Features of MB89202 F202RA Series 2 Flash Content Protection Flash Content Protection eessss 373 Flash Memory Detailed Explanation of Flash Memory Write Erase 408 Program Access to Flash Memory 373 Writing to the Flash Memory 369 Writing to Erasing Flash Memory 358 Flash Memory Control Status Register Flash Memory Control Status Register FMCS 359 Flash Memory Register Flash Memory Register eeeeeeeeese 358 Flash Security Behavior under the Flash Security Feature 372 How to disable the Flash Security Feature 372 How to enable the Flash Security Feature 372 FMCS Flash Memory Control Status Register FMCS 359 FPT 34P M03 Package Dimension of FPT 34P M03 11 Pin Assignment of FPT 34P MO3 9 Function Function of the External Reset 47 Functions of 12 bit PPG Timer 206 Functions of External Interrupt Circuit 1 226 Functions of External Interrupt Circuit 2 Level
245. in as the analog input set 1 to the bit that corresponds to the A D enable register ADEN set to the bit that corresponds to the port data direction register DDRO and switch the output transistor to OFF and select one using the bit for selecting an analog input channel ADC1 ANSO to ANS2 Even when the A D converter is used pins not used as analog inputs can be used as general purpose I O ports 263 CHAPTER 12 A D CONVERTER m Block Diagram of the Pins Related to the A D Converter Figure 12 3 1 Block Diagram of P03 INT23 AN7 to POO INT20 ANA Pins A D converter A D converter enable bit channel select only to Tothe A D L converter analog input To an external interrupt From disabling an external interrupt mode SPL 1 Pull up PDR read resistor At read modify write gt PDR write Pins POO INT20 AN4 PO1 INT21 AN5 PO2 INT22 ANG PO3 INT23 AN7 Internal data bus DDR write PUL read PUL write SPL Pin status setting bit of the standby control register STBC Figure 12 3 2 Block Diagram of P43 AN3 to P40 ANO Pins A D converter A D converter channel select enable bit TotheA D converter lt analog input Stop mode SPL 1 PDR read PDR read At read modify write Output latc PDR write Internal data bus P40 ANO P41 AN1 DDR write P42 AN2 Stapede P43 AN3 SPL 1 DDR read OUT read OUT
246. ine call XCHW A PC lt A 4 PC 1 RET RETI return from subroutine return from interrupt restore 397 APPENDIX B Overview of the Instructions m Other Instructions Table B 4 4 List of Other Instructions MNEMONIC Operation OP CODE PUSHW A SP lt SP SP 2 POPW A A SP SP SP 2 PUSHW IX SP IX SP SP 2 POPW IX IX amp SP SP SP 2 NOP No operation 398 Instruction Map B 5 Table B 5 1 shows the instruction map of the F2MC 8L Map m instruction Table B 5 1 Instruction Map of the F27MC 8L dS v pIP dS v up Gap Bpgup MHOX MON MAOW MONJ 6 HOX oans Od V 91 V v PT SP gps v 8P v c MHOX MAONW MAOW MAOW 1 qs 9p amp ry mo MANY SON 5 l Y ogns odav 2199 v s Tk ue jm qum 9LIppe O13S 3419 MAOMW AOW 4999 sag S MINN 5 45 95 dS MAOW MAOW M93G MONI Od v v V V 0 41 Sd Y x y MAOW Moga MONI 4 195 9192 MAOW AOW MdOd MHSNd dVMS d a 6 8 9 9 399 APPENDIX C Mask Options APPENDIX C Mask Options Table C 1 lists the mask options of the MB89202 F202RA series m Mask Options Table C 1 Mask Options Part number MB89202 MB89F202 F202RA MB89V20
247. ing has been completed m Writing to Erasing Flash Memory The flash memory cannot be written to and read at the same time That is when data is written to or erased data from the flash memory the program in the flash memory must first be copied to RAM The entire process is then executed in RAM so that data is simply written to the flash memory This eliminates the need for the program to access the flash memory from the flash memory itself m Flash Memory Register Compatible with JEDEC standard commands 00794 Read write Initial value 358 CHAPTER 17 FLASH MEMORY 17 2 Flash Memory Control Status Register FMCS The flash memory control status register FMCS together with the flash memory interface circuit is used to write data to and erase data from the flash memory m Flash Memory Control Status Register FMCS Figure 17 2 1 Flash Memory Control Status Register FMCS R W R Address bit bit6 bits bit4 bits bit2 biti bitO Initial value cor Nre we ror o J RW RW RW 4 R L Unused bit Reading Writing has no effect ReaDY bit RDY for enabling data to be written into erased from flash memory 0 Data is being written or erased 1 Data writing erasing has been completed Subsequent data can be written erased WE Write enable bit
248. ing one of four frequency divided source clocks gears B Operations in Each Clock Mode Table 3 6 2 Operations in Each Clock Mode Clock speed Operating clock in each block Cause that cancels standby mode excepting reset Standby SYCC register SYCC CS1 mode CPU time base Peripheral timer function and CSO 4 Interrupt request Generated 2 Foy 4 Stopped Stopped Stopped Stopped External interrupt Fop 8 Interrupt request Generated Fop 2 8 Stopped Stopped Stopped Stopped External interrupt 16 Interrupt request Generated LL 34 Feg2 16 Stopped Stopped Stopped Stopped External interrupt 64 Interrupt request Generated 2 64 Stopped Stopped Stopped Stopped External interrupt Each clock mode allows transition to a corresponding standby sleep stop mode For details of standby mode see Section 3 7 Standby Mode Low Power Consumption Mode Gears Clock Speed Switching Function Writing one of 00g to 11g into the clock speed selection bits SYCC CS1 and CSO in the system clock control register selects one of four clock speeds The CPU and peripheral circuits operate using the clock speed selected However the gear does not affect the time base timer Power consumption can be reduced by lowering the clock speed 58 CHAPTER 3 CPU B Op
249. input The input of P03 external interrupt 2 is a hysteresis input INT23 AN7 P04 General purpose CMOS I O ports INT24 These pins also serve as an input wake up input of external to interrupt 2 The input of external interrupt 2 is a hysteresis input P07 INT27 P30 General purpose CMOS I O ports UCK This pin also serves as the clock I O pin for the UART or 8 bit SCK serial I O The resource is a hysteresis input P31 General purpose CMOS I O ports UO SO This pin also serves as the data output pin for the UART or 8 bit serial I O CHAPTER 1 OVERVIEW Table 1 7 1 Pin Functions Description 2 2 Pin No SHDIP32 SSOP34 P32 UI SI Circuit type Function General purpose CMOS I O ports This pin also serves as the data input pin for the UART or 8 bit serial I O The resource is a hysteresis input P33 EC General purpose CMOS I O ports This pin also serves as the external clock input pin for the 8 16 bit capture timer counter The resource is a hysteresis input General purpose CMOS I O ports This pin also serves as the output pin for the 8 16 bit capture timer counter or as the input pin for external interrupt 1 The resource is a hysteresis input General purpose CMOS I O ports These pins also serve as the input pin for external interrupt 1 The resource is a hysteresis input General purpose CMOS I O ports These pins also serve as the input pin for
250. iod setting RCR23 24 SCLO to SCL11 H width setting RCR21 22 HSCO0 to HSC11 00 PPG output pulse waveform Extend by overflow 1 period 1 Because the count interval of the operating counter is less than the changed setting the setting is effective only within the cycle 2 Because a cycle period less than the count interval of the operating counter is set synchronization is not detected and the counter overflows 8 Because an width less the count interval of the operating counter is set synchronization is not detected until the next cycle e Error Because the counter start by program is asynchronous with the count up start by the selected count clock an error a time difference may occur until detection of synchronization of compare values for the H width and for the cycle period with a count by the counter major error may shorten the time before the above synchronization to one count clock cycle Figure 9 6 2 illustrates an error a time difference before the count operation start Figure 9 6 2 Error before Count Operation Start Count by counter 0 Count clock Error Count 0 time Period difference Counter start 222 CHAPTER 9 12 BIT PPG TIMER 9 7 Program Example for 12 bit PPG Timer An example of 12 bit PPG timer programming is given below m Program Example for 12 bit PPG Timer Processing specification Aremote control transmis
251. is 38 instruction cycles when the main clock oscillation frequency is 12 5 MHz the speed is 12 2 us When A D conversion is completed an interrupt occurs Software can determine that the conversion has been completed To activate A D conversion functions follow one of the methods given below e Activation with a software program Continuous activation through the output of a time base timer main clock oscillation frequency divided by 25 Continuous activation through the output of an 8 16 bit capture timer counter 16 bit mode CHAPTER 12 A D CONVERTER 12 2 Configuration of A D Converter The A D converter consists of the following nine blocks Clock selector input clock selector for activation of A D conversion Analog channel selector Sample hold circuit D A converter Comparator Control circuit A D data register ADDH and ADDL A D control register 1 ADC1 A D control register 2 ADC2 m Block Diagram of the A D Converter Figure 12 2 1 Block Diagram of the A D Converter A D control register 2 ADC2 RESV4 RESV3 ADCK ADIE RESVz EXT RESVIK X TO output of an 8 16 bit timer Clock 28 output of a time base selector timer POS INT23 AN7 PO2 INT22 AN6 PO1 INT21 AN5 POO INT20 AN4 sample Comparator circuit Control circuit A D data register imm AMO ADDH ADDL 1 converter ANs2 ANS1 ANSO ADI Apwv RESvo AD A D control regis
252. is dependent on the type of oscillator such as crystal or ceramic connected to the oscillation circuit clock generator Therefore an oscillation stabilization wait time setting appropriate to the oscillator used must be selected Figure 3 6 6 shows changes in a frequency generated by an resonator from generation to stabilization Figure 3 6 6 Changes of a Frequency after Generation Normal operation Duration required for a resonator Oscillation Return from stop mode starts oscillation stabilization wait time L OF reset operation Start of oscillation Oscillation stabilizes B Oscillation Stabilization Wait Time 60 Oscillation stabilization wait time is to be applied to start the clock in active mode while the clock is stopped Oscillation stabilization wait time is the duration from when the counter of the time base timer is cleared to when the specified bits overflow Oscillation stabilization wait time during operation For oscillation stabilization wait time applied for a return from stop mode to active RUN mode due to external interrupt one of three oscillation stabilization wait time settings can be selected using the oscillation stabilization wait time selection bits in the system clock control register SYCC WT1 and WTO CHAPTER 3 CPU Oscillation stabilization wait time at a reset Option settings specify oscillation stabilization wait time at a reset initial values of WT1 and WTO Cance
253. ister IX or another function Note A program must be created so that the values of the interrupt level bits in the condition code register CCR IL1 and ILO do not change when the register bank pointer RP is rewritten to specify a register bank in the interrupt processing routine 33 CHAPTER 3 CPU 3 4 Interrupts The MB89202 F202RA series supports 12 interrupt request inputs corresponding to peripheral functions and allows an interrupt level to be assigned to each of the inputs The interrupt controller compares levels of interrupts generated by peripheral functions when output of interrupt requests is allowed for peripheral functions The CPU performs the interrupt operation according to its interrupt acceptance settings The CPU cancels standby mode on reception of an interrupt request then returns to the interrupt operation or normal operation m interrupt Requests from Peripheral Functions Table 3 4 1 lists the interrupt requests that correspond to peripheral functions When the CPU accepts an interrupt the CPU takes a branch to the interrupt processing routine using the address in the interrupt vector table corresponding to the interrupt request as the branch address The interrupt level setting registers ILR1 2 3 and 4 allow one of four interrupt processing intensities to be assigned to each interrupt request Interrupt requests with levels equal to or less than that of an interrupt request being handled in the inte
254. it and external interrupt request flag bit 2 EIR2 are 1 the interrupt request is output Notes When using the external interrupt pin write 0 for bit6 of the port data direction register DDR3 so that the pin serves inputs only Regardless of the interrupt request enable bit state the state of external interrupt pin can be read directly from the port data register PDR3 EIE2 Interrupt request enable bit 2 236 CHAPTER 10 EXTERNAL INTERRUPT CIRCUIT 1 EDGE 10 5 Interrupt of External Interrupt Circuit 1 The detection of a signal with the specified edge or edges input to any of the external interrupt pins triggers external interrupt circuit 1 to generate an interrupt request m interrupt during the Operation of External Interrupt Circuit 1 When external interrupt circuit 1 detects the specified edge or edges of external interrupt input at a pin an external interrupt request flag bit EIC1 EIC2 EIRO to EIR2 corresponding to the pin is set to 1 At this time if the interrupt request enable bit corresponding to the pin contains the value indicating the enabled state EIC1 EIC2 EIEO to EIE2 1 the external interrupt circuit 1 generates and then issues the appropriate interrupt request IRQO IRQ1 IRQ2 to the CPU Write 0 for the external interrupt request flag bit within the interrupt processing routine for the interrupt request thus clearing the interrupt request If external interrupts are not
255. ite Operation 391 Receiving Status Receiving Status 296 Reception Reception Interrupt 303 Reception Operations Reception Operations Operating Mode 0 1 or 3 307 Reception Operations Operating Mode 2 Only 309 Register 12 bit PPG Control Register 1 RCR21 214 12 bit PPG Control Register 2 RCR22 215 12 bit PPG Control Register 3 RCR23 216 12 bit PPG Control Register 4 RCR24 218 8 bit Serial I O Interrupt Register and Vector Table TQ 324 A D Control Register 1 ADCI 266 A D Control Register 2 ADC2 268 A D Data Register ADDH and ADDL 270 A D Enable Register 271 Address Comparison EN Register WREN 354 Block Diagram of the Wild Register Function AUDERET 349 Buzzer Register BZCR esses 343 Capture Control Register TCCR 171 Capture Data Registers H and L TCPH and TCPL E E 182 Clock Divider Selection Register UPC 299 Configuration of the Condition Code Register CCR 29 Configuration of the General purpose Registers 32 Configuration of the Interrupt Level Setting Registers ILRI to ILRA
256. iting 1 into this bit sets states of the external pins to Hi Z states of pins for which a pull up resistor is specified are set to level H This bit becomes 0 after a reset RST Software reset bit This bit specifies software reset Writing 0 into this bit generates a source of 4 instruction cycle internal reset Writing 1 into this bit does not affect operations This bit is always read with the value of 1 RESV bit3 Reserved bit This bit is always read with the value of 0 Writing a value into this bit does not affect operations bit2 to bitO Unused bits Values read out of these bits are undefined Writing values into these bits does not affect operations 67 CHAPTER 3 CPU 3 7 5 Diagram for State Transition in Standby Mode Figure 3 7 2 shows the state transition diagram in standby mode m Diagram for State Transition in Standby Mode Figure 3 7 2 State Transition Diagram Power turned on Power on reset Oscillation stabilization wait Reset mode reset mode Sleep mode Oscillation stabilization wait Stop mode Cancellation of reset input Reset sources multiple Transition to sleep mode by the standby control register STBC SLP 1 External reset input T O 2 5 Transition to stop mode by the standby control register STBC STP 1 Interrupt request Nj External interrupt request 9
257. its of 10 bit data correspond to the ADDH register The low order 8 bits correspond to the ADDL register m A D Data Register ADDH and ADDL Figure 12 4 4 shows the bit configuration of the A D data registers Figure 12 4 4 A D Data Registers ADDH and ADDL ADDH A D data register H Address bit bit6 bits bit4 bit2 biti bito Initial value R R ADDL A D data register L Address bit7 bit6 bit5 bit4 bit3 bit2 bit bito Initial value o33 T T I I T lI ILI ooox R R R R R R R R R Read only X Undefined Of the 10 bit A D data the high order 2 bits correspond to bits 1 and 0 in the ADDH register The low order 8 bits correspond to bits 7 to 0 in the ADDL register When A D conversion functions are enabled When A D conversion is activated after about 38 instruction cycles the data on the conversion results are fixed and stored to these registers Therefore after A D conversion read these registers conversion results write 0 to the ADI bit bit3 in the ADCI register until the next A D conversion is completed and clear the flags after A D conversion During A D conversion the values in these registers are not determined When A D conversion functions are enabled these registers function as read only registers 270 CHAPTER 12 A D CONVERTER 12 4 4 A D Enable Register ADEN The ADEN register is used to select the analog input port that corresponds to differ
258. k Diagram for 8 bit Serial I O Pins 318 Block Diagram of 8 bit Serial I O 315 Functions of I O Ports eese 76 VO Circuit Types etn ettet rr 14 Map beet iens 376 T O Port Programming Example 113 Interrupt at Serial I O Operation 324 Notes on Using 8 bit Serial I O 333 Pins of 8 bit Serial IO uueuuss 317 Registers of 8 bit Serial I O 319 Serial I O Function seeeeeeeeeeeee 314 When Bidirectional Serial I O Operation is Performed 334 ILR Configuration of the Interrupt Level Setting Registers ILRI to ILRA 36 Indicating Arithmetic Operation Results Bits for Indicating Arithmetic Operation Results south Mate Leet 29 Influence Influence from a Reset of Contents in RAM 49 Input Input of a Hardware Reset RST 373 Instruction Branch Instructions eeeeeeeeeeeee 397 Explanation on the Codes Representing Instructions 381 Explanation on the Items of Instructions List 382 Instruction Map 399 Operation Instructions 394 Other Instructions eeeeeeeeeeen 398 Overview of the Ins
259. lag bit1 When signal with an edge or edges corresponding to edge polarity selected by edge polarity selection bits SL11 SL10 is input to INT11 external interrupt pin this bit is set to 1 When this bit and interrupt request enable bit 1 ETE1 are 1 the interrupt request is output Writing 0 clears this bit writing 1 does not affect this bit no change SL11 SL10 Edge polarity selection bits 1 These bits are used to select the polarity of an edge or edges of a signal pulse that triggers an interrupt when the signal is input to INT11 external interrupt pin When these bits provide a value of 00g edge detection is not performed and interrupt requests are not generated These bits may specify 01g indicating a rising edge 10g a falling edge or 11g both edges to be detected Note If an edge is selected while edge detection is OFF edge detection may be performed unconditionally Always clear the EIRO bit after selecting an edge EIEI Interrupt request enable bit 1 EIRO External interrupt request flag bit 0 This bit enables or disables interrupt request outputs to CPU When this bit and external interrupt request flag bit 1 EIR1 are 1 the interrupt request is output Notes e When using the external interrupt pin write 0 for bit5 of the port data direction register DDR3 so that the pin serves inputs only Regardless of the interrupt request enable bit state the state of the external
260. lated to operation Note When using timer in the 16 bit mode write 111g to the TCS12 TCS11 and TCS10 bits and then control timer 1 with TCRO 176 CHAPTER 8 8 16 BIT CAPTURE TIMER COUNTER 8 4 4 Timer Output Control Register TCR2 The timer output control register TCR2 is used to allow and prohibit the square wave output of the 8 16 bit capture timer counter and select timer 0 output and timer 1 output m Timer Output Control Register TCR2 Figure 8 4 5 Timer Output Control Register TCR2 Address bit bit6 bitS bit3 bit2 bit bito Initial value RAN RW TSEL Timer output selection bit Timer 0 output in the 8 bit mode or output in the 16 bit mode is selected Timer 1 output in the 8 bit mode is selected Port output enable bit E The P34 TO INT10 pin acts as the general purpose port P34 R W Readable Writable 4 The P34 TO INT10 pin acts as the square wave output pin Initial value of the 8 16 bit capture timer counter Table 8 4 4 Explanation of Functions of Each Bit in Timer Output Control Register TCR2 Bit name Function At read the values of these bits are undefined Unused bits At write these bits do not affect operation When this bit is 0 the P34 TO INT10 pin acts as the general purpose port P34 When 1 it acts as the square wave output pin TO PEN Port output enable bit When this bit is timer 0 output in the 8 bit mode or
261. ld circuit 2 During about 16 instruction cycles the voltage of the analog input is captured and held in the capacitor for internal sample hold This voltage is held until A D conversion has been completed 3 The comparator compares the voltage captured and held in the capacitor for sample hold with the reference voltage for A D conversion from the MSB to the LSB The results are transferred to the ADDH and ADDL registers in turn 4 When all the results have been transferred to the ADDH and ADDL registers the conversion in progress flag bit is cleared ADC1 ADMV 0 and the interrupt request flag bit is set ADC1 ADI 1 CHAPTER 12 A D CONVERTER 12 7 Notes on Using A D Converter This section describes notes on using the A D converter B Notes on Using the A D Converter Input impedance of the analog input The A D converter contains the sample hold circuit as shown in Figure 12 7 1 captures the voltage of the analog input and holds it in the capacitor for sample hold in about 16 instruction cycles after activation of A D conversion Accordingly when the output impedance of the external circuit of the analog input is high the analog input voltage may not be stabilized during analog input sampling period Therefore set the output impedance of the external circuit to a sufficiently low level lower than about 4 If the output impedance of the external circuit cannot be set low it is recommended that a
262. level pull up state instead of Hi Z during stop SPL 1 During a reset however the pull up is invalid and the pin remains at Hi Z Figure 4 6 2 shows the pull up resistor settings assigned to the values of the bits of the port 6 pull up setting register Figure 4 6 2 Pull up Resistor Settings PUL6 Address bit7 bit6 bit5 bit4 bits bit2 biti bito Initial value ll es CT Ste 0n R W BW R W Readable Writable NEU P61 pull up OFF P60 pull up OFF mmm Initial value P61 pull up ON P60 pull up ON 104 4 6 2 CHAPTER 4 I O PORTS Operations of Port 6 Functions This section describes the operation of port 6 B Operation of Port 6 Operation in output port mode When 1 is written for a bit of the DDR6 register the bit corresponding to a pin of port 6 the pin functions as an output port In output port mode the output transistor operation is enabled and the output latch data is output to the pin Once data has been written into the PDR6 register the written data is held in the output latch and output to the pin as it is The value state of the pin can be read by reading the PDR6 register Operation in input port mode When 0 is written for a bit of the DDR6 register the bit corresponding to a pin of port 6 the pin functions as an input port In input port mode the output transistor is OFF and the pin status is Hi Z Once data has been written into the PDR6 regist
263. lization time the interval interrupt request TBTC 1 is generated from the time base timer upon the start of normal mode In this case interrupts from the time base timer must be disabled TBTC TBIE 0 when switching to stop mode in which an oscillation is stopped m Register and Vector Table Related to Interrupts from Time base Timer Table 5 4 1 Register and Vector Table Related to Time base Timer Interrupts Interrupt level setting register Address of vector table Interrupt name Register Bits to be set High order Low order IRQ7 ILR2 007Cy L71 bit7 L70 bit6 FFECy FFEDg See Section 3 4 2 Steps in the Interrupt Operation for details on interrupt operations 121 CHAPTER 5 TIME BASE TIMER 5 5 Operations of Time base Timer Functions The time base timer functions as an interval timer or supplies clocks to some peripherals B Operations of Interval Timer Function Time base Timer To use as an interval timer the settings shown below must be made Figure 5 5 1 Setting Interval Timer Function bit bits bit4 bits bit2 biti bitO TBOF TBIE 78Ci TBCo TBR C1 0 1 9 0 Used bit 1 Setto 1 o Setto 0 The counter in the time base timer continues to count up in synchronization with the internal count clock at the oscillation frequency divided by two as long as the clock oscillates The counter counts from 0 upon being cleared
264. llation of stop mode by external reset also applies oscillation stabilization wait time Table 3 6 3 shows the relationship between the active mode operation start conditions and oscillation stabilization wait time Table 3 6 3 Active Mode Operation Start Conditions and Oscillation Stabilization Wait Time Cancellation of stop mode Active mode operation start When power is turned condition on External reset External interrupt ME of oscillation stabilization wait Optionset ngs SYCC WT1 WTO 61 CHAPTER 3 CPU 3 7 Standby Mode Low Power Consumption Mode The MB89202 F202RA series supports sleep mode and stop mode in standby mode Transition to standby mode is controlled by the standby control register STBC settings In active mode transition to sleep mode or stop mode is allowed In standby mode operation of the CPU and peripheral functions is stopped to reduce power consumption This section describes the relationship between standby mode and clock mode and explains block operations in standby mode m Standby Mode 62 In active mode power consumption is reduced by lowering the speed of the operating clock for the CPU and peripheral circuits using clock speed switching gears However in standby mode the clock controller stops supply of the clock to the CPU sleep mode or stops oscillation of the source stop mode to reduce power consumption Sleep mode In sleep mode the CPU and watchdog time
265. llowance bit e This bit is used to control shift clock I O When this bit is 0 the P30 UCK SCK pin functions as the shift clock input pin When 1 it functions as the shift clock output pin Notes To use the P30 UCK SCK pin as the shift clock input pin it must be set as an input port Also select the external shift clock with the shift clock selection bits Set the CKS1 and CKSO bits to 11g For shift clock output SCKE bit 1 select an internal shift clock do not set the CKS1 and CKSO bits to 115g Notes When shift clock output is allowed when this bit is 1 the P30 UCK SCK pin functions as the UCK SCK output pin irrespective of the general purpose port P30 state When using the P30 UCK SCK pin as a general purpose port P30 set its pin as the shift clock input pin set this bit to 0 SOE Serial data output allowance bit When this bit is 0 the P31 UO SO pin functions as a general purpose port P31 When 1 the P31 UO SO pin functions as the serial data output pin UO SO Note When serial data output is allowed when this bit is set to 1 the P31 UO SO pin functions as the UO SO pin irrespective of the general purpose port P31 state CKS1 CKSO Shift clock selection bits These bits are used to select three internal shift clocks or one external shift clock When these bits are not 11g an internal shift clock is selected When the shift clock output allowance
266. ly transferred reception data is stored in the SDR When the serial I O is in transfer operation When the serial I O is in transfer operation do not write data to the SDR Moreover note that the read values have no significance When serial output and serial input are allowed at the same time serial I O operation is performed 323 CHAPTER 14 8 BIT SERIAL I O 14 5 Interrupt of 8 Bit Serial I O An 8 bit serial I O interrupt is caused by completion of 8 bit serial data I O m Interrupt at Serial I O Operation In the 8 bit serial I O serial output operation and serial input operation are performed at the same time When serial I O transfer is started the values in the serial data register SDR are input and output on a per bit basis in synchronization with the set shift clock cycle When the shift clock of the 8th bit rises the interrupt request flag bit SMR SIOF is set to 1 In this case when the interrupt request output allowance bit is allowed SMR SIOE 1 the interrupt request IRQC for CPU interrupt occurs Write 0 to the SIOF bit with the interrupt processing routine and clear the interrupt request When 8 bit serial output is completed the SIOF bit is set irrespective of the SIOE bit value If serial I O transfer stop SMR SST 0 and serial data transfer termination take place at the same time during serial I O operation the interrupt request flag bit SMR SIOF 1 If the SIOE bit is allowed 0 gt
267. ment of any third party s intellectual property right or other right by using such information FUJITSU assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein The products described in this document are designed developed and manufactured as contemplated for general use including without limitation ordinary industrial use general office use personal use and household use but are not designed developed and manufactured as contemplated 1 for use accompanying fatal risks or dangers that unless extremely high safety is secured could have a serious effect to the public and could lead directly to death personal injury severe physical damage or other loss i e nuclear reaction control in nuclear facility aircraft flight control air traffic control mass transport control medical life support system missile launch control in weapon system or 2 for use requiring extremely high reliability 1 submersible repeater and artificial satellite Please note that FUJITSU will not be liable against you and or any third party for any claims or damages arising in connection with above mentioned uses of the products Any semiconductor devices have an inherent chance of failure You must protect against injury damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundanc
268. mer counter is cleared and stops operating until returning to normal operation RUN state 6 2 CHAPTER 6 WATCHDOG TIMER Configuration of Watchdog Timer The watchdog timer consists of the following four function blocks Watchdog timer counter Reset control circuit Counter clear control circuit Watchdog control register WDTC Block Diagram of Watchdog Timer Figure 6 2 1 Block Diagram of Watchdog Timer Watchdog control register WDTC 222 F oH eei Reset Time 1 bit counter a control base timer circuit output Watchdog timer counter 1 bit counter A 1 bit counter that operates by accepting output from the time base timer as the count clock Reset control circuit Sends the reset signal to the CPU when the watchdog timer counter overflows Counter clear control circuit Controls the clearing and stopping of the watchdog timer counter Watchdog control register WDTC Activates and clears the watchdog timer counter Because this register is write only bit manipulation instructions cannot be used 129 CHAPTER 6 WATCHDOG TIMER 6 3 Watchdog Control Register WDTC The watchdog control register WDTC activates and clears the watchdog timer m Watchdog Control Register WDTC Figure 6 3 1 Watchdog Control Register WDTC Address b it7 bit6 bitS bit4 bie bitt ote Initial value 0009H TES 0 XXXXB R W 2 E 3 Starts the watchdog time
269. mination timing LL RDYINT bit RDY bit 1 machine cycle 360 17 3 Starting the Flash Memory Automatic Algorithm CHAPTER 17 FLASH MEMORY Four types of commands are available for starting the flash memory automatic algorithm Read Reset Write and Chip Erase m Command Sequence Table Table 17 3 1 lists the commands used for flash memory write erase Table 17 3 1 Command Sequence Table Command Bus 1st bus write 2nd bus write 3rd bus write 4th bus read 5th bus write 6th bus write sequence write cycle cycle cycle write cycle cycle cycle access Address Data Address Data Address Data Address Data Address Data Address Data Read Reset 1 XXXX FO 5 2 J z 7 E 7 4 FAAA AA F554 55 FAAA FO RA RD Write 4 FAAA AA F554 55 FAAA PD program Chip Erase 6 FAAA AA F554 55 FAAA 80 FAAA AA F554 55 FAAA 10 Both of the two types of Read Reset commands can reset the flash memory to read mode Notes The addresses shown in the table are those on the CPU memory map addresses and data are represented in hexadecimal notation The letter X indicates an appropriate value RA Read address PA Write address RD Read data PD Write data The flash memory can only accept the command sequences mentioned on the above table Read Reset Write program Chip Erase other command sequences are strictly prohibited to be sent to the
270. mmand sequence CHAPTER 17 FLASH MEMORY 17 4 3 Timing Limit Exceeded Flag DQ5 The timing limit exceeded flag is used to post that execution of the automatic algorithm has exceeded the time internal pulse count prescribed in the flash memory Automatic Write Erase Bit5 indicates that execution of the automatic algorithm exceeded the time internal pulse count specified in flash memory For an excess bit5 outputs 1 Thus if this bit outputs 1 while the automatic algorithm is operating data writing or data erasing failed Bit5 indicates a failure when an attempt is made to write data into a non blank area without erasing any data In the case of such a failure fixed data cannot be read from bit7 data polling and bit6 toggle bit remains unchanged toggled If the time limit is exceeded while there is a failure 1 is set in bit5 In this case note that the setting of bit5 to 1 does not indicate a flash memory failure but the incorrect use of flash memory If bit5 is set to 1 as described above execute a reset command 365 CHAPTER 17 FLASH MEMORY 17 4 4 Toggle Bit 2 Flag DQ2 The toggle bit 2 flag DQ2 is used to detect that flash memory is performing an automatic erase operation together with the toggle bit m Automatic Write Erase 366 Making successive read accesses while the automatic erasing algorithm is being performed toggles flash memory and makes it output 1 and then in turn rega
271. mode Process CMOS Operating Voltage 2 7V to 5 5V 3 5V to 5 5V 2 2V to 5 5V The minimum operating voltage varies with conditions such as operating frequency functions and connecting ICE 2 MBM27C256A is used as the external ROM CHAPTER 1 OVERVIEW Table 1 2 2 CPU and Peripheral Functions of MB89202 F202RA Series Item Specification CPU function Number of basic instructions 136 instructions Instruction bit length 8 bits Instruction length 1 to 3 bytes Data bit length 1 8 or 16 bits Minimum instruction execution time 0 32 to 5 1 us at 12 5 MHz Interrupt processing time 2 88 to 46 1 us at 12 5 MHz Periphera function Port General purpose I O port 26 pins Also serve as peripherals 4 of which can be used as N ch open drain I O ports 21 bit time base timer 21 bits Interrupt cycle 0 66 ms 2 64 ms 21 ms or 335 5 ms with 12 5MHz main clock Watchdog timer Reset occurrence cycle When the main clock is at 12 5 MHz minimum 335 5 ms 8 bit PWM timer 8 16 bit capture timer counter UART 8 bit serial VO 8 bit interval timer operation Square wave output is supported Operating clock cycle 1 tnst 16 tnst 64 tsr and 8 16 bit capture timer counter output 8 bit resolution PWM operation Conversion cycle 256 tryst 4096 tjs p 16384 tnst and 256 times 8 16 bit capture timer counter output 8 bit capture timer counter x 1 channel 8 bit timer or 16 bit
272. mount required to stabilize output Note While PWM timer functions are enabled no interrupt request occurs 138 CHAPTER 7 8 BIT PWM TIMER 7 2 Configuration of 8 bit PWM Timer An 8 bit PWM timer consists of the following six blocks e Count clock selector e 8 bit counter e Comparator PWM generation and output control circuit PWM compare register COMR PWM control register CNTR m Block Diagram of an 8 bit PWM Timer Figure 7 2 1 Block Diagram of an 8 bit PWM Timer Internal data bus Output of an 8 16 bit capture timer counter PWM generation circuit and output control circuit Output pin control P50 PWM Suput tinst Instruction cycle 139 CHAPTER 7 8 BIT PWM TIMER Count clock selector The count clock selector selects one of three types of internal counter clock The selector also selects an 8 16 bit capture timer or counter and uses it to increment the count of the 8 bit counter 8 bit counter This counter is incremented by the count clock selected by the count clock selector Comparator A latch in the comparator holds the COMR register value when the value of the 8 bit counter is 00g and then compares the 8 bit counter with the COMR register value latched and detects a match PWM generation circuit and PWM output control circuit During the interval timer operation once a match is detected an interrupt request occurs And when the bit to control
273. n SST 0 Set SI pin to serial data input input port Set SCK pin to shift clock output Set SO pin to serial data output Select internal shift clock Set data transfer shift clock direction In io YES Set output data Start serial I O transfer SST 1 SIO A Serial data transfer End of 8 bit transfer 3 YES SST 0 Read input data ES NO Vif only whet used to monitor the wait time period that lasts until SIO B is allowed for transfer via software SIO B Stop SIO B operation SST 0 Set SI pin to serial data input input port Set SCK pin to shift clock input Set SO pin to serial data output Select external shift clock Select same data transfer shift direction as SIO A Set output data Allow serial data transfer SST 1 Transfer allowance state Serial data output via SIO A Simultaneous data input via SIO B End of 8 bit transfer 3 YES SST 0 Read input data SST The SST bit is the serial I O transfer start bit of the serial mode register SMR the SO SI and SCK pins are connected there is no method for directly checking er SIO B is in the serial transfer allowance state For this reason a timer etc must be 2 If SIO B is not allowed for serial I O transfer data cannot be transferred correctly even if SIO A starts serial I O transfer 3 When 8 bit data transfer terminates a interrupt request occurs 335 CHA
274. n EN Register WREN 354 Addressing Explanation on Addressing 383 ADEN A D Enable Register ADEN 271 Association Association between the Interrupt Enable Bits for External Interrupt Circuit 2 and the External Interrupt Pins eeeeeeeeeeees 248 Automatic Erasing Automatic Erasing 363 Automatic Write Erase Automatic Write Erase 364 365 366 INDEX Behavior Behavior under the Flash Security Feature 372 Bidirectional Serial 1 0 Operation When Bidirectional Serial I O Operation is Performed Bit Manipulation Read Destination at Execution of a Bit Manipulation Instruction nett nnn 391 Bits Bits for Controlling Acceptance of Interrupts 30 Bits for Indicating Arithmetic Operation Results DUI TET 29 Block Diagram Block Diagram for 8 16 bit Capture Timer Counter lun jT 169 Block Diagram for 8 bit Serial I O Pins 318 Block Diagram of 12 bit PPG Timer 209 Block Diagram of 8 16 bit Capture Timer Counter MEET 166 Block Diagram of 8 bit Serial I O 315 Block Diagram of an 8 bit PWM Timer 139 Block Diagram of Circuitry Terminating at the Pin Associated with the 12 bit PPG Timer Block Diagram of Circuitry Terminating at the Pins Associated with External Interrupt
275. n reset Note External reset input is accepted asynchronously regardless of the internal clock Initialization of the internal circuits requires a clock In particular for operations with an external clock the clock must be input when a reset signal is input Internal pull up control for RST is not available for MB89F202 F202RA To ensure proper external reset control in MB89F202 F202RA an external pull up recommend 100 for RST pin must be required 47 CHAPTER 3 CPU 3 5 3 Reset Operation The CPU reads the mode data mode fetch and reset vector from internal ROM according to the mode pin settings following the cancellation of a reset For a return triggered by a reset when power is turned on and in stop mode the CPU fetches the mode after oscillation stabilization wait time has expired When a reset occurs the contents in RAM cannot be guaranteed B Overview of the Reset Operation Being reset Mode fetch reset operation Normal operation RUN mode 48 Figure 3 5 3 Reset Operation Flow Software reset External reset input Watchdog reset Power on reset selected When power is turned on or in stop mode State of reset wait State of reset wait State of reset wait ing for stabilization ing for stabilization ing for stabilization of oscillation of oscillation of oscillation J E state cancelled Vv Mode data fetch Reset vector fetch Instruction code fetched from the address
276. n selection bits EDGS1 and EDGS0O of the capture control register TCCR 1 is written to the timer start bit TSTRO after the clock source selection bits TCS02 TCSO1 TCSO0 of the timer 0 control register TCRO have been set In the capture mode the count value is captured to the capture data register TCPL each time a capture input edge is detected and the capture edge detection flag CPIF is set to 1 In this case if the capture interrupt enable bit CPIEN is already set to 1 an interrupt request is output to the CPU The capture mode is divided into free run mode and clear mode 193 CHAPTER 8 8 16 BIT CAPTURE TIMER COUNTER Free run mode Setting the clear mask bits CCMSK and TCMSK of TCCR to 11g enables the capture function to operate as the free run timer Clear mode Setting the clear mask bits CCMSK and TCMSK of TCCR to a value other than 11g enables the capture function to operate as a clear mode The clear mode enables the measurement of signal pulse widths and cycles In this case using the clear mode with the compare match detection function also enables the determination of signal availability Note The capture input pin also serves as the external clock input pin The external clock mode cannot be used in the capture mode Table 8 8 1 shows the relationship between the counter mode and the compare latch operation according to the clear mask bit value Table 8 8 1 Relationship bet
277. n when a reset is performed When the CPU is reset the bits of the DDR5 register are initialized to 0 Thus the output transistor becomes OFF input port mode and the pin becomes Hi Z However CPU resets do not initialize the PDR5 register If the pin is used as an output port after the reset reinitialize the PDR5 register to contain new output data in the bit position corresponding to the pin and then set the corresponding bit of the DDR5 register so that the pin will function as an output port Operation in stop mode When the pin state setting bit of the standby control register STBC SPL is set to 1 and when the stop mode is entered the pin becomes Hi Z because the output transistor is turned OFF regardless of the value existing on the DDR5 register in the bit position corresponding to the pin Input remains fixed to prevent leaks by input open 98 CHAPTER 4 I O PORTS Table 4 5 4 summarizes the operating modes of the pin of port 5 Table 4 5 4 Operating Modes of Pin of Port 5 Pin name Normal operation sleep stop SPL 0 Stop SPL 1 P50 PWM General purpose I O port further may serve I O for peripherals SPL Pin state setting bit of standby control register STBC SPL Hi Z High impedance Note If the pull up resistor is selected by using the pull up setting register the pin state will be H level pull up state instead of Hi Z in stop mode SPL 1 During a reset however the pull up is i
278. nable flag is turned on CCR I 1 Otherwise an instruction is managed following the instruction causing standby mode to be set To prohibit a branch to the interrupt processing routine immediately after return interrupts must be prohibited before standby mode is set Notes on Setting Standby Mode 70 For setting standby mode using the standby control register STBC use the settings specified in Table 3 7 5 When 1 is set to both bits at the same time stop mode has precedence over sleep mode However it is recommended that 1 not be set to the bits at the same time Table 3 7 5 Low power Consumption Mode Established using the Standby Control Register STBC STBC register STP bit7 SLP bit6 Active Sleep Stop CHAPTER 3 CPU B Oscillation Stabilization Wait Time The oscillator for oscillation frequency stops in stop mode thus oscillation stabilization wait time must be applied after the oscillator is activated Use one of three clock oscillation stabilization wait time settings generated by the time base timer If the interval selected for the time base timer is shorter than the oscillation stabilization wait time an interval timer interrupt request is generated during oscillation stabilization wait time To prevent this from occurring disable output of time base timer interrupt requests TBTC TBIE 0 before transition to stop mode when necessary 71 CHAPTER 3 CPU 3 8 Memory Acces
279. nce a match is found the output is L until the counter value overflows 004 Figure 7 7 2 shows the PWM waveform output to the PWM pin 150 CHAPTER 7 8 BIT PWM TIMER Figure 7 7 2 Output Example of the PWM Waveform of 8 bit PWM Timer Functions When the COMR Register Value is 00 096 duty ratio Counter value OOH 35 FFu 00u H PWM waveform When the register value is 80 5096 duty ratio Counter value 0 gt 80 FFH 00 3 H PWM waveform T When the register value is 99 6 duty ratio Counter value 00H E FFH 004 5 p 1 PWM waveform For one count Notes While PWM timer functions are enabled CNTR 1 do not change the count clock cycle CNTR P1 PO While PWM timer functions are enabled the level immediately before the stop is held as the output level of the PWM pin in the counter stop state CNTR TPE 0 151 CHAPTER 7 8 BIT PWM TIMER 7 8 States in Each Mode During Operation This section describes the operations for a move to the sleep mode a move to the stop mode and the occurrence of a suspend request during the operation of an 8 bit PWM timer B Operations in the Standby Mode and at a Suspension When the mode is moved to sleep and st
280. nctions of Each Bit in the Serial Status and Data Register SSD Bit name Description RDRF Received data flag bit This bit indicates the state of serial input data register SIDR When this bit is 1 reading the SSD register then the SIDR register clears When this bit and reception interrupt request enable bit RIE are 1 the reception interrupt request is output This bit is intended only for read Writing a value into this bit has no significance and does not affect any operation ORFE Overrun Framing error flag bit This bit indicates that the overrun or framing error occurs When an error occurs ORFE 1 no data is transferred from the reception shift register to the SIDR register Therefore when an error occurs the RDRF bit is not set When this bit is 1 reading the SSD register then SIDR register clears the ORFE bit with 0 When this bit and reception interrupt request enable bit RIE are 1 the reception interrupt request is output This bit is intended only for read Writing a value into this bit has no significance and does not affect any operation TDRE Transmitted data flag bit This bit indicates the state of serial output data register SODR When this bit is 1 reading the SSD register and writing data into the SODR register output the data to the serial data output pin UO When this bit and transmission interrupt request enable bit TIE are 1 the transmission interru
281. nd DDR3 registers in the bit position corresponding to the output pin for the peripheral have no significance regardless of the value output from the peripheral and the output enabled Setting the input to a peripheral enable If a peripheral with an input pin is used set the pin of port 3 for the input to the peripheral to function as an input port In this mode the corresponding output latch value has no significance CHAPTER 4 I O PORTS Table 4 3 3 lists the functions of port 3 registers Table 4 3 3 Functions of Port 3 Registers Register When being name read When being written Address Initial value Output latch of 0 is set and Pin state is Yon ae L level L level is output to the pin in Port 3 data i output port mode register XXXXXXXXp PDR3 Output latch of 1 is set and H level is output to the pin in output port mode Pin state is H level Output transistor operation is Port 3 disabled and the pin is set to Read serve as an input pin prohibited 000000005 write only Output transistor operation is enabled and the pin is set to serve as an output pin direction register DDR3 R W Readable and Writable W Wrie only X Undefined Port 3 pull up setting register PULS The bits of the pull up setting register correspond to the pins of port 3 in one to one correspondence When the pull up resistor is selected by using the pull up settin
282. ndby Control Register Standby Control Register STBC 66 Standby Mode Cancellation of Standby Mode by an Interrupt DEEP 70 Diagram for State Transition in Standby Mode 68 Notes on Setting Standby Mode 70 Operation in Standby Mode and at Halfway Stop Rea 197 Operations in Standby Mode 63 Operations in the Standby Mode and at a Suspension 152 Standby eee Re Eee det 62 Transition to Standby Mode and Interrupt 70 State State of Reset Waiting for Stabilization of Oscillation TR 49 States of Pins after the CPU Reads the Mode Data ue ina 50 States of Pins during 50 STBC Standby Control Register STBC 66 Steps Steps in the Interrupt 37 Stop Mode Operations Related to Stop Mode 65 Structure Structure of Port 0 78 Structure of Port 3 esent 84 Structure of Port iiir deren 90 Structure of Port 94 Structure of Port 100 Structure of Port 7 1 diuine 107 Suspension Operations in the Standby Mode and at a Suspension E 152 SYCC Configuration of the System Clock Control Register SY CE siii se I Ry ue enn oae 56 System Cl
283. ne correspondence Table 4 7 2 tabulates the correspondence between the pins and the bits of the port 7 registers Table 4 7 2 Correspondence between the Pins and the Bits of the Port 7 Registers Bits of associated registers and corresponding pins PDR7 DDR7 PUL7 Pin corresponding to bit 108 CHAPTER 4 I O PORTS 4 7 1 Registers of Port 7 PDR7 DDR7 PUL7 This section describes the registers associated with port 7 m Functions of Port 7 Registers Port 7 data register PDR7 The PDR7 register indicates the state of the output latch For a pin set to function as an output port the same value 0 or 1 as the value state of the output pin can be read from this register If the pin is set to function as an input port however its output latch value cannot be read from the register Note When a bit manipulation instruction SETB CLRB is executed the output latch values not the value states of the pins are read thus output latch values other than those for bits to be manipulated do not change Port 7 data direction register DDR7 The DDR7 register sets the I O direction of each pin per bit When a bit of the DDR7 corresponding to a pin of port 7 is set to 1 the pin functions as an output port When the bit is set to O the pin functions as an input port Table 4 7 3 lists the functions of the port 7 registers Table 4 7 3 Functions of Port 7 Registers Register When being name re
284. ne for interrupt handling to clear the interrupt request The ADI bit is set when A D conversion is completed irrespective of the value of the ADIE bit Note When the ADI bit is 1 if the ADIE bit is enabled changed from 0 to 1 an interrupt request occurs immediately B Register and Vector Table Related to the Interrupt of the A D Converter Table 12 5 1 Register and Vector Table Related to the Interrupt of the A D Converter Register to set the interrupt level Address of the vector table Interrupt name Register Bit to be set High order Low order IRQ8 ILR3 007Dy L81 bitl L80 610 FFEAq FFEBy See Section 3 4 2 Steps in the Interrupt Operation for the interrupt operation 272 CHAPTER 12 A D CONVERTER 12 6 Operations of A D Converter Functions The A D converter can be activated with software or activated continuously B Activating the A D Converter Functions Software activation To activate A D conversion functions with software set registers as shown in Figure 12 6 1 Figure 12 6 1 Setting A D Conversion Functions at Software Activation bit7 bit6 bit5 bit4 bit3 bit2 bit1 bitO ADCi ANS2 ANS ANSO ADMV RESVO AD 1 ADC2 RESv4 RESv3 ADCK ADIE RESV2 EXT RESV1 0 0 x 0 0 1 ADDH The results of A D conversion are stored ADDL The results of A D conversion are stored ADEN Used bit Unused bit Set 1 Set 0 Set 1 to an approp
285. ned Undefined Undefined Flag I 0 IL1 and ILO 11 Figure 3 2 1 Configuration of Dedicated Register RP The other bits are undefined m Functions of the Dedicated Register Program counter PC Program counter Indicates the current instruction stored position Accumulator Temporary register that handles arithmetic operations and data transfer Temporary accumulator Handles arithmetic operations together with the accumulator Index register Indicates index address Extra pointer Indicates memory address Stack pointer Indicates the current position in the stack Program status register Stores the register bank pointer and condition code The size of the program counter is 16 bits It indicates the memory address at which the CPU is currently handling an instruction The program counter is updated with an instruction executed interrupt or reset The initial value specified after the reset operation is the mode data read address FFFD gy Accumulator A The accumulator is a 16 bit arithmetic operation register It handles arithmetic operations or data transfer using data on memory or data in another register such as temporary accumulator T The accumulator allows data in it to be used as a word 16 bits or bytes 8 bits When arithmetic operations or data transfer is handled in the unit of a byte only the lower 8 bits AL of the accumulator are used the upper 8 bits AH
286. nel has eight independent inputs and can be used for wake up from low power consumption mode L level detection function is supported Low power consumption modes standby modes Stop mode The oscillation is stopped so that current consumption is minimal e Sleep mode The CPU is stopped so that the current consumption is reduced by one third of normal consumption Up to 26 pins of I O ports e General purpose I O ports CMOS 26 pins 4 of which can be used as N ch open drain I O ports Wild registers e 2 byte data at two addresses are available When a specific address or data is used on a wild register the data in the ROM area is changed 16 Flash with read protection Once the protection code is written in the specified address the FLASH content cannot be read by parallel serial programmer CHAPTER 1 OVERVIEW 1 2 MB89202 F202RA Series Product Lineup Four MB89202 series models are available Table 1 2 1 shows the models and Table 1 2 2 shows the CPU and peripheral functions m MB89202 F202RA Series Models Table 1 2 1 MB89202 F202RA Series Models MB89201 MB89F202 F202RA MB89V201 Evaluation product Flash memory product Mask ROM product Classification for development read protection 32K x 8 bits 16K x 8 bits 16K x 8 bits External EPROM Internal Flash Internal mask ROM ROM size RAM size 512 x 8 bits Low power consumption Sleep mode and stop mode standby
287. ng Read access during execution of the automatic erasing algorithm causes the flash memory to output 0 regardless of the value at the address specified by the address signal After the automatic erasing algorithm is executed 1 is output Note When the automatic algorithm comes to the end of its operation bit7 data polling changes its state asynchronously during a read operation This means that flash memory sends data about the operation state to bit7 and will then send out fixed data When flash memory ends the automatic algorithm or even if bit7 is outputting fixed data the values of the other bits are still undetermined Fixed data in the other bits can be read by successively executing read operations 363 CHAPTER 17 FLASH MEMORY 17 4 2 Toggle Bit Flag DQ6 Like the data polling flag the toggle bit flag uses the toggle bit function to post that the automatic algorithm is being executed or has terminated m Automatic Write Erase 364 Making successive read accesses while the automatic writing erasing algorithm is being performed toggles flash memory and makes it output 1 and then in turn regardless of the specified address Making successive read accesses when the automatic writing erasing algorithm ends makes flash memory to stop bit6 toggle and outputs the value of bit6 DATA 6 corresponding to the value read from the specified address The toggle bit becomes effective after the last write cycle in each co
288. ng is Time base timer changed and affected when 1 is written initialization bit Note This bit is always 1 at the beginning of reading 120 CHAPTER 5 TIME BASE TIMER 5 4 Interrupt of Time base Timer The time base timer counter generates an interrupt when the specified bit of the counter overflows interval timer function m Interrupts when the Interval Timer Function is Enabled The counter counts up with the internal count clock When the specified interval timer bit overflows the overflow interrupt request flag bit TBTC is set to 1 Then if the interrupt request enable bit is enabled TBTC TBIE 1 an interrupt request IRQ7 is sent to the CPU When this occurs use the interrupt handling routine and set the bit to 0 to clear the interrupt request The bit is set to when the specified bit overflows regardless of the value of the TBIE bit Note When the interrupt request is allowed to be output TBIE 1 after a reset is released clear the bit 0 at the same time Note e An interrupt request is generated immediately after the TBIE bit is set from 0 disable to 1 enable if the TBOF bit is 1 When the counter is cleared TBTC TBR 0 and the specified bit overflows at the same time the TBOF bit is not set B Oscillation Stabilization Time and Time base Timer Interrupts If a time interval is set the time shorter than the oscillation stabi
289. nnected pins are opened before using Precautions on using an external clock When an external clock is used the oscillation stabilization wait time is also provided for power on reset and stop mode release Wild register function Because wild registers cannot be debugged on MB89V201 check operation on an actual MB89F202 F202RA Program execution on RAM When MB89V201 is used a program cannot be executed RAM Note to Noise in the External Reset Pin RST CHAPTER 2 HANDLING DEVICES If the reset pulse applied to the external reset pin RST does not meet the specifications it may cause malfunctions Use caution so that the reset pulse less than the specifications will not be fed to the external reset pin RST External pull up for the External Reset Pin RST of MB89F202 F202RA Internal pull up control for RST is not available for MB89F202 F202RA To ensure proper external reset control in MB89F202 F202RA an external pull up recommend 100 for RST pin must be required For MB89F202RA only high voltage must be applied to RST during flash memory program erase The typical high voltage is 10 V Step down circuit stabilization time The MB89202 F202RA series consists of the products listed in Table 2 1 1 Pin Processing for the Products with and without a Step down Circuit The operation characteristic depends on whether a product contains a step down circuit Table 2 1 1 Pin Proc
290. nsmitted data is written into the SODR register the transmitted data flag bit is cleared with 0 After the transmitted data is sent to the transmission shift register the transmitted data flag bit is set to 1 the data transmitted next then becomes writable At this time if the transmission interrupt request is enabled an interrupt is generated Write the data transmitted next when a transmission interrupt occurs or while the transmitted data flag bit is 1 298 CHAPTER 13 UART 13 4 6 Clock Divider Selection Register UPC The clock divider selection register is used to generate the UART reference clock by dividing the oscillation frequency It also enables disables operation of the prescaler for creating the reference clock m Clock Divider Selection Register UPC Figure 13 4 8 Clock Divider Selection Register UPC Address bit7 bit6 bits bit4 bit2 bitO Initial value 2 Pren PR2 PRO 0010 RW RW RW RW Clock divider selection bits PR2 PR1 Divider o 9 o 1 p p s e 3 KEKA R W Readable Writable as seen PREN UART prescaler operation enable bit Dx Disables the prescaler operation Initial value Enables the prescaler operation 299 CHAPTER 13 UART Table 13 4 4 Explanation of Functions of Each Bit in the Clock Divider Selection Register UPC
291. nstruction 1 byte Higher 4 bits Instruction map o 5 z e zl The instructions are classified into four groups including transfer instructions and branch instructions Various methods for addressing are supported Depending on the selection of an instruction and specification of operands 10 kinds of addressing can be selected Bitmanipulation instructions are supported so read modify write operation is possible nstructions directing special operations are supported 380 m Explanation on the Codes Representing Instructions Table B 1 describes the codes used to explain the instruction codes in Appendix B Table B 1 Explanation on Codes on Instructions List Code Meaning Direct address 8 bits Offset 8 bits Extended address 16 bits Vector table number 3 bits Immediate data 8 bits Immediate data 16 bits Bit direct address 8 3 bits Branch relative address 8 bits Register indirect Example 9 A IX and 9 EP Accumulator 8 bits or 16 bits determined on basis of instruction to be used Higher 8 bits of the accumulator 8 bits Lower 8 bits of the accumulator 8 bits Temporary accumulator 8 bits or 16 bits determined on basis of instruction to be used Higher 8 bits of the temporary accumulator 8 bits Lower 8 bits of the temporary accumulator 8 bits Index register 16 bits Extra poin
292. nstructions are required for the interrupt processing time However if the DIVU instruction and MULU instruction are not used in the program a maximum of 15 6 instructions 9 instructions instructions are required for the instruction processing time An instruction cycle is changed by clock speed switching gears For details see Section 3 6 Clock 40 CHAPTER 3 CPU 3 4 5 Stack Operation at Interrupt Processing This section describes how values in registers are saved and restored at interrupt processing Stack Operation at the Beginning of Interrupt Processing After accepting an interrupt the CPU automatically saves the values in the program counter PC and program status PS in the stack Figure 3 4 5 shows the stack operation at the beginning of interrupt processing Figure 3 4 5 Stack Operation at the Beginning of Interrupt Processing Immediately before Immediately after interruption interruption Address Memory Address Memory PS 027CH SP 027DH Po sss SP 0280H gt Do 20H 1 Stack Operation at the End of Interrupt Processing When the return instruction RETI is executed at the end of interrupt processing the values in the program status PS and the program counter PC are restored from the stack in that order which is opposite to that at the beginning of interrupt processing This operation restores the values in the PS and PC to those values used before inte
293. nter Notes on creating programs When creating a program that repeatedly clears the watchdog timer in the main loop ensure that the time necessary for main loop processing including interrupt handling is shorter than the minimum time interval of the watchdog timer 132 CHAPTER 6 WATCHDOG TIMER 6 6 Program Example for Watchdog Timer Programming exampl es for the watchdog timer are provided below m Programming Examples of Watchdog Timer Processing specification Activate the watchdog timer immediately after the program starts Clear the watchdog timer whenever the loop of the main program is run Ensure that the time necessary for running the main loop once including interrupt handling is shorter than the timer Coding example WDTC minimum time interval approximately 335 5 ms operating at 12 5 MHZ of the watchdog EQU 0009H Address of watchdog control register WDT CLR EQU 00000101B VECT RST V DSEG ABS DATA SEGMENT ORG OFFFEH DW PROG Setting reset vector ENDS Main program CSEG CODE SEGMENT Initialization routine upon reset INIT MAIN MOVW 0280 Setting initial value of stack pointer for interrupt pd interrupt or other peripheral functions MOV WDTC FWDT CLR Activating watchdog timer MOV WDTC fFWDT CLR Clearing watchdog timer iss p
294. nterrupt Circuit 2 ener entren 244 11 2 Configuration of External Interrupt Circuit 2 enne 245 11 3 Pins of External Interrupt Circuit 2 nennen nennen snnm 246 11 4 Registers of External Interrupt Circuit 2 essere nennen 249 11 4 1 External Interrupt 2 Control Register EIE2 sse 250 11 4 2 External Interrupt 2 Flag Register EIF2 rennes 252 11 5 Interrupt of External Interrupt Circuit 2 nennen 253 11 6 Operations of External Interrupt Circuit 2 nennen enne 254 11 7 Program Example for External Interrupt Circuit 2 sse 256 CHAPTER 12 A D CONVERTER scieete te cic eiue ue uou 2222503 c ri Die Fee tee veo rye eine 259 12 1 Overview of A D Converter nnn ne nennen ensis nennen 260 12 2 Configuration of A D Converter ssssssssssssseeseseeene ennt siete en nnns nr 261 12 32 Pins of A D GonVettet uiui tee e sie fat ei eid o ee eda Ep esie edere Aa EnS 263 12 4 Registers of A D Converter viisiin iee dated e a oce ea d e v dena eL ne e eu a eue e eee 265 12 4 4 A D Control Register 1 1 222 266 12 4 2 A D Control Register 2 2 3222 en 268 12 4 8 A D Data Register ADDH and ADDL 270 12 4 4 A D Enable Register ADEN
295. nterrupt Control Register 2 EIC2 beendet rt iei te 235 EIE External Interrupt Circuit 2 Control Register EIE2 250 EIF External Interrupt 2 Flag Register EIF2 252 Erase Automatic Write Erase 364 365 366 Detailed Explanation of Flash Memory Write Erase 367 Erasing Automatic Erasing eeeeseeeeeeeeee 363 Erasing All Data Erasing Chips 371 Writing to Erasing Flash Memory 358 Erasing All Data Erasing All Data Erasing Chips 371 Erasing Chips Erasing All Data Erasing Chips 371 Evaluation Chip Programming EPROM with Evaluation Chip um 401 Example Example of Operations of 12 bit PPG Timer Functions 219 Exercise Caution Exercise Caution when Changing Edge Polarity Selection iie eese 238 Explanation Explanation on Addressing 383 Explanation on the Codes Representing Instructions ER 381 Explanation on the Items of Instructions List 382 External Interrupt Association between the Interrupt Enable Bits for External Interrupt Circuit 2 and the External Interrupt Pins eeeeeeeeeesess 248 Block Diagram of Circuitry Terminating at the Pins Associated with External Interrupt Circuit 1 Block Diagram of Circuitry Terminating at the Pins Asso
296. nterrupt request enable bit setting changes from disable to enable 0 1 an interrupt request is generated immediately 237 CHAPTER 10 EXTERNAL INTERRUPT CIRCUIT 1 EDGE Register Associated with Interrupt Generation by External Interrupt Circuit 1 and Vector Table Table 10 5 1 Register Associated with Interrupt Generation by External Interrupt Circuit 1 and Vector Table Interrupt level setting register Vector table address Interrupt designation Register Bit for setting level Upper Lower L01 bit1 LOO bitO ILR1 007By L11 bit3 L10 bit2 L21 bit5 L20 For interrupt operation see Section 3 4 2 Steps in the Interrupt Operation Exercise Caution when Changing Edge Polarity Selection When changing edge polarity for INT10 to INT12 always write 0 for the appropriate EIR bit to prevent unintended interrupt generation 238 CHAPTER 10 EXTERNAL INTERRUPT CIRCUIT 1 EDGE 10 6 Operations of External Interrupt Circuit 1 The external interrupt circuit 1 can detect a specified edge or edges of a signal input to any of the external interrupt pins B Operation of External Interrupt Circuit 1 To operate external interrupt circuit 1 the bits of the registers must be set as shown in Figure 10 6 1 Figure 10 6 1 Setting External Interrupt Circuit 1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bitO EIR1 SL11 SL10 EIE1 EIRO SLO1 SLOO EIEO 9 9 9 9
297. ntrol Register 2 EIC2 UEM E 235 Functions of External Interrupt Circuit 1 226 Functions of External Interrupt Circuit 2 Level 55 244 Interrupt at Serial I O Operation 324 Interrupt during the Operation of External Interrupt CIC Ut iiec ciet tte lecti 237 Interrupt during the Operation of External Interrupt Crett 2 3er 253 Interrupt Processing Time uus 40 Interrupt when A D Conversion Functions are Enabled 272 Interrupts when the Interval Timer Function is Enabled rr tne 121 Interrupts while Interval Timer Functions are Enabled TR 147 Multiple Interrupts eee 39 Operation of External Interrupt Circuit 1 239 Operation of External Interrupt Circuit 2 254 Oscillation Stabilization Time and Time base Timer Interrupts 2 0 121 Pins Associated with External Interrupt Circuit 1 229 Pins Associated with External Interrupt Circuit 2 EEEE PELE E AE E E 246 409 INDEX Program Example for External Interrupt Circuit 2 t cct teet A T 256 Reception 303 Register and Vector Table Related to 8 16 bit Capture Timer Counter of Interrupts 184 Register and Vector Table Related to Interrupts from Time base 121 Register and Vector Table Related to the
298. nvalid with the pin remaining at Hi Z 99 CHAPTER 4 I O PORTS 4 6 Port 6 Port 6 is a general purpose I O port This section describes the port function when operating as general purpose I O port This section also describes the structure pins the block diagram of pins and associated registers of port 6 B Structure of Port 6 Port 6 comprises the following four elements e General purpose I O pins input pins P61 P60 for MB89F202 F202RA e Port 6 data register PDR6 e Port 6 data direction register DDR6 not used in MB89F202 F202RA Port 6 pull up setting register PUL6 m Pins of Port 6 Port 6 has 2 I O pins of CMOS input type they are input only pins for MB89F202 F202RA Table 4 6 1 lists the pins of port 6 Table 4 6 1 Pins of Port 6 Peripherals for Input and output form Port name Pin name Function which a pin may Circuit serve Input Output type P60 general purpose I O P61 general purpose I O P61 and P60 are general purpose input port for MB89F202 F202RA For circuit type see Section 1 7 Pin Functions Description and 1 8 I O Circuit Types 100 m Block Diagram of Port 6 Internal data bus Internal data bus CHAPTER 4 I O PORTS Figure 4 6 1 Block Diagram of Port6 PDR read PDR read D when read modify write is performed DDR write DDR read PUL write For MB89202 V201 Stop mode SPL 1 SPL Pin state se
299. o 8 bit counters timer 0 and timer 1 These counters can be used separately 8 bit mode or in combination 16 bit mode Timer 0 provides seven internal count clocks This timer can select the interval timer function or counter function The interval timer function increments the counter value in synchronization with one of the seven internal clocks The counter function increments the counter value according to the clock to be input to an external pin Timer 0 can output square waves of any frequency according to outputs from the interval timer and counter Timer 1 provides seven internal count clocks This timer can output square waves of any frequency but can use only the interval timer function that increments the timer value in synchronization with one of the seven internal counter clocks For the 16 bit mode timer 0 and timer 1 are connected in series to serve as a 16 bit timer m Interval Timer Function The interval timer function generates interrupt requests repeatedly at any time interval This function can also invert the output level of P34 TO INTI10O pin per time interval and output square waves of any frequency In the 8 bit mode the interval timer function operates as two independent timers timer 0 8 bit capture timer counter and timer 1 8 bit timer Interval timer operation from each count clock cycle to a 28 times cycle is possible The interval timer function can select and output square waves to the TO pin acc
300. ocessing is performed Otherwise if interrupts are unacceptable the processing resumes starting from an instruction next to the instruction which was issued immediately before transition to sleep mode 3 7 3 CHAPTER 3 CPU Stop Mode This section describes the stop mode B Operations Relating to Stop Mode Transition to stop mode In stop mode the oscillation frequency is stopped Most functions stop storing data in the registers and RAM used immediately before transition to stop mode The clock circuit stops oscillating the peripheral functions and CPU stop operating but the external interrupt circuit continues to operate Writing 1 to the stop bit in the standby control register STBC STP causes a transition to stop mode At that time if the pin state setting bit STBC SPL is the states of the external pins are maintained If the pin state setting bit is 1 the states of the external pins are set to Hi Z the states of pins for which a pull up resistor is specified in the pull up setting resistor are set to level H An attempt to write 1 into the STP bit while an interrupt request is being generated fails transition to stop mode cannot made and instructions are processed continuously Even after the interrupt is processed completely transition to stop mode is not made For a transition to stop mode prohibit the time base timer interrupt request output TBTC TBIE 0 when necessary Canc
301. ock Control Register Configuration of the System Clock Control Register SY CO PTS 56 415 INDEX T TBTC Time base Timer Control Register TBTC 119 TCCR Capture Control Register TCCR 171 TCPH and TCPL Capture Data Registers H and L TCPH and TCPL P 182 TCR Timer 0 Control Register TCRO 173 Timer 1 Control Register TCR1 175 Timer Output Control Register TCR2 177 TDR Timer 0 Data Register 178 Timer Data Register TDR1 180 Theory Theory of Operation for Operating Mode 0 1 2 and 3 305 Time base Timer Block Diagram of Time base Timer 118 Notes on Using Time base Timer 124 Operations of Interval Timer Function Time base Timer 122 Operations of Time base Timer 122 Oscillation Stabilization Time and Time base Timer Interrupts 121 Programming Examples for Time base Timer 125 Register and Vector Table Related to Interrupts from Time base Timer 121 Time base Timer Control Register Time base Timer Control Register TBTC 119 Timer 0 Control Register Timer 0 Control Register TCRO 173 Timer 0 Data Register
302. of MB89202 F202RA Series ssssssssssssseseseee eene tenen nri 2 1 2 MB89202 F202RA Series Product Lineup sssssssssssssseseeenneneten nennen eene nnns 4 1 3 Differences between Models 6 1 4 Block Diagram of MB89202 F202RA Series sssssssssssssseseeeneee eene 7 1 5 PiriAssigniTient iioii e E ince o P E b abc eet bois miedo et e edd 8 1 6 Package Dimensions oet ER Rd e A mte 10 1 7 Pin Fonctions DescrlptiQrizz tse e at ted env APUD ange 12 1 8 VO Circuit TYPES eL cc 14 CHAPTER 2 HANDLING DEVICES 17 2 1 Precautions on Handling Devices nnne nennen nens 18 CHAPTER 3 e 21 3 1 MOMOFY SPaCO AEE E A T E 22 3 1 1 Specific purpose Areas e a A DE A AA EA a nnns sen e 24 3 1 2 Location of 16 bit Data on Memory A a PEREA NaN 26 3 2 Dedicated Register e ote ater E ea oie oil e db eds 27 3 2 1 Condition Code Register CCR sse 29 3 2 2 Register Bank Pointer RP 31 3 3 General Purpose Registers ssssssssssssssssssseseeee enne nennen 32 3 4
303. of the watchdog control register When the counter is not cleared within the time interval of the watchdog timer the counter overflows and the timer generates the internal reset signal having a period of four instruction cycles Time intervals of watchdog timer The time interval varies depending on the timing at which the watchdog timer is cleared Figure 6 4 1 shows the relationship between the clear timings and time intervals of the watchdog timer when output from the time base timer is used as the count clock oscillation frequency 12 5 MHz Figure 6 4 1 Clearing Watchdog Timer and Time Interval Minimum time interval Count clock output from time base timer Watchdog clear Overtlow Watchdog 1 bit counter Watchdog reset _ Maximum time interval 671 0 ms Count clock output from we fF time base timer i Watchdog clear Overflow Watchdog 1 bit counter Watchdog reset i 131 CHAPTER 6 WATCHDOG TIMER 6 5 Notes on Using Watchdog Timer Notes on using the watchdog timer are provided below m Notes on Using Watchdog Timer Stopping watchdog timer The watchdog timer cannot be stopped without accepting a reset upon activation Clearing watchdog timer Clearing the time base timer counter that supplies the count clock to the watchdog timer also clears the watchdog timer counter at the same time Switching to sleep or stop mode clears the watchdog timer cou
304. on of interrupt request flag bit EQU 007CH Address of interrupt level setting register 2 DSEG ABS DATA SEGMENT ORG OFFECH DW WARI Setting interrupt vector ENDS CSEG CODE SEGMENT Stack pointer SP or other registers are assumed to have been initialized CLRI Interrupt disable MOV ILR2 01111111B Setting interrupt level level 1 MOV TBTC 01000100B Clearing interrupt request flag enabling interrupt request output selecting 218 Fcg and clearing time base timer SETI Interrupt enable CLRB Clearing interrupt request flag PUSHW A XCHW PUSHW A User processing POPW XCHW A T 125 CHAPTER 5 TIME BASE TIMER 126 CHAPTER 6 WATCHDOG TIMER This chapter describes the functions and operations of the watchdog timer 6 1 Overview of Watchdog Timer 6 2 Configuration of Watchdog Timer 6 3 Watchdog Control Register WDTC 6 4 Operations of Watchdog Timer Functions 6 5 Notes on Using Watchdog Timer 6 6 Program Example for Watchdog Timer 127 CHAPTER 6 WATCHDOG TIMER 6 1 Overview of Watchdog Timer The watchdog timer is a 1 bit counter that uses output from the time base timer based on oscillation frequency as the count clock The watchdog timer resets the CPU when not cleared within a specified period after activation m Watchdog Timer Function 128 The watchdog timer is a counter for preventing programs from hanging up The timer must be cleared at
305. on time and an operation clock for the watchdog timer The time base timer stops operating in modes in which oscillation stops m Interval Timer Function The interval timer function is used to continuously generate interrupts at specified intervals e An interrupt occurs when the interval timer bits of the time base timer counter overflow e One of four time intervals can be selected by setting the interval timer bits Table 5 1 1 lists the time intervals for the time base timer Table 5 1 1 Time Intervals for Time base Timer Internal count clock cycle Time interval 2 Bu Approximately 0 66 ms 2 5 Approximately 2 6 ms 2 0 16 us DIE di Approximately 21 0 ms 22 Fc Approximately 335 5 ms Fox Oscillation frequency The values enclosed in parentheses are time intervals when the oscillation frequency is 12 5 MHz m Clock Supply Function The clock supply function is used to provide one of three timer outputs for the oscillation stabilization wait time and the operation clock for the resource function Table 5 1 2 lists cycles of the clock that the time base timer supplies to peripherals Table 5 1 2 Clock Cycles Supplied by Time base Timer 1 2 Clock supplied to Clock cycle Remarks 2 Fe Approximately 1 31 ms Selected by the oscillation stabilization time 2 Fea Approximately 10 49 ms selection bits SYCC WT1 WTO of the clock control section system clock control register Os
306. on using the 8 bit serial I O B Notes on Using 8 bit Serial I O Error at serial transfer start The time at which serial I O transfer is started with a serial transfer program SMR SST 1 is asynchronous with the time when the falling edge output or rising input edge of a shift clock occurs For this reason the time that lasts until the first serial data is input or output is delayed by a maximum of one cycle of the set shift clock Malfunction due to noise If external noise causes an extra pulse pulse exceeding the hysteresis width to be placed on a shift clock during serial data transfer the 8 bit serial I O may malfunction Notes on setting via program Write data to the serial mode register SMR and serial data register SDR only when the 8 bit serial I is stopped SMR SST 0 When starting or allowing serial I O transfer SMR SST 1 do not change other bits of the SMR If MSB first is set when a shift clock is used in external shift clock input the highest bit level is output as the SO pin output level If LSB first is set the lowest bit level is output as the SO pin output level MSB first and LSB first are set when the external shift clock is input In this case however serial data output must be allowed SMR SOE 1 even if serial I O transfer is stopped SMR SST 0 If serial I O transfer stop SMR SST 0 and serial data transfer termination take place at the same time during se
307. op modes and when a suspend request occurs the counter value status in which interval timer functions are enabled is shown in the Figure 7 8 1 and the counter value status in which PWM timer functions are enabled is shown in the Figure 7 8 2 When switched to the stop mode the counter holds a value and stops When the stop mode is released by an external interrupt the counter starts operation from the held value Therefore the first interval and the first cycle of the PWM waveform are not the values that are set After the release of the stop mode initialize the 8 bit PWM timer 152 While interval timer functions are enabled CHAPTER 7 8 BIT PWM TIMER Figure 7 8 1 Operation of the Counter in the Standby Mode and during Suspension while Interval Functions are Enabled Counter value value FFH Timer cycle Clear by the program TIR bit TPE bit PWM pin OE 1 SLP bit STBC register Release of Clear by stopping operation 3 Stop Time to wait request for oscillation stabilization Stopping Restarting operation operation d L level while operation gt is being stopped Stop sleep by IRQ9 STP bit STBC register Release of stop by an external interrupt When the bit to specify the pin state STBC SPL of the standby control register is 1 and the PWM pin is not pulled up the PWM pin in the stop mode is Hi Z When the SPL
308. ording to the timer 0 or output Inthe 16 bit mode the interval timer function operates as a 16 bit capture timer counter in which timer 0 is concatenated as the lower counter and timer 1 is concatenated as the upper counter Interval timer operation from the count clock cycle to the 216 times cycle is possible The count clock can be selected from the seven internal clock cycles if timer 0 selects an external clock the interval timer function operates as the capture counter function The timer output cycle can be used as the clock for starting A D converters continuously or as the 8 bit PWM timer count clock 162 Table 8 1 1 to Table 8 1 3 show the interval time and square wave output range in each operation mode CHAPTER 8 8 16 BIT CAPTURE TIMER COUNTER Table 8 1 1 Timer 0 Interval Time and Square Wave Output Range in 8 bit Mode Count clock cycle Internal count clock Interval time 9 2tinst to 2 tINsT Square wave output range Hz 1 tsr to 1 QI Ptr 2 10 2 t sr to 2 1 to 1 Qt 4 12 2 tinst to 2 1 tsr to 1 Ptr p 6 14 2 tinst to 2 1 to 1 QPtgisp 7 15 2 tsrT to 2 1 23tyyg7 to 1 QI Ste 8 16 2 tinst t0 2 1 tsr to 1 21 tns 9 17 2 tnst to 2 tINST 1 2 tig to 1 2 tgs External clock Itext to 2 1 2 0 to 1 text Table 8 1 2 T
309. oscillation Fcp is 12 5 MHz the buzzer output frequency is calculated as follows Buzzer output frequency 12 5 2 2 12 5 MHz 4096 3 052 kHz Coding example MOV BZCR 00000010 BZCR 00000000 Address of the buzzer register CODE SEGMENT Buzzer output on 3 052 kHz Oscillation of 12 5 MHz Buzzer output off I O port or PPG output 345 CHAPTER 15 BUZZER OUTPUT 346 CHAPTER 16 WILD REGISTER FUNCTION This chapter describes the functions and operation of the wild registers 16 1 Overview of the Wild Register Function 16 2 Configuration of the Wild Register Function 16 3 Registers of the Wild Register Function 16 4 Operations of the Wild Register Functions 347 CHAPTER 16 WILD REGISTER FUNCTION 16 1 Overview of the Wild Register Function The wild register function is a function for patching the faulty part of a program by setting the address and the correct data in the incorporated registers Up to two bytes of data correction is possible m Wild Register Function The wild register function assigns an address in the ROM area of the microcontroller and replaces the existing data corresponding to the address with new data For example if an error exists in a program setting the address of the faulty part and correction data to the register can correct the faulty data m Wild Register Applicable Addresses The address area where the wild register function can apply varies
310. ounter is cleared and the values in the data register are loaded to the comparator data latch 187 CHAPTER 8 8 16 BIT CAPTURE TIMER COUNTER 16 bit mode To operate timer 0 as the interval timer function in the 16 bit mode the function must be set as shown in Figure 8 6 4 Figure 8 6 4 Setting of Interval Timer Function in 16 bit Mode bit7 bit6 bit5 bit4 bit3 bit2 bit TCCR CPIF EDGSO0 RESV x x x x X SgettingofO00 9 x TcR1 Tiri TFCR1 T IEN TCSi2 TCS11 TCS10 TSTRI x x x 1 1 1 x TIFO L Setting of a value 9 9 9 9 other than 111 PEN TSEL 0 Setting of higher 8 bits of interval time Setting of lower 8 bits of interval time Used bit Unused bit Set 0 Set 1 In the 16 bit mode timers are controlled by the timer 0 control register TCRO but the timer 1 control register TCR1 must be initialized The values to be set in the data register are the higher 8 bits of TDR1 and the lower 8 bits of TDRO 16 bits in total The values are compared with the 16 bit counter value The 16 bits of the counter are cleared at the same time Other operations in the 16 bit mode are the same as timer 0 operation in the 8 bit mode 188 CHAPTER 8 8 16 BIT CAPTURE TIMER COUNTER 8 7 Operation of Counter Functions This section describes the operation of the 8 16 bit capture timer counter function B Counter Function Operation 8 bit mode To operat
311. output in the TSEL 16 bit mode is selected In this case data is output from the TO pin Timer output selection bit When 1 timer 1 output in the 8 bit mode is selected In this case data is also output from the TO pin 177 CHAPTER 8 8 16 BIT CAPTURE TIMER COUNTER 8 4 5 Timer 0 Data Register TDRO The timer 0 data register is used to set the timer 0 value in the 8 bit mode of the 8 16 bit capture timer counter or the interval timer value interval timer function or counter value counter function of the lower 8 bits in 16 bit mode Timer 0 Data Register TDRO The values set in this register are compared with those set in the counter Figure 8 4 6 shows the bit structure of timer 0 data register Figure 8 4 6 Timer 0 Data Register TDRO Address bit7 bit6 bits bit4 bit3 bit2 biti bito Initial value RAN RAW RW RW RAW RW RW RW R W Readable Writable X Undefined 8 bit mode timer 0 The values set in this register are compared with those set in the counter When the interval timer function is used an interval timer value is set When the counter function is used the count value to be detected is set When the count operation is allowed TCRO TSTRO 0 21 the value in is set in loaded to the comparator data latch and the counter is incremented When the values in the comparator data latch match those in the counter as a result of the increment the value
312. p mode SPL 1 PUL read PUL write SPL Pin status setting bit of standby control register STBC Note When the A D converter is used deselect pull up action for pins PO3 INT23 AN7 to POO INT20 AN4 Pins set to be used as analog input pins must not be used as an output port m Registers PDRO DDRO and PULO of Port 0 Registers PDRO DDRO and PULO are associated with port 0 The bits of these registers correspond to the pins of port 0 in one to one correspondence Table 4 2 2 tabulates the correspondence between the pins and the bits of the port 0 registers Table 4 2 2 Correspondence between the Pins and the Bits of the Port 0 Registers Bits of associated registers and corresponding pins PDRO DDRO PULO Pin corresponding to bit 79 CHAPTER 4 I O PORTS 4 2 1 Registers of Port 0 PDRO DDRO and PULO This section describes the registers associated with port 0 m Functions of Port 0 Registers 80 Port 0 data register PDRO The PDRO register indicates the state of the output latch For a pin set to function as an output port the same value 0 or 1 as the value state of the output pin can be read from this register If the pin is set to function as an input port however its output latch value cannot be read from the register Note When a bit manipulation instruction SETB CLRB is executed the output latch values not the value states of the pins are read thus o
313. pin can be read by reading the PDR3 register Operation in input port mode When is written for a bit of the DDR3 register the bit corresponding to a pin of port 3 the pin functions as an input port In input port mode the output transistor is OFF and the pin state is Hi Z Once data has been written into the PDR3 register the written data is held in the output latch but is not output to the pin The value state of the pin can be read by reading the PDR3 register Operation in external interrupt input mode Set a bit of the DDR3 register to 0 the bit corresponding to a pin of port 3 that is to serve as an external interrupt input pin to set the pin to function as an input port The value state of the pin can be read by reading the PDR3 register regardless of whether or not the external interrupt inputs or interrupt request outputs are enabled Operation in mode enabling the output from a peripheral When the output enable bit for a peripheral is set to enable the corresponding pin is set to serve the output from the peripheral Because the value state of the pin can be read from the PDR3 register even when the output from the peripheral is enabled the value output from the peripheral can be read Operation in mode enabling the input to a peripheral Set a bit of the DDR3 register to O the bit corresponding to the pin of port 3 assigned for the input to the desired peripheral for the pin to function as an input
314. ple 113 Port 0 Block Diagram of Port 0 79 Functions of Port 0 80 Operation of Port 0 0 0 0 cee eee 82 Pins of Port 78 Registers PDRO DDRO and PULO of Port O 79 Structure of Port 78 Port 3 Block Diagram of Port 3 85 Functions of Port 3 86 Operation of Port 3 0 0 0 ce eee 88 genti ce ete deiode ge 84 Registers PDR3 DDR3 and PUL3 of Port 3 85 412 Structure of Port 84 Port 4 Block Diagram of Port 4 91 Operation of Port 4 93 Pins of Pott e eee dde tenui 90 Registers of Port 4 91 Structure of Port 4 90 Port 5 Block Diagram of Port 5 95 Functions of Port 5 Registers 96 Operation of Port 5 98 Pins of POPS ei er obe e advert 94 Registers of Port 95 Structure of Port iaa eena eteina 94 Port 6 Block Diagram of Port 6 101 Functions of Port 6 Registers 103 Operation of Port 6 sssseseeeeeeeeee 105 Pins of Port 6 100
315. ple External Interrupt Circuit 1 Programming Example 241 Programming Examples for Time base Timer Jet eder tue E CER ERE EAT 125 Programming Examples of Watchdog Timer 133 PUL Registers of Port 5 95 Registers PDRO DDRO and PULO of Port O 79 Registers PDR3 DDR3 and PUL3 of Port 3 85 Registers PDR6 DDR6 and PUL6 of Port 6 102 Registers PDR7 DDR7 and PUL of Port 7 108 PWM Compare Register PWM Compare Register COMR 145 PWM Control Register PWM Control Register CNTR 143 PWM Timer Program Example of PWM Timer Functions P HEC MM RE REDE TE 159 PWM Timer Functions eeeeeeeeeese 137 R RAM 16 bit Data Storage State on 26 Influence from a Reset of Contents in RAM 49 RCR 12 bit PPG Control Register 1 RCR21 214 12 bit PPG Control Register 2 RCR22 215 12 bit PPG Control Register 3 RCR23 216 12 bit PPG Control Register 4 RCR24 218 Read Setting the Read Reset State 368 States of Pins after the CPU Reads the Mode Data Read Destination Read Destination at Execution of a Bit Manipulation Instr ction zieeiie eerte pen 391 Read modify write Read modify wr
316. program counter using the contents of A accumulator as the address N items of jump destinations have been listed on the table one of which is selected and transferred to A Executing this instruction can achieve N kinds of branch processing Figure B 2 1 shows an overview Figure B 2 1 JMP A Before execution After execution 12545 Old PC NewPC 12344 MOVW A PC This instruction performs the opposite operation of JMP 2A In other words the contents of the PC are stored in A When this instruction has been executed in the main routine and a specific subroutine is to be called it is possible to verify that the contents of A are the predetermined value in the subroutine It is also possible to verify that the branch was not from an unexpected part so it is useful in judging that a runaway has occurred Figure B 2 2 shows an overview Figure B 2 2 MOVW A PC Before execution After execution a 9994 p 7299 odpe 12888 H NewPC 12344 When this instruction is executed the contents of A are not the address holding the operation code of this instruction but the same value as the address holding the next instruction In Figure B 2 2 therefore the value stored in A 1234y is the same as the address holding the operation code next to MOVW A PC 387 APPENDIX B Overview of the Instructions 388 MULUA This instruction multiplies AL th
317. pt request is output TIE Transmission interrupt request enable bit This bit enables or disables the transmission interrupt request to the CPU When this bit and transmission data flag bit TDRE are 1 the transmission interrupt request is output RIE Reception interrupt request enable bit This bit enables or disables the reception interrupt request to the CPU When this bit and reception data flag bit are 1 the reception interrupt request is output When this bit and error flag bit ORFE are 1 the reception interrupt request for an error is output Unused bit The value read out from this bit is undefined Writing a value into this bit does not affect any operations TD8 TP Bit 8 transmitting data parity bit When parity is not used and operating mode is 2 or 3 the length of data to be transmitted received is 9 this bit is handled as bit8 in the SODR register When operating mode is not 2 or 3 and parity is not used this bit is not significant When parity is used this bit selects even parity or odd parity for the transmitted data RD8 RP Bit 8 receiving data parity bit When parity is not used and operating mode is 2 or 3 the length of data to be transmitted received is 9 this bit is handled as bit8 in the SIDR register When operating mode is not 2 or 3 and parity is not used this bit is not significant When parity is used this bit indicates the parity of received
318. ption Mode 62 3 7 1 Operations in Standby Mode nens 63 3 7 2 oleep MOdO esee mt d At mue be M e IIR 64 3 7 3 Stop Mode ME 65 3 7 4 Standby Control Register STBO 66 3 7 5 Diagram for State Transition in Standby Mode ssssssssseeeeeeneene enne 68 3 7 6 Notes on Standby n E re o d e n HE a EU vg 70 3 8 Memory Access Mode tne e c e ERR RR M ee E ERE RE E RR EO rr Eust ea 72 CHAPTER VO PORTS 75 4 1 Overview ot VO POS saoi tote etri et pee abate cuara eta aie tap a Re 76 4 2 pend c 78 4 2 1 Registers of Port 0 PDRO DDRO and PULO 80 4 2 2 Operations of Port 0 Functions 0 02 00 ree tacere e aeree rene ena ae ve rea 82 4 3 MET 84 4 3 1 Registers of Port PDR3 DDR3 PULS ssssssseeeeeenee nennen rennen nnne 86 4 3 2 Operations of Port 3 FUNCTORS tiir tritt etti ette Re etin EHE Aa 88 4 4 incite test die E ii hub erat etd iidem ebrius 90 4 4 1 Registers of Port4 PDRA esie Dee teet ipee 92 4 4 2 Operations of Port 4 Functions sse nennen nter ener sineret nnns 93 4 5 pnt gelu Im 94 4 5 1 Registers of Port 5 PDR5 DDR5 PULS
319. quest enable bit Compare match TIIEN are 1 detection flag bit Note In the 16 bit mode the TIFO bit of TCRO is valid The TIF1 bit is unrelated to operation TFCRI This bit is used to clear the compare match detection flag bit TIF1 When this Compare match bit is set to 1 the compare match detection flag is cleared The flag is not detection flag clear bit affected even if this bit is set to 0 TIEN This bit is used to allow and prohibit interrupt request output to the CPU Interrupt request enable An interrupt request is output when this bit and the interrupt request enable bit bit TOIEN are 1 This bit is undefined at read Not used AM At write this bit does not affect operation These bits are used to select the count clocks to be supplied to the counter e Of seven internal clocks select one When 111 is written to these bits timer 1 operates as the 16 bit mode Note In the 16 bit mode the TCSO2 TCSO1 and TCSOO bits are valid The TCS12 TCS11 and TCS10 bits are used to select the 16 bit mode only TCS12 TCS11 TCS10 Clock source selection bits This bit is used to start and stop the counter When this bit is set to 1 the counter is cleared and incremented according to TSTRI the selected count clock When this bit is set to 0 the counter stops its Timer start bit operation In the 16 bit mode only the TSTRO bit can be used to start the timer The TSTRI bit is unre
320. r upon first writing after reset 1 1 Clears the watchdog timer upon second or subsequent writing after a reset Other than above RESV Reserved bit 0 Write 0 to this bit R W Readable writable Unused X Undefined Table 6 3 1 Explanation of Functions of Each Bit in Watchdog Control Register WDTC Bit name Description RESV Reserved bit Write to this bit Undefined when it is read Unused bits m Writing values does not affect operation Writing 0101 activates for first writing or clears for second or subsequent writing the watchdog timer Writing other than 0101 does not affect operation Note These bits indicate 1111 when read Bit manipulation WTE3 WTE2 WTE1 WTEO Watchdog control bits instructions cannot be used 130 CHAPTER 6 WATCHDOG TIMER 6 4 Operations of Watchdog Timer Functions The watchdog timer generates a watchdog reset when the watchdog timer counter overflows B Operations of Watchdog Timer Activating watchdog timer The watchdog timer is activated when the first time 0101g is written to the watchdog control bits WDTC WTE3 to WTEO of the watchdog control register The watchdog timer cannot be stopped without accepting a reset upon activation Clearing watchdog timer The watchdog timer counter is cleared the second or subsequent time 0101g is written to the watchdog control bits WDTC WTE3 to WTEO
321. r are stopped Peripheral functions operate using the normal clock Stop mode In stop mode the CPU and peripheral functions are stopped and the clock does not oscillate the functions except for external interrupt halt CHAPTER 3 CPU 3 7 1 Operations in Standby Mode This section describes CPU and peripheral function operation in standby mode B Operations in Standby Mode Table 3 7 1 Operations of the CPU and Peripheral Functions in Standby Mode Function Clock Active Active Stopped Stopped Instruction Active Stopped Stopped Stopped ROM Active Holding Holding Holding RAM I O port Active Holding Holding Hi Z Time base timer Active Active Stopped Stopped Watchdog timer Active Stopped Stopped Stopped 8 bit PWM timer counter Active Active Stopped Stopped 8 16 bit capture timer counter Active Active Stopped Stopped Peripheral function Stopped Stopped 8 bit serial I O Active Active Stopped Stopped 12 bit PPG Active Active Stopped Stopped Buzzer Active Active Stopped Stopped External interrupt 1 and 2 Active Active Active Active A D converter Active Active Stopped Stopped State of pins in standby mode The state of most I O pins can remain the same as those set immediately before transition to stop mode or set to Hi Z using the pin state setting bit in the standby control register STBC SPL reg
322. r is activated continuously Other operations are affected by the gear 52 CHAPTER 3 CPU 3 6 1 Clock Generator The clock generator enables oscillation in active mode and disables oscillation in stop mode m Clock Generator Foracrystal resonator or ceramic resonator Connect it as shown in Figure 3 6 2 Figure 3 6 2 Example of Connecting a Crystal Resonator or Ceramic Resonator MB89202 F202RA series Oscillation circuit X0 X1 For an external clock Connect it to the pin and open the pin as shown in Figure 3 6 3 Figure 3 6 3 Example of Connecting an External Clock MB89202 F202RA series Oscillation circuit X0 X1 53 CHAPTER 3 CPU 3 6 2 Clock Controller The clock controller consists of the following six blocks Oscillation circuit System clock selector Clock controller Oscillation stabilization wait time selector System clock control register SYCC Standby control register STBC 54 Block Diagram of Clock Controller Figure 3 6 4 is a block diagram of the clock controller Figure 3 6 4 Block Diagram of Clock Controller Standby control register STBC 5 SLP SPL BST 1 Pin control Stop Sleep 1 2 frequency for time base Pre scaler Supplied to the CPU 1 4 frequency 1 3 1 1 16 frequency 2 INST 1 64 frequency Supplied to peripheral circuits Itinst 1
323. rammer 401 APPENDIX E Pin State of the MB89202 F202RA Series APPENDIX E Pin State of the MB89202 F202RA Series Table E 1 describes the pin states in each operation mode of the MB89202 F202RA series Pin States in Each Operation Mode Table E 1 Pin States in Each Operation Mode Pin name In normal operation mode Oscillation input In sleep mode Oscillation input In stop mode SPL 0 Hi Z In stop mode SPL 1 Hi Z During a reset Oscillation input Oscillation output Oscillation output H output H output Oscillation output POO INT20 AN4 to PO7 INT27 Port I O or resource VO Hold Hi Z 2 Hi Z P30 UCK SCK to P37 BZ PPG Port I O or resource VO Hi Z 12 P40 ANO to P43 AN3 Port I O or resource VO Hi Z 2 P50 PWM Port I O or resource VO Hi Z 2 P60 P61 Port I O Hi Z P70 to P72 Port I O Hi Z 2 1 For port input and peripheral input the internal input level is fixed to prevent them from generating a leak via the input open However if external interrupts are allowed for POO to PO7 and P34 to P36 only the external interrupts are available as their inputs 2 The pins for which pull up is selected by the option setting enter the pull up state Hi Z Indicates high impedance Hold The pins for which output is set maintain the pin state level just b
324. rase is in progress i e while the automatic algorithm is being started secure a minimum low level width of 1650 ns In this case 20 us are required until the data becomes readable after the operation being performed terminates and the flash memory is fully initialized Performing a hardware reset during a write operation makes the data being written undetermined Also note that performing a hardware reset or shut down during an erase operation may make the sector from which data is being erased unusable m Software Reset Watchdog Timer Reset When write erase of flash memory is set up for normal mode and CPU memory access mode is internal ROM mode and if a reset cause occurs while the automatic algorithm of flash memory is being activated the CPU may run out of control The cause of a reset does not initialize the flash memory and keeps the automatic algorithm operating Thus when the CPU starts a sequence after the reset is cancelled the flash memory may not have been in a read state Prevent a cause of a reset from occurring while the flash memory is writing or erasing m Program Access to Flash Memory While the automatic algorithm is being activated any read access to the flash memory is disabled When CPU memory access mode is set to internal ROM mode move program areas into another area such as RAM and then start a write or erase In this case when the flash containing interrupt vectors are erased the writing or erasing of in
325. rcuitry Terminating Block Diagram of Circuitry Terminating at the Pin Associated with the 12 bit PPG Timer Block Diagram of Circuitry Terminating at the Pins Associated with External Interrupt Circuit 1 PEE 230 Block Diagram of Circuitry Terminating at the Pins Associated with External Interrupt Circuit 2 duri teri EA ni Means bent 247 Clock Controller Block Diagram of Clock Controller 54 Clock Divider Selection Register Clock Divider Selection Register UPC 299 Clock Generator Clock Generator eI entr qt 53 Clock Mode Operations in Each Clock Mode 58 Clock Speed Switching Gears Clock Speed Switching Function 58 Clock Supply Clock Supply Function 116 Clock Supply Map 51 Operations of Clock Supply Function 122 CNTR PWM Control Register CNTR 143 Command Sequence Command Sequence 361 COMR PWM Compare Register COMR 145 Condition Code Register Configuration of the Condition Code Register CCR INC 29 Configuration Configuration of Memory 22 Configuration of the Condition Code Register CCR TER 29 Configuration of the General purpose Registers VO a e a 32 Configuration of the Interrupt Level Setting Regis
326. rdless of the specified address Making successive read accesses while the automatic writing algorithm is being performed toggles flash memory and makes it output 1 regardless of the specified address Making successive read accesses when the automatic writing erasing algorithm ends makes flash memory to stop bit2 toggle and outputs the value of bit2 DATA 6 corresponding to the value read from the specified address The toggle bit becomes effective after the last write cycle in each command sequence CHAPTER 17 FLASH MEMORY 17 5 Detailed Explanation of Writing to Erasing Flash Memory This section describes each operation procedure of flash memory Read Reset Write Chip Erase when a command that starts the automatic algorithm is issued m Detailed Explanation of Flash Memory Write Erase The flash memory executes the automatic algorithm by issuing a command sequence see Table 17 3 1 in Section 17 3 Starting the Flash Memory Automatic Algorithm for a write cycle to the bus to perform Read Reset Write Chip Erase operations Each bus write cycle must be performed continuously In addition whether the automatic algorithm has terminated can be determined using the data polling or other function At normal termination the flash memory is returned to the read reset state Each operation of the flash memory is described in the following order 17 5 1 Setting The Read Reset State 17 5 2 Writing Data 17 5 3 Erasing All Data Erasing Chips
327. register 3 Address bit7 bitG bit5 bit4 bit3 bit bito Initial value 00160 RCEN SCL 5 SCL4 SCL3 SCL2 SCL1 SCLO 0 000000 R W RW RW RW RW RW RW RCR24 12 bit PPG control register 4 Address bit7 bit6 bit5 bit4 bit3 bit2 bit bito Initial value 00174 SCL11 SCL 0 SCL9 scLa SCL7 scLe 0000008 RW RW RW RW RW RW R W Readable and Writable 1 Unused 213 CHAPTER 9 12 BIT PPG TIMER 9 4 1 12 bit PPG Control Register 1 RCR21 The 12 bit PPG control register 1 comprises bits for count clock selection of the 12 bit PPG timer and bits for setting the H width 12 bit PPG Control Register 1 RCR21 Figure 9 4 2 12 bit PPG Control Register 1 RCR21 Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bitO Initial value 5 000000005 RW RW RW RW RW RW RW RW HSC5 to HSCO H width setting bits Compare value for the H width of 12 bit PPG outputs 1 ofai 1 0 we SSCS R W Readable Writable Initial value Table 9 4 1 Explanation of Functions of Each Bit in 12 bit PPG Control Register 1 RCR21 Bit name Function RCKI RCKO Count clock selection bits These bits are used to select a count clock of the 12 bit PPG timer from four types of internal count clocks These bits are used to set the number of counts corresponding to the H width of 12 bit PPG timer outputs the compare value for th
328. ress it7 bit6 bit5 bit4 bit3 bit2 biti bitO 001 TIFO TFCRO TOIEN CINV TCS02 TCSO1 TCS00 TSTRO R RW RW RW RW RW RW RW TDR1 timer 1 data register Address bit6 bit5 bit4 bit3 bit2 bit bitO 001 RW RW RW RW RW RW RW RW TDRO timer 0 data register Address pit7 bit6 bits bit3 bit bito 001DH RW RW RW RW RW RW RW RW TCPH capture data register H Address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bitO I T T 7 T T T R R R R R R R R TCPL capture data register L bitb bit 001FH R R R R R R R R TCR2 timer output control register Address pit7 bite bit5 bit4 bits bit2 bit bito 00204 PEN TSEL RW R W Readable Writable Read only Undefined Unused 170 Initial value 000000008 Initial value 000 0000B Initial value 00000000B Initial value XXXXXXXXB Initial value XXXXXXXXB Initial value XXXXXXXXB Initial value XXXXXXXXB Initial value CHAPTER 8 8 16 BIT CAPTURE TIMER COUNTER 8 4 1 Capture Control Register TCCR The capture control register TCCR is used to select functions and detection edges control interrupts and check interrupt states in timer 0 for the 8 bit mode of the 8 16 bit capture timer counter or in capture mode 16 bit mode B Capture Control Register TCCR Figure 8 4 2 Capture Control Register TCCR Address bit7 bit6 bits bit2 bit
329. rial I O operation the interrupt request flag bit SMR SIOF is not set to 1 If the SIOF bit is set to 1 and the interrupt request output allowance bit is enabled SMR SIOE 1 control cannot return from interrupt processing Be sure to clear the SIOF bit e Shift clock idle state The external shift clock must maintain the H level during the wait time between one 8 bit data transfer and another idle state When the internal shift clock is selected SMR CKS1 CKSO not 115 and the P30 UCK SCK pin is used as the shift clock output pin SMR SCKE 1 data is output at the H level in the idle state Figure 14 9 1 shows the shift clock idle state External shift Figure 14 9 1 Shift Clock Idle State Idle state 8 bit data transfer Idle state 8 bitdatatransfer Idle state clock uununnnnn o uuuuuunn 333 CHAPTER 14 8 BIT SERIAL I O 14 10 Example of 8 Bit Serial I O Connection This section provides an example of mutual connection between 8 bit serial I Os of MB89202 F202RA series for bidirectional serial I O operation m When Bidirectional Serial I O Operation is Performed Figure 14 10 1 Example of 8 bit Serial I O Connection Interface between MB89202 F202RA Series SO Sl ge i i y Ad pum Output RS Input Output SCK Internal shift clock External shift clock 334 CHAPTER 14 8 BIT SERIAL I O Figure 14 10 2 Bidirectional Serial I O Operation SIO A Stop SIO A operatio
330. riate bit When A D conversion is activated the operations of A D conversion functions are started In addition even during conversion A D conversion functions can be reactivated Continuous activation To activate A D conversion functions continuously set registers as shown in Figure 12 6 2 273 CHAPTER 12 A D CONVERTER Figure 12 6 2 Setting A D Conversion Functions at Continuous Activation bit bit6 bits bit4 bits bit2 bitt ADC1 52 51 AD ADMV RESVO AD x ADC2 __ RESV4 RESV3 ADCK ADIE RESV2 EXT RESV1 0 0 0 1 1 ADDH The results of A D conversion are stored ADDL The results of A D conversion are stored ADEN Used bit Unused bit 1 Set 0 Set 1 to an appropriate bit When continuous activation is enabled A D conversion is activated on a rising edge of the selected input clock and the operations of A D conversion functions are started When continuous activation is disabled ADC2 EXT 0 continuous activation is stopped and activation with software is possible B Operations of A D Conversion Functions 274 The operations of the A D converter are described here It takes about 38 instruction cycles from activating A D conversion to completing it 1 When A D conversion is activated the conversion in progress flag bit is set ADC1 ADMV 1 and the analog input set is connected to the sample ho
331. riting data to these bits does not affect operations Note A reset source flag is set when a reset source is generated When the reset source flag register 15 read all bits in the reset source flag register are cleared Therefore to determine the source of a reset read this register using the initial value setting routine after the reset 46 CHAPTER 3 CPU 3 5 2 External Reset Pin The external reset pin generates a reset by L level input When an option setting for enabling reset output is selected the L level signal is output depending on the internal reset source m Block Diagram of External Reset Pin The external reset pin RST on models with supported reset output has hysteresis input and pull up N ch open drain output The external reset pin on models without supported reset output is used only as the pin dedicated to reset input Figure 3 5 2 is a block diagram of the external reset pin Figure 3 5 2 Block Diagram of External Reset Pin Pull up resistor Approx 50kQ for 5 V Not available for MB89F202 Internal reset source Internal reset signal m Function of the External Reset Pin The external reset pin RST generates an internal reset signal by making use of L level input The RST outputs the L level signal according to the internal reset source and oscillation stabilization wait time applied following a reset The internal reset source may be software reset watchdog reset or power o
332. rocessing interrupt may occur in this processing JMP MAIN Ensure that the time necessary for running the loop is shorter than the minimum time interval of the watchdog timer ENDS END 133 CHAPTER 6 WATCHDOG TIMER 134 CHAPTER 7 8 BIT PWM TIMER This chapter describes the functions and operations of 8 bit PWM timer 7 1 Overview of 8 bit PWM Timer 7 2 Configuration of 8 bit PWM Timer 7 3 Pin of 8 bit PWM Timer 7 4 Registers of 8 bit PWM Timer 7 5 Interrupt of 8 bit PWM Timer 7 6 Operations of the Interval Timer Functions 7 7 Operations of the 8 bit PWM Timer Functions 7 8 States in Each Mode During Operation 7 9 Notes on Using 8 bit PWM Timer 7 10 Program Example for PWM Timer 135 CHAPTER 7 8 BIT PWM TIMER 7 1 Overview of 8 bit PWM Timer An 8 bit PWM timer has the interval timer functions and the PWM timer functions of an 8 bit resolution A counter is incremented using interval timer functions in synchronization with three types of internal count clocks or the output of 8 16 bit capture timer counter The user can select one of these functions Therefore the 8 bit interval timer can be set and the square wave of any frequency can be output using the set output In addition if a low pass filter is connected to the PWM output the D A converter can be used m interval Timer Functions Functions to Output the Square Wave Interrupts are generated repeatedly at any interval by the interval timer
333. rol register TCRO is used to select functions allow and prohibit operation control interrupts and check interrupt states in timer 0 for the 8 bit mode of the 8 16 bit capture timer counter or in the 16 bit mode Even if only timer 0 is used in the 8 bit mode the timer 1 control register TCR1 must be initialized m Timer 0 Control Register TCRO Figure 8 4 3 Timer 0 Control Register TCRO Address bit7 bite bit5 bit3 bit2 bit1 bitO Initial value 001By TIFO TFCRO TOIEN CINV TCSO2 TCS01 TCSOO TSTRO 000000006 R RW RW R W Readable Writable R Read only Ec Initial value RW RW RW RW Timer start bit o The counter operation is stopped 1 The counter is cleared and increment starts 501 TCSO00 Clock source selection bits oscillation 12 5 MHz 2tinst 0 64 us 8 1 4tinst 1 28 us o i 16tinst 5 12 us 1 EN zm 1 1 1 1 64tinst 20 48 us 128tinst 40 96 us 1 256tinst 81 92 us 1 512tinst 163 84 us 1 1 External clock tinst Instruction cycle Affected by the clock mode and others Count clock selection bit The counter is incremented at the falling edge of a selected clock source The counter is incremented at the rising edge of a selected clock source Interrupt request enable bit 0 Interrupt request output is prohibited Interrupt request output is allowed Compare match detection flag clear bit 0 Not affected at read alw
334. rom standby mode to active mode subsequent operations depend on whether interrupt requests are acceptable Transition to Standby Mode and Interrupt When an interrupt request with an interrupt level higher than 11g is generated in a peripheral function to the CPU an attempt to write 1 into the stop bit STBC STP or sleep bit SLP in the standby control register is ignored Therefore any attempt at transition to standby mode fails Even after the interrupt is processed transition to standby mode is not allowed This type of rejection does not depend on whether the CPU can accept interrupts Even if the CPU is processing an interrupt transition to standby mode is allowed when the request flag bit for the interrupt has been cleared and there are no other interrupt requests to be processed m Cancellation of Standby Mode by an Interrupt When an interrupt request with an interrupt level higher than 11g is generated in a peripheral function or another component in sleep mode or stop mode standby mode is cancelled This operation does not depend on whether the CPU can accept interrupts After cancellation of standby mode the CPU normally takes a branch to the interrupt processing routine if the priority of the interrupt level setting register to ILR4 corresponding to the interrupt request is higher than the level specified in the interrupt level bits CCR IL1 and ILO in the condition code register and if the interrupt e
335. rovided the system clock control register SYCC selects the fastest clock CS1 CSO 11 with one instruction cycle 4 206 CHAPTER 9 12 BIT PPG TIMER Cycle period Compare value for cycle period x Count clock cycle period 011110 30 clock period x 2 x 4 FcH 30 x 2 x 0 32 us 19 2 us H width Compare value for H width x Count clock cycle period 001010 10 clock width x 2 x 4 10 x 2 x 0 32 us 6 4 us If the set H width is equal to or greater than the set cycle period H level outputs occur m 12 bit PPG Function The timer s programmable pulse output generator function can be used as a 12 bit PPG because it can set a cycle period and H pulse width of output pulse waveforms separately A range of controllable duty cycles is 0 02 to 100 However the smaller the compare value for the cycle period the lower the resolution the greater a minimum step duty cycle If the compare value for the cycle period is 2 a comparative setting of H pulse width is 1 or 2 a duty cycle of 50 or 100 and the resolution is 1 2 An output frequency and a duty cycle can be calculated using the following equations Output pulse cycle period Compare value for cycle period x Count clock cycle period Duty cycle Compare value for H width Compare value x 100 Table 9 1 2 lists available resolution values minimum step duty cycles and output pulse cycle periods Table 9 1 2 Resolutions and Outpu
336. rred and control bits l IL1 and ILO for controlling the acceptance of interrupt requests Configuration of the Condition Code Register CCR Figure 3 2 2 Configuration of Condition Code Register RP CCR bit15 bit14 bit13 bit12 bit bit10 bit9 bit8 bit7 bit6 bitS bit4 bit3 bit2 bit bitO CCR initial value PS R4 R8 R2 Ri ROT ONZE X011XXXXs Half carry flag a Interrupt enable flag Interrupt level bits Negative flag Zero flag Overflow flag Carry flag X Undefined m Bits for Indicating Arithmetic Operation Results Half carry flag When a carry from bit3 to bit4 or a borrow from bit4 to bit3 occurs as a result of an arithmetic operation the half carry flag is set to 1 Otherwise the half carry flag is cleared with 0 The half carry flag is intended only for decimal adjustment instructions and thus should not be used for operations other than addition or subtraction Negative flag N When the highest bit becomes 1 as a result of an arithmetic operation the negative flag is set to 1 When it becomes it is cleared with Zero flag Z When the result of an arithmetic operation is O the zero flag is set to 1 Otherwise the zero flag is cleared with 0 Overflow flag V When a complement on 2 overflow occurs as a result of an arithmetic operation the overflow flag is set to 1 Otherwise the overflow flag is cleared with 0
337. rrent cycle CHAPTER 3 CPU 3 4 3 Multiple Interrupts Multiple interrupts are allowed by setting different levels into the interrupt level setting registers ILR1 to ILR4 for multiple interrupt requests from peripheral functions m Multiple Interrupts When an interrupt request with a higher interrupt level is generated while the interrupt processing routine is operating the current interrupt processing cycle is stopped to accept the higher level interrupt request Interrupt levels 1 2 and 3 can be specified Level 3 prohibits the CPU from accepting interrupts Example of multiple interrupts As an example of multiple interrupt processing suppose a case in which a timer interrupt has precedence using the A D interrupt and the A D interrupt level is set to level 2 and the timer interrupt level is set to level 1 Figure 3 4 3 shows the sequence performed when an external interrupt is generated while an A D interrupt is being processed Figure 3 4 3 Example of Multiple Interrupts i A D interrupt Timer interrupt Main program processing processing Interrupt level 1 Initializes peripherals Interrupt level 2 Timer interrupt A D interrupt p processed generated Q Resumes processing Return from A D interrupt 5 timer interrupt processed processing Main program Return from A D restarts D interrupt processing In the A D interrupt processing the interrupt level bits in the condition code regi
338. rrupt processing routine are usually handled after the current interrupt processing routine ends If interrupt requests with the same assigned level are generated simultaneously IRQO has priority Table 3 4 1 Interrupt Requests and Interrupt Vectors 1 2 Address in the vector table Names of bits Priority at the interrupt identical level at level setting simultaneous registers occurrence Interrupt request Upper Lower digits digits IRQO External interrupt INT10 L01 LOO IRQI External interrupt INT11 L11 L10 IRQ External interrupt INT12 L21 L20 IRQ3 8 16 bit capture timer counter s timer L31 L30 IRQ4 8 16 bit capture timer counter s capture 141 140 IRQS5 Transmission with UART L51 L50 IRQ6 Reception with UART L61 L60 IRQ7 Time base timer L71 L70 IRQS A D converter L81 L80 IRQO 8 bit PWM L91 L90 IRQA External interrupt 2 LAO 34 Table 3 4 1 Interrupt Requests and Interrupt Vectors 2 2 Interrupt request IRQB Flash interface Address in the vector table Upper digits Lower digits Names of bits in the interrupt level setting registers LB1 LBO IRQC 8 bit serial I O LC1 LCO IRQD Unused LD1 LDO IRQE Unused LE1 LEO IRQF Unused LF1 LFO CHAPTER 3 CPU Priority at identical level at simultaneous occurrence 35 CHAPTER 3 CP
339. rruption Note Values in the accumulator A and temporary accumulator T are not automatically saved in the stack Therefore save and restore the values using the PUSHW and POPW instructions 41 CHAPTER 3 CPU 3 4 6 Stack Area for Interrupt Processing A stack area on RAM is used for interrupt processing The value in the stack pointer SP is used as the start address of the stack area B Stack Area for Interrupt Processing 42 The stack area is used to save restore the value in the program counter PC when executing the subroutine call instruction CALL or vector call instruction CALLV or temporarily save and restore values in registers or other storage with the PUSHW and POPW instruction Locate the stack area on RAM together with the data area e It is recommended that the initial settings be specified such that the stack pointer SP indicates the highest address of RAM and that the data area be set up from the lowest address of RAM Figure 3 4 6 is an example showing the stack area Figure 3 4 6 Stack Area for Interrupt Processing Data area Value recommended for SP When the highest RAM address is 027FH Access prohibited Note For the stack area interrupts subroutine calls or PUSHW instruction use addresses in descending order and the return instructions RETI and RET or the POPW instruction releases addresses in the stack area in ascending order When a lower address is used in
340. rupt request is allowed SSD TIE 1 UART prescaler baud rate generator clock divider selection register The clock input to the baud rate generator is changeable by switching the rate of division using the clock divider selection registers 286 CHAPTER 13 UART 13 3 Pins of UART Pins relating to UART are the clock I O pin P30 UCK SCK serial data output pin P31 UO SO and serial data input pin P32 UI SI m UART Relating Pins P30 UCK SCK This pin functions as the general purpose I O port P30 UART clock I O pin UCK or 8 bit serial clock T O pin SCK When clock output is enabled SMC SCKE 1 this pin functions as the UART clock output pin UCK regardless of the value in the corresponding port direction register When this pin functions as the UART clock do not use any external clock SRC CS1 and CSO must be other than 005 When using this pin as the UART clock input pin disable clock output SMC SCKE 0 and set it as the input port using the corresponding port direction register DDR3 bitO 0 In this case be sure to select the external clock SRC CS1 and CSO 005 e P31 UO SO This port functions as the general purpose I O port P31 UART serial data output pin UO or 8 bit serial data output pin SO When serial data output is enabled SMC SOE 1 this pin functions as the UART serial data output pin UO regardless of the value in the corresponding port direction register e
341. rview of UART UART is a general purpose communication interface for serial data UART allows variable length serial data to be transferred synchronously or asynchronously with a clock The transfer format is NRZ The dedicated baud rate generator external clock or internal timer 8 bit PWM timer settings determine the data transfer format m Functions of UART UART supports serial I O functions for sending serial data to or receiving serial data from a CPU or peripheral functions The full duplex double buffer enables bi directional full duplex communication e Synchronous data transfer mode or asynchronous data transfer mode can be selected The internal baud rate generator allows one of 14 baud rates to be selected Also external clock input and 8 bit PWM timer output allow user defined baud rates to be specified The length of data is variable When no parity is used 7 bits to 9 bits are available When parity is used 6 bits to 8 bits are available Table 13 1 1 The data transfer format is NRZ Non Return to Zero Table 13 1 2 provides the transfer rates of the dedicated baud rate generator and Table 13 1 3 provides the transfer rates of the external clock Table 13 1 1 UART Operating Modes Data length Operating mode Synchronization mode Stop bit length Parity not used Parity used 7 bits Synchronous asynchronous 1 bit or 2 bits 8 bits Synchronous asynchronous bit or 2 bits 8 1 bits Syn
342. s Mode The MB89202 F202RA series supports only single chip mode for access to memory m Single chip Mode In single chip mode only internal RAM and ROM are used The CPU can access only the internal I O area RAM area and ROM area m Mode Data Set 00g into the mode data in internal ROM to select single chip mode Figure 3 8 1 Configuration of Mode Data bit7 bit6 bits bit4 bit2 FFFDH Selects single chip mode Other than 00H Reserved Do not specify this value B Operations for Selecting Memory Access Mode 72 Only single chip mode is selectable Table 3 8 1 provides the settings for the mode pins and mode data Table 3 8 1 Settings for Mode Data Single chip mode 00g Other modes Prohibited Figure 3 8 2 shows the operations for selecting memory access Figure 3 8 2 Wait for cancellation of the reset source external reset or oscillation stabilization wait time Mode fetch Check of the mode data Setup of I O pin functions at execution of program RUN mode Prohibited CHAPTER 3 CPU Operations for Selecting Memory Access Source of a reset is generated I O pins are high impedance Mode data and reset vector are fetched from internal ROM Other settings Mode data Single chip mode 00 I O settings for each I O pin using the port direction register DDR and other measures I O pins are available as ports 73 CHAPTER 3 CPU
343. s Related to the Wild Register Function D 350 Serial Data Register SDR 323 Serial Input Data Register SIDR 297 Serial Mode Control Register SMC 290 Serial Mode Register SMR 320 Serial Output Data Register SODR 298 Serial Rate Control Register SRC 292 Serial Status and Data Register SSD 294 Serial Switch Register SSEL 301 Standby Control Register STBC 66 Time base Timer Control Register TBTC 119 Timer 0 Control Register TCRO 173 Timer 0 Data Register 178 Timer 1 Control Register TCR1 175 Timer 1 Data Register TDR1 180 Timer Output Control Register TCR2 177 UART Interrupt Related Registers and Vector Table Addresses eiii ner innen 303 UART relating Registers suus 289 Watchdog Control Register WDTC 130 Wild Register Addresses List 356 Wild Register Applicable Addresses 348 Wild Register Function eese 348 Register Bank Pointer Configuration of the Register Bank Pointer RP Meses gl vue 31 Reset Block Diagram of External Reset Pin
344. s immediately after immediately before or while data is written the contents in the address to which data is written at that time is not guaranteed 49 CHAPTER 3 CPU 3 5 4 State of Each Pin at Reset The state of each pin is initialized by a reset B States of Pins during Reset When a reset occurs most I O pins resource pins become Hi Z and the CPU reads the mode data from internal ROM States of Pins after the CPU Reads the Mode Data Most of the I O pins remain Hi Z immediately after the CPU reads the mode data For pin states established by something other than a reset see APPENDIX E Pin State of the MB89202 F202RA Series for details Note For pins that are Hi Z when a reset source is generated set up the devices connected with the pins such that they do not malfunction 50 CHAPTER 3 CPU 3 6 Clock The clock generator includes the oscillation circuit A high speed clock is generated by connecting an external resonator for oscillation frequency Alternatively when the clock is supplied from an external source a clock signal can be connected to the clock input pin The clock controller manages the speed and supply of the clock in active mode and standby mode m Clock Supply Map The clock controller manages oscillation of the clock and provision of the clock to the CPU and peripheral circuits peripheral functions Thus the operating clock for the CPU or peripheral circuits is affected by
345. s in mm inches 2003 FUJITSU LIMITED F34003S c 2 3 Note The values in parentheses are reference values Please confirm the latest Package dimension by following URL http edevice fujitsu com f DATASHEET ef ovpklv html 11 CHAPTER 1 OVERVIEW 1 7 Pin Functions Description Table 1 7 1 describes the I O pins and functions The letters in the circuit type column shown in Table 1 7 1 correspond to the letters in the Circuit Type column shown in Table 1 8 1 m Pin Functions Description Table 1 7 1 Pin Functions Description 1 2 Pin No Circuit Function type SHDIP32 SSOP34 Pins for connecting the crystal for the main clock To use an external clock input the signal to XO and leave X1 open General purpose CMOS input port Reset I O pin This pin serves as an N ch open drain reset output and a reset input as well The reset is a hysteresis input It outputs the L signal in response to an internal reset request Also it initializes the internal circuit upon input of the L signal P00 General purpose CMOS I O ports INT20 These pins also serve as an input wake up input of external ANA interrupt 2 or as an 10 bit A D converter analog input The input of P01 external interrupt 2 is a hysteresis input INT21 AN5 P02 General purpose CMOS I O ports INT22 These pins also serve as an input wake up input of external AN6 interrupt 2 or as an 10 bit A D converter analog
346. s in the TDRO are reset in the comparator data latch the counter is cleared and the count operation is continued The comparator data latch is reset when a match is detected thus the values written to the TDRO when the counter is in operation become valid from the next cycle after match detection Note The values set in TDRO when the interval timer is in operation can be calculated from the expression shown below However the instruction cycle is affected by the clock mode and gear function Values set in TDRO interval time count clock cycle x instruction cycle 1 178 CHAPTER 8 8 16 BIT CAPTURE TIMER COUNTER 16 bit mode The values in TDRO are compared with the counter values in the lower 8 bits of the 16 bit timer When the interval timer function is used the lower 8 bits of the interval time are set When the counter function is used the lower 8 bits of the count value to be detected are set The values in TDRO are loaded to the lower 8 bits of the comparator data latch when matching the counter values of the 16 bit timer or when the count operation is started The values written to TDRO when the 16 bit counter is in operation become valid after match detection For the values set in TDR1 when the interval timer function is used see Section 8 4 6 Timer 1 Data Register TDR1 179 CHAPTER 8 8 16 BIT CAPTURE TIMER COUNTER 8 4 6 Timer 1 Data Register TDR1 The timer 1 data register TDR1 is used to set
347. s the shift clock input pin When using the SCK pin as the shift clock input pin set it to input port with the port direction register DDR3 bit3 0 and prohibit shift clock output SMR SCKE 0 In this case be sure to select the external shift clock SMR CKS1 CKSO 115 When using the P30 UCK SCK pin as the shift clock output pin When the shift clock output is allowed SMR SCKE 1 the P30 UCK SCK pin automatically becomes an output pin irrespective of the values in the port direction register DDR3 bitO and functions as the SCK output pin In this case be sure to select an internal shift clock when SMR CKS1 CKSO are not 11g 317 CHAPTER 14 8 BIT SERIAL I O m Block Diagram for 8 bit Serial 1 0 Pins Figure 14 3 1 Block Diagram for 8 bit Serial I O Pins a P30 UCK SCK a P32 UI SI PDR read Resource output Stop mode SPL 1 Resource a Resource output a output enable available PDR read read modify write Pull up resistor gt Output latch 1 write P30 UCK SCK P31 UO SO P32 UI SI gt a 5 c E DDR write PUL read PUL write Note When pull up resistor available is selected in the pull up setting register the pin state in stop mode SPL 1 becomes high pull up state not Hi Z During the reset however pull up becomes invalid and the pin state becomes Hi Z 318 CHAPTER 14 8 BIT SERI
348. sed Initial value 97 CHAPTER 4 I O PORTS 4 5 2 Operations of Port 5 Functions This section describes the operation of port 5 B Operation of Port 5 Operation in output port mode When 1 is written for a bit of the DDR5 register the bit corresponding to the pin of port 5 the pin functions as an output port In output port mode the output transistor operation is enabled and the output latch data is output to the pin Once data has been written into the PDR5 register the written data is held in the output latch and output to the pin as it is The value state of the pin can be read by reading the PDR5 register Operation in input port mode When 0 is written for a bit of the DDR5 register the bit corresponding to the pin of port 5 the pin functions as an input port In input port mode the output transistor is OFF and the pin state is Hi Z Once data has been written into the DDRS register the written data is held in the output latch but is not output to the pin The value state of the pin can be read by reading the PDR5 register Operation in mode enabling the output from a peripheral When the output enable bit for a peripheral is set enable the corresponding pin is set to serve the output from the peripheral Because the value state of the pin can be read from the PDRS register even when the output from the peripheral is enabled the value output from the peripheral can be read Operatio
349. sed bits The values read out from these bits are undefined Writing values to these bits does not affect any operations CR Clock rate input selection bit This bit selects the clock rate in asynchronous transfer mode However when the dedicated baud rate generator is used CS1 and CSO 115 it is fixed at 1 8 regardless of the value in the CR bit Specifying an external clock or 8 bit PWM timer output as the clock input the baud rate is set to 1 16 or 1 64 of the corresponding clock frequency depending on the CR value This bit is not significant in synchronous transfer mode CS1 CS0 Clock input selection bits These bits select the clock input The clock input can be an external clock UCK pin 8 bit PWM timer or dedicated baud rate generator RC2 RC1 RCO Baud rate selection bits There are 8 types of baud rate in asynchronous transfer mode and 6 types of baud rate in synchronous transfer mode 14 types of baud rate are selectable in total These bits are effective only when the dedicated baud rate generator is used for the clock input These bits are not significant when an external clock or 8 bit PWM timer output is used 293 CHAPTER 13 UART 13 4 3 Serial Status and Data Register SSD The serial status and data register SSD controls data transmission reception of UART and status in an error enables disables interrupts and specifies and checks settings for parity or bit 8 transmitting dat
350. set edge detection to OFF however no external interrupt requests are generated and when interrupt request outputs are disabled no interrupt requests are output The pin state can be read directly from the port data register PDR3 at any time Table 10 3 1 lists the pins associated with external interrupt circuit 1 Table 10 3 1 Pins Associated with External Interrupt Circuit 1 Use for input port only Interrupt request output or edge detection disabled Use for external interrupt input Interrupt request output enabled INT10 EIC1 ETEO 1 DDR3 bit4 0 P34 EIC1 EIE0 0 or 81 01 SLOO TCR2 PEN 0 34 EIC 1 EIE0 0 or SLO1 SL00 00g P34 TO INT 10 P35 INT11 INT11 EIC1 EIE1 1 DDR3 bit5 0 P35 EIC1 EIE1 0 SL11 SL10 005 P36 INT12 INT12 EIC2 EIE2 1 DDR3 bit6 0 P36 EIC2 EIE2 0 SL21 SL20 005 INT10 to INT12 When a signal with an edge or edges corresponding to the selected edge polarity is input to these pins an interrupt corresponding to the pin is generated 229 CHAPTER 10 EXTERNAL INTERRUPT CIRCUIT 1 EDGE m Block Diagram of Circuitry Terminating at the Pins Associated with External Interrupt Circuit 1 Figure 10 3 1 Block Diagram of Circuitry Terminating at the Pins Associated with External Interrupt Circuit 1 230 ut utput occurrin periph i RRR ag modify write is performed o 2 a s g Is o D 2 Stop mode SPL 1 PU
351. sing Time base Timer 124 Notes on Using Watchdog Timer 132 Operating Mode Reception Operations Operating Mode 0 1 or 3 daretur reist i que LIEGE POETE 307 Reception Operations Operating Mode 2 Only PATE 309 Theory of Operation for Operating Mode 0 1 2 and 3 Jared E HE eo P eda 305 Transmission Operations in Operating Mode is OVD OF 3 cete e eite ice 306 Operation Bits for Indicating Arithmetic Operation Results dee DE PU deser a 29 Capture Function Operation 193 Counter Function Operation 189 Example of Operations of 12 bit PPG Timer Functions raa aa rn FPE 219 Interrupt at Serial I O Operation 324 Interrupt during the Operation of External Interrupt Careuit o iie deiecit ee Upon 237 Interrupt during the Operation of External Interrupt CHO 253 Interval Timer Function 185 Operation at Serial Input Completion 328 Operation at Serial Output Completion 326 Operation in Standby Mode and at Halfway Stop 197 Operation Instructions 394 Operation of External Interrupt Circuit 1 239 Operation of External Interrupt Circuit 2 254 Operation of Port 0 82 Operation of Por
352. sion frequency with a period of about 38 us and a duty cycle of approx 3396 is generated e The compare value for the PPG output pulse cycle period giving the above period of about 38 us at the maximum gear speed with oscillation of 12 5 MHz Fcp is determined as below The count clock is assumed to be 4 Compare value for cycle period RCR23 SCL5 to SCLO and RCR24 SCL11 to SCL6 38 us 4 x 4 10MHz 30 The compare value for the H width of the PPG output pulse giving the duty cycle of approx 33 is determined as below At this time the width is about 3 us Compare value for the width RCR21 HSC5 to HSCO and RCR22 HSC11 to HSC6 233 100 x Compare value for the cycle period 0 33 x 30 10 Coding example RCR21 EQU RCR22 EQU RCR23 EQU RCR24 EQU 0014H 0015H 0016H 0017H RCR21 01001010B RCR22 00H RCR23 10011110B RCR24 00H Address of 12 bit PPG control register 1 Address of 12 bit PPG control register 2 Address of 12 bit PPG control register 3 Address of 12 bit PPG control register 4 CODE SEGMENT Select count clock of 4 and set the above compare value for width Specify outputs enabled and counter operation start and set the above compare value for cycle period 223 CHAPTER 9 12 BIT PPG TIMER 224 CHAPTER 10 EXTERNAL INTERRUPT CIRCUIT 1 EDGE This chapter describes the function and operation of external interrupt circuit 1 edge 10 1 Overv
353. slightly with the models Table 16 1 1 shows the wild register applicable addresses for each model Table 16 1 1 Wild Register Applicable Addresses MB89V201 8000y to FFFFy MB89202 F202 C000g to FFFFY Note The wild register function cannot be debugged with a tool Perform the operation check of the wild register on the actual microcontroller MB89202 F202 F202RA 348 CHAPTER 16 WILD REGISTER FUNCTION 16 2 Configuration of the Wild Register Function The wild register function consists of the following two blocks Memory area part e Data setting register WRDR Higher address set register WRARH Lower address set register WRARL Control circuit part m Block Diagram of the Wild Register Function Figure 16 2 1 Block Diagram of Wild Register Function Wild register function Incorporated ROM RAM Memory area part Data setting register WRDR Higher address set register WRARH a 3 a o c o 2 Lower address set register WRARL Control circuit part Access control circuit Address comparison EN register WREN Address comparison Access control Matching signal Memory area part This part consists of the data setting register higher address set register H address and lower address set register L address Set the address and data to be replaced by the wild register The MB89202 F202RA seri
354. specified intervals after being activated If the timer is not cleared within a specified period of time because for example a program goes into an endless loop the timer sends to the CPU a watchdog reset having a period of four instruction cycles The watchdog timer uses the output from the time base timer as the count clock The time intervals for the watchdog timer are listed in Table 6 1 1 When the watchdog timer is not cleared a watchdog reset occurs following the time between the minimum time interval and the maximum time interval The counter must be cleared before the time of the minimum time interval Table 6 1 1 Watchdog Timer Time Intervals Count clock Time base timer output Oscillation frequency 12 5 MHz Minimum time interval Approximately 335 5 ms Maximum time interval Approximately 671 0 ms number of counts of time base timer 222 X oscillation frequency Fcp divided by 2 See Section 6 4 Operations of Watchdog Timer Functions for details on the maximum and minimum time intervals of the watchdog timer Notes The watchdog timer counter is cleared when the time base counter is cleared TBTC TBR 0 while output from the time base timer is selected Therefore if the time base timer counter supplying the count clock is cleared repeatedly within the time interval of the watchdog timer the watchdog timer does not function correctly When switching to sleep or stop mode the watchdog ti
355. ss indicated by the contents of A before execution The contents of after execution become the value of the address next to the address holding the operation code XCHW A PC This instruction is useful especially when a table is specified in the main routine and a subroutine uses it Figure B 2 5 shows an overview Figure B 2 5 XCHW A PC Before execution After execution a a 1235s PC 5678H After execution of this instruction the contents of A do not become the address holding the operation code of this instruction Instead they are the same as the address holding the next instruction In Figure B 2 5 therefore the value stored in A is 1235 agreeing with the address holding the operation code next to XCHW A PC Note that it is not 1234y but 1235g Figure B 2 6 shows an example of assembler coding Figure B 2 6 Usage Example of XCHW A PC Main routine Subroutine MOVW PUTSUB XCHW EP PUSHW A XCHW A DB PUT OUT DATA EOL PTS1 MOV A EP MOVW A 1234H INCW EP MOV 10 A CMP 121828 BNE PTS1 POPW A XCHW A EP JMP QA 389 APPENDIX B Overview of the Instructions vct This addressing is used for branching to one of the subroutine addresses registered in the table After the return address the contents of PC is saved to the address indexed by SP stack pointer the control is branched to the address listed in t
356. start bit detection circuit detects start bits in serial input signals When the start bit detection circuit detects a start bit it writes data into the SIDR with shifts in accordance with the transfer rate When parity is used the received parity handling circuit stores the parity bit in the data received It also stores the most significant bit of 9 bit data received Transmission control circuit The transmission control circuit consists of the transmitted byte counter and transmitted parity handling circuit The transmitted byte counter takes count of data to be transmitted When a unit of data that corresponds to the specified data length is fully transmitted an interrupt request is generated When parity is used the transmitted parity handling circuit generates a parity bit for the data to be transmitted It sets the most significant bit for data transmitted when it is made up of 9 bits 285 CHAPTER 13 UART UART interrupt sources Reception When data with the specified length is correctly received or when the overrun error or framing error occurs while data is being received the reception interrupt request IRQ6 is generated if the reception interrupt request is enabled SSD RIE 1 Transmission When data to be transmitted is written into the SODR register sent to the internal shift register and the next data then becomes writable the transmission interrupt request IRQ5 is generated if the transmission inter
357. ster CCR IL1 and ILO are set to the same value as the value in the interrupt level setting register corresponding to the A D interrupt ILR1 2 3 or 4 1 2 in this example If an interrupt request with a higher interrupt level specified is generated 1 in this example processing for the higher interrupt level is effected first To temporarily prohibit multiple interrupts in the A D interrupt processing turn off the interrupt enable flag CCR I 0 in the condition code register or set 00g to the interrupt level bits IL1 and ILO Executing the return instruction RETI after interrupt processing restores the values of the program counter PC and program status PS and ensures resumption of the interrupted program The value in the condition code register CCR is returned to the value used before interruption when the program status PS value is restored 39 CHAPTER 3 CPU 3 4 4 Interrupt Processing Time From when an interrupt request is generated to when control is transferred to the interrupt processing routine both the time to quit the instruction being executed and the time to manage the interrupt required to prepare interrupt processing are required The total time must be within 30 instruction cycles m interrupt Processing Time From when an interrupt request is generated and accepted to when the interrupt processing routine starts sufficient time is required to wait for an interrupt request sample
358. t 3 88 Operation of Port 4 93 Operation of Port 5 98 Operation of Port 6 105 Operation of Port 7 111 Operations for Selecting Memory Access Mode tatit oeste un s A Ete 72 Operations in Active Mode 59 Operations in Each Clock Mode 58 Operations in Standby Mode 63 Operations in the Standby Mode and at a Suspension ax Rega 152 Operations of A D Conversion Functions 274 Operations of Clock Supply Function 122 Operations of Interval Timer Function Time base Timer 122 Operations of the 8 bit PWM Timer Functions 150 Operations of the Interval Timer Functions 148 Operations of Time base Timer 122 Operations of Watchdog Timer 131 Operations Related to Sleep Mode 64 Operations Related to Stop Mode 65 Overview of the Reset 48 Pin States in Each Operation Mode 402 Read modify write Operation 391 Reception Operations Operating Mode 0 1 or 3 307 Reception Operations Operating Mode 2 Only
359. t Enable Bits for External Interrupt Circuit 2 and the External Interrupt Pins The interrupt enable bits are associated with the external interrupt pins as listed in Table 11 3 2 Table 11 3 2 Correspondence between the External Interrupt Enable Bits and the External Register 248 Interrupt Pins Bit name External interrupt pin bit2 IE22 INT22 bitl IE21 INT21 bitO IE20 INT20 CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT 2 LEVEL 11 4 Registers of External Interrupt Circuit 2 The external interrupt 2 control register EIE2 is used to enable or disable the external interrupt pins m Registers Associated with External Interrupt Circuit 2 Figure 11 4 1 Registers Associated with External Interrupt Circuit 2 EIE2 External interrupt 2 control register Address bit7 bit6 bit5 bit4 bit2 bit bito Initial value 0036H IE20 000000008 RAN RW RW RW RW RW RW RW EIF2 External interrupt 2 flag register Address bit7 bit bit5 bit4 bit3 bit2 bit bito Initial value gimp pompe pe es Da R W R W Readable Writable x Unused 249 CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT 2 LEVEL 11 4 1 External Interrupt 2 Control Register EIE2 The external interrupt circuit 2 control register EIE2 enables or disables the interrupt inputs to the external interrupt pins INT20 to INT27 m External Interrupt Circuit 2 Control Register EIE2 Figure 11 4 2 Ext
360. t Pulse Cycle Periods Supported when the Timer is Used as a 12 bit PPG 1 2 Range of Output pulse cycle period available Minimum compare Resolution step duty values for cycle Compare value for cycle Count clock Count clock Count clock Count clock period H width 2 4 16 tinst 256 Unavailable 4 tINST 32 tINST 512 tINST 6 UNST 48 tINST 768 tINST 8 tINST 64 tINST 1024 trust 10 tinsT 80 tINsT 1280 tiNsT 12 tjNsT 96 tINST 1536 tINST 112 tryst 1792 128 tINST 2048 tINST 207 CHAPTER 9 12 BIT PPG TIMER Table 9 1 2 Resolutions and Output Pulse Cycle Periods Supported when the Timer is Used as a 12 bit Compare value for cycle period PPG 2 2 Range of available compare values for H width Output pulse cycle period Count clock 2 Count clock 4 tinsT Count clock 16 144 tINST Count clock 256 2304 tINST Resolution Minimum step duty cycle 160 tinsT 2560 tinstT 1 to 100 1600 tinsT 25600 tINST 1 to 500 8000 tinsT 128000 tinsT 1 to 1000 4000 tryst 16000 tryst 256000 1 1000 1 to 2000 8000 tINST 32000 tINST 512000 INST 1 2000 1 to 3000 768000 tryst 1 3000 1 to 4095 trust Instruction cycle 208 16380 1048320 1 4095
361. t pin Intimer 0 for the 8 bit mode a count operation up to 28 is possible Inthe 16 bit mode a count operation up to 216 is possible e Inputting an external clock whose cycle is constant enables the counter to be used as a device whose function is similar to an interval timer 165 CHAPTER 8 8 16 BIT CAPTURE TIMER COUNTER 8 2 Configuration of 8 16 bit Capture Timer Counter The 8 16 bit capture timer counter consists of the following seven blocks Count clock selectors 0 1 Counter circuits 0 1 Square wave output control circuit Timer 0 1 data registers TDRO TD R1 Timer 0 1 control registers TCRO TCR1 Capture data registers TCPL TCP Timer output control register TCR H 2 m Block Diagram of 8 16 bit Capture Timer Counter Figure 8 2 1 Block Diagram of 8 16 bit Capture Timer Counter TSTRO TCS00 501 TCS02 CINV TOIEN TFCRO TIFO 3 TCRO TCCR RESV EDGSO EDGS1 TCMSK ma Counter CCMSK CPIEN CFCLR CPIF Counter clear Counter clear Capture latch CK am CLR amp bit counter L co Sk capture clr lear mask idehtity clr L omparator EQ ure P34 TO INT10 Pin D gt TDR1 LOAD comparator latch E Data register L Data register H Capture register H Internal data bus Y TCPH LOAD comparator latch Comparator EQ F CLR 8 bit counter
362. t time m Configuration of the System Clock Control Register SYCC Figure 3 6 5 Configuration of System Clock Control Register SYCC Address bit7 bit6 bit5 bit4 bits bit2 biti bitO Initial value 00074 SCM WT1 WTO 51 50 1 00 R Readable Writable Read only Unused Mask option Initial value 56 R W R W Clock speed selection bits CS1 CS0 Instruction cycle when Fcu is 12 5 MHz 0 0 6 12 us 0 1 16 Foy 1 28 us 1 0 8 Foy 0 64 us 4 F ou 0 32 us Oscillation stabilization wait time selection bits TO Oscillation stabilization wait time according to output of the time base timer when FcH is 12 5 MHz Setting prohibited 1 Approx 214 approx 1 31 ms Approx 217 approx 10 5 ms 1 Approx 218 approx 21 0 ms System clock monitor bit 0 Clock stopping or waiting for stabilization of oscillation Active mode CHAPTER 3 CPU Table 3 6 1 Explanation of Functions of Each Bit in the System Clock Control Register SYCC Bit name Description SCM System clock monitor bit Used to check the current clock mode When this bit is 0 the clock is stopping or waiting for stabilization of oscillation When this bit is 1 operations are performed in active mode Note This bit is read only enabled Writing a value to this bit does not affect operation Unused bits Values in these bits are und
363. t time has expired Watchdog reset Watchdog reset generates a 4 instruction cycle reset when no data is written into the watchdog control register WDTC within a specified time after the watchdog timer is activated Watchdog reset does not wait until oscillation stabilization wait time is up 43 CHAPTER 3 CPU Power on reset Power on reset occurs when power is turned on Power on reset occurs after oscillation stabilization wait time has expired Power on reset requires an external reset circuit Reset Sources and Oscillation Stabilization Wait Time Operations in oscillation stabilization wait time depend on the operating mode used when a reset occurs After a reset active mode is set regardless of the operating mode applied before the reset standby mode and reset source Therefore if a reset occurs while oscillation is being stopped or within the oscillation stabilization wait time the oscillation stabilization wait reset mode is set Software reset and watchdog reset do not apply oscillation stabilization wait time Table 3 5 2 shows the relationship between reset sources oscillation stabilization wait time and the reset operation mode fetch Table 3 5 2 Relationship between the Reset Sources and Oscillation Stabilization Wait Time Reset source Operating mode Reset operation and oscillation stabilization wait time When power is External reset turned on or stop mode The reset operation is performed when
364. t2 bit1 bito Initial value o9 cR csi cso RC2 RC1 011000 R W R W R W R W R W R W SSD serial status and data register Address bit7 bit6 bit5 bit4 bit3 bit2 bit bitO Initial value 002AH RDRF ORFE TDRE TIE RIE TD8 TP RD8 RP 00100 1 R R R W R W R W R W R SIDR serial input data register Address bit7 bit6 bit5 bit4 bit3 bit2 bit bito Initial value 002By XXXXXXXXB R R R R R R R R SODR serial output data register Address bit7 bits bit3 bit2 bit bito Initial value 002Bu XXXXXXXXB W W W W W UPC clock divider selection register Address bit7 bit6 bits bit4 bit3 bit2 bit bitO Initial value 0020 PREN PR2 PRi PRO 0010 R W R W R W R W SSEL serial switch register Address bit7 bits bit3 bit2 bit bito ODE _ SSEL R W Readable Writable Read only Write only Unused Undefined 289 CHAPTER 13 UART 13 4 4 Serial Mode Control Register SMC The serial mode control register SMC specifies the parity setting stop bit length operating mode data length and synchronous asynchronous mode and enables disables UART serial clock output and serial data output m Serial Mode Control Register SMC Figure 13 4 2 Serial Mode Control Register SMC Address bit7 bit6 bits bit4 bit3 bit2 biti bitO Initial value
365. ta direction register 00000000 Vacancy System clock control register 1 11100 Standby control register 00010 Watchdog control register 0 Time base timer control register 00 000 Vacancy Port 3 data register XXXXXXXX Port 3 data direction register 00000000 Reset flag register XXXX Port 4 data register XXXX Port 4 data direction register 0000 Port 4 output format register Port 5 data register Port 5 data direction register 12 bit PPG control register 1 00000000 12 bit PPG control register 2 000000 12 bit PPG control register 3 0 000000 12 bit PPG control register 4 000000 376 Table A 1 I O Map 2 4 Address Register abbreviation Register name Buzzer register Read write Initial value Capture control register 00000000 Timer 1 control register 000 0000 Timer 0 control register 00000000 Timer 1 data register XXXXXXXX Timer 0 data register XXXXXXXX Capture data register H XXXXXXXX Capture data register L XXXXXXXX Timer output control register Vacancy PWM control register 0 000000 PWM compare register XXXXXXXX External interrupt 1 control register 1 External interrupt 1 control register 2 Vacancy Serial mode control register Serial rate control register 00000000 00000 00 011000
366. tails see Section 3 4 Interrupts Section 3 5 Reset CALLV vct in APPENDIX B 2 Special Instructions Table 3 1 1 Vector Table 1 2 Address in the vector table Vector call instruction Upper digits Lower digits CALLV 0 CALLV 1 CALLV 2 CALLYV 3 FFC7g CALLYV 4 FFC8g FFC9g CALLYV 5 FFCAg FFCBy CALLYV 6 FFCCH FFCDg CALLNV 7 FFCEg FFCFy IRQF FFDCy FFDDy IRQE FFDEq FFDFy IRQD FFElg IRQC FFE2qQ FFE3 4 24 CHAPTER 3 CPU Table 3 1 1 Vector Table 2 2 Address in the vector table Vector call instruction Upper digits Lower digits IRQB IRQA IRQ9 IRQS IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQI IRQO Mode data Reset vector For MB89202 MB89V201 FFFC is prohibited Use For MB89F202 F202RA write 01 to FFFCy to activate read protection otherwise write 25 CHAPTER 3 CPU 3 1 2 Location of 16 bit Data on Memory Upper digits of 16 bit data and stack data are stored in lower addresses on memory 16 bit Data Storage State on RAM When 16 bit data is written into RAM the upper byte of the data is stored with a lower address and the lower byte of the data is stored with the next address 16 bit data is read in the same manner Figure 3 1 2 shows the location of 16 bit data on RAM Figure 3 1 2 Location of 16 bit Data on R
367. taken when selecting a MB89202 F202RA series model m Precautions when Selecting a Model Table 1 3 1 Differences between Models Package DIP 32P M06 MB89201 MB89F202 F202RA MB89V202 FPT 32P M03 FPT 64P M03 Current consumption When operated at a low speed the current consumption of a model with a flash is greater than that of a model with a mask ROM though the current consumption in sleep or stop mode is the same Notes For details on each package see Section 1 6 Package Dimensions For details on current consumption and electrical characteristics of A D converter see the electrical characteristics in the Data Sheet CHAPTER 1 OVERVIEW 1 4 Block Diagram of MB89202 F202RA Series Figure 1 4 1 shows the block diagram of the MB89202 F202RA series m Block Diagram of MB89202 F202RA Series Figure 1 4 1 Block Diagram of MB89202 F202RA Series Main clock oscillator Time base timer Clock controller CMOS I O port RST 8 bit PWM P50 PWM P60 P61 gt i UART prescaler P70 3 to P72 P04 INT24 CMOS I O port to _ P30 UCK SCK P07 INT27 gt P31 UO SO P32 UI SI Internal bus External P02 INT22 AN6 interrupt2 P03 INT23 AN7 wake up serial o 2 2 o S ic o INT20 P01 INT21 AN5 8 16 bit P33 EC 10 bit A D capture timer converter counter
368. te 17 5 Detailed Explanation of Writing to Erasing Flash Memory 17 6 Flash Security Feature 17 7 Notes on using Flash Memory 357 CHAPTER 17 FLASH MEMORY 17 1 Overview of Flash Memory The 128K bit flash memory is mapped to the C000 to FFFF bank the CPU memory map The functions of the flash memory interface circuit enable read access and program access from the CPU in the same way as mask ROM Instructions from the CPU can be used via the flash memory interface circuit to write data to and erase data from the flash memory Internal CPU control therefore enables rewriting of the flash memory while it is mounted As a result improvements in programs and data can be performed efficiently m Flash Memory Features e 16 Kbyte x 8 bit configuration e Use of automatic program algorithm Embedded Algorthm Detection of completion of writing erasing using data polling or toggle bit functions Detection of completion of writing erasing using CPU interrupts Compatible with JEDEC standard commands Minimum of 10000 write erase operations MB89F202 F202RA m High voltage supply on RST pin applicable to MB89F202RA only During writing data to or erasing all data in flash memory a typical 10V D C voltage should be applied at the RST pin After applying the high voltage wait for 10ms before writing data or erasing all data in flash memory And this applied voltage should be kept at the RST pin until data writing or eras
369. tects L level at any of the external interrupt pins then generates and issues an interrupt request to the CPU B Operation of External Interrupt Circuit 2 To operate the external interrupt circuit 2 the bits of the registers must be set as shown in Figure 11 6 1 Figure 11 6 1 Setting External Interrupt Circuit 2 bit7 bite bit5 bit4 bit3 bit2 bit EIE2 EF gt gt F I I TI I DL 0 0 0 0 0 0 0 0 N I T I I T T T 0 0 0 0 x X x x Used bit x Unused bit 0 Set 0 When an L level signal is input to an external interrupt pin among the pins INT20 to INT27 with external interrupt inputs being enabled by one of the IE20 to IE27 bits corresponding to the pin external interrupt circuit 2 generates and issues an IRQA interrupt request to the CPU Figure 11 6 2 shows the operation of external interrupt circuit 2 when the INT20 AN4 pin is used 254 CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT 2 LEVEL Figure 11 6 2 Operation of External Interrupt 2 INT20 Pulse waveform input to INT20 AN4 pin Detection of the L level External interrupt input enabled state I EIE2 IE20 Clear the bit within interrupt processing routine EIF2 IF20 Interrupt processing Interrupt processing Operation of interrupt GIA Sing routine for RETI Can be read at any time PDRO bitO Note
370. ter 16 bits Program counter 16 bits Stack pointer 16 bits Program status 16 bits Either accumulator or index register 16 bits Condition code register 8 bits Register bank pointer 5 bits General purpose register 8 bits i 0 to 7 Indicates that X itself is the immediate data 8 bits or 16 bits determined on basis of instruction to be used Indicates that the contents of X is the accessing subject 8 bits or 16 bits determined on basis of instruction to be used Indicates that the address specified in X is the accessing subject 8 bits or 16 bits determined on basis of instruction to be used 381 APPENDIX B Overview of the Instructions m Explanation on the Items of Instructions List Table B 2 Explanation on Items of Instructions List Item Description MNEMONIC Represents the instruction coded in the assembler Indicates the number of cycles of the instruction number of instruction cycles Indicates the number of bytes of the instruction Operation Indicates the operation of the instruction Indicates how the contents of TL TH and AH change automatic transfer from A to T when the instruction is executed The codes in this column indicate the following e indicates no change dH indicates the higher 8 bits of the data coded for the operation e AL and AH indicate the contents of AL and AH just before the execution of the
371. ter 1 ADC1 o 2 a iw 5 c TO Output of an 8 16 bit capture timer counter Foy Oscillation 261 CHAPTER 12 A D CONVERTER Clock selector The clock selector selects the clock to be used to activate A D conversion while continuous activation is enabled ADC2 EXT 1 Analog channel selector This circuit selects one out of the eight analog inputs Sample hold circuit This circuit holds the input voltage selected by the analog channel selector By performing the sample hold of the voltage input immediately after the activation of A D conversion A D conversion can be performed without the variance of the input voltage affecting it during A D conversion during comparison D A converter This generates the voltage that corresponds to the values set in the ADDH and ADDL registers Comparator This compares the input voltage for which sample hold is performed with the output voltage of the D A converter to determine which is the greater of the two Control circuit The control circuit has the following function For A D conversion functions this circuit determines the values in turn from the MSB in the 10 bit A D data register toward the LSB based on the large and small signals from the comparator When the conversion is completed it sets the interrupt request flag bit ADC1 ADI A D data register ADDH and ADDL The high order 2 bits of 10 bit A D data are stor
372. terrupt processing cannot be executed For the same reason other interrupt processing shall be disabled while the automatic algorithm is being activated m Flash Content Protection Flash content can be read using parallel serial programmer if the flash content protection mechanism is not activated One predefined area of the flash is assigned to be used for preventing the read access of flash content If the protection code 01g is written in this address FFFC y the flash content cannot be read by any parallel serial programmer Note The program written into the flash cannot be verified once the flash protection code is written Olg in FFFCp It is advised to write the flash protection code at last 373 CHAPTER 17 FLASH MEMORY 374 APPENDIX This appendix shows the I O map the overview of the instructions mask options in MB89202 F202RA series and the pin states APPENDIX A I O Map APPENDIX B Overview of the Instructions APPENDIX C Mask Options APPENDIX D Programming EPROM with Evaluation Chip APPENDIX E Pin State of the MB89202 F202RA Series 375 APPENDIX A I O Map APPENDIX A I O Map For the registers of peripheral functions incorporated the MB89202 F202RA series the addresses shown in Table A 1 are assigned m I O Map Table A 1 I O Map 1 4 Register Address abbreviation Register name Read write Initial value Port 0 data register XXXXXXXX Port 0 da
373. ters LRI to ILRA 36 Configuration of the Register Bank Pointer RP MR 31 Configuration of the Reset Flag Register RSFR EE 45 Configuration of the System Clock Control Register SY CO caida Ge i 56 Dedicated Register Configuration 27 Controlling Acceptance Bits for Controlling Acceptance of Interrupts 30 Counter Counter Function eeeeeeeeeeeeee 165 Counter Function Operation 189 Program Example of Counter Function 202 CPU Reads States of Pins after the CPU Reads the Mode Data T 50 D Data Setting Register Data Setting Register WRDR 351 DDR Registers of Port 91 Registers of Port 5 95 Registers PDRO DDRO and PULO of Port O 79 Registers PDR3 DDR3 and PUL3 of Port 3 85 Registers PDR6 DDR6 and PUL6 of Port 6 102 Registers PDR7 DDR7 and PUL7 of Port 7 108 Detailed Explanation Detailed Explanation of Flash Memory Write Erase EET 367 Diagram Diagram for State Transition in Standby Mode 68 DIP 32P M06 Package Dimension of DIP 32P M06 10 Pin Assignment of DIP 32P MO6 8 INDEX E EIC External Interrupt Control Register 1 EIC1 232 External I
374. that indicates the reset vector the instruction is then executed CHAPTER 3 CPU m Mode Fetch The CPU reads the mode data and reset vector from internal ROM following the cancellation of the reset Mode data address FFFDy Set single chip mode 00y to the mode data Reset vector address FFFEy highest FFFF lowest Specify the address at which execution is to be started after the reset operation is completed The CPU starts executing instructions from the specified address State of Reset Waiting for Stabilization of Oscillation The CPU performs a reset operation for a reset when power is turned on or an external reset in stop mode when the oscillation stabilization wait time specified with option settings has expired In this case if the external reset input is not cancelled the CPU performs the reset operation following cancellation of the external reset When an external clock is used oscillation stabilization wait time is applied and thus input of an external clock is required at a reset The time base timer generates oscillation stabilization wait time m influence from a Reset of Contents in RAM When reset conditions occur the CPU stops handling the current instruction then enters the reset state The contents in RAM does not change even after a reset However if a reset occurs while 16 bit data is being written the upper byte only is written the lower byte may be unwritten If a reset occur
375. that are used for analog inputs cannot be used as a general purpose I O port Table 4 4 1 lists the pins of port 4 Table 4 4 1 Pins of Port 4 P40 ANO Function Peripherals for which the pin may serve ANO analog input 0 Input and output form P41 ANI ANI analog input 1 P42 AN2 AN2 analog input 2 P43 AN3 ANG analog input 3 Input Output CMOS push pull N ch open drain For circuit type see Section 1 7 Pin Functions Description and 1 8 I O Circuit Types 90 Circuit type CHAPTER 4 I O PORTS m Block Diagram of Port 4 Figure 4 4 1 Block Diagram of Port 4 A D converter channel select A D converter enable bit To A D converter s analog input Stop mode SPL 1 PDR read PDR read when read modify write is performed Internal data bus Stop mode SPL 1 OUT write m Registers of Port 4 The registers PDR4 DDR4 and OUTA are associated with port 4 The bits of these registers correspond to the pins of port 4 in one to one correspondence Table 4 4 2 tabulates the correspondence between the pins and the bits of the port 4 registers Table 4 4 2 Correspondence between the Pins and the Bits of the Port 4 Register Bits of associated registers and corresponding pins PDR4 DDR4 OUT4 Pin corresponding to bit 91 CHAPTER 4 I O PORTS 4 4 1 Registers of Port 4 PDR4 This section describes the registers associ
376. the Flash Security Feature After writing the code Olg to the flash security address the subsequent external reset or power on enables the flash security feature m How to disable the Flash Security Feature Perform the chip erase operation m Behavior under the Flash Security Feature Read operation invalid data read Write operation ignored Others For the configuration of the standard parallel programmer please follow the specification of parallel programmer n order to prevent the device form enabling the flash security feature accidentally writing the protection code at the last of flash memory programming is recommended Note The security byte is allocated inside the flash memory After writing the code 01 to the flash security address the subsequent external reset or power on enables the flash security feature Therefore if the flash security feature is not required do not write 01g to the security byte address Once the flash security feature is enabled all the flash memory failure analysis cannot be performed 372 17 7 CHAPTER 17 FLASH MEMORY Notes on using Flash Memory This section provides notes on using the MB89F202 especially for flash memory m input of a Hardware Reset RST To input a hardware reset when reading is in progress i e when the automatic algorithm has not been started secure a minimum low level width of 1650 ns To input a hardware reset while a write or e
377. the comparator data latch the TIFO bit is set to 1 regardless of the TFCRO bit value In the 8 bit mode timer 0 and timer 1 operate independently and because they generate the same interrupt request IRQ3 determination of the interrupt request flag by software may be required 183 CHAPTER 8 8 16 BIT CAPTURE TIMER COUNTER Notes When the counter value matches the TDRO value and at the same time the counter stops TCRO TSTRO 0 the TIFO bit is not set If the TOIEN bit is set to 1 enable when the TIFO bit is 1 an interrupt request is generated immediately e Ifthe compare register value is 0000y or 00g the 8 16 bit capture timer counter cannot generate an interrupt Therefore when using interrupts set a value greater than or equal to 0001g or Oly The 8 16 bit capture timer counter also cannot generate an interrupt if the counter function detects the 0000 or 00g width m Register and Vector Table Related to 8 16 bit Capture Timer Counter of Interrupts Table 8 5 2 Register and Vector Table Related to 8 16 bit Capture Timer counter of Interrupts Interrupt level setting register Vector table address Interrupt name Register Setting bit Higher Lower Timer counter ILRI 007B function 007Bg L31 bit7 L30 bit6 Capture function ILR2 007Cy L41 bitl 140 bitO For interrupt operation see Section 3 4 2 Steps in the Interrupt Operation 184 CHAPTER 8 8 16 BIT CAPT
378. the following 17 chapters and appendix CHAPTER 1 OVERVIEW This chapter describes the features and basic specification of the MB89202 F202RA series CHAPTER 2 HANDLING DEVICES This chapter describes the precautions to be taken when handling the MB89202 F202RA series CHAPTER 3 CPU This chapter describes the functions and operation of the CPU CHAPTER 4 I O PORTS This chapter describes the functions and operation of the I O ports CHAPTER 5 TIME BASE TIMER This chapter describes the functions and operation of the time base timer CHAPTER 6 WATCHDOG TIMER This chapter describes the functions and operation of the watchdog timer CHAPTER 7 8 BIT PWM TIMER This chapter describes the functions and operation of the 8 bit PWM timer CHAPTER 8 8 16 BIT CAPTURE TIMER COUNTER This chapter describes the functions and operation of the 8 16 bit capture timer counter CHAPTER 9 12 BIT PPG TIMER This chapter describes the functions and operation of the 12 bit PPG timer CHAPTER 10 EXTERNAL INTERRUPT CIRCUIT 1 EDGE This chapter describes the functions and operation of external interrupt circuit 1 edge CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT 2 LEVEL This chapter describes the functions and operation of external interrupt circuit 2 level CHAPTER 12 A D CONVERTER This chapter describes the functions and operation of the A D converter CHAPTER 13 UART This chapter describes the functions and operation of UART CHAPTER 14 8 BIT SERIAL I O This ch
379. the number of stop bits is 1 in operating mode 0 1 or 3 Figure 13 6 4 Reception Operations in Operating Mode O 1 or 3 Reception interrupt 307 CHAPTER 13 UART Figure 13 6 5 Operations in Operating Mode 0 1 or 3 when the Overrun Error Occurs START 0 RDRF 1 reception buffer full ORFE Reception interrupt Figure 13 6 6 Operations in Operating Mode 0 1 or 3 when the Framing Error Occurs START 0 RDRF 0 ORFE Reception interrupt Note After initialization is cancelled due to a reset time for 11 shift clock cycles is required to initialize the internal controller Therefore be sure to enable the prescaler operation 1 using the oscillation frequency register after a reset 308 CHAPTER 13 UART 13 6 3 Reception Operations Operating Mode 2 Only When data is received at the serial data input pin the internal reception shift register converts it from serial to parallel If the data is correctly transmitted up to the stop bit s data in the internal shift register is transferred to the SIDR register then 1 is set to the RDRF bit m Reception Operations Operating Mode 2 Only If an overrun error or framing error occurs the received data is not transmitted to the SIDR register but the ORFE bit is set to 1 For both RDRF and ORFE data is fully received transmitted with the final data bit D8 set to 1 these flags go on when the stop bit at the end is d
380. the output pin CNTR OB is 1 the output level of the P50 PWM pin is inverted by the output control circuit at which time the 8 bit counter is cleared During the PWM timer operation once a match is detected the output level of the P50 PWM pin is changed from H level to L level by the PWM generation circuit Thereafter when the 8 bit counter overflows the output level is returned to H level register This register is used to set a value for comparison with the counter value of the 8 bit counter CNTR register This register is used to select the operation mode enable and disable operations set the count clock control interrupts and check status When the operation mode is the PWM timer mode P TX z 0 the 8 bit counter cannot be cleared by the match detection signal from the comparator and the interrupt request IRQ9 is disabled 140 CHAPTER 7 8 BIT PWM TIMER 7 3 Pin of 8 bit PWM Timer This section describes the pin and provides a block diagram of the pin related to the 8 bit PWM timer m Pin Related to the 8 bit PWM Timer The pin related to the 8 bit PWM timer is the P50 PWM pin P50 PWM pin This pin can be used as a general purpose I O port P50 and for output of the interval timer or PWM timer PWM PWM While the pin functions as the interval timer the square wave is output to the pin While the pin functions as the PWM timer the PWM wave is output to the pin When the bit
381. the program TIR bit TPE bit OE bit When the bit to control the output pin OE is O the pin functions as a general purpose I O port pin P50 If the PWM compare register value is changed during counter operation the value takes effect at the next cycle Notes While interval timer functions are enabled CNTR TPE 1 do not change the count clock cycle CNTR P1 PO When 00g is set to the COMR register the output of the PWM pin is inverted in the cycle of the count clock While interval timer functions are enabled the output level of the PWM pin in the counter stop state CNTR 0 is at L level 149 CHAPTER 7 8 BIT PWM TIMER 7 7 Operations of the 8 bit PWM Timer Functions This section describes the operations of the 8 bit PWM timer functions B Operations of the 8 bit PWM Timer Functions To enable 8 bit PWM timer functions set registers as shown in Figure 7 7 1 Figure 7 7 1 Setting 8 bit PWM Timer Functions bit7 bit6 bit5 bit4 bit3 bit2 bit1 bitO CNTR P TX P1 Po TPE TIR OE TIE 1 1 x 1 x COMR Set an H level pulse width compare value Used bit x Unused bit 1 Set 1 When the counter is activated the counter is incremented from 00g at the start up of the selected count clock The output PWM waveform of the PWM pin is H until a match between the counter value and the value set in the COMR register is found O
382. thm Execution State can be used to determine the state of the automatic algorithm in the flash memory Here the data polling flag DQ7 is used to confirm that writing has terminated The data read to check the flag is read from the address written to last The data polling flag DQ7 changes at the same time that the timing limit exceeded flag DQ5 changes For example even if the timing limit exceeded flag 005 is 1 the data polling flag bit DQ7 must be rechecked Also for the toggle bit flag DQ6 the toggle operation stops at the same time that the timing limit exceeded flag bit DQ5 changes to 1 The toggle bit flag DQ6 must therefore be rechecked 369 CHAPTER 17 FLASH MEMORY Figure 17 5 1 Example of the Flash Memory Write Procedure Make sure 10V DC voltage is applied at the RST pin before start writing FMCS WE bit5 Enable flash memory write Write command sequence 1 FAAA AA F554 55 FAAA lt AO Write address lt Write data Read internal address d Next address Data polling DQ7 Timing limit DQ5 Read internal address Data polling DQ7 Final address FMCS WE bit5 Write disable flash memory Confirm with the hardware Complete writing sequence flags 370 CHAPTER 17 FLASH MEMORY 17 5 3 Erasing All Data Erasing Chips This section describes the procedure for issuing the Chip Erase command to erase all data in th
383. timer control register TBTC Time base timer counter A 21 bit up counter that accepts the oscillation frequency divided by two as the count clock and stops operating when oscillation stops Counter clear circuit Clears the counter when the TBTC register is set TBR 0 stop mode is entered STBC STP 1 ora power on reset occurs Interval timer selector Selects 1 bit for the interval timer from four bits in the time base counter When the specified bit overflows an interrupt occurs Time base timer control register TBTC Selects a time interval clears the counter controls interrupts or checks the status 118 CHAPTER 5 TIME BASE TIMER 5 3 Time base Timer Control Register TBTC The time base timer control register TBTC selects a time interval clears the counter controls interrupts or checks the status Time base Timer Control Register TBTC Figure 5 3 1 Time base Timer Control Register TBTC Address 7 bit6 bit2 biti bitO Initial value oo0Au TBOF TBIE TBCI TBCO TBR 00 000 RAN RAN RAN R W R W Time base timer initialization bit The time base timer counter is cleared 1 is always read Nothing is changed and affected TBC1 TBCO Time interval selection bits o 213 i OO Oscillation frequency Interrupt request enable bit o The interrupt request output is disabled The interrupt req
384. tion register DDR3 bit4 it functions as the TO pin The TCR2 TSEL is used to select whether timer 0 output or timer output is to be used 168 CHAPTER 8 8 16 BIT CAPTURE TIMER COUNTER m Block Diagram for 8 16 bit Capture Timer Counter Pins e 2 e 5 0 t c x c Figure 8 3 1 Block Diagram for 8 16 bit Capture Timer Counter Pins PDR read At read modify write DDR write D PUL write Stop mode SPL 1 Note External interrup allowed AU P3A TO INT10 l P33 EC Stop mode SPL 1 Resource output Pull up resistor available P33 EC P34 TO INT10 When pull up resistor available is selected in the pull up setting register the pin state in the stop mode SPL 1 becomes high pull up state not Hi Z During the reset however pull up becomes ineffective and the pin state becomes Hi Z 169 CHAPTER 8 8 16 BIT CAPTURE TIMER COUNTER 8 4 Registers of 8 16 bit Capture Timer Counter This section shows registers of 8 16 bit capture timer counter m Registers of 8 16 bit Capture Timer Counter Figure 8 4 1 Registers of 8 16 bit Capture Timer Counter TCCR capture control register Address bit7 bite bit5 bit4 bit3 bit2 bit1 bito 0019H R RW RW RW RW RW RW RW TCR1 timer 1 control register Address bit7 bite bit5 bit4 bit3 bit2 biti bitO 001 TIF1 TFCR1 T1IEN TCS12 TCS11 TCS10 TSTR1 R RW RW RW RW RW RW TCRO timer 0 control register Add
385. tions of the Interval Timer Functions nennen 148 7 7 Operations of the 8 bit PWM Timer Functions sssssssssssseseeeeeeeene nennen 150 7 8 States in Each Mode During Operation sse nnne enne nnne 152 7 9 Notes on Using 8 bit PWM Timer sssssesssseeeeenennnneennneeennnnnnnnen 155 7 10 Program Example for PWM Timer 157 CHAPTERS8 8 16 CAPTURE TIMER COUNTER cernere 161 8 1 Overview of 8 16 bit Capture Timer Counter ssssssssssssseseeeeen nnne 162 8 2 Configuration of 8 16 bit Capture Timer Counter sse 166 8 3 Pins of 8 16 bit Capture Timer Counter sssssssssssesseseeneeene nennen eene nennen 168 8 4 Registers of 8 16 bit Capture Timer Counter 170 8 4 1 Capture Control Register TCCR eraranta a arinaa araea ranana En 171 8 4 2 Timer 0 Control Register TCRO sssssssssssseseeeeeneen nennen nnne enters nnns nnne 173 8 4 3 Timer 1 Control Register TCR1 ssssssssssssseseseeeee nennen nnne en rennen 175 8 4 4 Timer Output Control Register TCR2 sse enne 177 8 4 5 Timer 0 Data Register TDRO seenior a entree nennen nnn trn enne nennen nnns 178 8 4 6 Timer4 Data Registe IDRA id date eei
386. to function as an input port by the DDRO register the state of these pins can be read from the port 0 data register PDRO at any time PO4 INT24 to PO7 INT27 These external interrupt pins function as external interrupt input pins hysteresis input and also serving as the pins of the general purpose I O port The POA4 INT24 to PO7 INT27 pins function as external interrupt input pins INT24 to INT27 if set to function as an input port by the corresponding bits of the port O data direction register DDRO and if external interrupt inputs are enabled by the external interrupt 2 control register EIE2 When set to function as an input port the state of these pins can be read from the port 0 data register PDRO at any time Table 11 3 1 lists the pins associated with external interrupt circuit 2 Table 11 3 1 Pins Associated with External Interrupt Circuit 2 External Use for external interrupt input Use for general purpose I O port interrupt pin Interrupt input enabled Interrupt input disabled POO INT20 AN4 INT20 EIE2 IE20 1 DDRO bit0 0 ADEN ADE4 0 2 1 20 0 POL INT21 AN5 INT21 EIE2 1E21 1 DDRO bit1 0 ADEN ADE5 0 P01 2 1 21 0 PO2 INT22 AN6 INT22 EIE2 IE22 1 DDRO bit220 ADEN ADE6 0 P02 2 1 22 0 PO3 INT23 AN7 INT23 EIE2 1E23 1 DDRO bit3 0 ADEN ADE7 0 2 1 23 0 PO4 INT24 INT24 EIE2 IE24 1 DDRO bit4 0 P04 2 1 24 0 POS INT25 INT25 EIE2 IE25 1 D
387. to select an input clock enable and disable an interrupt and continuous activation B A D Control Register 2 ADC2 Figure 12 4 3 A D Control Register 2 ADC2 Address bit7 bit6 bits bit4 bits biti bito Initial value 0031n Resvafeesvs nocx note nesve ext RESvi 0000001 RAN RW RW RW RAN RW RW RESV1 Reserved bit Be sure to write 1 to this bit Bit for enabling continuous activation 0 Enables activation by setting the AD bit in the ADC1 register 1 Enables continuous activation through the clock selected in the ADCK bit RESV2 Reserved bit IR Be sure to write O to this bit ADIE Enabling an interrupt request bit 0 Disables the interrupt request output 1 Enables the interrupt request output Selecting an input clock bit ADCK Enabled only at continuous activation EXT 1 ET From the time base timer output 28 From the 8 16 bit capture timer counter output TO RESV3 RESV4 Reserved bits oe eet Be sure to write 00g to these bits R W Readable Writable Unused Initial value 268 CHAPTER 12 A D CONVERTER Table 12 4 2 Explanation of Functions of Each Bit in A D Control Register 2 ADC2 Bit name Function Unused bit The value during read is not determined Write does not affect operations RESVA RESV3 Reserved bits This bit is a reserved bit Be sure to write 00 to these bits ADCK Selecting an input clock bit This bit is
388. tput format of the pin is output set to N ch open drain type format setting Output format of the pin is register CMOS push pull type set to CMOS push pull type OUT4 R W Readable and Writable X Undefined 92 CHAPTER 4 I O PORTS 4 4 2 Operations of Port 4 Functions This section describes the operation of port 4 B Operation of Port 4 Operation in output port mode When 1 is written for a bit of the DDR4 register the bit corresponding to a pin of port 4 the pin functions as an output port In output port mode the output transistor operation is enabled and output latch data is output to the pin By setting the bit corresponding to the pin on the OUTA register N ch open drain or CMOS push pull type can be selected as the output format of the pin Once data has been written into the PDR4 register the written data is held in the output latch and output to the pin as it is The value state of the pin can be read by reading the PDR4 register Analog input mode setting Set a bit of the DDR4 register to 0 the bit corresponding to a pin of port 4 assigned for desired analog input so that its output transistor is set to OFF and the pin is set at Hi Z Its output latch value can be read by reading the PDR4 register Set the bit of the ADEN register of the A D converter to 1 the bit corresponding to the analog input pin in use Operation when a reset is performed When the CPU
389. trol interrupts and check interrupt states 8 bit serial I O interrupt IRQC If the interrupt request output is allowed SMR SIOE 1 when the I O function of the 8 bit serial I O inputs or outputs 8 bit serial data a interrupt request IRQC is generated CHAPTER 14 8 BIT SERIAL I O 14 3 Pins of 8 Bit Serial I O 8 bit serial I O pins include P32 UI SI P31 UO SO and P30 UCK SCK pins m Pins of 8 bit Serial I O P32 UI SI pin The P32 UI SI pin functions as the general purpose I O port P32 It also functions as the serial data input pin 51 of the 8 bit serial I O or as the serial data input pin UI of the UART When using the P32 SI pin as the SI pin set the P32 UI SI pin to input port with the port direction register DDR3 bit2 0 P31 UO SO pin The P31 UO SO pin functions as the general purpose I O port P31 It also functions as the serial data output pin SO function of the 8 bit serial I O or as the serial data output pin UO function of the UART When the serial data output is allowed SMR SOE 1 the P31 UO SO pin automatically becomes an output pin irrespective of the values in the port direction register bit of DDR3 and functions as the SO pin P30 UCK SCK pin The P30 UCK SCK pin functions as the general purpose I O port P30 It also functions as the shift clock I O pin SCK of the 8 bit serial I O or as the shift clock I O pin UCK of the UART When using the P30 UCK SCK pin a
390. tructions of the F MC 8L EUER 380 Read Destination at Execution of a Bit Manipulation Instruction n ttes 391 Special Instructions eeeseeeeeeeeeeee 387 Transfer Instructions eeeeeeeesesss 392 Instruction Cycle Instruction Cycle tjs 57 INDEX Internal Shift Clock When the Internal Shift Clock is Used 329 Interrupt 8 16 bit Capture Timer Counter of Interrupts Association between the Interrupt Enable Bits for External Interrupt Circuit 2 and the External Interrupt Pins eese 248 Bits for Controlling Acceptance of Interrupts 30 Block Diagram of Circuitry Terminating at the Pins Associated with External Interrupt Circuit 1 Block Diagram of Circuitry Terminating at the Pins Associated with External Interrupt Circuit 2 247 Block Diagram of External Interrupt Circuit 1 Lies ede agde edu aude vi de 227 Block Diagram of External Interrupt Circuit 2 245 Cancellation of Standby Mode by an Interrupt 70 Configuration of the Interrupt Level Setting Registers ILRI to 36 External Interrupt 2 Flag Register EIF2 252 External Interrupt Circuit 1 Programming Example TEES PA 241 External Interrupt Circuit 2 Control Register EIE2 TCI EC ERE 250 External Interrupt Control Register 1 EIC1 dece utet de chu 232 External Interrupt Co
391. tting bit of standby control register STBC SPL For MB89F202 F202RA PDR read PDR reag M when read modify write is performed Output latch PDR write DDR read PUL read PUL write a Stop mode SPL 1 SPL Pin state setting bit of standby control register STBC SPL 101 CHAPTER 4 I O PORTS m Registers PDR6 DDR6 and PUL6 of Port 6 Registers PDR6 DDR6 and PUL6 are associated with port 6 The bits of these registers correspond to the pins of port 6 in one to one correspondence Table 4 6 2 tabulates the correspondence between the pins and the bits of the port 6 registers Table 4 6 2 Correspondence between the Pins and the Bits of Port 6 Registers Bits of associated registers and corresponding pins PDR6 DDR6 PUL6 Pin corresponding to bit DDR control is not used for this bit in MB89F202 F202RA 102 CHAPTER 4 I O PORTS 4 6 1 Registers of Port 6 PDR6 DDR6 PUL6 This section describes the registers associated with port 6 m Functions of Port 6 Registers Port 6 data register The PDR6 register indicates the state of the output latch For a pin set to function as an output port the same value 0 or 1 as the value state of the output pin can be read from this register If the pin is set to function as an input port however its output latch value cannot be read from the register Note When a bit manipulation instruction SETB CLRB is e
392. tus can be determined from the RDY bit of the flash memory control status register FMCS that indicates whether writing has been completed After writing erasing has terminated the state returns to the read reset state When creating a program use one of the flags to confirm that automatic writing erasing has terminated Then perform the next processing operation such as data read In addition the hardware sequence flags can be used to confirm whether the second or subsequent sector erase code write is valid The following sections describe each hardware sequence flag separately Table 17 4 2 lists the functions of the hardware sequence flags Table 17 4 2 Hardware Sequence Flag Functions Executing Automatic writing operation Automatic erasing operation Exceeding Automatic writing operation the time limit Automatic erasing operation CHAPTER 17 FLASH MEMORY 17 4 4 Data Polling Flag DQ7 The data polling flag uses the data polling function to post that the automatic algorithm is being executed or has terminated m Write Read access during execution of the automatic write algorithm causes the flash memory to output the opposite data of bit7 last written regardless of the value at the address specified by the address signal Read access at the end of the automatic write algorithm causes the flash memory to output bit7 of the read value of the address specified by the address signal m Automatic Erasi
393. uest output is enabled Overflow interrupt request flag bit TED Read The specified bit has not overflowed This bit is cleared 1 The specified bit has overflowed Nothing is changed and affected R W Readable Writable Unused Initial value 119 CHAPTER 5 TIME BASE TIMER Table 5 3 1 Explanation of Functions of Each Bit in Time base Timer Control Register TBTC Bit name Description This bit is set to 1 when the specified bit of the time base timer counter overflows An interrupt request is sent when this bit and the interrupt request enable bit TBIE are both 1 While this bit is written it is cleared when 0 is specified and nothing is changed and affected when 1 is specified TBOF Overflow interrupt request flag bit This bit enables or disables an interrupt request to be output to the CPU An interrupt request is output when this bit and the overflow interrupt request flag bit TBOF are both 1 TBIE Interrupt request enable bit These bits are undefined when they are read Unused bits Nothing is affected when they are written These bits specify a time interval for the interval timer The interval timer bits of the time base timer counter are specified One of four time intervals can be selected TBCI TBCO Time interval selection bits This bit clears the time base timer counter TBR The counter is cleared to 000000 when 0 is written to this bit nothi
394. ure 3 7 1 Standby Control Register STBC Address bit7 bit6 bits bit3 bit2 biti bito Initial value 00084 STP SLP spt rst RESV 00010 RAN RW RW RW R RESV Reserved bit Le Always 0 Does not affect operations Software reset bit When written 4 instruction reset signal generated Pin state setting bit Pin states applied are maintained in stop mode Pin states are set to Hi Z in stop mode Transition to sleep mode STP Stop bit o Always 0 Does not affect operations Transition to stop mode R W Readable Writable p R Read only Unused EH Initial value 66 CHAPTER 3 CPU Table 3 7 2 Explanation of Functions of Each Bit in the Standby Control Register STBC Bit name Description STP Stop bit This bit specifies transition to stop mode Writing 1 into this bit allows transition to stop mode Writing 0 into this bit does not affect operations This bit is always read with the value of 0 SLP Sleep bit This bit specifies transition to sleep mode Writing 1 into this bit allows transition to sleep mode Writing 0 into this bit does not affect operations This bit is always read with the value of 0 SPL pin state setting bit This bit specifies external pin states in stop mode Writing into this bit maintains states levels of the external pins at transition to stop mode Wr
395. ure B 1 2 shows an example Figure B 1 2 Example of Extended Addressing MOVW A 123 4H 1234H 56u 1235 78 A 5678H 383 APPENDIX B Overview of the Instructions Bit Direct Addressing The addressing which is indicated by dir b in the instructions list is used for accessing the area from 0000g to OOFFy on a per bit basis In this addressing the higher one byte of the address is 00g Specify the lower one byte with the operand and the bit position in the specified address with the lower three bits of the operation code Figure B 1 3 shows an example Figure B 1 3 Example of Bit Direct Addressing SETB 34H 2 76543210 0034H KXXXX1X XB Index addressing The addressing which is indicated by IX off in the instructions list is used for accessing the entire area of 64 KB In this addressing the contents of the first operand are signed and added to IX index register Then the results are used as the address Figure B 1 4 shows an example Figure B 1 4 Example of Index Addressing MOVW A QS AH AH IX 2 7 A 5 T 27 1 2H 1234H np 12340 Pointer Addressing The addressing which is indicated by in the instructions list is used for accessing the entire area of 64 KB In this addressing the contents of EP extra pointer are used as the address Figure B 1 5 shows an example Figure B 1 5 Example of Pointer Addressing MOVW A 5 EP 2 7 Asu gt 2 7 5 Da
396. used in the 16 bit mode TCR1 is controlled by the timer 0 control register TCRO but TCR1 setting is required m Timer 1 Control Register TCR1 Figure 8 4 4 Timer 1 Control Register TCR1 Address bit7 bit6 bits bit4 bit3 bit2 bit bito Initial value 00 TIFt TFCRI TMEN TCST2 TCST TCS 0 TSTR 000 0000 R RW RW R W R W RW RW TSTR1 Timer start bit EN The counter operation is stopped The counter is cleared and increment is started ERE RORIS 2s 064 ps o 9 t o 9 ieu o esros 1 9 9 sos 3 msr 3 1 Si2insr 16384us tinst Instruction cycle Affected by the clock mode and others 0 interrupt request output is prohibited Interrupt request output is allowed TFCR1 Compare match detection flag clear bit Not affected at read always The compare match detection flag is cleared TIF1 Compare match detection flag bit 0 A compare match has not occurred R W Readable Writable A compare match has occurred R Read only Initial value 175 CHAPTER 8 8 16 BIT CAPTURE TIMER COUNTER Table 8 4 3 Explanation of Functions of Each Bit in Timer 1 Control Register TCR1 Bit name Function This bit is set to 1 when the counter value of timer 1 matches the value comparator data latch set in the timer data register TDR1 TIF1 e An interrupt request is output when this bit and the interrupt re
397. used to select an input clock for activation of A D conversion functions in the state where continuous activation is performed EXT 1 When this bit is 0 the internal clock with an oscillation frequency selected using the output of a time base timer divided by 28 is selected When 1 the output of an 8 16 bit capture timer counter TO 16 bit mode is selected ADIE Enabling an interrupt request bit This bit is used to enable and disable the output of an interrupt to the CPU When this bit and the interrupt request flag bit ADC1 are 1 an interrupt request is output RESV2 Reserved bit e This bit is a reserved bit e Be sure to write to this bit EXT Bit for enabling continuous activation This bit is used to select whether the A D conversion functions are to be activated with software or activated continuously in synchronization with an input clock When this bit is 0 software activation with the bit for activating A D conversion ADCI AD is enabled When 1 continuous activation on the rising edge of the clock selected using the bit for selecting an input clock ADC2 ADCK is enabled RESVI Reserved bit This bit is a reserved bit e Be sure to write 1 to this bit 269 CHAPTER 12 A D CONVERTER 12 4 8 A D Data Register and ADDL A D data register ADDH and ADDL stores the results of A D conversion at 10 bit A D conversion The high order 2 b
398. utput latch values other than those for bits to be manipulated do not change Port 0 data direction register DDRO The DDRO register sets the I O direction of each pin per bit When a bit of the DDRO register corresponding to a pin of port 0 is set to 1 the pin functions as an output port When the bit is set to O the pin functions as an input port Note Because the DDRO register is write only bit manipulation instructions SETB CLRB do not apply Setting a port pin to serve external interrupt inputs If a pin of port 0 is used as an external interrupt input pin enable the external interrupt circuit operation and set the pin to function as an input port When the pin is set in this mode its output latch value has no significance Setting a port pin to serve analog inputs If a pin of port O is used as an analog input pin write for the bit corresponding to the pin on the DDRO register The output transistor is then set to OFF and the pin is set in the Hi Z state Set the bit of the ADEN register of the A D converter to 1 the bit corresponding to the analog input pin in use Setting the input to a peripheral enable If a peripheral with an input pin is used set the pin of port O for the input to the peripheral to function as an input port In this mode the corresponding output latch value has no significance CHAPTER 4 I O PORTS Table 4 2 3 lists the functions of the port 0 registers Table
399. ween Counter Mode and Compare Latch Operation Data load to compare latch and counter clear provided not provided Counter mode At capture edge detection At compare match Clear mode Data load Provided Counter clear Provided Data load Provided Counter clear Provided Provided Not provided Provided Not provided Not provided Provided Not provided Provided Free run mode 194 Not provided Not provided Not provided Not provided Counter clear TDRO Compare latch Count value Capture latch Capture input EC TSTRO TIFO CPIF CHAPTER 8 8 16 BIT CAPTURE TIMER COUNTER Figure 8 8 2 Capture Mode Operation TFCRO 1 W TFCRO 1 W 1 W CFCLR 1 W CCMSK 1 CCMSK 1 TCMSK 1 TCMSK 0 195 CHAPTER 8 8 16 BIT CAPTURE TIMER COUNTER 196 16 bit mode To operate the capture function in the 16 bit mode the function must be set as shown in Figure 8 8 3 Figure 8 8 3 Setting of Capture Function in 16 bit Mode bit7 bit6 bit5 bit4 bit3 bit2 bit bito TCCR _CPIF LSetting of a value x other than 00 1 1 THEN Tes12 TCSt1 TCS10 TSTR1 x x x Setting of 111 0 TCSO0 L Setting of a value other than 111 x x Higher 8 bits of the number of detected events Lower 8 bits of the number of detected events
400. xecuted the output latch values not the value states of the pins are read thus output latch values other than those for bits to be manipulated do not change Port 6 data direction register DDR6 for P60 P61 The DDR6 register sets the I O direction of each pin per bit When a bit of the DDR6 corresponding to a pin of port 6 is set to 1 the pin functions as an output port When the bit is set to O the pin functions as an input port Table 4 6 3 lists the functions of the port 6 registers Table 4 6 3 Functions of Port 6 Registers Register When being name read When being written Address Initial value Output latch of 0 is set and L level is output to the pin in output port mode Pin state is L level Port 6 data register PDR6 Output latch of 1 is set and H level is output to the pin in output port mode Pin state is H level Output transistor operation Input port is disabled and the pin is set Port 6 data to serve as an input pin direction register DDR6 Output transistor operation Output port is enabled and the pin is set to serve as output pin R W Readable Writable X Undefined 103 CHAPTER 4 I O PORTS Port 6 pull up setting register PUL6 The bits of the pull up setting register correspond to the pins of port 6 in one to one correspondence When the pull up resistor is selected by using the pull up setting register the pin will be at H
401. y fire protection and prevention of over current levels and other abnormal operating conditions Exportation release of any products described in this document may require necessary procedures in accordance with the regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and or US export control laws The company names and brand names herein are the trademarks or registered trademarks of their respective owners Copyright 2005 2008 FUJITSU LIMITED All rights reserved READING THIS MANUAL B Example Notation of Register Names and Pin Names O Example notation of register names and bit names By writing 1 into the sleep bit of the standby control register T SLP Bit name T Register name E Bit abbreviation Register abbreviation Prohibit the output of interrupt request of the time base timer TBTC TBIE 0 Setting data Bit abbreviation Register abbreviation If interrupt enabled s specified the interrupt is accepted arene state Bit abbreviation Register abbreviation O Example notation of multi use pins P33 EC pin Some pins can switch functions according to a setting made by a program or other method These pins are called multi use pins For multi use pins the names corresponding to functions are listed and divided by CONTENTS CHAPTER 1 OVERVIEW ecc cone cux eec connu sd n Xa kx exea naue nS Sue xr DUE ry xu Ya eiaa naat 1 1 1 Features
402. y Cleared by switching to stop mode Oscillation stabilization overflow 000000 Interval cycle CPU TBTC TBC1 TBCO 1 1p Counter clear operation start 0 Power on reset optional Cleared by interrupt handling routine TBOF bit TBIE bit SLP bit STBC register Exit stop state by IRQ7 Stop lt gt STP bit STBC register Exit stop state by an external interrupt Note When the interval time selection bits of time base timer control register TBTC TBC1 TBCO are set to 11 222 Oscillation stabilization time 123 CHAPTER 5 TIME BASE TIMER 5 6 Notes on Using Time base Timer Notes on using the time base timer are shown below B Notes on Using Time base Timer Notes on using programs to set time base timer When the interrupt request flag bit TBTC is 1 and the interrupt request enable bit is enabled TBTC TBIE 1 a return from interrupt handling is not possible The TBOF bit must be cleared Clearing time base timer The time base timer is cleared when the time base timer initialization bit is set to 0 TBTC TBR 0 or when the oscillation stabilization time is required Because the time base timer is used as the count clock for the watchdog timer clearing the time base timer also clears the watchdog timer Using time base timer as oscillation stabilization time timer Oscillation has not yet started in stop mode or when the pow

Fujitsu F2MC-8L F202RA User's Manual

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