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Fujitsu CM71-00101-5E User's Manual

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1. Example LDUH R13 R2 R3 Instruction bit pattern 0000 0001 0010 0011 R2 0000 0004 R2 0000 0004 R3 XXXX KK KK R3 0000 4321 R13 1234 5678 R13 1234 5678 1234567C 4321 1234567C 4321 Before execution After execution 160 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 65 LDUH Load Half word Data in Memory to Register Extends with zeros the half word data at memory address R14 08 x 2 loads to Ri The value 08 is a signed calculation LDUH Load Half word Data in Memory to Register Assembler format LDUH R14 disp9 Ri Operation extu R14 08 x 2 Ri Flag change N Z V and C Unchanged Execution cycles b cycle s Instruction format MSB LSB 0 1 0 0 o8 Ri Example LDUH R14 2 R3 Instruction bit pattern 0100 0000 0001 0011 R3 xx xx X X X X R3 0000 4321 R14 1234 5678 R14 1234 5678 12345678 Memory b 12345678 Memory 1234567A 4321 1234567A 4321 Before execution After execution 161 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 66 LDUB Load Byte Data in Memory to Register Extends with zeros the byte data at memory address Rj loads to Ri LDUB Load Byte Data in Memory to Register Assembler format LDUB Ri Operation extu Rj Ri Flag change N Z V
2. 1 Low speed LI FR family CPU peripherals EN DMAC 0 1 Hg E Low speed 9 peripherals e mtem i R L Low speed _ L Data cache al peripherals H L 8151 5 1 ton es L RAM 7777 T EEEE FI missis a Highspeed _ 5 H P peripherals Internal bus interface H Macr M iLowspeed B i 27 19078180 bus F peripherals User bus interface General purpose port I I OO DIT Mandatory Standard in all models Option Not included in some models CHAPTER 1 FR FAMILY OVERVIEW 1 3 Sample Configuration of the FR Family CPU The FR family CPU core features a block configuration organized around general purpose registers with dedicated registers ALU units multipliers and other features included for each specific application Figure 1 3 1 shows a sample configuration of an FR family CPU Sample Configuration of the FR Family CPU Figure 1 3 1 Sample Configuration of the FR Family CPU R Instruction Exception Interrupt S __ Bypass Instruction 8 sequencer Pipeline interlock processing NMI data 8 control Wait bus 2 Wait cancel control control Data Y gt T T n i A Internal bus Internal bus
3. Example DIV4S Instruction bit pattern 1001 1111 0111 0000 R2 OOFF FFFF R2 OOFF FFFF MDH 0000 0000 MDH 0000 0000 MDL 0000 000F MDL FFFFFFF 1 D1DOT D1DOT SCR 110 SCR 110 NZVC NZVC CCR 0000 CCR 0000 Before execution After execution 137 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 44 LSL Logical Shift to the Left Direction Makes a logical left shift of the word data in Ri by Rj bits stores the result to Ri Only the lower 5 bits of Rj which designates the size of the shift are valid and the shift range is 0 to 31 bits Logical Shift to the Left Direction Assembler format LSL Rj Ri Operation Ri lt lt Rj Ri Flag change Set when the MSB of the operation result is 1 cleared when the MSB is 0 N Z Set when the operation result is 0 cleared otherwise V Unchanged C Holds the bit value shifted last Cleared when the shift amount is 0 Execution cycles 1 cycle Instruction format MSB LSB Example LSL R2 R3 Instruction bit pattern 1011 0110 0010 0011 R2 0000 0008 b R2 0000 0008 R3 R3 FFFFFF00 2 VC NZ VC CCR 0000 CCR 1001 Before execution After execution 138 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 45 LSL Logical Shift to the Left Direction Makes a logical
4. LD R10 R1 IF ID EX MA WB LD R11 R2 IF ID EX MA WB ADD R1 R3 IF ID EX MA WB BNE D TestOK branching conditions not satisfied IF ID EX MA WB ST R2 Q R12 delay slot instruction IF ID EX MA WB Notcanceled ADD 4 R12 IF ID EX MA WB 61 CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU Examples of Programing Delayed Branching Instructions An example of programing a delayed branching instruction is shown below LD R10 LD R11 R2 ADD R1 R3 BNE D TestOK ST R2 OG R12 ADD 4 R12 not satisfy TestOK satisfied ST R2 R13 62 CHAPTER 6 INSTRUCTION OVERVIEW This chapter presents an overview of the instructions used with the FR family CPU All FR family CPU instructions are in 16 bit fixed length format except for immediate data transfer instructions which may exceed 16 bits in length This format enables the creation of a compact object code and smoother pipeline processing 6 1 Instruction Formats 6 2 Instruction Notation Formats 63 CHAPTER 6 INSTRUCTION OVERVIEW 6 1 Instruction Formats The FR family CPU uses six types of instruction format TYPE A through TYPE F B Instruction Formats All instructions used by the FR family CPU are written in the six formats shown in Figure 6 1 1 Figure 6 1 1 Instruction Formats
5. 252 Multiplication Division Register Overview of the Multiplication Division Register Multiply Half word Data MULH Multiply Half word Data 124 Multiply Unsigned Half word Data MULUH Multiply Unsigned Half word Data EET RE hops 126 Multiply Unsigned Word Data MULU Multiply Unsigned Word Data 122 Multiply Word Data MUL Multiply Word Data 120 MULU MULU Multiply Unsigned Word Data 122 MULUH MULUH Multiply Unsigned Half word Data DUET 126 N NMI Relation of Step Trace Traps to NMI and External Inteitpls i oreet tete ep aie 47 No Operation NOP No Operation ss 237 Non delayed Branching Instructions Examples of Processing Non delayed Branching Instructions 60 Overview of Branching with Non delayed Branching Instructions i ettet 58 Non maskable Interrupt Conditions for Acceptance of Non maskable Interrupt R QUESTS m ES 40 Operation Following Acceptance of a Non maskable Intefr pt 5 uie tene tein 40 Time to Start of Non maskable Interrupt Processing 40 Non maskable Interrupts PC Values Saved for Non maskable Interrupts unix ku aasan atus 41 How to Use Non maskable Interrupts 41 Overview of Non maskable Interrupts 40 NOP NOP No Operation ss 237 Use of O
6. R13 FFFF FFFE R13 FFFF FFFE Memory Memory 52 X x 52 X X 53 X X 53 FE 54 54 Before execution After execution 222 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 112 DMOVB Move Byte Data from Direct Address to Post Increment Register Indirect Address Moves the byte data at the direct address indicated by the value dir8 to the address indicated by R13 After the data transfer it increments the value of R13 by 1 DMOVB Move Byte Data from Direct Address to Post Increment Register Indirect Address Assembler format DMOVB dir8 R13 Operation dir8 R13 R13 1 R13 Flag change N Z V and C Unchanged Execution cycles 2a cycles Instruction format MSB LSB 1 1 1 110 dir8 223 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example 224 DMOVB 71H R13 Instruction bit pattern 0000 1110 0111 0001 R13 8800 1234 Memory 00000071 9 9 88001234 88001235 Before execution R13 8800 1235 Memory 00000071 99 88001234 9 9 88001235 After execution CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 113 DMOVB Move Byte Data from Post Increment Register Indirect Address to Direct Address Transfers the byte data at the address indicated by R13 to the direct address indicated by the value dir8 After the data trans
7. MSB LSB 16bits 8bits 4bits 4bits TYPE A OP Rj Ri 4bits 8bits 4bits TYPE B OP i8 08 Ri 8bits Abits 4bits TYPE C OP u4 m4 i4 Ri 8bits 8bits TYPE D OP u8 rel8 dir rlist 12bits 4bits TYPE E OP Ri Rs 5bits L1 1 bits TYPE F OP 11 Relation between Bit Patterns Ri and Rj and Register Values Table 6 1 1 shows the relation between general purpose register numbers and field bit pattern values Table 6 1 1 General purpose Register Numbers and Field Bit Pattern Values Ri Rj Register Ri Rj Register Ri Rj Register Ri Rj Register 64 CHAPTER 6 INSTRUCTION OVERVIEW Relation between Bit Pattern Rs and Register Values Table 6 1 2 shows the relation between dedicated register numbers and field bit pattern values Table 6 1 2 Dedicated Register Numbers and Field Bit Pattern Values Register Register Register Register MDH reserved reserved MDL reserved reserved reserved reserved reserved reserved reserved reserved Note Bit patterns marked reserved are reserved for system use Proper operation is not assured if these patterns are used in programming 65 CHAPTER 6 INSTRUCTION OVERVIEW 6 2 Instruction Notation Formats FR family CPU instructions are written in the following three notation formats Calculations are designated by a mnemonic placed between operand 1 and operand
8. Example INTE Instruction bit pattern 1001 1111 0011 0000 R15 4000 0000 R15 7FFFFFF8 SSP 8000 0000 SSP 7FFF FFF8 USP 4000 0000 USP 4000 0000 TBR 000F FCOO TBR 000F FCOO PC 8088 8086 PC 6809 6800 PS FFF5 F8FO PS FFEAFB8DO ILM 10101 ILM 00100 SINZVC SINZVC CCR 110000 CCR 010000 Memory Memory 000FFFD8 6809 6800 000FFFD8 6809 6800 7FFFFFF8 X X X X X X X X 7FFFFFF8 8088 8088 7FFFFFFC X X X X X X X X 7FFFFFFC FFFF F8FO 80000000 X X X X X X X X 80000000 X X X X X X X X Before execution After execution 191 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 93 RETI Return from Interrupt Loads data from the stack indicated by R15 to the program counter PC and program status PS and retakes control from the interrupt handler This instruction requires the S flag in the register CCR to be executed in a state of 0 Do not manipulate the S flag in the normal interrupt handler use it in a state of 0 as it is This instruction has no delay slot At the time this instruction is executed if the value of the interrupt level mask register ILM is in the range 16 to 31 only new ILM settings between 16 and 31 can be entered If data in the range 0 to 15 is loaded in memory the value 16 will be added to that data before being transferred to the ILM If the original ILM value is in the range to 15 then any value between 0 and 31 can be transferred to the ILM Return from In
9. 110 ORCCR Or Condition Code Register and Immediate Indirect Address DMOV Move Word Data from Post Increment Register Indirect Address to Direct Address DMOVB Move Byte Data from Post Increment Register Indirect Address to Direct Address DMOVH Move Half word Data from Post Increment Register Indirect Address to Direct Address EEE TEE 219 Instruction INT Instruction Operation 45 INTE Instruction Operation 46 PC Values Saved for INT Instruction Execution P 45 282 PC Values Saved for INTE Instruction Execution 46 Values Saved for Undefined Instruction Exceptions 5 13 43 Examples of Processing Delayed Branching Instructions u ine 61 Examples of Processing Non delayed Branching Instructions 60 Examples of Programing Delayed Branching Instructions 62 General purpose Registers during Execution of COPST COPSV Instructions 48 How to Use Undefined Instruction Exceptions 43 Instruction Formats 64 Instruction Lists 265 Instruction Notation Formats 66 Instructions Prohibited in Delay Slots 58 Operations of Undefined Instruction Exception
10. a RENE 206 DMOVB Move Byte Data from Direct Address to Post Increment Register Indirect Address 223 DMOVB Move Byte Data from Direct Address to Resister 221 DMOVB Move Byte Data from Register to Direct Address 2 s e 222 DMOVH Move Half word Data from Direct Address to Post Increment Register Indirect Address Division 217 DMOVH Move Half word Data from Direct Address to Register iniiai 215 DMOVH Move Half word Data from Register to Direct Address 216 DIVOS Initial Setting Up for Signed Division as 128 DIVOU Initial Setting Up for Unsigned Division Du HP HA 130 DIV1 Main Process of Division 132 DIV2 Correction when Remainder is 0 134 DIV3 Correction when Remainder is 0 136 DIVAS Correction Answer for Signed Division E ETE EM 137 DIVOS Initial Setting Up for Signed Division wig daa SS maia u sama aude tante asa 128 DIVOU Initial Setting Up for Unsigned Division whats kaku ede eu qas du ve 130 DIV1 Main Process of Division 132 DMOV DMOV Move Word Data from Direct Address to Post Increment Register Indirect Address uywaykutaya sapu DR PPT sya 207 DMOV Move Word Data from Direct Address to Pre decrement Register Indirect Address
11. 157 LDUH Load Half word Data in Memory to Register 159 LDUH Load Half word Data in Memory to Register a 160 LDUH Load Half word Data in Memory to Register 161 LDUB Load Byte Data in Memory to 162 LDUB Load Byte Data in Memory to 163 LDUB Load Byte Data in Memory to Register u 164 ST Store Word Data in Register to Memory n a 165 ST Store Word Data in Register to Memory n 166 ST Store Word Data in Register to Memory n 167 ST Store Word Data in Register to Memory I a 168 ST Store Word Data in Register to Memory a 169 ST Store Word Data in Register to Memory a 170 ST Store Word Data in Program Status Register to 171 STH Store Half word Data in Register to Memory sse 172 STH Store Half word Data in Register to Memory nennen 173 STH Store Half word Data in Register to Memory sse 174 STB Store Byte Data in Register to Memory n a 175 STB Store Byte Data in Register to Memory n a 176 STB Sto
12. 48 Initial Value of General purpose Registers 16 INDEX Interlocking Produced by Reference to R15 and General purpose Registers after Changing the Flag eere reir aa aya aaa 57 Overview of General purpose Registers 15 Special Uses of General purpose Registers 15 H Hazards Overview of Register Hazards 56 ILM Interrupt Level Mask Register ILM Bit 20 to bit 16 TIE 19 Immediate Data ADD Add 4 bit Immediate Data to Destination PIERDEN 73 ADD2 Add 4 bit Immediate Data to Destination Register gaa asna nh dents 74 ADDN Add Immediate Data to Destination Register ADDN2 Add Immediate Data to Destination 78 ADDSP Add Stack Pointer and Immediate Data 241 ANDCCR And Condition Code Register and Immediate Data 238 BANDH And 4 bit Immediate Data to Higher 4 Bits of Byte Data in Memory 108 BANDL And 4 bit Immediate Data to Lower 4 Bits of Byte Data in Memory 106 BEORH Eor 4 bit Immediate Data to Higher 4 Bits of Byte Data in Memory 116 BEORL Eor 4 bit Immediate Data to Lower 4 Bits of Byte Data in Memory 114 BORH Or 4 bit Immediate Data to Higher 4 Bits of Byte Data in Memory 112 BORL Or 4 bit Immediate Data to Lower 4 Bits of Byte Data in Memory
13. Memory 7FFFFFCO X X X X X X X X 7FFFFFC4 X X X X X X X X 7FFFFFC8 X X X X X X X X 7FFFFFCC x x X X X X X X Before execution R10 R11 R12 R15 7FFFFFC0 7FFFFFC4 7FFFFFC8 7FFFFFCC 8FE39E8A 90BC9363 8DF788E4 7FFFFFCO Memory 8FE39E8A 90BC9363 8DF788E4 X X X X X X X X After execution 253 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 133 ENTER Enter Function This instruction is used for stack frame generation processing for high level languages The value u8 is calculated as an unsigned value ENTER Enter Function Assembler format ENTER u10 Operation R14 R15 4 R15 4 gt R14 R15 extu u8 x 4 R15 Flag change N Z V and C Unchanged Execution cycles 1 a cycles Instruction format MSB LSB 254 Example CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS ENTER 0CH Instruction bit pattern 0000 1111 0000 0011 R14 8000 0000 R14 R15 FFF8 R15 Memory 7FFFFFEC X X X X X X X X 7FFFFFEC 7FFFFFFO X X X X X X X X 7FFFFFFO 7FFFFFF4 X X X X X X X X 7FFFFFF4 7FFFFFF8 X XXX X X X X 7FFFFFF8 7FFFFFFC X X X X X X X X 7FFFFFFC 80000000 X XXX X X X X 80000000 Before execution 7FFFFFF4 7FFFFFEC Memory XXX X XX X X X XXX XX X X 8000 0
14. Example EXTUH 1 Instruction bit pattern 1001 0111 1011 0001 R1 FFFFFFFF R1 0000 FFFF Before execution After execution 245 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 129 LDMO Load Multiple Registers The LDMO instruction accepts registers in the range RO to R7 as members of the parameter reglist See Table 7 129 1 Registers are processed in ascending numerical order LDMO Load Multiple Registers Assembler format LDMO reglist Operation The following operations are repeated according to the number of registers specified in the parameter reglist R15 gt Ri R15 4 R15 Flag change N Z V and C Unchanged Execution cycles If n is the number of registers specified in the parameter reglist the execution cycles are as follows If n 0 1 cycle For other values of n a n 1 b 1 cycles Instruction format MSB LSB 1 1 0 1 1 010 reglist Table 7 129 1 Bit Values and Register Numbers for reglist 246 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example LDM0 R3 R4 Instruction bit pattern 1000 1100 0001 1000 R3 XXXX X XXX R3 90BC 9363 R4 XXXX R4 8343 834A R15 7FFF FFCO R15 7FFF FFC8 Memory Memory 7FFFFFCO 90BC9363 7FFFFFCO 90BC9363 7FFFFF
15. caveats 37 STH STH Store Half word Data in Register to Memory 172 173 174 STILM STILM Set Immediate Data to Interrupt Level Mask Register ect eheu 240 STM 5 Store Multiple Registers 250 STM Store Multiple Registers 252 Store COPST Store 32 bit Data from Coprocessor Register to Registe 233 Store Byte Data STB Store Byte Data in Register to Memory TEES 175 176 177 Store Half word Data STH Store Half word Data in Register to Memory 172 173 174 Store Multiple Registers STMO Store Multiple Registers 250 STM Store Multiple Registers 252 Store Word Data ST Store Word Data in Program Status Register to 171 ST Store Word Data in Register to Memory 165 166 167 168 169 170 STRES Store Word Data in Resource to Memory STRES STRES Store Word Data in Resource to Memory SUB SUB Subtract Word Data in Source Register from Destination Register 79 SUBC SUBC Subtract Word Data in Source Register and Carry Bit from Destination Register 80 SUBN SUBN Subtract Word Data in Source Register from Destination Register 81 Subroutine CALL Call Subroutine 185 186 CALL D Call
16. 0000 OOFF NZVC 0001 After execution 143 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 50 ASR Arithmetic Shift to the Right Direction Makes an arithmetic right shift of the word data in Ri by Rj bits stores the result to Ri Only the lower 5 bits of Rj which designates the size of the shift are valid and the shift range is 0 to 31 bits ASR Arithmetic Shift to the Right Direction Assembler format ASR Rj Ri Operation Ri gt gt Rj Ri Flag change Set when the MSB of the operation result is 1 cleared when the MSB is 0 N Z Set when the operation result is 0 cleared otherwise V Unchanged C Holds the bit value shifted last Cleared when the shift amount is 0 Execution cycles 1 cycle Instruction format MSB LSB 1 0 11111 1 01 110 Rj Ri Example ASR R2 R3 Instruction bit pattern 1011 1010 0010 0011 R2 0000 0008 b R2 0000 0008 R3 FFOFFFFF R3 FFFFOFFF NZVC NZVC CCR 0000 CCR 100 1 Before execution After execution 144 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 51 ASR Arithmetic Shift to the Right Direction Makes an arithmetic right shift of the word data in Ri by u4 bits stores the result to Ri ASR Arithmetic Shift to the Right Direction Assembler format ASR 04 Ri Operation Ri gt gt u4 gt Ri Flag
17. Register Bypass Pig adder inc a Internal bus Data address Y Y l 1 1 gt Instruction lt gt address CHAPTER 2 MEMORY ARCHITECTURE This chapter describes memory space in the FR family CPU Memory architecture includes the allocation of memory space as well as methods used to access memory 2 1 FR Family Memory Space 2 2 Bit Order and Byte Order 2 3 Word Alignment CHAPTER 2 MEMORY ARCHITECTURE 2 1 FR Family Memory Space The FR family controls memory space in byte units and provides linear designation of 32 bit spaces Also to enhance instruction efficiency specific areas of memory are allocated for use as direct address areas and vector table areas Memory Space Figure 2 1 1 illustrates memory space in the FR family For a detailed description of the direct address area see Section 2 1 1 Direct Address Area and for the vector table area see Section 2 1 2 Vector Table Area Figure 2 1 1 FR Family Memory Space Direct address area General addressing 0000 0000 Byte data 0000 0100H 0000 0200H Half word data Word data 0000 04004 000F FCOOH TBR Vector table eee initial area 1 TBR initial value FFFF FFFFH 212 Unused Vector Table Area Unused vector table area is available for use as program or data area CHAPTER 2 MEMORY ARCHITECTURE 2 1 1 Direct Address Area
18. 229 Coprocessor PC Values Saved for Coprocessor Error Traps umm 49 PC Values Saved for Coprocessor Not Present Traps tunt DETENTE PEER 48 Conditions for Generation of Coprocessor Error Traps eerie ed Donde a TT aya aca sansa assasi PUER da 49 Conditions for Generation of Coprocessor Not Found 48 COPLD Load 32 bit Data from Register to Coprocessor Register 231 COPOP Coprocessor Operation 229 Coprocessor Error Trap Operation 49 Coprocessor Not Found Trap Operation 48 COPST Store 32 bit Data from Coprocessor Register to Register 233 Save 32 bit Data from Coprocessor Register to Register eee 235 Overview of Coprocessor Error Traps 49 Overview of Coprocessor Not Found 48 Results of Coprocessor Operations after a Coprocessor Error hanaq ata 49 Saving and Restoring Coprocessor Error Information 50 5 COPST Store 32 bit Data from Coprocessor Register to Register 233 General purpose Registers during Execution of COPST COPSV Instructions 48 COPSV COPSV Save 32 bit Data from Coprocessor Register to Register 235 General purpose Registers during Execution of COPST COPSV Instructions 48 CPU Features of
19. MSB LSB 110101110111 of of 1 Ri Example CALL R1 Instruction bit pattern 1001 0111 0001 0001 R1 FFFF F800 R1 FFFF F800 PC 8000 FFFE PC FFFF F800 RP X X X X X X X X RP 8001 0000 Before execution After execution 186 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 90 Return from Subroutine This is a branching instruction with no delay slot Branches to the address indicated by the return pointer RP RET Return from Subroutine Assembler format RET Operation RP 5 PC Flag change N Z V and C Unchanged Execution cycles 2 cycles Instruction format MSB LSB Example RET Instruction bit pattern 1001 0111 0010 0000 PC FFFO 8820 PC 8000 86 RP 8000 86 RP 8000 86 Before execution After execution 187 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 91 INT Software Interrupt Stores the values of the program counter PC and program status PS to the stack indicated by the system stack pointer SSP for interrupt processing Writes 0 to the S flag in the condition code register CCR and uses the SSP as the stack pointer for the following steps Writes 0 to the I flag interrupt enable flag in the CCR to disable external interrupts Reads the vector table for the interrupt vector number u8 to determine the branch destination addre
20. D TO LEO Et 144 145 ASR2 Arithmetic Shift to the Right Direction 146 B BANDH BANDH And 4 bit Immediate Data to Higher 4 Bits of Byte Data in Memory 108 BANDL BANDL And 4 bit Immediate Data to Lower 4 Bits of Byte Data in Memory 106 Bcc Bcc Branch Relative if Condition Satisfied 194 Bcc D Branch Relative if Condition Satisfied 203 BEORH Eor 4 bit Immediate Data to Higher 4 Bits of Byte Data in Memory 116 BEORL BEORL Eor 4 bit Immediate Data to Lower 4 Bits of Byte Data in 114 Bit Order Bit Order and Byte Order 10 Bit Pattern Relation between Bit Pattern Rs and Register Values 65 Bit Patterns Relation between Bit Patterns Ri and Rj and Register Values 64 BORH BORH Or 4 bit Immediate Data to Higher 4 Bits of Byte Data in Memory 112 BORL BORL Or 4 bit Immediate Data to Lower 4 Bits of Byte Data in Memory 110 Branch Relative Bcc Branch Relative if Condition Satisfied 194 Bcc D Branch Relative if Condition Satisfied Loose uu asa Q 203 BTSTH BTSTH Test Higher 4 Bits of Byte Data in Memory na 119 BTSTL BTSTL Test Lower 4 Bits of Byte Data in Mem
21. DMOV Move Word Data from Register to Direct Address Assembler format DMOV R13 dir10 Operation R13 gt dir8 x 4 Flag change N Z V and C Unchanged Execution cycles a cycle s Instruction format MSB LSB 010101111101010 dir8 1 1 1 1 1 1 1 Example DMOV R13 54H Instruction bit pattern 0001 1000 0001 0101 R13 89AB CDEF R13 89AB CDEF Memory Memory 50H XXXX 50 54 XXXX 54 89AB CDEF 58 XXXX XXXX 58 XXXX XXXX Before execution After execution 206 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 102 DMOV Move Word Data from Direct Address to Post Increment Register Indirect Address Transfers the word data at the direct address corresponding to 4 times the value of dir8 to the address indicated in R13 After the data transfer it increments the value of R13 by 4 DMOV Move Word Data from Direct Address to Post Increment Register Indirect Address Assembler format dir10 R13 Operation dir8 x 4 R13 R13 4 5 R13 Flag change N Z V and C Unchanged Execution cycles 2a cycles Instruction format MSB LSB 1 11010 dir8 207 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example 208 DMOV 88H R13 Instruction bit pattern 0000 1100 0010 0010 R13 000000
22. m Example 2 Half word data DMOVH R13 58H Right 1 bit shift Memory space Object code 192CH Left 1 bit shift 58H 7 R13 12345678 0000 0058 5678 Example 3 Word data DMOV R13 58H eon 2 bit shift Memory space Object code 1816H Left 2 bit shift 58H ul RH13 12345678 0000 0058H 1345678 CHAPTER 2 MEMORY ARCHITECTURE 2 1 2 Vector Table Area An area of 1 Kbyte beginning with the address shown in the table base register TBR is used to store EIT vector addresses Overview of Vector Table Areas An area of 1 Kbyte beginning with the address shown in the table base register TBR is used to store EIT vector addresses Data written to this area includes entry addresses for exception processing interrupt processing and trap processing The table base register TBR can be rewritten to allocate this area to any desired location within word alignment limitations Figure 2 1 3 Relation between Table Base Register TBR and Vector Table Addresses Offset Memory space from TBR EIT source 0000 00000 Entry address for INT instruction Entry address for INT instruction Entry address for INT instruction Entry address for INT instruction FFFF FFFFH 1 Entry address for reset processing CHAPTER 2 MEMORY ARCHITECTURE Contents of Vect
23. Coprocessor register Coprocessor register CR3 0000000 9 CR3 C000 0000 1x 2 CR4 4080 0000 CR4 40C00000 2x29 3x 2 Before execution After execution 230 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 117 COPLD Load 32 bit Data from Register to Coprocessor Register Transfers the 16 bit data consisting of parameters CC Rj CRi to the coprocessor indicated by channel number u4 then on the next cycle transfers the contents of CPU general purpose register Rj to that coprocessor Basically this operation transfers data to a register within the coprocessor The 32 bit data stored in CPU general purpose register Rj is transferred to coprocessor register Note that the actual interpretation of the fields CC Rj CRi is done by the coprocessor so that the detailed actual operation is determined by the specifications of the coprocessor If the coprocessor designated by the value u4 is not mounted a coprocessor not found trap is generated If the coprocessor designated by the value u4 has generated an error in a previous operation a coprocessor error trap is generated COPLD Load 32 bit Data from Register to Coprocessor Register Assembler format COPLD 04 CC Rj Operation CC Rj CRi Coprocessor on channel u4 Rj CRi Flag change N Z V and C Unchanged Execution cycles 1 2 cycles Instruction format MSB LSB
24. 194 D JUMP EMI 196 GALE D Call Subroutine a Ee prin Dee ete tis 197 CALLED Call Subroutine sr o ete ym butt ene Me ate de 2 199 RET D Return from Subroutine iii 201 Bcc D Branch Relative if Condition Satisfied 203 DMOV Move Word Data from Direct Address to Register 205 Move Word Data from Register to Direct Address 206 DMOV Move Word Data from Direct Address to Post Increment Register Indirect Address Le A EN mallata Annee 207 DMOV Move Word Data from Post Increment Register Indirect Address to Direct Address M 209 DMOV Move Word Data from Direct Address to Pre decrement Register Indirect Address D an ve ed note ctn ap 211 DMOV Move Word Data from Post Increment Register Indirect Address to Direct Address EE 213 DMOVH Move Half word Data from Direct Address to Register 215 DMOVH Move Half word Data from Register to Direct Address 216 DMOVH Move Half word Data from Direct Address to Post Increment Register Indirect Address EE te I 21
25. 32 DIV1s are arranged DIVI R2 DIV2 R2 DIV3 DIV4S R2 0123 4567 R2 0123 4567 x xxx xxx x MDH FFFFFFFF MDL FEDC 98 MDL FFFFFFFF D1 DOT D1 DOT SCR x x0 SCR 110 Before execution After execution 129 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 739 DIVOU Initial Setting Up for Unsigned Division This command is used for unsigned division in which the multiplication division register MDL contains the dividend and the Ri the divisor with the quotient stored in the MDL register and the remainder in the multiplication division register MDH The MDH and bits 01 and DO are cleared to 0 To execute unsigned division the instructions are used in combinations such as DIVOU and DIV1 x 32 DIVOU Initial Setting Up for Unsigned Division Assembler format DIVOU Ri Operation 0 00 0 01 0 Flag change N Z V and C Unchanged Execution cycles 1 cycle Instruction format 130 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example DIV0U R2 Instruction bit pattern 1001 0111 0101 0010 R2 OOFF FFFF R2 OOFF FFFF MDH 0000 0000 MDH 0000 0000 MDL OFFFFFFO MDL OF FF FFFO D1 DOT D1 DOT SCR x x0 SCR 000 Before execution After execution Example Actual use MDL R2 MDL quotient MDH remainder unsigned calculation DIVOU R2
26. 7 76 STH Store Half word Data in Register to Memory is changed Instruction bit pattern 0001 0101 0010 0011 is added 7 77 STH Store Half word Data in Register to Memory is changed Instruction bit pattern 0001 0001 0010 0011 is added 7 79 STB Store Byte Data in Register to Memory is changed Instruction bit pattern 0001 0110 0010 0011 is added 7 80 STB Store Byte Data in Register to Memory is changed Instruction bit pattern 0001 0010 0010 0011 is added 7 82 MOV Move Word Data in Source Register to Destination Register is changed Instruction bit pattern 1000 1011 0010 0011 is added 7 83 MOV Move Word Data in Source Register to Destination Register is changed Instruction bit pattern 1011 0111 0101 0011 is added 7 84 MOV Move Word Data in Program Status Register to Destination Register is changed Instruction bit pattern 0001 0111 0001 0011 is added 7 85 MOV Move Word Data in Source Register to Destination Register is changed Instruction bit pattern 1011 0011 0101 0011 is added 7 86 MOV Move Word Data in Source Register to Program Status Register is changed Instruction bit pattern 0000 0111 0001 0011 is added 7 87 JMP Jump is changed Instruction bit pattern 1001 0111 0000 0001 is added XV Page Changes For details refer to main body 7 88 CALL Call Subroutine
27. Ri amp u4 lt lt 4 xix Page Changes For details refer to main body Table A 2 6 Shift Instructions 9 Instructions is changed lt lt u4 16 Ri lt lt u4 16 Ri gt gt 04 16 gt Ri gt gt u4 16 Ri gt gt 04 16 gt Ri Ri gt gt 04 16 Ri Table A 2 13 Direct Addressing Instructions 14 Instructions is changed disp8 dir8 disp9 dir9 disp10 gt dirl0 Table A 2 16 Other Instructions 16 Instructions is changed 18 u8 Table B 2 1 E Format is changed Undefined is added XX CHAPTER 1 FR FAMILY OVERVIEW This chapter describes the features of the FR FAMILY CPU core and provides sample configurations 1 1 Features of the FR Family CPU Core 1 2 Sample Configuration of an FR Family Device 1 3 Sample Configuration of the FR Family CPU CHAPTER 1 FR FAMILY OVERVIEW 1 1 Features of the FR Family CPU Core The FR family CPU core features proprietary Fujitsu architecture and is designed for controller applications using 32 bit RISC based computing The architecture is optimized for use in microcontroller CPU cores for built in control applications where high speed control is required Features of the FR Family CPU Core General purpose register architecture Linear space for 32 bit 4 Gbytes addressing 16 bit fixed instruction length excluding
28. SINZVC SINZVC CCR 000101 CCR 010101 Before execution After execution 239 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 123 STILM Set Immediate Data to Interrupt Level Mask Register Transfers the immediate data to the interrupt level mask register ILM in the program status PS Only the lower 5 bits bit4 to bit0 of the immediate data are valid At the time this instruction is executed if the value of the interrupt level mask register ILM is in the range 16 to 31 only new ILM settings between 16 and 31 can be entered If the value is in the range 0 to 15 the value 16 will be added to that data before being transferred to the ILM If the original ILM value is in the range 0 to 15 then any value between 0 and 31 can be transferred to the ILM STILM Set Immediate Data to Interrupt Level Mask Register Assembler format STILM u8 Operation u8 ILM Flag change N Z V and C Unchanged Execution cycles 1 cycle Instruction format MSB LSB Example STILM 14H Instruction bit pattern 1000 0111 0001 0100 ILM 11111 ILM 10100 Before execution After execution 240 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 124 ADDSP Add Stack Pointer and Immediate Data Adds 4 times the immediate data as a signed extended value to the value in R15 ADDSP Add Stack Pointer and Immediate Data Assem
29. 284 DMOVH Move Half word Data from Direct Address to Register 215 DMOVH Move Half word Data from Post Increment Register Indirect Address to Direct Address EE 219 DMOVH Move Half word Data from Register to Direct Address 216 Move Word Data DMOV Move Word Data from Direct Address to Post Increment Register Indirect Address IEEE 207 DMOV Move Word Data from Direct Address to Pre decrement Register Indirect Address 211 DMOV Move Word Data from Direct Address to 2422 i 205 DMOV Move Word Data from Post Increment Register Indirect Address to Direct Address 209 213 DMOV Move Word Data from Register to Direct Address 206 MOV Move Word Data in Program Status Register to Destination Register 180 MOV Move Word Data in Source Register to Destination Register 178 179 181 MOV Move Word Data in Source Register to Program Status Register 182 MUL MUL Multiply Word Data 120 MULH MULH Multiply Half word Data 124 Multiple Processes Priority of Multiple Processes 52 Multiple Registers LDMO Load Multiple Registers 246 LDMI Load Multiple Registers 248 STMO Store Multiple Registers 250 STMI Store Multiple
30. ADD SP instruction Sign extension 8 32bit Zero extension 8 32bit Sign extension 16 32bit Zero extension 16 32bit m m m g J R15 gt reglist increment R15 R15 gt reglist increment R15 Load multiple RO to R7 Load multiple R8 to R15 Decrement R15 reglist R15 Decrement R15 reglist R15 Store multiple RO to R7 Store multiple R8 to R15 RI4 R15 4 R15 4 RIA R15 ul0 R15 Function entry processing R14 4 gt R15 R15 4 gt R14 Function exit processing Rj Ri Ri gt TEMP Rj Ri Byte data for semaphore processing TEMP gt Rj Notes n the ADD SP instruction the field s8 in the TYPE D instruction format has the following relation to the value s10 in assembly notation S10 2 s8 s10 gt gt 2 In the ENTER instruction the field u8 in the TYPE D instruction format has the following relation to the value u10 in assembly notation u10 2 u8 u10 gt gt 2 The number of execution cycles for the LDMO reglist LDM1 reglist instructions is a x n 1 b 1 cycles where n is the number of registers designated The number of execution cycles for the STMO reglist and STM1 reglist instructions is a x n 1 cycles where n is the number of registers designated 273 APPENDIX B Instruction Maps APPENDIX B Instruction Maps This appendi
31. STBR13 8R1 4321567 in 1 R13 R2 4321567 FN 89ABCDEFH BE 1 0 0 L_ 4321 56784 EFH Bit 0 0 4321567CH I gt 4321 567AH CDEFH lt 4321 567CH 89ABH 4321 567EH CDEFH FFFF FFFFH L T CHAPTER 2 MEMORY ARCHITECTURE CHAPTER 3 REGISTER DESCRIPTIONS This chapter describes the registers used in the FR family CPU 3 1 FR Family Register Configuration 3 2 General purpose Registers 3 3 Dedicated Registers CHAPTER 3 REGISTER DESCRIPTIONS 3 1 FR Family Register Configuration FR family devices use two types of registers general purpose registers and dedicated registers General purpose registers Store computation data and address information Dedicated registers Store information for specific applications Figure 3 1 1 shows the configuration of registers in FR family devices FR Family Register Configuration Figure 3 1 1 FR Family Register Configuration Initial value 32 bits RO Undefined General purpose registers R1 Undefined R2 Undefined R3 Undefined R12 Undefined R13 Undefined R14 Undefined PC Reset entry address Dedicated registers ILM 011118 PS SCR XX0B CCR XX00XXXXB SSP 00000000H USP 11 Undefined 64 bits CHAPTER 3 REGISTER DESCRIPTIONS 3 2 General purpose Registers The FR family CPU uses general purpose registers to hold the results of various calculations as well as information
32. Symbols in Mnemonic and Operation Columns is changed 0x80000000g to 00000000 to FFFFFFFFg A 1 Symbols Used in Instruction Lists is chenged Symbols in Mnemonic and Operation Columns is changed Note Data from 0x80000000g to 1 is handled as data from 0 80000000 to OXFFFFFFFFy is deleted A 1 Symbols Used in Instruction Lists is changed Symbols in Mnemonic and Operation Columns is changed Ri gt e Ri Rj Symbols in Operation Column is changed indicates indirect addressing which values reading or loading from to the memory address where the registers within or the formula indicate indicates the calculation priority is used for specifying indiiirect address is added Cycle CYC Column is changed special dedicated Table A 2 4 Bit Operation Instructions 8 Instructions is changed Rp amp FOH u4 gt Ri amp FOH u4 Table A 2 4 Bit Operation Instructions 8 Instructions is changed Rip amp u4 lt lt 4 FH RI amp u4 lt lt 4 FH Table A 2 4 Bit Operation Instructions 8 Instructions is changed RD u4 lt lt 4 Ri ud 4 Table A 2 4 Bit Operation Instructions 8 Instructions is changed Ri 04 lt lt 4 Ri u4 lt lt 4 Table A 2 4 Bit Operation Instructions 8 Instructions is changed Rp amp 04 lt lt 4
33. 4 x u is stored in PC Time to Start of Trap Processing for INT Instructions The time required to start trap processing is 6 cycles B PC Values Saved for INT Instruction Execution The PC value saved to the system stack represents the address of the next instruction after the INT instruction Precautionary Information for Use of INT Instructions The INT instruction should not be used within an INTE instruction handler or step trace trap handler routine This will prevent normal operation from resuming after the RETI instruction 45 CHAPTER 4 RESET AND EIT PROCESSING 4 5 2 INTE Instruction The INTE instruction is used to create a software trap for debugging This section describes the operation time requirements program counter PC values saved and other information of the INTE instruction Overview of the INTE Instruction The INTE instruction is used to create a software trap for debugging This instruction allows the use of emulators This technique can be utilized by users for systems that have not been debugged by emulators B INTE Instruction Operation When the INTE instruction is executed the following operations take place 1 2 3 4 5 6 The contents of the program status PS are saved to the system stack The address of the next instruction is saved to the system stack The value of the system stack pointer SSP is reduced by
34. 49 Conditions for Generation of Coprocessor Not Found 48 Conditions for Generation of Step Trace Traps 47 Coprocessor Error Trap Operation 49 Coprocessor Not Found Trap Operation 48 Overview of Coprocessor Error Traps 49 Overview of Coprocessor Not Found Traps 48 Overview of Step Trace Traps 47 Overview of Traps 44 Precautionary Information for Use of Step Trace Traps 47 Relation of Step Trace Traps to NMI and External nter piae nay tee sites 47 Results of Coprocessor Operations after a Coprocessor Error Trap uie ns 49 Sources of Traps 44 Step Trace Trap Operation 47 Time to Start of Trap Processing for INT Instructions nre 45 Time to Start of Trap Processing for INTE Instructions rtr 46 U Undefined Instruction Exception PC Values Saved for Undefined Instruction cedet sieste 43 288 How to Use Undefined Instruction Exceptions 43 Operations of Undefined Instruction Exceptions Overview of Undefined Instruction Exceptions 43 Time to Start of Undefined Instruction Exception Processing iere 43 Undefined Instructions Undefined Instructions Placed in Delay Slots
35. CALL D Ri RET RET D RETI INTE DIVOS Ri DIVOU Ri DIVI Ri DIV3 DIV2 Ri DIV4S LD R15 Rs ST Rs R15 EXTSB Ri LDI 32 32 Ri LD R15 PS ST PS G R15 EXTUB Ri LEAVE EXTSH Ri NOP EXTUH Ri COPOP u4 CC CRj CRi COPLD u4 CC Rj CRi COPST u4 CC CRj Ri Undefined COPSV u4 CC CRj Ri INDEX INDEX The index follows on the next page This is listed in alphabetical order 277 INDEX Index A ADD ADD Add 4 bit Immediate Data to Destination Register nre 73 ADD Add Word Data of Source Register to Destination Register 72 ADD2 Add 4 bit Immediate Data to Destination Register 74 Add Stack Pointer ADDSP Add Stack Pointer and Immediate Data ER 241 Add Word Data ADD Add Word Data of Source Register to Destination Register 72 ADDC Add Word Data of Source Register and Carry Bit to Destination Register 75 ADDN Add Word Data of Source Register to Destination Register 76 ADDC ADDC Add Word Data of Source Register and Carry Bit to Destination Register 75 ADDN ADDN Add Immediate Data to Destination Register T 77 ADDN Add Word Data of Source Register to Destination Register 76 ADDN2 Add Immedia
36. 0000 000F D1 DOT 000 NZVC 0100 After execution 135 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 42 DIV3 Correction when Remainder is 0 This instruction is used in signed division It should be used in combinations such as DIV0S DIV1 x 32 DIV2 DIV3 and DIV4S DIV3 Correction when Remainder is 0 Assembler format DIV3 Operation if Z 1 MDL 1 MDL Flag change N Z V and C Unchanged Execution cycles 1 cycle Instruction format MSB LSB 110 011 1 1 1 11011119 0 0 010 Example DIV3 Instruction bit pattern 1001 1111 0110 0000 R2 OOFF FFFF R2 OOFF FFFF MDH 0000 0000 MDH 0000 0000 MDL 0000 000F MDL 00000010 D1DOT D1DOT SCR 000 SCR 000 NZVC NZVC CCR 0100 CCR 0100 Before execution After execution 136 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 43 DIV4S Correction Answer for Signed Division This instruction is used in signed division It should be used in combinations such as DIVOS DIV1 x 32 DIV2 DIV3 and DIVAS DIVAS Correction Answer for Signed Division Assembler format DIV4S Operation 01 1 0 MDL MDL Flag change N Z V and C Unchanged Execution cycles 1 cycle Instruction format MSB LSB
37. 150 7 57 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS LD Load Word Data in Memory to Register Loads the word data at memory address R13 Rj to Ri LD Load Word Data in Memory to Register Assembler format Operation Flag change Execution cycles Instruction format Example LD R13 Rj Ri R13 gt Ri N Z V and C Unchanged b cycle s MSB LSB LD R13 R2 R3 Instruction bit pattern 0000 0000 0010 0011 R2 0000 0004 R2 R3 XXXX XXXX R3 R13 1234 5678 R13 12345678 Memory 12345678 1234567C 8765 4321 1234567C Before execution 00000004 8765 4321 1234 5678 Memory 8765 4321 After execution 151 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 58 LD Load Word Data in Memory to Register Loads the word data at memory address R14 08 x 4 to Ri The value 08 is a signed calculation LD Load Word Data in Memory to Register Assembler format LD R14 disp10 Ri Operation R14 08 x 4 2 Ri Flag change N Z V and C Unchanged Execution cycles b cycle s Instruction format MSB LSB 1 08 Ri Example LD R14 4 R3 Instruction bit pattern 0010 0000 0001 0011 R3 XXXX R3 8765 4321
38. 2a cycles Instruction format MSB LSB 106 Example BANDL 0 R3 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Instruction bit pattern 1000 0000 0000 0011 R3 1234 5678 12345678 12345679 CCR Memory 11 NZ VC 0000 Before execution R3 1234 5678 Memory 12345678 10 12345679 NZVC CCR 0000 After execution 107 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 27 And 4 bit Immediate Data to Higher 4 Bits of Byte Data in Memory Takes the logical AND of the 4 bit immediate data and the higher 4 bits of byte data at memory Ri stores the results to the memory address corresponding to Ri The CPU will not accept hold requests between the memory read operation and the memory write operation of this request BANDH And 4 bit Immediate Data to Higher 4 Bits of Byte Data in Memory Assembler format BANDH u4 Ri Operation u4 lt 4 and Ri Ri Operation uses higher 4 bits only Flag change N Z V and C Unchanged Execution cycles 1 2a cycles Instruction format MSB LSB 108 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example BANDH 0 R3 Instruction bit pattern 1000 0001 0000 0011 R3 1234 5678 R3 1234 5678 Memory p Memory 12345678 11 12345678 01 12345679 12345679
39. 7 47 LSR Logical Shift to the Right Direction is changed Instruction bit pattern 1011 0010 0010 0011 is added 7 50 ASR Arithmetic Shift to the Right Direction is changed Instruction bit pattern 1011 1010 0010 0011 is added 7 53 LDE32 Load Immediate 32 bit Data to Destination Register is changed Instruction bit pattern 1001 1111 1000 0011 1000 0111 0110 0101 0100 0011 0010 0001 is added 7 54 LDE20 Load Immediate 20 bit Data to Destination Register is changed Instruction bit pattern 1001 1011 0101 0011 0100 0011 0010 0001 is added 7 55 LDES Load Immediate 8 bit Data to Destination Register is changed Instruction bit pattern 1100 0010 0001 0011 is added 7 56 LD Load Word Data in Memory to Register is changed Instruction bit pattern 0000 0100 0010 0011 is added 7 57 LD Load Word Data in Memory to Register is changed Instruction bit pattern 0000 0000 0010 0011 is added 7 59 LD Load Word Data in Memory to Register is changed o4 gt 04 7 60 LD Load Word Data Memory to Register is changed Instruction bit pattern 0000 0111 0000 0011 is added 7 61 LD Load Word Data in Memory to Register is changed Instruction bit pattern 0000 0111 1000 0100 is added 7 62 LD Load Word Data in Memory to Program Status Register is changed Flag change Ri R15 7
40. CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 88 CALL Call Subroutine This is a branching instruction with no delay slot After storing the address of the next instruction in the return pointer RP branch to the address indicated by lavel12 relative to the value of the program counter PC When calculating the address double the value of rel11 as a signed extension CALL Call Subroutine Assembler format CALL label12 Operation PC 2 RP PC 2 exts rel11 x 2 gt PC Flag change N Z V and C Unchanged Execution cycles 2 cycles Instruction format MSB LSB Example CALL label label CALL instruction address 122 Instruction bit pattern 1101 0000 1001 0000 PC FF800000 PC FF80 0122 RP XXXX XXXX RP FF80 0004 Before execution After execution 185 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 89 CALL Call Subroutine This is a branching instruction with no delay slot After storing the address of the next instruction in the return pointer RP a branch to the address indicated by Ri occurs CALL Call Subroutine Assembler format CALL Ri Operation PC 2 gt RP Ri 2 PC Flag change N Z V and C Unchanged Execution cycles 2 cycles Instruction format
41. Instruction format MSB LSB Example LD R15 R3 Instruction bit pattern 0000 0111 0000 0011 R3 XXXX XXXX R3 8765 4321 R15 1234 5678 R15 1234 567C Memory Memory 12345678 8765 4321 12345678 8765 4321 1234567C 1234567C Before execution After execution 154 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 61 LD Load Word Data in Memory to Register Loads the word data at memory address R15 to dedicated register Rs and adds 4 to the value of R15 If the number of a non existent register is given as parameter Rs the read value Ri will be ignored If Rs is designated as the system stack pointer SSP or user stack pointer USP and that pointer is indicating R15 the 5 flag in the condition code register CCR is set to 0 to indicate the SSP and to 1 to indicate the USP the last value remaining in R15 will be the value read from memory LD Load Word Data in Memory to Register Assembler format LD R15 Rs Operation R15 Rs R15 4 5 R15 Flag change N Z V and C Unchanged Execution cycles b cycle s Instruction format MSB LSB 155 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example LD R15 MDH Instruction bit pattern 0000 0111 1000 0100 R15 1234 5674 R15 1234 5678 MDH MDH 8765 4321 1
42. MA WB Data read cycle to RO Read cycle from R1 In cases such as this the FR family CPU executes the instruction correctly by pausing before execution of the subsequent instruction This function is called interlocking In the example in Figure 5 3 4 the ID stage of the SUB instruction is delayed until the data is loaded from the MA stage of the LD instruction Figure 5 3 4 Example of Interlocking LD RO R1 IF ID EX WB SUB R1 R2 IF ID WB Data read cycle to RO Read cycle from R1 Interlocking Produced by Reference to R15 and General purpose Registers after Changing the S Flag The general purpose register R15 is designed to function as either the system stack pointer SSP or user stack pointer USP For this reason the FR family CPU is designed to automatically generate an interlock whenever a change to the S flag in the condition code register CCR in the program status PS is followed immediately by an instruction that references the R15 This interlock enables the CPU to reference the SSP or USP values in the order in which they are written in the program FR family hardware design similarly generates an interlock whenever a TYPE A format instruction immediately follows an instruction that changes the value of the S flag For information on instruction format types see Section
43. OR Or Word Data of Source Register to Data in Memory ORH Or Half word Data of Source Register to Data in Memory ORB Or Byte Data of Source Register to Data in Memory EOR Exclusive Or Word Data of Source Register to Destination Register EOR Exclusive Or Word Data of Source Register to Data in Memory EORH Exclusive Or Half word Data of Source Register to Data in Memory EORB Exclusive Or Byte Data of Source Register to Data in Memory BANDL And 4 bit Immediate Data to Lower 4 Bits of Byte Data in Memory BANDH And 4 bit Immediate Data to Higher 4 Bits of Byte Data in Memory BORL Or 4 bit Immediate Data to Lower 4 Bits of Byte Data in Memory BORH Or 4 bit Immediate Data to Higher 4 Bits of Byte Data in Memory BEORL Eor 4 bit Immediate Data to Lower 4 Bits of Byte Data in Memory BEORH Eor 4 bit Immediate Data to Higher 4 Bits of Byte Data in Memory BTSTL Test Lower 4 Bits of Byte Data in Memory BTSTH Test Higher 4 Bits of Byte Data in Memory MUL Multiply Word Data MULU Multiply Unsigned Word Data MULH Multiply Half word Data MULUH Multiply Unsigned Half word Data DIVOS Initial Setting Up for Signed Division DIVOU Initial Setting Up for Unsigned Division 7 40 7 41 7 42 7 43 7 44 7 45 7 46 7 47 7 48 7 49 7 50 7 51 7 52 7 53 7 54 7 55 7 56 7 57 7 58 7 59 7 60 7 61 7 62 7 63 7 64 7 65 7 66 7 67 7 68 7 69 7 70 7 71 7 72 7 73 7 74 7 75 7 76 CHAPTER 7 DETAILED EXECUTION INST
44. PC 2 rel8x2 PC if V 0 PC 2 rel8x2 PC if V xor N PC 2 rel8x2 PC if V xor N PC 2 rel8x2 PC if V xor N or Z PC 2 rel8x2 PC if V xor N or Z 0 PC 2 rel8x2 PC if C or Z 1 PC 2 rel8x2 PC if C or Z label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 E D D D D D D D D D D D D D D D D Notes The field rel8 in the TYPE D instruction format and the field rel11 in the TYPE F format have the following relation to the values label9 and 12 in assembly notation label9 rel8 label9 PC 2 2 label12 rel11 label12 PC 2 2 The value 2 1 in the cycle CYC column indicates 2 cycles if branching 1 if not branching e tis necessary to set the S flag to 0 for RETI execution 270 APPENDIX A Instruction Lists Table A 2 12 Delayed Branching Instructions 20 Instructions Mnemonic Operation Remarks JMP D Ri CALL D label12 Ri PC PC 4 RP PC 2 rell 1 2 PC PC 4 RP Ri gt PC RP PC Return No branch PC 2 rel8x2 PC PC 2 rel8x2 PC if Z PC 2 rel8x2 PC if Z 0 PC 2 rel8x2 PC if C PC 2 rel8x2 PC if C 0 PC 2 rel8x2 PC if N PC 2 rel8x2 PC if N PC 2 rel8x2 PC if V 1 PC 2 rel8x2 PC if V PC 2 rel8x2 PC if V xor N PC 2 rel8x2 PC if
45. Reset 35 CHAPTER 4 RESET AND EIT PROCESSING Saved Registers Except in the case of reset processing the values of the PS and PC are saved to the stack as designated by the SSP regardless of the value of the S flag in the CCR No save operation is used in reset processing Figure 4 2 3 illustrates the saving of the values of the PC and PS in EIT processing Figure 4 2 3 Saving PC and PS Values in EIT Processing Immediately before interrupt Immediately after interrupt Memory space Memory space 00000000H 4 00000000H 4 7FFFFFF8H SSP 7FFFFFF8H 12345678H Interrupt 7FFFFFFCH 7FFFFFFCH 000C0010H SSP 80000000H 80000000H IL 9 TBR 000FFC00H TBR 000FFC00H 4 4 56781234H offset 000003B8H offset 000003B8H PC 12345678H PC 56781234H 56781234H PS 000C0010H PS 00090010H 1 FFFFFFFFH Recovery from EIT handler RETI instruction is used for recovery from the EIT handler To insure the program execution results after recovery it is required that all the contents of the CPU register are saved Ensure that the PC and PS values in the stack are not overwritten unless necessary because those values saved in the stack at the occurrence of EIT are recovered from the stack during the recovery sequence using the RETI instruction Be sure
46. ST Store Word Data in Register to Memory ST Store Word Data in Register to Memory ST Store Word Data in Register to Memory ST Store Word Data in Register to Memory ST Store Word Data in Program Status Register to Memory STH Store Half word Data in Register to Memory 69 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 70 7 77 7 78 7 79 7 80 7 81 7 82 7 83 7 84 7 85 7 86 7 87 7 88 7 89 7 90 7 91 7 92 7 93 7 94 7 95 7 96 7 97 7 98 7 99 7 100 7 101 7 102 7 103 7 104 7 105 7 106 7 107 7 108 7 109 STH Store Half word Data in Register to Memory STH Store Half word Data in Register to Memory STB Store Byte Data in Register to Memory STB Store Byte Data in Register to Memory STB Store Byte Data in Register to Memory MOV Move Word Data in Source Register to Destination Register MOV Move Word Data in Source Register to Destination Register MOV MOV Move Word Data in Source Register to Destination Register Move Word Data in Program Status Register to Destination Register MOV Move Word Data in Source Register to Program Status Register JMP Jump CALL Call Subroutine CALL Call Subroutine RET Return from Subroutine INT Software Interrupt INTE Software Interrupt for Emulator RETI Return from Interrupt Bec Branch Relative if Condition Satisfied JMP D Jump CALL D Call Subroutine CALL D Call Subroutine RET D Return from Subroutine Bcc D Br
47. The lower portion of the address space is used for the direct address area Instructions that specify direct addresses allow you to access this area without the use of general purpose registers using only the operand information in the instruction itself The size of the address area that can be specified by direct addressing varies according to the length of the data being transferred Direct Address Area The size of the address area that can be specified by direct addressing varies according to the length of the data being transferred as follows Transfer of byte data 0000 0000 to 0000 00 Transfer of half word data 0000 0000y to 0000 01 Transfer of word data 0000 0000y to 0000 03 Use of Operand Information Contained in Instructions The 8 bit address information contained in the instruction has the following significance nbyte data Value represents the lower 8 bits of the address nhalf word data Value is doubled and used as the lower 9 bits of the address n word data Value is multiplied by 4 and used as the lower 10 bits of the address Figure 2 1 2 shows the relationship between the length of the data that designates the direct address and the actual address in memory Figure 2 1 2 Relation between Direct Address Data and Memory Address Value Example 1 Byte data DMOVB R13 Q 58H Memory space Object code 1A58H data shift 58H T R13 12345678 0000 0058H
48. is changed extension for use as the branch destination address gt extension 7 88 CALL Call Subroutine is changed CALL 120H gt CALL label label CALL instruction address 1224 7 88 CALL Call Subroutine is changed Instruction bit pattern 1101 0000 1001 0000 is added 7 89 CALL Call Subroutine is changed Instruction bit pattern 1001 0111 0001 0001 is added 7 90 RET Return from Subroutine is changed Instruction bit pattern 1001 0111 0010 0000 is added 7 91 INT Software Interrupt is changed INT 9 to 13 64 65 gt INT 9 to INT 13 INT 64 INT 65 7 91 INT Software Interrupt is changed Instruction bit pattern 0001 1111 0010 0000 is added 7 92 INTE Software Interrupt for Emulator is changed Instruction bit pattern 1001 1111 0011 0000 is added 7 93 RETI Return from Interrupt is changed 02 1 S 7 93 Return from Interrupt is changed Instruction bit pattern 1001 0111 0011 0000 is added 7 94 Bcc Branch Relative if Condition Satisfied is changed extension for use as the branch destination address extension 7 94 Bcc Branch Relative if Condition Satisfied is changed 50H gt BHI label label BHI instruction address 50y 7 95 JMP D Jump is changed Instruction bit pattern 1001 1111 0000
49. 2 with the results stored at operand 2 Operations are designated by a mnemonic and use operand 1 Operations are designated by a mnemonic B Instruction Notation Formats FR family CPU instructions are written in the following 3 notation formats Calculations are designated by a mnemonic placed between operand 1 and operand 2 with the results stored at operand 2 lt Mnemonic gt lt 1 gt lt 2 Example ADD Rl R2 R1 R2 gt R2 Operations are designated by a mnemonic and use operand 1 lt Mnemonic gt lt Operand 1 gt Example JMP 1 R1 gt PC Operations are designated by a mnemonic lt Mnemonic gt Example NOP No operation 66 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS This chapter presents each of the execution instructions used by the FR family assembler in reference format The execution instructions used by the FR family CPU are classified as follows e Add Subtract Instructions Compare Instructions Logical Calculation Instructions e Bit Operation Instructions e Multiply Divide Instructions e Shift Instructions e Immediate Data Transfer Instructions e Memory Load Instructions Memory Store Instructions Inter register Transfer Instructions Dedicated Register Transfer Instructions Non delayed Branching Instructions e Delayed Branching Instructions Direct Addressing Instructions e Resource Instructions Coprocesso
50. CC CRj and CRi is done by the coprocessor so that the detailed operation is determined by the specifications of the coprocessor If the coprocessor designated by the value u4 is not mounted a coprocessor not found trap is generated If the coprocessor designated by the value u4 has generated an error in a previous operation a coprocessor error trap is generated COPOP Coprocessor Operation Assembler format u4 CC Operation CC CRj CRi Coprocessor on channel u4 Flag change N Z V and C Unchanged Execution cycles 2 acycles Instruction format MSB LSB n 0 1 01011 1 1 1 1 1 1 010 u4 n 2 CC CRj CRi 229 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example COPOP 15 1 CR3 CR4 16 bit data is transferred through the bus to the coprocessor indicated by channel number 15 Assuming that the coprocessor indicated by channel 15 is a single precision floating decimal calculation unit the coprocessor command CC set as shown in Table 7 116 1 will have the following effect on coprocessor operation Table 7 116 1 Conditions for Coprocessor Command CC COPOP Calculation Addition CRi CRj CRi Subtraction CRi CRj CRi Multiplication CRi x CRj CRi Division CRi CRj CRi No operation
51. ES R14 1234 5678 R14 1234 5678 12345678 Memory 12345678 1234567 8765 4321 1234567 8765 4321 Before execution After execution 152 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 59 LD Load Word Data in Memory to Register Loads the word data at memory address R15 u4 x 4 to Ri The value u4 is an unsigned calculation LD Load Word Data in Memory to Register LD R15 udisp6 Ri Assembler format Operation Flag change Execution cycles Instruction format Example R15 u4 x 4 gt Ri N Z V and C Unchanged b cycle s MSB LSB 0 0 10 01 01 011 1 4 LD R15 4 R3 Instruction bit pattern 0000 0011 0001 0011 R3 XXXX XXXX R3 8765 4321 R15 1234 5678 R15 1234 5678 12345678 Memory 12345678 Memory 1234567C 8765 4321 1234567C 8765 4321 Before execution After execution 153 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 60 LD Load Word Data in Memory to Register Loads the word data at memory address R15 to Rj and adds 4 to the value of R15 If R15 is given as parameter Ri the value read from the memory will be loaded into memory address R15 LD Load Word Data in Memory to Register Assembler format LD R15 Ri Operation R15 gt Ri R15 4 5 R15 Flag change N Z V and C Unchanged Execution cycles b cycle s
52. FUJITSU does not warrant proper operation of the device with respect to use based on such information When you develop equipment incorporating the device based on such information you must assume any responsibility arising out of such use of the information FUJITSU assumes no liability for any damages whatsoever arising out of the use of the information Any information in this document including descriptions of function and schematic diagrams shall not be construed as license of the use or exercise of any intellectual property right such as patent right or copyright or any other right of FUJITSU or any third party or does FUJITSU warrant non infringement of any third party s intellectual property right or other right by using such information FUJITSU assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein The products described in this document are designed developed and manufactured as contemplated for general use including without limitation ordinary industrial use general office use personal use and household use but are not designed developed and manufactured as contemplated 1 for use accompanying fatal risks or dangers that unless extremely high safety is secured could have a serious effect to the public and could lead directly to death personal injury severe physical damage or other loss i e nuclear reaction
53. R3 9999 9999 R3 8765 4321 NZVC NZVC CCR 0000 CCR 0000 Before execution After execution 81 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 11 Compare Word Data in Source Register and Destination Register Subtracts the word data in Rj from the word data in Ri places results in the condition code register CCR CMP Compare Word Data in Source Register and Destination Register Assembler format Rj Ri Operation Ri Rj Flag change N Set when the MSB of the operation result is 1 cleared when the MSB is 0 Z Set when the operation result is 0 cleared otherwise V Set when an overflow has occurred as a result of the operation cleared otherwise C Set when a borrow has occurred as a result of the operation cleared otherwise Execution cycles 1 cycle Instruction format MSB LSB 110111011 011 0 Rj Ri 1 1 1 1 1 1 Example CMP R2 R3 Instruction bit pattern 1010 1010 0010 0011 R2 1234 5678 R2 1234 5678 R3 1234 5678 R3 1234 5678 NZ VC NZ VC CCR 0000 CCR 0100 Before execution After execution 82 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 12 Compare Immediate Data of Source Register and Destination Register Subtracts the result of the higher 28 bits of 4 bit immediate data with zero extension from the word data in Ri places results in the
54. V and C Unchanged Execution cycles 1 cycle Instruction format MSB LSB 1101011111 11111 0101010 Ri Example JMP D R1 LDI 8 0FFH R1 Instruction placed in delay slot Instruction bit pattern 1001 1111 0000 0001 R1 C000 8000 R1 0000 00FF PC FF800000 PC 0008000 Before execution of JMP instruction After branching The instruction placed in the delay slot will be executed before execution of the branch destination instruction The value above will vary according to the specifications of the LDI 8 instruction placed in the delay slot 196 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 796 CALL D Call Subroutine This is a branching instruction with a delay slot After saving the address of the next instruction after the delay slot to the RP branch to the address indicated by 12 relative to the value of the program counter When calculating the address double the value of rel11 as a signed extension CALL D Call Subroutine Assembler format CALL D label12 Operation PC 4 RP PC 2 exts rel11 x 2 gt PC Flag change N Z V and C Unchanged Execution cycles 1 cycle Instruction format MSB LSB 1 1 0 1 1 rel11 l l 197 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example CALL D label LDI
55. and C Unchanged Execution cycles b cycle s Instruction format MSB LSB Example LDUB R2 R3 Instruction bit pattern 0000 0110 0010 0011 R2 1234 5678 R2 1234 5678 R3 XXXX XXXX R3 0000 0021 Memory Memory 12345678 21 12345678 21 Before execution After execution 162 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 67 LDUB Load Byte Data in Memory to Register Extends with zeros the byte data at memory address R13 Rj loads to Ri LDUB Load Byte Data in Memory to Register LDUB R13 Rj Ri Assembler format Operation Flag change Execution cycles Instruction format Example extu R13 Rj gt Ri N Z V and C Unchanged b cycle s LSB LDUB R13 R2 R3 R2 R3 R13 Instruction bit pattern 0000 0010 0010 001 1 00000004 XXXX XXXX 1234 5678 12345678 Memory 1234567C 2 1 Before execution R2 00000004 R3 0000 0021 R13 1234 5678 12345678 Memory 1234567C 21 After execution 163 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 68 LDUB Load Byte Data in Memory to Register Extends with zeros the byte data at memory address R14 08 loads to Ri The value 08 is a signed calculation LDUB Load Byte Data in Memory to Reg
56. 0000 CCR 0000 Before execution After execution 76 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 6 ADDN Add Immediate Data to Destination Register Adds the result of the higher 28 bits of 4 bit immediate data with zero extension to the word data in Ri stores the results to Ri without changing flag settings ADDN Add Immediate Data to Destination Register Assembler format ADDN i4 Ri Operation Ri extu i4 Ri Flag change N Z V and C Unchanged Execution cycles 1 cycle Instruction format MSB LSB Example ADDN 2 R3 Instruction bit pattern 1010 0000 0010 0011 R3 9999 9997 R3 9999 9999 NZVC NZ VC CCR 0000 CCR 0000 Before execution After execution 77 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 7 ADDN2 Add Immediate Data to Destination Register Adds the result of the higher 28 bits of 4 bit immediate data with minus extension to word data in Ri stores the results to Ri without changing flag settings ADDN2 Add Immediate Data to Destination Register Assembler format Operation Flag change Execution cycles Instruction format Example 78 ADDNe 14 Ri Ri extn i4 Ri N Z V and C Unchanged 1 cycle MSB LSB 110 1 0 0 0 0
57. 12345679 NZVC CCR 0000 Before execution R3 1234 5678 12345678 12345679 CCR Memory 10 NZVC 0000 After execution 117 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 32 BTSTL Test Lower 4 Bits of Byte Data in Memory Takes the logical AND of the 4 bit immediate data and the lower 4 bits of byte data at memory address Ri places the results in the condition code register CCR BTSTL Test Lower 4 Bits of Byte Data in Memory Assembler format Operation Flag change Execution cycles Instruction format Example 118 BTSTL u4 Ri u4 and Ri Test uses lower 4 bits only N Cleared Z Set when the operation result is 0 cleared otherwise V and Unchanged 2 a cycles MSB LSB BTSTL 1 R3 Instruction bit pattern 1000 1000 0001 0011 R3 1234 5678 R3 1234 5678 Memory Memory 12345678 10 12345678 1 0 12345679 12345679 NZVC NZVC CCR 0000 CCR 0100 Before execution After execution CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 733 BTSTH Test Higher 4 Bits of Byte Data in Memory Takes the logical AND of the 4 bit immediate data and the higher 4 bits of byte data at memory address Ri places the results in the condition code register CCR BTSTH Test Higher 4 Bits of Byte Data in Memory Assembler format BTSTH u4 Ri
58. 2 MEMORY ARCHITECTURE 2 2 1 5 2 1 FR Family Memory Space REM 6 2 1 1 Direct Address Area u ecc Ie eA wawawa aQ a ae 0 7 2 1 2 Vector Table Nea inii Ee eii sh a nv bed eet ed neg ei 8 2 2 Bit Order and Byte Order snarsintur aeaii ia nue 10 2 3 ANNMAN e vel eine 11 CHAPTER3 REGISTER DESCRIPTIONS 13 3 1 FR Family Register Configuration suisse 14 3 2 General purpose Registers iii 15 3 3 Dedicated Registers hectare tir ten Dee te ete tet gate tees 17 3 3 1 Program Gounter BO tette ttem n dent NEN 18 3 3 2 Program Status PS 19 3 3 3 Table Base Register TBR sise 23 3 3 4 Return Pointer RP m 25 3 3 5 System Stack Pointer SSP User Stack Pointer USP ss 27 3 3 6 Multiplication Division Register MD su 29 CHAPTER 4 RESET AND EIT PROCESSING T 31 4 1 Reset Processing ede re eue 33 4 2 Basic Operations EIT Processing us 34 4 3 Interr pts 5 suni te rte 37 4 3 1 38 4 3 2 Non maskable Interrupts NMI iii 40 4 4 Exception Processing u
59. 240 7 124 ADDSP Add Stack Pointer and Immediate 241 7 125 EXTSB Sign Extend from Byte Data to Word Data a 242 7 126 EXTUB Unsign Extend from Byte Data to Word Data 243 7 127 EXTSH Sign Extend from Byte Data to Word 244 7 128 Unsigned Extend from Byte Data to Word 245 7 129 LDMO Load Multiple Registers iii 246 7 130 LDM1 Load Multiple Registers is 248 7 131 STMO Store Multiple Registers siens 250 7 132 STMT Store Multiple Registers iii 252 7 133 ENTER Enter F nctlon apu iier eerie ie up Eten rene dro Era RER 254 7 134 LEAVE Leave Function ua ied dentes Eee dE Ree EO te etre De duca 256 7 135 XCHB Exchange Byte Data marora etienne referet pene dete bete 258 APPENDIX Ny ua ise porc annee TURN RN FEN E NE 261 APPENDIX A Instr ctloru Lists 2 asas qasata urA VARKA edes tene sere Dani Pra pent 262 Symbols Used in Instruction Lists ss 263 A2 Instruction 81555225 Le MR RAA s u w u mu MIS ANNE ARR AE 265 APPENDIX B Instruction Maps 2 Eme nre ebbe b eg e Daaka qaa Dai 274 Instruction ul hth bau t tute gu kaa der en uet Rt CUT ODER 275 Bio 55827 Rau abusata 276 INDEX 2
60. 6 1 Instruction Formats 57 CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU 5 4 Delayed Branching Processing Because the FR family CPU features pipeline operation branching instructions must first be loaded before they are executed Delayed branching processing is the function to execute the loaded instruction and allows to accelerate processing speeds Overview of Branching with Non delayed Branching Instructions In a pipeline operation by the time the CPU recognizes an instruction as a branching instruction the next instruction has already been loaded To process the program as written the instruction following the branching instruction must be canceled in the middle of execution Branching instructions that are handled in this manner are non delayed branching instructions Examples of processing non delayed branching instructions both when branching conditions are satisfied and not satisfied are described in Section 5 4 1 Processing Non delayed Branching Instructions Overview of Branching with Delayed Branching Instructions An instruction immediately following a branching instruction will already be loaded by the CPU by the time the branching instruction is executed This position is called the delay slot A delayed branching instruction is a branching instruction that executes the instruction in the delay slot regardless of whether the branching conditions are satisfied or not satisfied Exampl
61. C gt Ri Flag change N Set when the MSB of the operation result is 1 cleared when the MSB is 0 Z Set when the operation result is 0 cleared otherwise Set when an overflow has occurred as a result of the operation cleared otherwise C Set when a carry has occurred as a result of the operation cleared otherwise Execution cycles 1 cycle Instruction format MSB LSB 11011101011141 1 Rj Ri 1 1 1 1 1 1 Example ADDC R2 R3 Instruction bit pattern 1010 0111 0010 0011 R2 1234 5678 R2 1234 5678 R3 8765 4320 R3 9999 9999 NZ VC NZ VC CCR 0001 CCR 1000 Before execution After execution 75 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 5 ADDN Add Word Data of Source Register to Destination Register Adds the word data in Rj and the word data in Ri stores results to Ri without changing flag settings ADDN Add Word Data of Source Register to Destination Register Assembler format ADDN Rj Ri Operation Ri Rj Ri Flag change N Z V and C Unchanged Execution cycles 1 cycle Instruction format MSB LSB 1101110101 1011 0 Rj Ri 1 1 1 1 1 Example ADDN R2 R3 Instruction bit pattern 1010 0010 0010 0011 R2 1234 5678 R2 1234 5678 R3 8765 4321 R3 9999 9999 NZ VC NZVC CCR
62. Data to Destination Register sa 148 LDI 32 Load Immediate 32 bit Data to Destination Register daret deett 147 LDI 8 Load Immediate 8 bit Data to Destination Du E 149 LDM LDMO Load Multiple Registers 246 LDMI Load Multiple Registers 248 LDRES LDRES Load Word Data in Memory to Resource TRE ee 227 LDUB LDUB Load Byte Data in Memory to Register 162 163 164 LDUH LDUH Load Half word Data in Memory to Register pui uis sex 286 159 160 161 LEAVE LEAVE Leave Function 256 Leave Function LEAVE Leave Function 256 Left Direction LSL Logical Shift to the Left Direction 138 139 LSL2 Logical Shift to the Left Direction 140 Load COPLD Load 32 bit Data from Register to Coprocessor Register 231 Load Byte Data LDUB Load Byte Data in Memory to Register ORE 162 163 164 Load Half word Data LDUH Load Half word Data in Memory to Register RE 159 160 161 Load Immediate LDI 20 Load Immediate 20 bit Data to Destination 148 LDI 32 Load Immediate 32 bit Data to Destination Register kie eer fe eicit oa 147 283 INDEX LDI 8 Load Immediate 8 bit Data to Destination Register heit 149 Load Multiple Registers LDMO Load Multiple Registers 246 LDMI Load
63. Example LD GR15 Ri Stack pointer for reserve release of dynamic memory area Example ENTER u10 E Relation between R15 and Stack Pointer The R15 functions physically as either the system stack pointer SSP or user stack pointer USP for the general purpose registers When the notation R15 is used in an instruction this register will function as the USP if the S flag in the condition code register CCR section of the program status register PS is set to 1 The R15 register will function as the SSP if the S flag is set to 0 Ensure that the S flag value is set to 0 when R15 is recovered from the EIT handler with the RETI instruction Bi Initial Value of General purpose Registers After a reset the value of registers ROO through R14 are undefined and the value of R15 is 000000004 CHAPTER 3 REGISTER DESCRIPTIONS 3 3 Dedicated Registers The FR family has six 32 bit registers reserved for various special purposes plus one 64 bit dedicated register for multiplication and division operations Dedicated Registers The following seven dedicated registers are provided For details see the descriptions in Sections 3 3 1 Program Counter PC through 3 3 6 Multiplication Division Register MD 32 bit Dedicated Registers Program counter PC Program status PS Table base register TBR Return pointer RP System stack pointer SSP User stack pointer US
64. Multiple Registers 248 Load Word Data LD Load Word Data in Memory to Program Status Register dca ian ico teintes 157 LD Load Word Data in Memory to Register 150 151 152 153 154 155 LDRES Load Word Data Memory to Resource Logical Shift LSL Logical Shift to the Left Direction LSL2 Logical Shift to the Left Direction 140 LSR Logical Shift to the Right Direction LSL LSL Logical Shift to the Left Direction LSL2 Logical Shift to the Left Direction 140 LSR LSR Logical Shift to the Right Direction M MD Configuration of the MD Register 30 Memory Space Memory Space eene tetris 6 MOV MOV Move Word Data in Program Status Register to Destination Register 180 MOV Move Word Data in Source Register to Destination Register 178 179 181 MOV Move Word Data in Source Register to Program Status Register 182 Move Byte Data DMOVB Move Byte Data from Direct Address to Post Increment Register Indirect Address 223 DMOVB Move Byte Data from Direct Address to SES D cei 221 DMOVB Move Byte Data from Post Increment Register Indirect Address to Direct Address A 225 DMOVB Move Byte Data from Register to Direct AINddfess si eir tentia 222 Move Half word Data DMOVH Move Half word Data from Direct Address to Post Increment Register Indirect Address
65. R13 Rj Ri R14 disp10 Ri R15 udisp6 Ri R15 Ri R15 Rs R15 PS Operation Rj Ri R13 Rj Ri R14 disp10 Ri R15 udisp6 Ri R15 2 Ri R15 4 R15 gt Rs R15 4 R15 PS R15 4 Remarks Rs dedicated register LDUH Rj Ri LDUH R13 Rj Ri LDUH R14 disp9 Ri Rj gt Ri R13 Rj gt Ri R14 disp9 Rj Zero extension Zero extension Zero extension LDUB Rj Ri LDUB R13 Rj Ri LDUB R14 disp8 Ri W gt gt Q gt gt m i i Rj gt Ri R13 Rj Ri R14 disp8 Ri Zero extension Zero extension Zero extension Note The field o8 in the TYPE B instruction format and the field u4 in the TYPE C format have the following relation to the values disp8 to disp10 in assembly notation e disp8 o8 disp8 disp9 o8 disp9 gt gt 1 e disp10 o8 disp10 gt gt 2 udisp6 u4 udisp6 gt gt 2 268 Mnemonic Ri Rj Ri R13 Rj Ri R14 disp10 Ri R15 udisp6 Ri R15 Rs R15 PS R15 Table A 2 9 Memory Store Instructions 13 Instructions APPENDIX A Instruction Lists Operation Ri gt Rj Ri gt R13 Rj Ri gt R14 disp 10 Ri gt R15 udisp6 R15 4 Ri gt R15 15 4 Rs gt R15 R15 4 PS gt R15 Remarks Rs dedicated register Ri Rj Ri R13 Rj Ri R14 disp9 Ri gt Rj Ri R13 Rj Ri R14
66. Register 85 7 15 AND And Word Data of Source Register to Data in Memory 86 7 16 And Half word Data of Source Register to Data in Memory 88 7 17 X ANDB And Byte Data of Source Register to Data in Memory 90 7 18 OR Or Word Data of Source Register to Destination Register 92 7 19 OR Or Word Data of Source Register to Data in Memory sss 93 7 20 Or Half word Data of Source Register to Data in Memory 95 7 24 ORB Or Byte Data of Source Register to Data in 97 7 22 EOR Exclusive Or Word Data of Source Register to Destination Register 99 7 23 EOR Exclusive Or Word Data of Source Register to Data in Memory 100 7 24 Exclusive Or Half word Data of Source Register to Data in Memory 102 7 25 EORB Exclusive Or Byte Data of Source Register to Data in Memory 104 7 26 BANDL And 4 bit Immediate Data to Lower 4 Bits of Byte Data in Memory 106 7 27 BANDH And 4 bit Immedia
67. Subroutine 197 199 RET Return from Subroutine 187 Return from Subroutine 201 Subtract Word Data SUB Subtract Word Data in Source Register from Destination Register 79 SUBC Subtract Word Data in Source Register and Carry Bit from Destination Register 80 SUBN Subtract Word Data in Source Register from Destination Register 81 System Condition Code Register System Condition Code Register SCR Bit 10 to 287 INDEX System Stack Pointer Functions of the System Stack Pointer and User Stack Pointer aaa 28 System Stack Pointer SSP User Stack Pointer USP 27 Table Base Register Overview of the Table Base Register 23 Precautions Related to the Table Base Register 24 Table Base Register Configuration 24 Table Base Register 24 Test BTSTH Test Higher 4 Bits of Byte Data in Memory 119 BTSTL Test Lower 4 Bits of Data in Memory 118 Values Saved for Coprocessor Error Traps 49 Values Saved for Coprocessor Not Present Traps 48 PC Values Saved for Step Trace Traps 47 Conditions for Generation of Coprocessor Error Traps
68. The value of the system stack pointer SSP is reduced by 8 4 The value 0 is written to the S flag in the condition code register CCR in the PS 5 The value TBR 3E0p is stored in PC PC Values Saved for Coprocessor Not Present Traps The PC value saved to the system stack represents the address of the next instruction after the coprocessor instruction that caused the trap General purpose Registers during Execution of COPST COPSV Instructions Execution of any COPST COPS V instruction referring to a coprocessor that is not present in the system will cause undefined values to be transferred to the general purpose register RO to R14 designated in the operand The coprocessor not found trap will be activated after the designated general purpose register is updated 48 CHAPTER 4 RESET AND EIT PROCESSING 4 5 5 Coprocessor Error Trap A coprocessor error trap is generated when an error has occurred in a coprocessor operation and the CPU executes another coprocessor instruction involving the same coprocessor This section describes conditions for the generation operations and program counter PC values saved of coprocessor error traps Overview of Coprocessor Error Traps A coprocessor error trap is generated when an error has occurred in a coprocessor operation and the CPU executes another coprocessor instruction involving the same coprocessor Note that no coprocessor error traps are generated f
69. about addresses to be used as pointers for memory access These registers also have special functions with certain types of instructions Overview of General purpose Registers The FR family CPU has sixteen 16 general purpose registers each 32 bits in length Normal instructions can use any of these sixteen registers without distinction Figure 3 2 1 shows the configuration of a general purpose register Figure 3 2 1 General purpose Register Configuration Initial value 32bits RO Undefined R1 Undefined R2 Undefined R3 Undefined Undefined Undefined 00000000H Special Uses of General purpose Registers In addition to functioning as general purpose registers R13 R14 and R15 have the following special uses with certain types of instructions R13 Accumulator AC e Base address register for load store to memory instructions Example LD R13 Rj Ri e Accumulator for direct address designation Example DMOV dir10 R13 Memory pointer for direct address designation Example DMOV dir10 R13 CHAPTER 3 REGISTER DESCRIPTIONS R14 Frame Pointer FP Index register for load store to memory instructions Example LD R14 disp10 Ri Frame pointer for reserve release of dynamic memory area Example ENTER u10 R15 Stack Pointer SP Index register for load store to memory instructions Example LD R15 udisp6 Stack pointer
70. be accessed in multiples of two With branching instructions and other instructions that may result in attempting to store odd numbered values to the PC the lowest value in the PC will be read as 0 Thus an even numbered address will always be generated by fetching a branching instruction Data Restrictions on Word Alignment Word data Data must be assigned to addresses that are multiples of 4 Even if the operand value is not a multiple of 4 the lower two bits of the memory address will explicitly be read as 0 Half word data Data must be assigned to addresses that are multiples of 2 Even if the operand value is not a multiple of 2 the lowest bit of the memory address will explicitly be read as 0 Byte data There are no restrictions on addresses The forced setting of some bits to 0 during memory access for word data and half word data is applied after the computation of the execution address not at the source of the address information Figure 2 3 1 shows an example of the program word boundary and data word boundary Figure 2 3 1 Example of Program word Boundary and Data word Boundary R10 12345679H Memory space JMP R10 Bit 0 0 0000 0000 01 R14 4321567BH 12345678H 4234 5678 ST R13 R14 4 4321567BH 1234 567 STHR13 R2 00000004 R1 432156798 1234 567
71. disp9 Half word Half word Half word Ri Rj Ri R13 Rj Ri R14 disp8 m m m Q gt gt Ri 2 Rj Ri gt RI34Rj Ri R144disp8 Byte Byte Byte Note The field o8 in the TYPE B instruction format and the field u4 in the TYPE C format have the following relation to the values disp8 to disp10 in assembly notation disp8 o8 disp8 disp9 o8 disp9 gt gt 1 disp10 o8 disp10 gt gt 2 e udisp6 u4 udisp6 gt gt 2 Table A 2 10 Inter register Transfer Instructions Dedicated Register Transfer Instructions 5 Instructions Mnemonic Format Operation Remarks Transfer between general purpose registers Rs dedicated register Rs dedicated register 269 APPENDIX A Instruction Lists Table A 2 11 Non delayed Branching Instructions 23 Instructions Mnemonic Operation Remarks Ri PC 2 RP PC 2 rell 1x2 PC PC42 RP Ri PC RP PC Return SSP 4 PS SSP SSP 4 PC 2 SSP 0 gt I flag 0 S flag TBR 3FC u8x4 PC SSP 4 PS SSP SSP 4 PC 2 SSP 0 S flag 4 ILM TBR 3D8 u8x4 PC R15 gt 15 44 15 PS R15 4 No branch PC 2 rel8x2 PC 2 18 2 PC if Z PC 2 rel8x2 PC if Z 0 2 18 2 PC if C PC 2 rel8x2 PC if C PC 2 rel8x2 PC if N 1 PC 2 rel8x2 PC if N PC 2 rel8x2 PC if V
72. execution of simultaneously occurring EIT handlers is as shown in Table 4 6 2 Table 4 6 2 Priority of Execution of EIT Handlers Priority Masking of other sources Reset Other sources discarded Undefined instruction exception Other sources disabled Step trace trap ILM 4 4 INTE instruction ILM 4 5 NMI ILM 15 6 INT instruction I flag 0 7 User interrupt ILM level of source accepted Coprocessor not found trap None Coprocessor error trap When INTE instructions are run stepwise only the step trace EIT is generated Sources related to the INTE instruction will be ignored 52 CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU This chapter presents precautionary information related to the use of the FR family CPU 5 1 Pipeline Operation 5 2 Pipeline Operation and Interrupt Processing 5 3 Register Hazards 5 4 Delayed Branching Processing 53 CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU 5 1 Pipeline Operation The FR family CPU processes all instructions using a 5 stage pipeline operation This makes it possible to process nearly all instructions within one cycle Overview of Pipeline Operation In a pipeline operation the steps by which the CPU interprets and executes instructions are divided into several cycles so that instructions can be processed simultaneously in successive cycles This enables the system to appear to execute in
73. is a register used to contain the result of multiplication operations as well as the dividend and result of division operations The products of multiplication are stored in the MD in 64 bit format In division operations the dividend must first be placed in the lower 32 bits of the MD beforehand Then as the division process is executed the remainder is placed in the higher 32 bits of the MD and the quotient in the lower 32 bits Figure 3 3 15 shows an example of the use of the MD in multiplication and Figure 3 3 16 shows an example of division Figure 3 3 15 Sample Operation of MD in Multiplication Before execution of instruction MUL R00 R01 After execution of instruction MUL R00 R01 ROO 12345678H ROO 12345678H RO1 76543210H RO1 76543210H 086A1C970B88D780H Figure 3 3 16 Sample Operation of MD in Division Before execution of stepwise division u After execution of stepwise division ROO 12345678H ROO 12345678H Using ROO MD 2222222276543210 MD 091A264000000006H 29 CHAPTER 3 REGISTER DESCRIPTIONS Configuration of the MD Register Figure 3 3 17 shows the bit configuration of the MD Figure 3 3 17 Bit Configuration of the MD 31 00 MDH MDL Functions of the MD Storing Results of Multiplication and Division The re
74. left shift of the word data in Ri by u4 bits stores the result to Ri Logical Shift to the Left Direction Assembler format LSL u4 Ri Operation Ri lt lt u4 gt Ri Flag change N Set when the MSB of the operation result is 1 cleared when the MSB is 0 Z Set when the operation result is 0 cleared otherwise V Unchanged C Holds the bit value shifted last Cleared when the shift amount is 0 Execution cycles 1 cycle Instruction format MSB LSB 1 0 1 1 0 1 0 0 u4 Ri Example LSL 8 R3 Instruction bit pattern 1011 0100 1000 0011 R3 FFFFFFFF R3 FFFFFF00 NZVC NZ VC CCR 0000 CCR 1001 Before execution After execution 139 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 46 LSL2 Logical Shift to the Left Direction Makes a logical left shift of the word data Ri by u4 16 bits stores the results to Ri LSL2 Logical Shift to the Left Direction Assembler format LSL2 u4 Ri Operation Ri lt lt u4 16 Ri Flag change N Set when the MSB of the operation result is 1 cleared when the MSB is 0 Z Set when the operation result is 0 cleared otherwise V Unchanged C Holds the bit value shifted last Execution cycles 1 cycle Instruction format MSB LSB Example LSL2 8 R3
75. met The peripheral circuit is operating and generates an interrupt request The interrupt enable bit in the peripheral circuit s control register is set to enable The value of the interrupt request ICR is lower than the value of the ILM setting The I flag is set to 1 1 Interrupt Control Register a register on the microcontroller that controls interrupts 2 ILM Interrupt Level Mask Register a register in the CPU s program status PS Operation Following Acceptance of a User Interrupt The following operating sequence takes place after a user interrupt is accepted 38 The contents of the program status PS are saved to the system stack The address of the next instruction is saved to the system stack The value of the system stack pointer SSP is reduced by 8 The value level of the accepted interrupt is stored in the ILM The value 0 is written to the S flag in the condition code register CCR in the program status PS The vector address of the accepted interrupt is stored in the program counter PC CHAPTER 4 RESET AND EIT PROCESSING Time to Start of Interrupt Processing The time required to start interrupt processing can be expressed as a maximum of n 6 cycles from the start of the instruction currently executing when the interrupt was received where n represents the number of execution cycles in the instruction If the instruction includes memory access o
76. program counter PC value that is saved to the stack Sources of Traps Sources of traps include the following NT instructions For details see Section 4 5 1 INT Instructions INTE instructions For details see Section 4 5 2 INTE Instruction Step trace traps For details see Section 4 5 3 Step Trace Traps Coprocessor not found traps For details see Section 4 5 4 Coprocessor Not Found Traps Coprocessor error traps For details see Section 4 5 5 Coprocessor Error Trap CHAPTER 4 RESET AND EIT PROCESSING 4 5 1 INT Instructions The INT instruction is used to create a software trap This section describes the operation time requirements program counter PC values saved and other information of the INT instruction Overview of the INT Instruction The INT u8 instruction is used to create a software trap with the interrupt number designated in the operand B INT Instruction Operation When the INT u8 instruction is executed the following operations take place 1 2 3 4 5 6 The contents of the program status PS are saved to the system stack The address of the next instruction is saved to the system stack The value of the system stack pointer SSP is reduced by 8 The value 0 is written to the I flag in the condition code register CCR in the PS The value 0 is written to the S flag in the CCR in the PS The value 3FCy
77. register Ri Basically this operation transfers data from a register within the coprocessor The 32 bit data stored in coprocessor register CRj is transferred to CPU general purpose register Ri Note that the actual interpretation of the fields CC CRj Ri is done by the coprocessor so that the detailed actual operation is determined by the specifications of the coprocessor If the coprocessor designated by the value u4 is not mounted a coprocessor not found trap is generated If the coprocessor designated by the value u4 has generated an error in a previous operation a coprocessor error trap is generated COPST Store 32 bit Data from Coprocessor Register to Register Assembler format u4 CC Ri Operation CC CRj Ri Coprocessor on channel u4 Ri Flag change N Z V and C Unchanged Execution cycles 1 2a cycles Instruction format MSB LSB n 0 E k k n 2 CRj Ri 233 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example COPST 15 4 CR2 R4 16 bit data is transferred through the bus to the coprocessor indicated by channel number 15 Next the output data of the coprocessor are transferred through the bus to that coprocessor Assuming that the coprocessor indicated by channel 15 is a single precision floating
78. set to enable step trace traps both NMI and external interrupts are disabled Precautionary Information for Use of Step Trace Traps Step trace traps cannot be used in user programs involving debugging with an emulator Note also that no EIT events can be generated by INTE instructions when the step trace trap function is used 47 CHAPTER 4 RESET AND EIT PROCESSING 4 5 4 Coprocessor Not Found Traps Coprocessor not found traps are generated by executing coprocessor instructions using coprocessors not found in the system This section describes conditions for the generation of coprocessor not found traps in addition to operation program counter PC values saved and other information Overview of Coprocessor Not Found Traps Coprocessor not found traps are generated by executing coprocessor instructions using coprocessors not found in the system Conditions for Generation of Coprocessor Not Found Traps A coprocessor not found trap is generated when the following conditions are met e Execution of a COPOP COPLD COPST COPSV instruction No coprocessor present in the system corresponds to the operand u4 in any of the above instructions Coprocessor Not Found Trap Operation When a coprocessor not found trap is generated the following operations take place 1 The contents of the program status PS are saved to the system stack 2 The address of the next instruction is saved to the system stack 3
79. to Memory Stores the byte data in Ri to memory address R14 08 The value 08 is a signed calculation STB Store Byte Data in Register to Memory Assembler format STB Ri R14 disp8 Operation Ri R14 08 Flag change N Z V and C Unchanged Execution cycles a cycle s Instruction format MSB LSB o 1 1 1 08 Ri Example STB R3 R14 1 Instruction bit pattern 0111 0000 0001 0011 R3 0000 0021 R3 0000 0021 R14 1234 5678 R14 1234 5678 12345678 Memory 12345678 Memory 12345679 12345679 21 Before execution After execution 177 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 82 MOV Move Word Data in Source Register to Destination Register Moves the word data in Rj to Ri MOV Move Word Data in Source Register to Destination Register Assembler format MOV Rj Ri Operation Rj Ri Flag change N Z V and C Unchanged Execution cycles 1 cycle Instruction format Example MOV R2 R3 Instruction bit pattern 1000 1011 0010 0011 R2 8765 4321 R2 8765 4321 R3 XXXX XXXX R3 8765 4321 Before execution After execution 178 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 83 MOV Move Word Data in Source Register to Destination Register Moves the word data in dedicated registe
80. to set the S flag to 0 when the RETI instruction is executed 36 CHAPTER 4 RESET AND EIT PROCESSING 4 3 Interrupts Interrupts originate independently of the instruction sequence They are processed by saving the necessary information to resume the currently executing instruction sequence and then starting the processing routine corresponding to the type of interrupt that has occurred There are two types of interrupt sources User interrupts e Non maskable interrupts NMI Overview of Interrupt Processing Interrupts originate independently of the instruction sequence They are processed by saving the necessary information to resume the currently executing instruction sequence and then starting the processing routine corresponding to the type of interrupt that has occurred Instructions loaded and executing in the CPU before the interrupt will be executed to completion however any instructions loaded in the pipeline after the interrupt will be canceled After completion of interrupt processing therefore execution will return to the next instruction following the generation of the interrupt signal Sources of Interrupts There are two types of interrupt sources User interrupts See Section 4 3 1 User Interrupts Non maskable interrupts NMI See Section 4 3 2 Non maskable Interrupts NMI Interrupts during Execution of Stepwise Division Programs To enable resumption of processing when interrupts
81. u aci u ed lide ieee teed penne ne dev nd E Ende a 42 4 4 1 Undefined Instruction Exceptions ss 43 4 5 TraD8 ee emm 44 4 5 1 NTT 081 555250 u y ted cet ep Eton ate 45 4 5 2 INTE InStr CtlOD s o tto 4442 taba or e ite eiie E 46 4 5 3 Step Trace Traps uet ee etra eret teri Eat E EP Rabe Rt Pt Ace nait 47 4 5 4 Coprocessor Not Found Traps issue 48 4 5 5 Coprocessor Error Trap ge E UR EE 49 4 6 Priority Levels u atic Teese E nine een en el nina are E EY AS 51 CHAPTER5 PRECAUTIONARY INFORMATION FOR THE FR FANILY CPU 53 5 1 Pipeline Op ration uuu ote he e Qu eset tede dus Qu tau 54 5 2 Pipeline Operation and Interrupt Processing ss 55 5 3 iE eite i ele ende ER 56 5 4 Delayed Branching Processing sise 58 5 4 1 Processing Non delayed Branching Instructions 60 5 4 2 Processing Delayed Branching Instructions 61 CHAPTER6 INSTRUCTION OVERVIEW 63 6 1 Instruction Formats ul ae le Re re chee 64 6 2 Instruction Notation Formats iii 66 CHAPTER 7 DETAILED EXECUTION INS
82. 0 ss 134 DIV3 Correction when Remainder is 0 ss 136 DIV4S Correction Answer for Signed Division a 137 LSL Logical Shift to the Left Direction sus 138 LSL Logical Shift to the Left Direction su 139 LSL2 Logical Shift to the Left Direction su 140 LSR Logical Shift to the Right Direction sis 141 LSR Logical Shift to the Right Direction suis 142 LSR2 Logical Shift to the Right Direction su 143 ASR Arithmetic Shift to the Right Direction ss 144 ASR Arithmetic Shift to the Right Direction ss 145 ASR2 Arithmetic Shift to the Right Direction ss 146 LDI 32 Load Immediate 32 bit Data to Destination Register 147 LDI 20 Load Immediate 20 bit Data to Destination Register 148 LDI 8 Load Immediate 8 bit Data to Destination Register 149 LD Load Word Data in Memory to Register 150 LD Load Word Data in Memory to Register enm nennen 151 LD Load Word Data in Memory to Register 152 LD Load Word Data in Memory to Register 153 LD Load Word Data in Memory to Register a 154 LD Load Word Data in Memory to Register 155 LD Load Word Data in Memory to Program Status Register
83. 00 0100 0010 0011 is added 7 16 ANDH And Half word Data of Source Register to Data in Memory is changed Instruction bit pattern 1000 0101 0010 0011 is added 7 17 ANDB And Byte Data of Source Register to Data in Memory is changed Instruction bit pattern 1000 0110 0010 0011 is added 7 18 OR Or Word Data of Source Register to Destination Register is changed Instruction bit pattern 1001 0010 0010 0011 is added 7 19 OR Or Word Data of Source Register to Data in Memory is changed Instruction bit pattern 1001 0100 0010 0011 is added 7 20 ORH Or Half word Data of Source Register to Data in Memory is changed Instruction bit pattern 1001 0101 0010 0011 is added 7 21 ORB Or Byte Data of Source Register to Data in Memory is changed Instruction bit pattern 1001 0110 0010 0011 is added 7 22 EOR Exclusive Or Word Data of Source Register to Destination Register is changed Instruction bit pattern 1001 1010 0010 0011 is added 7 23 EOR Exclusive Or Word Data of Source Register to Data in Memory is changed Instruction bit pattern 1001 1100 0010 0011 is added 7 24 EORH Exclusive Or Half word Data of Source Register to Data in Memory is changed Instruction bit pattern 1001 1101 0010 0011 is added 7 25 EORB Exclusive Or Byte Data of Source Register to Data in Memory is changed Instruction bit pat
84. 000 X XXX X X X X X XXX X X X X X XXX X X X X After execution 255 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 134 LEAVE Leave Function This instruction is used for stack frame release processing for high level languages LEAVE Leave Function Assembler format LEAVE Operation R14 4 R15 R15 4 R14 Flag change N Z V and C Unchanged Execution cycles b cycle s Instruction format MSB LSB 256 Example CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS LEAVE Instruction bit pattern 1001 1111 1001 0000 R14 7FFF FFF4 R14 8000 0000 gt R15 7F FF FFEC Ri5 7FFF Memory Memory 7FFFFFEC XX XX XX XX ZFFFFFED X XXX 7FFFFFFO x xxx xx xx 7FFFFFFO XXX X 7FFFFFF4 8000 0000 7FFFFFF4 8000 0000 7FFFFFF8 X XXX XX CX X 7FFFFFF8 XX XX 7FFFFFFC x xxx xxx x XX XX 80000000 XXXX 80000000 XXXX Before execution After execution 257 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 135 XCHB Exchange Byte Data Exchanges the contents of the byte address indicated by Rj and those indicated by Ri The lower 8 bits of data originally at Ri are transferred to the byte address indicated by Rj and the data originally at Rj
85. 000 001 1 R3 8765 4321 R3 8765 4321 R15 1234 5678 R15 1234 5674 Memory Memory 12345674 xX XXX XX X X 12345674 8765 4321 12345678 12345678 Before execution After execution 169 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 4 ST Store Word Data in Register to Memory Subtracts 4 from the value of R15 stores the word data in dedicated register Rs to the memory address indicated by the new value of R15 If a non existent dedicated register is given as Rs undefined data will be transferred ST Store Word Data in Register to Memory Assembler format ST Rs R15 Operation R15 4 R15 Rs R15 Flag change N Z V and C Unchanged Execution cycles a cycle s Instruction format MSB LSB 01001110 11111 1 01010 Rs Example ST MDH R15 Instruction bit pattern 0001 0111 1000 0100 R15 1234 5678 R15 1234 5674 MDH 8765 4321 MDH 8765 4321 12345670 Memory 12345670 Memory 12345674 XXXX 12345674 8765 4321 Before execution After execution 170 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 75 ST Store Word Data in Program Status Register to Memory Subtracts 4 from the value of R15 stores the word data in the program status PS to the memory address indicated by the new value of R15 ST Store Word Data in Program Status Register to Memo
86. 0001 is added 7 96 CALL D Call Subroutine is changed extension for use as the branch destination address extension xvi Page Changes For details refer to main body 7 96 CALL D Call Subroutine is changed CALL D 120H LDI 8 0 R2 Instruction placed in delay slot gt CALL D label LDI 8 0 R2 Instruction placed in delay slot label CALL D instruction address 1224 7 96 CALL D Call Subroutine is changed Instruction bit pattern 1101 1000 1001 0000 is added 7 97 CALL D Call Subroutine is changed Instruction bit pattern 1001 1111 0001 0001 is added 7 98 RET D Return from Subroutine is changed Instruction bit pattern 1001 1111 0010 0000 is added 7 99 Bcc D Branch Relative if Condition Satisfied is changed extension for use as the branch destination address extension 7 99 Bcc D Branch Relative if Condition Satisfied is changed BHI D 50H LDI 8 255 Instruction placed in delay slot gt BHED label LDI 8 255 R1 Instruction placed in delay slot label BHI D instruction address 50g 7 99 Bcc D Branch Relative if Condition Satisfied is changed Instruction bit pattern 1111 1111 0010 1000 is changed 7 114 LDRES Load Word Data in Memory to Resource is changed Instruction bit pattern 1011 1100 1000 0010 is added 7 115 STRES Store Word D
87. 01 0111 0110 0010 R2 OOFFFFFF MDH OOFF FFFF MDL 0000 0000 SCR CCR D1 DOT NZVC 0000 Before execution R2 MDH MDL SCR CCR OOFFFFFF 0100 0000 0000 0001 D1 DOT 000 NZVC 0000 After execution 133 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 41 DIV2 Correction when Remainder is 0 This instruction is used in signed division It should be used in combinations such as DIV0S DIV1 x 32 DIV2 DIV3 and DIV4S DIV2 Correction when Remainder is 0 Assembler format DIV2 Ri Operation if D1 1 MDH Ri gt temp else MDH Ri gt temp if Z 0 1 Flag change Nand V Unchanged Z Set when the operation result of stepwise division is 0 cleared otherwise Set according to remainder of division results not according to quotient C Set when the result of stepwise division involves a carry or borrow operation cleared otherwise Execution cycles 1 cycle Instruction format MSB LSB 134 Example DIV2 R2 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS R2 MDH MDL SCR CCR OOFF OOFF FFFF 0000 000F D1 DOT 000 NZVC 0000 Before execution Instruction bit pattern 1001 0111 0111 0010 R2 MDH MDL SCR CCR OOFFFFFF 0000 0000
88. 02 R2 0000 0002 R3 8000 0001 R3 8000 0001 MDH XXXX XXXX MDH 0000 0001 MDL MDL 0000 0002 NZVC NZVC CCR 0000 CCR 0010 Before execution After execution 123 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 736 MULH Multiply Half word Data Multiplies the half word data in the lower 16 bits of Rj by the half word data in the lower 16 bits of Ri as signed numbers and stores the resulting signed 32 bit data in the multiplication division register MDL The multiplication division register MDH is undefined MULH Multiply Half word Data Assembler format MULH Rj Ri Operation Rj x Ri MDL Flag change N Set when the MSB of the MDL of the operation result is 1 cleared when the MSB is 0 Z Set when the MDL of the operation result is 0 cleared otherwise V Unchanged C Unchanged Execution cycles 3 cycles Instruction format MSB LSB 124 Example MULH R2 R3 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS R2 R3 MDH MDL CCR FEDCBA98 0123 4567 XX XX XX XX XX XX NZVC 0000 Before execution Instruction bit pattern 1011 1111 0010 0011 R2 R3 MDH MDL CCR FEDCBAOS9S8 0123 4567 XXXX XX XX ED2F0B28 NZVC 1000 After execution 125 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
89. 1 i4 Ri 1 l 1 1 1 1 ADDN2 2 Instruction bit pattern 1010 0001 1110 0011 R3 9999 9999 R3 9999 9997 NZVC NZVC CCR 0000 CCR 0000 Before execution After execution CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 8 SUB Subtract Word Data in Source Register from Destination Register Subtracts the word data in Rj from the word data in Ri stores results to Ri SUB Subtract Word Data in Source Register from Destination Register Assembler format SUB Rj Ri Operation Ri Rj Ri Flag change Set when the MSB of the operation result is 1 cleared when the MSB is 0 Z Set when the operation result is 0 cleared otherwise V Set when an overflow has occurred as a result of the operation cleared otherwise C Set when a borrow has occurred as a result of the operation cleared otherwise Execution cycles 1 cycle Instruction format MSB LSB 110111011 110 0 Rj Ri Example SUB R2 R3 Instruction bit pattern 1010 1100 0010 0011 R2 1234 5678 R2 1234 5678 R3 9999 9999 R3 8765 4321 NZVC NZVC CCR 0000 CCR 1000 Before execution After execution 79 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 9 SUBC Subtract Word Data in Source Register and Carry Bit from Destination Register Subtracts the word data in Rj and the carry bit from the word data in Ri stores results to Ri SUBC Subtract Word Data in Source
90. 10 Operation R15 dir8 x 4 R15 4 5 R15 Flag change N Z V and C Unchanged Execution cycles 2a cycles Instruction format MSB LSB 1 1 1 0 1 1 dir8 213 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example DMOV R15 38H Instruction bit pattern 0001 1011 0000 1110 R15 7FFEEE8O R15 7FFEEE84 Memory Memory 00000038 X X X X X X X X 00000038 8343 834A 7FFEEE80 8343 834A 7FFEEE80 8343 834A 7FFEEE84 X X X X X X X X 7FFEEE84 X X X X X X X X Before execution After execution 214 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 106 DMOVH Move Half word Data from Direct Address to Register Transfers the half word data at the direct address corresponding to 2 times the value dir8 to R13 Uses zeros to extend the higher 16 bits of data DMOVH Move Half word Data from Direct Address to Register Assembler format DMOVH dir9 R13 Operation Flag change dir8 x 2 R13 N Z V and C Unchanged Execution cycles b cycle s Instruction format MSB LSB 010101 1011101011 dir8 Example DMOVH 88H R13 Instruction bit pattern 0000 1001 0100 0100 R13 XX XX XX XX R13 0000 B2B6 Memory J Memory 86 X X X X 86 X X X X 88 B2B6 88 B2B6 8A X X X X 8A X X X X Before execution After execution 215 CHAPT
91. 1011 0101 0011 0100 0011 0010 0001 R3 0000 0000 p R3 0005 4321 Before execution After execution 148 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 55 LDI 8 Load Immediate 8 bit Data to Destination Register Extends the 8 bit immediate data with 24 zeros in the higher bits loads to Ri LDI 8 Load Immediate 8 bit Data to Destination Register Assembler format LDI 8 i8 Ri Operation extu 18 gt Ri Flag change N Z V and C Unchanged Execution cycles 1 cycle Instruction format MSB LSB Example LDI 8 21H R3 Instruction bit pattern 1100 0010 0001 0011 R3 0000 0000 p R3 0000 0021 Before execution After execution 149 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 56 LD Load Word Data in Memory to Register Loads the word data at memory address Rj to Ri LD Load Word Data in Memory to Register Assembler format LD Ri Operation Rj Ri Flag change N Z V and C Unchanged Execution cycles b cycle s Instruction format MSB LSB Example LD R2 R3 Instruction bit pattern 0000 0100 0010 0011 R2 1234 5678 R2 1234 5678 R3 0000 0000 R3 8765 4321 Memory Memory 12345678 8765 4321 12345678 8765 4321 Before execution After execution
92. 211 DMOV Move Word Data from Direct Address to ene eee Eae 205 DMOV Move Word Data from Post Increment Register Indirect Address to Direct Address Vua Asia dece Ea aa ues 209 213 DMOV Move Word Data from Register to Direct Address 206 DMOVB DMOVB Move Byte Data from Direct Address to Post Increment Register Indirect Address 223 DMOVB Byte Data from Direct Address to Register iiie 221 DMOVB Move Byte Data from Post Increment Register Indirect Address to Direct Address 225 DMOVB Move Byte Data from Register to Direct Address sio ieu reset asas 222 DMOVH DMOVH Move Half word Data from Direct Address to Post Increment Register Indirect Address idisse se EE awama Qa u iege ES dome sheet 217 DMOVH Move Half word Data from Direct Address to Register eie eerte derat 215 DMOVH Move Half word Data from Post Increment Register Indirect Address to Direct Address Pea T EE TREE 219 DMOVH Move Half word Data from Register to Direct Address 216 E E Format E Format tte ns 276 EIT Basic Operations in EIT Processing 34 EIT handler Recovery from EIT handler 28 36 Emulator INTE Software Interrupt for Emulator 190 ENTER ENTER Enter Function 254 Enter Function EN
93. 2345670 Memory 12345670 Memory 12345674 8765 4321 12345674 8765 4321 Before execution After execution 156 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 62 LD Load Word Data in Memory to Program Status Register Loads the word data at memory address R15 to the program status PS and adds 4 to the value of R15 At the time this instruction is executed if the value of the interrupt level mask register ILM is in the range 16 to 31 only new ILM settings between 16 and 31 can be entered If data in the range 0 to 15 is loaded from memory the value 16 will be added to that data before being transferred to the ILM If the original ILM value is in the range 0 to 15 then any value from 0 to 31 can be transferred to the ILM LD Load Word Data in Memory to Program Status Register Assembler format LD Q R15 PS Operation R15 PS R15 4 5 R15 Flag change N Z V and C Data is transferred from R15 Execution cycles 1 a ccycles The value of c is normally 1 cycle However if the next instruction involves read or write access to memory address R15 the system stack pointer SSP or the user stack pointer USP then an interlock is applied and the value becomes 2 cycles Instruction format MSB LSB 157 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example 158 LD R15 PS R15 PS 12345670 1
94. 2345674 1234 5674 FFFFF8D5 Memory FFF8 F8CO Before execution Instruction bit pattern 0000 0111 1001 0000 R15 PS 12345670 12345674 1234 5678 FFF8F8CO0 Memory FFF8F8CO0 After execution CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 63 LDUH Load Half word Data in Memory to Register Extends with zeros the half word data at memory address Rj loads to Ri LDUH Load Half word Data in Memory to Register Assembler format LDUH Qhij Ri Operation extu Rj Ri Flag change N Z V and C Unchanged Execution cycles b cycle s Instruction format MSB LSB Example LDUH R2 R3 Instruction bit pattern 0000 0101 0010 0011 R2 1234 5678 R2 1234 5678 R3 XXXX XXXX R3 0000 4321 Memory b Memory 12345678 4321 12345678 4321 Before execution After execution 159 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 64 LDUH Load Half word Data in Memory to Register Extends with zeros the half word data at memory address R13 Rj loads to Ri LDUH Load Half word Data in Memory to Register Assembler format LDUH R13 Rij Ri Operation extu R13 Rj Ri Flag change N Z V and C Unchanged Execution cycles b cycle s Instruction format MSB LSB
95. 33 FF801222 XXXX After execution CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 110 DMOVB Move Byte Data from Direct Address to Register Transfers the byte data at the address indicated by the value dir8 to R13 Uses zeros to extend the higher 24 bits of data DMOVB Move Byte Data from Direct Address to Register Assembler format DMOVB dir8 R13 Operation dir8 gt R13 Flag change N Z V and C Unchanged Execution cycles b cycle s Instruction format MSB LSB 01010 011101110 dir8 Example DMOVB 91H R13 Instruction bit pattern 0000 1010 1001 0001 R13 XXXX XXXX R13 0000 0032 Memory Memory 90 X x 90 X X 91 3 2 91 3 2 92 X X 92 X X Before execution After execution 221 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 111 DMOVB Move Byte Data from Register to Direct Address Transfers the byte data from R13 to the direct address indicated by the value dir8 DMOVB Move Byte Data from Register to Direct Address Assembler format DMOVB R13 dir8 Operation R13 dir8 Flag change N Z V and C Unchanged Execution cycles a cycle s Instruction format MSB LSB 010101111 011 10 dir8 1 DMOVB R13 53H Instruction bit pattern 0001 1010 0101 0011
96. 43 Unsign Extend EXTUB Unsign Extend from Byte Data to Word Data pep EE 243 Unsigned Division DIVOU Initial Setting Up for Unsigned Division erm 130 Unsigned Extend EXTUH Unsigned Extend from Byte Data to Word Data iva esos ete tassa ER Re 245 User Interrupt Conditions for Acceptance of User Interrupt Requests rene tesi abra Pattes tra in RE Pg aeta 38 How to Use User Interrupts 39 Operation Following Acceptance of an User Interrupt 38 Overview of User Interrupts 38 User Stack Pointer Functions of the System Stack Pointer and User Stack Pointer 4 ios cc ii terret 28 System Stack Pointer SSP User Stack Pointer USP ETE 27 USP System Stack Pointer SSP User Stack Pointer USP u u ANa 27 V Vector Table Contents of Vector Table Areas 9 Overview of Vector Table Areas 8 Unused Vector Table 6 Vector Table Area Initial 9 Vector Table Configuration 35 w Word Alignment Data Restrictions on Word Alignment 11 Program Restrictions on Word Alignment 11 X XCHB XCHB Exchange Byte Data 258 CM71 00101 5E FUJITSU SEMICONDUCTOR CONTRO
97. 567C Memory Memory ch 8 Resource KE X OK KEK ch 8 Resource 8765 4321 12345678 8765 4321 12345678 8765 4321 1234567C 1234567C Before execution After execution 227 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 115 STRES Store Word Data in Resource to Memory Transfers the word data at the resource on channel u4 to the address indicated by Ri Increments the value of Ri by 4 STRES Store Word Data in Resource to Memory Assembler format STRES 04 Ri Operation Resource on channel u4 Ri Ri 4 Ri Flag change N Z V and C Unchanged Execution cycles a cycle s Instruction format Example STRES 8 R2 Instruction bit pattern 1011 1101 1000 0010 R2 1234 5678 R2 1234 5670C Memory Memory ch 8 Resource 8765 4321 ch 8 Resource 8765 4321 12345678 Xx XXX XXXX 12345678 8765 4321 1234567C 1234567C Before execution After execution 228 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 116 COPOP Coprocessor Operation Transfers the 16 bit data consisting of parameters CC CRj CRi to the coprocessor indicated by channel number u4 Basically this operation is a calculation between registers within the coprocessor The calculation process indicated by the value CC is carried out between coprocessor registers CRj and CRi Note that the actual interpretation of the fields
98. 62 LD Load Word Data in Memory to Program Status Register is changed Instruction bit pattern 0000 0111 1001 0000 is added 7 63 LDUH Load Half word Data in Memory to Register is changed Instruction bit pattern 0000 0101 0010 0011 is added 7 64 LDUH Load Half word Data in Memory to Register is changed Instruction bit pattern 0000 0001 0010 0011 is added 7 66 LDUB Load Byte Data in Memory to Register is changed Instruction bit pattern 0000 0110 0010 0011 is added XiV Page Changes For details refer to main body 7 67 LDUB Load Byte Data in Memory to Register is changed Instruction bit pattern 0000 0010 0010 0011 is added 7 69 ST Store Word Data in Register to Memory is changed Instruction bit pattern 0001 0100 0010 0011 is added 7 70 ST Store Word Data in Register to Memory is changed Instruction bit pattern 0001 0000 0010 0011 is added 7 72 ST Store Word Data in Register to Memory is changed o4 gt u4 7 73 ST Store Word Data in Register to Memory is changed Instruction bit pattern 0001 0111 0000 0011 is added 7 74 ST Store Word Data in Register to Memory is changed Instruction bit pattern 0001 0111 1000 0100 is added 7 75 ST Store Word Data in Program Status Register to Memory is changed Instruction bit pattern 0001 0111 1001 0000 is added
99. 7 DMOVH Move Half word Data from Post Increment Register Indirect Address to Direct Address m ber awama 219 DMOVB Move Byte Data from Direct Address to Register 221 DMOVB Move Byte Data from Register to Direct Address a 222 DMOVB Move Byte Data from Direct Address to Post Increment Register Indirect Address Em 223 DMOVB Move Byte Data from Post Increment Register Indirect Address to Direct Address it 225 LDRES Load Word Data in Memory to Resource I 227 STRES Store Word Data in Resource to Memory sse 228 COPOP Coprocessor Operation 229 COPLD Load 32 bit Data from Register to Coprocessor Register 231 COPST Store 32 bit Data from Coprocessor Register to Register 233 Save 32 bit Data from Coprocessor Register to Register 235 INOP No Operatiori a tel red tenes 237 ANDCCR And Condition Code Register and Immediate Data 238 ORCCR Or Condition Code Register and Immediate Data 239 viii 7 123 STILM Set Immediate Data to Interrupt Level Mask Register
100. 7 37 MULUH Multiply Unsigned Half word Data Multiplies the half word data in the lower 16 bits of Rj by the half word data in the lower 16 bits of Ri as unsigned numbers and stores the resulting unsigned 32 bit data in the multiplication division register MDL The multiplication division register MDH is undefined MULUH Multiply Unsigned Half word Data Assembler format MULUH Rj Ri Operation Rj x Ri MDL Flag change N Set when the MSB of the MDL of the operation result is 1 cleared when the MSB is 0 Z Set when the MDL of the operation result is 0 cleared otherwise V Unchanged C Unchanged Execution cycles 3 cycles Instruction format MSB LSB 126 Example MULUH R2 R3 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS R2 R3 MDH MDL CCR FEDCBA98 0123 4567 XXXX XX XX X XXX X X X X NZVC 0000 Before execution Instruction bit pattern 1011 1011 0010 0011 R2 R3 MDH MDL CCR 98 0123 4567 XXXX X X X X 3296 0B28 NZVC 0000 After execution 127 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 738 DIVOS Initial Setting Up for Signed Division This command is used for signed division in which the multiplication division register MDL contains the dividend and the Ri the divisor with the quotien
101. 7 97 R1 0000 00FF PC FF80 0000 gt PC FF80 0052 NZVC NZVC CCR 1010 CCR 1010 Z or C 0 conditions satisfied Before execution After execution The instruction placed in the delay slot will be executed before execution of the branch destination instruction The value R1 above will vary according to the specifications of the LDI 8 instruction placed in the delay slot 204 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 100 DMOV Move Word Data from Direct Address to Register Transfers to R13 the word data at the direct address corresponding to 4 times the value of dir8 DMOV Move Word Data from Direct Address to Register Assembler format DMOV dir10 R13 Operation dir8 x 4 R13 Flag change N Z V and C Unchanged Execution cycles b cycle s Instruction format MSB LSB 010101011101 010 Dog HB Example DMOV 288H R13 Instruction bit pattern 0000 1000 0010 0010 R13 XXXX XXXX R13 0123 4567 Memory Memory 84 XXXX XXXX 84 XXXX 88 0123 4567 88 0123 4567 8C XXXX XXXX 8C XXXX XXXX Before execution After execution 205 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 101 DMOV Move Word Data from Register to Direct Address Transfers the word data in R13 to the direct address corresponding to 4 times the value of dir8
102. 77 Main changes in this edition Page Changes For details refer to main body Be sure to refer to the Check Sheet for the latest cautions on development is changed Check Sheet is seen at the following support page is deleted Bl Objectives and intended reader is changed FR gt FR Bl Objectives and intended reader is changed is added PREFACE is changed E Trademark is added PREFACE is changed The company names and brand names herein are the trademarks or registered trademarks of their respective owners is added Table 2 1 1 Structure of a Vector Table Area is changed For 3F8H Yes Lowest Bit Value of Program Counter is changed incremented by one and therefore incremented and therefore Figure 3 3 4 ILM Register Functions is changed A line from ILM to COMP is added Figure 3 3 7 Sample of Table Base Register TBR Operation is changed 31 bit31 B System Stack Pointer SSP User Stack Pointer USP is changed ST R13 R15 ST R13 R15 The title of Figure 3 3 12 Example of Stack Pointer Operation in Execution of Instruction ST R13 R15 when S Flag 0 is changed ST R13 R15 ST R13 R15 The title of Figure 3 3 13 Example of Stack Pointer Operation in Execution of Instruction ST R13 R15 when S Flag 1 is changed ST R13
103. 785 MOV Move Word Data in Source Register to Destination Register Moves the word data in general purpose register Ri to dedicated register Rs If the number of a non existent register is given as parameter Rs the read value Ri will be ignored MOV Move Word Data in Source Register to Destination Register Assembler format MOV Ri Rs Operation Ri 2 Rs Flag change N Z V and C Unchanged Execution cycles 1 cycle Instruction format MSB LSB 1 O 1 1 01011 1 Rs Ri Example MOV R3 MDL Instruction bit pattern 1011 0011 0101 0011 R3 8765 4321 R3 8765 4321 MDL XXXX XXXX MDL 8765 4321 Before execution After execution 181 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 86 MOV Move Word Data in Source Register to Program Status Register Moves the word data in general purpose register Ri to the program status PS At the time this instruction is executed if the value of the interrupt level mask register ILM is in the range 16 to 31 only new ILM settings between 16 and 31 can be entered If data in the range 0 to 15 is loaded from Ri the value 16 will be added to that data before being transferred to the ILM If the original ILM value is in the range 0 to 15 then any value from 0 to 31 can be transferred to the ILM MOV Move Word Data in Source Register to Program Status Reg
104. 7FE multiples of 2 for the value of PC Ri Rj indicates a general purpose register ROO to R15 sus indicates a dedicated register TBR RP USP SSP MDH MDL Symbols in Operation Column extu indicates a zero extension operation in which values lacking higher bits are complemented by adding the value 0 as necessary extn indicates a minus extension operation in which values lacking higher bits are complemented by adding the value 1 as necessary exts indicates a sign extension operation in which a zero extension is performed for the data within in which the MSB is 0 and a minus extension is performed for the data in which the MSB is 1 Chimie indicates indirect addressing which values reading or loading from to the memory address where the registers within or the formula indicate rem indicates the calculation priority is used for specifying indirect address 263 APPENDIX A Instruction Lists 264 Format Column OP Column format TYPE A through F as described in Section 6 1 Instruction Formats OP codes have the following significance according to the format type listed in the format column Format types A C D 2 digit hexadecimal value represents 8 bit OP code Format type B 2 digit hexadecimal value represents higher 4 bits of OP code lower 4 bits NOM Format type E 4 digit hexadecimal value with highe
105. 8 The value 4 is written to the interrupt level mask register ILM in the PS The value 0 is written to the S flag in the CCR in the PS The value TBR 308 is stored in PC Time to Start of Trap Processing for INTE Instructions The time required to start trap processing is 6 cycles PC Values Saved for INTE Instruction Execution The PC value saved to the system stack represents the address of the next instruction after the INTE instruction Precautionary Information for Use of INTE Instructions The INTE instruction cannot be used in user programs involving debugging with an emulator Also the INTE instruction should not be used within an INTE instruction handler or step trace trap handler routine This will prevent normal operation from resuming after the RETI instruction Note also that no EIT events can be generated by INTE instructions during stepwise execution 46 CHAPTER 4 RESET AND EIT PROCESSING 4 5 3 Step Trace Traps Step trace traps are traps used by debuggers This type of trap can be created for each individual instruction in a sequence by setting the T flag in the system condition code register SCR in the program status PS This section describes conditions for the generation operations program counter PC values saved and other information of step trace traps Overview of Step Trace Traps Step trace traps are traps used by debuggers
106. 8 0 R2 Instruction placed in delay slot label CALL D instruction address 1224 Instruction bit pattern 1101 1000 1001 0000 R2 X X X X R2 0000 0000 PC 0 0000 PC FF800122 RP xxx x X X X X RP FF80 0004 Before execution of CALL instruction After branching The instruction placed in the delay slot will be executed before execution of the branch destination instruction The value R2 above will vary according to the specifications of the LDI 8 instruction placed in the delay slot 198 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 797 CALL D Call Subroutine This is a branching instruction with a delay slot After saving the address of the next instruction after the delay slot to the RP it branches to the address indicated by Ri CALL D Call Subroutine Assembler format CALL D Ri Operation PC 4 gt RP Ri 2 PC Flag change N Z V and C Unchanged Execution cycles 1 cycle Instruction format MSB LSB 199 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example CALL D R1 LDI 8 1 R1 Instruction placed in delay slot Instruction bit pattern 1001 1111 0001 0001 R1 FFFFF800 R1 0000 0001 PC 8000 FFFE PC FFFFF800 RP X X X X x x x x RP 8001 0002 Before execution of CALL instructi
107. 88 FFFF1248 FFFF124C FFFF1248 Memory 1414 2135 XXX X X X X X XX XX X X X X Before execution R13 00000088 FFFF1248 FFFF124C FFFF124C Memory 14142135 14142135 X XXX XX XX After execution CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 103 DMOV Move Word Data from Post Increment Register Indirect Address to Direct Address Transfers the word data at the address indicated in R13 to the direct address corresponding to 4 times the value dir8 After the data transfer it increments the value of R13 by 4 DMOV Move Word Data from Post Increment Register Indirect Address to Direct Address Assembler format DMOV R13 dir10 Operation R13 dir8 x 4 R13 4 5 R13 Flag change N Z V and C Unchanged Execution cycles 2a cycles Instruction format MSB LSB 1 0 1 1 1 010 dir8 209 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example 210 DMOV R13 54H R13 00000054 FFFF1248 FFFF124C FFFF1248 Memory XXX X X X X X 8947 91AF XX XX XX XX Before execution Instruction bit pattern 0001 1100 0001 0101 R13 00000054 FFFF1248 FFFF124C FFFF124C Memory 8947 91AF 8947 91AF XXXX XXXX After execution CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 104 DMOV Move Wo
108. 90BC 9363 R12 X X X X X X X X R12 8DF788E 4 R15 7FFF FFCO R15 7FFF FFCC Memory Memory 7FFFFFCO 8BFE39E8A 7FFFFFCO 8FE39E8A 7FFFFFC4 90BC9363 7FFFFFC4 90BC9363 7FFFFFC8 8DF788E4 7FFFFFC8 8DF788EA 7FFFFFCC X X X X X X X X 7FFFFFCC X X X X X X X X Before execution After execution 249 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 131 STMO0 Store Multiple Registers The STMO instruction accepts registers in the range RO to R7 as members of the parameter reglist See Table 7 131 1 Registers are processed in descending numerical order STMO Store Multiple Registers Assembler format STMO reglist Operation The following operations are repeated according to the number of registers specified in the parameter reglist R15 4 5 R15 Ri R15 Flag change N Z V and C Unchanged Execution cycles If n is the number of registers specified in the parameter reglist the execution cycles required are as follows 1 cycle Instruction format MSB LSB 1 1 1 1 0 reglist Table 7 131 1 Bit Values and Register Numbers for reglist STMO 7 e 5 4 250 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example STMO R2 R3 Instruction bit pattern 1000 1110 0011 0000 R2 90BC9363 R2 90BC 9363 R3 8343 834A R3 8343 834A R15 7FFF FFC8 R15 7FFF FFCO Memory Memory 7
109. APTER 7 DETAILED EXECUTION INSTRUCTIONS 7 23 EOR Exclusive Or Word Data of Source Register to Data in Memory Takes the logical exclusive OR of the word data at memory address Ri and the word data in Rj stores the results to the memory address corresponding to Ri The CPU will not accept hold requests between the memory read operation and the memory write operation of this request EOR Exclusive Or Word Data of Source Register to Data in Memory Assembler format EOR Rj Ri Operation Ri eor Rj Ri Flag change N Set when the MSB of the operation result is 1 cleared when the MSB is 0 7 Set when the operation result is 0 cleared otherwise V and C Unchanged Execution cycles 1 2a cycles Instruction format MSB LSB 100 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example EOR R2 R3 Instruction bit pattern 1001 1100 0010 0011 R2 1111 0000 R2 1111 0000 R3 1234 5678 R3 1234 5678 Memor Memor y b y 12345678 1010 1010 12345678 0101 1010 1234567C 1234567C NZVC NZVC CCR 0000 CCR 0000 Before execution After execution 101 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 24 EORH Exclusive Or Half word Data of Source Register to Data in Memory Takes the logical exclusive OR of the half word data at memory address Ri and the half word data in Rj stores the resul
110. C4 8343 834A 7FFFFFC4 8343 834A 7FFFFFC8 x XXX XX XX 7FFFFFC8 X XXX Before execution After execution 247 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 130 LDM1 Load Multiple Registers The LDM1 instruction accepts registers in the range R8 to R15 as members of the parameter reglist See Table 7 130 1 Registers are processed in ascending numerical order If R15 is specified in the parameter reglist the final contents of R15 will be read from memory B LDM1 Load Multiple Registers Assembler format LDM1 reglist Operation The following operations are repeated according to the number of registers specified in the parameter reglist R15 gt Ri R15 4 R15 Flag change N Z V and C Unchanged Execution cycles If n is the number of registers specified in the parameter reglist the execution cycles required are as follows If n 0 1 cycle For other values of n a n 1 b 1 cycles Instruction format MSB LSB 1 01010 1 1 0 1 reglist l l l l 248 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Table 7 130 1 Bit Values and Register Numbers for reglist LDM1 Register Bit Register Example LDM1 R10 R11 R12 Instruction bit pattern 1000 1101 0001 1100 R10 X X X X X X X X R10 8FE39E8A R11 X XXX X X X X R11
111. DIVI R2 32 DIV1s are arranged DIVI R2 R2 0123 4567 R2 0123 4567 MDH x xxx xxx x MDH 0000 0078 MDL FEDC 98 MDL 0000 OOEO 1 DOT D1 DOT SCR x x 0 SCR 000 Before execution After execution 131 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 40 DIV1 Main Process of Division This instruction is used in unsigned division It should be used in combinations such as DIV0U and DIV1 x 32 DIV1 Main Process of Division Assembler format Operation Flag change Execution cycles Instruction format 132 DIV1 Ri MDH MDL lt lt 1 if D1 1 MDH Ri gt temp else MDH Ri gt temp if DO eor D1 eor C 0 temp 1 2 MDL 0 N and V Unchanged Z Set when the result of step division is 0 cleared otherwise Set according to remainder of division results not according to quotient C Set when the operation result of step division involves a carry operation cleared otherwise d cycle s Normally executed within one cycle However a 2 cycle interlock is applied if the instruction immediately after is one of the following MOV MDH Ri MOV MDL Ri ST Rs 15 Rs dedicated register TBR RP USP SSP MDH MDL MSB LSB 0111110 Example DIV1 R2 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Instruction bit pattern 10
112. Data is changed Instruction bit pattern 1001 0111 1010 0001 is added 7 128 EXTUH Unsigned Extend from Byte Data to Word Data is changed Instruction bit pattern 1001 0111 1011 0001 is added 7 133 ENTER Enter Function is changed XXXX XXXX 0000 0011 0000 1111 0000 0011 7 134 LEAVE Leave Function is changed Instruction bit pattern 1001 1111 1001 0000 is addded 7 135 XCHB Exchange Byte Data is chenged Rj gt Ri extu Rj gt Ri 7 135 XCHB Exchange Byte Data is chenged Instruction bit pattern 1000 1010 0001 0000 is added xviii Page Changes For details refer to main body A 1 Symbols Used in Instruction Lists is chenged Symbols in Mnemonic and Operation Columns is changed 128 to 255 Oto255 A 1 Symbols Used in Instruction Lists is chenged Symbols in Mnemonic and Operation Columns is changed Note Data from 128 to 1 is handled as data from 128 to 255 is deleted A 1 Symbols Used in Instruction Lists is chenged Symbols in Mnemonic and Operation Columns is changed 0x80000 to 00000 to FFFFFg A 1 Symbols Used in Instruction Lists is chenged Symbols in Mnemonic and Operation Columns is changed Note Data from 0x80000 to 1 is handled as data from 0x80000 to OXFFFFF is deleted A 1 Symbols Used in Instruction Lists is chenged
113. Destination Register 85 CMP Compare Immediate Data of Source Register and Destination Register 83 CMP Compare Word Data in Source Register and Destination Register 82 CMP2 Compare Immediate Data and Destination ee eheu 84 EOR Exclusive Or Word Data of Source Register to Destination Register 99 LDI 20 Load Immediate 20 bit Data to Destination aaa au dade 148 LDI 32 Load Immediate 32 bit Data to Destination Register 147 LDI 8 Load Immediate 8 bit Data to Destination Register P 149 MOV Move Word Data in Program Status Register to Destination Register 180 MOV Move Word Data in Source Register to Destination Register 178 179 181 OR Or Word Data of Source Register to Destination ui E 92 SUB Subtract Word Data in Source Register from Destination Register 79 SUBN Subtract Word Data in Source Register from Destination Register 81 Direct Address Direct Address Area 002 7 DMOV Move Word Data from Direct Address to Post Increment Register Indirect Address DMOV Move Word Data from Direct Address to Pre decrement Register Indirect Address DMOV Move Word Data from Direct Address to Register ente 205 DMOV Move Word Data from Register to Direct Address
114. ER 7 DETAILED EXECUTION INSTRUCTIONS 7 407 DMOVH Move Half word Data from Register to Direct Address Transfers the half word data from R13 to the direct address corresponding to 2 times the value dir8 DMOVH Move Half word Data from Register to Direct Address Assembler format Operation Flag change Execution cycles Instruction format Example 216 DMOVH R13 dir9 R13 dir8 x 2 Z V C Unchanged a cycle s MSB LSB 0 1 1 dir8 DMOVH R13 52H Instruction bit pattern 0001 1001 0010 1001 R13 FFFF 86 R13 FFFF AE86 Memory Memory 50 X XX X 50 X X X X 52 X X X X 52 AE86 54 X X X X 54 X XXX Before execution After execution CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 108 DMOVH Move Half word Data from Direct Address to Post Increment Register Indirect Address Transfers the half word data at the direct address corresponding to 2 times the value dir8 to the address indicated by R13 After the data transfer it increments the value of R13 by 2 DMOVH Move Half word Data from Direct Address to Post Increment Register Indirect Address Assembler format DMOVH dir9 R13 Operation dir8 x 2 2 R13 R13 2 R13 Flag change N Z V and C Unchanged Execution cycles 2a cycles Instruction format MSB LSB 1 1 011 di
115. FFFFFCO X X X X X X X X 7FFFFFCO 90BC9363 7FFFFFC4 X X X X X X X X 7FFFFFC4 8343 834A 7FFFFFC8 X X X X X X X X 7FFFFFC8 x X X X X X X X Before execution After execution 251 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 132 STM1 Store Multiple Registers The STM1 instruction accepts registers in the range R8 to R15 as members of the parameter reglist See Table 7 132 1 Registers are processed in descending numerical order If R15 is specified in the parameter reglist the contents of R15 retained before the instruction is executed will be written to memory STM1 Store Multiple Registers Assembler format Operation Flag change Execution cycles Instruction format 252 STM1 reglist The following operations are repeated according to the number of registers specified in the parameter reglist 15 4 gt 15 Ri gt R15 N Z V and C Unchanged If n is the number of registers specified in the parameter reglist the execution cycles required are as follows a x n 1 cycles MSB LSB 1 0 1 1 1 1 reglist Table 7 132 1 Bit Values and Register Numbers for reglist STM1 R10 R11 Example CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS STM1 R10 R11 R12 Instruction bit pattern 1000 1111 0011 1000 R10 8FE39E8A R11 90BC9363 R12 8DF788E4 15 7
116. FUJITSU SEMICONDUCTOR CONTROLLER MANUAL CM71 00101 5E FR Family 32 BIT MICROCONTROLLER INSTRUCTION MANUAL cO FUJITSU FR Family 32 BIT MICROCONTROLLER INSTRUCTION MANUAL FUJITSU LIMITED PREFACE Objectives and intended reader The FR family CPU core features proprietary Fujitsu architecture and is designed for controller applications using 32 bit RISC based computing The architecture is optimized for use in microcontroller CPU cores for built in control applications where high speed control is required This manual is written for engineers involved in the development of products using the FR family of microcontrollers It is designed specifically for programmers working in assembly language for use with FR family assemblers and describes the various instructions used with FR family Be sure to read the entire manual carefully Note that the use or non use of coprocessors as well as coprocessor specifications depends on the functions of individual FR family products For information about coprocessor specifications users should consult the coprocessor section of the product documentation Also for the rules of assembly language grammar and the use of assembler programs refer to the FR Family Assembler Manual FR the abbreviation of FUJITSU RISC controller is a line of products of FUJITSU Limited B Trademark The company names and brand names herein are the trademarks or registered tradema
117. Half word Data in Register to Memory Assembler format STH Ri R13 Rj Operation Ri R13 Rj Flag change N Z V and C Unchanged Execution cycles a cycle s Instruction format MSB LSB Example STH R3 Q R13 R2 Instruction bit pattern 0001 0001 0010 0011 R2 00000004 R2 00000004 R3 0000 4321 R3 0000 4321 R13 1234 5678 R13 1234 5678 1234567A Memory 1234567A Memory 1234567C X X X X 1234567C 4321 Before execution After execution 173 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 78 STH Store Half word Data in Register to Memory Stores the half word data in Ri to memory address R14 08 x 2 The value 08 is a signed calculation STH Store Half word Data in Register to Memory STH Ri R14 disp9 Assembler format Operation Flag change Execution cycles Instruction format Example 174 Ri gt R14 08 x 2 N Z V and C Unchanged a cycle s MSB LSB 0 1 0 STH R3 R14 2 R3 0000 4321 R14 1234 5678 12345678 1234567A X X X X Before execution Instruction bit pattern 0101 0000 0001 0011 R3 00004321 R14 1234 5678 12345678 Memory 1234567A 43821 After execution CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 779 STB S
118. Initial value 011118 ILM Functions The ILM determines the level of interrupt that will be accepted Whenever the I flag in the CCR register is 1 the contents of this register are compared to the level of the current interrupt request If the value of this register is greater than the level of the request interrupt processing is activated Interrupt levels are higher in priority at value approaching 0 and lower in priority at increasing values up to 31 Note that bit ILM4 differs from the other bits in the register in that setting values for this bit are restricted Figure 3 3 4 shows the functions of the ILM CHAPTER 3 REGISTER DESCRIPTIONS Figure 3 3 4 ILM Register Functions FR family CPU Interrupt controller ILM I flag Interrupt activated ICR 29 1 lt Peripheral Interrupt 25 Comp 29 gt 25 Activation OK request Range of ILM Program Setting Values If the original value of the register is in the range 16 to 31 the new value may be set in the range 16 to 31 If an instruction attempts to set a value between 0 and 15 that value will be converted to setting value 16 and then transferred If the original value is in the range 0 to 15 any new value from 0 to 31 may be set Initialization of the ILM at Reset The reset value is 01111 System Condition Code Register SCR Bit 10 to bit 08 Bit Configuration of th
119. Instruction bit pattern 1011 0101 1000 0011 R3 FFFFFFFF R3 FF000000 NZVC NZVC CCR 0000 CCR 1001 Before execution After execution 140 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 47 LSR Logical Shift to the Right Direction Makes a logical right shift of the word data in Ri by Rj bits stores the result to Ri Only the lower 5 bits of Rj which designates the size of the shift are valid and the shift range is 0 to 31 bits LSR Logical Shift to the Right Direction Assembler format Operation Flag change Execution cycles Instruction format Example LSR Rj Ri Ri gt gt Rj gt Ri Set when the MSB of the operation result is 1 cleared when the MSB is 0 N Z Set when the operation result is 0 cleared otherwise V Unchanged C Holds the bit value shifted last Cleared when the shift amount is 0 1 cycle MSB LSB LSR R2 Instruction bit pattern 1011 0010 0010 0011 R2 0000 0008 b R2 0000 0008 R3 FFFFFFFF R3 OOFF FFFF NZVC NZVC CCR 0000 CCR 0001 Before execution After execution 141 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 48 LSR Logical Shift to the Right Direction Makes a logical right shift of the word data in Ri by u4 bits stores the result to Ri B LSR Logical Shift to the Ri
120. Instruction format MSB LSB 1 0 0 1 011 1 1 1 01011 Ri Example EXTUB R1 Instruction bit pattern 1001 0111 1001 0001 R1 FFFFFFFF R1 0000 00FF Before execution After execution 243 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 127 EXTSH Sign Extend from Byte Data to Word Data Extends the half word data indicated by Ri to word data as a signed binary value EXTSH Sign Extend from Byte Data to Word Data Assembler format Operation Flag change Execution cycles Instruction format Example 244 EXTSH Ri exts Ri Ri half word word N Z V and C Unchanged 1 cycle MSB LSB EXTSH R1 Instruction bit pattern 1001 0111 1010 0001 R1 0000 ABCD Before execution R1 FFFFABCD After execution CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 128 EXTUH Unsigned Extend from Byte Data to Word Data Extends the half word data indicated by Ri to word data as an unsigned binary value EXTUH Unsigned Extend from Byte Data to Word Data Assembler format EXTUH Ri Operation extu Ri Ri half word word Flag change N Z V and C Unchanged Execution cycles 1 cycle Instruction format MSB LSB
121. LLER MANUAL FR Family 32 BIT MICROCONTROLLER INSTRUCTION MANUAL December 2007 the fifth edition Published FUJITSU LIMITED Electronic Devices Edited Strategic Business Development Dept
122. NSTRUCTIONS 792 INTE Software Interrupt for Emulator This software interrupt instruction is used for debugging It stores the values of the program counter PC and program status PS to the stack indicated by the system stack pointer SSP for interrupt processing It writes 0 to the S flag in the condition code register CCR and uses the SSP as the stack pointer for the following steps It determines the branch destination address by reading interrupt vector number 9 from the vector table then branches There is no change to the I flag in the condition code register CCR The interrupt level mask register ILM in the program status PS is set to level 4 This instruction is the software interrupt instruction for debugging In step execution no EIT events are generated by the INTE instruction This instruction has no delay slot INTE Software Interrupt for Emulator Assembler format INTE Operation SSP 4 gt SSP PS SSP SSP 4 gt SSP PC 2 SSP 4 ILM 0 2 S flag TBR 3D84 PC Flag change I N Z V and C Unchanged S Cleared to 0 Execution cycles 3 3a cycles Instruction format MSB LSB 11010141 1 1 1 11010141 1 0 01010 190 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
123. NZVC NZVC CCR 0000 CCR 0000 Before execution After execution 109 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 728 Or 4 bit Immediate Data to Lower 4 Bits of Byte Data in Memory Takes the logical OR of the 4 bit immediate data and the lower 4 bits of byte data at memory address Ri stores the results to the memory address corresponding to Ri The CPU will not accept hold requests between the memory read operation and the memory write operation of this request BORL Or 4 bit Immediate Data to Lower 4 Bits of Byte Data in Memory Assembler format BORL u4 Ri Operation u4 or Ri Ri Operation uses lower 4 bits only Flag change N Z V and C Unchanged Execution cycles 1 2 cycles Instruction format MSB LSB 110 Example CHAPTER 7 BORL 1 R3 Instruction bit pattern 1001 0000 0001 0011 R3 1234 5678 Memory 12345678 00 12345679 NZVC CCR 0000 Before execution R3 1234 5678 12345678 12345679 CCR Memory 01 NZVC 0000 After execution DETAILED EXECUTION INSTRUCTIONS 111 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 729 Or 4 bit Immediate Data to Higher 4 Bits of Byte Data in Memory Takes the logical OR of the 4 bit immediate data and the higher 4 bits of byte data at memory address Ri stores the results to th
124. Operation u4 lt lt 4 and Ri Test uses higher 4 bits only Flag change N Set when the MSB bit 7 of the operation result is 1 cleared when the MSB is 0 Z Set when the operation result is 0 cleared otherwise Vand C Unchanged Execution cycles 2 a cycles Instruction format LSB Example BTSTH 1 R3 Instruction bit pattern 1000 1001 0001 0011 R3 1234 5678 R3 1234 5678 Memory 12345678 01 12345678 01 12345679 12345679 NZVC NZ VC CCR 0000 CCR 0100 Before execution After execution 119 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 734 MUL Multiply Word Data Multiplies the word data in Rj by the word data in Ri as signed numbers and stores the resulting signed 64 bit data with the high word in the multiplication division register MDH and the low word in the multiplication division register MDL MUL Multiply Word Data Assembler format MUL Rj Ri Operation Rj x Ri MDH MDL Flag change Set when the MSB of the MDL of the operation result is 1 cleared when the MSB is 0 Z Set when the operation result is 0 cleared otherwise V Cleared when the operation result is in the range 2147483648 to 2147483647 set otherwise C Unchanged Execution cycles 5 cycles Instruction format MSB LSB 1 0 1 0 1 1 1 1 Rj Ri 120 Ex
125. P 64 bit Dedicated Register Multiplication Division Register MD Figure 3 3 1 shows the configuration of the dedicated registers Figure 3 3 1 Dedicated Register Configuration PC Reset entry address ILM 01111B ps wm scr ccr CCREXKOOXXXX8 s 00000000 5 64 bits CHAPTER 3 REGISTER DESCRIPTIONS 3 3 1 Program Counter PC This register indicates the address containing the instruction that is currently executing Following a reset the contents of the PC are set to the reset entry address contained in the vector table Overview of the Program Counter This register indicates the address containing the instruction that is currently executing The value of the lowest bit is always read as 0 and therefore all instructions must be written to addresses that are multiples of 2 Program Counter Functions Lowest Bit Value of Program Counter The value of the lowest bit in the program counter is read as 0 by the internal circuits in the FR family device Even if 1 is written to this bit it will be treated as 0 for addressing purposes physical cell does exist for this bit however the lowest bit value remains 0 even when the program address value is incremented and therefore the value of this bit is always 0 except following a branching operation Because the internal circuits in the FR family device are designed to read the value of the lowest bit as 0 all instr
126. P update and PS save ID 2 2 2 2 3 SSP update and PC save ID 3 EX 3 MA 3 WB 3 4 Detection of new EIT event ID 4 EX 4 MA 4 WB 4 First instruction in EIT handler sequence branching instruction IF ID EX MA PC Note For a description of pipeline operations see Section 5 1 Pipeline Operation 34 CHAPTER 4 RESET AND EIT PROCESSING Vector Table Configuration Vector tables are located in the main memory occupying an area of 1 Kbyte beginning with the address shown in the TBR These areas are intended for use as a table of entry addresses for processing however in applications where vector tables are not required this area can be used as a normal instruction or data area Figure 4 2 2 shows the structure of the vector table Example of 32 source Figure 4 2 2 Vector Table Configuration TBR H Offset Vector Description oo INT 0FFH 00000000H i 004H INT 0FEH 1 008H FDH INT 0FDH 1 Kbyte 1 1 T 1 mu 33CH 30H INT 030H jos 340 2 02FH or IR31 FFFFFFFFFL h 344H 2EH INT 02EH or IR30 3BCH 10H INT 010H or IR00 3C0H OFH INT 00FH or NMI 3C4H OEH Undefined instruction exception 3C8H ODH Emulator exception 3CCH 0CH Step trace trap 3D0H OBH Operand break trap System reserved or Mode Vector
127. R Operation Vector correspondence table bit31 0 Vector no Vector offset EAddr0 EAddr1 EAddr2 EAddr3 Timer interrupt 4 11H 3B8H TBR 87654123H Vector table 87654123H 000003B8H 0 1 2 3 876544DBH P Po 3 876544D8H EAddri 2 EAddr3 Note The process of referencing a vector table involves application of address alignment rules for word access 23 CHAPTER 3 REGISTER DESCRIPTIONS Table Base Register Configuration Figure 3 3 8 shows the bit configuration of the table base register Figure 3 3 8 Table Base Register Bit Configuration Bitno 31 00 Table Base Register Functions Vector Table Reference Addresses Addresses for vector reference are generated by adding the contents of the TBR register and the vector offset value which is determined by the type of interrupt used Because vector access is in word units the lower two bits of the resulting address value are explicitly read as 0 Vector Table Layout Vector table layout can be realized in word 32 bits units Initial Values in Table Base Register After a reset the initial value is 000FFCOOg Precautions Related to the Table Base Register The TBR should not be assigned values greater than FFFFFC00 If values higher than this are placed in the register the operation may result in an overflow w
128. R15 ST R13 R15 Recovery from EIT handler is changed 4 2 Basic Operations in EIT Processing M Recovery from EIT handler gt Recovery from EIT handler of 4 2 Basic Operations in EIT Processing 4 3 Interrupts is changed External User Bl Sources of Interrupts is changed External User xi Page Changes For details refer to main body 4 3 1 User Interrupts is changed External gt User external user Bl Overview of User Interrupts is changed External gt User Bl Overview of User Interrupts is changed Interrupts are referred to as external when they originate outside the CPU is deleted E Conditions for Acceptance of User Interrupt Requests is changed External User E Conditions for Acceptance of User Interrupt Requests is changed The CPU accepts interrupts The CPU accepts user interrupts Bl Operation Following Acceptance of an User Interrupt is changed External User external user E How to Use User Interrupts is changed External User external user Figure 4 3 1 How to Use User Interrupts is changed External User Table 4 6 1 Priority of EIT Requests is changed External gt User INT gt INTE B Examples of Programing Delayed Branching Instructions is changed The position of comment n
129. RUCTIONS DIV1 DIV2 Main Process of Division Correction when Remainder is 0 DIV3 Correction when Remainder is 0 DIV4S Correction Answer for Signed Division LSL Logical Shift to the Left Direction LSL Logical Shift to the Left Direction LSL2 Logical Shift to the Left Direction LSR Logical Shift to the Right Direction LSR Logical Shift to the Right Direction LSR2 Logical Shift to the Right Direction ASR Arithmetic Shift to the Right Direction ASR Arithmetic Shift to the Right Direction ASR2 Arithmetic Shift to the Right Direction LDI 32 Load Immediate 32 bit Data to Destination Register LDI 20 Load Immediate 20 bit Data to Destination Register LDI 8 Load Immediate 8 bit Data to Destination Register Load Word Data in Memory to Register Load Word Data in Memory to Register Load Word Data in Memory to Register LD LD LD LD LD Load Word Data in Memory to Register LD Load Word Data in Memory to Register Load Word Data in Memory to Register LD Load Word Data in Memory to Program Status Register LDUH Load Half word Data in Memory to Register LDUH Load Half word Data in Memory to Register LDUH LDUB LDUB Load Byte Data in Memory to Register LDUB Load Byte Data in Memory to Register ST Store Word Data in Register to Memory Load Half word Data in Memory to Register Load Byte Data in Memory to Register ST Store Word Data in Register to Memory
130. Register and Carry Bit from Destination Register Assembler format SUBC Rj Ri Operation Ri Rj C gt Ri Flag change N Set when the MSB of the operation result is 1 cleared when the MSB is 0 Z Set when the operation result is cleared otherwise Set when an overflow has occurred as a result of the operation cleared otherwise C Setwhen a borrow has occurred as a result of the operation cleared otherwise Execution cycles 1 cycle Instruction format MSB LSB 1 0 1 0 1 1 0 1 Rj Ri Example SUBC R2 R3 Instruction bit pattern 1010 1101 0010 0011 R2 1234 5678 R2 1234 5678 R3 9999 9999 R3 8765 4320 NZVC NZVC CCR 0001 CCR 1000 Before execution After execution 80 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 10 SUBN Subtract Word Data in Source Register from Destination Register Subtracts the word data in Rj from the word data in Ri stores results to Ri without changing the flag settings SUBN Subtract Word Data in Source Register from Destination Register Assembler format SUBN Rj Ri Operation Ri Rj gt Ri Flag change N Z V and C Unchanged Execution cycles 1 cycle Instruction format MSB LSB 1 0 1 0 1 1 1 0 Rj Ri Example SUBN R2 Instruction bit pattern 1010 1110 0010 0011 R2 1234 5678 R2 1234 5678
131. T Ri R13 Rj Operation Ri gt R13 Rj Flag change N Z V and C Unchanged Execution cycles a cycle s Instruction format MSB LSB Example ST R3 R13 R2 Instruction bit pattern 0001 0000 0010 0011 R2 0000 0004 R2 0000 0004 R3 8765 4321 R3 8765 4321 R13 1234 5678 R13 1234 5678 12345678 Memory 12345678 Memory 1234567C XXXX XXXX 1234567C 8765 4321 Before execution After execution 166 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 71 ST Store Word Data in Register to Memory Loads the word data in Ri to memory address R14 08 x 4 The value 08 is a signed calculation ST Store Word Data in Register to Memory Assembler format ST Ri R14 disp10 Operation Ri gt R14 08 x 4 Flag change N Z V and C Unchanged Execution cycles a cycle s Instruction format MSB LSB o o 1 1 08 Ri ST R14 4 Instruction bit pattern 0011 0000 0001 0011 R3 8765 4321 R3 8765 4321 R14 1234 5678 R14 1234 5678 12345678 Memory 12345678 Memory 1234567C XXXX XX XX 1234567C 8765 4321 Before execution After execution 167 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 72 ST Store Word Data in Register to Me
132. TER Enter Function 254 EOR EOR Exclusive Or Word Data of Source Register to Data in Memory 100 EOR Exclusive Or Word Data of Source Register to Destination Register 99 EORB EORB Exclusive Or Byte Data of Source Register to Data in Memory 104 EORH EORH Exclusive Or Half word Data of Source Register to Data in Memory 102 Error Information Saving and Restoring Coprocessor Error Information 50 Error Trap PC Values Saved for Coprocessor Error Traps 49 Conditions for Generation of Coprocessor Error Traps PU 49 Coprocessor Error Trap Operation 49 Overview of Coprocessor Error Traps 49 Results of Coprocessor Operations after a Coprocessor Trap iudi ete pepe cati 49 Exception PC Values Saved for Undefined Instruction eiie 43 Factors Causing Exception Processing 42 INDEX How to Use Undefined Instruction Exceptions 43 Operations of Undefined Instruction Exceptions 43 Overview of Exception Processing 42 Overview of Undefined Instruction Exceptions 43 Time to Start of Undefined Instruction Exception Processing eei tie 43 Exchange Byte Data XCHB Exchange Byte Data 258 E
133. TRUCTIONS 67 7 1 ADD Add Word Data of Source Register to Destination Register 72 7 2 ADD Add 4 bit Immediate Data to Destination Register 73 7 3 ADD2 Add 4 bit Immediate Data to Destination Register 74 7 4 ADDC Add Word Data of Source Register and Carry Bit to Destination Register 75 7 5 ADDN Add Word Data of Source Register to Destination Register 76 7 6 ADDN Add Immediate Data to Destination Register essem 77 7 7 ADDN Add Immediate Data to Destination Register 78 7 8 SUB Subtract Word Data in Source Register from Destination Register 79 7 9 SUBC Subtract Word Data in Source Register and Carry Bit from Destination Register 80 7 10 SUBN Subtract Word Data in Source Register from Destination Register 81 7 11 Compare Word Data in Source Register and Destination Register 82 7 12 Compare Immediate Data of Source Register and Destination Register 83 7 13 CMP2 Compare Immediate Data and Destination Register 4 04441 8 84 7 14 AND And Word Data of Source Register to Destination
134. This type of trap can be created for each individual instruction in a sequence by setting the flag in the SCR in the PS In the execution of delayed branching instructions step trace traps are not generated immediately after the execution of branching The trap is generated after execution of the instruction s in the delay slot The step trace trap can be utilized by users for systems that have not been debugged by emulators Conditions for Generation of Step Trace Traps A step trace trap is generated when the following conditions are met The T flag in the SCR in the PS is set to 1 The currently executing instruction is not a delayed branching instruction The CPU is not processing an INTE instruction or a step trace trap processing routine Step Trace Trap Operation When a step trace trap is generated the following operations take place 1 The contents of the program status PS are saved to the system stack 2 The address of the next instruction is saved to the system stack 3 The value of the system stack pointer SSP is reduced by 8 4 The value 0 is written to the S flag in the CCR in the PS 5 The value TBR 4 is stored in PC PC Values Saved for Step Trace Traps The PC value saved to the system stack represents the address of the next instruction after the step trace trap Relation of Step Trace Traps to NMI and External Interrupts When the T flag is
135. V and C Unchanged Execution cycles 1 2a cycles Instruction format MSB LSB 114 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example BEORL 1 R3 Instruction bit pattern 1001 1000 0001 0011 R3 1234 5678 R3 1234 5678 Memory Memory 12345678 00 12345678 01 12345679 12345679 NZ VC NZ VC CCR 0000 CCR 0000 Before execution After execution 115 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 34 BEORH Eor 4 bit Immediate Data to Higher 4 Bits of Byte Data in Memory Takes the logical exclusive OR of the 4 bit immediate data and the higher 4 bits of byte data at memory address Ri stores the results to the memory address corresponding to Ri The CPU will not accept hold requests between the memory read operation and the memory write operation of this request BEORH Eor 4 bit Immediate Data to Higher 4 Bits of Byte Data in Memory Assembler format BEORH u4 Ri Operation u4 lt lt 4 eor Ri Ri Operation uses higher 4 bits only Flag change N Z V and C Unchanged Execution cycles 1 2a cycles Instruction format MSB LSB 116 Example CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS BEORH 1 R3 Instruction bit pattern 1001 1001 0001 0011 R3 1234 5678 Memory 12345678 00
136. V and Unchanged Execution cycles 1 2a cycles Instruction format MSB LSB 90 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example ANDB R2 R3 Instruction bit pattern 1000 0110 0010 0011 R2 0000 0010 R2 0000 0010 R3 1234 5678 R3 1234 5678 Memor Memor y p y 12345678 11 12345678 10 12345679 12345679 NZVC NZVC CCR 0000 CCR 0000 Before execution After execution 91 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 18 Or Word Data of Source Register to Destination Register Takes the logical OR of the word data in Ri and the word data in Rj stores the results to Ri OR Or Word Data of Source Register to Destination Register Assembler format OR Hj Ri Operation Ri or Rj Ri Flag change N Set when the MSB of the operation result is 1 cleared when the MSB is 0 Z Set when the operation result is 0 cleared otherwise V and C Unchanged Execution cycles 1 cycle Instruction format MSB LSB 110 101110101110 Rj Ri Example OR R2 Instruction bit pattern 1001 0010 0010 0011 R2 11111 0000 R3 1010 1010 R3 1111 1010 NZVC NZVC CCR 0000 CCR 0000 Before execution After execution 92 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 19 OR Or Word Data of Sou
137. V xor N PC 2 rel8x2 PC if V xor N or Z PC 2 rel8x2 PC if V xor N or Z 0 PC 2 rel8x2 PC if C or Z PC 2 rel8x2 PC if C or Z 0 BNO D label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 label9 0 atm Notes The field rel8 in the TYPE D instruction format and the field rel11 in the TYPE F format have the following relation to the values label9 and 12 in assembly notation label9 rel8 label9 PC 2 2 label12 rel11 label12 PC 2 2 Delayed branching instructions are always executed after the following instruction the delay slot In order to occupy a delay slot an instruction must satisfy either of the following conditions Any other instructions used in this position may not be executed according to definition Instructions other than branching instructions with the cycle CYC column showing the value 1 Instructions with the cycle CYC column showing the value b or d 271 APPENDIX A Instruction Lists Table A 2 13 Direct Addressing Instructions 14 Instructions Mnemonic Format Operation Remarks dir10 R13 R13 dir10 dir10 R13 R13 dir10 dir10 R15 R15 dir10 DMOVH dir9 R13 DMOVH R13 dir9 DMOVH dir9 R13 DMOVH R13 dir9 DMOVB dir8 R13 DMO
138. VB dir8 DMOVB dir8 R13 DMOVB R13 dir8 dir10 R13 Word R13 dir10 Word dir10 13 13 44 Word R13 gt dir10 R13 4 Word 15 4 01 10 gt R15 Word R15 gt dirl0 R15 4 Word dir9 R13 Half word dir9 Half word dir9 R13 R13 2 Half word R13 gt dir9 R13 2 Half word dir8 R13 R13 dir8 dir8 R13 R13 R13 dir8 R13 00 0 CO Note The field dir in the TYPE D instruction format has the following relation to the values dir8 to dir10 in assembly notation dir8 dir dir8 dir9 gt dir dir9 gt gt 1 dir10 gt dir dir10 gt gt 2 Table A 2 14 Resource Instructions 2 Instructions Mnemonic Format Operation Remarks LDRES Ri 04 Ri resource u4 u4 Channel number Ri 4 STRES u4 Ri Resource u4 Ri u4 Channel number Ri 4 Mnemonic Operation Remarks COPOP u4 CC CRj CRi Designates operation COPLD u4 CC Rj CRi Rj CRi COPST u4 CC Ri gt Ri COPSV 04 CC CRJ Ri CRj gt Ri No error trap generated 272 Table A 2 16 Other Instructions 16 Instructions Mnemonic Operation No change APPENDIX A Instruction Lists Remarks CCR and u8 CCR CCR or u8 CCR g g g m u8 ILM Sets ILM immediate value R15 s10
139. ample MUL R2 R3 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS R2 R3 MDH MDL CCR 0000 0002 8000 0001 XX XX XX X X XX XX XX X X NZVC 0000 Before execution Instruction bit pattern 1010 1111 0010 0011 R2 R3 MDH MDL CCR 0000 0002 8000 0001 FFFFFFFF 0000 0002 NZVC 0010 After execution 121 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 735 MULU Multiply Unsigned Word Data Multiplies the word data in Rj by the word data in Ri as unsigned numbers and stores the resulting unsigned 64 bit data with the high word in the multiplication division register MDH and the low word in the multiplication division register MDL i MULU Multiply Unsigned Word Data Assembler format MULU Ri Operation Rj x Ri MDH MDL Flag change N Set when the MSB of the MDL of the operation result is 1 cleared when the MSB is 0 Z Set when the MDL of the operation result is 0 cleared otherwise V Cleared when the operation result is in the range 0 to 4294967295 set otherwise C Unchanged Execution cycles 5 cycles Instruction format MSB LSB 1 0 1 0 1 0 1 1 Rj Ri 122 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example MULU R2 R3 Instruction bit pattern 1010 1011 0010 0011 R2 0000 00
140. anch Relative if Condition Satisfied DMOV Move Word Data from Direct Address to Register DMOV Move Word Data from Register to Direct Address DMOV Move Word Data from Direct Address to Post Increment Register Indirect Address DMOV Move Word Data from Post Increment Register Indirect Address to Direct Address DMOV Move Word Data from Direct Address to Pre decrement Register Indirect Address DMOV Move Word Data from Post Increment Register Indirect Address to Direct Address DMOVH Move Half word Data from Direct Address to Register DMOVH Move Half word Data from Register to Direct Address DMOVH Move Half word Data from Direct Address to Post Increment Register Indirect Address DMOVH Move Half word Data from Post Increment Register Indirect Address to Direct Address 7 110 7 111 7 112 7 113 7 114 7 115 7 116 7 117 7 118 7 119 7 120 7 121 7 122 7 123 7 124 7 125 7 126 7 127 7 128 7 129 7 130 7 131 7 132 7 133 7 134 7 135 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS DMOVB Move Byte Data from Direct Address to Register DMOVB Move Byte Data from Register to Direct Address DMOVB Move Byte Data from Direct Address to Post Increment Register Indirect Address DMOVB Move Byte Data from Post Increment Register Indirect Address to Direct Address LDRES Load Word Data in Memory to Resource STRES Store Word Data in Resource to Memory COPOP Coprocessor Operation COPLD Load 32 bi
141. ata in Resource to Memory is changed Instruction bit pattern 1011 1101 1000 0010 is added 7 116 COPOP Coprocessor Operation is changed Resource Coprocessor 7 117 COPLD Load 32 bit Data from Register to Coprocessor Register is changed Resource Coprocessor 7 118 COPST Store 32 bit Data from Coprocessor Register to Register is changed Resource Coprocessor 7 119 COPSV Save 32 bit Data from Coprocessor Register to Register is changed Resource Coprocessor 7 120 NOP No Operation is changed Instruction bit pattern 1001 1111 1010 0000 is addded xvii Page Changes For details refer to main body 7 121 ANDCCR And Condition Code Register and Immediate Data is changed Instruction bit pattern 1000 0011 1111 1110 is added 7 122 ORCCR Or Condition Code Register and Immediate Data is changed Instruction bit pattern 1001 0011 0001 0000 is added 7 123 STILM Set Immediate Data to Interrupt Level Mask Register is changed Instruction bit pattern 1000 0111 0001 0100 is added 7 125 EXTSB Sign Extend from Byte Data to Word Data is changed Instruction bit pattern 1001 0111 1000 0001 is added 7 126 EXTUB Unsign Extend from Byte Data to Word Data is changed Instruction bit pattern 1001 0111 1001 0001 is changed 7 127 EXTSH Sign Extend from Byte Data to Word
142. ations When a auser interrupt or NMI is executed b step execution is implemented or c a break occurs in a data event or emulator menu due to a command just before DIV0U DIV0S commands the following operation may be implemented 1 DO and D1 flags are changed first 2 EIT process routine user interrupt NMI or emulator is executed 3 Returning from EIT DIVOU DIVOS commands are executed and DO and D1 flags are set to the same value in 1 When a user interrupt or NMI factor exists and a command such as ORCCR STILM MOV Ri PS is executed to allow an interruption the following operation is executed 1 PS register is changed first 2 EIT process routine user interrupt NMI is executed 3 Returning from EIT any above command is executed and PS register is set to the same value in 1 22 CHAPTER 3 REGISTER DESCRIPTIONS 3 3 3 Table Base Register TBR The Table Base Register TBR designates the table containing the entry address for EIT operations Overview of the Table Base Register The Table Base Register TBR designates the table containing the entry address for EIT operations When an EIT condition occurs the address of the vector reference is determined by the sum of the contents of this register and the vector offset corresponding to the EIT operation Figure 3 3 7 shows an example of the operation of the table base register Figure 3 3 7 Sample of Table Base Register TB
143. bler format ADDSP s10 Operation R15 exts s8 x 4 R15 Flag change N Z V and C Unchanged Execution cycles 1 cycle Instruction format MSB LSB Example ADDSP 4 Instruction bit pattern 1010 0011 1111 1111 R15 8000 0000 R15 7FFFFFFC Before execution After execution 241 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 125 EXTSB Sign Extend from Byte Data to Word Data Extends the byte data indicated by Ri to word data as a signed binary value EXTSB Sign Extend from Byte Data to Word Data Assembler format Operation Flag change Execution cycles Instruction format Example 242 EXTSB Ri exts Ri Ri byte word N Z V and C Unchanged 1 cycle MSB LSB EXTSB R1 Instruction bit pattern 1001 0111 1000 0001 R1 0000 00AB Before execution R1 FFFFFFAB After execution CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 126 EXTUB Unsign Extend from Byte Data to Word Data Extends the byte data indicated by Ri to word data as an unsigned binary value EXTUB Unsign Extend from Byte Data to Word Data Assembler format EXTUB Ri Operation extu Ri Ri byte word Flag change N Z V and C Unchanged Execution cycles 1 cycle
144. branching conditions are not satisfied In this example the instruction ST R2 R12 which immediately follows the branching instruction has entered the pipeline operation before the fetching of the branch destination instruction and is executed without being canceled Because instructions are executed without branching the program is processed in the order in which it is written The branching instruction requires an apparent processing time of one cycle Figure 5 4 2 Example Processing a Non delayed Branching Instruction Branching Conditions Not Satisfied LD R10 R1 IF ID EX MA WB LD R11 R2 IF ID EX MA WB ADD R1 R3 IF ID EX MA WB BNE TestOK branching conditions not satisfied IF ID EX MA WB ST R2 R12 instruction immediately after IF ID EX MA WB Not canceled ADD 4 R12 subsequent instruction IF ID EX MA WB 60 5 4 2 Processing Delayed Branching Instructions CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU The FR family CPU processes delayed branching instructions with an apparent execution speed of 1 cycle regardless of whether branching conditions are satisfied or not satisfied When branching occurs this is one cycle faster than using non delayed branching instructions However the apparent order of instruction processing is inverted in cases where branching occurs Examples of Processing Delayed Branching I
145. branching processing 59 CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU 5 4 1 Processing Non delayed Branching Instructions The FR family CPU processes non delayed branching instructions in the order in which the program is written introducing a 1 cycle delay in execution speed if branching takes place Examples of Processing Non delayed Branching Instructions Figure 5 4 1 shows an example of processing a non delayed branching instruction when branching conditions are satisfied In this example the instruction ST R2 R12 which immediately follows the branching instruction has entered the pipeline operation before the fetching of the branch destination instruction but is canceled during execution As a result the program is processed in the order in which it is written and the branching instruction requires an apparent processing time of two cycles Figure 5 4 1 Example Processing a Non delayed Branching Instruction Branching Conditions Satisfied LD R10 R1 IF ID EX MA WB LD R11 R2 IF ID EX MA WB ADD R1 R3 IF ID EX MA WB BNE TestOK branching conditions satisfied IF ID EX MA WB ST R2 R12 instruction immediately after IF ST R2 R13 branch destination instruction IF ID EX MA WB Canceled stages PC change Figure 5 4 2 shows an example of processing a non delayed branching instruction when
146. branching instruction with a delay slot If the conditions established for each particular instruction are satisfied branch to the address indicated by label9 relative to the value of the program counter PC When calculating the address double the value of rel8 as a signed extension If conditions are not satisfied no branching can occur Conditions for each instruction are listed in Table 7 99 1 Bcc D Branch Relative if Condition Satisfied Assembler format BRA D label9 BV D label9 BNO D label9 BNV D label9 BEQ D label9 BLT D label9 BNE D label9 BGE D label9 BC D label9 BLE D label9 BNC D label9 BGT D label9 BN D label9 BLS D label9 BP D label9 BHI D label9 Operation if conditions satisfied PC 2 exts rel8 x 2 PC Table 7 99 1 Branching Conditions Mnemonic Conditions Mnemonic Conditions Always satisfied V 1 Always unsatisfied 0 7 1 1 7 0 V xorN 0 C 1 or Z 1 C 0 or Z 0 N 1 7 1 N 0 7 0 Flag change N Z V and C Unchanged 203 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Execution cycles 1 cycle Instruction format MSB LSB Example BHI D label LDI 8 255 R1 Instruction placed in delay slot label BHI D instruction address 504 Instruction bit pattern 1111 1111 0010 1000 R1 894
147. cessing The FR family CPU processes all instructions through pipeline operation Therefore particularly for instructions that start hardware events it is possible for contradictory conditions to exist before and after an instruction Precautionary Information for Interrupt Processing in Pipeline Operation Because the FR family CPU operates in pipeline mode the recognition of an interrupt signal is preceded by several instructions in respective states of pipeline processing If one of those instructions being executed in the pipeline acts to delete the interrupt the CPU will branch normally to the respective interrupt processing program but when control is transferred to interrupt processing the interrupt request will no longer be effective Note that this type of condition does not occur in exception or trap processing Figure 5 2 1 Example Interrupt Accepted and Deleted Causing Mismatched Pipeline Conditions Interrupt request None None None None Generated Deleted None None None LD R10 R1 IF ID EX MA 2022204 ST R2 R11 IF ID EX ADD R1 R3 cancelled IF ID BNE TestOK cancelled IF EIT sequence execution 1 EX MA WB Canceled stages Conditions that Are Actually Generated The following processing conditions may cause an interrupt to be deleted after acceptance A program that clears interrupt sources whi
148. change N Set when the MSB of the operation result is 1 cleared when the MSB is 0 Z Set when the operation result is 0 cleared otherwise V Unchanged C Holds the bit value shifted last Cleared when the shift amount is 0 Execution cycles 1 cycle Instruction format MSB LSB 110111111101010 u4 Ri Example ASR 8 R3 Instruction bit pattern 1011 1000 1000 0011 R3 FFOFFFFF R3 FFFFOFFF NZVC NZVC CCR 0000 CCR 1001 Before execution After execution 145 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 52 ASR2 Arithmetic Shift to the Right Direction Makes an arithmetic right shift of the word data in Ri by u4 16 bits stores the result to Ri ASR2 Arithmetic Shift to the Right Direction Assembler format ASR2 u4 Ri Operation Ri gt gt u4 16 Ri Flag change N Set when the MSB of the operation result is 1 cleared when the MSB is 0 Z Set when the operation result is 0 cleared otherwise V Unchanged C Holds the bit value shifted last Execution cycles 1 cycle Instruction format MSB LSB 1101111 11 101011 u4 Ri L L L L 1 1 Example ASR2 8 R3 Instruction bit pattern 1011 1001 1000 0011 R3 FOFFFFFF gt R3 FFFFFFF0 NZ VC NZ VC CCR 0000 CCR 1001 Before execution Af
149. condition code register CCR CMP Compare Immediate Data of Source Register and Destination Register Assembler format CMP i4 Ri Operation Ri extu i4 Flag change N Set when the MSB of the operation result is 1 cleared when the MSB is 0 Z Set when the operation result is 0 cleared otherwise V Set when an overflow has occurred as a result of the operation cleared otherwise C Set when a carry has occurred as a result of the operation cleared otherwise Execution cycles 1 cycle Instruction format MSB LSB Example CMP 3 R3 Instruction bit pattern 1010 1000 0011 0011 R3 0000 0003 R3 0000 0003 NZ VC NZ VC CCR 0000 CCR 0100 Before execution After execution 83 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 713 CMP2 Compare Immediate Data and Destination Register Subtracts the result of the higher 28 bits of 4 bit immediate from 16 to 1 data with minus extension from the word data in Ri places results in the condition code register CCR CMP2 Compare Immediate Data and Destination Register Assembler format CMP2 i4 Ri Operation Ri extn i4 Flag change N Set when the MSB of the operation result is 1 cleared when the MSB is Z Set when the operation result is 0 cleared otherwise V Set when an overflow has occurred as a result of th
150. control in nuclear facility aircraft flight control air traffic control mass transport control medical life support system missile launch control in weapon system or 2 for use requiring extremely high reliability i e submersible repeater and artificial satellite Please note that FUJITSU will not be liable against you and or any third party for any claims or damages arising in connection with above mentioned uses of the products Any semiconductor devices have an inherent chance of failure You must protect against injury damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy fire protection and prevention of over current levels and other abnormal operating conditions Exportation release of any products described in this document may require necessary procedures in accordance with the regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and or US export control laws The company names and brand names herein are the trademarks or registered trademarks of their respective owners Copyright 1997 2007 FUJITSU LIMITED All rights reserved CONTENTS CHAPTER1 FR FAMILY OVERVIEW U U 1 1 1 Features of the FR Family CPU Core issues 2 1 2 Sample Configuration of an FR Family Device ss 3 1 3 Sample Configuration of the FR Family CPU 4 CHAPTER
151. cution of a RET Instruction Memory space Memory space Before execution ae After execution nd T CALL SUB1 CALL D SUB PC SUB1 ADD 1 R00 PC 1234567AH ADD 1 R00 RP 1234567AH RP 1234567AH ED ES m 25 CHAPTER 3 REGISTER DESCRIPTIONS Return Pointer Configuration Figure 3 3 11 shows the bit configuration of the return pointer Figure 3 3 11 Return Pointer Bit Configuration Bit no 21 00 Return Pointer Functions Return Pointer in Multiple CALL Instructions Because the RP does not have a stack configuration it is necessary to first execute a save when calling one subroutine from another subroutine Initial Value of Return Pointer The initial value is undefined 26 CHAPTER 3 REGISTER DESCRIPTIONS 3 3 5 System Stack Pointer SSP User Stack Pointer USP The system stack pointer SSP and user stack pointer USP are registers that refer to the stack area The S flag in the CCR determines whether the SSP or USP is used Also when an EIT event occurs the program counter PC and program status PS values are saved to the stack area designated by the SSP regardless of the value of the 5 flag at that time System Stack Pointer SSP User Stack Pointer USP The system stack pointer SSP and user stack pointer USP are po
152. d the following operations take place 1 The contents of the PS are saved to the system stack 2 The address of the next instruction is saved to the system stack 3 The value of the system stack pointer SSP is reduced by 8 4 The value 15 is written to the ILM 5 The value 0 is written to the S flag in CCR in the PS 6 The value TBR 3 is stored in the program counter Time to Start of Non maskable Interrupt Processing 40 The time required to start processing of an NMI can be expressed as a maximum of n 6 cycles from the start of the instruction currently executing when the interrupt was received where n represents the number of execution cycles in the instruction If the instruction includes memory access or insufficient instructions are present the corresponding number of wait cycles must be added CHAPTER 4 RESET AND EIT PROCESSING PC Values Saved for Non maskable Interrupts When an NMI is accepted by the processor those instructions in the pipeline that cannot be interrupted in time will be executed The remainder of the instructions will be canceled and will not be processed after the interrupt The EIT processing sequence saves PC values to the system stack representing the addresses of canceled instructions How to Use Non maskable Interrupts The following programming steps must be set up to enable the use of NMI 1 Enter values in the int
153. decimal calculation unit the coprocessor command CC set as shown in Table 7 118 1 Will have the following effect on coprocessor operation Table 7 118 1 Conditions for Coprocessor Command CC COPST Calculation Addition CRi CRj CRi Subtraction CRi CRj CRi Multiplication gt Division CRi CRj gt CRi No calculation CPU register Before execution R4 XXXX XXXX R4 BF80 0000 Coprocessor register Coprocessor register CR2 BF80 0000 CR2 BF80 0000 CPU register After execution 234 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 119 COPSV Save 32 bit Data from Coprocessor Register to Register Transfers the 16 bit data consisting of parameters CC CRj Ri to the coprocessor indicated by channel number u4 then on the next cycle loads the data output by the coprocessor to CPU general purpose register Ri Basically this operation transfers data from a register within the coprocessor The 32 bit data stored in coprocessor register CRj is transferred to CPU general purpose register Ri Note that the actual interpretation of the fields CC CRj Ri is done by the coprocessor so that the detailed actual operation is determined by the specifications of the coprocessor If the coprocessor designated by the value u4 is not mounted a coprocessor not found trap is generated However no coprocess
154. dsp Medsp odsip 64 0105 oggi 8 107 21 11 37 viu viu 106 1 619081 als HLS Hnq1 H1s a da 6leqel dg 5 AOW fy wiog 888 WILS 3 ywo 3 6leqel Hu 5 aav ais andi 6leqel Ho TH leqei 1 2161 zaav HHO HLS undi 61eqe aoa 6leqdeO8 zjjeqe 1S1 HO H9 fH 16 qi 6l qel TiO 0188 eng gng opn siH o q dspn d ANg legei sH H dsaav H20HO 16 staa 01 61eqe uero Q 038 6leqel 034 YO 815 anaq 6leqel rl n Herdo 6leqel ZAST HHO8 IH HLS 61946 aerd ty 6leqel vua HS1 IH pH 7409 iH 1S H erH 4 3 q 9 9 6 8 2 9 5 v z L 0 Sig p Lower 4 bits 275 APPENDIX B Instruction Maps B 2 E Format This section shows E format for FR family CPU mg E Format Lower 4 bits 276 Table B 2 1 E Format LD RI15 Ri Higher 8 bits ST Ri R15 JMP Ri JMP D Ri MOV Ri PS MOV PS Ri CALL Ri
155. e Data of Source Register to Data in Memory Assembler format EORB Rj Ri Operation Ri eor Rj Ri Flag change N Set when the MSB bit 7 of the operation result is 1 cleared when the MSB is 0 7 Set when the operation result is 0 cleared otherwise V and C Unchanged Execution cycles 1 2a cycles Instruction format MSB LSB 104 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example EORB R2 R3 Instruction bit pattern 1001 1110 0010 0011 R2 0000 0011 R2 0000 0011 R3 1234 5678 R3 1234 5678 Memor Memor y y 12345678 10 12345678 01 12345679 12345679 NZ VC NZ VC CCR 0000 CCR 0000 Before execution After execution 105 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 26 BANDL And 4 bit Immediate Data to Lower 4 Bits of Byte Data in Memory Takes the logical AND of the 4 bit immediate data and the lower 4 bits of byte data at memory Ri stores the results to the memory address corresponding to Ri The CPU will not accept hold requests between the memory read operation and the memory write operation of this request BANDL And 4 bit Immediate Data to Lower 4 Bits of Byte Data in Memory Assembler format BANDL u4 Ri Operation u4 and Ri Ri Operation uses lower 4 bits only Flag change N Z V and C Unchanged Execution cycles 1
156. e SCR Figure 3 3 5 Bit Configuration of the SCR 10 09 08 SCR D1 Initial value SCR Functions Bits D1 DO Bits D1 DO are used for intermediate data in stepwise division calculations This register is used to assure resumption of division calculations when the stepwise division program is interrupted during processing If changes are made to the contents of this register during division processing the results of the division are not assured T bit The T bit is a step trace trap flag When this bit is set to 1 step trace trap operation is enabled Note Step trace trap processing routines cannot be debugged using emulators Initialization of the SCR at Reset The values of bits D1 DO are undefined and the T bit is set to 0 20 CHAPTER 3 REGISTER DESCRIPTIONS Condition Code Register CCR Bit 07 to bit 00 Bit Configuration of the CCR Figure 3 3 6 Bit Configuration of the CCR 05 04 03 CCR z Initial value 00XXXXB 07 06 02 01 00 CCR Functions MGN Flag This flag selects the stack pointer to be used The value 0 selects the system stack pointer SSP and 1 selects the user stack pointer USP RETI instruction is executable only when the S flag is 0 Flag This flag is used to enable disable system interrupts The value 0 disables and 1 enables interrupts N Flag This flag is used to indicate positive o
157. e memory address corresponding to Ri The CPU will not accept hold requests between the memory read operation and the memory write operation of this request BORH Or 4 bit Immediate Data to Higher 4 Bits of Byte Data in Memory Assembler format BORH 444 Ri Operation u4 lt lt 4 or Ri Ri Operation uses higher 4 bits only Flag change N Z V and C Unchanged Execution cycles 1 2 cycles Instruction format 112 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example BORH 1 R3 Instruction bit pattern 1001 0001 0001 0011 R3 1234 5678 R3 1234 5678 Memor Memor y p y 12345678 00 12345678 1 0 12345679 12345679 NZVC NZVC CCR 0000 CCR 0000 Before execution After execution 113 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 30 BEORL Eor 4 bit Immediate Data to Lower 4 Bits of Byte Data in Memory Takes the logical exclusive OR of the 4 bit immediate data and the lower 4 bits of byte data at memory address Ri stores the results to the memory address corresponding to Ri The CPU will not accept hold requests between the memory read operation and the memory write operation of this request BEORL Eor 4 bit Immediate Data to Lower 4 Bits of Byte Data in Memory Assembler format BEORL u4 Ri Operation u4 eor Ri Ri Operation uses lower 4 bits only Flag change N Z
158. e operation cleared otherwise C Set when a carry has occurred as a result of the operation cleared otherwise Execution cycles 1 cycle Instruction format MSB LSB 1 1 1 1 i4 Ri Example CMP2 3 R3 Instruction bit pattern 1010 1001 1101 0011 R3 FFFFFFFD R3 FFFFFFFD NZVC NZVC CCR 0000 CCR 0100 Before execution After execution 84 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 14 AND And Word Data of Source Register to Destination Register Takes the logical AND of the word data in Rj and the word data in Ri stores the results to Ri AND And Word Data of Source Register to Destination Register Assembler format AND Ri Ri Operation Ri and Rj Ri Flag change N Set when the MSB of the operation result is 1 cleared when the MSB is 0 Z Set when the operation result is 0 cleared otherwise V and Unchanged Execution cycles 1 cycle Instruction format MSB LSB 110101010101 1 0 Rj Ri Example AND R2 R3 Instruction bit pattern 1000 0010 0010 0011 R2 1111 0000 FE 8200 R3 1010 1010 R3 1010 0000 NZ VC NZVC CCR 0000 CCR 0000 Before execution After execution 85 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 15 AND And Word Data of Source Register to Data in Memory Takes the logical AND of th
159. e word data at memory address Ri and the word data in Rj stores the results to the memory address corresponding to Ri The CPU will not accept hold requests between the memory read operation and the memory write operation of this request AND And Word Data of Source Register to Data in Memory Assembler format AND Rj Ri Operation Ri and Rj Ri Flag change N Set when the MSB of the operation result is 1 cleared when the MSB is 0 Z Set when the operation result is 0 cleared otherwise V and Unchanged Execution cycles 1 2a cycles Instruction format MSB LSB 86 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example AND R2 R3 Instruction bit pattern 1000 0100 0010 0011 R2 1111 0000 R2 1111 0000 R3 1234 5678 R3 1234 5678 Memory Memory 12345678 1010 1010 12345678 10100000 1234567C 1234567C NZVC NZVC CCR 0000 CCR 0000 Before execution After execution CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 16 And Half word Data of Source Register to Data in Memory Takes the logical AND of the half word data at memory address Ri and the half word data in Rj stores the results to the memory address corresponding to Ri The CPU will not accept hold requests between the memory read operation and the memory write operation of this request ANDH And Half word Data of Source Register t
160. errupt for Emulator 190 Interrupts during Execution of Stepwise Division 37 Operation Following Acceptance of a Non maskable Interr pt aasan qu un 40 Operation Following Acceptance of an User Interrupt 38 Overview of Interrupt Processing 37 Overview of Non maskable Interrupts 40 Overview of User Interrupts 38 Precautionary Information for Interrupt Processing in Pipeline Operation 55 Relation of Step Trace Traps to NMI and External Intert pts 24 netiis 47 Restrictions on Interrupts during Processing of Delayed Branching Instructions 59 RETI Return from Interrupt 192 Sources of Interrupts eee 37 Time to Start of Interrupt Processing 39 Time to Start of Non maskable Interrupt Processing a ad 40 Interrupt Level Mask Register Interrupt Level Mask Register ILM Bit 20 to bit 16 19 STILM Set Immediate to Interrupt Level Mask Register iuret tener 240 INDEX J JMP JMP Jump seid cidade eadein terit 184 JMP D Qu rd e oreet 196 Jump IMP JUMP een 184 L LD LD Load Word Data in Memory to Program Status MP 157 LD Load Word Data in Memory to Register CIS 150 151 152 153 154 155 LDI LDI 20 Load Immediate 20 bit
161. errupt vector table defined as data 2 Set up the SSP values 3 Setup TBR values 4 Set up the appropriate value in the ILM field in the PS 41 CHAPTER 4 RESET AND EIT PROCESSING 4 4 Exception Processing Exceptions originate from within the instruction sequence Exceptions are processed by first saving the necessary information to resume the currently executing instruction and then starting the processing routine corresponding to the type of exception that has occurred Overview of Exception Processing Exceptions originate from within the instruction sequence Exceptions are processed by first saving the necessary information to resume the currently executing instruction and then starting the processing routine corresponding to the type of exception that has occurred Branching to the exception processing routine takes place before execution of the instruction that has caused the exception The address of the instruction in which the exception occurs becomes the program counter PC value that is saved to the stack Factors Causing Exception Processing The factor which causes the exception processing is the undefined instruction exception For details see 4 4 1 Undefined Instruction Exceptions 42 CHAPTER 4 RESET AND EIT PROCESSING 4 4 1 Undefined Instruction Exceptions Undefined instruction exceptions are caused by attempts to execute instruction codes that are not defined This
162. es of processing delayed branching instructions both when branching conditions are satisfied and not satisfied are described in Section 5 4 2 Processing Delayed Branching Instructions Instructions Prohibited in Delay Slots 58 The following instructions may not be used in delayed branching processing by the FR family CPU LDI 32 132 Ri LDI 20 20 Ri e COPOP u4 CC CRi COPLD u4 CC Rj CRi COPST u4 CC CRj Ri COPSV u4 CC CRj Ri JMP Ri CALL label12 CALL Ri RET Conditional branching instruction and related delayed branching instructions INT u8 RETI INTE CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU AND Rj Rj GRi ANDB Rj OR Rj GRi ORH Rj Ri ORB Rj Ri EOR Rj EORH Rj EORB Rj BANDH 04 Ri BANDL 04 Ri Ri BORL u4 Ri BEORH 04 Ri BEORL 04 Ri BTSTH Ri BTSTL Ri MUL Rj Ri MULU Rj Ri RjRi MULUH Rj Ri LD R15 PS LDMO reglist LDM1 reglist STM0 reglist STMI reglist ENTER 010 XCHB Q Rj Ri e DMOV QGdir10 R13 DMOV R13 dir10 DMOV dir10 R15 DMOV RIS dir10 DMOVH dir9 R13 DMOVH R13 dir9 DMOVB dir8 R13 DMOVB R13 dir8 Restrictions on Interrupts during Processing of Delayed Branching Instructions EIT processing is not accepted during execution of delayed branching instructions or delayed
163. et Priority Level Resets have a higher priority than all EIT operations 33 CHAPTER 4 RESET AND EIT PROCESSING 4 2 Basic Operations in EIT Processing Interrupts exceptions and traps are similar operations applied under partially differing conditions Each EIT event involves terminating the execution of instructions saving information for restarting and branching to a designated processing program Basic Operations in EIT Processing The FR family device processes EIT events as follows 1 The vector table indicated by the table base register TBR and the number corresponding to the particular EIT event are used to determine the entry address for the processing program for the EIT 2 For restarting purposes the contents of the old program counter PC and the old program status PS are saved to the stack area designated by the system stack pointer SSP 3 After the processing flow is completed the presence of new EIT sources is determined Figure 4 2 1 shows the operations in the EIT processing sequence Figure 4 2 1 EIT Processing Sequence Instruction at which EIT event is detected IF ID EX MA WB Canceled instruction IF ID xxxx xxxx xxxx Canceled instruction 1 Vector address calculation and new PC setting ID 1 1 1 1 EIT sequence 2 SS
164. ew of the Table Base Register 23 Precautions Related to the Table Base Register 24 STILM Set Immediate Data to Interrupt Level Mask Register aet ener 240 System Condition Code Register SCR Bit 10 to eie seite tob rr 20 Table Base Register Configuration 24 Table Base Register Functions 24 Register Bypassing Register Bypassing 56 Register Hazards Overview of Register Hazards 56 Remainder DIV2 Correction when Remainder is 0 134 Correction when Remainder is O 136 Reset Initialization of CPU Internal Register Values at Reset 33 Reset Operations 22222 2 33 Reset Priority Level eese 33 Restoring Saving and Restoring Coprocessor Error Information 50 Restrictions Data Restrictions on Word Alignment 11 Program Restrictions on Word Alignment 11 Restrictions on Interrupts during Processing of Delayed Branching Instructions 59 RET RET Return from Subroutine 187 RET D Return from Subroutine 201 RETI RETI Return from Interrupt 192 Return Pointer Overview of the Return Pointer 25 Return Pointer Co
165. f the table base register TBR is initialized to 000 so that the vector table area is between addresses and 000FFFFFq CHAPTER 2 MEMORY ARCHITECTURE 2 2 Bit Order and Byte Order This section describes the order in which three types of data 8 16 and 32 bits are placed in the memory in the FR family In the FR family the bit number increases approaching the MSB and the byte number increases approaching the lowest address value Bit Order and Byte Order Bit order in the general purpose register is that the larger numbers are placed in the vicinity of the MSB while the smaller numbers are near the LSB Byte order configuration requires the upper data to be placed in the smaller address memory while the lower data are placed in the larger address memory Figure 2 2 1 illustrates the bit order and byte order in the FR family Figure 2 2 1 Bit Order and Byte Order Bitorder 31 2423 1615 87 0 Memory space RO 12H 34H 56H 78H 0000 0000H 1234 5678H LD R10 RO 1234 5679H 1234 567AH 1234 567BH FFFFFFFFH T R10 12345678 CHAPTER 2 MEMORY ARCHITECTURE 2 3 Word Alignment In the FR family the type of data length used determines restrictions on the designation of memory addresses word alignment Program Restrictions on Word Alignment When using half word instruction length memory addresses must
166. fer it increments the value of R13 by 1 DMOVB Move Byte Data from Post Increment Register Indirect Address to Direct Address Assembler format DMOVB R13 dir8 Operation R13 dir8 R13 1 R13 Flag change N Z V and C Unchanged Execution cycles 2a cycles Instruction format MSB LSB oo o 1 4 141 o dir8 225 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example 226 DMOVB R13 57H Instruction bit pattern 0001 1110 0101 0111 R13 FF80 1220 Memory 00000057 FF801220 5 5 FF801221 Before execution R13 FF80 1221 Memory 00000057 5 5 FF801220 5 5 FF801221 X X After execution CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 114 LDRES Load Word Data in Memory to Resource Transfers the word data at the address indicated by Ri to the resource on channel u4 Increments the value of Ri by 4 LDRES Load Word Data in Memory to Resource Assembler format LDRES Ri u4 Operation Ri Resource on channel u4 Ri 4 Ri Flag change N Z V and C Unchanged Execution cycles a cycle s Instruction format MSB LSB 1 0 1 1 41 u4 Ri Example LDRES R2 8 Instruction bit pattern 1011 1100 1000 0010 R2 1234 5678 R2 1234
167. fined Instruction Exceptions The following programming steps must be set up to enable the use of undefined instruction exceptions 1 Enter values in the interrupt vector table defined as data 2 Set up the SSP value 3 Setup TBR value Undefined Instructions Placed in Delay Slots Undefined instructions placed in delay slots do not generate undefined instruction exceptions In such cases undefined instructions have the same operation as NOP instructions 43 CHAPTER 4 RESET AND EIT PROCESSING 4 5 Traps Traps originate from within the instruction sequence Traps are processed by first saving the necessary information to resume processing from the next instruction in the sequence and then starting the processing routine corresponding to the type of trap that has occurred Sources of traps include the following INT instructions INTE instructions Step trace traps Coprocessor not found traps Coprocessor error traps 44 Overview of Traps Traps originate from within the instruction sequence Traps are processed by first saving the necessary information to resume processing from the next instruction in the sequence and then starting the processing routine corresponding to the type of trap that has occurred Branching to the exception processing routine takes place after execution of the instruction that has caused the exception The address of the instruction in which the exception occurs becomes the
168. ftware Interrupt 188 Overview of the INT Instruction 45 Precautionary Information for Use of INT Instructions 45 Time to Start of Trap Processing for INT Instructions 45 INTE INTE Instruction Operation 46 PC Values Saved for INTE Instruction Execution 46 INTE Software Interrupt for Emulator 190 Overview of the INTE Instruction 46 Precautionary Information for Use of INTE INSUPUCHONS si u eet 46 Time to Start of Trap Processing for INTE INSTTUCUIONS L uu t A 46 Interlocking Interlocking Permet 57 Interlocking Produced by Reference to R15 and General purpose Registers after Changing the S Flag usun aun yanin 57 Interrupt PC Values Saved for Interrupts 39 PC Values Saved for Non maskable Interrupts akin EU M EET don a JD a i 41 Conditions for Acceptance of Non maskable Interrupt Requests eere ness eroi nop Un 40 Conditions for Acceptance of User Interrupt Requests eda Dea rie eu dod 38 How to Use Non maskable Interrupts 41 How to Use User Interrupts 39 INT Software Interrupt 188 INTE Software Int
169. ght Direction Assembler format LSR u4 Ri Operation Ri gt gt u4 gt Ri Flag change N Set when the MSB of the operation result is 1 cleared when the MSB is 0 Z Setwhen the operation result is 0 cleared otherwise V Unchanged C Holds the bit value shifted last Cleared when the shift amount is O Execution cycles 1 cycle Instruction format MSB LSB 1 0 1 1 u4 Ri Example LSR 8 R3 Instruction bit pattern 1011 0000 1000 0011 R3 FFFFFFFF gt R3 OOFF FFFF NZVC NZVC CCR 0000 CCR 0001 Before execution After execution 142 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 49 LSR2 Logical Shift to the Right Direction Makes a logical right shift of the word data in Ri by u4 16 bits stores the result to Ri LSR2 Logical Shift to the Right Direction Assembler format Operation Flag change Execution cycles Instruction format Example LSR2 u4 Ri Ri gt gt u4 16 gt Ri N Cleared Z Set when the operation result is 0 cleared otherwise V Unchanged C Holds the bit value shifted last 1 cycle MSB LSB 110111110 01 011 u4 Ri LSR2 8 R3 Instruction bit pattern 1011 0001 1000 0011 R3 FFFFFFFF gt NZVC CCR 0000 Before execution R3 CCR
170. hen summed with the offset value An overflow condition will result in vector access to the area 00000000 to 000003 which can cause program runaway 24 CHAPTER 3 REGISTER DESCRIPTIONS 3 3 4 Return Pointer RP The return pointer RP is a register used to contain the program counter PC value during execution of call instructions in order to assure return to the correct address after the call instruction has executed Overview of the Return Pointer The contents of the return pointer RP depend on the type of instruction For a call instruction with a delay slot the value is the address stored 4 and for a call instruction with no delay slot the value is the address stored 2 The save data is returned from the RP pointer to the PC counter by execution of a RET instruction Figure 3 3 9 shows a sample operation of the RP pointer in the execution of a CALL instruction with no delay slot and Figure 3 3 10 shows a sample operation of the RP pointer in the execution of a RET instruction Figure 3 3 9 Sample Operation of RP in Execution of a CALL Instruction with No Delay Slot Memory space Memory space Before execution TONY space After execution FO space PC 12345678H CALL SUB1 D PC SUB1 CALL SUB1 i RP 2222222 RP 1234567AH ei 1 Figure 3 3 10 Sample Operation of RP in Exe
171. i CRj CRi Subtraction CRi CRi 02 Multiplication CRi x CRj CRi 03 Division CRi CRj CRi Other No calculation CPU register CPU register R4 XXXX XXXX R4 4000 0000 Coprocessor register Coprocessor register CR2 4000 0000 CR2 4000 0000 Before execution After execution CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 120 NOP No Operation This instruction performs no operation NOP No Operation Assembler format NOP Operation This instruction performs no operation Flag change N Z V and C Unchanged Execution cycles 1 cycle Instruction format MSB LSB Example NOP Instruction bit pattern 1001 1111 1010 0000 PC 8343 834A PC 8343 834C Before execution After execution 237 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 121 ANDCCR And Condition Code Register and Immediate Data Takes the logical AND of the byte data in the condition code register CCR and the immediate data and returns the results into the CCR ANDCCR And Condition Code Register and Immediate Data Assembler format u8 Operation CCR and u8 CCR Flag change 5 I N Z V and C Varies according to results of calculation E
172. immediate data coprocessor instructions 5 stage pipeline configuration for basic instructions one instruction one cycle execution 32 bit by 32 bit computation enables completion of multiplication instructions within five cycles Stepwise division instructions enable 32 bit 32 bit division Direct addressing instructions for peripheral circuit access Coprocessor instructions for direct designation of peripheral accelerator High speed interrupt processing complete within 6 cycles CHAPTER 1 FR FAMILY OVERVIEW 1 2 Sample Configuration of an FR Family Device FR family devices have block configuration with bus connections between individual modules This enables module connections to be altered as necessary to accommodate a wide variety of functional configurations Figure 1 2 1 shows an example of the configuration of an FR family device Sample Configuration of an FR Family Device Figure 1 2 1 Sample Configuration of an FR Family Device 1 1 1
173. inters that refer to the stack area The stack area is accessed by instructions that use general purpose register R15 as an indirect register as well as register multi transfer instructions R15 is used as an indirect register by the SSP when the S flag in the condition code register CCR is 0 and the USP when the S flag is 1 Also when an EIT event occurs the program counter PC and program status PS values are saved to the stack area designated by the SSP regardless of the value of the S flag at that time Figure 3 3 12 shows an example of stack pointer operation in executing the instruction ST R13 R15 when the S flag is set to 0 Figure 3 3 13 shows an example of the same operation when the S flag is set to 1 Figure 3 3 12 Example of Stack Pointer Operation in Execution of Instruction ST R13 R15 when S Flag 0 Before execution of ST R13 R15 After execution of ST R13 R15 Memory space Memory space r 00000000H 4 00000000 4 22222222 SSP 12345674H 17263540H USP 76543210H R13 17263540H R13 17263540H L FEFFFFFFH 5 L SSP 12345678 297 USP 76543210H CCR 27 CHAPTER 3 REGISTER DESCRIPTIONS Figure 3 3 13 Example of Stack Pointer Operation in Execution of Instruction ST R13 R15 when S Flag 1 Before execution of ST R13 R15 Afte
174. ion of this request ORH Or Half word Data of Source Register to Data in Memory Assembler format ORH Rj Ri Operation Ri or Rj Ri Flag change N Set when the MSB bit 15 of the operation result is 1 cleared when the MSB is 0 Z Set when the operation result is 0 cleared otherwise V and C Unchanged Execution cycles 1 2a cycles Instruction format MSB LSB 95 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example ORH R2 R3 Instruction bit pattern 1001 0101 0010 0011 R2 0000 1100 R2 0000 1100 R3 1234 5678 R3 1234 5678 Memory Memory 12345678 1010 12345678 1110 1234567A 1234567A NZ VC NZ VC CCR 0000 CCR 0000 Before execution After execution 96 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 721 ORB Or Byte Data of Source Register to Data in Memory Takes the logical OR of the byte data at memory address Ri and the byte data in Rj stores the results to the memory address corresponding to Ri The CPU will not accept hold requests between the memory read operation and the memory write operation of this request ORB Or Byte Data of Source Register to Data in Memory Assembler format ORB Rj Ri Operation Ri or Rj Ri Flag change N Set when the MSB bit 7 of the operation result is 1 cleared when the MSB is 0 7 Set when operation resu
175. is extended with zeros and transferred to Ri The CPU will not accept hold requests between the memory read operation and the memory write operation of this instruction XCHB Exchange Byte Data Assembler format XCHB Ri Ri Operation Ri TEMP extu Rj gt Ri TEMP gt Rj Flag change N Z V and C Unchanged Execution cycles 2a cycles Instruction format MSB LSB 258 Example XCHB R1 R0 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Instruction bit pattern 1000 1010 0001 0000 RO 0000 0078 R1 8000 0002 80000001 80000002 80000003 Memory X X F D X X Before execution RO 0000 00FD R1 8000 0002 80000001 80000002 80000003 Memory X X 78 X X After execution 259 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 260 APPENDIX The appendix section includes lists of CPU instructions used in the FR family as well as instruction map diagrams APPENDIX A Instruction Lists APPENDIX B Instruction Maps 261 APPENDIX A Instruction Lists APPENDIX A Instruction Lists Appendix A includes a description of symbols used in instruction lists plus the instruction lists A 1 Symbols Used in Instruction Lists A 2 Instruction Lists 262 APPENDIX A Instruction Lists A 1 Symbols Used in Instruction Lists This sectio
176. ister Assembler format LDUB R14 disp8 Ri Operation extu R14 08 Ri Flag change N Z V and C Unchanged Execution cycles b cycle s Instruction format MSB LSB o 141 0 o8 m Ri Example LDUB R14 1 R3 Instruction bit pattern 0110 0000 0001 0011 R3 x x x x X X X X R3 0000 0021 R14 1234 5678 R14 1234 5678 12345678 Memor 12345678 Memor y p y 12345679 21 12345679 21 Before execution After execution 164 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 69 ST Store Word Data in Register to Memory Loads the word data in Ri to memory address Rj ST Store Word Data in Register to Memory Assembler format ST Ri Rj Operation Ri Rj Flag change N Z V and C Unchanged Execution cycles a cycle s Instruction format MSB LSB Example ST R3 R2 Instruction bit pattern 0001 0100 0010 0011 R2 1234 5678 R2 1234 5678 R3 8765 4321 R3 8765 4321 Memory Memory 2 12345678 XXXX X XX X 12345678 8765 4321 Before execution After execution 165 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 70 ST Store Word Data in Register to Memory Loads the word data Ri to memory address R13 Rj ST Store Word Data in Register to Memory Assembler format S
177. ister Assembler format MOV Ri PS Operation Ri PS Flag change N Z V and C Data is transferred from Ri Execution cycles c cycle s The number of execution cycles is normally 1 However if the instruction immediately after involves read or write access to memory address R15 the system stack pointer SSP or the user stack pointer USP then an interlock is applied and the value becomes 2 cycles Instruction format MSB LSB 1 1 1 Ri 182 Example MOV R3 PS CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS R3 PS FFF3F8D5 X XXX XX XX Before execution Instruction bit pattern 0000 0111 0001 0011 R3 PS FFF3 F8D5 FFF3 F8D5 After execution 183 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 87 JMP Jump This is a branching instruction with no delay slot Branches to the address indicated by Ri B JMP Jump Assembler format JMP Ri Operation Ri 2 PC Flag change N Z V and C Unchanged Execution cycles 2 cycles Instruction format MSB LSB Example JMP R1 R1 PC Instruction bit pattern 1001 0111 0000 0001 C000 8000 FF80 0000 Before execution R1 PC 0000 C000 8000 After execution 184
178. it Immediate Data to Destination Register Adds the result of the higher 28 bits of 4 bit immediate data with minus extension to the word data in Ri stores results to Ri The way a C flag of this instruction varies is the same as the ADD instruction it is different from that of the SUB instruction ADD2 Add 4 bit Immediate Data to Destination Register Assembler format ADD2 i4 Ri Operation Ri extn i4 gt Ri Flag change Set when the MSB of the operation result is 1 cleared when the MSB is 0 Z Set when the operation result is 0 cleared otherwise V Set when an overflow has occurred as a result of the operation cleared otherwise C Set when a carry has occurred as a result of the operation cleared otherwise Execution cycles 1 cycle Instruction format MSB LSB Example ADD2 2 R3 Instruction bit pattern 1010 0101 1110 0011 R3 9999 9999 R3 9999 9997 NZ VC NZVC CCR 0000 CCR 1001 Before execution After execution 74 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 4 ADDC Add Word Data of Source Register and Carry Bit to Destination Register Adds the word data in Rj to the word data in Ri and carry bit stores results to Ri ADDC Add Word Data of Source Register and Carry Bit to Destination Register Assembler format ADDC Rj Ri Operation Ri Rj
179. le in interrupt enabled mode Writing to an interrupt enable bit in a peripheral function while in interrupt enabled mode How to Avoid Mismatched Pipeline Conditions To avoid deleting interrupts that have already been accepted programmers should use the I flag in the condition code register CCR in the program status PS to regulate interrupt sources 55 CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU 5 3 Register Hazards The FR family CPU executes program steps in the order in which they are written and is therefore equipped with a function that detects the occurrence of register hazards and stops pipeline processing when necessary This enables programs to be written without attention to the order in which registers are used Overview of Register Hazards The CPU in pipeline operation may simultaneously process one instruction that involves writing values to a register and a subsequent instruction that attempts to refer to the same register before the write process is completed This is called a register hazard In the example in Figure 5 3 1 the program will read the address value at R1 before the desired value has been written to R1 by the previous instruction As a result the old value at R1 will be read instead of the new value Figure 5 3 1 Example of a Register Hazard ADD RO R1 Write cycle to R1 SUB R1 R2 Read cycle from R1 Register Bypassi
180. lt is cleared otherwise V and C Unchanged Execution cycles 1 2a cycles Instruction format MSB LSB 97 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example 98 ORB R2 R3 Instruction bit pattern 1001 0110 0010 0011 R3 1234 5678 R2 0000 0011 Memory 12345678 10 12345679 NZVC CCR 0000 Before execution R2 0000 0011 R3 1234 5678 Memory 12345678 11 12345679 NZVC CCR 0000 After execution CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 22 EOR Exclusive Or Word Data of Source Register to Destination Register Takes the logical exclusive OR of the word data in Ri and the word data in Rj stores the results to Ri EOR Exclusive Or Word Data of Source Register to Destination Register Assembler format EOR Rj Ri Operation Ri eor Rj Ri Flag change N Set when the MSB of the operation result is 1 cleared when the MSB is 0 Z Set when the operation result is 0 cleared otherwise V and Unchanged Execution cycles 1 cycle Instruction format MSB LSB 1 1 Rj Ri Example EOR R2 R3 Instruction bit pattern 1001 1010 0010 0011 R2 1111 0000 R2 1111 0000 R3 1010 1010 R3 0101 1010 NZ VC NZVC CCR 0000 CCR 0000 Before execution After execution 99 CH
181. lt of the operation cleared otherwise C Set when a carry has occurred as a result of the operation cleared otherwise 1 cycle MSB LSB 1 0 1 0 0 1 1 0 Rj Ri ADD R2 R3 Instruction bit pattern 1010 0110 0010 0011 R2 1234 5678 R2 1234 5678 R3 8765 4321 R3 9999 9999 NZVC NZVC CCR 0000 CCR 1000 Before execution After execution CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 2 ADD Add 4 bit Immediate Data to Destination Register Adds the result of the higher 28 bits of 4 bit immediate data with zero extension to the word data in Ri stores results to the Ri m ADD Add 4 bit Immediate Data to Destination Register Assembler format ADD i4 Ri Operation Ri extu i4 Ri Flag change Set when the MSB of the operation result is 1 cleared when the MSB is 0 Z Set when the operation result is 0 cleared otherwise Set when an overflow has occurred as a result of the operation cleared otherwise C Set when a carry has occurred as a result of the operation cleared otherwise Execution cycles 1 cycle Instruction format MSB LSB 1101110101110 0 i4 Ri 1 1 1 1 1 1 Example ADD 2 R3 Instruction bit pattern 1010 0100 0010 0011 R3 9999 9997 R3 9999 9999 NZVC NZVC CCR 0000 CCR 1000 Before execution After execution 73 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 3 ADD2 Add 4 b
182. mory Loads the word data in Ri to memory address R15 u4 x 4 The value u4 is an unsigned calculation ST Store Word Data in Register to Memory ST Ri R15 udisp6 Assembler format Operation Flag change Execution cycles Instruction format Example 168 Ri gt R15 u4 x 4 N Z V and C Unchanged a cycle s MSB LSB ST R3 Q R15 4 R3 R15 12345678 1234567C Instruction bit pattern 0001 0011 0001 0011 8765 4321 1234 5678 Memory X XXX XX XX Before execution R3 R15 12345678 1234567C 8765 4321 1234 5678 Memory 8765 4321 After execution CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 773 ST Store Word Data in Register to Memory Subtracts 4 from the value of R15 stores the word data in Ri to the memory address indicated by the new value of R15 If R15 is given as the parameter Ri the data transfer will use the value of R15 before subtraction ST Store Word Data in Register to Memory Assembler format Ri R15 Operation R15 4 R15 Ri gt R15 Flag change N Z V and C Unchanged Execution cycles a cycle s Instruction format MSB LSB Example ST R15 Instruction bit pattern 0001 0111 0
183. n 0 1 0 0 1 1 1 1 1 1 1 0 1 u4 n 2 CC Rj CRi 231 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example COPLD 15 4 R8 CR1 16 bit data is transferred through the bus to the coprocessor indicated by channel number 15 Next the contents of general purpose register R8 are transferred through the bus to that coprocessor Assuming that the coprocessor indicated by channel 15 is a single precision floating decimal calculation unit the coprocessor command CC set as shown in Table 7 117 1 will have the following effect on coprocessor operation Table 7 117 1 Conditions for Coprocessor Command CC COPLD Calculation Addition CRi CRj CRi Subtraction CRi CRj CRi Multiplication CRi x CRj CRi Division CRj gt CRi No calculation CPU register Before execution CPU register R8 3F80 0000 R8 3F80 0000 Coprocessor register Coprocessor register CR1 XXXX CR1 3F80 0000 After execution 232 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 118 COPST Store 32 bit Data from Coprocessor Register to Register Transfers the 16 bit data consisting of parameters CC CRj Ri to the coprocessor indicated by channel number u4 then on the next cycle loads the data output by the coprocessor into CPU general purpose
184. n describes symbols used in the FR family instruction lists Symbols Used in Instruction Lists Symbols in Mnemonic and Operation Columns 14 4 bit immediate data range 0 to 15 with zero extension and 16 to 1 with minus extension unsigned 8 bit immediate data range 0 to 255 12O ies unsigned 20 bit immediate data range 000004 to FFFFFy 13255153 unsigned 32 bit immediate data range 000000004 to FFFFFFFF y SS esee signed 8 bit immediate data range 128 to 127 810 signed 10 bit immediate data range 512 to 508 multiples of 4 u4 unsigned 4 bit immediate data range 0 to 15 US 5 unsigned 8 bit immediate data range 0 to 255 ulO unsigned 10 bit immediate data range 0 to 1020 multiples of 4 udisp6 unsigned 6 bit address values range 0 to 60 multiples of 4 disp8 signed 8 bit address values range 0 80 to Ox7F disp9 signed 9 bit address values range 0x100 to OxFE multiples of 2 disp10 signed 10 bit address values range 0x200 to 0x1FC multiples of 4 dir8 unsigned 8 bit address values range 0 to 0xFF dir9 unsigned 9 bit address values range 0 to 0x1FE multiples of 2 dir10 unsigned 10 bit address values range 0 to Ox3FC multiples of 4 label9 signed 9 bit branch address range 0x100 to OxFE multiples of 2 for the value of PC labell12 signed 12 bit branch address range 0x800 to Ox
185. ned Instruction Exceptions ntt 43 Pipeline How to Avoid Mismatched Pipeline Conditions 55 Overview of Pipeline Operation 54 Precautionary Information for Interrupt Processing in Pipeline Operation 55 Priority Priority of Multiple Processes 52 Priority of Simultaneous Occurrences 51 Reset Priority Level 33 Program Counter Overview of the Program Counter 18 Program Counter Functions 18 Program Status Register LD Load Word Data in Memory to Program Status Register 157 Move Word Data in Program Status Register to Destination Register 180 MOV Move Word Data in Source Register to Program Status Register 182 Overview of Program Status Register 19 Program Status Register Configuration 19 ST Store Word Data in Program Status Register to Memory 171 Unused Bits in the Program Status Register 19 PS Register Note on PS Register 22 R Register Configuration of the MD Register 30 285 INDEX Interrupt Level Mask Register ILM Bit 20 to bit 16 19 LD Load Word Data Memory to Program Status Register meine 157 Note on PS Register 22 Overview of the Multiplication Division Register nS 29 Overvi
186. nfiguration 26 Return Pointer Functions 26 Right Direction ASR Arithmetic Shift to the Right Direction 144 145 ASR2 Arithmetic Shift to the Right Direction 286 S Sample Sample Configuration of an FR Family Device 3 Sample Configuration of the FR Family CPU 4 Save COPSV Save 32 bit Data from Coprocessor Register to Register dee pne 235 Saving Saving and Restoring Coprocessor Error Information EP 50 SCR System Condition Code Register SCR Bit 10 to bit 08 iouis ier itte etes 20 Set Immediate Data STILM Set Immediate Data to Interrupt Level Mask Re ister a eee qe tees 240 Sign Extend EXTSB Sign Extend from Byte Data to Word Data EE 242 EXTSH Sign Extend from Byte Data to Word Data eco 244 Signed Division DIVOS Initial Setting Up for Signed Division uqa ade dede 128 DIVAS Correction Answer for Signed Division 137 Simultaneous Occurrences Priority of Simultaneous Occurrences 51 Software Interrupt INT Software Interrupt 188 INTE Software Interrupt for Emulator 190 Source Register ADD Add Word Data of Source Register to Destination Register 72 ADDC Add Word Data of Source Register and Carry Bit to Destination Register 75 ADDN Add Word Data of Source Register t
187. ng Even when a register hazard does occur it is possible to process instructions without operating delays if the data intended for the register to be accessed can be extricated from the preceding instruction This type of data transfer processing is called register bypassing and the FR family CPU is equipped with a register bypass function In the example in Figure 5 3 2 instead of reading the R1 in the ID stage of the SUB instruction the program uses the results of the calculation from the EX stage of the ADD instruction before the results are written to the register and thus executes the instruction without delay Figure 5 3 2 Example of a Register Bypass ADD RO R1 IF ID WB Data calculation cycle to R1 SUB R1 R2 IF EX MA WB Read cycle from R1 56 Interlocking CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU Instructions which are relatively slow in loading data to the CPU may cause register hazards that cannot be handled by register bypassing In the example in Figure 5 3 3 data required for the ID stage of the SUB instruction must be loaded to the CPU in the MA stage of the LD instruction creating a hazard that cannot be avoided by the bypass function Figure 5 3 3 Example Register Hazard that Cannot be Avoided by Bypassing LD RO R1 IF ID EX MA WB SUB R1 R2 IF ID EX
188. nstructions Figure 5 4 3 shows an example of processing a delayed branching instruction when branching conditions are satisfied In this example the branch destination instruction ST R2 R13 is executed after the instruction ST R2 R12 in the delay slot As a result the branching instruction has an apparent execution speed of one cycle However the instruction ST R2 9R12 in the delay slot is executed before the branch destination instruction ST R2 G R13 and therefore the apparent order of processing is inverted Figure 5 4 3 Example Processing a Delayed Branching Instruction Branching Condition Satisfied LD R10 R1 IF ID EX MA WB LD R11 R2 IF ID EX MA WB ADD R1 R3 IF ID EX MA WB BNE D TestOK branching conditions satisfied IF ID EX MA WB ST R2 R12 delay slot instruction IF ID EX MA WB Not canceled ST R2 R13 branch destination instruction IF ID EX MA WB PC change Figure 5 4 4 shows an example of processing a delayed branching instruction when branching conditions are not satisfied In this example the delay slot instruction ST R2 R12 is executed without being canceled As a result the program is processed in the order in which it is written The branching instruction requires an apparent processing time of one cycle Figure 5 4 4 Example Processing a Delayed Branching Instruction Branching Conditions Not Satisfied
189. o Destination 76 AND And Word Data of Source Register to Data in 86 AND And Word Data of Source Register to Destination Register 85 ANDB And Byte Data of Source Register to Data in Metnory iiiter denne 90 ANDH And Half word Data of Source Register to Data in Memory 88 CMP Compare Immediate Data of Source Register and Destination 83 CMP Compare Word Data in Source Register and Destination 82 EOR Exclusive Or Word Data of Source Register to Data in Memory 100 EOR Exclusive Or Word Data of Source Register to Destination 99 EORB Exclusive Or Byte Data of Source Register to Data in Memory 104 EORH Exclusive Or Half word Data of Source Register to Data in Memory 102 MOV Move Word Data in Source Register to Destination Register 178 179 181 MOV Move Word Data in Source Register to Program Status Register 182 OR Or Word Data of Source Register to Data in Memory EE 93 OR Or Word Data of Source Register to Destination Register 92 ORB Or Byte Data of Source Register to Data in Memory inibi ttti 97 ORH Or Half word Data
190. o Data in Memory Assembler format Rj Operation Ri and Rj Ri Flag change N Set when the MSB bit 15 of the operation result is 1 cleared when the MSB is 0 7 Set when the operation result is 0 cleared otherwise V and C Unchanged Execution cycles 1 2a cycles Instruction format MSB LSB 88 Example CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS ANDH R2 R3 R2 R3 Instruction bit pattern 1000 0101 0010 0011 0000 1100 1234 5678 12345678 1010 1234567A CCR Memory p NZ VC 0000 Before execution R2 0000 1100 R3 1234 5678 Memory 12345678 1000 1234567A NZ VC CCR 0000 After execution 89 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 17 ANDB And Byte Data of Source Register to Data in Memory Takes the logical AND of the byte data at memory address Ri and the byte data in Rj stores the results to the memory address corresponding to Ri The CPU will not accept hold requests between the memory read operation and the memory write operation of this request ANDB And Byte Data of Source Register to Data in Memory Assembler format ANDB Ri Operation Ri and Rj Ri Flag change N Set when the MSB bit 7 of the operation result is 1 cleared when the MSB is 0 Z Set when the operation result is 0 cleared otherwise
191. o OF C 99 1 2a Ri u4 lt lt 4 O Higher 4 bit operation BTSTL 04 Ri 04 0 to C 88 2 a 0C Ri amp u4 Lower 4 bit test 5 04 Ri 04 0 to C 89 2 a Ri amp u4 lt lt 4 Higher 4 bit test 266 Table A 2 5 Multiply Divide Instructions 10 Instructions Mnemonic APPENDIX A Instruction Lists Operation Rj x Ri gt MDH MDL Rj x Ri MDH MDL Rj x Ri gt MDL Rj x Ri gt MDL Remarks 32bits x 32bits 64bits Unsigned 16bits x 16bits 32bits Unsigned i i Format Q m Un Operation Ri lt lt Rj Ri Ri lt lt u4 gt Ri Ri lt lt u4 16 Ri Step operation 32bits 32bits 32bits Remarks Logical shift Ri gt gt Rj Ri Ri gt gt u4 gt Ri Ri gt gt u4 16 Ri Logical shift OOP jasa ml a ja pu Ri gt gt Rj Ri Ri gt gt u4 Ri Ri gt gt u4 16 gt Ri Arithmetic shift Table A 2 7 Immediate Data Transfer Instructions Immediate Transfer Instructions for Immediate Value Set or 16 bit or 32 bit Values 3 Instructions FLAG LDI 32 132 Ri 2s 8 JHES S LDI 20 20 LDI 8 8 Ri Higher 12 bits are zeros Higher 24 bits are zeros 267 APPENDIX A Instruction Lists Table A 2 8 Memory Load Instructions 13 Instructions Mnemonic Ri
192. occur during stepwise division programs intermediate data is placed in the program status PS and saved to the stack Therefore if the interrupt processing program overwrites the contents of the PS data in the stack the processor will resume executing the stepwise division instruction following the completion of interrupt processing however the results of the division calculation will be incorrect 37 CHAPTER 4 RESET AND EIT PROCESSING 4 3 1 User Interrupts User interrupts originate as requests from peripheral circuits Each interrupt request is assigned an interrupt level and it is possible to mask requests according to their level values This section describes conditions for acceptance of user interrupts as well as their operation and uses Overview of User Interrupts User interrupts originate as requests from peripheral circuits Each interrupt request is assigned an interrupt level and it is possible to mask requests according to their level values Also it is possible to disable all interrupts by using the I flag in the condition code register CCR in the program status PS It is possible to enter an interrupt signal through a signal pin but in virtually all cases the interrupt originates from the peripheral circuits contained on the FR family microcontroller chip itself Conditions for Acceptance of User Interrupt Requests The CPU accepts user interrupts when the following conditions are
193. of Source Register to Data in 95 SUB Subtract Word Data in Source Register from Destination Register 79 SUBC Subtract Word Data in Source Register and Carry Bit from Destination Register 80 SUBN Subtract Word Data in Source Register from Destination Register 81 SSP System Stack Pointer SSP User Stack Pointer USP 27 ST ST Store Word Data in Program Status Register to Memory 171 ST Store Word Data in Register to Memory 165 166 167 168 169 170 Stack Pointer Functions of the System Stack Pointer and User Stack a ga Sua a eee a eee 28 Relation between R15 and Stack Pointer 16 Stack Pointer Configuration 28 System Stack Pointer SSP User Stack Pointer USP 27 STB STB Store Byte Data in Register to Memory 175 176 177 Step Trace PC Values Saved for Step Trace Traps 47 Conditions for Generation of Step Trace Traps 47 Overview of Step Trace Traps 47 Precautionary Information for Use of Step Trace Traps EE 47 Relation of Step Trace Traps to NMI and External Intefr pts 47 Step Trace Trap Operation 47 Stepwise Division Programs Interrupts during Execution of Stepwise Division Progratns te
194. on After branching The instruction placed in the delay slot will be executed before execution of the branch destination instruction The value above will vary according to the specifications of the LDI 8 instruction placed in the delay slot 200 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 98 RET D Return from Subroutine This is a branching instruction with a delay slot Branches to the address indicated by the RP RET D Return from Subroutine Assembler format RET D Operation RP 5 PC Flag change N Z V and C Unchanged Execution cycles 1 cycle Instruction format MSB LSB 201 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example RET D MOV RO R1 Instruction placed in delay slot Instruction bit pattern 1001 1111 0010 0000 RO 00112233 RO 0011 2233 R1 X X X X X X X X R1 0011 2233 PC FFF08820 PC 8000 86 RP 8000 AE86 RP 8ooo AE86 Before execution of RET instruction After branching The instruction placed in the delay slot will be executed before execution of the branch destination instruction The value R1 above will vary according to the specifications of the MOV instruction placed in the delay slot 202 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 99 Bcc D Branch Relative if Condition Satisfied This is a
195. one cycle many instructions that would require several cycles in other methods of processing The FR family CPU simultaneously executes five types IF ID EX MA and WB of processing cycles as shown in Figure 5 1 1 This is referred to as five stage pipeline processing IF Load instruction ID Interpret instruction EX Execute instruction MA Memory access WB Write to register Figure 5 1 1 Example of Pipeline Operation in the FR Family CPU 1 cycle 0 0 9 wc 6 LD R10 R1 IF ID EX WB x LD R11 R2 IF ID EX MA WB ADD R1 IF ID EX MA WB BNE D TestOK IF EX MA WB ST R2 R12 IF ID EX MA WB Processes occurring in each 1 cycle in the above example 1 2 3 4 5 Load instruction LD R10 R1 Interpret instruction LD R10 R1 Load instruction LD R11 R2 Execute instruction LD R10 R1 Interpret instruction LD R11 R2 Load instruction ADD R1 R3 Memory access instruction LD R10 R1 Execute instruction LD R11 R2 Interpret instruction ADD Load instruction BNE D TestOK Write instruction LD R10 R1 to register Memory access instruction LD R11 R2 Execute instruction ADD R3 Interpret instruction BNE D TestOK Load instruction ST R2 R12 54 CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU 5 2 Pipeline Operation and Interrupt Pro
196. ons for each instruction are listed in Table 7 94 1 Bcc Branch Relative if Condition Satisfied Assembler format BRA label9 BV label9 BNO label9 BNV label9 BEQ label9 BLT label9 BNE label9 BGE label9 BC label9 BLE label9 BNC label9 label9 BN label9 BLS label9 BP label9 BHI label9 Operation if conditions satisfied PC 2 exts rel8 x 2 PC Table 7 94 1 Branching Conditions Mnemonic Conditions Mnemonic Conditions Always satisfied V 1 Always unsatisfied V 0 Z 1 V xorN 1 Z 0 V xorN 0 1 V N or Z 1 C 0 V xor N or Z 0 N 1 CorZ 1 N 0 CorZ 0 Flag change N Z V and C Unchanged 194 Execution cycles Instruction format Example Branch 2 cycles Not branch 1 cycle MSB LSB 1 1 1 0 cc rel8 BHI label label BHI instruction address 504 Instruction bit pattern 1110 1111 0010 1000 PC FF80 0000 p PC FF80 0052 NZVC NZVC CCR 1010 CCR 1010 Z or C 0 conditions satisfied Before execution After execution CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 195 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 95 JMP D Jump This branching instruction has a delay slot Branches to the address indicated by Ri B JMP D Jump Assembler format JMP D Operation Ri PC Flag change N Z
197. or Table Areas A vector table is composed of entry addresses for each of the EIT processing programs Each table contains some values whose use is fixed according to the CPU architecture and some that vary according to the types of built in peripheral circuits present Table 2 1 1 shows the structure of a vector table area Table 2 1 1 Structure of a Vector Table Area Offset from TBR 000 Model dependent EIT value description INT 0FF Remarks 0044 INT amp 0FE 2F8y 41H No System reserved 2FCH 40H No System reserved 33CH 30H No INT 0304 3404 2 Yes INT or IR31 Values will increase 3444 2 Yes INT 02E or IR30 towards higher limits INT 0101 or IROO INT 00F or NMI when using over 32 source extension Refer to Users Manual T for each model Undefined instruction exception Emulator exception Step trace break trap Operand break trap Instruction break trap Emulator exception 3DCH 08H No INT 008 or coprocessor error trap 07 No ud 0074 or coprocessor not found rap 3E4y 06 No System reserved Do not use OH Yes System reserved or Mode Vector Merer to ore ManualTor each model Reset Even when the TBR value is changed the reset vector remains the fixed address OOOFFFFC Vector Table Area Initial Value After a reset the value o
198. or condition Hidden error condition Coprocessor CPU C C No notification C O main COPOP COPST Interrupt RETI CPU dispatcher C m 2 e CHAPTER 4 RESET AND EIT PROCESSING 4 6 Priority Levels When multiple EIT requests occur at the same time priority levels are used to select one source and execute the corresponding EIT sequence After the EIT sequence is completed EIT request detection is applied again to enable processing of multiple EIT requests Acceptance of certain types of EIT requests can mask other factors In such cases the priority applied by the EIT processing handler may not match the priority of the requests Priority of Simultaneous Occurrences The FR family uses a hardware function to determine the priority of acceptance of EIT requests Table 4 6 1 shows the priority levels of EIT requests Table 4 6 1 Priority of EIT Requests Priority Masking of other sources Reset Other sources discarded Undefined instruction exception Other sources disabled INT instruction I flag 0 Coprocessor not found trap None Coprocessor error trap User interrupt ILM level of source accepted NMI ILM 15 Step trace trap ILM 4 INTE instruction ILM 4 51 CHAPTER 4 RESET AND EIT PROCESSING Priority of Multiple Processes When the acceptance of an EIT source results in the masking of other sources the priority of
199. or error trap will be generated even if the coprocessor designated by the value u4 has generated an error in a previous operation The operation of this instruction is basically identical to COPST except for the above difference in the operation of the error trap COPSV Save 32 bit Data from Coprocessor Register to Register Assembler format u4 CC Ri Operation CC CRj Ri gt Coprocessor on channel u4 Ri Flag change N Z V and C Unchanged Execution cycles 1 2a cycles Instruction format MSB LSB n 0 1 01011 1 1 1 1 1 1 1 1 u4 n 2 CRj Ri 235 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example 236 COPSV 15 4 CR2 R4 16 bit data is transferred through the bus to the coprocessor indicated by channel number 15 Next the data output by the coprocessor is loaded into the CPU through the data bus Note that no coprocessor error trap will be generated even if the coprocessor designated by the value u4 has generated an error in a previous operation Assuming that the coprocessor indicated by channel 15 is a single precision floating decimal calculation unit the coprocessor command CC set as shown in Table 7 119 1 will have the following effect on coprocessor operation Table 7 119 1 Conditions for Coprocessor Command CC COPSV Calculation Addition CR
200. or execution of COPSV instructions Conditions for Generation of Coprocessor Error Traps A coprocessor error trap is generated when the following conditions are met An error has occurred in coprocessor operation A COPOP COPLD COPST instruction is executed involving the same coprocessor Coprocessor Error Trap Operation When a coprocessor error trap is generated the following operations take place 1 The contents of the program status PS are saved to the system stack 2 The address of the next instruction is saved to the system stack 3 The value of the system stack pointer SSP is reduced by 8 4 The value 0 is written to the S flag in the condition code register CCR in the PS 5 The value TBR 30 is stored in PC PC Values Saved for Coprocessor Error Traps The PC value saved to the system stack represents the address of the next instruction after the coprocessor instruction that caused the trap Results of Coprocessor Operations after Coprocessor Error Trap Despite the occurrence of a coprocessor error trap the execution of the coprocessor instruction COPOP COPLD COPST remains valid and the results of the instruction are retained Note that the results of operations affected by the coprocessor error will not be correct 49 CHAPTER 4 RESET AND EIT PROCESSING Saving and Restoring Coprocessor Error Information When a coprocessor is used in a multi tasking environment
201. ory reas crai aa Reno e nage Rua 118 Bypassing Register Bypassing 56 Byte Order Bit Order and Byte Order 10 CALL CALL Call Subroutine 185 186 CALL D Call Subroutine 197 199 Carry Bit ADDC Add Word Data of Source Register and Carry Bit to Destination Register 75 SUBC Subtract Word Data in Source Register and Carry Bit from Destination Register 80 CCR Condition Code Register CCR Bit 07 to bit 00 tre fan du 21 CMP CMP Compare Immediate Data of Source Register and Destination Register 83 CMP Compare Word Data in Source Register and Destination Register 82 CMP2 Compare Immediate Data and Destination Register 84 Compare Immediate Data CMP Compare Immediate Data of Source Register and Destination Register 83 CMP2 Compare Immediate Data and Destination Register rette etre q 84 Compare Word Data CMP Compare Word Data in Source Register and Destination Register 82 Condition Code Register Condition Code Register CCR Bit 07 to bit 00 INDEX COPLD COPLD Load 32 bit Data from Register to Coprocessor Register 231 COPOP COPOP Coprocessor Operation
202. ot satisfy is changed 2 gt R13 Calculations are designated by a mnemonic placed between operand 1 and operand 2 with the results stored at operand 2 is changed The position of R2 is changed 7 1 ADD Add Word Data of Source Register to Destination Register is changed Instruction bit pattern 1010 0110 0010 0011 is added 7 4 ADDC Add Word Data of Source Register and Carry Bit to Destination Register is changed Instruction bit pattern 1010 0111 0010 0011 is added 7 8 SUB Subtract Word Data in Source Register from Destination Register is changed Instruction bit pattern 1010 1100 0010 0011 is added 7 9 SUBC Subtract Word Data in Source Register and Carry Bit from Destination Register is changed Instruction bit pattern 1010 1101 0010 0011 is added 7 10 SUBN Subtract Word Data in Source Register from Destination Register is changed Instruction bit pattern 1010 1110 0010 0011 is added 7 11 CMP Compare Word Data in Source Register and Destination Register is changed Instruction bit pattern 1010 1010 0010 0011 is added 7 14 AND And Word Data of Source Register to Destination Register is changed Instruction bit pattern 1000 0010 0010 0011 is added xii Page Changes For details refer to main body 7 15 AND And Word Data of Source Register to Data in Memory is changed Instruction bit pattern 10
203. perand Information Contained Instructions 7 OR OR Or Word Data of Source Register to Data in Memory deh 93 OR Or Word Data of Source Register to Destination R ister PAT de are 92 Or Byte Data ORB Or Byte Data of Source Register to Data in MEM OLY ara Cuypicyusqespacasasqapassasqassapaka 97 Or Condition Code ORCCR Or Condition Code Register and Immediate Data cs aaa eles 239 Or Half word Data ORH Or Half word Data of Source Register to Data in Memory ua qasaqa gt 95 Or Word Data OR Or Word Data of Source Register to Data in Memory intr insanis 93 Or Word Data of Source Register to Destination Register iere 92 ORB ORB Or Byte Data of Source Register to Data in INDEX ORCCR ORCCR Or Condition Code Register and Immediate Dat S has 239 ORH ORH Or Half word Data of Source Register to Data 1n Memory ie 95 P PC PC Values Saved for INT Instruction Execution 45 PC Values Saved for INTE Instruction Execution 46 Values Saved for Coprocessor Error Traps 49 Values Saved for Coprocessor Not Present Traps 48 PC Values Saved for Interrupts 39 PC Values Saved for Non maskable Interrupts ini 41 Values Saved for Step Trace Traps 47 PC Values Saved for Undefi
204. r Rs to general purpose register Ri If the number of a non existent dedicated register is given as Rs undefined data will be transferred MOV Move Word Data in Source Register to Destination Register Assembler format MOV Rs Ri Operation Rs Ri Flag change N Z V and C Unchanged Execution cycles 1 cycle Instruction format MSB LSB 0 011 1 1 Rs Ri Example MOV MDL R3 Instruction bit pattern 1011 0111 0101 0011 R3 XXXX R3 8765 4321 MDL 8765 4321 MDL 8765 4321 Before execution After execution 179 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 84 MOV Move Word Data in Program Status Register to Destination Register Moves the word data in the program status PS to general purpose register Ri MOV Move Word Data in Program Status Register to Destination Register Assembler format Operation Flag change Execution cycles Instruction format Example 180 MOV PS Ri PS gt Ri N Z V and C Unchanged 1 cycle 1 1 1 Ri MOV PS R3 Instruction bit pattern 0001 0111 0001 0011 R3 X X X X X X X X R3 FFF8F8CO0 PS FFF8F8CO0 PS FFF8F8CO0 Before execution After execution CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
205. r 2 digits representing higher 8 bits of OP code next digit representing 4 bit SUB OP code last digit 0 Format type F 2 digit hexadecimal code representing higher 5 bits of OP code remainder 0 Cycle CYC Column Numerical values represent machine cycles variables a through d have a minimum value of 1 FLAG Column LEE vem lisses Memory access cycles may be increased by Ready function Memory access cycles may be increased by Ready function Note that if the next instruction references a register involved in a LD operation an interlock will be applied increasing the number of execution cycles from 1 cycle to 2 cycles If the instruction immediately after is a read or write operation involving register R15 or the SSP or USP pointers or the instruction format is TYPE A an interlock will be applied increasing the number of execution cycles from 1 cycle to 2 cycles If the instruction immediately after references MDH MDL register interlock will be applied increasing the number of execution cycles from 1 cycle to 2 cycles When dedicated register such as TBR RP USP SSP MDH and MDL is accessed with ST Rs R15 command just after DIVI command an interlock is always brought increasing the number of execution cycles from 1 cycle to 2 cycles varies according to results of operation no change value becomes 0 value becomes 1 APPENDIX A Instruc
206. r Instructions Other Instructions 7 1 ADD Add Word Data of Source Register to Destination Register 7 2 ADD Add 4 bit Immediate Data to Destination Register 7 8 ADD2 Add 4 bit Immediate Data to Destination Register 67 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 68 7 4 7 5 7 6 7 7 7 8 7 9 7 10 7 11 7 12 7 13 7 14 7 15 7 16 7 17 7 18 7 19 7 20 7 21 7 22 7 23 7 24 7 25 7 26 7 27 7 28 7 29 7 30 7 31 7 32 7 33 7 34 7 35 7 36 7 37 7 38 7 39 ADDC ADDN ADDN Add Immediate Data to Destination Register ADDN2 Add Immediate Data to Destination Register Add Word Data of Source Register and Carry Bit to Destination Register Add Word Data of Source Register to Destination Register SUB Subtract Word Data in Source Register from Destination Register SUBC Subtract Word Data in Source Register and Carry Bit from Destination Register SUBN Subtract Word Data in Source Register from Destination Register CMP Compare Word Data in Source Register and Destination Register CMP Compare Immediate Data of Source Register and Destination Register CMP2 Compare Immediate Data and Destination Register AND And Word Data of Source Register to Destination Register AND And Word Data of Source Register to Data in Memory ANDH And Half word Data of Source Register to Data in Memory ANDB And Byte Data of Source Register to Data in Memory OR Or Word Data of Source Register to Destination Register
207. r execution of ST R13 R15 Memory space Memory space r 00000000H 4 00000000H SSP 12345678H 17263540H use zoom R13 17263540H SSP 12345678H USP 76543210H R13 17263540H L FFFFFFFFH 4 DEN CCR L FFFFFFFFH CCR Stack Pointer Configuration Figure 3 3 14 shows the bit configuration of the stack pointer Figure 3 3 14 Bit Configuration of the Stack Pointers Bitno 31 00 SSP USP Functions of the System Stack Pointer and User Stack Pointer Automatic increment decrement of stack pointer The stack pointer uses automatic pre decrement post increment counting Stack Pointer Initial Value The SSP has the initial value 000000004 The USP initial value is undefined Recovery from EIT handler When RETI instruction is used for recovery from an EIT handler it is necessary to set the S flag to 0 and select the system stack For further details see Recovery from EIT handler of 4 2 Basic Operations in EIT Processing 28 CHAPTER 3 REGISTER DESCRIPTIONS 3 3 6 Multiplication Division Register MD The multiplication division register MD is a 64 bit register used to contain the result of multiplication operations as well as the dividend and result of division operations Overview of the Multiplication Division Register The multiplication division register MD
208. r insufficient instructions are present the corresponding number of wait cycles must be added PC Values Saved for Interrupts When an interrupt is accepted by the processor those instructions in the pipeline that cannot be interrupted in time will be executed The remainder of the instructions will be canceled and will not be processed after the interrupt The EIT processing sequence saves PC values to the system stack representing the addresses of canceled instructions How to Use User Interrupts The following programming steps must be set up to enable the use of user interrupts Figure 4 3 1 illustrates the use of user interrupts Figure 4 3 1 How to Use User Interrupts FR family CPU SSP USP Interrupt 2 controller PS ILM 5 else ICR n lt enable bit Peripheral device Interrupt Comparator Internal bus 1 Enter values in the interrupt vector table defined as data 2 Set up the SSP values 3 Set up the table base register TBR values 4 Within the interrupt controller enter the appropriate level for the ICR corresponding to interrupts from the peripheral from which the interrupt will originate 5 Initialize the peripheral function that requests the occurrence of the interrupt and enable its interrupt function 6 Set up the app
209. r negative values when the results of a calculation are expressed in two s complement form The value 0 indicates positive and 1 indicates negative 7 Flag This flag indicates whether the results of a calculations are zero The value 0 indicates a non zero value and 1 indicates a zero value Flag This flag indicates that an overflow occurred when the results of a calculation are expressed in two s complement form The value 0 indicates no overflow and 1 indicates an overflow Flag This flag indicates whether a carry or borrow condition has occurred in the highest bit of the results of a calculation The value 0 indicates no carry or borrow and 1 indicates a carry or borrow condition This bit is also used with shift instructions and contains the value of the last bit that is shifted out Initialization of the CCR at Reset Following a reset the S and I flags are set to 0 and the N Z V and C flags are undefined 21 CHAPTER 3 REGISTER DESCRIPTIONS Note on PS Register Because of prior processing of the PS register by some commands a break may be brought in an interrupt processing subroutine during the use of a debugger or flag display content in the PS register may be changed with the following exceptional operations In both cases right re processing is designed to execute after returning from the EIT So operations before and after EIT are performed conforming to the specific
210. r8 1 1 1 217 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example 218 DMOVH 88H R13 Instruction bit pattern 0000 1101 0100 0100 R13 FF00 0052 Memory 00000088 1374 000052 X X X X FF000054 X XX X Before execution R13 FFO00 0054 Memory 00000088 1374 000052 1374 000054 X X X X After execution CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 109 DMOVH Move Half word Data from Post Increment Register Indirect Address to Direct Address Transfers the half word data at the address indicated by R13 to the direct address corresponding to 2 times the value dir8 After the data transfer it increments the value of R13 by 2 DMOVH Move Half word Data from Post Increment Register Indirect Address to Direct Address Assembler format DMOVH R13 dir9 Operation R13 dir8 x 2 R13 2 R13 Flag change N Z V and C Unchanged Execution cycles 2a cycles Instruction format MSB LSB 219 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example 220 DMOVH R13 52H Instruction bit pattern 0001 1101 0010 1001 R13 FF80 1220 Memory 00000052 XXXX FF801220 8933 FF801222 XXXX Before execution R13 FF80 1222 Memory 00000052 8933 FF801220 89
211. rce Register to Data in Memory Takes the logical OR of the word data at memory address Ri and the word data in Rj stores the results to the memory address corresponding to Ri The CPU will not accept hold requests between the memory read operation and the memory write operation of this request OR Or Word Data of Source Register to Data in Memory Assembler format OR Rj Ri Operation Ri or Rj Ri Flag change N Set when the MSB of the operation result is 1 cleared when the MSB is 0 7 Set when operation result is cleared otherwise V and C Unchanged Execution cycles 1 2a cycles Instruction format MSB LSB 93 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example OR R2 R3 Instruction bit pattern 1001 0100 0010 0011 R2 1111 0000 R2 1111 0000 R3 1234 5678 R3 1234 5678 Memory D Memory 12345678 1010 1010 12345678 1111 1010 1234567C 1234567C NZVC NZVC CCR 0000 CCR 0000 Before execution After execution 94 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 20 ORH Or Half word Data of Source Register to Data in Memory Takes the logical OR of the half word data at memory address Ri and the half word data in Rj stores the results to the memory address corresponding to Ri The CPU will not accept hold requests between the memory read operation and the memory write operat
212. rd Data from Direct Address to Pre decrement Register Indirect Address Decrements the value of R15 by 4 then transfers word data at the direct address corresponding to 4 times the value of dir8 to the address indicated in R15 DMOV Move Word Data from Direct Address to Pre decrement Register Indirect Address Assembler format DMOV dir10 R15 Operation R15 4 gt R15 dir8 x 4 R15 Flag change N Z V and C Unchanged Execution cycles 2a cycles Instruction format 211 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example 212 DMOV 2CH R15 Instruction bit pattern 0000 1011 0000 1011 R15 0000002C 7FFFFF84 7FFFFF88 7FFFFF88 Memory 82 282 9 X XXX XX XX X XXX XX X X R15 0000002C 7FFFFF84 7FFFFF88 7FFFFF84 Memory 82 282 9 82 282 9 XX XX X X X X After execution Before execution CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 105 DMOV Move Word Data from Post Increment Register Indirect Address to Direct Address Transfers the word data at the address indicated in R15 to the direct address corresponding to 4 times the value dir8 After the data transfer it increments the value of R15 by 4 DMOV Move Word Data from Post Increment Register Indirect Address to Direct Address Assembler format DMOV R15 dir
213. re Byte Data in Register to Memory n 177 vii 7 82 7 83 7 84 7 85 7 86 7 87 7 88 7 89 7 90 7 91 7 92 7 93 7 94 7 95 7 96 7 97 7 98 7 99 7 100 7 101 7 102 7 103 7 104 7 105 7 106 7 107 7 108 7 109 7 110 7 111 7 112 7 113 7 114 7 115 7 116 7 117 7 118 7 119 7 120 7 121 7 122 MOV Move Word Data in Source Register to Destination Register 178 MOV Move Word Data in Source Register to Destination Register 179 MOV Move Word Data in Program Status Register to Destination Register 180 MOV Move Word Data in Source Register to Destination Register 181 MOV Move Word Data in Source Register to Program Status Register 182 JMEP SUID a PA nt saree as 184 CALE Gall Subroutine ie eevee i ee p dee ee ee 185 CALL Call Subroutin aid ahi e tete Eee A a es 186 RET Return from Subroutine sienne 187 INT Software Interrupt n angu le eec ttl 188 INTE Software Interrupt for Emulator ss 190 RETI Return from Interrupt 192 Bcc Branch Relative if Condition Satisfied
214. rks of their respective owners Organization of this manual This manual consists of the following 7 chapters and 1 appendix CHAPTER 1 FR FAMILY OVERVIEW This chapter describes the features of the FR FAMILY CPU core and provides sample configurations CHAPTER 2 MEMORY ARCHITECTURE This chapter describes memory space in the FR family CPU CHAPTER 3 REGISTER DESCRIPTIONS This chapter describes the registers used in the FR family CPU CHAPTER 4 RESET AND EIT PROCESSING This chapter describes reset and EIT processing in the FR family CPU CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU This chapter presents precautionary information related to the use of the FR family CPU CHAPTER 6 INSTRUCTION OVERVIEW This chapter presents an overview of the instructions used with the FR family CPU CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS This chapter presents each of the execution instructions used by the FR family assembler in reference format APPENDIX The appendix section includes lists of CPU instructions used in the FR family as well as instruction map diagrams The contents of this document are subject to change without notice Customers are advised to consult with sales representatives before ordering The information such as descriptions of function and application circuit examples in this document are presented solely for the purpose of reference to show examples of operations and uses of FUJITSU semiconductor device
215. ropriate value in the ILM field in the PS 7 Set the I flag to 1 39 CHAPTER 4 RESET AND EIT PROCESSING 4 3 2 Non maskable Interrupts NMI Non maskable interrupts NMI are interrupts that cannot be masked NMI requests can be produced when NMI external signal pin input to the microcontroller is active This section describes conditions for the acceptance of NMI interrupts as well as their operation and uses Overview of Non maskable Interrupts Non maskable interrupts NMI are interrupts that cannot be masked NMI requests can be produced when NMI external signal pin input to the microcontroller is active Non maskable interrupts cannot be disabled by the I flag in the condition code register CCR in the program status PS The masking function of the interrupt level mask register ILM in the PS is valid for NMI However it is not possible to use the software input to set ILM values for masking of NMI so that these interrupts cannot be masked by programming Conditions for Acceptance of Non maskable Interrupt Requests The FR family CPU will accept an NMI request when the following conditions are met if NMI Pin Input is Active Innormal operation Detection of a negative signal edge In stop mode Detection of an L level signal if the ILM Value is Greater than 15 Operation Following Acceptance of a Non maskable Interrupt When an NMI is accepte
216. ruction in which the trap occurred 31 CHAPTER 4 RESET AND EIT PROCESSING 32 4 1 Reset Processing 4 2 Basic Operations in ElT Processing 4 3 Interrupts 4 4 Exception Processing 4 5 Traps 4 6 Priority Levels CHAPTER 4 RESET AND EIT PROCESSING 4 1 Reset Processing A reset is a means of forcibly terminating the currently executing process initializing the entire device and restarting the program from the beginning Resets are used to start the LSI operating from its initial state as well as to recover from error conditions Reset Operations When a reset is applied the CPU terminates processing of the instruction executing at that time and goes into inactive status until the reset is canceled When the reset is canceled the CPU initializes all internal registers and starts execution beginning with the program indicated by the new value of the program counter PC Initialization of CPU Internal Register Values at Reset When a reset is applied the FR family CPU initializes internal registers to the following values si PC Word data stored at address ILM 011118 TFlag 0 trace OFF IFlag 0 interrupt disabled S Flag 0 use SSP pointer TBR OOOFFC00 SSP 00000000 ROOto R14 Undefined RIS SSP For a description of built in functions following a reset refer to the Hardware Manual provided with each FR family device Res
217. ry Assembler format ST PS R15 Operation R15 4 R15 PS 5 R15 Flag change N Z V and C Unchanged Execution cycles a cycle s Instruction format MSB LSB 0 1 0 1 1 1 10 0 41 0 0 010 Example ST PS R15 Instruction bit pattern 0001 0111 1001 0000 R15 1234 5678 R15 1234 5674 PS FFF8F8CO PS FFF8F8CO 12345670 Memory 12345670 Memory 12345674 Xx XXX XX XX 12345674 FFF8F8CO0 Before execution After execution 171 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 76 STH Store Half word Data in Register to Memory Stores the half word data in Ri to memory address Rj STH Store Half word Data in Register to Memory Assembler format STH Ri Rj Operation Ri Rj Flag change N Z V and C Unchanged Execution cycles a cycle s Instruction format MSB LSB Example STH R3 R2 Instruction bit pattern 0001 0101 0010 0011 R2 1234 5678 R2 1234 5678 R3 0000 4321 R3 0000 4321 Memory Memory 12345678 X X X X 12345678 4321 Before execution After execution 172 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 77 STH Store Half word Data in Register to Memory Stores the half word data Ri to memory address R13 Rj STH Store
218. s tente podes 43 Overview of Branching with Delayed Branching Instructions 58 Overview of Branching with Non delayed Branching Instructions 58 Overview of the INT Instruction 45 Overview of the INTE Instruction 46 Overview of Undefined Instruction Exceptions 43 Precautionary Information for Use of INT Instructions 45 Precautionary Information for Use of INTE Instructions 2 Ren 46 Restrictions on Interrupts during Processing of Delayed Branching Instructions 59 Symbols Used in Instruction Lists 263 Time to Start of Trap Processing for INT Instructions La 45 Time to Start of Trap Processing for INTE Instructions la eee 46 Time to Start of Undefined Instruction Exception PLOCESSIN Bis te nine 43 Undefined Instructions Placed in Delay Slots 43 Use of Operand Information Contained in Instructions Instruction Execution PC Values Saved for INT Instruction Execution 45 PC Values Saved for INTE Instruction Execution ei aT a qa Aha de 46 Instruction Map Instruction 275 INT INT Instruction Operation 45 PC Values Saved for INT Instruction Execution Dudes st Den neo 45 INT So
219. section describes the operation time requirements and uses of undefined instruction exceptions Overview of Undefined Instruction Exceptions Undefined instruction exceptions are caused by attempts to execute instruction codes that are not defined Operations of Undefined Instruction Exceptions The following operating sequence takes place when an undefined instruction exception occurs 1 The contents of the program status PS are saved to the system stack 2 The address of the instruction that caused the undefined instruction exception is saved to the system stack 3 The value of the system stack pointer SSP is reduced by 8 4 The value 0 is written to the S flag in the condition code register CCR in the PS 5 The value TBR 3C4 is stored in the program counter PC Time to Start of Undefined Instruction Exception Processing The time required to start exception processing is 7 cycles PC Values Saved for Undefined Instruction Exceptions The address saved to the system stack as a PC value represents the instruction itself that caused the undefined instruction exception When instruction is executed the contents of the system stack should be rewritten with the exception processing routine so that execution will either resume from the address of the next instruction after the instruction that caused the exception or branch to the appropriate processing routine How to Use Unde
220. ss and branches This instruction has no delay slot Vector numbers 9 to 13 64 and 65 are used by emulators for debugging interrupts and therefore the corresponding numbers INT 9 to INT 13 INTZ64 INT 65 should not be used in user programs E INT Software Interrupt Assembler format INT u8 Operation SSP 4 gt SSP PS SSP SSP 4 gt SSP PC 2 SSP 0 gt flag 0 gt S flag 3FC u8 x 4 2 PC Flag change N Z V and C Unchanged S and I Cleared to 0 Execution cycles 3 3a cycles Instruction format MSB LSB 188 Example INT 20H CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Instruction bit pattern 0001 1111 0010 0000 R15 SSP TBR USP PC PS CCR OOOFFF7C 7FFFFFF8 7FFFFFFC 80000000 40000000 80000000 000F 00 40000000 8088 8086 FFFFF8F0 SINZVC 110000 Memory 6809 6800 X X X X X X X X X X X X X X X X X X X X X X X X Before execution R15 SSP TBR USP PC PS CCR 000FFF7C 7FFFFFF8 7FFFFFFC 80000000 7FFFFFF8 7FFFFFF8 000F 00 4000 0000 6809 6800 FFFFF8CO SINZVC 000000 Memory 6809 6800 8088 8088 FFFFF8FO X X X X X X X X After execution 189 CHAPTER 7 DETAILED EXECUTION I
221. sults of multiplication operations are stored in the MDH higher 32 bits and MDL lower 32 bits registers The results of division are stored as follows quotients in the 32 bit MDL register and remainders in the 32 bit MDH register Initial Value of the MD The initial value is undefined 30 CHAPTER 4 RESET AND EIT PROCESSING This chapter describes reset and EIT processing in the FR family CPU A reset is a means of forcibly terminating the currently executing process initializing the entire device and restarting the program from the beginning EIT processing in contrast terminates the currently executing process and saves restart information to the memory then transfers control to a predetermined processing program EIT processing programs can return to the prior program by use of the RETI instruction EIT processing operates in essentially the same manner for exceptions interrupts and traps with the following minor differences Interrupts originate independently of the instruction sequence Processing is designed to resume from the instruction immediately following the acceptance of the interrupt e Exceptions are related to the instruction sequence and processing is designed to resume from the instruction in which the exception occurred Traps are also related to the instruction sequence and processing is designed to resume from the instruction immediately following the inst
222. t Data from Register to Coprocessor Register COPST Store 32 bit Data from Coprocessor Register to Register COPSV Save 32 bit Data from Coprocessor Register to Register NOP No Operation ANDCCR And Condition Code Register and Immediate Data ORCCR Or Condition Code Register and Immediate Data STILM Set Immediate Data to Interrupt Level Mask Register ADDSP Add Stack Pointer and Immediate Data EXTSB Sign Extend from Byte Data to Word Data EXTUB Unsign Extend from Byte Data to Word Data EXTSH Sign Extend from Byte Data to Word Data EXTUH Unsigned Extend from Byte Data to Word Data LDMO Load Multiple Registers LDM1 Load Multiple Registers STMO Store Multiple Registers STM1 Store Multiple Registers ENTER Enter Function LEAVE Leave Function XCHB Exchange Byte Data 71 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 1 ADD Add Word Data of Source Register to Destination Register Adds word data in Rj to word data in Ri stores results to Ri m ADD Add Word Data of Source Register to Destination Register Assembler format Operation Flag change Execution cycles Instruction format Example 72 ADD Rj Ri Ri Rj gt Ri Set when the MSB of the operation result is 1 cleared when the MSB is 0 Z Set when the operation result is cleared otherwise V Set when an overflow has occurred as a resu
223. t stored in the and the remainder in the multiplication division register The value of the sign bit in the MDL and Ri is used to set the DO and D1 flag bits in the system condition code register SCR e Set when the dividend is negative cleared when positive e D1 Set when the divisor and dividend signs are different cleared when equal The word data in the MDL is extended to 64 bits with the higher word in the MDH and the lower word in the MDL To execute signed division the following instructions are used in combination DIVOS DIV1x32 DIV2 DIV3 DIV4S DIVOS Initial Setting Up for Signed Division Assembler format DIVOS Ri Operation MDL 31 DO MDL 81 eor Ri 31 gt D1 exts MDL MDH MDL Flag change N Z V and C Unchanged Execution cycles 1 cycle Instruction format MSB LSB 128 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example DIV0S R2 Instruction bit pattern 1001 0111 0100 0010 R2 OFFF FFFF R2 OFFF FFFF MDH 0000 0000 MDH FFFFFFFF MDL MDL FFFF FFFO D1 DOT 01 DOT SCR x x 0 SCR 110 Before execution After execution Example Actual use MDL R2 MDL quotient MDH remainder signed calculation DIVOS R2 DIVI R2
224. te Data to Destination ierit Erde 78 ADDSP ADDSP Add Stack Pointer and Immediate Data 241 Alignment Data Restrictions on Word Alignment 11 Program Restrictions on Word Alignment 11 AND AND And Word Data of Source Register to Data in E 86 AND And Word Data of Source Register to Destination Register 85 And Byte Data ANDB And Byte Data of Source Register to Data in p M 90 And Condition Code ANDCCR And Condition Code Register and Immediate Data 238 And Half word Data ANDH And Half word Data of Source Register to Data in Memory 88 278 And Word Data AND And Word Data of Source Register to Data in Memory 86 AND Word Data of Source Register to Destination Register 85 ANDB ANDB And Byte Data of Source Register to Data in M MOTY ait a ta u a qa ua 90 ANDCCR ANDCCR And Condition Code Register and Immediate Data 238 ANDH ANDH And Half word Data of Source Register to Data in Memory 88 Arithmetic Shift ASR Arithmetic Shift to the Right Direction te eat ane insta 144 145 ASR2 Arithmetic Shift to the Right Direction u n e 146 ASR ASR Arithmetic Shift to the Right Direction
225. te Data to Higher 4 Bits of Byte Data in Memory 108 7 28 BORL Or 4 bit Immediate Data to Lower 4 Bits of Byte Data in Memory 110 7 29 BORH Or 4 bit Immediate Data to Higher 4 Bits of Byte Data in Memory 112 7 80 BEORL Eor 4 bit Immediate Data to Lower 4 Bits of Byte Data in Memory 114 7 31 BEORH Eor 4 bit Immediate Data to Higher 4 Bits of Byte Data in Memory 116 7 32 BTSIL Test Lower 4 Bits of Byte Data in 118 7 33 BTSTH Test Higher 4 Bits of Byte Data in Memory 119 7 34 MUE Multiply Word Data steel eer Pere traite tae deer tin 120 vi 7 35 7 36 7 37 7 38 7 39 7 40 7 41 7 42 7 43 7 44 7 45 7 46 7 47 7 48 7 49 7 50 7 51 7 52 7 53 7 54 7 55 7 56 7 57 7 58 7 59 7 60 7 61 7 62 7 63 7 64 7 65 7 66 7 67 7 68 7 69 7 70 7 71 7 72 7 73 7 74 7 75 7 76 7 77 7 78 7 79 7 80 7 81 MULU Multiply Unsigned Word Data ss 122 MULH Multiply Half word Data ss 124 MULUH Multiply Unsigned Half word Data 126 DIVOS Initial Setting Up for Signed 128 DIVOU Initial Setting Up for Unsigned 130 DIV1 Main Process of Division usine 132 DIV2 Correction when Remainder is
226. tension Ri Rj Ri Ri Rj c gt Ri Subtract with carry Ri Rj gt Ri gt gt gt O O gt aar 265 APPENDIX A Instruction Lists Table A 2 2 Compare Instructions 3 Instructions Mnemonic Format SERE E 126 126 CCCC CCCC Mnemonic Ri Rj Ri extu i4 Ri extn i4 Zero extension Minus extension Remarks AND RjRi AND Rj Ri ANDH Rj Ri ANDB Rj Ri Operation Ri amp Rj Ri amp Rj Ri amp Rj Ri amp Rj Word Word Half word Byte OR Rj Ri OR RjGRi ORH Rj ORB Rj Ri Ri Rj Ri I Rj Ri I Rj Ri I Rj Word Word Half word Byte EOR Ri EOR Rj Ri EORH Rj Ri EORB Rj Ri Ri Rj Ri Rj Ri Rj Ri Rj gt gt gt p gt gt gt gt gt gt gt gt Word Word Half word Byte Mnemonic Format Operation Remarks BANDL 04 Ri 04 0 to OFy C 80 1 2a Ri amp F0y u4 O Lower 4 bit operation BANDH 04 u4 0 to 0Fy C 81 1 2a Higher 4 61 operation BORL 04 04 0 to OFy C 90 142a Ri 2 u4 O Lower 4 bit operation BORH 04 Ri 04 0 to OF C O1 1 2 Ri u4 lt lt 4 O Higher 4 bit operation BEORL u4 Ri u4 0 to C 98 142a Ri u4 O Lower 4 bit operation BEORH u4 04 0 t
227. ter execution 146 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 53 LDI 32 Load Immediate 32 bit Data to Destination Register Loads 1 word of immediate data to Ri LDI 32 Load Immediate 32 bit Data to Destination Register Assembler format LDI 32 132 Ri Operation i32 Ri Flag change N Z V and C Unchanged Execution cycles 3 cycles Instruction format MSB LSB 140 1 7 1 Ri n 2 i32 higher 1 1 1 1 1 1 1 1 1 1 1 1 1 1 n 4 i32 lower EE EE EE ee ee Example LDI 32 87654321H R3 Instruction bit pattern 1001 1111 1000 0011 1000 0111 0110 0101 0100 0011 0010 0001 R3 0000 0000 p R3 8765 4321 Before execution After execution 147 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 54 LDI 20 Load Immediate 20 bit Data to Destination Register Extends the 20 bit immediate data with 12 zeros in the higher bits loads to Ri LDI 20 Load Immediate 20 bit Data to Destination Register Assembler format LDI 20 i20 Ri Operation extu i20 Ri Flag change N Z V and C Unchanged Execution cycles 2 cycles Instruction format MSB LSB 140 1 0 1 1 0 1 1 Ri n 2 i20 lower 1 1 1 1 1 1 1 1 1 Example LDI 20 54321H R3 Instruction bit pattern 1001
228. tern 1001 1110 0010 0011 is added 7 34 MUL Multiply Word Data is changed Instruction bit pattern 1010 1111 0010 0011 is added 7 35 MULU Multiply Unsigned Word Data is changed Instruction bit pattern 1010 1011 0010 0011 is added 7 36 MULH Multiply Half word Data is changed Instruction bit pattern 1011 1111 0010 0011 is added 7 37 MULUH Multiply Unsigned Half word Data is changed Instruction bit pattern 1011 1011 0010 0011 is added 7 38 DIVOS Initial Setting Up for Signed Division is changed Instruction bit pattern 1001 0111 0100 0010 is added 7 39 DIVOU Initial Setting Up for Unsigned Division 147 308 is changed Instruction bit pattern 1001 0111 0101 0010 is added 7 40 DIV1 Main Process of Division is changed Instruction bit pattern 1001 0111 0110 0010 is added 7 41 DIV2 Correction when Remainder is 0 is changed Instruction bit pattern 1001 0111 0111 0010 is added xiii Page Changes For details refer to main body 7 42 DIV3 Correction when Remainder is 0 is changed Instruction bit pattern 1001 1111 01100000 is added 7 43 DIVAS Correction Answer for Signed Division is changed Instruction bit pattern 1001 1111 0111 0000 is added 7 44 LSL Logical Shift to the Left Direction is changed Instruction bit pattern 1011 0110 0010 0011 is added
229. terrupt Assembler format RETI Operation R15 PC R15 4 gt R15 R15 gt PS R15 4 R15 Flag change S I N Z V and C Change according to values retrieved from the stack Execution cycles 2 2a cycles Instruction format MSB LSB 10 010 1 1 110 1 1 192 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS Example RETI Instruction bit pattern 1001 0111 0011 0000 R15 7FFF FFF8 R15 4000 0000 SSP 7FFF FFF8 SSP 8000 0000 USP 4000 0000 USP 4000 0000 PC FF0090BC PC 8088 8088 PS FFF0F8D4 PS FFF3F8F1 ILM 10000 ILM 10011 SINZVC SINZVC CCR 010100 CCR 110001 Memory Memory TFFFFFF8 8088 8088 7FFFFFF8 8088 8088 7FFFFFEC FFF3 F8F1 7FFFFFFC FFF 3 F8F1 80000000 X X X X X X X X 80000000 X X X X X X X X Before execution After execution 193 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 94 Bcc Branch Relative if Condition Satisfied This branching instruction has no delay slot If the conditions established for each particular instruction are satisfied branch to the address indicated by label9 relative to the value of the program counter PC When calculating the address double the value of rel8 as a signed extension If conditions are not satisfied no branching can occur Conditi
230. the FR Family CPU 2 Initialization of CPU Internal Register Values at Reset EUER 33 Sample Configuration of the FR Family CPU 4 D Dedicated Registers Dedicated Registers 17 Delay Slots Instructions Prohibited in Delay Slots 58 Undefined Instructions Placed in Delay Slots 43 Delayed Branching Instructions Examples of Processing Delayed Branching Instructions i inei teet 61 279 INDEX Examples of Programing Delayed Branching InstructionS nien 62 Overview of Branching with Delayed Branching 2 3 58 Restrictions on Interrupts during Processing of Delayed Branching Instructions 59 Destination Register ADD Add 4 bit Immediate Data to Destination Register 73 ADD Add Word Data of Source Register to Destination Register 72 ADD2 Add 4 bit Immediate Data to Destination Register aasawa 74 ADDC Add Word Data of Source Register and Carry Bit to Destination Register 75 ADDN Add Immediate Data to Destination Register na u ha due Pun dera a D 77 ADDN Add Word Data of Source Register to Destination Register 76 ADDN2 Add Immediate Data to Destination Register ete 78 AND And Word Data of Source Register to
231. the internal resources of the coprocessor become part of the system context Thus whenever context switching occurs it is necessary to save or restore the contents of the coprocessor Problems arise when there are hidden coprocessor errors remaining from former tasks at the time of context switching In such cases when the exception is detected in a coprocessor context save instruction by the dispatcher it becomes impossible to return the information to the former task This problem is avoided by executing a COPSV instruction which does not send notification of coprocessor errors but acts to clear the internal error Note that the error information is retained in the status information that is saved If the saved status information is returned to the coprocessor at the time of re dispatching to the former task the hidden error condition is cleared and the CPU is notified when the next coprocessor instruction is executed Figure 4 5 1 shows an example in which notification to the coprocessor does not succeed and Figure 4 5 2 illustrates the use of the COPSV instruction to save and restore error information Figure 4 5 1 Example Coprocessor Error Notification Not Successful Hidden error condition Coprocessor J4 4 J i CPU main C C C C Notification COPOP Interrupt Y ceu date 5 Figure 4 5 2 Use of COPSV Instruction to Save Restore Error Information Hidden err
232. tion Lists A 2 Instruction Lists The full instruction set of the FR family CPU is 165 instructions consisting of the following sixteen types These instructions are listed in Table A 2 1 through Table A 2 16 e Add Subtract Instructions 10 Instructions e Compare Instructions 3 Instructions Logical Calculation Instructions 12 Instructions Bit Operation Instructions 8 Instructions e Multiply Divide Instructions 10 Instructions e Shift Instructions 9 Instructions Immediate Data Transfer Instructions 3 Instructions Memory Load Instructions 13 Instructions Memory Store Instructions 13 Instructions Inter register Transfer Instructions Dedicated Register Transfer Instructions 5 Instructions Non delayed Branching Instructions 23 Instructions Delayed Branching Instructions 20 Instructions Direct Addressing Instructions 14 Instructions e Resource Instructions 2 Instructions Coprocessor Instructions 4 Instructions e Other Instructions 16 Instructions B Instruction Lists Table A 2 1 Add Subtract Instructions 10 Instructions Mnemonic Format Operation Remarks Rj Ri i4 Ri i4 Ri Rj Ri Rj Ri i4 Ri ADDN 4 Ri SUB Rj Ri SUBC Ri Ri SUBN Rj Ri Ri Rj Ri Ri extu i4 Ri Zero extension Ri extn i4 Ri Minus extension Ri Rj c gt Ri Add with carry Ri Rj Ri Ri extu i4 gt Ri Zero extension Ri extn i4 Ri Minus ex
233. tore Byte Data in Register to Memory Stores the byte data in Ri to memory address Rj STB Store Byte Data in Register to Memory Assembler format Ri Rj Operation Ri gt Rj Flag change N Z V and C Unchanged Execution cycles a cycle s Instruction format MSB LSB Example STB R3 R2 Instruction bit pattern 0001 0110 0010 0011 R2 1234 5678 R2 1234 5678 R3 0000 0021 R3 0000 0021 Memory Memory 12345678 12345678 21 Before execution After execution 175 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 780 STB Store Byte Data in Register to Memory Stores the byte data in Ri to memory address R13 Rj STB Store Byte Data in Register to Memory Assembler format STB Ri R13 Rj Operation Ri gt R13 Rj Flag change N Z V and C Unchanged Execution cycles a cycle s Instruction format MSB LSB Example STB R13 R2 Instruction bit pattern 0001 0010 0010 0011 R2 0000 0004 R2 0000 0004 R3 0000 0021 gt R3 0000 0021 R13 1234 5678 R13 1234 5678 1234567B Memory 1234567B Memory 1234567C 1234567 21 Before execution After execution 176 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 81 STB Store Byte Data in Register
234. ts to the memory address corresponding to Ri The CPU will not accept hold requests between the memory read operation and the memory write operation of this request EORH Exclusive Or Half word Data of Source Register to Data in Memory Assembler format EORH Rj Ri Operation Ri eor Rj Ri Flag change N Set when the MSB bit 15 of the operation result is 1 cleared when the MSB is 0 7 Set when the operation result is 0 cleared otherwise V and C Unchanged Execution cycles 1 2a cycles Instruction format MSB LSB 102 Example EORH R2 R3 Instruction bit pattern 1001 1101 0010 0011 R2 0000 1100 R3 1234 5678 Memory 12345678 1010 1234567A NZVC CCR 0000 Before execution R2 R3 0000 1100 1234 5678 Memory 12345678 0110 1234567A CCR NZVC 0000 After execution CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 103 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 725 Exclusive Or Byte Data of Source Register to Data in Memory Takes the logical exclusive OR of the byte data at memory address Ri and the byte data in Rj stores the results to the memory address corresponding to Ri The CPU will not accept hold requests between the memory read operation and the memory write operation of this request EORB Exclusive Or Byt
235. uctions must be written to addresses that are multiples of 2 Program Counter Initial Value Following a reset the contents of the PC are set to the reset entry address contained in the vector table Because initialization is applied first to the table base register TBR the value of the reset vector address will be CHAPTER 3 REGISTER DESCRIPTIONS 3 3 2 Program Status PS The program status PS indicates the status of program execution and consists of the following three parts Interrupt level mask register ILM System condition code register SCR Condition code register CCR Overview of Program Status Register The program status register consists of sections that set the interrupt enable level control the program trace break function in the CPU and indicate the status of instruction execution Program Status Register Configuration Figure 3 3 2 shows the configuration of the program status register Figure 3 3 2 Program Status Register Configuration Bitno 34 2120 1615 1110 0807 00 PS CCR Unused Bits in the Program Status Register Unused bits are all reserved for future system expansion Write values should always be 0 The read value of these bits is always 0 Interrupt Level Mask Register ILM Bit 20 to bit 16 Bit Configuration of the ILM Register Figure 3 3 3 Bit Configuration of the ILM Register 20 19 18 17 1 6 ILM
236. x presents FR family instruction map and E format B 1 Instruction Map B 2 E Format 274 APPENDIX B Instruction Maps Instruction Map B 1 This section shows instruction maps for FR family CPU Table B 1 1 Instruction Map Instruction 61 HINN IAW LNLS INI OLN H31N3 6l q l Ho Tu EIU etH gp 518 S18 Nans OWLS 6l qel 5 6P IH 8140 q iog 6leqel 158 S3uis Sgns HHO3 HAOWG 6P HAOWG 61eqe HU LHO OLpO C318 seq 319 eqe S3Yq1 amvo IH OZI OID SIH 0 0100 a 399 legei 399 MIN AOW ELU eld q rid Gl qel usv 8HOX 6191 HO vni 6P ELU eld ANS 2 HHO38 18 HAOWG 6 HAOWG 6l q l OIPO EIU IH OIpO lequel Ag mn usv Mr 4No THO38 usig 8
237. xclusive Or Byte Data EORB Exclusive Or Byte Data of Source Register to Data in Memory sess 104 Exclusive Or Half word Data EORH Exclusive Or Half word Data of Source Register to Data in Memory 102 Exclusive Or Word Data EOR Exclusive Or Word Data of Source Register to Data in Memory 100 EOR Exclusive Or Word Data of Source Register to Destination Register 99 Execution PC Values Saved for INT Instruction Execution MEI 45 PC Values Saved for INTE Instruction Execution A 46 External Interrupts Relation of Step Trace Traps to NMI and External Interr pts eue de ecu 47 EXTSB EXTSB Sign Extend from Byte Data to Word Data eerte 242 5 EXTSH Sign Extend from Byte Data to Word Data d Ec 244 EXTUB Unsign Extend from Byte Data to Word IBEX 243 EXTUH EXTUH Unsigned Extend from Byte Data to Word Data eise eer repetita 245 F Format ues e Ce 276 FR Family Features of the FR Family CPU Core 2 FR Family Register Configuration 14 Sample Configuration of an FR Family Device 3 Sample Configuration of the FR Family CPU 4 G General purpose Registers General purpose Registers during Execution of COPST COPSV Instructions
238. xecution cycles c cycle s The number of execution cycles is normally 1 However if the instruction immediately after involves read or write access to memory address R15 the system stack pointer SSP or the user stack pointer USP then an interlock is applied and the value becomes 2 cycles Instruction format MSB LSB Example ANDCCR 0FEH Instruction bit pattern 1000 0011 1111 1110 SINZVC SINZVC CCR 010101 CCR 010100 Before execution After execution 238 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS 7 122 ORCCR Or Condition Code Register and Immediate Data Takes the logical OR of the byte data in the condition code register CCR and the immediate data and returns the results into the CCR ORCCR Or Condition Code Register and Immediate Data Assembler format ORCCR u8 Operation CCR or u8 gt CCR Flag change 5 I N Z V and C Varies according to results of calculation Execution cycles c cycle s The number of execution cycles is normally 1 However if the instruction immediately after involves read or write access to memory address R15 the system stack pointer SSP or the user stack pointer USP then an interlock is applied and the value becomes 2 cycles Instruction format MSB LSB 11010 1 01011 1 u8 Example ORCCR 10H Instruction bit pattern 1001 0011 0001 0000

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