Home

Freescale Semiconductor DSP56366 User's Manual

1. PDC i PC i Port Pin i Function 0 0 disconnected 0 1 GPIO input 1 0 GPIO output 1 1 ESAI 11 10 9 8 7 6 5 4 3 2 1 0 X FFFFBF PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC2 PC1 PCO 23 22 21 20 19 18 17 16 15 14 13 12 Reserved bit read as zero should be written with zero for future compatibility Figure 8 19 PCRC Register 11 10 9 8 7 6 5 4 3 2 1 0 X FFFFBE PDC11 PDC10 PDC9 PDC8 PDC7 PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 23 22 21 20 19 18 17 16 15 14 13 12 Reserved bit read as zero should be written with zero for future compatibility Figure 8 20 PRRC Register 8 5 3 Port C Data register PDRC The read write 24 bit Port C Data Register see Figure 8 21 is used to read or write data to from ESAI GPIO pins Bits PD 11 0 are used to read or write data from to the corresponding port pins if they are configured as GPIO If a port pin i is configured as a GPIO input then the corresponding bit reflects the value present on this pin Ifa port pin 1 is configured as a GPIO output then the value written into the corresponding 1 bit is reflected on this pin If a port pin 1 is configured as disconnected the corresponding PD i bit is not reset and contains undefined data DSP56366 24 Bit Digital Signal Processor User Manual Rev 4
2. Peripheral Address Register Name DMA4 X FFFFDF DMA SOURCE ADDRESS REGISTER DSR4 X FFFFDE DESTINATION ADDRESS REGISTER DDR4 X FFFFDD COUNTER DCO4 X FFFFDC DMA CONTROL REGISTER DCR4 5 X FFFFDB DMA SOURCE ADDRESS REGISTER DSR5 X FFFFDA DESTINATION ADDRESS REGISTER DDR5 X FFFFD9 DMA COUNTER DCO5 X FFFFD8 CONTROL REGISTER DCR5 PORT D X FFFFD7 PORT D CONTROL REGISTER PCRD X FFFFD6 PORT D DIRECTION REGISTER PRRD X FFFFD5 PORT D DATA REGISTER PDRD DAX X FFFFD4 DAX STATUS REGISTER XSTR X FFFFD3 DAX AUDIO DATA REGISTER B XADRB X FFFFD2 DAX AUDIO DATA REGISTER A XADRA X FFFFD1 DAX NON AUDIO DATA REGISTER XNADR X FFFFDO DAX CONTROL REGISTER XCTR X FFFFCF Reserved X FFFFCE Reserved X FFFFCD Reserved X FFFFCC Reserved X FFFFCB Reserved X FFFFCA Reserved PORT B X FFFFC9 HOST PORT GPIO DATA REGISTER HDR X FFFFC8 HOST PORT GPIO DIRECTION REGISTER HDDR HDIO8 X FFFFC7 HOST TRANSMIT REGISTER HOTX X FFFFC6 HOST RECEIVE REGISTER HORX 5 HOST BASE ADDRESS REGISTER HBAR X FFFFC4 HOST PORT CONTROL REGISTER HPCR X FFFFC3 HOST STATUS REGISTER HSR X FFFFC2 HOST CONTROL REGISTER HCR X FFFFC1 Reserved X FFFFCO Reserved PORT C X FFFFBF PORT C CONTROL REGISTER PCRC X FFFFBE PORT C DIRECTIO
3. PROGRAM X DATA Y DATA FFFF SFFFF INTERNAL SFFFF EXTERNAL I O FF80 128 words FFBO 80 words INTERNAL 1 O 48 words FF80 EXTERNAL EXTERNAL EXTERNAL C000 6000 32K INTERNAL 8K INTERNAL ROM ROM INT RESERVED 2800 INT RESERVED IK RAM 52000 1C00 2400 INT RESERVED 1000 4K INTERNAL 11K INTERNAL 7K INTERNAL 0000 RAM 0000 RAM 0000 RAM Figure 3 13 Memory Maps for MSW 1 0 CE 0 MS 1 SC 1 PROGRAM X DATA Y DATA FFFF SFFFF INTERNAL EXTERNAL FF80 128 words FFBO 80 words INTERNAL I O 48 words FF80 EXTERNAL EXTERNAL EXTERNAL 000 6000 32K INTERNAL 8K INTERNAL ROM ROM ies 34009 INT RESERVED INT RESERVED 2000 1400 2400 9K INTERNAL 8K INTERNAL 5K INTERNAL 0000 RAM 0000 RAM 0000 RAM 1K I CACHE ENABLED Figure 3 14 Memory Maps for MSW 0 0 1 5 1 5 1 DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 3 9 Data and Program Memory Maps PROGRAM X DATA Y DATA SFFFF FFFF INTERNAL FFFF EXTERNAL I O 128 5 80 words INTERNAL 48 words FF80 EXTERNAL EXTERNAL EXTERNAL 000 6000 32K INTERNAL 8K INTERNAL ROM ROM 177 ied INT RESERVED 52000 NT RESERVED
4. ccell dis ccell dis amp amp amp amp amp amp amp amp amp amp amp amp amp amp amp amp amp 81 83 85 87 89 9T 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 191 rslt rslt Freescale Semiconductor JTAG BSDL 1133 BC 1 control 1 amp 134 6 500141 bidir 133 135 BC 1 control 1 amp 136 6 500132 bidir X 135 Z 2137 BC 1 control 1 amp 138 BC 6 SDOI23 bidir X 137 zy 1139 1 control 1 amp num cell port func safe ccell dis rslt 140 BC 6 5001 bidir X 139 A 141 BC 1 control 1 amp 142 BC 6 SDOO bidir X 141 Zn 143 BC i control 1 amp 144 BC 6 HREQ bidir X 143 2 145 1 SS input X amp 146 control 1 amp 147 BC 6 SCK bidir X 146 Z 148 BC 1 control 1 amp 149 BC 6 SDA bidir X 148 Z t 150 BC A control 1 amp 151 BC 6 MOSI bidir X 150 2 end DSP56366 DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor C 7 rTr lt sms JTAG BSDL NOTES DSP56366 24 Bit Digital
5. 01 ON 0 0 19407 spol peiqeua 0121 121 1 epo JOYI 4 55 1 3 Interrupt Priority Register Core IPR C Figure D DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 D 18 Programming Sheets Date Application Programmer 0 se x 000000 19s9H 216 Vues d 491S b ti 01010 D 01753 15 T 015 153 O0 IHS HIHS 9 2 6 tm 9L Zt 81 1 25 SO SOA SOX ON 0 so 594 SoA 594 SoA 594 ON 0 ON 0 01 5 peiqeua 01V 1 Idi IHS 0 0753 qdl IV 3 931 SoA SoA 594 SOA SoA ON 0 ON 0 peiqeu 0154 Idi 80IGH di 5 dOSSsdo0O0dud IVH LN3O Figure D 4 Interrupt Priority Register Peripherals DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 D 19 Freescale Semicondu
6. XJ0M9N 195 sov 1d ANY 1S3n038 Y VING HO 1 H3AISO3H Y ou s Jed eouo peuejsuei 51 pue 310 13S S9Y14 ANY y 5 YNWA HO LdrtHH31NI H3 LLIINSNVH L ONAS 32079 VIH3S Figure 8 6 Normal and Network Operation DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 8 17 Freescale Semiconductor ESAI Programming Model 8 3 2 10 TCR Tx Slot and Word Length Select TSWS4 TSWSO Bits 10 14 The TSWS4 TSWS0 bits are used to select the length of the slot and the length of the data words being transferred via the ESAI The word length must be equal to or shorter than the slot length The possible combinations are shown in Table 8 5 See also the ESAI data path programming model in Figure 8 13 and Figure 8 14 Table 8 5 ESAI Transmit Slot and Word Length Selection TSWS4 TSWS3 TSWS2 TSWS1 TSWSO SLOT LENGTH WORD LENGTH 0 0 0 0 0 8 8 0 0 1 0 0 12 8 0 0 0 0 1 12 0 1 0 0 0 16 8 0 0 1 0 1 12 0 0 0 1 0 16 0 1 1 0 0 20 8
7. 8 8 14 pue e p 8 ees uonduoseq 21033 ujBue pue 1015 uonduoseg pejqeue 94192934 L 1dnuu lul 0 ou s awed poued 1Iq L uonduoseq an ou s awed pio 0 75344 1016 1527 p jqes p 1016 1527 94192834 0 IVS J 000000 3 5 4 44445 m 5 IVS3 HOM D 33 Figure D 18 ESAI Receive Control Register DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor Programming Sheets Application Programmer L GER 995 pues uonduoseg a uonduoseg snouoJuou S snouoJupou sy uondiosaq NAS 6 8 pue 9 9 2 8 995 4S4 sjo3uo uonduoseg SL yo o yo uonduoseg 000000 3959 r84444 1 2 2 VS3 YOIWS 3 uonduoseg EEUU ee m Tu SL 19 ESAI Common Control Register Figure D DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor D 34 Programming Sheets 9 9
8. PROGRAM X DATA Y DATA SFFFFFF INTERNAL SFFFFFF INTERNAL SFFFFFF EXTERNAL RESERVED 128 words 80 words FEFB090 srrrooo EXTERNAL FFFFB0 40K INTERNAL INTERNAL 48 words ROM INTERNAL FFFF80 FF1000 RESERVED FFF000 EXTERNAL INTERNAL NT ies INTERNAL RESERVED RESERVED FFOOCO FF0000 BOOT ROM EXTERNAL EXTERNAL 00 000 006000 32K INTERNAL 8K INTERNAL ROM ROM EXTERNAL 004000 004000 INT RESERVED 002000 001400 002800 10K INTERNAL 8K INTERNAL 5K INTERNAL 000000 RAM 000000 000000 Figure 3 3 Memory Maps for MSW 0 0 0 5 1 SC 0 PROGRAM X DATA Y DATA SFFFFFF INTERNAL SFFFFFF INTERNAL SFFFFFF EXTERNAL RESERVED FFFF80 128 words 80 words srrrooo EXTERNAL FFFFBO 40K INTERNAL INTERNAL I O 48 words ROM INTERNAL SFFFF80 FF1000 RESERVED FFFO00 EXTERNAL INTERNAL INTERNAL RESERVED RESERVED FFOOCO 9 FF0000 BOOT ROM EXTERNAL EXTERNAL 00 000 006000 EXTERNAL 32K INTERNAL 8K INTERNAL ROM ROM 004000 004000 INT RESERVED 002800 MK RAM 002009 NT RESERVED 001C00 002400 INT RESERVED 001C00 7K INTERNAL 8K INTERNAL 7K INTERNAL 000000 RAM 000000 RAM 000000 RAM Figure 3 4 Memory Maps for MSW 0 1 CE 0 MS 1 SC 0 DSP56366 24 Bit Digital Signal Processor User Manual Rev 4
9. Signals Identified by Functional Group Memory Maps for MSW X X CE 0 MS 0 SC 0 Memory Maps for MSW X X CE 1 MS 0 SC 0 Memory Maps for MSW 0 0 CE 0 MS 1 SC 0 Memory Maps for MSW 0 1 CE 0 MS 1 SC 0 Memory Maps for MSW 1 0 CE 0 MS 1 SC 0 Memory Maps for MSW 0 0 CE 1 MS 1 SC 0 Memory Maps for MSW 0 1 CE 1 MS 1 SC 0 Memory Maps for MSW 1 0 CE 1 MS 1 SC 0 Memory Maps for MSW X X 0 MS 0 SC 1 Memory Maps for MSW X X CE 1 MS 0 SC 1 Memory Maps for MSW 0 0 CE 0 MS 1 SC 1 Memory Maps for MSW 0 1 CE 0 MS 1 SC 1 Memory Maps for MSW 1 0 CE 0 MS 1 SC 1 Memory Maps for MSW 0 0 CE 1 MS 1 SC 1 Memory Maps for MSW 0 1 CE 1 MS 1 SC 1 Memory Maps for MSW 1 0 CE 1 MS 1 SC 1 Interrupt Priority Register P Interrupt Priority Register C HDIOS BlockDiagratm eos Dec Se boa UP DU nie RS Host Control Register HCR X FFFFC2 Host Status Register HSR X FFFFC3 Host Base Address Register HBAR X FFFFC5 Chip select logic oL eee bea orte at et da e ce CR pco Host Port Control Register HPCR X FFFFC4 Single strobe bus Dual Strobes sive Ee ain a A URS E C ES edad Host Data Direction
10. diusuonejed Nad pue diSd Figure D 5 Phase Lock Loop Control Register PCTL DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 D 20 Programming Sheets Application Date Programmer Sheet 1 of 6 HOST HDIO8 DSP Side Host Receive Data usually read by program 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 Receive High Byte Receive Middle Byte Receive Low Byte Host Receive Register HORX X FFFEC6 Read Only Reset empty Host Transmit Data usually loaded by program 23 22 21 20119 18 17 16115 14 13 12 Transmit High Byte Transmit Low Byte Host Transmit Register HOTX X FFFEC7 Write Only Reset empty Figure D 6 Host Receive and Host Transmit Data Registers DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor D 21 Programming Sheets Application Date Programmer Sheet 2 of 6 Host Receive Interrupt Enable 0 Disable 1 Enable if HRDF 1 Host Transmit Interrupt Enable 0 Disable 1 Enable if HTDE 1 Host Command Interrupt Enable 0 Disable 1 Enable if HCP 1 Host Control Bits 158 7 6 413 2 1 Host Control Register HCR 0j 0 5 2 Read Write Reset 0 Reserved Program as 0 DSP Side Host Receive Data Full O Wait 1 Read Host Transmit Data Empty 0 1 Write Host Command Pending 0 Wait 1 Ready Host
11. Peripheral Address Register Name X FFFF97 Reserved X FFFF96 Reserved X FFFF95 Reserved SHI X FFFF94 SHI RECEIVE FIFO HRX X FFFF93 SHI TRANSMIT REGISTER HTX X FFFF92 SHI IC SLAVE ADDRESS REGISTER HSAR X FFFF91 SHI CONTROL STATUS REGISTER HCSR X FFFF90 SHI CLOCK CONTROL REGISTER HCKR TRIPLE TIMER X FFFF8F 0 CONTROL STATUS REGISTER TCSRO X FFFF8E TIMER 0 LOAD REGISTER TLRO X FFFF8D 0 COMPARE REGISTER TCPRO X FFFF8C 0 COUNT REGISTER TCRO X FFFF8B TIMER 1 CONTROL STATUS REGISTER TCSR1 X FFFF8A TIMER 1 LOAD REGISTER TLR1 X FFFF89 TIMER 1 COMPARE REGISTER 1 88 TIMER 1 COUNT REGISTER TCR1 X FFFF87 TIMER 2 CONTROL STATUS REGISTER TCSR2 X FFFF86 TIMER 2 LOAD REGISTER TLR2 X FFFF85 TIMER 2 COMPARE REGISTER TCPR2 X FFFF84 TIMER 2 COUNT REGISTER TCR2 X FFFF83 TIMER PRESCALER LOAD REGISTER TPLR X FFFF82 TIMER PRESCALER COUNT REGISTER TPCR X FFFF81 Reserved X FFFF80 Reserved ESAI MUX PIN Y FFFFAF MUX PIN CONTROL REGISTER EMUXR CONTROL Y FFFFAE Reserved Y FFFFAD Reserved DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 3 16 Freescale Semiconductor Table 3 4 Internal Memory Map continued Internal Memory Peripheral Address Register Name Y FFFFAC Reserved Y FFFFAB Reserved Y FFFFAA Rese
12. 8 45 8 4 4 2 Synchronous Asynchronous Operating Modes 8 45 8 4 4 3 Frannie Syne Selections A ROSE MN E NEA 8 46 8 4 4 4 Shift Direction Selection roi ati ERE RESSORT 8 46 8 4 5 Serial Rer ke eM e iare 8 46 8 5 GPIO Pins and Registers UR a deed T RSA 8 47 8 5 1 Port C Control Register PCRC 8 47 8 5 2 Port C Direction Register PRRC 8 47 8 5 3 Port PD RC c c oiov Tete ene pde aq Ea qa 8 48 8 6 ESAI Initialization Examples eee TES Nt a ea vans Sim a Mofa 8 49 8 6 1 Initializing the ESAI Using Individual Reset 8 49 8 6 2 Initializing Just the ESAI Transmitter Section 8 49 8 6 3 Initializing Just the ESAI Receiver 8 50 9 Enhanced Serial Audio Interface 1 ESAI 1 9 1 9 1 Introduction uu l de eee okie RS pu Res OE eode aca a Rodale 9 92 ESAL T Data and Control PINS ng deri th p PURI __ _ hd 4 9 3 9 2 Serial Transmit 0 Data Pin 5 0_1 9 3 9 2 2 Serial Transmit 1 Data Pin SDO1_1 9 3 9 2 3 Serial Transmit 2 Receive 3 Data P
13. PROGRAM X DATA Y DATA SFFFFFF INTERNAL SFFFFFF INTERNAL I O SFFFFFF EXTERNAL I O RESERVED FFFF80 128 words 80 words EXTERNAL FFFFBO 40K INTERNAL SFFFOO0 INTERNAL 48 words ROM INTERNAL SFFFF80 FF1000 RESERVED FFF000 EXTERNAL INTERNAL SEE CDU INTERNAL RESERVED RESERVED FFOOCO gt FF0000 BOOT ROM EXTERNAL EXTERNAL 00 000 006000 32K INTERNAL 8K INTERNAL ROM ROM EXTERNAL 004000 004000 H INT RESERVED 003400 S 001C00 000C00 3K INTERNAL 13K INTERNAL 7K INTERNAL 000000 RAM 000000 RAM 000000 RAM Figure 3 1 Memory Maps for MSW X X CE 0 MS 0 SC 0 PROGRAM X DATA Y DATA SFFFFFF INTERNAL SFFFFFF INTERNAL SFFFFFF EXTERNAL I O RESERVED FFFF80 128 words 80 words srrrooo EXTERNAL FFFFBO 40K INTERNAL INTERNAL 48 words ROM INTERNAL SFFFF80 FF1000 RESERVED FFF000 EXTERNAL INTERNAL acne 2 INTERNAL RESERVED FFooco RESERVED 0000 __ BOOT ROM EXTERNAL EXTERNAL 00C000 006000 32K INTERNAL 8K INTERNAL ROM ROM EXTERNAL 004000 004000 H z INT RESERVED 003400 001 00 000800 2K INTERNAL 13K INTERNAL 7K INTERNAL 000000 RAM 000000 RAM 000000 RAM 1K I CACHE ENABLED Figure 3 2 Memory Maps for MSW X X 1 5 0 SC 0 DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 3 8 Data and Program Memory Maps
14. 11 10 9 8 7 6 5 4 3 2 1 0 X FFFFB7 RSWS1 RSWSO RMOD RMOD RSHFD RE2 RE1 REO 23 22 21 20 19 18 17 16 15 14 13 12 RLIE RPR RFSL RSWS4 RSWSS3 RSWS2 Reserved bit read as zero should be written with zero for future compatibility Figure 8 9 RCR Register Hardware and software reset clear all the bits in the RCR register The ESAI RCR bits are described in the following paragraphs DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 8 26 Freescale Semiconductor ESAI Programming Model 8 3 4 1 RCR ESAI Receiver 0 Enable REO Bit 0 When REO is set and TES is cleared the ESAI receiver 0 is enabled and samples data at the SDOS SDIO pin 5 and should not be enabled at the same time REO 1 and TE5 1 When REO is cleared receiver 0 is disabled by inhibiting data transfer into R X0 If this bit is cleared while receiving a data word the remainder of the word is shifted in and transferred to the RXO data register If REO is set while some ofthe other receivers are already in operation the first data word received in R X0 will be invalid and must be discarded 8 3 4 2 RCR ESAI Receiver 1 Enable RE1 Bit 1 When REI is set and is cleared the ESAI receiver 1 is enabled and samples data at the SDO4 SDI1 pin TX4 and RX1 should not be enabled at the same time 1 1 and TE4 1
15. 6 11 6 5 4 6 HSE DMA Status DIMA Bit ee ou cuts ERE ek age RA A S RO 6 11 6 5 5 Host Base Address Register ABAR 6 11 6 5 5 1 HBAR Base Address BA 10 3 Bits 0 7 6 11 6 5 5 2 HBAR Reserved Bits 8 6 12 6 5 6 Host Port Control Register HPCR 6 12 6 5 6 1 HPCR Host GPIO Port Enable AGEN 0 6 12 6 5 6 2 HPCR Host Address Line 8 Enable HA8EN Bit 1 6 13 6 5 6 3 HPCR Host Address Line 9 Enable HA9EN 2 6 13 6 5 6 4 HPCR Host Chip Select Enable Bit 3 6 13 6 5 6 5 HPCR Host Request Enable HREN Bit 4 6 13 6 5 6 6 HPCR Host Acknowledge Enable HAEN Bit 6 13 6 5 6 7 HPCR HostEnable HENX E es 6 13 6 5 6 8 HPOCR Reserved Bit T ul l Ee RU UOS cage I e Red 6 13 6 5 6 9 HPCR Host Request Open Drain 8 6 14 6 5 6 10 HPCR Host Data Strobe Polarity HDSP Bit9 6 14 6 5 6 11 HPCR Host Address Strobe Polarity HASP Bit 10 6 14 6 5 6 12 HPCR Host Multiplexed bus 11 6 14 6 5 6 13 HPCR Host Dual Data
16. 6 28 6 7 1 HDIOS Host Processor Data Transfer 6 28 6 7 2 Polines user cu es eu AA E 4 AA 6 28 6 7 3 Servicing IntertuptSr thee dues true ox ete eda a a arte bue 6 29 7 Serial Host Interface 7 1 7 1 Desa or ele ae de nea aus e 7 1 7 2 Serial Host Interface Internal Architecture 7 2 7 3 SHL CICK Generator aqa y CARO aine ute de eo PRE RY 7 2 7 4 Serial Host Interface Programming Model 7 3 7 4 1 SHI Input Output Shift Register IOSR Host Side 7 5 7 4 2 SHI Host Transmit Data Register HTX DSP 81 7 6 7 4 3 SHI Host Receive Data FIFO HRX DSP Side 7 6 7 4 4 SHI Slave Address Register HSAR DSP 81 7 6 7 4 4 1 HSAR Reserved Bits Bits 19 17 0 7 7 7 4 4 2 HSAR Slave Address HA 6 3 HA1 Bits 23 20 18 7 7 7 4 5 SHI Clock Control Register HCKR DSP Side 7 7 7 4 5 1 Clock Phase and Polarity 1 0 7 7 7 4 5 2 HCKR Prescaler Rate Select 5 2
17. Equates M XBLK EQU 2 DAX Block Transferred XBLK gt non audio bits in XNADR M XVA EQU 10 DAX Channel A Validity XVA M XUA EQU 11 DAX Channel A User Data XUA M XCA EQU 12 DAX Channel A Channel Status XCA M XVB EQU 13 DAX Channel B Validity XVB M XUB EQU 14 DAX Channel B User Data XUB M XCB EQU 15 DAX Channel B Channel Status XCB control bits in XCTR M XDIE EQU 0 DAX Audio Data Register Empty Interrupt Enable XDIE M EQU 1 DAX Underrun Error Interrupt Enable XUIE M XBIE EQU 2 DAX Block Transferred Interrupt Enable XBIE M XCSO EQU 3 DAX Clock Input Select 0 XCSO M XCS1 EQU 4 DAX Clock Input Select 1 XCS1 M XSB EQU 5 DAX Start Block XSB EQUATES for SHI Register Addresses M HRX EQU SFFFF94 SHI Receive FIFO HRX M_HTX EQU SFFFF93 SHI Transmit Register HTX M HSAR EQU SFFFF92 SHI I2C Slave Address Register HSAR M_HCSR EQU SFFFF91 SHI Control Status Register HCSR M HCKR EQU SFFFF90 SHI Clock Control Register HCKR DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 B 18 Freescale Semiconductor Equates HSAR bits M HA6 EQU 23 SHI I2C Slave Address HA6 M 5 EQU 22 SHI I2C Slave Address 5 M 4 EQU 21 SHI I2C Slave Address 4 M HA3 EQU 20 SHI I2C Slave Address HA3 M 1 EQU 18 SHI I2C Slave Address HA1 s control and status bits in HCSR M HBUSY EQU 22 SHI H
18. Receiver RHCKD RFSD RCKD Bit Clock OUTPUTS Source 0 0 0 SCKR 0 0 1 HCKR SCKR 0 1 0 SCKR FSR 0 1 1 HCKR FSR SCKR 1 0 0 SCKR HCKR 1 0 1 INT HCKR SCKR 1 1 0 SCKR HCKR FSR 1 1 1 INT HCKR FSR SCKR 8 2 8 Transmitter Serial Clock SCKT SCKT is a bidirectional pin providing the transmitters serial bit clock for the ESAI interface The direction of this pin is determined by the TCKD bit in the TCCR register The SCKT is a clock input or output used by all the enabled transmitters in the asynchronous mode SYN 0 or by all the enabled transmitters and receivers in the synchronous mode SYN 1 see Table 8 2 DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 8 5 ESAI Data and Control Pins Table 8 2 Transmitter Clock Sources Transmitter THCKD TFSD TCKD Bit Clock OUTPUTS Source 0 0 0 SCKT 0 0 1 HCKT SCKT 0 1 0 SCKT FST 0 1 1 HCKT FST SCKT 1 0 0 SCKT HCKT 1 0 1 INT HCKT SCKT 1 1 0 SCKT HCKT FST 1 1 1 INT HCKT FST SCKT SCKT may be programmed as a general purpose I O pin PC3 when the ESAI SCKT function is not being used NOTE Although the external ESAI serial clock can be independent of and asynchronous to the DSP system clock the DSP clock frequency must be at least three times the external ESAI serial clock frequency and each ESAI serial clock phase must exceed the minimum of 1 5 DSP clock per
19. D 32 Figure D 18 ESAI Receive Control Register D 33 Figure D 19 ESAI Common Control Register y RA D 34 DSP56366 24 Bit Digital Signal Processor Rev 4 Freescale Semiconductor LOF 3 Figure D 20 ESAI Status Register s 1i s ou chara Vues Vet tio vois D 35 Figure 0 21 ESAI 1 Multiplex Control Register D 36 Figure 9 22 ESAI 1 Transmit Clock Control D 37 Figure 9 23 ESAI 1 Transmit Control Register peu e dp pA rey e PR ER REA D 38 Figure D 24 ESAI 1 Receive Clock Control D 39 Figure D 25 ESAI 1 Receive Control Register ses ve AM UR rx etu D 40 Figure D 26 ESAI 1 Common Control Register D 41 Figure 109227 ESAF Status Register oae oue Vane D 42 Figure D 28 DAX Non Audio Data Register 22 208 S ERG EA D 43 Figure 0 29 DAX Control and Status Registers D 44 Figure D 30 Timer Prescaler Load and Prescaler Count Registers TPLR TPCR D 45 Figure D 31 Timer Control Status Register 4 Sls Cy e uA ERA ARRA ERAN EAR D 46 Figure D 32 Timer Load Compare and Count Registers D 47 Figure D 35 GPIO Port
20. 01 7644445 IHS OdI3H LSWH L3OHH SIGH 3n4H 3OHH H38H ASNH eni 0 L v S 9 L 8 6 01 LE vl SL 91 24 8L 61 02 Ic c L64444 usoH snielS lonuoO IHS 0 L 4 9 9 2 8 6 OL L v SL 91 ZL 8 61 02 be 22 c 0644449 X 1e1siBeu 49010 IHS 0 L 4 9 9 2 8 6 OL L v SL 91 ZL 8 61 02 be gc 64444 X sseippy O I IHS Figure 7 4 SHI Programming Model DSP Side DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 7 4 Serial Host Interface Programming Model The SHI interrupt vector table is shown in Table 7 1 and the exception priorities generated by the SHI are shown in Table 7 2 Table 7 1 SHI Interrupt Vectors Program Address Interrupt Source VBA 0040 SHI Transmit Data VBA 0042 SHI Transmit Underrun Error VBA 0044 SHI Receive FIFO Not Empty VBA 0048 SHI Receive FIFO Full VBA 004A SHI Receive Overrun Error VBA 004C SHI Bus Error Table 7 2 SHI Internal Interrupt Priorities Priority Interrupt Highest SHI Bus Error SHI Receive Overrun Error SHI Transmit Underrun Error SHI R
21. 7 9 7 4 5 3 HCKR Divider Modulus Select HDM 7 0 Bits 10 3 7 9 7 4 5 4 HCKR Reserved Bits Bits 23 14 11 7 9 7 4 5 5 HCKR Filter Mode 0 13 12 7 9 7 4 6 SHI Control Status Register HCSR DSP Side 7 10 7 4 6 1 HCSR Host Enable HEN Bit0 7 10 7 4 6 1 1 es ves eS a SC ef vens tiec Vi a SOS 7 11 DSP56366 24 Bit Digital Signal Processor Rev 4 TOC 4 Freescale Semiconductor 7 4 6 2 HCSR PC SPI Selection HI2C Bit 1 7 11 7 4 6 3 Serial Host Interface Mode 0 3 2 7 11 7 4 6 4 HCSR Clock Freeze HCKFR Bit 4 7 11 7 4 6 5 HCSR FIFO Enable Control HFIFO Bit 5 7 12 7 4 6 6 Master Mode HMST Bit 6 7 12 7 4 6 7 HCSR Host Request Enable HRQE 1 0 Bits 8 7 7 12 7 4 6 8 HCSR Idle HIDEBEE Bit 9 ides LIVE epi 7 13 7 4 6 9 HCSR Bus Error Interrupt Enable HBIE Bit 10 7 13 7 4 6 10 HCSR Transmit Interrupt Enable 11 7 13 7 4 6 11 HCSR Receive Interrupt Enable HRIE 1 0 Bits 13 12 7 14 7 4 6
22. Operation mode MD MC MB MA 0011 is reserved UE UE EE UE aaa If MD MC MB MA 01xx then the Program RAM is loaded from the SHI EE UE UE UE UE EE UE aaa Operation mode MD MC MB MA 1001 is used for burn in testing UE UE UE Operation mode MD MC MB MA 1010 is reserved Operation mode MD MC MB MA 1011 is reserved If MD MC MB MA 1100 then it loads the program RAM from the Host Interface programmed to operate in the ISA mode The HOST ISA bootstrap code expects to read a 24 bit word Specifying the number of program words a 24 bit word specifying the address to start loading the program words and then a 24 bit word for each program word to be loaded The program words will be stored in contiguous PRAM memory locations starting at the specified starting address After reading the program words program execution starts from the same address where loading started The Host Interface bootstrap load program may be stopped by Setting the Host Flag 0 HFO This will start execution of the loaded program from the specified starting address If MD MC MB MA 1101 then it loads the program RAM from the Host Interface programmed to operate in the 11 non multiplexed mode The HOST 11 bootstrap cod
23. 5 pojoouuoosip X poroeuuoosip 824 cas coas X 6941 ras T TOAS pojoouuoosip TX gt pojoouuoosip 624 TX 5 gt 018411 1045 pojoouuoosip IX 5 pojoouuoosip 01241045 IX gt 0045 pojoouuoosip 0x 5 gt pojoouuoosip 1124 ooas 0 m m m 0x 5 TVSA uid NINA IVS3 IVS3 sXnWa3 IVS3 000000 39594 4V4444 2 xejdnini IVS3 Figure 0 21 ESAI 1 Multiplex Control Register DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor D 36 Programming Sheets Date Application Programmer LLLIWV vodl Odsal 5 1 962 L 445 00 JojeJeueB BU 10 SI seyioeds uonduoseq 0 2 pessed q 1ejeosaud 8 Aq g uonduoseg 47 l 2 vL SL 9 2 18 Ze 1 44 00 JEPIAIG uonduoseg
24. This signal is tri stated during hardware software personal reset or when the HREQ1 HREQO bits in the HCSR are cleared There is no need for external pull up in this state This input is 5 V tolerant DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 2 9 Enhanced Serial Audio Interface Enhanced Serial Audio Interface Table 2 11 Enhanced Serial Audio Interface Signals Signal Name Signal Type State during Reset Signal Description HCKR PC2 Input or output Input output or disconnected GPIO disconnected High Frequency Clock for Receiver When programmed as an input this signal provides a high frequency clock source for the ESAI receiver as an alternate to the DSP core clock When programmed as an output this signal can serve as a high frequency sample clock e g for external digital to analog converters DACs or as an additional system clock Port C 2 When the ESAI is configured as GPIO this signal is individually programmable as input output or internally disconnected The default state after reset is GPIO disconnected This input is 5 V tolerant HCKT PC5 Input or output Input output or disconnected GPIO disconnected High Frequency Clock for Transmitter When programmed as an input this signal provides a high frequency clock source for the ESAI transmitter as an alternate to the DSP core clock When pro
25. 11 10 11 3 4 7 TOSR Direction DIR 24 eres rias edet UE e RO 11 10 11 3 4 8 TCSR Data Input DD Bit 12 52 Sew LORI T ehh ade HE east dea 11 10 11 3 4 9 TCSR Data Output DO Bit 13 11 10 11 3 4 10 TCSR Prescaler Clock Enable PCE Bit 15 11 11 11 3 4 11 Timer Overflow Flag TOF Bit20 11 11 DSP56366 24 Bit Digital Signal Processor Rev 4 TOC 10 Freescale Semiconductor 11 3 4 12 Timer Compare Flag TCF Bit 21 11 11 11 3 4 13 TCSR Reserved Bits Bits 3 10 14 16 19 22 23 11 11 11 3 5 Timer Load Register LER qu papa der q u odes 11 12 11 3 6 Timer Compare Register TCPR 11 12 11 3 7 Timer Count Register TCR E ER Patines E eS 11 12 11 4 Timer Modes of Operation 11 12 11 4 1 Timer Modis u uqu ceu heo emeret VER us ah tet dro ah 11 13 11 4 1 1 Timer GPIO Mode rac Rap BE ede Fe etd rd bates 11 13 11 4 1 2 Timer Pulse Model docens Rte uai BER ap us 11 14 11 4 1 3 Timer Toggle Mode 2 ovS ues tay diets ga ate E CPU 11 14 11 4 1 4 Timer Event Counter Mode 3
26. TX FRAME SYNC Figure 8 7 Frame Length Selection DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 8 20 Freescale Semiconductor ESAI Programming Model 8 3 2 12 TCR Transmit Frame Sync Relative Timing TFSR Bit 16 TFSR determines the relative timing of the transmit frame sync signal as referred to the serial data lines for a word length frame sync only TFSL 0 When is cleared the word length frame sync occurs together with the first bit of the data word of the first slot When TFSR 15 set the word length frame sync starts one serial clock cycle earlier i e together with the last bit of the previous data word 8 3 2 13 TCR Transmit Zero Padding Control Bit 17 When PADC is cleared zero padding is disabled When PADC is set zero padding is enabled PADC in conjunction with the TWA control bit determines the way that padding is done for operating modes where the word length is less than the slot length See the TWA bit description in Section 8 3 2 8 TCR Transmit Word Alignment Control TWA Bit 7 for more details Since the data word is shorter than the slot length the data word is extended until achieving the slot length according to the following rules 1 Ifthe data word is left aligned TWA 0 and zero padding is disabled PADC 0 then the last data bit is repeated after the data word has been transmitted If zero padding is enabled PADC 1 Zeroes are transmitted aft
27. X FFFFFA DRAM CONTROL REGISTER DCR 9 ADDRESS ATTRIBUTE REGISTER 0 AARO X FFFFF8 ADDRESS ATTRIBUTE REGISTER 1 AAR1 X FFFFF7 ADDRESS ATTRIBUTE REGISTER 2 AAR2 X FFFFF6 ADDRESS ATTRIBUTE REGISTER 3 AAR3 X FFFFF5 ID REGISTER IDR DMA X FFFFF4 DMA STATUS REGISTER DSTR X FFFFF3 DMA OFFSET REGISTER 0 DORO X FFFFF2 DMA OFFSET REGISTER 1 DOR1 X FFFFF1 DMA OFFSET REGISTER 2 DOR2 X FFFFFO DMA OFFSET REGISTER DOR3 DMAO X FFFFEF DMA SOURCE ADDRESS REGISTER DSRO X FFFFEE DMA DESTINATION ADDRESS REGISTER DDRO X FFFFED DMA COUNTER DCOO X FFFFEC DMA CONTROL REGISTER DCRO DMA1 X FFFFEB DMA SOURCE ADDRESS REGISTER DSR1 X FFFFEA DMA DESTINATION ADDRESS REGISTER DDR1 X FFFFE9 DMA COUNTER DCO1 X FFFFE8 DMA CONTROL REGISTER DCR1 DMA2 X FFFFE7 DMA SOURCE ADDRESS REGISTER DSR2 X FFFFE6 DMA DESTINATION ADDRESS REGISTER DDR2 5 DMA COUNTER 2 X FFFFE4 DMA CONTROL REGISTER DCR2 X FFFFE3 DMA SOURCE ADDRESS REGISTER DSR3 X FFFFE2 DMA DESTINATION ADDRESS REGISTER DDR3 X FFFFE1 DMA COUNTER DCO3 X FFFFEO DMA CONTROL REGISTER DCR3 pin not available DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 D 2 Freescale Semiconductor Table D 1 Internal Memory Map continued Internal Memory
28. 11 15 11 4 2 Signal Measurement Modes s sot ode Scab Haw REA ERE EN E pL POS RENE 11 16 11 4 2 1 Measurement Accuracy 11 16 11 4 2 2 Measurement Input Width Mode 4 11 16 11 4 2 3 Measurement Input Period Mode 5 11 17 11 4 2 4 Measurement Capture Mode 6 11 17 11 4 3 Pulse Width Modulation PWM Mode 7 11 18 11 4 4 Watchdog Modes ee Vea Sia hr bed vat kia wes cta Ss 11 19 11 4 4 1 Watchdos Pulse Mode 9 ROC Re uya aaa E dS 11 19 11 4 4 2 Watchdog Toggle Mode 10 11 20 11 4 5 Reserved Modes sd acs catia aos e ee RE Te a UR Ead a trs 11 20 11 4 6 2 diusta 11 20 11 4 6 1 Timer Behavior during Wait xax odor sq DV Sx RS EIE VOUS So edd 11 20 11 4 6 2 Timer Behavior during Stop 11 21 11 4 7 Hen area eat VI eU HR ENS e ves 11 21 Appendix A Bootstrap ROM A 1 A l DSP56366 Bootstrap Program 2225 1 Appendix Equates 1 Appendix JTAG BSDE RR C 1 Appendix D Programmer s Reference D 1 BU troduction RT ARE Sade PED
29. 5 RPM4 RPM2 RPM1 23 22 21 20 19 18 17 16 15 14 13 12 RHCKD RFSD RFSP RCKP RFP3 RFP2 RDC4 RDC3 Reserved bit read as zero should be written with zero for future compatibility Figure 9 7 RCCR 1 Register Hardware and software reset clear all the bits of the RCCR 1 register 9 3 4 1 RCCR 1 Rx High Freq Clock Divider RFP3 RFPO Bits 14 17 Since the ESAI 1 does not have the receiver high frequency clock pin the RFP3 RFPO bits simply specify an additional division ratio in the clock divider chain See Figure 9 4 9 3 4 2 RCCR 1 Rx High Freq Clock Polarity RHCKP Bit 20 The ESAI 1 does not have the receiver high frequency clock pin It it recommended that RHCKP should be kept cleared 9 3 4 3 RCCR 1 Rx High Freq Clock Direction RHCKD Bit 23 The ESAI 1 does not have the receiver high frequency clock pin RHCKD must be set for proper ESAI 1 receiver section operation Table 9 3 Receiver Clock Sources asynchronous mode only Receiver RHCKD RFSD RCKD Bit Clock OUTPUTS Source 0 X X Reserved 1 0 0 SCKR_1 1 0 1 INT SCKR_1 1 1 0 SCKR_1 FSR_1 1 1 1 INT FSR_1 SCKR_1 DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 9 9 ESAI 1 Programming Model 9 3 5 ESAI 1 Rec
30. GPIO mode 0 Internal timer interrupt generated by the internal clock Pulse mode 1 External timer pulse generated by the internal clock Toggle mode 2 Output timing signal toggled by the internal clock DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 11 12 Freescale Semiconductor Timer Modes of Operation Event counter mode 3 Internal timer interrupt generated by an external clock Measurement Input width mode 4 Input pulse width measurement Input pulse mode 5 Input signal period measurement Capture mode 6 Capture external signal PWM mode 7 Pulse Width Modulation Watchdog Pulse mode 9 Output pulse internal clock Toggle mode 10 Output toggle internal clock These modes are described in detail below Timer modes are selected by setting the TC 3 0 bits in the TCSR Table 11 2 and Table 11 3 show how the different timer modes are selected by setting the bits in the TCSR Table 11 2 also shows the TIOO signal direction and the clock source for each timer mode NOTE To ensure proper operation the TC 3 0 bits should be changed only when the timer is disabled 1 e when the TE bit in the TCSR is cleared 11 4 1 Timer Modes 11 411 Timer GPIO Mode 0 Bit Settings Mode Characteristics TC3 TC2 TC1 TCO TIOO Clock KIND NAME 0 0 0 0 GPIO Internal 0 Timer GPIO In this mode the timer generates an internal interrupt when a c
31. i wi D 16 Figure D 2 Operating Mode Register D 17 Figure D 3 Interrupt Priority Register Core IPR C D 18 Figure D 4 Interrupt Priority Register Peripherals IPR P D 19 Figure D 5 Phase Lock Loop Control Register PCTL D 20 Figure D 6 Host Receive and Host Transmit Data Registers D 21 Figure D 7 Host Control and Status Registers 94034 D 22 Figure 0 8 Host Base Address and Host Port D 23 Figure D 9 Host Interrupt Control and Interrupt Status D 24 Figure D 10 Host Interrupt Vector and Command D 25 Figure D 11 Host Receive and Transmit Byte Registers D 26 Figure D 12 SHI Slave Address and Clock Control D 27 Figure 0 13 SHI Transmit and Receive Data Registers D 28 Figure D 14 SHI Host Control Status Register D 29 Figure 0 15 ESAI Transmit Clock Control Register D 30 Figure D 16 ESAI Transmit Control Register D 31 Figure D 17 ESAI Receive Clock Control
32. jou jusueJ l uonduoseg uonduoseg uoissiuisueJ Buunp ou S JIUISUEJ 4n220 jou pip Su s ewe uonduoseg ______________ uonduoseq 49181691 ejep ppo uonduosoq ister Figure D 27 ESAI 1 Status Reg DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor D 42 Programming Sheets Date Application Programmer Sheet 1 of 2 00 0 E E W 00 00 195844 LG4343 X ejeg oipny uoN 9 9 109988 Se amp S 9 Z 9 6 01 Hl L L vi SL 9L ZL OZ 12 ec ec anx 1955 g jauueyuD 9 ISuueuo vnx 1955 v WAX v Figure D 28 DAX Non Audio Data Register DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 D 43 Freescale Semiconductor Programming Sheets Date Application Programmer 0 x v03334 X BESHEHPBHBBHBBBBBBBEHBHHBHE 7 gavginvxpnex e 99s 0 L ze S 9 7218 6 OL LL ZL SL 9L LL 8L 6L O
33. 5 RPM3 RPM RPM1 RPMO 23 22 21 20 19 18 17 16 15 14 13 12 RFSD RFSP RCKP RFP3 RFP2 RDC4 RDC3 Figure 8 8 RCCR Register DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 8 22 Freescale Semiconductor ESAI Programming Model Hardware and software reset clear all the bits of the RCCR register 8 3 3 1 RCCR Receiver Prescale Modulus Select RPM7 RPMO Bits 7 0 The RPM7 RPMO bits specify the divide ratio ofthe prescale divider in the ESAI receiver clock generator A divide ratio from 1 to 256 RPM 7 0 00 to FF may be selected The bit clock output is available at the receiver serial bit clock SCKR pin ofthe DSP The bit clock output is also available internally for use as the bit clock to shift the receive shift registers The ESAI receive clock generator functional diagram is shown in Figure 8 3 8 3 3 2 RCCR Receiver Prescaler Range RPSR Bit 8 The RPSR controls a fixed divide by eight prescaler in series with the variable prescaler This bit is used to extend the range of the prescaler for those cases where a slower bit clock is desired When RPSR is set the fixed prescaler is bypassed When RPSR is cleared the fixed divide by eight prescaler is operational see Figure 8 3 The maximum internally generated bit clock frequency is Fosc 4
34. System Stack Control Status 20119 18 17 16 Register SCS Asynchronous Bus Arbitration Enable Extended Stack Underflow Flag Stack Extension Enable Memory Switch Mode Patch Enable Y 15 14 13 12 10 9 pee r 8 7 6 5 4 3 2 1 0 _ 0 Extended Chip Operating Chip Operating Mode Mode Register COM Register COM Operating Mode Register Read Write Reset 00030X Reserved Program as 0 Figure D 2 Operating Mode Register OMR DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor Sheet 3 of 5 333333 X va amana zi 001 i191 2120 riva 1 6L 02 L 6 OL L vL SL OL ZI 8L lo M e Freescale Semiconductor Date Programmer ON 0 0 o6p3 19407 S A SOX SOA ON 0 0 0 peiqeua gol epo Programming Sheets Application SO S9A ON 0 0
35. Ue 4 13 4 6 4 XTAL Disable Bit TED us uoce a cd 4 13 47 Device Identification ID Register 4 13 4 8 JTAG Identification ID Register 4 13 4 9 Boundary Scan Register 4 14 5 General Purpose Input Output 5 1 5 1 RETE T E V EE LL E UE 5 1 2 2 _ Programmim Model DE 5 1 5 2 1 Port B Signals and Registers 5 1 5 2 2 Port C Sienals dnd Registets cuevas tico Co eek no Pac 5 1 5 2 3 Port D Signals and Registers 5 1 5 24 Port E Signals and Registers 5 2 5 2 5 vent Counter Signals 5 2 6 Host Interface HDIO8 6 1 6 1 MM GUUCHON 52 Sau asus 6 1 JHDIOS EESUUEES 542 Lou aD a E Mua 6 1 6 2 1 Intertaec DSP Side cosas eee ed eaa 6 1 6 2 2 Interiace Host Side 22 os sete latus Fo MR Pat Laue Patente pg cuc Ea aas 6 2 6 3 Host Por osc aor ea a t T
36. bus protocol defines the following events Bus not busy Both data and clock lines remain high Start data transfer the start event is defined as a change in the state of the data line from high to low while the clock is high see Figure 7 8 Stop data transfer The stop event is defined as a change in the state of the data line from low to high while the clock is high see Figure 7 8 Data valid tThe state of data line represents valid data when after a start event the data line is stable for the duration of the high period ofthe clock signal The data on the line may be changed during the low period of the clock signal There is one clock pulse per bit of data Start Event Stop Event AA0423 Figure 7 8 Start and Stop Events Each 8 bit word is followed by one acknowledge bit This acknowledge bit is a high level put on the bus by the transmitter when the master device generates an extra acknowledge related clock pulse A slave receiver that is addressed must generate an acknowledge after each byte is received Also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter The acknowledging device must pull down the SDA line during the acknowledge clock pulse so that the SDA line is stable low during the high period of the acknowledge related clock pulse see Figure 7 9 DSP56366 24 Bit Digital Signal Processor User Manual Rev 4
37. 0610 Figure 10 5 Clock Multiplexer Diagram NOTE For proper operation of the DAX the DSP core clock frequency must be at least five times higher than the DAX bit shift clock frequency 64 x Fs 10 5 12 DAX State Machine The DAX state machine generates a set of sequencing signals used in the DAX 10 6 DAX Programming Considerations The following sections describe programming considerations for the DAX 10 6 1 Initiating A Transmit Session To initiate the DAX operation follow this procedure 1 Ensure that the is disabled and PCO bits of port control register PCR are cleared 2 Write the non audio data to the corresponding bits in the XNADR register 3 Write the channel A and channel B audio data in the XADR register 4 Wirite the transmit mode to the XCTR register 5 Enable by setting 1 bit and by setting PCO bit if in slave mode in the port control register PCR transmission begins 10 6 2 Audio Data Register Empty Interrupt Handling When the XDIE bit is set and the DAX is active an audio data register empty interrupt XADE 1 is generated once at the beginning of every frame transmission Typically within an XADE interrupt the DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 10 10 Freescale Semiconductor DAX Programming Considerations non audio data bits of the next frame are stored in XNADR and one frame of audio data to be transmitted in the next frame is sto
38. 13K x 24 Bit X Data RAM and 32K x 24 Bit X Data ROM 40K x 24 Bit Program ROM 3K x 24 Bit Program RAM and 192 x 24 Bit Bootstrap ROM 1K of Program RAM may be used as Instruction Cache or for Program ROM patching 2 24 from Y Data RAM and 5K x 24 Bit from X Data RAM can be switched to Program RAM resulting in up to 10K x 24 Bit of Program RAM Off chip memory expansion External Memory Expansion Port DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 1 2 Freescale Semiconductor DSP56366 Audio Processor Architecture Off chip expansion up to two 16M x 24 bit word of Data memory Off chip expansion up to 16M x 24 bit word of Program memory Simultaneous glueless interface to SRAM and DRAM Peripheral modules Serial Audio Interface ESAD up to 4 receivers and up to 6 transmitters master or slave PS Sony AC97 network and other programmable protocols Serial Audio Interface I ESAI 1 up to 4 receivers and up to 6 transmitters master or slave PS Sony AC97 network and other programmable protocols The ESAI 1 shares four of the data pins with ESAI and ESAI 1 does NOT support HCKR and HCKT high frequency clocks Serial Host Interface SHI SPI and protocols multi master capability 10 word receive FIFO support for 8 16 and 24 bit words Byte wide parallel Host Interface HDI08 with DMA support Triple Timer module TEC Digita
39. 47 L S A 1 ejeq uonduoseg WML YJOMION 0 0 9po N 4109N OGOWL L GOWL pue 10 6 I uonduoseq 7 01 SMSL Su s we poued 1Iq ous owed uonduoseq 1841 IVS3 000000 39593 S64443 1 043002 1753 MOL 3015 351 ejep Jo 9J0Jeq 400 2446 ujBue pJoM 101816 Jo BuruuiDeq o snouoJuouKs ou s ujBue pJoM uonduoseg p lqeu oJez oJez uonduoseg Josey jeuosJeg Jejulsuei uoneJedo uonduoseg pejqeue uondeox3 3IUSUeI peiqesip 1dnujeyu uondeox3 1 uonduoseg p lqeu Ydnueju 1016 ue 3 p jqes p 1dn u lul ejeq 1016 ue 3 uonduoseg 1dnueju peigesip 0 uonduoseg p lqeu 1015 1861 1 3dn ueyu 301 1527 jusueJ uonduoseg ter it Control Regis 1 Transm 0 23 ESAI Figure DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor D 38 Programming Sheets Date Application Progra
40. 8 48 Freescale Semiconductor ESAI Initialization Examples 11 10 9 8 7 6 5 4 3 2 1 0 X FFFFBD 11 PD10 PD9 PD8 PD7 PD6 PD5 PD2 PD1 PDO 23 22 21 20 19 18 17 16 15 14 13 12 Reserved bit read as zero should be written with zero for future compatibility Figure 8 21 PDRC Register 8 6 ESAI Initialization Examples 8 6 1 Initializing the ESAI Using Individual Reset The ESAI should be in its individual reset state PCRC 000 and 000 In the individual reset state both the transmitter and receiver sections of the ESAI are simultaneously reset The TPR bit in the TCR register may be used to reset just the transmitter section The RPR bit in the RCR register may be used to reset just the receiver section Configure the control registers TCCR TCR RCCR according to the operating mode but do not enable transmitters TES TEO 0 or receivers RE3 REO 0 It is possible to set the interrupt enable bits which are in use during the operation no interrupt occurs Enable the ESAI by setting the PCRC register and PRRC register bits according to pins which are in use during operation e Write the first data to be transmitted to the transmitters which are in use during operation This step is needed even if DMA is used to service the transmitters Enable the transmitters and receiver
41. Data is transmitted only when the transmitter enable TEx bit 15 set and after the occurrence of frame sync signal either internally or externally generated The transmitter outputs remain tri stated after TEx bit 15 set until the frame sync occurs From now on the transmitters are operating and can be serviced either by polling interrupts or DMA Initializing Just the ESAI Receiver Section It is assumed that the ESAI is operational that is at least one pin is defined as an ESAI pin The receiver section should be in its personal reset state RPR 1 Configure the control registers RCCR and RCR according to the operating mode making sure to clear the receiver enable bits REO RE3 RPR must remain set Take the receiver section out of the personal reset state by clearing RPR Enable the receivers by setting their RE bits From now on the receivers are operating and can be serviced either by polling interrupts or DMA DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 8 50 Freescale Semiconductor 9 Enhanced Serial Audio Interface 1 ESAI 1 9 1 Introduction The Enhanced Serial Audio Interface I ESAI 1 is the second ESAI peripheral in the DSP56366 It is functionally identical to the ESAI peripheral described in Section 8 Enhanced Serial AUDIO Interface ESAJ except for minor differences described in this section Refer to the ESAI section for functional information about the ESAI 1 in addition to
42. Sheet 2 of 3 3 0 Mode 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 GPIO Output Output Input Input Input Input Output Output Output Internal Internal Internal External Internal Internal Internal Internal Internal Internal Timer Timer Pulse Timer Toggle Event Counter Input Width Input Period Capture Pulse Width Modulation Reserved Watchdog Pulse Watchdog Toggle Reserved Reserved Reserved Reserved Reserved Timer Enable Bit 0 0 Timer Disabled 1 Timer Enabled Timer Overflow Interrupt Enable Bit 1 0 Overflow Interrupts Disabled 1 Overflow Interrupts Enabled Timer Compare Interrupt Enable Bit 2 0 Compare Interrupts Disabled 1 Compare Interrupts Enabled 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 k TRM dati i IST TTT Reserved Program as 0 Timer Control Status Register TCSRO FFFF8F Read Write TCSR1 FFFF8B Read Write TCSR2 FFFF87 Read Write Reset 000000 Note that for Timers 1 and 2 TC 3 0 All other combinations are reserved Figure D 31 Timer Control Status Register 0000 is the only valid combination DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 D 46 Freescale Semiconductor Programming Sheets Appl
43. a Word is received it indicates only in the network mode that the frame sync did not occur during reception of that word RFS is cleared by hardware software ESAI individual or STOP reset RFS is valid only if at least one of the receivers 15 enabled REx 1 NOTE In normal mode RFS always reads as a one when reading data because there is only one time slot per frame the frame sync time slot 8 3 6 6 SAISR Receiver Overrun Error Flag ROE Bit 7 The ROE flag is set when the serial receive shift register of an enabled receiver is full and ready to transfer to its receiver data register RXx and the register is already full RDF 1 If REIE is set an ESAI receive data with exception overrun error interrupt request is issued when ROE is set Hardware software ESAI individual and STOP reset clear ROE ROE is also cleared by reading the SAISR with ROE set followed by reading all the enabled receive data registers 8 3 6 7 SAISR Receive Data Register Full RDF Bit 8 RDF is set when the contents of the receive shift register of an enabled receiver is transferred to the respective receive data register RDF is cleared when the DSP reads the receive data register of all enabled receivers or cleared by hardware software ESAI individual or STOP reset If RIE is set an ESAIreceive data interrupt request is issued when RDF is set 8 3 6 8 SAISR Receive Even Data Register Full REDF Bit 9 When set REDF indicates th
44. one word is transferred per frame sync during the frame sync time slot as shown in Figure 8 6 In network mode it is possible to transfer a word for every time slot as shown in Figure 8 6 For more details see Section 8 4 Operating Modes In order to comply with AC 97 specifications TSWSA TSWSO should be set to 00011 20 bit slot 20 bit word length TFSL and TFSR should be cleared and TDC4 TDCO should be set to 0C 13 words in frame If TMOD 1 0 11 and the above recommendations are followed the first slot and word will be 16 bits long and the next 12 slots and words will be 20 bits long as required by the AC97 protocol Table 8 4 Transmit Network Mode Selection TMOD1 TMODO TDC4 TDCO Transmitter Network Mode 0 0 0 1F Normal Mode 0 1 0 On Demand Mode 0 1 1 1F Network Mode 1 0 X Reserved 1 1 0C AC97 DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 8 16 Freescale Semiconductor ESAI Programming Model ye eq e pue sidnueju 3 LON LAS SOV1s ANY LSANO3Y HO 1 H3AI3O3H Y Y Y Y Y 13 SOV14 VINO HO SLANYYALNI HALLINSNVYL ONAS 32079 TVIH3S
45. to the Address Bus A0 A17 if the Address Bus is not needed by the DSP56300 Core for external accesses The ATE bit is cleared on hardware reset 4 2 4 Patch Enable PEN Bit 23 The Patch Enable function is used for patching Program ROM locations i e to replace during program execution the contents of the Program ROM This is done by using the Instruction Cache to supply the instruction word instead of the Program ROM The Patch Enable function is activated by setting bit 23 PEN in the OMR Register The PEN bit is cleared by hardware reset DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 4 2 Freescale Semiconductor Operating Mode Register OMR The Instruction Cache should be initialized with the new instructions according to the following procedure These steps should be executed from external memory or by download via host interface 1 scc Set Cache Enable 1 Set Patch Enable 1 Initialize TAGs to different values by unlock eight different external sectors Lock the PATCH sector s Move new code to locked sector s to the addresses that should be replaced Start regular PROM program k k k k e KUK K e ke he he e ke ke he e ke he he e ke he he e ke he he e ke he he e ke he he e ke he he e ke he he e ke ke he e e ke ke e e ke ke e e e PATCH initialization example ecce k ke k ke ke he ek ke he e ke K he e khe he e ke he he e ke he he e ke he h
46. uonduoseg 0 2 da IVS3 000000 119524 984444 X 2 42019 Jluusueul IVS3 4991 yusue Busu uo oojo Jo eBpe 0 Jes 4 YOOID Jo uo xoojo Jo Buisu 3noxooj Jas 0 uonduoseg 4 ou s owes L eAnisod Ajuejod ou s 4 0 uonduoseg 4541 uo jo uo 1es 4 uo Jo Huis uo 98 Ajuejog 9012 ASu nb iuj 0 uonduoseg eoJnos L pesn eoJnos 0 uonduoseg yndyno 51 154 jndui s 154 uonduoseq yndyno s s uonduoseg 1 Figure D 15 ESAI Transmit Clock Control Register DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor D 30 Programming Sheets
47. 122 11 23 124 125 126 127 128 129 130 ISI 132 BC 1 RESET input BC 1 control BC 6 HP 0 bidir BC 1 control BC 6 HP 1 bidir BC i control BC 6 HP 2 bidir BC i control BC 6 HP 3 bidir BC i control BC 6 HP 4 bidir BC 1 control BC 6 HP 5 bidir BG control BC 6 HP 6 bidir BG control BC 6 HP 7 bidir BG control BC 6 HP 8 bidir BG control cell port func BC 6 HP 9 bidir BG 9 control BC 6 HP 10 bidir BE uL control BC 6 HP 13 bidir BC 1 control BC 6 TIO bidir BC 1 control BC 6 ACI bidir BC 1 control BC 6 ADO bidir BC 4 control BC 6 HP 14 bidir BC 14 control BC 6 HP 15 bidir BC 1 control BC 6 HP 11 bidir BC 1 control BC 6 HP 12 bidir control cell port func BC 6 HSCKR bidir BC 1 control BC 6 HSCKT bidir control BC 6 SCKR bidir BC 1 control BC 6 SCKT bidir Berd control BC_6 FSR bidir BC 1 control BC 6 FST bidir BC Ly control 6 SDOI50 bidir DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 n 5 D D D FF bX F D F F p4 P D D X D D D op safe D B BD D op D F
48. 3 11 34 2 Program ROM Area Reserved for Motorola Use 3 11 3 1 3 Bootstrap ROM i ccs aces a ARR ape 2 RON 3 11 3 14 Dynamic Memory Configuration Switching 3 11 3 1 5 External Memory Support Luise esce 3 12 3 2 Internal VO Memory MAD oec ete ee oirun tu FRED tur C PESE 3 12 4 Core Configuration rene beeen ae sees 4 1 4 1 4 1 4 2 Operating Mode Register OMR 4 1 4 2 1 Asynchronous Bus Arbitration Enable ABE Bit 13 4 2 4 2 2 Address Attribute Priority Disable APD Bit 14 4 2 4 2 3 Address Tracing Enable ATE Bit 15 4 2 4 2 4 Patch Enable PEN Bit23 evoked IDE rr bee bd 4 2 4 3 Operating MOUs elu ds M ada d s 4 4 44 Interr pt Priority Registers a s aces oe READ RU RS 4 6 4 5 DMA R g st SourceS v icd paw deed bes das 4 12 46 JPEE Tanta zation ats cerco Ie Pb e E MER DUM 4 13 4 6 1 PLL Multiplication Factor MF0 MF11 4 13 4 6 2 PLL Pre Divider Factor PDO PD3 4 13 4 6 3 Crystal Range BIECXTERJ S uQ u unu
49. ESAI M TPSR EQU 8 ESAI M TPM EQU SFF M 7 EQU 7 ESAI M TPM6 EQU 6 ESAI M TPM5 EQU 5 ESAI M EQU 4 ESAI M EQU 3 ESAI M TPM2 EQU 2 ESAI M EQU ji ESAI M EQU 0 ESAI TCR Register bits DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor B 27 Equates M TLIE M TIE M TEDIE M TEIE M TPR M PADC M TFSR M TFSL M TSWS M TSWSA M TSWS3 M TSWS2 M TSWS1 M TSWSO M TMOD M TMOD1 M TMODO M 5 M 4 M TE3 M TE2 M 1 M TEO EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU 23 22 21 20 19 17 16 15 57 00 14 13 12 11 10 5300 3F control bits of SAICR DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 ESAI ESAI ESAI ESAI ESAI ESAI ESAI ESAI ESAI ESAI ESAI ESAI ESAI ESAI ESAI ESAI ESAI ESAI ESAI ESAI ESAI ESAI ESAI B 28 Freescale Semiconductor Equates EQU 8 ESAI M TEBE EQU 7 ESAI M_SYN EQU 6 ESAI M OF2 EQU 2 ESAI M OF1 EQU 1 ESAI OFO EQU 0 ESAI Status bits of SAISR M TODE EQU 17 ESAI M TEDE EQU 16 ESAI M TDE EQU 15 ESAI M TUE EQU 14 ESAI M TFS EQU 13 ESAI M RODF EQU 10 ESAI M REDF E
50. Figure DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 D 31 Freescale Semiconductor Programming Sheets Programmer Date Application L g ees 9SZ L 44 00 2 Je eosoJud seyioeds uonduoseg pessed q Jajeosaid 9 Aq ES JeuoneJedo 9 Aq uonduoseg 2668 005 ZE L 11111 00000 SJOIJUOD uonduoseg 0 7 vegg 99S 9I 4 0 yoojo AouenboJ JO 5195 uonduoseq Jo uo Jo uo ynoyoo D AI9581 JO uo AI 591 jo eBpe uo noy20 9 uonduoseg Ajuejod ou s 4 NM eAnisod Ajuejod ou s uonduoseg AI9581 jo Buisu uo eAieoai Jo uo ynoyoo D pesn eoJnos xooj uonduoseg 3 1 5 IonuoS 3420 2 941999 IVS3 YOON jndino s 4MOH 000000 3 5 4 88 44445 jndui s uonduoseq Figure D 17 ESAI Receive Clock Control Register DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semi
51. Freescale Semiconductor 7 17 Characteristics Of The I2C Bus Start Clock Pulse For Event Acknowledgment SCL From Master Device ZEN 8 9 Data Output I Data Output S by Receiver m N 0424 Figure 7 9 Acknowledgment on the I C Bus A device generating a signal is called a transmitter and a device receiving a signal is called a receiver A device controlling a signal is called a master and devices controlled by the master are called slaves A master receiver must signal an end of data to the slave transmitter by not generating an acknowledge on the last byte clocked out of the slave device In this case the transmitter must leave the data line high to enable the master to generate the stop event Handshaking may also be accomplished by using the clock synchronizing mechanism Slave devices can hold the SCL line low after receiving and acknowledging a byte to force the master into a wait state until the slave device is ready for the next byte transfer The SHI supports this feature when operating as a master device and waits until the slave device releases the SCL line before proceeding with the data transfer 7 6 2 Data Transfer Formats bus data transfers follow the following process after the start event a slave device address is sent The address consists of seven address bits and an eighth bit as a data direction bit R W In the data direction bit zero indicates a transmission write
52. RDF ROE RFS IF2 IF1 IFO 23 22 21 20 19 18 17 16 15 14 13 12 TODE TDE TUE TFS Reserved bit read as zero should be written with zero for future compatibility Figure 9 10 SAISR 1 Register 9 3 8 ESAI 1 Receive Shift Registers The receive shift registers receive the incoming data from the serial receive data pins Data is shifted in by the selected internal external bit clock when the associated frame sync I O is asserted Data is assumed to be received MSB first if RSHFD 0 and LSB first if RSHFD 1 Data is transferred to the ESAI 1 receive data registers after 8 12 16 20 24 or 32 serial clock cycles were counted depending on the slot length control bits in 1 register 9 3 9 ESAI 1 Receive Data Registers The Receive Data Registers RX3 1 2 1 1 and 1 are 24 bit read only registers that accept data from the receive shift registers when they become full The data occupies the most significant portion of the receive data registers according to the ALC control bit setting The unused bits least significant portion and 8 most significant bits when ALC 1 read as zeros The DSP is interrupted whenever RXx 1 becomes full if the associated interrupt is enabled 9 3 10 ESAI 1 Transmit Shift Registers The Transmit Shift Registers contain the data being transmitted Data is shifted out to the serial transmit data pins by the selected internal
53. align for correct modulo addressing ORG PL BURN END PL BURN_ END dup PATTERNS dc endm ORG dc dc dc dc NUM PATTERNS equ PL PATTERNS PL PATTERNS Each value is written to all memories 555555 SAAAAAA 333333 SFOFOFO PATTERNS This code fills the unused bootstrap rom locations with their address dup FF00CO dc endm Reserved Area the Program ROM upper 128 words Address range FFAF80 SFFAFFF ORG PL S FFAF80 PL S FFAF80 This code fills the unused rom locations with their address dup FFBO00 14 dc endm Code segment for testing of ROM Patch This code segment is located in the uppermost addresses of the Program ROM ORG PL S FFB000 14 PL FFBO00 14 move move 580000 0 50 0 DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 write address in unused Boot ROM location Freescale Semiconductor 13 Azz DSP56366 Bootstrap Program move move move move move move move move move move move move move move move move move end x0 x r0 51 x0 x0 x 52 0 0 53 0 0 54 0 0 55 0 x0 x 56 0 x0 x 57 0 x0 x 58 0 0 DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 A 14 Freescale Semiconductor Appendix B Equates PRR RRR k Kk k k Kk k k KR K k Kk
54. 018 Input Output Data 87 HAD3 Control 12 017 Input Output Data 88 HAD3 Input Output Data 13 D16 Input Output Data 89 HAD4 Control 14 015 Input Output Data 90 HAD4 Input Output Data 15 D 23 13 Control 91 HAD5 Control 16 D14 Input Output Data 92 HAD5 Input Output Data DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 4 14 Freescale Semiconductor JTAG Boundary Scan Register BSR Table 4 10 DSP56366 BSR Bit Definition continued pu Pin Name Pin Type e P Pin Name Pin Type e 17 D13 Input Output Data 93 HAD6 Control 18 012 Input Output Data 94 HAD6 Input Output Data 19 D11 Input Output Data 95 HAD7 Control 20 D10 Input Output Data 96 HAD7 Input Output Data 21 D9 Input Output Data 97 5 Control 22 D8 Input Output Data 98 5 Input Output Data 23 D7 Input Output Data 99 HA8 A1 Control 24 D6 Input Output Data 100 HA8 A1 Input Output Data 25 D5 Input Output Data 101 HA9 A2 Control 26 D4 Input Output Data 102 HA9 A2 Input Output Data 27 03 Input Output Data 103 HCS A10 Control 28 D 12 0 Control 104 HCS A10 Input Output Data 29 D2 Input Output Data 105 0 Control 30 D1 Input Output Data 106 TIOO Input Output Data 31 DO Input Output Data 107 ACI Control 32 17 Output3 Data
55. 4 8 12 Freescale Semiconductor ESAI Programming Model 11 10 9 8 7 6 5 4 3 2 1 0 X FFFFB5 TSWS1 TSWSO TMOD1 TMODO TWA TSHFD 5 4 2 TE1 TEO 23 22 21 20 19 18 17 16 15 14 13 12 TLIE TIE TEIE TPR TFSR TFSL 5 54 TSWS3 TSWS2 Reserved bit read as zero should be written with zero for future compatibility Figure 8 5 TCR Register Hardware and software reset clear all the bits in the TCR register The TCR bits are described in the following paragraphs 8 3 2 1 TCR ESAI Transmit 0 Enable Bit 0 enables the transfer of data from TXO to the transmit shift register 0 When is set and a frame sync is detected the transmit 0 portion of the ESAI is enabled for that frame When is cleared the transmitter 70 is disabled after completing transmission of data currently in the ESAI transmit shift register The SDOO output is tri stated and any data present in TXO is not transmitted 1 e data be written to with cleared but data is not transferred to the transmit shift register 0 The normal mode transmit enable sequence is to write data to one or more transmit data registers before setting TEx The normal transmit disable sequence is to clear TEx TIE and TEIE after TDE equals one In the network mode the operation of clearing TEO and setting
56. 6 DAX internal architecture 4 DAX Interrupt Enable XIEN bit 7 DAX Non Audio Data Buffer XNADBUF 6 DAX Operation During Stop 12 DAX Parity Generator PRTYG 9 DAX preamble generator 9 DAX Preamble sequence 9 12 DAX Programming Considerations 10 DAX programming model 3 DAX Status Register XSTR 7 DAX Transmit Underrun error XAUR status flag 8 DI 10 Digital Audio Transmitter 1 21 Digital Audio Transmitter DAX 10 1 DIR 10 Divide Factor DF 7 DMA 6 DSP56366 24 Bit Digital Signal Processor Rev 4 Freescale Semiconductor Index 1 triggered by timer 21 DO bit 10 DO loop 6 DRAM 8 DSP56300 core 2 DSP56300 Family Manual i 2 DSP56303 Technical Data i Enhanced Serial Audio Interface 15 19 Enhanced Synchronous Audio Interface 1 ESAI 1 15 19 ESAI block diagram 1 ESSIO GPIO 1 2 ESSII GPIO 1 external address bus 5 external bus control 5 6 7 external data bus 5 External Memory Expansion Port 5 F functional signal groups 1 G Global Data Bus 6 GPIO 9 22 GPIO ESSIO Port C 1 2 GPIO ESSII Port D 1 108 Port B 1 GPIO Timer 2 Ground 3 ground 1 H HA1 HA3 HA6 HSAR Slave Address 7 hardware stack 5 HBER HCSR Bus Error 16 HBIE HCSR Bus Error Interrupt Enable 13 HBUSY HCSR Host Busy 16 HCKR SHI Clock Control Register 7 HCSR Receive Interrupt Enable Bits 14 SHI Control Status Register 10 HDIOS 1 9 11 12 HDMO0 HDM5 HCKR Divider Mo
57. 6 6 7 Host Side Registers After Reset Table 6 15 shows the result of the four kinds of reset on bits in each of the HDIOS registers seen by the host processor The hardware reset HW is caused by asserting the RESET signal The software reset SW is caused by executing the RESET instruction The individual reset IR is caused by clearing the HEN bit in the HPCR register The stop reset ST is caused by executing the STOP instruction Table 6 15 Host Side Registers After Reset Reset Type Register Register Name Data HW SW IR ST Reset Reset Reset Reset ICR Bits 0 0 CVR HC 0 0 0 0 HV 6 0 32 32 ISR HREQ 0 0 1 if TREQ is set 1 if TREQ is set 0 otherwise 0 otherwise HF3 HF2 0 0 TRDY 1 1 1 1 TXDE 1 1 1 1 RXDF 0 0 0 0 IVR IV 7 0 RXH RXM RXL empty empty empty empty TX TXH TXM TXL empty empty empty empty Note A long dash denotes that the register value is not affected by the specified reset 6 6 8 General Purpose INPUT OUTPUT GPIO When configured as general purpose I O the HDIOS is viewed by the DSP core as memory mapped registers see Section 6 5 HDI08 DSP Side Programmer s Model that control up to 16 I O pins The software and hardware resets clear all DSP side control registers and configure the HDI08 as GPIO with all 16 signals disconnected External circuitry connected to the HDI08 may need externa
58. Acknowledgment on the Log RC 7 18 Bus Protocol For Host Write eh Sa S ebay ids 7 18 Bus Protocol For Host Read 7 19 ESAI Block Diatram 5222652 q wau eee oie eons 8 2 PCER RELIST scp cede Ser We aS dati ENS a ies VIS HERMES 8 8 ESAI Clock Generator Functional Block Diagram 8 9 ESAI Frame Sync Generator Functional Block Diagram 8 11 TOR ROBISICI eines hus Melde evi tae VITE 8 13 Normal and Network Operation 8 17 Frame re us a ayama ET Sowa Eee qud 8 20 E Ra HELL MS eet ux idu xat ad 8 22 RCR Register Fatto RM esae Cut eeu estne Phe o AA 8 26 SATCROREPISIBES 24 ten ovS trf au eA t 8 32 SAICR SYN Bit Operation u ef aues Sou 8 34 SAISR dun Vu D apa DURS hd a a Ut DA D aeu Cane a 8 35 ESAI Data Path Programming Model RITIJISHFD 0 8 38 ESAI Data Path Programming Model R T ISHFD 1 8 39 mediate Roo 8 41 TSMB Register i tesoru enee cL e epo futt di Ie Eu 8 41 RSMA Resister Z 1 Vi Se E Wood Somos Mey Deseo Ve Ry nw Vates ota Me 8 42 RO MB Register Ca ene NC sque ou
59. Bit 23 8 31 ESAI Common Control Register SAICR 8 31 SAICR Serial Output Flag 0 OF0 BitO 8 32 SAICR Serial Output Flag 1 OF1 8 32 SAICR Serial Output Flag 2 OF2 Bit2 8 32 SAICR Reserved Bits Bits 3 5 9 23 8 32 SAICR Synchronous Mode Selection 8 32 SAICR Transmit External Buffer Enable Bit 8 33 SAICR Alignment Control 8 8 33 ESAI Status Register ia ooo esi C EM LN EE 8 34 SAISR Serial Input Flag 0 0 0 8 35 SAISR Serial Input Flag 1 8 35 SAISR Serial Input Flag 2 2 2 8 35 SAISR Reserved Bits Bits 3 5 11 12 18 23 8 35 SAISR Receive Frame Sync Flag RFS Bit6 8 35 SAISR Receiver Overrun Error Flag ROE Bit7 8 36 SAISR Receive Data Register Full RDF Bit 8 8 36 SAISR Receive Even Data Register Full REDF Bit 8 36 SAISR Receive Odd Data Register Bit 10 8 36 SAI
60. Freescale Semiconductor 8 7 ESAI Programming Model special purpose time slot register The following paragraphs give detailed descriptions and operations of each bit in the ESAI registers The ESAI pins can also function as GPIO pins Port C described in Section 8 5 GPIO Pins and Registers 8 3 1 ESAI Transmitter Clock Control Register TCCR The read write Transmitter Clock Control Register TCCR controls the transmitter clock generator bit and frame sync rates the bit clock and high frequency clock sources and the directions of the HCKT FST SCKT signals See Figure 8 2 In the synchronous mode SYN 1 the bit clock defined for the transmitter determines the receiver bit clock as well TCCR also controls the number of words per frame for the serial data 11 10 9 8 7 6 5 4 3 2 1 0 X FFFFB6 TDC2 TDC1 TDCO TPSR TPM7 TPM6 TPM5 TPM4 TPM3 TPM2 TPM1 TPMO 23 22 21 20 19 18 17 16 15 14 13 12 TFSD TCKD TFSP TCKP 2 TDC4 TDC3 Figure 8 2 TCCR Register Hardware and software reset clear all the bits of the TCCR register The TCCR control bits are described in the following paragraphs 8 3 1 1 TCCR Transmit Prescale Modulus Select 7 Bits 0 7 The TPM7 TPMO bits specify the divide ratio of the prescale divider the ESAI transmitter clock generator A
61. In interrupt mode the TREQ and RREQ control bits are used for host processor interrupt control via the external HOREQ output signal and the HACK input signal is used for the MC68000 Family vectored interrupt acknowledge input When and or are set they enable DMA mode and determine the size of the DMA word to be transferred In the DMA mode the HOREQ signal is used to request DMA transfers the TREQ and RREQ bits select the direction of DMA transfers see Table 6 10 and the HACK input signal is used as a DMA transfer acknowledge input If the DMA direction is from DSP to host the contents of the selected register are enabled onto the host data bus when HACK is asserted If the DMA direction is from host to DSP the selected register is written from the host data bus when HACK is asserted The size of the word to be transferred is determined by the DMA control bits and HMI The HDI08 host side data register selected during DMA transfer is determined by 2 bit address counter which is preloaded with the value in HM1 and HMO The address counter substitutes for the HA1 and HAO host address signals of the HDIOS8 during a DMA transfer The host address signal HA2 is forced to one during each DMA transfer The address counter can be initialized with the INIT bit feature After each transfer on the host data bus the address counter is incremented to the next data register When the address counter reaches th
62. Interrupt Priority Registers 11 10 9 8 7 6 5 4 3 2 1 0 ESL11 ESL10 TAL1 TALO DAL1 DALO HDL1 HDLO 5 SHLO ESL1 ESLO ESAI IPL SHI IPL HDI08 IPL DAX IPL TRIPLE TIMER IPL ESAI_1 IPL 23 22 21 20 19 18 17 16 15 14 13 12 reserved Reserved bit Read as zero should be written with zero for future compatibility Figure 4 1 Interrupt Priority Register P 11 10 9 8 7 6 5 4 3 2 1 0 IDL2 1011 IDLO ICL1 ICLO IBL2 IBL1 IBLO IAL2 IAL1 IALO IRQA IPL IRQA mode IRQB IPL IRQB mode IRQC IPL IRQC mode IRQD IPL IRQD mode 23 22 21 20 19 18 17 16 15 14 13 12 D5L1 D5LO D4L1 0410 D3L1 0310 D2L1 D2LO D1L1 D1LO DOL1 DOLO DMAO IPL 1 IPL IPL IPL 4 IPL DMAS IPL Figure 4 2 Interrupt Priority Register C DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 4 7 Interrupt Priority Registers Table 4 5 Interrupt Sources Priorities Within IPL Priority Interrupt Source Level 3 Nonmaskable Highest Hardware RESET Stack Error Illegal Instruction Debug Request Interrupt Trap Lowest Non Maskable Interrupt Levels 0 1 2 Maskable Highest IRQA External Interrupt IRQB External Interrupt IRQC External Interrupt IRQD Exte
63. Lowest ESAI 1 Transmit Data DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor Interrupt Priority Registers Table 4 6 DSP56366 Interrupt Vectors m pee Interrupt Source VBA 00 3 Hardware RESET VBA 02 3 Stack Error VBA 04 3 Illegal Instruction VBA 06 3 Debug Request Interrupt VBA 08 3 Trap VBA 0A 3 Non Maskable Interrupt NMI VBA 0C 3 Reserved For Future Level 3 Interrupt Source VBA 0E 3 Reserved For Future Level 3 Interrupt Source VBA 10 0 2 IRQA VBA 12 0 2 IRQB VBA 14 0 2 IRQC VBA 16 0 2 IRQD VBA 18 0 2 DMA Channel 0 VBA 1A 0 2 DMA Channel 1 VBA 1C 0 2 DMA Channel 2 VBA 1E 0 2 DMA Channel 3 VBA 20 0 2 DMA Channel 4 VBA 22 0 2 DMA Channel 5 VBA 24 0 2 Reserved VBA 26 0 2 Reserved VBA 28 0 2 DAX Underrun Error VBA 2A 0 2 DAX Block Transferred VBA 2C 0 2 Reserved VBA 2E 0 2 DAX Audio Data Empty VBA 30 0 2 ESAI Receive Data VBA 32 0 2 ESAI Receive Even Data VBA 34 0 2 ESAI Receive Data With Exception Status VBA 36 0 2 ESAI Receive Last Slot VBA 38 0 2 ESAI Transmit Data VBA 3A 0 2 ESAI Transmit Even Data VBA 3C 0 2 ESAI Transmit Data with Exception Status VBA 3E 0 2 ESAI Transmit Last Slot VBA 40 0 2 SHI Transmit Data VBA 42 0 2 SHI Transmit Underrun Error DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 4 10 Freesc
64. SC stack counter register The PCU also includes a hardware system stack SS 1 4 4 Internal Buses To provide data exchange between blocks the following buses are implemented Peripheral input output expansion bus PIO EB to peripherals Program memory expansion bus PM EB to program memory Xmemory expansion bus XM EB to X memory memory expansion bus EB to Y memory Global data bus GDB between registers in the DMA AGU OnCE PLL BIU and PCU as well as the memory mapped registers in the peripherals DMA data bus DDB for carrying DMA data between memories and or peripherals DMA address bus DAB for carrying DMA addresses to memories and peripherals Program Data Bus PDB for carrying program data throughout the core X memory Data Bus XDB for carrying X data throughout the core memory Data Bus YDB for carrying Y data throughout the core Program address bus PAB for carrying program memory addresses throughout the core X memory address bus XAB for carrying X memory addresses throughout the core Y memory address bus for carrying Y memory addresses throughout the core internal buses on the DSP56300 family members are 24 bit buses See Figure 1 1 1 4 5 Direct Memory Access DMA The DMA block has the following features Six DMA channels supporting internal and external accesses One two and three dimensional transfers including circular buffering
65. SFFFFAO Register bits 15 14 13 12 11 10 DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 ESAI ESAI ESAI ESAI ESAI ESAI ESAI ESAI ESAI ESAI ESAI ESAI ESAI ESAI ESAI ESAI ESAI ESAI ESAI ESAI ESAI ESAI ESAI ESAI ESAI ESAI Receive Control Register RCR Transmit Clock Control Register TCCR Transmit Control Register TCR Control Register SAICR Status Register SAISR Receive Da Receive Da Receive Da Receive Da ta Regis ta Regis ta Regis ta Regis ter 3 ter 2 ter 1 ter 0 Time Slot Register TSR Transmit Transmit Transmit Transmit Transmit Transmit Data Data Data Data Data Register Register Register Register Register Data Register 5 4 RX3 RX2 RX1 RXO TX5 TX4 B 22 Freescale Semiconductor Equates 2521 EQU 5 ESAI 2520 EQU 4 ESAI 2519 EQU 3 ESAI 2518 EQU 2 ESAI 2517 EQU 1 ESAI 2516 EQU 0 ESAI RSMA Register bits M RS15 EQU 15 ESAI RS14 EQU 14 ESAI M RS13 EQU 13 ESAI M RS12 EQU 12 ESAI RS11 EQU 11 ESAI M RS10 EQU 10 ESAI M 259 EQU 9 ESAI M 258 EQU 8 ESAI M RS7 EQU 7 ESAI M 256 EQU 6 ESAI M 855 EQU 5 ESAI M 854 EQU 4 ESAI 253 EQU 3 ESAI M 852 EQU 2 ESAI M RS1 EQU 1 ESAI M
66. TX2 X FFFFA1 ESAI TRANSMIT DATA REGISTER 1 TX1 X FFFFAO ESAI TRANSMIT DATA REGISTER 0 TXO X FFFF9F Reserved X FFFF9E Reserved X FFFF9D Reserved X FFFF9C Reserved X FFFF9B Reserved X FFFF9A Reserved DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 D 4 Freescale Semiconductor Table D 1 Internal Memory Map continued Internal Memory Peripheral Address Register Name X FFFF99 Reserved X FFFF98 Reserved X FFFF97 Reserved X FFFF96 Reserved X FFFF95 Reserved SHI X FFFF94 SHI RECEIVE FIFO HRX X FFFF93 SHI TRANSMIT REGISTER HTX X FFFF92 SHI IC SLAVE ADDRESS REGISTER HSAR X FFFF91 SHI CONTROL STATUS REGISTER HCSR X FFFF90 SHI CLOCK CONTROL REGISTER HCKR TRIPLE TIMER X FFFF8F 0 CONTROL STATUS REGISTER TCSRO X FFFF8E TIMER 0 LOAD REGISTER TLRO X FFFF8D TIMER 0 COMPARE REGISTER TCPRO X FFFF8C 0 COUNT REGISTER TCRO X FFFF8B TIMER 1 CONTROL STATUS REGISTER TCSR1 X FFFF8A TIMER 1 LOAD REGISTER TLR1 X FFFF89 1 COMPARE REGISTER 1 88 TIMER 1 COUNT REGISTER TCR1 X FFFF87 TIMER 2 CONTROL STATUS REGISTER TCSR2 X FFFF86 TIMER 2 LOAD REGISTER TLR2 X FFFF85 TIMER 2 COMPARE REGISTER TCPR2 X FFFF84 TIMER 2 COUNT REGISTER TCR2
67. Table 4 3 DSP56366 Mode Descriptions Mode 0 DSP starts fetching instructions beginning at address C00000 Memory accesses are performed using SRAM memory access type with 31 wait states and no address attributes selected Address C00000 is reflected as address 00000 on Port A pins 0 17 Mode 1 The bootstrap program loads instructions through Port A from external byte wide memory connected to the least significant byte of the data bus bits 7 0 and starting at address P D00000 The bootstrap code expects to read 3 bytes specifying the number of program words 3 bytes specifying the address to start loading the program words and then 3 bytes for each program word to be loaded The number of words the starting address and the program words are read least significant byte first followed by the mid and then by the most significant byte The program words will be stored in contiguous PRAM memory locations starting at the specified starting address After reading the program words program execution starts from the same address where loading started The SRAM memory access type is selected by the values in Address Attribute Register 1 AAR1 with 31 wait states for each memory access Address D00000 is reflected as address 00000 on Port A pins 0 17 Mode2 The DSP starts fetching instructions from the starting address of the on chip Program ROM Mode 3 Reserved Mode 4 Reserved Mode 5 In this mode the internal PRAM is loaded from t
68. The pins are described in the following sections 9 2 1 Serial Transmit 0 Data Pin SDOO 1 SDOO 1 transmits data from the TXO 1 serial transmit shift register It is shared with the ESAI SDOO signal The pin may be used as SDOO 1 if it is not defined as ESAI SDOO The pin may be used as GPIO if not used by the ESAI or ESAI 1 The ESAI 1 Multiplex Control Register EMUXR defines if the pin belongs to the ESAI or to the ESAI 1 9 2 2 Serial Transmit 1 Data Pin SDO1 1 SDOI 1 transmits data from the 1 serial transmit shift register It is shared with the ESAI SDO1 signal The pin may be used as SDOI 1 if it is not defined as ESAI SDOI The pin may be used as GPIO PE10 if not used by the ESAI or ESAI 1 The ESAI 1 Multiplex Control Register EMUXR defines if the pin belongs to the ESAI or to the ESAI 1 9 2 3 Serial Transmit 2 Receive Data Pin SDO2 1 SDIS3 1 SDO2 I SDI3 1 transmits data from the 2 1 serial transmit shift register when programmed as a transmitter pin or receives serial data to the RX3 1 serial receive shift register when programmed as a receiver pin It is shared with the ESAI SDO2 SDI3 signal The pin may be used as SDO2 1 SDI3 1 if it is not defined as ESA I SDO2 SDI3 The pin may be used as GPIO if not used by the ESAI or ESAI 1 The ESAI 1 Multiplex Control Register EMUXR defines if the pin belongs to the ESAI or to the ESAI 1 9 2 4 Serial Transmit 3 Receive 2 Data Pin SDOS3 1 SDI2 1 S
69. The user must provide adequate decoupling capacitors There are three inputs Vcca 3 Address Bus Power Vcca is an isolated power for sections of the address bus drivers This input must be tied externally to all other chip power inputs The user must provide adequate external decoupling capacitors There are three inputs 4 Data Bus Power is an isolated power for sections of the data bus I O drivers This input must be tied externally to all other chip power inputs The user must provide adequate external decoupling capacitors There are four Vccp inputs Vccc 2 Bus Control Power Vccc is an isolated power for the bus control I O drivers This input must be tied externally to all other chip power inputs The user must provide adequate external decoupling capacitors There are two inputs VccH Host Power Vcc is an isolated power for the HDIOB8 I O drivers This input must be tied externally to all other chip power inputs The user must provide adequate external decoupling capacitors There is one input Vecs 2 SHI ESAI ESAI 1 DAX and Timer Power Vccs is an isolated power for the SHI ESAI ESAI 1 DAX and Timer This input must be tied externally to all other chip power inputs The user must provide adequate external decoupling capacitors There are two Vccs inputs 2 3 Ground Table 2 3 Grounds
70. This condition ensures that the data byte written to HTX is interpreted as being a slave address byte This data byte must specify the slave device address to be selected and the requested data transfer direction NOTE The slave address byte should be located in the high portion of the data word whereas the middle and low portions are ignored Only one byte the slave address byte is shifted out independent ofthe word length defined by the HM 1 0 bits In order for the DSP to initiate a data transfer the following actions are to be performed DSP tests the HIDLE status bit e Ifthe HIDLE status bit is set the DSP writes the slave device address and the R W bit to the most significant byte of HTX The SHI generates a start event The SHI transmits one byte only internally samples the R W direction bit last bit and accordingly initiates a receive or transmit session The SHI inspects the SDA level at the ninth clock pulse to determine the ACK value If __ acknowledged 0 it starts its receive or transmit session according to the sampled R W value If not acknowledged ACK 1 the HBER status bit in HCSR is set which causes an SHI Bus Error interrupt request if HBIE is set and a stop event is generated The HREQ input pin is ignored by the master device if HRQE 1 0 are cleared and considered if either of them is set When asserted HREQ indicates that the external slave device is ready for the n
71. X FFFF83 TIMER PRESCALER LOAD REGISTER TPLR X FFFF82 TIMER PRESCALER COUNT REGISTER TPCR X FFFF81 Reserved X FFFF80 Reserved ESAI MUX PIN Y FFFFAF ESAI MUX PIN CONTROL REGISTER EMUXR CONTROL Y FFFFAE Reserved Y FFFFAD Reserved Y FFFFAC Reserved Y FFFFAB Reserved Y FFFFAA Reserved Y FFFFA9 Reserved Y FFFFA8 Reserved DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor Internal Memory Table D 1 Internal Memory Map continued Peripheral Address Register Name Y FFFFA7 Reserved Y FFFFA6 Reserved 5 Reserved Y FFFFA4 Reserved Reserved Y FFFFA2 Reserved Y FFFFA1 Reserved Y FFFFAO Reserved PORTE Y FFFF9F PORT E CONTROL REGISTER PCRE Y FFFF9E PORT E DIRECTION REGISTER PRRE Y FFFF9D PORT E GPIO DATA REGISTER PDRE DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor Internal Memory Table D 1 Internal Memory Map continued Peripheral Address Register Name ESAI 1 Y FFFF9C ESAI 1 RECEIVE SLOT MASK REGISTER B RSMB 1 Y FFFF9B ESAI 1 RECEIVE SLOT MASK REGISTER A RSMA 1 Y FFFF9A ESAI 1 TRANSMIT SLOT MASK REGISTER B TSMB 1 Y FFFF99 ESAI 1 TRANSMIT SLOT MASK REGISTER A TSMA 1 Y FFFF98 ESAI_1 RECEI
72. and one indicates a request for data read A data transfer is always terminated by a stop event generated by the master device However if the master device still wishes to communicate on the bus it can generate another start event and address another slave device without first generating a stop event the SHI does not support this feature when operating as an master device This method is also used to provide indivisible data transfers Various combinations of read write formats are illustrated in Figure 7 10 and Figure 7 11 ACK from ACK from ACK from Slave Device Slave Device Slave Device N 0to M Start R W Data Bytes Start or Bit 0425 Stop Bit Figure 7 10 12 Bus Protocol For Host Write Cycle DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 7 18 Freescale Semiconductor SHI Programming Considerations ACK from ACK from No ACK Slave Device Master Device from Master Device us N 0to M W Start R Data Bytes Stop Bit AA0426 Bit Figure 7 11 12 Bus Protocol For Host Read Cycle NOTE The first data byte in a write bus cycle can be used as a user predefined control byte e g to determine the location to which the forthcoming data bytes should be transferred 7 7 SHI Programming Considerations The SHI implements both SPI and PC bus protocols and can be programmed to operate as a slave device or a single master device Once the operating mode is selected the SHI may communicate
73. endif move y rO al eor x0 a add a b Check xram clr a dstart xram rO do nO loopx move x 10 1 1 a b check yram start_yram rl1 do 11 loopy move y 1 1 eor x0 a add a b Check pram clr a Hstart pram r2 do n2 loopp move r2 al eor 0 a b if error tne rb r7 movep r7 x M OGDB beq label1 bclr HSCKT x M enddo bra burni bchg SCKT x M_PDRC debug wait 0 2 0 accumulate error b x y ram not symmetrical restore pointer clear a 0 2 0 accumulate error b restore pointer clear a 0 2 0 accumulate error b restore pointer clear a 0 2 0 accumulate error b r7 SFFFFFF as long as test pass condition codes preserved this instr can be removed in case of shortage write pass fail flag to OnCE condition codes preserved this instr can be removed in case of shortage clear SCKT if error terminate the loop normally this instr can be removed in case of shortage and stop execution if no error toggle pin and keep on looping test completion enter debug mode if OnCE port enabled this instr can be removed in case of shortage enter wait otherwise OnCE port disabled DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor sss CIS DSP56366 Bootstrap Program BURN END ORG PL PL PATTERNS dsm 4
74. host chip select HCS input The polarity of the chip select is programmable but is configured active low HCS after reset Host Address 10 When HDIO8 is programmed to interface a multiplexed host bus and the HI function is selected this signal is line 10 of the host address HA10 input bus Port B 13 When the HDIO8 is configured as GPIO this signal is individually programmed as input output or internally disconnected The default state after reset for this signal is GPIO disconnected This input is 5 V tolerant HOREQ HOR EQ Output HTRQ Output PB14 Input output or disconnected GPIO disconnected Host Request When HDIO8 is programmed to interface a single host request host bus and the HI function is selected this signal is the host request HOREQ output The polarity of the host request is programmable but is configured as active low HOREQ following reset The host request may be programmed as a driven or open drain output Transmit Host Request When HDIOS8 is programmed to interface double host request host bus and the HI function is selected this signal is the transmit host request HTRQ output The polarity of the host request is programmable but is configured as active low HTRQ following reset The host request may be programmed as a driven or open drain output Port B 14 When the HDIO8 is configured as GPIO this signal is
75. move 6 0 n DSP56366 Bootstrap Program rb r7 test fail flag test pass flag 000000 SFFFFFF pattern for x memory pattern for y memory pattern for p memory Write pattern to all memory locations EQUALDATA write x and y memory clr Wdstart dram rO ii move gt length_dram UE rep mac 1 1 DE Write x memory clr a start_xram r0 23 move gt length mac 0 0 1 Pd Write y memory clr start_yram rl E move gt length 1 E rep ni mac x1 y0 a 1 Write p memory clr a Hstart pram r2 ii move gt length_pram n2 ii rep n2 move y0 p 2 Pi Check memory contents EQUALDATA Check dram clr a Hstart dram nO loopd move x r0 al eor xl a add a b x y ram symmetrical start of x y ram length of x y ram exercise mac write x y ram ram not symmetrical start of xram length of xram exercise mac write xram start of yram length of yram exercise mac write yram start of pram length of pram write pram x y ram symmetrical restore pointer clear a 0 2 0 accumulate error b DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor DSP56366 Bootstrap Program __ loopx loopy __ loopp label1 burni else
76. n a 11K 7K 32K 8K DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 3 1 Data and Program Memory Maps Table 3 2 On chip RAM Memory Locations Bit Settings RAM Memory Locations mswi MSWO MS SC ape ie AM X X 0 0 X 0000 n a 0000 33FF 0000 1BFF X X 1 0 X 0000 07FF enabled 0000 33FF 0000 1BFF 0 0 0 1 X 0000 27FF n a 0000 1FFF 0000 13FF 0 1 0 1 X 0000 1BFF and n a 0000 1FFF 0000 1BFF 2400 27FF 1 0 0 1 X 50000 OFFF and n a 0000 2BFF 0000 1BFF 2400 27FF 0 0 1 1 X 0000 23FF enabled 0000 1FFF 0000 13FF 0 1 1 1 X 0000 1BFF enabled 0000 1FFF 0000 1BFF 1 0 1 1 X 0000 0FFF enabled 0000 2BFF 0000 1BFF Table 3 3 On chip ROM Memory Locations Bit Settings ROM Memory Locations mswi mswo MS sc UM EOM OM i X X X X 0 FF1000 FF0000 004000 004000 FFAFFF FFOOBF 00BFFF 005FFF X X X X 1 no access no access 004000 004000 00BFFF 005FFF DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor Data and Program Memory Maps
77. the first data word received in RX3 will be invalid and must be discarded 8 3 4 5 RCR Reserved Bits Bits 4 5 17 18 These bits are reserved They read as zero and they should be written with zero for future compatibility 8 3 4 6 RCR Receiver Shift Direction RSHFD Bit 6 The RSHFD bit causes the receiver shift registers to shift data in MSB first when is cleared LSB first when RSHFD is set see Figure 8 13 and Figure 8 14 DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 8 27 ESAI Programming Model 8 3 4 7 RCR Receiver Word Alignment Control RWA Bit 7 The Receiver Word Alignment Control RWA bit defines the alignment of the data word in relation to the slot This is relevant for the cases where the word length is shorter than the slot length If RWA is cleared the data word is assumed to be left aligned in the slot frame If RWA is set the data word is assumed to be right aligned in the slot frame Ifthe data word is shorter than the slot length the data bits which are not in the data word field are ignored For data word lengths of less than 24 bits the data word is right extended with zeroes before being stored in the receive data registers 8 3 4 8 RCR Receiver Network Mode Control RMOD1 RMODO Bits 8 9 The RMODI and bits are used to define the network mode of the ESAI receivers according to Table 8 10 In the normal mode the frame rate div
78. used to extend the range of the prescaler for those cases where a slower bit clock is desired When TPSR is set the fixed prescaler is bypassed When TPSR is cleared the fixed divide by eight prescaler is DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 8 9 ESAI Programming Model operational see Figure 8 3 The maximum internally generated bit clock frequency is Fosc 4 the minimum internally generated bit clock frequency is Fosc 2 x 8 x 256 Fosc 4096 NOTE Do not use the combination TPSR 1 and 7 0 00 which causes synchronization problems when using the internal DSP clock as source TCKD 1 or THCKD 1 8 3 1 3 TCCR Tx Frame Rate Divider Control TDCA4 TDCO Bits 9 13 The TDC4 TDC0 bits control the divide ratio for the programmable frame rate dividers used to generate the transmitter frame clocks In network mode this ratio may be interpreted as the number of words per frame minus one The divide ratio may range from 2 to 32 TDC 4 0 00001 to 11111 for network mode A divide ratio of one TDC 4 0 00000 in network mode is a special case on demand mode In normal mode this ratio determines the word transfer rate The divide ratio may range from 1 to 32 TDC 4 0 00000 to 11111 for normal mode In normal mode a divide ratio of 1 TDC 4 0 00000 provides continuous periodic data word transfers A bit length frame sync TFSL 1 must be used in this case The ESAI frame
79. 0 1 0 0 1 12 0 0 1 1 0 16 0 0 0 1 1 20 1 0 0 0 0 24 8 0 1 1 0 1 12 0 1 0 1 0 16 0 0 1 1 1 20 1 1 1 1 0 24 1 1 0 0 0 32 8 1 0 1 0 1 12 1 0 0 1 0 16 0 1 1 1 1 20 1 1 1 1 1 24 DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 8 18 Freescale Semiconductor ESAI Programming Model Table 8 5 ESAI Transmit Slot and Word Length Selection continued TSWSA TSWS3 TSWS2 TSWS1 TSWSO SLOT LENGTH WORD LENGTH 0 1 0 1 1 Reserved 0 1 1 1 0 1 0 0 0 1 1 0 0 1 1 1 0 1 0 0 1 0 1 1 0 1 0 1 1 1 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 1 1 1 0 0 1 1 1 0 1 8 3 2 11 The TFSL bit selects the length of frame sync to be generated or recognized If TFSL is cleared a word length frame sync is selected If TFSL is set a 1 bit clock period frame sync is selected See Figure 8 7 for examples of frame length selection TCR Transmit Frame Sync Length TFSL Bit 15 DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 8 19 ESAI Programming Model WORD LENGTH TFSL 0 RFSL 0 RX TX FRAME SYNC NOTE Frame sync occurs while data is valid ONE BIT LENGTH TFSL 1 RFSL 1 RX TX FRAME SYNC NOTE Frame sync occurs for one bit time preceding the data MIXED FRAME LENGTH TFSL 1 RFSL 0 RX FRAME SYNC TX FRAME SYNC MIXED FRAME LENGTH TFSL 0 RFSL 1 RX FRAME SYNC
80. 1 ESAI 1 After Reset Hardware or software reset clears the EMUXR register the port E control register bits and the port E direction control register bits which configure all 6 ESAI 1 dedicated I O pins as disconnected and all 4 shared pins as belonging to the ESAI The ESAI 1 is in the individual reset state while all ESAI 1 signals are programmed as general purpose I O or disconnected and is active only if at least one ofthe ESAI 1 I O pins is programmed as belonging to the ESAI 1 9 5 GPIO Pins and Registers The GPIO functionality of the ESAI 1 port is controlled by three registers Port E Control register PCRE Port E Direction register PRRE and Port E Data register PDRE 9 5 1 Port E Control Register PCRE The read write 24 bit Port E Control Register PCRE in conjunction with the Port E Direction Register PRRE controls the functionality of the ESAI 1 GPIO pins Each of the PE 11 0 bits controls the functionality of the corresponding port pin See Table 9 4 for the port pin configurations Hardware and software reset clear all PCRE bits DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 9 13 GPIO Pins and Registers 9 5 2 Port E Direction Register PRRE The read write 24 bit Port E Direction Register PRRE in conjunction with the Port E Control Register controls the functionality of the ESAI 1 GPIO pins Table 9 4 describes the port pin configurations Hardware an
81. 108 ACI Input Output Data 33 16 Output3 Data 109 ADO Control 34 A15 Output3 Data 110 ADO Input Output Data 35 A 17 9 Control 111 HREQ HTRQ Control 36 14 Output3 Data 112 HREQ HTRQ Input Output Data 37 A13 Output3 Data 113 HACK RRQ Control 38 12 Output3 Data 114 HACK RRQ Input Output Data 39 11 Output3 Data 115 HRW RD Control 40 A10 Output3 Data 116 HRW RD Input Output Data 41 9 Output3 Data 117 HDS WR Control 42 A8 Output3 Data 118 HDS WR Input Output Data DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 4 15 JTAG Boundary Scan Register BSR Table 4 10 DSP56366 BSR Bit Definition continued p Pin Name Pin Type eeu P Pin Name Pin Type hun 43 7 Output3 Data 119 HSCKR Control 44 6 Output3 Data 120 HSCKR Input Output Data 45 8 0 Control 121 HSCKT Control 46 5 Output3 Data 122 HSCKT Input Output Data 47 A4 Output3 Data 123 SCKR Control 48 Output3 Data 124 SCKR Input Output Data 49 A2 Output3 Data 125 SCKT Control 50 1 Output3 Data 126 SCKT Input Output Data 51 Output3 Data 127 FSR Control 52 BG Input Data 128 FSR Input Output Data 53 Control 129 FST Control 54 Output3 Data 130 FST Input Output Data 55 1 Control 131 SDO5 SDIO
82. 13 Pipure 9 15 PCRERG91806868 OO Se oor But teu Suo p ana au SO 9 14 Fasure 9 T6 vete DEDE br a qu Ex pau qiu qu e ood 9 14 Figure 9 17 PDRE Register S ub Pu 9 15 Figure 10 1 Digital Audio Transmitter DAX Block Diagram 10 2 Figure 10 2 DAX Programming Model 10 4 Figure 10 3 DAX Relative 12524 wee PX FANE REO 10 8 Figure 10 4 Preamble sequence vao dte p eR EE dV 10 9 Figure 10 5 Clock Multiplexer Diagram 10 10 Figure 10 6 Examples of data organization in memory 10 12 Figure 10 7 Port D Direction Register PRRD 10 13 Figure 10 8 Port Data Register 10 14 Figure 11 1 Timer Event Counter Block Diagram 11 2 Figure 11 2 Timer Block Diagram oce REY 11 3 Figure 11 3 Timer Module Programmer s 1 11 4 Figure 11 4 Timer Presealer Load Register EPLR 11 5 Figure 11 5 Time Prescaler Count Register IPCR hon goed oe Ties 11 6 FiourejD 1 Statue Resister SI vM
83. 2 0 010 Line transfer mode DTM 2 0 010 Line transfer mode D3D 0 Not 3D D3D 0 Not 3D DAM 5 3 2000 2D mode DAM 5 3 2000 2D mode DAM 2 0 101 post increment by 1 DAM 2 0 101 post increment by 1 DDS 1 0 200 X memory space DDS 1 0 200 X memory space DRS 4 0 01010 DAX is DMA request source DRS 4 0 01010 DAX is DMA request source Other bits are application dependent Other bits are application dependent DCO2 DCOH number of frames in block 1 DCOH number of frames in block 1 DCOL 002 3 destination registers DCOL 001 2 destination registers DSR2 first memory address of the block first memory address of the block DDR2 XNADR address base address 1 XADR address base address 2 DORO FFFFFE offset 2 FFFFFF offset 1 The memory organization employed for DMA transfers depends on whether or not non audio data changes from frame to frame as shown in Figure 10 6 DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 10 11 GPIO PORT D Pins and Registers Channel B 00000B Channel B 00000B Channel A 00000A Channel A 00000A Non Audio Data 00009 Channel B 000009 Channel B 000008 Channel A 000008 Channel A 000007 Channel B 000007 Non Audio Data 000006 Channel A 000006 Channel B 000005 Channel B 000005 Channel A 000004 Channel A 000004 Non Audio Data 000003 Channel B 0
84. 250 EQU 0 ESAI TSMB Register bits M TS31 EQU 15 ESAI M 530 EQU 14 ESAI M TS29 EQU i3 ESAI M 528 EQU 12 ESAI DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor B 23 Equates M TS27 EQU 11 ESAI M 526 EQU 10 ESAI M 525 EQU 9 ESAI M 524 EQU 8 ESAI M TS23 EQU uh ESAI M TS22 EQU 6 ESAI M TS21 EQU 5 ESAI M 520 EQU 4 ESAI M TS19 EQU 3 ESAI M 518 EQU 2 ESAI M TS17 EQU 1 ESAI M 516 EQU 0 ESAI TSMA Register bits M TS15 EQU 15 ESAI M 514 EQU 14 ESAI M 513 EQU 13 ESAI M 512 EQU 12 ESAI M TS11 EQU 11 ESAI M 510 EQU 10 ESAI M TS9 EQU 9 ESAI M TS8 EQU 8 ESAI M TS7 EQU 7 ESAI M TS6 EQU 6 ESAI M TS5 EQU 5 ESAI M TS4 EQU 4 ESAI M TS3 EQU 3 ESAI M TS2 EQU 2 ESAI DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 B 24 Freescale Semiconductor Equates M TS1 EQU 1 ESAI M TSO EQU 0 ESAI Register bits M RHCKD EQU 23 ESAI RFSD EQU 22 ESAI EQU 21 EQU 20 ESAI RFSP EQU 19 ESAI M RCKP EQU 18 ESAI M RFP EQU 83 000 ESAI MASK M RFP3 EQU 17 ESAI RFP2 EQU 16 ESAI EQU 15 ESAI M EQU 14 ESAI M RDC EQU 00 ESAI MASK M_RDC4 EQU 13 ESAI M_RDC3 EQU 12 ESAI M_RDC2 EQU 11 ESAI M RDC1 EQU 10 ESAI M RDCO EQU 9 ESAI M_RPSR EQU 8 ESAI M_RPM EQU SF
85. 3 Operating Mode D 4 External Bus Disable bit in OMR 6 Stop Delay 7 Memory Switch Mode 300 mask for CORE DMA priority bits in OMR 8 bit 0 of priority bits in OMR Core DMA 9 bit 1 of priority bits in OMR Core DMA DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 B 16 Freescale Semiconductor Equates M BE EQU 10 Burst Enable M TAS EQU 11 TA Synchronize Select M BRT EQU 12 Bus Release Timing M ABE EQU 13 Async Bus Arbitration Enable M APD EQU 14 Addess Priority Disable M ATE EQU 15 Address Tracing Enable M XYS EQU 16 Stack Extension space select bit in OMR M EUN EQU 17 Extensed stack UNderflow flag in OMR M EOV EQU 18 Extended stack OVerflow flag in OMR M WRP EQU 19 Extended WRaP flag in OMR M SEN EQU 20 Stack Extension Enable bit in OMR M PAEN EQU 23 Patch Enable EQUATES for DAX SPDIF Tx Register Addresses M XSTR EQU SFFFFD4 DAX Status Register XSTR M XADRB EQU SFFFFD3 DAX Audio Data Register B XADRB M XADR EQU SFFFFD2 DAX Audio Data Register XADR M XADRA EQU SFFFFD2 DAX Audio Data Register A XADRA M XNADR EQU SFFFFD1 DAX Non Audio Data Register XNADR M XCTR EQU SFFFFDO DAX Control Register XCTR Status bits in XSTR M XADE EQU 0 DAX Audio Data Register Empty XADE XAUR EQU 1 DAX Trasmit Underrun Error Flag XAUR DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor B 17
86. 3 1 6 IHS O o c63333 X eee ee ee ee ee ee S el een on svH 9VH ALIS IHS 6 0 EL vl SL 2 6 Oc lt cc 66 ovHlo evH LLOL 19501 Joye ZYH pue EVH 9VH SSOAPPY 5 9 1 HVSH Figure 0 12 SHI Slave Address and Clock Control Registers DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 D 27 Freescale Semiconductor Programming Sheets 5 N E 8 deep 01 03143 ISOH IHS 5 E XXXXXX 1osou r64444 X 1 8 6 OL LL ZL SL 9L ZL 6L Oz 12 9M998H 15 IHS l Q HM slu luoo ISOH 150 IHS XXXXXX 1959 914A 623244 X XH L 8 6 OL IL Z vL SL 9L L 8L 6L OZ 12 zz ec 1SOH IHS a rC P U9 U05 19 1s B5 ti 1SOH Application IHS Freescale Semiconductor Figure D 13 SHI Transmit and Receive Data Registers DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 D 28 Program
87. 32 1 TCR ESAI Transmit 0 Enable TEO Bit O 8 13 8 3 2 2 TCR ESAI Transmit 1 Enable TET Bit 1 8 13 8 3 2 3 TCR ESAI Transmit 2 Enable TE2 Bit2 8 14 8 3 2 4 TCR ESAI Transmit 3 Enable Bit3 8 14 8 3 2 5 TCR ESAI Transmit 4 Enable TE4 Bit 4 8 14 8 3 2 6 TCR ESAI Transmit 5 Enable TES Bit 5 8 15 8 3 2 7 TCR Transmit Shift Direction TSHFD Bit6 8 15 8 3 2 8 TCR Transmit Word Alignment Control 7 8 15 8 3 2 9 TCR Transmit Network Mode Control TMODI TMODO Bits 8 9 8 16 8 3 2 10 TCR Tx Slot and Word Length Select TSWSA TSWSO Bits 10 14 8 18 8 3 2 11 TCR Transmit Frame Sync Length TFSL Bit 15 8 19 8 3 2 12 TCR Transmit Frame Sync Relative Timing TFSR Bit 16 8 21 8 3 2 13 TCR Transmit Zero Padding Control PADC Bit 17 8 21 8 3 2 14 TCR Reserved Bit BR EE AN RIA ADS 8 21 8 3 2 15 TCR Transmit Section Personal Reset TPR Bit 19 8 21 8 3 2 16 Transmit Exception Interrupt Enable Bit 20 8 21 8 3 2 17 TCR Transmit Even Slot Data Interrupt Enable TEDIE Bit21 8 22 8 3 2 18 TCR
88. 4 6 2 PLL Pre Divider Factor PDO PD3 The DSP56366 PLL Pre Divider factor is set to 1 during hardware reset i e the Pre Divider Factor Bits PDO PD3 in the PLL Control Register PCTL are set to 0 4 6 3 Crystal Range Bit XTLR The Crystal Range XTLR bit controls the on chip crystal oscillator transconductance The on chip crystal oscillator is not used on the DSP56366 since no XTAL pin is available The XTLR bit is set to zero during hardware reset in the DSP56366 4 6 4 XTAL Disable Bit XTLD The XTAL Disable Bit XTLD is set to 1 XTAL disabled during hardware reset in the DSP56366 4 7 Device Identification ID Register The Device Identification Register IDR is a 24 bit read only factory programmed register used to identify the different DSP56300 core based family members This register specifies the derivative number and revision number This information may be used in testing or by software Table 4 8 shows the ID register configuration Table 4 8 Identification Register Configuration 23 16 15 12 11 0 Heserved Revision Number Derivative Number 00 0 366 4 8 JTAG Identification ID Register The JTAG Identification ID Register is a 32 bit read only thought JTAG factory programmed register used to distinguish the component on a board according to the IEEE 1149 1 standard Table 4 9 shows the JTAG ID register configuration DSP56366 24 Bit Digital Signal Processor User Manual Rev 4
89. ANIT BIET a cess Qa esaet d teg Hes 6 23 6 6 2 Command Vector Register CVR 6 23 6 6 2 1 CVR Host Vector HV 6 0 Bits 0 6 6 23 6 6 2 2 CVR Host Command BIt HC Bit7 6 24 6 6 3 Interface Status Register ISR 6 24 6 6 3 1 ISR Receive Data Register Full RXDF 0 6 24 6 6 3 2 ISR Transmit Data Register Empty TXDE Bit 6 24 6 6 3 3 ISR Transmitter Ready 2 6 25 6 6 3 4 ISR Host Flag 2 5 neie 6 25 6 6 3 5 ISR Host Flag 3 HF3 Bit 4 6 25 6 6 3 6 ISR Reserved Bits 5 0 qu kee FO a AURORA end 6 25 6 6 3 7 ISR Host Request HREQ Bit _ 6 25 6 6 4 Interr pt Vector Register as u Gees s ERE SR e Race sal 6 26 6 6 5 Receive Byte Registers RXH RXM RXL 6 26 6 6 6 Transmit Byte Registers TXH TXM TXL 6 26 6 6 7 Host Side Registers After Resets cuoco nies 6 27 6 6 8 General Purpose INPUT OUTPUT GPIO 6 27 6 7 Servicing The Host cd used rey RD
90. AUDIO INTERFACE ESAI SCKT PC3 FST PC4 HCKT PC5 SCKR PCO FSR PC1 HCKR PC2 SDOO 11 SDOO 1 PE11 001 PC10 SDO1 1 PE10 SDO2 SDI3 PC9 5002 1 SDI3 1 PE9 SDO3 SDI2 PC8 SDO3 1 SDI2 1 PE8 5004 8011 PC7 5005 8010 PC6 SERIAL AUDIO INTERFACE ESAI 1 SCKT 1 PE3 FS T 1 PE4 SCKR 1 PEO FSR 1 PE1 SDO4_1 SDI1_1 PE7 5 5 1 SDIO 1 PE6 vccs 2 GS 2 SERIAL HOST INTERFACE SHI 4 bh 4 55 2 MISO SDA lt SCK SCL HREQ Figure 2 1 Signals Identified by Functional Group DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 2 2 Freescale Semiconductor 2 2 Power Power Table 2 2 Power Inputs Power Name Description VccP PLL Power Vccp is Vcc dedicated for PLL use The voltage should be well regulated and the input should be provided with an extremely low impedance path to the Vcc power rail There is one Vccp input Vcca 4 Quiet Core Low Power Vccq_ is an isolated power for the internal processing logic This input must be tied externally to all other chip power inputs The user must provide adequate external decoupling capacitors There are four Veca inputs 3 Quiet External High Power is a quiet power source for I O lines This input must be tied externally to all other chip power inputs
91. Audio Interface Signals continued Signal Name 005 SDIO PC6 Signal Type Output Input Input output or disconnected State during Reset GPIO disconnected Signal Description Serial Data Output 5 When programmed as a transmitter 5005 is used to transmit data from the TX5 serial transmit shift register Serial Data Input 0 When programmed as a receiver SDIO is used to receive serial data into the RXO serial receive shift register Port C 6 When the ESAI is configured as GPIO this signal is individually programmable as input output or internally disconnected The default state after reset is GPIO disconnected This input is 5 V tolerant 004 5011 PC7 Output Input Input output or disconnected GPIO disconnected Serial Data Output 4 When programmed as a transmitter 5004 is used to transmit data from the 4 serial transmit shift register Serial Data Input 1 When programmed as a receiver SDI1 is used to receive serial data into the RX1 serial receive shift register Port C 7 When the ESAI is configured as GPIO this signal is individually programmable as input output or internally disconnected The default state after reset is GPIO disconnected This input is 5 V tolerant SDO3 003_1 SDI2 SDI2 1 PC8 PE8 Output Input Input output or disconnected GPIO disconnected Serial Data Output 3 When programme
92. B o e e p ud D 48 Fagure D 34 GPIO Port 5 tue ax eR Tm ie da eu ER EQ CU da tuu eaa D 49 bigure D33 GPIO Port y ur ay ear ede peu A D 50 Figure D 36 GPIO Port E ions SP aed SEE a IOS ed s D 51 DSP56366 24 Bit Digital Signal Processor Rev 4 LOF 4 Freescale Semiconductor List of Tables Table 2 1 DSP56364 Functional Signal Groupings 1 2 Table 2 2 Power puts AR Sete eee Be 2 3 Table 2 3 Gronds qe P a p a Sup una 2 3 Table 2 4 Clock did PEL b See 2 4 Table 2 5 External Address Bus Signals 2 5 Table 2 6 External Data Bus Signals o C errat octies 2 5 Table 2 7 External Bus Control Signals 2 5 Table 2 8 Interrupt and Mode Control 2 8 Table 2 9 Host Interfaeeu Seg Sek 2 9 Table 2 10 Serial Host Interface Signals 2 1 2 12 Table 2 11 Enhanced Serial Audio Interface Signals 2 15 Table 2 12 Enhanced Serial Audio Interface 1 Signals 2 19 Table 2 3
93. DSP CORE INTERRUPTS RECIEVE DATA FULL TRANSMIT DATA EMPTY HOST COMMAND AN S vs STATUS Figure 6 11 HSR HCR Operation 6 6 08 External Host Programmer s Model The HDIOS has been designed to provide a simple high speed interface to a host processor To the host bus the HDI08 appears to be eight byte wide registers Separate transmit and receive data registers double buffered to allow the DSP core and host processor to transfer data efficiently at high speed The host may access the HDI08 asynchronously by using polling techniques or interrupt based techniques The HDIOS appears to the host processor as a memory mapped peripheral occupying 8 bytes in the host processor address space See Table 6 8 The eight HDIO8 include the following Acontrol register ICR A status register ISR Three data registers RXH TXH RXM TXM and RXL TXL Two vector registers IVR and CVR These registers can be accessed only by the host processor Host processors may use standard host processor instructions e g byte move and addressing modes to communicate with the HDI08 registers The HDIOS registers are aligned so that 8 bit host processors can use 8 16 24 bit load and store instructions for data transfers The HOREQ HTRQ and HACK HRRQ handshake flags are provided for polled or interrupt driven data transfers with the host processor Because the DSP interrupt response most host microprocessors can load or store
94. DSR1 EQU SFFFFEB Source Address Register M DDR1 EQU SFFFFEA DMA1 Destination Address Register M DCO1 EQU SFFFFE9 DMA1 Counter M DCR1 EQU SFFFFE8 DMA1 Control Register Register Addresses Of DMA2 DSR2 EQU SFFFFE7 DMA2 Source Address Register M DDR2 EQU SFFFFE6 DMA2 Destination Address Register M DCO2 EQU SFFFFE5 DMA2 Counter M DCR2 EQU SFFFFE4 DMA2 Control Register Register Addresses Of DMA3 DSR3 EQU SFFFFE3 DMA3 Source Address Register M_DDR3 EQU SFFFFE2 DMA3 Destination Address Register M DCO3 EQU SFFFFE1 DMA3 Counter DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 B 8 Freescale Semiconductor Equates M DCR3 EQU SFFFFEO DMA3 Control Register Register Addresses DMA4 5 4 EQU SFFFFDF DMA4 Source Address Register M DDR4 EQU SFFFFDE DMA4 Destination Address Register M DCO4 EQU SFFFFDD DMA4 Counter M DCR4 EQU SFFFFDC DMA4 Control Register Register Addresses Of DMA5 M_DSR5 EQU SFFFFDB DMA5 Source Address Register M DDR5 EQU SFFFFDA DMA5 Destination Address Register M DCO5 EQU SFFFFD9 DMA5 Counter M DCR5 EQU SFFFFD8 DMA5 Control Register DMA Control Register M DSS EQU 3 DMA Source Space Mask DSS0 Dss1 M DSSO EQU 0 DMA Source Memory space 0 M DSS1 EQU 1 DMA Source Memory space 1 M DDS EQU C DMA Destination Space Mask DDS DDS1 M DDSO EQU 2 DMA Destination Memory Space 0 DDS1 EQU 3 DMA De
95. Digital Audio Interface DAX Signals 2 21 Table2 T4 Tim rSisgnal us usu us w a us yQ ed ERES 2 22 Table2 15 JFIAG OnCE Pferfac ayat SEDE Vd Net ain Pri basico 2 22 Table 3 1 Internal Memory Configurations c stre ne Rd Ehe is ad 3 1 Table 3 2 On chip Memory Locations 3 2 Table 3 3 On chip ROM Memory 3 2 Table 3 4 Internal I O Memory Map 3 12 Table 4 1 Operating Mode Register 4 2 Table 4 2 DSP56366 Operating Modes 4 4 Table 4 3 DSP56366 Mode Descriptions 4 5 Table 4 4 Interrupt Priority Level Bits u aede ERO wits aa 4 6 Table 4 5 Interrupt Sources Priorities Within an IPL 4 8 Table 4 6 DSP56360 Interrupt Vectors 4 10 Table 4 7 DIMA Request SOUECES a quotus du es 4 12 Table 4 8 Identification Register Configuration 4 13 Table 4 9 JT AG Identification Register Configuration 4 14 Table 4 10 DSP56366 BSR Bit Definition 4 14 Table 6 1 HDIOS Signal S mmaty esset aS e
96. ESAI Receive Slot and Word Length Selection 8 29 PCRC and Bits Functionality 8 48 EMUXR ESA ESAI 1 Pin Selection 9 5 Transmitter Clock Sources carier urt ee idis 9 6 Receiver Clock Sources asynchronous mode only 9 9 PCRE and Bits Functionality 9 14 DAX nterr pt Veetorg ides tiu s MEI Vales 10 4 DAX Intertupt BHO ou Ves tue VISUS Ms ED MICH Vs 10 4 Clock Souree Selectiolio sis cele per 10 7 Preamble tee yusa we ESI E acer edd eer E EARN 10 9 Examples of DMA configuration 10 11 DAX Port GPIO Control Register Functionality 10 13 Piescaler Source Selecto uu Ve a c dahl Rea 11 6 Timer Control Bits for Timer Q 11 8 Timer Control Bits for Timers 1 and2 11 8 Inverter INV Bit deus ua seite Y EY Sade 4 11 9 Internal TO Memory Map aas en s CR NUR D 2 DSP56366 Interrupt Vectors 22 cena cob wena a gua ug Usupa sua Rew OT D 8 Interrupt Sources Priorities Within an IPL D 10
97. FFFFB6 ESAI TRANSMIT CLOCK CONTROL REGISTER TCCR 5 ESAI TRANSMIT CONTROL REGISTER TCR X FFFFB4 ESAI COMMON CONTROL REGISTER SAICR X FFFFB3 ESAI STATUS REGISTER SAISR X FFFFB2 Reserved X FFFFB1 Reserved Reserved Reserved Reserved X FFFFAD Reserved X FFFFAC Reserved X FFFFAB ESAI RECEIVE DATA REGISTER 3 RX3 ESAI RECEIVE DATA REGISTER 2 RX2 RX3 RX2 X FFFFAQ ESAI RECEIVE DATA REGISTER 1 RX1 X FFFFA8 ESAI RECEIVE DATA REGISTER 0 7 Reserved X FFFFA6 ESAI TIME SLOT REGISTER TSR 5 ESAI TRANSMIT DATA REGISTER 5 TX5 X FFFFA4 ESAI TRANSMIT DATA REGISTER 4 TX4 X FFFFA3 ESAI TRANSMIT DATA REGISTER 3 TX3 X FFFFA2 ESAI TRANSMIT DATA REGISTER 2 TX2 X FFFFA1 ESAI TRANSMIT DATA REGISTER 1 TX1 X FFFFAO ESAI TRANSMIT DATA REGISTER 0 X FFFF9F Reserved X FFFF9E Reserved X FFFF9D Reserved X FFFF9C Reserved Reserved X FFFF9A Reserved X FFFF99 Reserved X FFFF98 Reserved DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 3 15 Internal Memory Table 3 4 Internal Memory Map continued
98. Flags Read Only DMA status bs 413 2 1 0 0 Mode Disabled HCP HrbE HRDF 1 Mode Enabled Host Status Register HSR X FFFFC3 Reset 2 Reserved Program as 0 Figure D 7 Host Control and Status Registers DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 D 22 Freescale Semiconductor Application OST 0108 Host Base Address Register HBAR X FFFFC5 Reset 80 Host Request Open Drain HDRQ HROD HREN HEW 0 0 1 0 1 1 1 0 1 1 1 1 Host Data Strobe Polarity 0 Strobe Active Low 1 Strobe Active High Host Address Strobe Polarity 0 Strobe Active Low 1 Strobe Active High Host Multiplexed Bus 0 Nonmultiplexed 1 Multiplexed Host Dual Data Strobe 0 Single Strobe 1 Dual Strobe Host Chip Select Polarity 0 HCS Active Low HTRQ amp HRRQ Enable 1 HCS Active High Host Request Polarity HDRQ HRP 0 0 Active Low 1 Active High 0 HTRQ HRRQ Active Low 1 HTRQ HRRQ Active High Host Acknowledge Polarity 0 HACK Active Low 1 HACK Active High Host Port Control Register HPCR X FFFFC4 Read Write Reset 0 Reserved Program as 0 Programming Sheets Date Programmer Sheet 3 of 6 14 11 la HCSP HDDS HASP HDSP HAEN HREN HCSEN HA9EN HGEN eeu 22 Host GPIO Port Enable 0 GPIO P
99. Frequency Clock for Receiver HCKR HCKR is a bidirectional pin providing the receivers high frequency clock for the ESAI interface The direction of this pin is determined by the RHCKD bit in the RCCR register In the asynchronous mode SYN 0 the HCKR pin operates as the high frequency clock input or output used by all the enabled receivers In the synchronous mode SYN 1 it operates as the serial flag 2 pin For further information on pin mode and definition see Table 8 9 and on receiver clock signals see Table 8 1 When this pin is configured as serial flag pin its direction is determined by the RHCKD bit in the RCCR register When configured as the output flag OF2 this pin reflects the value of the OF2 bit in the SAICR register and the data in the OF2 bit shows up at the pin synchronized to the frame sync being used by the transmitter and receiver sections When configured as the input flag IF2 the data value at the pin is stored in the IF2 bit in the SAISR register synchronized by the frame sync in normal mode or the slot in network mode HCKR may be programmed as a general purpose I O pin PC2 when the ESAI HCKR function is not being used 8 3 ESAI Programming Model The ESAI can be viewed as five control registers one status register six transmit data registers four receive data registers two transmit slot mask registers two receive slot mask registers and a DSP56366 24 Bit Digital Signal Processor User Manual Rev 4
100. HDIO8 Programming Model D 12 DSP56366 24 Bit Digital Signal Processor Rev 4 LOT 2 Freescale Semiconductor Preface This manual describes the DSP56366 24 bit digital signal processor DSP its memory operating modes and peripheral modules The DSP56366 is a member of the DSP56300 family of programmable CMOS DSPs Changes in core functionality specific to the DSP56366 are also described in this manual The DSP56366 is targeted to applications that require digital audio compression and decompression sound field processing acoustic equalization and other digital audio algorithms This manual is intended to be used with the following publications The DSP56300 Family Manual DSP56300FM which describes the CPU core programming models and instruction set details The DSP56366 Technical Data Sheet DSP56366 which provides electrical specifications timing pinout and packaging descriptions of the DSP56366 These documents as well as Freescale s DSP development tools can be obtained through a local Freescale Semiconductor Sales Office or authorized distributor To receive the latest information on this DSP access the Freescale DSP home page at the address given on the back cover of this document This manual contains the following sections and appendices SECTION 1 DSP56366 OVERVIEW Provides brief description of the DSP56366 including a features list and block diagra
101. Input Mode Select A External Interrupt Request A MODA IRQA is an active low Schmitt trigger input internally synchronized to the DSP clock MODA IRQA selects the initial chip operating mode during hardware reset and becomes a level sensitive or negative edge triggered maskable interrupt request input during normal instruction processing MODA MODB MODC and MODD select one of 16 initial chip operating modes latched into the OMR when the RESET signal is deasserted If the processor is in the stop standby state and the MODA IRQA pin is pulled to GND the processor will exit the stop state This input is 5 V tolerant MODB IRQB Input Input Mode Select B External Interrupt Request B MODB IRGB is an active low Schmitt trigger input internally synchronized to the DSP clock MODB IRQB selects the initial chip operating mode during hardware reset and becomes a level sensitive or negative edge triggered maskable interrupt request input during normal instruction processing MODA MODB MODC and MODD select one of 16 initial chip operating modes latched into OMR when the RESET signal is deasserted This input is 5 V tolerant MODC IRQC Input Input Mode Select C External Interrupt Request C MODC IRQC is an active low Schmitt trigger input internally synchronized to the DSP clock MODC IRQC selects the initial chip operating mode during hardware reset and becomes a level sensitive or negative edge triggered maskable interrupt
102. Interface ESAT 1 5 5 Enhanced Serial Audio Interface 1 ESAI 1 The ESAI 1 is a second ESAI interface with just 6 dedicated pins instead of the 12 pins of the full ESAI Four data pins are shared with the ESAI while the two high frequency clock pins are not available Other than the available pins ESAI 1 is functionally identical to ESAI For more information on the ESAI 1 refer to Section 9 Enhanced Serial Audio Interface 1 ESAI 1 1 5 6 Serial Host Interface SHI The SHI is a serial input output interface providing a path for communication and program coefficient data transfers between the DSP and an external host processor The SHI can also communicate with other serial peripheral devices The SHI can interface directly to either of two well known and widely used synchronous serial buses the Freescale serial peripheral interface SPI bus and the Philips inter integrated circuit control PC bus The SHI supports either the SPI or bus protocol as required from a slave or a single master device To minimize DSP overhead the SHI supports single double and triple byte data transfers The SHI has a 10 word receive FIFO that permits receiving up to 30 bytes before generating a receive interrupt reducing the overhead for data reception For more information on the SHI refer to Section 7 Serial Host Interface 1 5 7 Digital Audio Transmitter DAX The DAX is a serial audio interface module that outputs digital audio dat
103. Internal Memory Peripheral Address Register Name DMA1 X SFFFFEB DMA SOURCE ADDRESS REGISTER DSR1 X FFFFEA DMA DESTINATION ADDRESS REGISTER DDR1 X FFFFEQ DMA COUNTER DCO1 X FFFFE8 DMA CONTROL REGISTER DCR1 DMA2 X FFFFE7 DMA SOURCE ADDRESS REGISTER DSR2 X FFFFE6 DMA DESTINATION ADDRESS REGISTER DDR2 5 DMA COUNTER DCO2 X FFFFE4 DMA CONTROL REGISTER DCR2 DMA3 X FFFFE3 DMA SOURCE ADDRESS REGISTER DSR3 X FFFFE2 DMA DESTINATION ADDRESS REGISTER DDR3 X FFFFE1 DMA COUNTER DCO3 DMA CONTROL REGISTER DCR3 DMA4 X FFFFDF DMA SOURCE ADDRESS REGISTER DSR4 X FFFFDE DESTINATION ADDRESS REGISTER DDR4 X FFFFDD COUNTER DCO4 X FFFFDC DMA CONTROL REGISTER DCR4 5 X FFFFDB SOURCE ADDRESS REGISTER DSR5 X FFFFDA DESTINATION ADDRESS REGISTER DDR5 X FFFFD9 DMA COUNTER DCO5 X FFFFD8 DMA CONTROL REGISTER DCR5 PORT D X SFFFFD7 PORT D CONTROL REGISTER PCRD X FFFFD6 PORT D DIRECTION REGISTER PRRD X FFFFD5 PORT D DATA REGISTER PDRD DAX X FFFFD4 DAX STATUS REGISTER XSTR X FFFFD3 DAX AUDIO DATA REGISTER B XADRB X FFFFD2 DAX AUDIO DATA REGISTER A XADRA X FFFFD1 DAX NON AUDIO DATA REGISTER XNADR X FFFFDO DAX CONTROL REGISTER XCTR X FFFFCF Reserved X FFFFCE Reserved X FFFFCD Re
104. M HDM2 EQU 5 SHI Divider Modulus Select HDM2 M HDM1 EQU 4 SHI Divider Modulus Select HDM1 M HDM0 EQU 3 SHI Divider Modulus Select HDMO M HRS EQU 2 SHI Prescalar Rate Select HRS M CPOL EQU 1 SHI Clock Polarity CPOL M CPHA EQU 0 SHI Clock Phase CPHA EQUATES for ESAI 1 Registers register bit equates can be the same as for the ESAI register bit equates Register Addresses M EMUXR EQU SFFFFAF MUX PIN CONTROL REGISTER EMUXR M_RSMB 1 EQU SFFFF9C ESAI 1 Receive Slot Mask Register B RSMB 1 M RSMA 1 EQU SFFFF9B ESAI_1 Receive Slot Mask Register A RSMA_1 M TSMB 1 EQU SFFFF9A ESAI 1 Transmit Slot Mask Register B TSMB 1 M TSMA 1 EQU SFFFF99 ESAI 1 Transmit Slot Mask Register A TSMA 1 M RCCR 1 EQU SFFFF98 ESAI 1 Receive Clock Control Register RCCR 1 DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 B 20 Freescale Semiconductor M RCR 1 M TCR 1 M RX3 1 EQU M TCCR 1 EQU EQU M SAICR 1 EQU M SAISR 1 EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU SFFFF97 SFFFF96 SFFFF95 SFFFF94 SFFFF93 SFFFF8B SFFFF8A SFFFF89 SFFFF88 SFFFF86 SFFFF85 SFFFF84 SFFFF83 SFFFF82 SFFFF81 SFFFF80 ESAI 1 ESAI 1 ESAI 1 ESAI 1 Equates Receive Control Register RCR 1 Transmit Clock Control Register TCCR 1 Transmit Control Register TCR 1 Control Registe
105. NT RESERVED 0800 2K INTERNAL 13K INTERNAL 7K INTERNAL 0000 RAM 0000 0000 RAM 1K I CACHE ENABLED Figure 3 10 Memory Maps for MSWz X X 1 5 0 5 1 DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 3 7 Data and Program Memory Maps PROGRAM X DATA Y DATA SFFFF SFFFF INTERNAL FFFF EXTERNAL FF80 128 words FFB0 80 words INTERNAL 48words FF80 EXTERNAL EXTERNAL EXTERNAL C000 6000 32K INTERNAL 8K INTERNAL ROM ROM AK 009 INT RESERVED INT RESERVED 2000 gt 1400 2800 10K INTERNAL 8K INTERNAL 5K INTERNAL 0000 RAM 0000 RAM 0000 RAM Figure 3 11 Memory Maps for MSW 0 0 0 5 1 5 1 PROGRAM X DATA Y DATA FFFF FFFF INTERNAL I O FFFF EXTERNAL FF80 128 words FFBO 80 words INTERNAL I O 48 words FF80 EXTERNAL EXTERNAL EXTERNAL 000 6000 32K INTERNAL 8K INTERNAL ROM ROM MM INT RESERVED INT RESERVED 2000 S 1C00 2400 1C00 INT RESERVED 7K INTERNAL 8K INTERNAL 7K INTERNAL 0000 RAM 0000 RAM 0000 RAM Figure 3 12 Memory Maps for MSW 0 1 CE 0 MS 1 SC 1 DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 3 8 Freescale Semiconductor Data and Program Memory Maps
106. Programming Model R T SHFD 0 DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 8 38 Freescale Semiconductor ESAI Programming Model 23 16 15870 d ESAI RECEIVE DATA REGISTER RECEIVE HIGH MIDDLE BYTERECEIVE LOW BYTE READ ONLY 7 0 7070 23 16 15870 RECEIVE HIGH BYTERECAVE MIDDLE BYTERECEIVE LOW BYTE ESAI RECEIVE SHIFT REGISTER 7 0 7070 MSB LSB 8 BIT DATA 0 0 0 0 LSB 12 BIT DATA MSB LSB 16 BIT DATA MSB LSB 20 BIT DATA LS 24 BIT DATA LEAST SIGNIFICANT ZERO FILL NOTES a Receive Reaisters 1 Data is received LSB first if RSHFD 1 g 2 24 bit fractional format ALC 0 3 32 bit mode is not shown 23 16 15870 TRANSMIT HIGH BYTETRANSMIT MIDDLE BYTETRANSMIT LOW BYTE ESAI TRANSMIT DATA REGISTER WRITE ONLY ESAI TRANSMIT SHIFT REGISTER MSB 12 DATA MSB LSB TSW 8 BITDATA 0 0 0 puc LSB MSB LSB 16 BIT DATA 20 81 DATA LSB MSB LSB 5 24 BIT DATA M NOTES b Transmit Registers 1 Data is sent LSB first if TSHFD 1 2 24 bit fractional format ALC 0 3 32 bit mode is not shown 4 Data word is left aligned TWA 0 PADC 1 Figure 8 14 ESAI Data Path Programming Model R T SHFD 1 DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale S
107. SAICR Alignment Control ALC Bit 8 The ESAI is designed for 24 bit fractional data thus shorter data words are left aligned to the MSB bit 23 Some applications use 16 bit fractional data In those cases shorter data words may be left aligned to bit 15 The Alignment Control ALC bit supports these applications If ALC is set transmitted and received words are left aligned to bit 15 in the transmit and receive shift registers If ALC is cleared transmitted and received word are left aligned to bit 23 in the transmit and receive shift registers NOTE While ALC is set 20 bit and 24 bit words may not be used and word length control should specify 8 12 or 16 bit words otherwise results are unpredictable DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 8 33 ESAI Programming Model ASYNCHRONOUS SYN 0 TRANSMITTER EXTERNAL TRANSMIT CLOCK ESAI BIT INTERNAL CLOCK CLOCK EXTERNAL RECEIVE CLOCK SCKR O EXTERNAL TRANSMIT FRAME SYNC I INTERNAL FRAME SYNC 4 EXTERNAL RECEIVE FRAME SYNC RECEIVER NOTE Transmitter and receiver may have different clocks and frame syncs SYNCHRONOUS SYN 1 TRANSMITTER EXTERNAL FRAME SYNC EXTERNAL CLOCK SCKT O ESAI BIT INTERNAL CLOCK INTERNAL FRAME SYNC CLOCK RECEIVER NOTE Transmitter and receiver have the same clocks and frame syncs Figure 8 11 SAICR SYN Bit Operation 8 3 6 ESAI Status Register SAISR
108. Signal Processor Rev 4 Freescale Semiconductor TOC 5 8 2 10 Frame Syne for Transmitter FST d aay ae eee Vah no WA Ma Mex 2 5 8 7 8 2 11 High Frequency Clock for Transmitter 8 7 8 2 12 High Frequency Clock for Receiver 8 7 892 JESAI Programming Model usse E DURAS FERA RU SENA 8 7 8 3 1 ESAI Transmitter Clock Control Register 8 8 8 3 1 1 TCCR Transmit Prescale Modulus Select 7 Bits 0 7 8 8 8 3 1 2 TCCR Transmit Prescaler Range TPSR Bit8 8 9 8 3 1 3 TCCR Tx Frame Rate Divider Control TDCA TDCO Bits 9 13 8 10 8 3 1 4 TCCR Tx High Frequency Clock Divider TFP3 TFPO Bits 14 17 8 11 8 3 1 5 TCCR Transmit Clock Polarity TCKP Bit 18 8 12 8 3 1 6 TCCR Transmit Frame Sync Polarity TFSP Bit 19 8 12 8 3 1 7 TCCR Transmit High Frequency Clock Polarity THCKP Bit20 8 12 8 3 1 8 TCCR Transmit Clock Source Direction TCKD 21 8 12 8 3 1 9 TCCR Transmit Frame Sync Signal Direction TFSD Bit22 8 12 8 3 1 10 TCCR Transmit High Frequency Clock Direction THCKD Bit23 8 12 8 3 2 ESAI Transmit Control Register TCR 8 12 8
109. Signal Processor User Manual Rev 4 2 18 Freescale Semiconductor Enhanced Serial Audio Interface 1 2 10 Enhanced Serial Audio Interface 1 Table 2 12 Enhanced Serial Audio Interface 1 Signals Signal Name Signal Type State during Reset Signal Description FSR 1 PE1 Input or output Input output or disconnected GPIO disconnected Frame Sync for Receiver 1 This is the receiver frame sync input output signal In the asynchronous mode 5 0 the FSR operates as the frame sync input or output used by all the enabled receivers In the synchronous mode SYN 1 it operates as either the serial flag 1 pin TEBE O or as the transmitter external buffer enable control 1 RFSD 1 When this pin is configured as serial flag pin its direction is determined by the RFSD bit in the RCCR register When configured as the output flag OF1 this pin will reflect the value of the OF1 bit in the SAICR register and the data in the OF1 bit will show up at the pin synchronized to the frame sync in normal mode or the slot in network mode When configured as the input flag IF1 the data value at the pin will be stored in the IF1 bit in the SAISR register synchronized by the frame sync in normal mode or the slot in network mode Port E 1 When the ESAI is configured as GPIO this signal is individually programmable as input output or internally disconnected The default state after reset is GPIO d
110. Signal Processor User Manual Rev 4 C 8 Freescale Semiconductor Appendix D Programmer s Reference D 1 Introduction This section has been compiled as a reference for programmers It contains a table showing the addresses of all the DSPs memory mapped peripherals an interrupt address table an interrupt exception priority table a quick reference to the host interface and programming sheets for the major programmable registers on the DSP D 1 1 Peripheral Addresses Table D 1 lists the memory addresses of all on chip peripherals D 1 2 Interrupt Addresses Table D 2 lists the interrupt starting addresses and sources D 1 3 Interrupt Priorities Table D 3 lists the priorities of specific interrupts within interrupt priority levels D 1 4 Host Interface Quick Reference Table D 4 is a quick reference guide to the host interface 08 D 1 5 Programming Sheets The remaining figures describe major programmable registers on the DSP56366 D 2 Internal Memory DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor D 1 Internal Memory Table D 1 Internal Memory Peripheral Address Register Name IPR X FFFFFF INTERRUPT PRIORITY REGISTER CORE IPR C X FFFFFE INTERRUPT PRIORITY REGISTER PERIPHERAL IPR P PLL X FFFFFD PLL CONTROL REGISTER PCTL ONCE X FFFFFC ONCE GDB REGISTER OGDB BIU X FFFFFB BUS CONTROL REGISTER BCR
111. Slot Mask Registers TSMA and TSMB two read write registers used by the transmitters in network mode to determine for each slot whether to transmit a data word and generate a DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 8 40 Freescale Semiconductor ESAI Programming Model transmitter empty condition TDE 1 or to tri state the transmitter data pins TSMA and TSMB should each be considered as containing half a 32 bit register TSM See Figure 8 15 and Figure 8 16 Bit number N in TSM TS is the enable disable control bit for transmission in slot number N 11 10 9 8 7 6 5 4 3 2 1 0 X FFFFB9 TS11 TS10 TS9 TS8 TS7 TS6 TS5 TS4 TS3 TS2 TS1 TSO 23 22 21 20 19 18 17 16 15 14 13 12 TS15 TS14 TS13 TS12 Reserved bit read as zero should be written with zero for future compatibility Figure 8 15 TSMA Register 11 10 9 8 7 6 5 4 3 2 1 0 X FFFFBA TS27 TS26 TS25 TS24 TS23 TS22 TS21 TS20 TS19 TS18 TS17 TS16 23 22 21 20 19 18 17 16 15 14 13 12 TS31 TS30 TS29 TS28 Reserved bit read as zero should be written with zero for future compatibility Figure 8 16 TSMB Register When bit number N in TSM is cleared all the transmit data pins of the enabled transmitters are tri stated during transmit time
112. Strobe HDDS Bit 12 6 14 6 5 6 14 HPCR Host Chip Select Polarity HCSP Bit 13 6 15 6 5 6 15 HPCR Host Request Polarity HRP BIt14 6 15 6 5 6 16 HPCR Host Acknowledge Polarity HAP Bit 15 6 15 6 5 7 Data direction register 6 15 6 5 8 Host Data Register HDR Ju ed y eoe d o sur a ATO e RAT 6 16 6 5 9 DSP Side Registers After Reset 6 16 6 5 10 Host Interface DSP Core Interrupts 6 17 6 6 HDI08 External Host Programmer s 1 6 18 6 6 1 Interface Control Register ICR 6 19 6 6 1 1 ICR Receive Request Enable RREQ Bit O 6 20 6 6 1 2 ICR Transmit Request Enable TREQ Bit 6 20 6 6 1 3 ICR Double Host Request HDRQ Bit 2 6 21 DSP56366 24 Bit Digital Signal Processor Rev 4 Freescale Semiconductor TOC 3 6 6 1 4 ICR Host Flag 0 HEU BIS 5 2 ond ha Sor Wibe hodie Sq ach hio d Was dub Seach rufa 6 21 6 6 1 5 ICR Host Flag HET Bit Fe eat e e RON 6 21 6 6 1 6 ICR Host Little Endian HEEND Bit 5 6 22 6 6 1 7 TCR Initialize Bit
113. TXH RXL TXL Receive Transmit 6 RXM TXM RXM TXM Bytes 7 RXL TXL RXH TXH Host Data Bus Host Data Bus H0 H7 H0 H7 The RXH TXH register is always mapped to the most significant byte of the DSP word 6 6 1 Interface Control Register ICR The ICR is an 8 bit read write control register used by the host processor to control the HDI08 interrupts and flags The ICR cannot be accessed by the DSP core The ICR is a read write register which allows the use of bit manipulation instructions on control register bits The control bits are described in the following paragraphs Bits 2 5 and 6 of the ICR are affected by the condition of HDM 2 0 HCR bits 5 7 as shown in Figure 6 12 DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 6 19 HDIO8 External Host Programmer s Model 7 6 5 4 3 2 1 0 For HDM 2 0 2000 INIT HLEND HF1 HFO HDRQ TREQ RREQ For HDM 2 0 100 INIT 1 HMO HF1 HFO TREQ RREQ For HDM1 1 and or HDMO 1 INIT HDM1 HDMO HF1 HFO TREQ RREQ 0 These read only bits reflect the value of the HDM 1 0 bits in the HCR Reserved bit Read as 0 Should be written with O for future compatibility Figure 6 12 Interface Control Register ICR 6 6 1 1 ICR Receive Request Enable RREQ Bit 0 In interrupt mode HDM 2 0 000 or HM 1 0 00 RREQ is used to enable host receive data requests via the host re
114. Transmit Interrupt Enable TIE Bit22 8 22 8 3 2 19 TCR Transmit Last Slot Interrupt Enable 23 8 22 8 3 3 ESAI Receive Clock Control Register RCCR 8 22 8 3 3 1 RCCR Receiver Prescale Modulus Select RPM7 RPMO Bits 7 0 8 23 8 3 3 2 RCCR Receiver Prescaler Range RPSR Bit8 8 23 8 3 3 3 RCCR Rx Frame Rate Divider Control RDCA RDCO Bits 9 13 8 23 8 3 3 4 RCCR Rx High Frequency Clock Divider RFP3 RFPO Bits 14 17 8 23 8 3 3 5 RCCR Receiver Clock Polarity RCKP Bit 18 8 24 8 3 3 6 RCCR Receiver Frame Sync Polarity RFSP Bit 19 8 24 8 3 3 7 RCCR Receiver High Frequency Clock Polarity 20 8 24 8 3 3 8 RCCR Receiver Clock Source Direction RCKD 21 8 24 8 3 3 9 RCCR Receiver Frame Sync Signal Direction RFSD Bit22 8 25 DSP56366 24 Bit Digital Signal Processor Rev 4 TOC 6 Freescale Semiconductor 8 3 3 10 8 3 4 8 3 4 1 8 3 4 2 8 3 4 3 8 3 4 4 8 3 4 5 8 3 4 6 8 3 4 7 8 3 4 8 8 3 4 9 8 3 4 10 8 3 4 11 8 3 4 12 8 3 4 13 8 3 4 14 8 3 4 15 8 3 4 16 8 3 5 8 3 5 1 8 3 5 2 8 3 5 3 8 3 5 4 8 3 5 5 8 3 5 6 8 3 5 7 8 3 6 8 3 6 1 8 3 6 2 8 3 6 3 8 3 6 4 8 3 6 5 8 3 6 6 8 3 6 7 8 3 6 8 8 3 6 9 8 3 6 10 8 3 6 11 8 3
115. a a al a ase Mami ouai DL 1 4 Data AEU Resister ss 5 OP aed 1 4 Multiplier Aecumulator MAC 1 4 Address Generation Unit AGU 1 5 Program Control e eese e ROI e e Re Fre es 1 5 Internal Buses 2 24225 b u ep pet p ES 1 6 Direct Memory Access DMA sexes Rx enema Un RECS E UEA 1 6 PLE based Clock Oscillator yee owt ua deeper etuer eate EOD ede utet xatd 1 7 TAP and ONCE Module 5 532952 Pra pas asua dd 1 7 Ou C hip Memon yr y itn 1 7 Off Chip Memory Expansion sur xr RE RET a 1 8 Peripheral Overview VAY TIONES 1 8 Host Interface HDI08 Leyes ht PRE EO OE E RUP 1 9 General Purpose Input Output 4 1 9 Triple Timer TEC Roses a ce 1 9 Enhanced Serial Audio Interface ESAD 1 10 Enhanced Serial Audio Interface 1 ESAT 1 1 10 Serial Host Interface SHD no eines 1 10 Digital Audio Transmitter DA X 1 10 Signal Connection Descriptions 2 1 Signal Groupings x conce WES ps VEN RIO MERE Tq WELT HS IPS 2 1 POWT x asas ss Saa
116. are shifted out MSB first on the SDA line Following each transmitted byte the SHI controller samples the SDA line at the ninth clock pulse and inspects the ACK status If the transmitted byte was acknowledged ACK 0 the SHI controller continues and transmits the next byte However if it was not acknowledged ACK 1 the transmit session is stopped and the SDA line is released Consequently the external master device may generate a stop event in order to terminate the session contents are transferred to IOSR when the complete word according to HM 1 0 has been shifted out It is therefore the responsibility of the programmer to select the correct number of bytes in an frame so that they fit in a complete number of words For this purpose the slave device address byte does not count as part of the data therefore it is treated separately In a transmit session only the transmit path is enabled and the IOSR to HRX FIFO transfers are inhibited When the HTX transfers its valid data word to IOSR the HTDE status bit is set and the DSP may write a new data word to HTX with either DSP instructions or DMA transfers If HCKFR is cleared and both IOSR and HTX are empty when the master device attempts a transmit session an underrun condition occurs setting the HTUE status bit and the previous word is retransmitted If HCKFR is set and both IOSR and HTX are empty when the master device attempts a transmit session the SHI holds
117. as well as the desired clock polarity and phase format see Figure 7 6 The SS line allows selection of an individual slave SPI device slave devices that are not selected do not interfere with SPI bus activity i e they keep their MISO output pin in the high impedance state When the SHI is configured as an SPI master device the SS line should be held high If the SS line is driven low when the SHI is in SPI master mode a bus error is generated the HCSR HBER bit is set 7 6 Characteristics Of The Bus The 2 serial bus consists of two bidirectional lines one for data signals SDA and one for clock signals SCL Both the SDA and SCL lines must be connected to a positive supply voltage via a pull up resistor NOTE In the bus specifications the standard mode 100 kHz clock rate and a fast mode 400 kHz clock rate are defined The SHI can operate in either mode DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 7 16 Freescale Semiconductor Characteristics Of The I2C Bus 7 6 1 Overview The C bus protocol must conform to the following rules e Data transfer may be initiated only when the bus is not busy During data transfer the data line must remain stable whenever the clock line is high Changes in the data line when the clock line is high are interpreted as control signals see Figure 7 7 X M Data Valid Allowed AA0422 Figure 7 7 Bit Transfer Accordingly
118. assuming no accesses to the affected address ranges of the data memory occur up to 3 instructions after the instruction that changes the OMR bit Special care should be taken in relation to the interrupt vector routines since an interrupt could cause the DSP to fetch instructions out of sequence and might violate the switch condition Special attention should be given when running a memory switch routine using the OnCE port Running the switch routine in Trace mode for example can cause the switch to complete after the MS bit change DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 3 11 Internal Memory while the DSP is in Debug mode As a result subsequent instructions might be fetched according to the new memory configuration after the switch and thus might execute improperly 3 1 5 External Memory Support The DSP56366 does not support the SSRAM memory type It does support SRAM and DRAM as indicated in the DSP56300 24 Bit Digital Signal Processor Family Manual Freescale publication DSP56300FM Also care should be taken when accessing external memory to ensure that the necessary address lines are available For example when using glueless SRAM interfacing it is possible to directly address 3 x 218 memory locations 768k when using the 18 address lines and the three programmable address attribute lines 3 2 Internal Memory The DSP56366 on chip peripheral modules
119. before it is written to the DI bit If the INV bit 15 cleared the value of the TIOO signal is written directly to the DI bit DI is cleared by the hardware RESET signal or the software RESET instruction 11 3 4 9 TCSR Data Output DO Bit 13 The DO bit is the source of the TIOO value when it is a data output signal The TIOO signal is data output when the GPIO mode is enabled and DIR is set A value written to the DO bit is written to the TIOO signal Ifthe INV bit is set the value of the DO bit is inverted when written to the TIOO signal When the INV bit is cleared the value of the DO bit is written directly to the TIOO signal When GPIO mode is disabled writing the DO bit has no effect DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 11 10 Freescale Semiconductor Timer Event Counter Programming Model The DO bit is cleared by the hardware RESET signal or the software RESET instruction This bit is not in use for timers 1 and 2 It should be left cleared 11 3 4 10 TCSR Prescaler Clock Enable PCE Bit 15 The PCE bit is used to select the prescaler clock as the timer source clock When the PCE bit is cleared the timer uses either an internal CLK 2 signal or an external signal TIOO as its source clock When the PCE bit 15 set the prescaler output is used as the timer source clock for the counter regardless of the timer operating mode To ensure proper operation the PCE bit should be changed only when the tim
120. bus 00 023 Otherwise WR is tri stated Input Ignored Input Transfer Acknowledge If the DSP is the bus master and there is no external bus activity or the DSP is not the bus master the TA input is ignored The TA input is a data transfer acknowledge DTACK function that can extend an external bus cycle indefinitely Any number of wait states 1 2 infinity may be added to the wait states inserted by the BCR by keeping TA deasserted In typical operation TA is deasserted at the start of a bus cycle is asserted to enable completion of the bus cycle and is deasserted before the next bus cycle The current bus cycle completes one clock period after TA is asserted synchronous to the internal system clock The number of wait states is determined by the TA input or by the bus control register BCR whichever is longer The BCR can be used to set the minimum number of wait states in external bus cycles In order to use the TA functionality the BCR must be programmed to at least one wait state A zero wait state access cannot be extended by TA deassertion otherwise improper operation may result TA can operate synchronously or asynchronously depending on the setting of the TAS bit in the operating mode register OMR TA functionality may not be used while performing DRAM type accesses otherwise improper operation may result Output Output deasserted Bus Request BR is an active low output never
121. clock This process is repeated until the TE bit is cleared disabling the timer The TLR value in the TCPR sets the delay between starting the timer and toggling the TIOO signal To generate output signals with a delay of X clock cycles between toggles the TLR value should be set to X 2 and the TRM bit should be set This process is repeated until the timer is disabled 1 TE is cleared If the counter overflows the TOF bit is set and if TOIE is set an overflow interrupt is generated The counter contents can be read at any time by reading the TCR 11 4 1 4 Timer Event Counter Mode 3 Bit Settings Mode Characteristics TC3 TC2 TC1 TCO TIOO Clock KIND NAME 0 0 1 1 Input External 3 Timer Event Counter In this mode the timer counts internal events and issues an interrupt when a preset number of events is counted Timer 0 can also count external events Set the TE bit to clear the counter and enable the timer The number of events the timer is to count is loaded into the TPCR The counter is loaded with the TLR value when the first timer clock signal is received The timer clock signal is provided by the prescaler clock output Timer 0 can be also be clocked from the TIOO input signal Each subsequent clock signal increments the counter If an external clock is used it must be internally synchronized to the internal clock and its frequency must be less than the DSP56366 internal operating
122. data and then outputs the result through the biphase encoder to the ADO pin at the last two time slots This is the end of the first channel A subframe transmission The second subframe transmission channel B starts with the preamble generator generating the channel B preamble Y preamble At the same time channel B audio and non audio data is transferred to the XADSR shift register from the XADBUFB and XNADBUF registers The generated Y preamble is output immediately after the channel A parity and is followed by the audio and non audio data in the XADSR which is in turn followed by the calculated parity for channel B This completes a frame transmission When the channel B parity is sent the audio data for the next frame stored in XADBUFA and the non audio data bits from the XNADR are uploaded to XADSR 10 4 DAX Programming Model The programmer accessible DAX registers are shown in Figure 10 2 The registers are described in the following subsections The Interrupt Vector table for the DAX is shown in Table 10 1 The internal interrupt priority is shown in Table 10 2 DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 10 3 DAX Internal Architecture Table 10 1 DAX Interrupt Vectors Condition Address Description XAUR VBA 28 DAX transmit underrun error XADE amp XBLK VBA 2A DAX block transferred XADE VBA 2bE DAX audio data register empty Table 10 2 DAX Interru
123. data at their maximum programmed I O instruction rate without testing the handshake flags for each transfer If full handshake is not needed the host processor can treat the DSP as a fast device and data can be transferred between the host processor and the DSP at the fastest host processor data rate DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 6 18 Freescale Semiconductor HDI08 External Host Programmer s Model One of the most innovative features of the host interface 15 the host command feature With this feature the host processor can issue vectored interrupt requests to the DSP core The host may select any of 128 DSP interrupt routines to be executed by writing a vector address register in the HDI08 This flexibility allows the host programmer to execute up to 128 pre programmed functions inside the DSP For example host interrupts can allow the host processor to read or write DSP registers X Y or program memory locations force interrupt handlers e g IRQA IRQB etc interrupt routines and perform control and debugging operations if interrupt routines are implemented in the DSP to perform these tasks Table 6 8 HDI08 Host Side Register Map Host Big Endian Little Endian Function Address HLEND 0 HLEND 1 0 ICR ICR Interface Control 1 CVR CVR Command Vector 2 ISR ISR Interface Status 3 IVR IVR Interrupt Vector 4 00000000 00000000 Unused 5 RXH
124. demand mode with an internally generated bit clock the SDO4 SDII pin becomes high impedance for a full clock period after the last data bit has been transmitted assuming another data word does not follow immediately If a data word follows immediately there is no high impedance interval SDO4 SDI1 may be programmed as a general purpose I O PC7 when ESAI SDO4 and SDII functions are not being used 8 2 6 Serial Transmit 5 Receive 0 Data Pin SDO5 SDIO SDOS SDIO is used as the SDOS signal for transmitting data from the TX5 serial transmit shift register when programmed as transmitter pin or as the SDIO signal for receiving serial data to the RXO serial shift register when programmed as a receiver pin SDOS SDIO is an input when data is being received by the RXO shift register SDOS SDIO 15 an output when data is being transmitted from the TX5 shift register In the on demand mode with an internally generated bit clock the SDOS SDIO pin becomes high impedance for a full clock period after the last data bit has been transmitted assuming another data word does not follow immediately If a data word follows immediately there is no high impedance interval SDOS SDIO may be programmed as a general purpose I O pin PC6 when the ESAI 5005 and SDIO functions are not being used 8 2 7 Receiver Serial Clock SCKR SCKR is a bidirectional pin providing the receivers serial bit clock for the ESAI interface The direction of this pin is deter
125. divide ratio from 1 to 256 TPM 7 0 00 to may be selected The bit clock output is available at the transmit serial bit clock SCKT pin of the DSP The bit clock output is also available internally for use as the bit clock to shift the transmit and receive shift registers The ESAI transmit clock generator functional diagram is shown in Figure 8 3 DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 8 8 Freescale Semiconductor ESAI Programming Model RHCKD 1 Foss PRESCALE DIVIDER DIVIDER DIVIDE DIVIDE BY DIVIDE BY DIVIDE BY BY2 1 1 1 OR TO DIVIDE TO DIVIDE RHCKD 0 gt RPMO RPM7 RFPO RFP3 FLAGO OUT FLAGO IN INTERNAL BIT CLOCK SYNC MODE SYNC MODE RSWS4 RSWSO RX WORD CLOCK RX WORD LENGTH DIVIDER RX SHIFT REGISTER TSWS4 TSWSO TX WORD LENGTH DIVIDER TX SHIFT REGISTER RCLOCK TCLOCK INTERNAL BIT CLOCK TX WORD CLOCK TPM7 gt THCKD 0 DIVIDE BY 2 DIVIDE BY DIVIDE BY DIVIDE BY 1 1 1 Foss THCKD 1 OR DIVIDE BY TO DIVIDE TO DIVIDE BY 256 BY 16 Notes 1 is the DSP56300 Core internal clock frequency Figure 8 3 ESAI Clock Generator Functional Block Diagram 8 3 1 2 TCCR Transmit Prescaler Range TPSR Bit 8 The TPSR bit controls a fixed divide by eight prescaler in series with the variable prescaler This bit is
126. external bit clock when the associated frame sync I O is asserted The number of bits shifted out before the shift registers are considered empty and may be written to again can be 8 12 16 20 24 or 32 bits determined by the slot length control bits in the TCR 1 register Data is shifted out of these registers MSB first if TSHFD 0 and LSB first if TSHFD 1 9 3 11 ESAI 1 Transmit Data Registers The Transmit Data registers TX5 1 TX4 1 TX3 1 TX2 1 1 and TXO 1 are 24 bit write only registers Data to be transmitted is written into these registers and is automatically transferred to the transmit shift registers The data written 8 12 16 20 or 24 bits should occupy the most significant portion of the TXx 1 according to the ALC control bit setting The unused bits least significant portion and the 8 most significant bits when ALC 1 of the TXx 1 are don t care bits The DSP is interrupted whenever the TXx 1 becomes empty if the transmit data register empty interrupt has been enabled DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 9 11 ESAI 1 Programming Model 9 3 12 ESAI 1 Time Slot Register 1 The write only Time Slot Register 1 is effectively a null data register that is used when the data is not to be transmitted in the available transmit time slot The transmit data pins of all the enabled transmitters are in the high impedance state for the respective time slot
127. for external program and data memory accesses Otherwise DO D23 are tri stated 2 5 3 External Bus Control Table 2 7 External Bus Control Signals State during 225 Signal Name Type Reset Signal Description AAO AA2 RASO Output Tri stated Address Attribute or Row Address Strobe When defined as AA these RAS2 signals can be used as chip selects or additional address lines When defined as RAS these signals can be used as RAS for DRAM interface These signals are tri statable outputs with programmable polarity CAS Output Tri stated Column Address Strobe When the DSP is the bus master CAS is an active low output used by DRAM to strobe the column address Otherwise if the bus mastership enable BME bit in the DRAM control register is cleared the signal is tri stated RD Output Tri stated Read Enable When the DSP is the bus master RD is an active low output that is asserted to read external memory on the data bus DO D23 Otherwise RD is tri stated DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 2 5 External Memory Expansion Port Port A Table 2 7 External Bus Control Signals continued Signal Name WR Type Output State during Reset Tri stated Signal Description Write Enable When the DSP is the bus master WR is an active low output that is asserted to write external memory on the data
128. from the TX1 serial transmit shift register SDOI is an output when data is being transmitted from the TX1 shift register In the on demand mode with an internally generated bit clock the SDOI pin becomes high impedance for a full clock period after the last data bit has been transmitted assuming another data word does not follow immediately If a data word follows immediately there is no high impedance interval 5001 may be programmed as a general purpose I O pin PC10 when the ESAI SDOI function is not being used 8 2 3 Serial Transmit 2 Receive Data Pin SDO2 SDIS SDO2 SDI3 is used as the SDO2 for transmitting data from the TX2 serial transmit shift register when programmed as a transmitter pin or as the SDI3 signal for receiving serial data to the RX3 serial receive shift register when programmed as a receiver pin SDO2 SDI3 is an input when data is being received by the RX3 shift register SDO2 SDI3 is an output when data is being transmitted from the TX2 shift register In the on demand mode with an internally generated bit clock the SDO2 SDI3 pin becomes high impedance for a full clock period after the last data bit has been transmitted assuming another data word does not follow immediately If a data word follows immediately there is no high impedance interval SDO2 SDI3 may be programmed as a general purpose I O pin PC9 when the ESAI SDO2 SDI3 functions are not being used DSP56366 24 Bit Digital Signal Processor User
129. host processor first performs a data read transfer to read the ISR register This allows the host processor to assess the status of the HDIO08 1 If RXDF 1 the receive byte registers are full and therefore a data read can be performed by the host processor 2 If TXDE 1 the transmit byte registers are empty A data write be performed by the host processor 3 If TRDY 1 the transmit byte registers and the receive data register on the DSP side are empty Data written by the host processor is transferred directly to the DSP side 4 If HF2 Z 0 depending on how the host flags have been defined may indicate an application specific state within the DSP core has been reached Intervention by the host processor may be required 5 If HREQ 1 the HOREQ HTRQ HRRQ signal has been asserted and the DSP 15 requesting the attention of the host processor One of the previous four conditions exists After the appropriate data transfer has been made the corresponding status bit is updated to reflect the transfer If the host processor has issued a command to the DSP by writing the CVR and setting the HC bit it can read the HC bit in the CVR to determine when the command has been accepted by the interrupt controller in the DSP core When the command has been accepted for execution the HC bit is cleared by the interrupt controller in the DSP core DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 6 28 Freescale Semicon
130. if 0 1 HCS active high 0 14 HRP Host Request polarity 0 HOREQ HTRQ HRRQ active low _ this bitis ignored if 0 1 HOREQ HTRQ HRRQ active high HEN 0 15 HAP Host Acknowledge Polarity 0 active low this bit is ignored if 0 1 HACK active high 0 DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor D 13 Host Interface Quick Reference Table 0 4 HDI08 Programming Model continued Bit Reset Type Reg Comments HW Num Mnemonic Name Val Function SW IR ST HSR 0 HRDF Host Receive Data Full 0 receive data to be read 0 0 0 1 receive data register is full 1 HTDE Host Transmit Data Empty 1 transmit data register empty 1 1 1 0 transmit data reg not empty 2 HCP Host Command Pending 0 host command pending 0 0 0 1 host command pending 3 HFO Host FlagO 0 4 HF1 Host Flag1 0 7 Status 0 mode disabled 0 1 DMA mode enabled HBAR 7 0 BA10 BA3 Host base Address 80 Register HORX 23 0 DSP Receive Data empty Register 23 0 DSP Transmit Data empty Register HDR 15 0 D15 DO GPIO Pin Data 000 0 HDDR 15 0 DR15 DRO GPIO Pin Direction O Input 000 1 Output 0 Host Side ICR 0 RREQ Receive Request Enable 0 HRRQ interrupt disabled 0 1 inte
131. in the slave mode the clock is external and is input to the SHI HMST 0 Figure 7 2 illustrates the internal clock path connections It is the DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 7 2 Freescale Semiconductor Serial Host Interface Programming Model user s responsibility to select the proper clock rate within the range as defined in IC and SPI bus specifications SHI Clock lt Eckiscl gt Divide 1 Bye Divide By 256 Controller HDMO HDM7 HRS CPOL 0417 Figure 7 2 SHI Clock Generator 7 4 Serial Host Interface Programming Model The Serial Host Interface programming model has two parts Host side see Figure 7 3 below and Section 7 4 1 SHI Input Output Shift Register IOSR Host Side DSP side see Figure 7 4 and Section 7 4 2 SHI Host Transmit Data Register HTX DSP Side through Section 7 4 6 SHI Control Status Register HCSR DSP Side for detailed information 23 0 IOSR Shift Register IOSR Figure 7 3 SHI Programming Model Host Side AA0418 DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 7 3 Serial Host Interface Programming Model enjny 10 IM Pinoys 0 se peel yq pamasa 6 Iran 10 0 uenu p qp u XLH 0 gz g64443 X eq 1 IHS
132. is cleared pins configured as GPIO are disconnected outputs are high impedance inputs are electrically disconnected Pins configured as HDIOS are not affected by the state of HGEN DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 6 12 Freescale Semiconductor HDIO8 DSP Side Programmer s Model 6 5 6 2 HPCR Host Address Line 8 Enable HA8EN Bit 1 If the HA8EN bit is set and the HDIOS is used in multiplexed bus mode then is used as host address line 8 HA8 If this bit is cleared and the HDIOS is used in multiplexed bus mode then 8 1 is configured as pin according to the value of HDDR and registers is ignored when the HDIOS is not in the multiplexed bus mode HMUX 0 6 5 6 3 HPCR Host Address Line 9 Enable HA9EN Bit 2 If the HA9EN bit is set and the HDIOS is used in multiplexed bus mode then HA9 HA2 is used as host address line 9 HA9 If this bit is cleared and the HDIOS is used in multiplexed bus mode then HA9 HA2 is configured as GPIO pin according to the value of HDDR and HDR registers HA9EN is ignored when the HDIOS is not in the multiplexed bus mode HMUX 0 6 5 6 4 HPCR Host Chip Select Enable HCSEN Bit 3 If the HCSEN bit is set then HCS HA10 is used as host chip select HCS in the non multiplexed bus mode HMUX 0 and as host address line 10 in the multiplexed bus mode HMUX 1 If this bit is cleared then 10 is configu
133. is cleared the TIOO signal generates the following signal 0101 The counter contents can be read at any time by reading the TCR The value of the TLR determines the output period SFFFFFF TLR 1 The timer counter increments the initial TLR value and toggles the TIOO signal when the counter value exceeds SFFFFFF DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 11 18 Freescale Semiconductor Timer Modes of Operation The duty cycle of the TIOO signal is determined by the value in the TCPR When the value in the TLR is incremented to a value equal to the value in the TCPR the TIOO signal is toggled The duty cycle 16 equal to SFFFFFF TCPR divided by SFFFFFF TLR 1 For a 50 duty cycle the value of TCPR is equal to SFFFFFF TLR 1 2 NOTE The value in TCPR must be greater than the value in TLR 11 4 4 Watchdog Modes 11 4 4 44 Watchdog Pulse Mode 9 Bit Settings Mode Characteristics TC2 TC1 TCO Mode Name Kind TIOO Clock 1 0 0 1 9 Pulse Watchdog Output Internal In this mode the timer generates an interrupt at a preset rate Timer 0 also generates pulse on TIOO The signal period is equal to the period of one timer clock Set the TE bit to clear the counter and enable the timer The value the timer is to count is loaded into the TCPR The counter is loaded with the TLR value on the first timer clock received from either the DSP56366 internal cloc
134. is cleared by writing two channels of audio data to XADR 10 5 7 2 Transmit Underrun Error Flag XAUR Bit 1 The XAUR status flag is set when the audio data buffers XADBUFA or XADBUFB are empty and the respective audio data upload occurs When a DAX underrun error occurs the previous frame data will be retransmitted in both channels When XAUR is set and the interrupt is enabled XUIE 1 an underrun error interrupt request is sent to the DSP core This allows programmers to write an exception handling routine for this special case The XAUR bit is cleared by reading the XSTR register with XAUR set followed by writing two channels of audio data to XADR 10 5 7 3 DAX Block Transfer Flag XBLK Bit 2 The XBLK flag indicates that the frame being transmitted is the last frame in a block This bit is set at the beginning of the transmission of the last frame the 191st frame This bit does not cause any interrupt However if XBIE 1 it causes a change in the interrupt vector sent to DSP core in the event of an audio data register empty interrupt so that a different interrupt routine can be called providing the next non audio data structures for the next block as well as storing audio data for the next frame Writing two channels of audio data to XADR clears this bit The relative timing of transmit frames and XADE and XBLK flags is shown in Figure 10 3 Frame XADE XBLK Frame XADE XBL
135. is reflected on port pin n Figure D 36 GPIO Port E DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor D 51 Programming Sheets NOTES DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 D 52 Freescale Semiconductor Index Numerics 5 V tolerance 1 A adder modulo 5 offset 5 reverse carry 5 address bus 1 Address Generation Unit 5 addressing modes 5 AES EBU 10 1 AGU 5 B barrel shifter 4 bus external address 5 external data 5 bus control 1 buses internal 6 C Central Processing Unit CPU i CLKGEN 7 Clock 4 clock 1 Clock divider 11 Clock Generator CLKGEN 7 CP 340 10 1 CPHA and CPOL HCKR Clock Phase and Polar ity Controls 7 D data ALU 4 registers 4 data bus 1 Data Output bit DO 10 DAX 1 21 Block Transferred Interrupt Handling 11 Initiating Transmit Session 10 Transmit Register Empty Interrupt Handling 10 DAX Audio Data register Empty XADE status flag 8 DAX Audio Data Registers XADRA XADRB 5 DAX Audio Data Shift Register XADSR 5 DAX biphase encoder 9 DAX Block transfer XBLK flag 8 DAX Channel A Channel status XCA bit 6 DAX Channel A User data XUA bit 6 DAX Channel A Validity bit 5 DAX Channel B Channel Status XCB bit 6 DAX Channel B User Data XUB bit 6 DAX Channel B Validity XVB bit 6 DAX Clock input Select bits 7 DAX clock multiplexer 9 DAX clock selection 7 DAX Control Register XCTR
136. it again disables the transmitter 0 after completing transmission of the current data word until the beginning of the next frame During that time period the SDOO pin remains in the high impedance state The on demand mode transmit enable sequence can be the same as the normal mode or TEO can be left enabled 8 3 2 2 TCR ESAI Transmit 1 Enable TE1 Bit 1 enables the transfer of data from to the transmit shift register 1 When is set and a frame sync is detected the transmit 1 portion of the ESAI is enabled for that frame When is cleared the transmitter 1 is disabled after completing transmission of data currently in the ESAI transmit shift register The SDO1 output is tri stated and any data present in TX1 is not transmitted 1 data can be written to with TEI cleared but data is not transferred to the transmit shift register 1 The normal mode transmit enable sequence is to write data to one or more transmit data registers before setting TEx The normal transmit disable sequence is to clear TEx TIE and TEIE after TDE equals one In the network mode the operation of clearing and setting it again disables the transmitter 1 after completing transmission of the current data word until the beginning of the next frame During that time period the SDOI pin remains in the high impedance state The on demand mode transmit enable sequence can be the same as the normal mode or 1 can be left enable
137. last slot interrupt may be used for resetting the receive mask slot register reconfiguring the DMA channels and reassigning data memory pointers Using the receive last slot interrupt guarantees that the previous frame was serviced with the previous setting and the new frame 15 serviced with the new setting without synchronization problems Note that the maximum receive last slot interrupt service time should not exceed N 1 ESAI bits service time where N is the number of bits in a slot ESAI Transmit Data with Exception Status Occurs when the transmit exception interrupt is enabled TEIE 1 at least one transmit data register of the enabled transmitters is empty TDE 1 and a transmitter underrun error has occurred TUE 1 TUE is cleared by first reading the SAISR and then writing to all the enabled transmit data registers or to the TSR register ESAI Transmit Last Slot Interrupt Occurs if enabled TLIE 1 at the start of the last slot of the frame in network mode regardless of the transmit mask register setting The transmit last slot interrupt may be used for resetting the transmit mask slot register reconfiguring the DMA channels and reassigning data memory pointers Using the transmit last slot interrupt guarantees that the previous frame was serviced with the previous setting and the new frame is serviced with the new setting without synchronization problems Note that the maximum transmit last slot interrupt service time should not exc
138. led to developing this standard under the sponsorship of the Test Technology Committee of IEEE and JTAG The DSP56300 core implementation supports circuit board test strategies based on this standard The test logic includes a TAP consisting of four dedicated signals a 16 state controller and three test data registers A boundary scan register links all device signals into a single shift register The test logic implemented utilizing static logic design is independent of the device system logic More information on the JTAG port is provided in DSP56300 Family Manual JTAG Port The OnCE module provides a nonintrusive means of interacting with the DSP56300 core and its peripherals so a user can examine registers memory or on chip peripherals This facilitates hardware and software development on the DSP56300 core processor OnCE module functions are provided through the JTAG TAP signals More information on the OnCE module is provided in DSP56300 Family Manual On Chip Emulation Module 1 4 8 On Chip Memory The memory space of the DSP56300 core is partitioned into program memory space X data memory space and Y data memory space The data memory space is divided into X and Y data memory in order to work with the two Address ALUs and to feed two operands simultaneously to the Data DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 1 7 Peripheral Overview ALU Memory space includes internal RAM and R
139. load from EPROM jset If MD MC MB MA 0011 go to RESERVED This is the routine that jumps to the internal Program ROM MD MC MB MA 0010 move PROMADDR r1 store starting PROM address in r1 bra lt FINISH This is the routine that loads from SHI MD MC MB MA 0100 reserved for SHI MD MC MB MA 0101 Bootstrap from SHI SPI slave MD MC MB MA 0110 Bootstrap from SHI I2C slave HCKFR 1 100ns filter MD MC MB MA 0111 Bootstrap from SHI I2C slave HCKFR 0 DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 A 4 Freescale Semiconductor DSP56366 Bootstrap Program SHILD This is the routine which loads a program through the SHI port The SHI operates in the slave mode with the 10 word FIFO enabled and with the HREQ pin enabled for receive operation The word size for transfer is 24 bits The SHI operates in the SPI or in the I2C mode according to the bootstrap mode The program is downloaded according to the following rules 1 3 bytes Define the program length 2 3 bytes Define the address to which to start loading the program to 3 3n bytes while n is the program length defined by the first 3 bytes The program words will be stored in contiguous PRAM memory locations starting at the specified starting address After storing the program words program execution starts from the same address where loading started move
140. other exception in the slave device has occurred Consequently the master device generates a stop event and terminates the session HTX contents are transferred to the IOSR when the complete word according to HM 1 0 has been shifted out It is therefore the responsibility of the programmer to select the right number of bytes in an frame so that they fit in a complete number of words Remember that for this purpose the slave device address byte does not count as part of the data In a transmit session only the transmit path is enabled and the IOSR to HRX FIFO transfers are inhibited When the HTX transfers its valid data word to the IOSR the HTDE status bit is set and the DSP may write anew data word to HTX with either DSP instructions or DMA transfers If both IOSR and HTX are empty the SHI suspends the serial clock until new data is written into HTX when the SHI proceeds with the transmit session or HIDLE is set the SHI reactivates the clock to generate the stop event and terminate the transmit session DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 7 24 Freescale Semiconductor SHI Programming Considerations 7 7 5 SHI Operation During DSP Stop The SHI operation cannot continue when the DSP is in the stop state because no DSP clocks are active While the DSP is in the stop state the SHI remains in the individual reset state While in the individual reset state the following is true Ifthe SHI w
141. output and its operation is defined in Table 7 5 HRQE 1 0 should be changed only when the SHI is idle HBUSY 0 0 are cleared during hardware reset and software reset Table 7 5 HREQ Function In SHI Slave Modes HRQE1 HRQEO HREQ Pin Operation 0 0 High impedance 0 1 Asserted if IOSR is ready to receive a new word 1 0 Asserted if IOSR is ready to transmit a new word 1 1 Asserted if IOSR is ready to transmit or receive SPI Asserted if IOSR is ready to transmit and receive DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 7 12 Freescale Semiconductor Serial Host Interface Programming Model 7 4 6 8 Idle HIDLE Bit 9 The read write control status bit HIDLE is used only in the master mode it is ignored otherwise It is only possible to set the HIDLE bit during writes to the HCSR HIDLE is cleared by writing to HTX To ensure correct transmission of the slave device address byte HIDLE should be set only when HTX is empty HTDE 1 After HIDLE is set a write to HTX clears HIDLE and causes the generation of a stop event a start event and then the transmission of the eight MSBs of the data as the slave device address byte While HIDLE is cleared data written to HTX is transmitted as is If the SHI completes transmitting a word and there is no new data in HTX the clock is suspended after sampling ACK If HIDLE is set when the SHI completes transmitti
142. processor DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 6 4 Freescale Semiconductor HDIO8 DSP Side Programmer s Model Core DMA Data Bus DSP Peripheral Data Bus o 24 24 24 24 24 24 24 24 24 a i M i DN 7 Address Comparator 24 24 X TR 3 5 1 R 3 8 8 8 8 3 8 8 8 HOST Bus ICR Interface Control Register HCR Host Control Register CVR Command Vector Register HSR Host Status Register ISR Interface Status Register HPCR Host Port Control Register IVR Interrupt Vector Register HBAR Host Base Address register RXH RXM RXL Receive Register High Middle Low HOTX Host Transmit register TXH TXM TXL Transmit Register High Middle Low HORX Host Receive register HDDR Host Data Direction Register HDR Host Data Register Figure 6 1 HDIO8 Block Diagram 6 5 HDIO8 DSP Side Programmer s Model The DSP core threats the 08 as a memory mapped peripheral occupying eight 24 bit words in X data memory space The DSP may use the HDI08 as a normal memory mapped peripheral employing either standard polled or interrupt driven programming techniques Separate transmit and receive data registers are double buffered to allow the DSP and host processor to transfer data efficiently at high speed Direct memory mapping allows the DSP core to communicate with the HDI08 registers using standard instr
143. reset and during the stop state 7 4 6 14 Reserved Bits Bits 23 18 and 16 These bits are reserved They read as zero and should be written with zero for future compatibility 7 4 6 15 Host Receive FIFO Not Empty HRNE Bit 17 The read only status bit HRNE indicates that the Host Receive FIFO HRX contains at least one data word HRNE is set when the FIFO is not empty is cleared when HRX 15 read by the DSP read instructions or DMA transfers reducing the number of words in the FIFO to zero HRNE is cleared during hardware reset software reset SHI individual reset and during the stop state 7 4 6 16 Host Receive FIFO Full HRFF Bit 19 The read only status bit HRFF indicates when set that the Host Receive FIFO HRX is full HRFF is cleared when HRX is read by the DSP read instructions or DMA transfers and at least one place is available in the FIFO HRFF is cleared by hardware reset software reset SHI individual reset and during the stop state 7 4 6 17 Host Receive Overrun Error HROE Bit 20 The read only status bit HROE indicates when set that a data receive overrun error has occurred Receive overrun errors cannot occur when operating in the master mode because the clock is suspended if the receive FIFO is full nor can they occur in the slave mode when HCKFR is set HROE is set when the shift register IOSR is filled and ready to transfer the data word to the HRX FIFO and the FIFO
144. side Mapping Registers are directly mapped into eight internal X data memory locations Data Word 24 bit native data words are supported as 8 bit and 16 bit words Transfer Modes DSP to Host Host to DSP Host Command Handshaking Protocols Software polled Interrupt driven Core DMA accesses Instructions Memory mapped registers allow the standard MOVE instruction to be used to transfer data between the DSP and the external host Special MOVEP instruction provides for I O service capability using fast interrupts DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 6 1 HDIOS Features 6 2 2 Bit addressing instructions e g BCHG BCLR BSET BTST JCLR JSCLR JSET JSSET simplify I O service routines Interface Host Side Sixteen signals are provided to support non multiplexed or multiplexed buses HO0 H7 HADO HAD7 Host data bus 7 or host multiplexed address data bus HADO HAD7 Address strobe HAS or Host address line HAO HAS HAI Host address line 8 or Host address line 1 HA9 HA2 Host address line HA9 or Host address line HA2 HRW HRD Read write select HRW or Read Strobe HRD HDS HWR Data Strobe HDS or Write Strobe HWR HCS HA10 Host chip select HCS or Host address line HA10 HOREQ HTRQ Host request HOREQ or Host transmit request
145. signal from the TIOO signal 4 Width of the high input Width of the low input pulse pulse is measured is measured 5 Period is measured Period is measured between the rising edges between the falling edges of the input signal of the input signal 6 Event is captured on the Event is captured on the E E rising edge of the signal falling edge of the signal from the TIOO signal from the TIOO signal 7 Pulse generated by the Pulse generated by the timer has positive polarity timer has negative polarity 9 Pulse generated by the Pulse generated by the timer has positive polarity timer has negative polarity 10 Pulse generated by the Pulse generated by the timer has positive polarity timer has negative polarity The INV bit is cleared by the hardware RESET signal or the software RESET instruction DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 11 9 Timer Event Counter Programming Model NOTE The bit affects both the timer and GPIO modes of operation To ensure correct operation this bit should be changed only when one or both of the following conditions is true timer has been disabled by clearing the TE bit in the TCSR The timer is in GPIO mode The INV bit does not affect the polarity of the prescaler source when TIOO is used as input to the prescaler 11 3 4 Timer Reload Mode TRM Bit 9 The TRM bit controls the counter p
146. slot number N The data is still transferred from the transmit data registers to the transmit shift registers but neither the TDE nor the TUE flags are set This means that during a disabled slot no transmitter empty interrupt is generated The DSP is interrupted only for enabled slots Data that is written to the transmit data registers when servicing this request is transmitted in the next enabled transmit time slot When bit number N in TSM register is set the transmit sequence is as usual data is transferred from the TX registers to the shift registers transmitted during slot number N and the TDE flag is set Using the slot mask in TSM does not conflict with using TSR Even if a slot is enabled in TSM the user may chose to write to TSR instead of writing to the transmit data registers TXx This causes all the transmit data pins of the enabled transmitters to be tri stated during the next slot Data written to the TSM affects the next frame transmission The frame being transmitted is not affected by this data and would comply to the last TSM setting Data read from TSM returns the last written data After hardware or software reset the TSM register is preset to SFFFFFFFF which means that all 32 possible slots are enabled for data transmission DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 8 41 ESAI Programming Model NOTE When operating in normal mode bit 0 of the mask register mu
147. sync generator functional diagram is shown in Figure 8 4 DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 8 10 Freescale Semiconductor ESAI Programming Model RDC4 RFSL RX WORD CLOCK RECEIVER INTERNAL RX FRAME CLOCK FRAME RATE DIVIDER RECEIVE CONTROL LOGIC RECEIVE FRAME SYNC FLAG1 IN FLAG1OUT d DE TFSL SYNC MODE SYNC MODE TX WORD CLOCK TRANSMITTER INTERNAL TX FRAME CLOCK FRAME RATE DIVIDER TRANSMIT CONTROL LOGIC FRAME SYNC Figure 8 4 ESAI Frame Sync Generator Functional Block Diagram 8 3 1 4 TCCR Tx High Frequency Clock Divider Bits 14 17 The TFP3 TFPO bits control the divide ratio of the transmitter high frequency clock to the transmitter serial bit clock when the source of the high frequency clock and the bit clock is the internal DSP clock When the HCKT input is being driven from an external high frequency clock the TFP3 TFPO bits specify an additional division ratio in the clock divider chain See Table 8 3 for the specification of the divide ratio The ESAI high frequency clock generator functional diagram is shown in Figure 8 3 Table 8 3 Transmitter High Frequency Clock Divider TFP3 TFPO Divide Ratio 0 1 1 2 2 3 3 4 SF 16 DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 8 11 ESAI Programming Model 8 3 1 5 TCCR Transmi
148. terminate the loading process by setting the HF1 0 and HF0 1 When the downloading is terminated the program will start execution of the loaded program from the specified starting address The HDIO8 boot ROM program enables the following busses to download programs through the 108 port C ISA Dual strobes non multiplexed bus with negative strobe pulses dual positive request D 11 Single strobe non multiplexed bus with positive strobe pulse single negative request DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 A 6 Freescale Semiconductor E 18051 MC68302 DSP56366 Bootstrap Program Dual strobes multiplexed bus with negative strobe pulses dual negative request Single strobe non multiplexed bus with negative strobe pulse single negative request MC68302HOSTLD movep bra OMR1ISO 0000000000111000 HPCR lt HDIO8CONT jset MA omr HC11HOSTLD ISAHOSTLD movep Configure HAP 0 HRP 0 HCSP 0 HDDS 0 HMUX 0 HASP 0 HDSP 0 HROD 0 spare 0 HEN 0 HAEN 1 HREN 1 HCSEN 1 HA9EN 0 0 HGEN 0 the following conditions Negative host acknowledge Negative host request Negatice chip select input Single strobe bus R W and DS Non multiplexed bus address strobe polarity has no meaning in non multiplexed bus Negative data stobes polarity Host request is active when enabled This bit should be set to 0 for future
149. the MISO line when in SPI master mode and the MOSI line when in SPI slave mode DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 7 9 Serial Host Interface Programming Model Table 7 3 SHI Noise Reduction Filter Mode HFM1 HFMO Description 0 0 Bypassed Disabled 0 1 Reserved 1 0 Narrow Spike Tolerance 1 1 Wide Spike Tolerance When HFM 1 0 00 the filter is bypassed spikes are not filtered out This mode is useful when higher bit rate transfers are required and the SHI operates in a noise free environment When HFM 1 0 7 10 the narrow spike tolerance filter mode is selected In this mode the filters eliminate spikes with durations of up to 50ns This mode is suitable for use in mildly noisy environments and imposes some limitations on the maximum achievable bit rate transfer When HFM 1 0 11 the wide spike tolerance filter mode is selected In this mode the filters eliminate spikes up to 100 ns This mode is recommended for use in noisy environments the bit rate transfer 18 strictly limited The wide spike tolerance filter mode is highly recommended for use in bus systems as it fully conforms to the bus specification and improves noise immunity NOTE HFM 1 0 are cleared during hardware reset and software reset After changing the filter bits in the HCKR to non bypass mode HFM 1 0 not equal to 00 the programmer should wait at leas
150. the RFP3 RFPO bits specify an additional division ration in the clock divider chain See Table 8 6 for the specification of the divide ratio The ESAI high frequency generator functional diagram is shown in Figure 8 3 DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 8 23 ESAI Programming Model Table 8 6 Receiver High Frequency Clock Divider RFP3 RFPO Divide Ratio 0 1 1 2 2 3 3 4 F 16 8 3 3 5 RCCR Receiver Clock Polarity RCKP Bit 18 The Receiver Clock Polarity RCKP bit controls on which bit clock edge data and frame sync are clocked out and latched in If RCKP is cleared the data and the frame sync are clocked out on the rising edge of the receive bit clock and the frame sync is latched in on the falling edge of the receive bit clock If RCKP is set the falling edge of the receive clock is used to clock the data and frame sync out and the rising edge of the receive clock is used to latch the frame sync in 8 3 3 6 RCCR Receiver Frame Sync Polarity RFSP Bit 19 The Receiver Frame Sync Polarity RFSP determines the polarity of the receive frame sync signal When RFSP is cleared the frame sync signal polarity is positive i e the frame start is indicated by a high level on the frame sync pin When is set the frame sync signal polarity is negative i e the frame start is indicated by a low level on the frame sync pin 8 3 3 7 RCCR Receiver
151. the XADE bit in the XSTR is cleared XADR can also be accessed by DMA When XADR and XADBUFA are empty the DAX sends DMA request to the core The DMA first transfers non audio data bits to XNADR optional then transfers channel A and channel B to XADR The XADR can be accessed with two different successive addresses This feature supports sending non audio data bits channel A and channel B to the DAX in three successive DMA transfers 10 5 2 DAX Audio Data Buffers XADBUFA XADBUFB XADBUFA XADBUFB are 24 bit registers that buffer XADR XADSR creating a FIFO like data path These registers hold the next two subframes of audio data to be transmitted Channel A audio data is transferred from XADR to XADBUFA if XADBUFA is empty Channel B audio data is transferred from XADR to XADBUFB if XADBUFB is empty Audio data is transferred from XADBUFA and XADBUFEB alternately to XADSR provided that XADSR shifted out all the audio and non audio bits of the currently transmitted channel This buffering mechanism provides more cycles for writing the next audio data to XADR These registers are not directly accessible by DSP instructions 10 5 3 Audio Data Shift Register XADSR The XADSR is a 27 bit shift register that shifts the 24 bit audio data and the 3 bit non audio data for one subframe The contents of XADBUFA or XADBUFB are directly transferred to the XADSR at the beginning of the subframe transmission The channel A subframe i
152. the clock line to GND to avoid an underrun condition The HREQ output pin if enabled for transmit HRQE 1 0 10 is asserted when HTX is transferred to IOSR for transmission When asserted HREQ indicates that the slave device is ready to transmit the next data word HREQ is deasserted at the first clock pulse of the next transmitted data word The HREQ line DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 7 22 Freescale Semiconductor SHI Programming Considerations may be used to interrupt the external master device Connecting the HREQ line between two SHI equipped DSPs one operating as an C master device and the other as an slave device enables full hardware handshaking 7 74 1 Master Mode The master mode is entered by enabling the SHI HEN 1 selecting the mode 1 and selecting the master mode of operation HMST 1 Before enabling the SHI as an master the programmer should program the appropriate clock rate in HCKR When configured in the master mode the SHI external pins operate as follows SCK SCL is the SCL open drain serial clock output MISO SDA is the SDA open drain serial data line MOSI HAO is the HAO slave device address input SS HA2 is the HA2 slave device address input HREQ is the Host Request input In the master mode a data transfer session is always initiated by the DSP by writing to the HTX register when HIDLE is set
153. the minimum internally generated bit clock frequency is Fosc 2 x 8 x 256 4096 NOTE Do not use the combination RPSR 1 and RPM7 RPMO0 00 which causes synchronization problems when using the internal DSP clock as source RHCKD 1 or RCKD 1 8 3 3 3 RCCR Rx Frame Rate Divider Control RDC4 RDCO Bits 9 13 The RDC4 RDCO bits control the divide ratio for the programmable frame rate dividers used to generate the receiver frame clocks In network mode this ratio may be interpreted as the number of words per frame minus one The divide ratio may range from 2 to 32 RDC 4 0 00001 to 11111 for network mode A divide ratio of one RDC 4 0 00000 in network mode is a special case on demand mode In normal mode this ratio determines the word transfer rate The divide ratio may range from 1 to 32 RDC 4 0 00000 to 11111 for normal mode In normal mode a divide ratio of one RDC 4 0 00000 provides continuous periodic data word transfers A bit length frame sync RFSL 1 must be used in this case The ESAI frame sync generator functional diagram is shown in Figure 8 4 8 3 3 4 RCCR Rx High Frequency Clock Divider Bits 14 17 The RFP3 RFPO bits control the divide ratio of the receiver high frequency clock to the receiver serial bit clock when the source of the receiver high frequency clock and the bit clock is the internal DSP clock When the HCKR input is being driven from an external high frequency clock
154. to 0 for future compatability HEN 0 When the HPCR register is modified II HEN should be cleared 0 Host acknowledge is disabled HREN 1 Host requests are enabled HCSEN 1 Host chip select input enabled HA9EN 1 Enable address 9 input HA8EN 1 Enable address 8 input HGEN 0 Host pins are disabled HDIO8CONT bset HHEN x M HPCR Enable the HDIO8 to operate as host interface set HEN 1 HHRDF x M HSR wait for the program length to be written movep x M HORX a0 HHRDF x M HSR wait for the program starting address to be written movep x M move r0 r1 do a0 HDIO8LOOP set a loop with the downloaded length HDIO8LL jset HHRDF x M HSR HDIOSNW If new word was loaded then jump to read that word HHFO x M HSR HDIOSLL HFO 0 then continue with the downloading enddo Must terminate the do loop bra HDI08LOOP HDI08NW movep HORX p Move the new word into its destination location in the program RAM nop pipeline delay HDIO8LOOP This is the exit handler that returns execution to normal expanded mode and jumps to the RESET vector FINISH andi 50 Clear CCR as if RESET to 0 jmp r1 Then go to starting Prog addr DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor A 9 L AANAAW N E KKKXXEEE EE E I I LL NEKEKEK KR X XZJZ DSP563
155. to TSR 8 3 6 12 SAISR Transmit Data Register Empty Bit 15 TDE is set when the contents of the transmit data register of all the enabled transmitters are transferred to the transmit shift registers it is also set for a TSR disabled time slot period in network mode as if data were being transmitted after the TSR was written When set TDE indicates that data should be written to all the TX registers of the enabled transmitters or to the time slot register TSR is cleared when the DSP writes to all the transmit data registers ofthe enabled transmitters or when the DSP writes to the TSR to disable transmission of the next time slot If TIE is set an ESAI transmit data interrupt request is issued when TDE 15 set Hardware software ESAI individual and STOP reset clear TDE 8 3 6 13 SAISR Transmit Even Data Register Empty Bit 16 When set TEDE indicates that the enabled transmitter data registers became empty at the beginning of an even time slot Even time slots are all even numbered slots 0 2 4 6 etc Time slots are numbered from zero to N 1 where N is the number of time slots in the frame The zero time slot is considered even This flag is set when the contents of the transmit data register of all the enabled transmitters are transferred to the transmit shift registers it is also set for a TSR disabled time slot period in network mode as if data were being transmitted after the TSR was written When se
156. to start loading the program words and then a 24 bit word for each program word to be loaded The program words will be stored in contiguous PRAM memory locations starting at the specified starting address After reading the program words program execution starts from the same address where loading started The Host Interface bootstrap load program may be stopped by setting the Host Flag 0 This will start execution of the loaded program from the specified starting address in Mode C but HDIOB is set for interfacing to Freescale HC11 microcontroller non multiplexed mode As in Mode C but HDI08 is set for interfacing to Intel 8051 multiplexed bus As in Mode C but HDIO8 is set for interfacing to Freescale 68302 bus Interrupt Priority Registers There are two interrupt priority registers in the DSP56366 1 IPR C is dedicated for DSP56300 Core interrupt sources 2 1 is dedicated for DSP56366 peripheral interrupt sources The interrupt priority registers are shown in Figure 4 1 and Figure 4 2 The Interrupt Priority Level bits are defined in Table 4 4 The interrupt vectors are shown in Table 4 6 and the interrupt priorities are shown in Table 4 5 Table 4 4 Interrupt Priority Level Bits IPL bits Interrupts Interrupt Enabled Priority xxL1 xxLO Level 0 0 No 0 1 Yes 0 1 0 Yes 1 1 1 Yes 2 DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 4 6 Freescale Semiconductor
157. ulBu l pio 191 351 154 857 ejeq o snouoJuou s ou s awe ujBue pJo 0 154 GSW peyius 0 uondioseg uSdH uonduoseg 19594 EuosJog JoAlo29 euuoN 1 0 peubi e yo uonduoseg ASH O3HSH peus LOOWNY 0SMSH 2SMS8 SMSH SMSY 9 uonduoseg 1dnueju uondeox3 p jqes p 1dnuueju 169v uonduoseg pejqeue 1dnuueiu 81611016 USAF 941929 L p jqes p 1015 ue 3 0 uonduoseq 21033 ulBu pom pue 018 uonduosoeg pejqeue peigesip 3dn ueju 0 ou s awed poued 2012 1Iq L ou s owed pio 0 uonduoseg 7544 1016 1527 p jqes p 10 5 1527 L IVSd 000000 39594 4644445 uonduoseg JasiBay 1043405 ze Freescale Semic
158. value and a new event causes the counter to be incremented to 000000 the timer generates an overflow interrupt Clearing the TOIE bit disables overflow interrupt generation The TOIE bit is cleared by the hardware RESET signal or the software RESET instruction 11 3 4 3 TCSR Timer Compare Interrupt Enable TCIE Bit 2 The Timer Compare Interrupt Enable bit is used to enable or disable the timer compare interrupts Setting TCIE enables the compare interrupts In the timer PWM or watchdog modes a compare interrupt is generated after the counter value matches the value ofthe TCPR The counter will start counting up from the number loaded from the TLR and if the TCPR value is an interrupt occurs after N M 1 events where M is the value of TLR Clearing the TCIE bit disables the compare interrupts The TCIE bit is cleared by the hardware RESET signal or the software RESET instruction 11 3 4 4 Timer Control TC 3 0 Bits 4 7 The four TC bits control the source ofthe timer clock the behavior of the TIOO signal and the timer mode of operation Table 11 2 summarizes the TC bit functionality A detailed description ofthe timer operating modes 15 given in Section 11 4 Timer Modes of Operation The TC bits are cleared by the hardware RESET signal or the software RESET instruction NOTE If the clock is external the counter is incremented by the transitions on the TIOO signal The external clock is internal
159. with an external device by receiving and or transmitting data Before changing the SHI operational mode an SHI individual reset should be generated by clearing the HEN bit The following paragraphs describe programming considerations for each operational mode 7 7 1 SPI Slave Mode The SPI slave mode is entered by enabling the SHI HEN 1 selecting the SPI mode 0 selecting the slave mode of operation HMST 0 The programmer should verify that the and CPOL bits in the HCKR correspond to the external host clock phase and polarity Other HCKR bits are ignored When configured in the SPI slave mode the SHI external pins operate as follows SCK SCL is the SCK serial clock input MISO SDA is the MISO serial data output MOSI HAO is the MOSI serial data input SS HA2 is the SS slave select input HREQ is the Host Request output In the SPI slave mode a receive transmit or full duplex data transfer may be performed Actually the interface performs data receive and transmit simultaneously The status bits of both receive and transmit paths are active however the programmer may disable undesired interrupts and ignore irrelevant status bits It is recommended that an SHI individual reset HEN cleared be generated before beginning data reception in order to reset the HRX FIFO to its initial empty state e g when switching from transmit to receive data DSP56366 24 Bit Digital Signal Processor Use
160. words Generate vectored interrupts separately for receive and transmit events and update status bits Generate a separate vectored interrupt for a receive exception Generate a separate vectored interrupt for a bus error exception Generate the serial clock signal in master mode Trigger DMA interrupts to service the transmit and receive events When configured in the mode the SHI can perform the following functions Detect generate start and stop events Identify its slave ID address in slave mode Identify the transfer direction receive transmit Transfer data byte wise according to the SCL clock line Generate ACK signal following a byte receive Inspect ACK signal following a byte transmit Directly operate with 8 16 and 24 bit words Generate vectored interrupts separately for receive and transmit events and update status bits Generate a separate vectored interrupt for a receive exception Generate a separate vectored interrupt for a bus error exception Generate the clock signal in master mode Trigger DMA interrupts to service the transmit and receive events DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 7 1 Serial Host Interface Internal Architecture 7 2 Serial Host Interface Internal Architecture The DSP views the SHI as a memory mapped peripheral in the X data memory space The DSP uses the SHI as a normal memory mapped peripheral using standard polling or interrupt progr
161. 0 scaling 01 01 Scale down 10 0 1 Scale up 11 0 1 2 Reserved Sixteen Bit Compatibilitity Double Precision Multiply Mode Loop Flag DO Forever Flag Sixteenth Bit Arithmetic Reserved Instruction Cache Enable Arithmetic Saturation Rounding Mode Core Priority CP 1 0 Core Priority 00 0 lowest 01 1 10 2 11 3 highest 23 22 21 20119 5 17 16 15 14 13 11 10 9 Extended Mode Register MR Mode Register MR Condition Code Register CCR Status Register SR Read Write Reset C00300 Reserved Program as 0 Figure D 1 Status Register SR DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 D 16 Freescale Semiconductor Application Central Processor External Bus Disable Stop Delay Memory Switch Mode Programming Sheets Date Programmer Sheet 2 of 5 Chip Operating Modes MOD D A Reset Vector Description See Core Configuration Section CDP 1 0 Core DMA Priority Core DMA Priority 00 01 10 11 Core vs DMA Priority accesses gt Core accesses Core DMA accesses Core Burst Mode E nable TA Synchronize Select Bus Release Timing Address Priority Disable Address Tracing Enable Stack Extension Space Select Extended Stack Overflow Flag Extended Stack Wrap Flag 23 22 21 u
162. 0 000000 X DATA INTERNAL 128 words EXTERNAL INTERNAL RESERVED EXTERNAL 32K INTERNAL ROM INT RESERVED 11K INTERNAL RAM FFFFFF FFFFB0 FFFF80 FFF000 FF0000 006000 004000 001C00 000000 Y DATA EXTERNAL I O 80 words INTERNAL I O 48 words EXTERNAL INTERNAL RESERVED EXTERNAL 8K INTERNAL ROM INT RESERVED 7K INTERNAL RAM Figure 3 8 Memory Maps for MSW 1 0 CE 1 MS 1 SC 0 DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 3 6 Freescale Semiconductor Data and Program Memory Maps PROGRAM X DATA Y DATA BEERE SFFFF INTERNAL I O FFFF EXTERNAL FF80 128 words 82 words INTERNAL 46 words FF80 EXTERNAL EXTERNAL EXTERNAL C000 6000 32K INTERNAL 8K INTERNAL ROM ROM 4000 4000 INT RESERVED 3400 INT RESERVED 1000 0C00 3K INTERNAL 13K INTERNAL 7K INTERNAL 0000 RAM 0000 RAM 0000 mM Figure 3 9 Memory Maps for MSWz X X 0 5 0 5 1 PROGRAM X DATA Y DATA SEED SFFFF INTERNAL FFFF EXTERNAL IO FF80 1 28 words FFBO 80 words INTERNAL 48words FF80 EXTERNAL EXTERNAL EXTERNAL 52000 56000 32K INTERNAL 8K INTERNAL ROM ROM 4000 4000 58400 INT RESERVED sicoo
163. 0 1 0 DMA Mode Data Output Transfers Enabled 16 Bit words O 1 1 DMA Mode Data Output Transfers Enabled 8 Bit words INIT HDM1 HDMO HF1 HFO TREQ RREQ 1 0 4 Mode Data Input Transfers Enabled 24 Bit words 1 1 0 DMA Mode Data Input Transfers Enabled 16 Bit words 1 1 1 DMA Mode Data Input Transfers Enabled 8 Bit words If HDMI or HDMO are set DMA mode is enabled and the signal is used to request DMA transfers the value of the HM1 HLEND and HDREQ bits in ICR have no affect When the DMA mode is enabled the HDM2 bit selects the direction of DMA transfers setting HDM2 sets the direction of DMA transfer to be DSP to host and enables the HOREQ signal to request data transfer clearing HDM2 sets the direction of DMA transfer to be host to DSP and enables the HOREQ signal to request data transfer The HACK input signal is used as a DMA transfer acknowledge input If the DMA direction is from DSP to host the contents of the selected register are driven onto the host data bus when HACK is asserted If the DMA direction is from host to DSP the selected register is written from the host data bus when HACK is asserted The size of the DMA word to be transferred is determined by the DMA control bits HDM 1 0 Only the data registers TXH TXL and RXH RXL can be accessed in DMA mode The HD
164. 0 0 0 0 0 8 8 0 0 1 0 0 12 8 0 0 0 0 1 12 0 1 0 0 0 16 8 0 0 1 0 1 12 0 0 0 1 0 16 0 1 1 0 0 20 8 0 1 0 0 1 12 0 0 1 1 0 16 0 0 0 1 1 20 1 0 0 0 0 24 8 0 1 1 0 1 12 0 1 0 1 0 16 0 0 1 1 1 20 1 1 1 1 0 24 1 1 0 0 0 32 8 1 0 1 0 1 12 1 0 0 1 0 16 0 1 1 1 1 20 1 1 1 1 1 24 DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 8 29 ESAI Programming Model Table 8 11 ESAI Receive Slot and Word Length Selection continued RSWS4 RSWS3 RSWS2 RSWS1 RSWSO SLOT LENGTH WORD LENGTH 0 1 0 1 1 Reserved 0 1 1 1 0 1 0 0 0 1 1 0 0 1 1 1 0 1 0 0 1 0 1 1 0 1 0 1 1 1 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 1 1 1 0 0 1 1 1 0 1 8 3 4 10 Receiver Frame Sync Length RFSL Bit 15 The RFSL bit selects the length ofthe receive frame sync to be generated or recognized If RFSL is cleared a word length frame sync is selected If RFSL is set a 1 bit clock period frame sync is selected See Figure 8 7 for examples of frame length selection 8 3 4 11 Receiver Frame Sync Relative Timing RFSR Bit 16 RFSR determines the relative timing of the receive frame sync signal as referred to the serial data lines for a word length frame sync only When RFSR is cleared the word length frame sync occurs together with the first bit ofthe data word ofthe first slot When RFSR is set the word length frame sync starts one serial clock cycle
165. 0 7 1 04 1 4 0 uonduoseg 0 da IVSA Ja siBay 0 002 12015 1 Iysa 000000 3 5 964444 349591 6L 0c lo cc yusue Busu uo oojo Jo eBpe 0 Jes 4 YOOID Jo uo 5 Jo Buisu Jas Auejod 010 0 uonduoseg 4 ou s owes L eAnisod ou s 4 0 uonduoseg 3531 peAieses uoneJedo Jedoud 10 0 uonduoseg eoJnos L pesn eoJnos 0 uonduoseg yndyno 51 154 s 154 uonduoseq uone4edo Jedoud 104 198 eq JSN uonduoseg Figure D 22 ESAI 1 Transmit Clock Control Register DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 D 37 Freescale Semiconductor Programming Sheets Programmer Date Application 8 6 sau qaHs1 vu OGOWL LAOWL OSMSL SMSY ZSMS 15 1 SI 9 4 L LL L
166. 00000 RAM 000000 RAM 000000 RAM 1K I CACHE ENABLED Figure 3 6 Memory Maps for MSW 0 0 1 5 1 SC 0 DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 3 5 Data and Program Memory Maps FFFFFF PROGRAM INTERNAL RESERVED FF1000 FFOOCO FF0000 002400 001C00 000000 40K INTERNAL ROM INTERNAL RESERVED BOOT ROM EXTERNAL INT RESERVED 7K INTERNAL RAM 1K I CACHE ENABLED FFFFFF FFFF80 FFF000 FF0000 00C000 004000 002000 000000 X DATA INTERNAL I O 128 words EXTERNAL INTERNAL RESERVED EXTERNAL 32K INTERNAL ROM INT RESERVED 8K INTERNAL RAM FFFFFF FFFFB0 FFFF80 FFF000 FF0000 006000 004000 001C00 000000 Y DATA EXTERNAL I O 80 words INTERNAL I O 48 words EXTERNAL INTERNAL RESERVED EXTERNAL 8K INTERNAL ROM INT RESERVED 7K INTERNAL RAM Figure 3 7 Memory Maps for MSW 0 1 CE 1 MS 1 SC 0 FFFFFF FF1000 FFOOCO FF0000 002400 001000 000000 1K I CACHE ENABLED PROGRAM INTERNAL RESERVED 40K INTERNAL ROM INTERNAL RESERVED BOOT ROM EXTERNAL INT RESERVED 4K INTERNAL RAM FFFFFF FFFF80 FFF000 FF0000 00C000 004000 002C0
167. 00003 Channel B 000002 Channel A 000002 Channel A 000001 Channel B 000001 Non Audio Data 000000 Channel A 000000 Non audio data bits do not change from frame to frame Non audio data bits change from frame to frame Figure 10 6 Examples of data organization in memory 10 6 5 Operation During Stop The DAX operation cannot continue when the DSP is in the stop state since no DSP clocks are active While the DSP is in the stop state the DAX will remain in the individual reset state and the status flags are initialized as described for resets No DAX control bits are affected The DAX should be disabled before the DSP enters the stop state 10 7 GPIO PORT D Pins and Registers The Port D GPIO functionality of the DAX is controlled by three registers Port D Control Register PCRD Port D Direction Register PRRD and Port D Data Register PDRD 10 7 1 Port D Control Register PCRD The read write 24 bit DAX Port D Control Register controls the functionality of the DAX GPIO pins Each of the PC 1 0 bits controls the functionality of the corresponding port pin When bit is set the corresponding port pin is configured as a DAX pin When a bit is cleared the corresponding port pin is configured as pin If both PC1 and PCO are cleared the DAX is disabled Hardware and software reset clear all PCRD bits DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 10 12 Freescale Semico
168. 08000 MD 1 assuming that an external memory of SRAM type is used The accesses will be performed using 31 wait states with no address attributes selected default area If MD MC MB MA 0001 then it loads a program RAM segment from consecutive byte wide P memory locations starting at P D00000 bits 7 0 The memory is selected by the Address Attribute AA1 and is accessed with 31 wait states The EPROM bootstrap code expects to read 3 bytes Specifying the number of program words 3 bytes specifying the address to start loading the program words and then 3 bytes for each program word to be loaded The number of words the starting address and the program words are read least significant byte first followed by the mid and then by the most significant byte The program words will be condensed into 24 bit words and stored in contiguous PRAM memory locations starting at the specified starting address After reading the program words program execution starts from the same address where loading started UE UE OE UE UE EE aaa If MD MC MB MA 0010 then the bootstrap code jumps to the internal DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor A 1 DSP56366 Bootstrap Program Program ROM without loading the Program RAM EE UE UE OE UE UE OE UE UE UE UE EE
169. 1 amp 54 BC 1 AA 0 output3 X 53 T 2 amp 55 control 1 amp 56 BC 1 AA 1 output3 X diy Z amp t57 BC 1 RD output3 X 68 dy 2 amp 58 BC 1 output3 xs 68 1 Z amp 59 BC control 1 amp num cell port func safe ccell dis rslt 60 BC 6 bidir x 59 1 Z amp 61 BC 1 BR_ output2 amp 62 BC 1 input amp 63 BC 1 PINIT input X amp 64 BC 1 control I amp 65 BC 6 SCKR 1 bidir x 64 1 Z amp 66 BC 1 control Ly UR 67 BC 6 FSR 1 bidir X 66 1 2 amp 68 BC 1 control 69 1 EXTAL input X amp 70 BC 1 control 1 amp 71 BC 6 SCKT 1 bidir X 70 1 2 amp 172 BC 1 control 1 amp 173 BC 1 CAS output3 X 72 13 2 amp 74 BC 1 control 1 amp 75 BC 1 AA 2 output3 X 74 l 2 amp 76 BC 1 control 1 amp 77 BC 6 FST 1 bidir X 76 l 2 amp 78 BC 1 control 1 amp 79 6 10050 1 bidir X 78 1 2 amp num cell port func safe ccell dis rslt DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor C 5 JTAG BSDL 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 num 100 101 102 103 104 105 106 107 108 109 120 IIL 122 123 114 125 116 1117 118 119 num 120 121
170. 1 PD1 Input 1 1 ACI Enabled 1 0 PD1 Output 0 0 Disconnected Personal Reset 1 0 PD1 Output 0 1 PDO Input Personal Reset 1 0 PD1 Output 1 0 PDO Output Personal Reset 1 0 PD1 Output 1 1 ACI Enabled 1 1 ADO 0 0 Disconnected Enabled 1 1 ADO 0 1 PDO Input Enabled DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 10 13 GPIO PORT D Pins and Registers Table 10 6 DAX Port GPIO Control Register Functionality PDC1 PC1 ADO PD1 PDCO PCO ACI PDO pin DAX state 1 1 ADO 1 0 PDO Output Enabled 1 1 ADO 1 1 ACI Enabled 10 7 3 Port D Data Register PDRD The read write 24 bit Port D Data Register is used to read or write data to from the DAX GPIO pins Bits PD 1 0 are used to read or write data from to the corresponding port pins if they are configured as GPIO Ifa port pin i is configured as a GPIO input then the corresponding PD i bit will reflect the value present on this pin If a port pin i is configured as a GPIO output then the value written into the corresponding bit will be reflected on the this pin Hardware and software reset clear all PDRD bits PDRD Port D Data Register X FFFFD5 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 LL ICE EST EHE HE IE HE E SEE IEEE C read as zero should be written with zero for future compatibility Figure 10 8 Port D Data Register PDRD DSP56366 24 Bit Digita
171. 1 X X Reserved 1 X X X Reserved DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 11 3 4 5 Inverter INV Bit 8 The INV bit affects the polarity of the incoming signal on the TIOO input signal and the polarity of the output pulse generated on the TIOO output signal The effects of the INV bit are summarized in Table 11 4 Timer Event Counter Programming Model This bit is not in use for timers 1 and 2 It should be left cleared Table 11 4 Inverter INV Bit Operation TIOO Programmed as Input TIOO Programmed as Output Mode 0 1 0 1 0 GPIO signal on the TIOO GPIO signal on the TIOO Bit written to GPIO put on Bit written to GPIO signal read directly signal inverted TIOO signal directly inverted and put on TIOO signal 1 Counter is incremented Counter is incremented on the rising edge of the the falling edge of the signal from the TIOO signal signal from the TIOO signal 2 Counter is incremented on Counter is incremented TCRx output put on TIOO TCRx output inverted and the rising edge of the the falling edge of the signal directly put on TIOO signal signal from the TIOO signal signal from the TIOO signal 3 Counter is incremented Counter is incremented on the rising edge of the the falling edge of the signal from the TIOO signal
172. 12 Host Transmit Underrun Error HTUE Bit 14 7 14 7 4 6 13 HCSR Host Transmit Data Empty HTDE Bit 15 7 15 7 4 6 14 Reserved Bits Bits 23 18 16 7 15 7 4 6 15 Host Receive FIFO Not Empty HRNE Bit 17 _ 7 15 7 4 6 16 Host Receive FIFO Full 19 7 15 7 4 6 17 Host Receive Overrun Error HROE Bit 20 7 15 7 4 6 18 Host Bus Error HBBR Bit 21 7 16 7 4 6 19 HCSR Host Busy HBUSY Bit 22 7 16 7 5 Chatacteristics Of The SPI Bus rer pos 7 16 7 6 Characteristics Of The C Bus 7 16 7 6 1 ioa Ave stia Ra Gee CRUS ACER ERE 7 17 7 6 2 Data Transfer Formats 7 18 7 7 SHI Programming Considerations 7 19 Fel SPI Slave teneo dat EE Ree a 7 19 7 7 2 SPINIJSICEMOUE S yaq ee ead 7 20 7 7 3 ostii inst Car 7 21 7 7 3 1 Receive Data in PC Slave Mode 7 21 7 7 3 2 Transmit Data In PC Slave M
173. 24 4 Bootstrap ADDRESS EXTERNAL GENERATION T ADDRESS PAB ILI BUS SIX CHANNELS _______ __ DAB ___ swrcH UNIT DSP56300 SRAM BUS Core INTERFACE amp CACHE _ L externa INTERNAL i DATA ALU POWER MNGMNT PROGRAM PROGRAM PROGRAM i 24X24 56 gt 56 BIT MAC JTAG CLOCK TWO 56 BIT ACCUMULATORS BARREL SHIFTER MODA IRGA 24 BITS BUS MODB IRQB MODC IRQC MODD IRQD Figure 1 1 DSP56366 Block Diagram DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 1 1 DSP56300 Core Description 1 2 05 56300 Core Description The DSP56366 uses the DSP56300 core a high performance single clock cycle per instruction engine that provides up to twice the performance of Freescale s popular DSP56000 core family while retaining code compatibility with it The DSP56300 core family offers a new level of performance in speed and power provided by its rich instruction set and low power dissipation thus enabling a new generation of wireless telecommunications and multimedia products For a description of the DSP56300 core see Section 1 4 DSP56300 Core Functional Blocks Significant architectural enhancements to the DSP56300 core family include a barrel shifter 24 bit addressing an instruction cache and direct memory access DMA The DSP
174. 2400 1 00 INT RESERVED 7K INTERNAL 8K INTERNAL 7K INTERNAL 0000 RAM 0000 RAM 0000 RAM 1K I CACHE ENABLED Figure 3 15 Memory Maps for MSW 0 1 1 MS 1 5 1 PROGRAM X DATA Y DATA FFFF FFFF INTERNAL FFFF EXTERNAL I O FF80 128 words FFBO 80 words INTERNAL 48 words FF80 EXTERNAL EXTERNAL EXTERNAL C000 6000 32K INTERNAL 8K INTERNAL ROM ROM iN 4090 INT RESERVED secoo NT RESERVED 1508 2400 INT RESERVED 1000 AK INTERNAL 11K INTERNAL 7K INTERNAL 0000 RAM 0000 RAM 0000 RAM 1K I CACHE ENABLED Figure 3 16 Memory Maps for MSW 1 0 1 MS 1 5 1 DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 3 10 Freescale Semiconductor Data and Program Memory Maps 3 1 1 Reserved Memory Spaces The reserved memory spaces should not be accessed by the user They are reserved for future expansion 3 1 2 Program ROM Area Reserved for Freescale Use The last 128 words SFFAF80 SFFAFFF of the Program ROM are reserved for Freescale use This memory area is reserved for use as expansion area for the bootstrap ROM as well as for testing purposes Customer code should not use this area The contents of this Program ROM segment is defined by the Appendix A Bootstrap ROM Contents 3 1 3 Bootstrap ROM The 192 word Bootstrap ROM occupies locations FF0000 SFFOOBF The bootstrap ROM is factory programmed to perform the bootstrap operation following
175. 3 4 Freescale Semiconductor Data and Program Memory Maps PROGRAM X DATA Y DATA SFFFFFF INTERNAL SFFFFFF INTERNAL I O SFFFFFF EXTERNAL I O RESERVED 128 5 80 5 srrrooo EXTERNAL FFFFBO 40K INTERNAL INTERNAL 48 words ROM INTERNAL SFFFF80 FF1000 RESERVED FFF000 EXTERNAL INTERNAL INTERNAL RESERVED srFooco RESERVED 0000 EXTERNAL EXTERNAL 00 000 006000 EXTERNA 32K INTERNAL 8K INTERNAL ROM ROM 004000 004000 RESERVED 002800 FK RAM gsoo coo NT RESERVED 001C00 002400 001000 INT RESERVED INTERNAL 11K INTERNAL 7K INTERNAL 000000 RAM 000000 RAM 000000 RAM Figure 3 5 Memory Maps for MSWz 1 0 0 5 1 5 0 PROGRAM X DATA Y DATA SFFFFFF INTERNAL SFFFFFF INTERNAL SFFFFFF EXTERNAL RESERVED 128 words 80 words SFFB090 FFFooo EXTERNAL FFFFB0 40K INTERNAL INTERNAL 48 words ROM INTERNAL FFFF80 FF1000 RESERVED FFF000 EXTERNAL INTERNAL iu Bises INTERNAL RESERVED RESERVED FFOOCO 5 0000 ROM EXTERNAL EXTERNAL 00 000 006000 32K INTERNAL 8K INTERNAL ROM ROM EXTERNAL 004000 004000 esse ss INT RESERVED 002000 001400 002400 9K INTERNAL 8K INTERNAL 5K INTERNAL 0
176. 3 Trap VBA 0A 3 Non Maskable Interrupt NMI VBA 0C 3 Reserved For Future Level 3 Interrupt Source VBA 0E 3 Reserved For Future Level 3 Interrupt Source VBA 10 0 2 IRQA VBA 12 0 2 IRQB VBA 14 0 2 IRQC VBA 16 0 2 IRQD VBA 18 0 2 DMA Channel 0 VBA 1A 0 2 DMA Channel 1 VBA 1C 0 2 DMA Channel 2 VBA 1E 0 2 DMA Channel 3 VBA 20 0 2 DMA Channel 4 VBA 22 0 DMA Channel 5 VBA 24 0 Reserved VBA 26 0 2 Reserved VBA 28 0 2 DAX Underrun Error VBA 2A 0 2 DAX Block Transferred VBA 2C 0 2 Reserved VBA 2E 0 2 DAX Audio Data Empty VBA 30 0 2 ESAI Receive Data VBA 32 0 2 ESAI Receive Even Data VBA 34 0 2 ESAI Receive Data With Exception Status VBA 36 0 2 ESAI Receive Last Slot VBA 38 0 2 ESAI Transmit Data VBA 3A 0 2 ESAI Transmit Even Data VBA 3C 0 ESAI Transmit Data with Exception Status VBA 3E 0 ESAI Transmit Last Slot VBA 40 0 2 SHI Transmit Data DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor Table D 2 DSP56366 Interrupt Vectors continued Interrupt Vector Addresses Added interrupt Source VBA 42 0 2 SHI Transmit Underrun Error VBA 44 0 2 SHI Receive FIFO Not Empty VBA 46 0 2 Reserved VBA 48 0 2 SHI Receive FIFO Full VBA 4A 0 2 SHI Receive Overrun Error VBA 4C 0 2 SHI Bus Error VBA 4E 0 2 Reserved VBA 50 0 2 Reserved VBA 52 0 2
177. 323H O3I3 peAJeso4 9 9291 YSIO J 146 L 3OHH 04 3 JO 45601 JI 55 0 30HH 9 3NSH jou 0514 e re2es 450 J peuessy eu paiqesip MAU 9A419991 peeJ 4501 JI peuessv uonipuo23 D 29 SHI Host Control Status Register Figure D 14 DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor Programming Sheets Date Application Programmer LLLIWV vodl Odsal 5 1 L lb S 9 18 Jo X V ES 995 992 L 445 00 JojeJeueB 10 SI seyioeds uonduoseg 0 2 pessed q 1ejeosaud 8 Aq g uonduoseg L 98ees Ze 1 44 00 JEPIAIG uonduoseg 0 7 1 6L 0c lo cc tt t u gg 89S 9L L 4 0 yoojo ASu nb uj uBiu UOISSIUISUEJ JO
178. 56300 core family members contain the DSP56300 core and additional modules The modules are chosen from a library of standard predesigned elements such as memories and peripherals New modules may be added to the library to meet customer specifications A standard interface between the DSP56300 core and the on chip memory and peripherals supports a wide variety of memory and peripheral configurations Refer to Section 3 Memory Configuration Core features are described fully in the DSP56300 Family Manual Pinout memory and peripheral features are described in this manual DSP56300 modular chassis 120 Million Instructions Per Second MIPS with an 120 MHz clock at 3 3V Object Code Compatible with the 56K core Data ALU with a 24 x 24 bit multiplier accumulator and 56 bit barrel shifter 16 bit arithmetic support Program Control with position independent code support and instruction cache support Six channel DMA controller PLL based clocking with a wide range of frequency multiplications 1 to 4096 predivider factors 1 to 16 and power saving clock divider 2 1 0 to 7 Reduces clock noise Internal address tracing support and OnCE for Hardware Software debugging JTAG port Very low power CMOS design fully static design with operating frequencies down to DC STOP and WAIT low power standby modes e On chip Memory Configuration 7K x 24 Bit Y Data RAM and 8K x 24 Bit Y Data ROM
179. 6 12 8 3 6 13 8 3 6 14 8 3 7 8 3 8 8 3 9 8 3 10 RCCR Receiver High Frequency Clock Direction RHCKD Bit 23 8 26 ESAI Receive Control Register RCR 8 26 ESAI Receiver 0 Enable REO 8 27 RCR ESAI Receiver 1 Enable 1 l 8 27 RCR ESAI Receiver 2 Enable RE2 BIf2 8 27 ESAI Receiver 3 Enable Bit3 8 27 Reserved Bits Bits 4 5 17 18 8 27 RCR Receiver Shift Direction RSHFD Bit6 8 27 Receiver Word Alignment Control RWA Bit 7 8 28 RCR Receiver Network Mode Control RMODI RMODO Bits 8 9 8 28 RCR Receiver Slot and Word Select RSWSA4 RSWSO Bits 10 14 8 28 Receiver Frame Sync Length RFSL Bit 15 8 30 Receiver Frame Sync Relative Timing RFSR Bit 16 8 30 RCR Receiver Section Personal Reset RPR 19 8 30 RCR Receive Exception Interrupt Enable REIE Bit 20 8 31 RCR Receive Even Slot Data Interrupt Enable Bit21 8 31 RCR Receive Interrupt Enable RIE Bit 22 8 31 RCR Receive Last Slot Interrupt Enable RLIE
180. 66 Bootstrap Program MD MC MB MA 1001 is used for Burn in code BURN RESER MB omr BURN IF MD MC MB MA 1001 go to BURN The following modes are reserved some of which are used for internal testing MD MC MB MA 0011 is reserved MD MC MB MA 1010 is reserved MD MC MB MA 1011 is reserved RESERVED bra lt M PCRC EQU SFFFFBF Port C GPIO Control Register M EQU SFFFFBD Port C GPIO Data Register M PRRC EQU SFFFFBE i Port C Direction Register SCKT EQU 3 SCKT is GPIO bit 3 in ESAI Port C EQUALDATA equ 0 1 if xram and yram are of equal Size and addresses 0 otherwise if EQUALDATA start dram equ 0 n length dram equ 1600 Same addresses else start xram equ 0 13k XRAM length xram equ 3400 start yram equ 0 7k length yram equ 51200 endif start pram equ 0 PRAM length pram equ 5 00 BURN get PATTERN pointer clr b HPATTERNS b is the error accumulator move lt NUM PATTERNS 1 m6 ii program runs forever in Cyclic form configure SCKT as gpio output movep Clear GPIO data register belr HSCKT x M PCRC Define SCKT as output GPIO pin bset HSCKT x M PRRC SCKT toggles means test pass DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 A 10 Freescale Semiconductor burnin loop if else endif if lua 15 ii do 9 burnl test RAM move 26 1 n move p r6 x0 d
181. 7 Configure line 1 MISOO MOSIO SCKO for SPI master line 2 550 PC3 for line 3 Hex values are indicated with a dollar sign preceding the hex value as follows FFFFFF is the X memory address for the core interrupt priority register IPR C The word reset is used in four different contexts in this manual the reset signal written as RESET the reset instruction written as RESET the reset operating state written as Reset and the reset function written as reset DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor iii NOTES DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 1 DSP56366 Overview 1 1 Introduction This manual describes the DSP56366 24 bit digital signal processor DSP its memory operating modes and peripheral modules The DSP56366 is a member of the DSP56300 family of programmable CMOS DSPs The DSP56366 is targeted to applications that require digital audio compression decompression sound field processing acoustic equalization and other digital audio algorithms Changes in core functionality specific to the DSP56366 are also described in this manual See Figure 1 1 for the block diagram of the DSP56366 MEMORY EXPANSION AREA DAX PROGRAM RAM TRIPLE SPDIF Tx INSTR TIMER INTER FAC CACHE 3K x 24 ROM PROGRAM 32K x 24 ROM 40K x
182. 8 interrupt control 7 8 Interrupt Vectors SHI 5 INV 9 J JTAG 7 22 JTAG OnCE port 1 L LA register 6 LC register 6 Loop Address register LA 6 Loop Counter register LC 6 M MAC 4 Manual Conventions 11 memory expansion 8 external expansion port 8 off chip 8 on chip 7 mode control 7 8 modulo adder 5 multiplier accumulator MAC 4 O offset adder 5 OMR register 6 OnCE module 7 22 On Chip Emulation OnCE module 7 on chip memory 7 Operating Mode Register OMR 6 P PAB 6 PAG 5 PC register 6 20 bits 6 PCE 11 PCU 5 PDB 6 PDC 5 Peripheral I O Expansion Bus 6 PIC 5 PLO PL20 bits 5 PL21 PL22 bits 5 PLL 7 1 4 Port 1 5 Port B 1 9 10 11 12 1 Port C 1 15 19 1 2 Port D 21 1 Power 2 power 1 Prescaler Counter 5 Prescaler Counter Value bits PCO PC20 6 Prescaler Load Value bits PLO PL20 5 Prescaler Source bits PL21 PL22 5 Program Address Bus PAB 6 Program Address Generator PAG 5 Program Control Unit PCU 5 Program Counter register PC 6 Program Data Bus PDB 6 Program Decode Controller PDC 5 Program Interrupt Controller PIC 5 Program Memory Expansion Bus 6 Programming Model SHI DSP Side 4 SHI Host Side 3 DSP56366 24 Bit Digital Signal Processor Rev 4 Freescale Semiconductor Index 3 H reserved bits in TCSR register bits 3 10 14 16 19 22 23 11 in TPCR 6 in TPLR 6 RESET 8 reverse carry adder 5 5 SC register 6 Serial Host Int
183. 8 17 16 15 14 13 12 41 10 9 8 7 6 5 4 3 2 1 0 Current Value of Prescaler Counter PC 0 20 Timer Prescaler Count Register Reserved Program as 0 TPCR FFFF82 Read Only Reset 000000 Figure D 30 Timer Prescaler Load and Prescaler Count Registers TPLR TPCR DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor D 45 Programming Sheets Application Inverter Bit 8 0 0 to 1 transitions on TIO input increment the counter Date Programmer or high pulse width measured or high pulse output on TIO 1 1 to 0 transitions on TIO input increment the counter or low pulse width measured or low pulse output on TIO Timer Control Bits 4 7 TC3 Timer Reload Mode Bit 9 0 Timer operates as a free running counter 1 Timer is reloaded when selected condition occurs Direction Bit 11 0 TIO pin is input 1 TIO pin is output Data Input Bit 12 0 Zero read on TIO pin 1 One read on TIO Data Output Bit 13 0 Zero written to TIO pin 1 One written to TIO pin Prescaled Clock Enable Bit 15 0 Clock source is CLK 2 or TIO 1 Clock source is prescaler output Timer Compare Flag Bit 21 0 1 has been written to TCSR TCF or timer compare interrupt serviced 1 Timer Compare has occurred Timer Overflow Flag Bit 20 0 1 has been written to TCSR TOF or timer Overflow interrupt serviced 1 Counter wraparound has occurred
184. 8 3 2 4 TCR ESAI Transmit 3 Enable TE3 Bit 3 enables the transfer of data from TX3 to the transmit shift register 3 When is set and a frame sync is detected the transmit 3 portion of the ESAI is enabled for that frame When is cleared the transmitter 3 is disabled after completing transmission of data currently in the ESAI transmit shift register Data can be written to TX3 when is cleared but the data is not transferred to the transmit shift register 3 The SDO3 SDI2 pin is the data input pin for RX2 if is cleared and RE2 in the register is set If both RE2 and are cleared the transmitter and receiver are disabled and the pin is tri stated Both RE2 and should not be set at the same time The normal mode transmit enable sequence is to write data to one or more transmit data registers before setting TEx The normal transmit disable sequence is to clear TEx TIE and TEIE after TDE equals one In the network mode the operation of clearing and setting it again disables the transmitter 3 after completing transmission of the current data word until the beginning of the next frame During that time period the SDO3 SDD pin remains in the high impedance state The on demand mode transmit enable sequence can be the same as the normal mode or TE3 can be left enabled 8 3 2 5 TCR ESAI Transmit 4 Enable Bit 4 4 enables the transfer of data from TX4 to the transmit shi
185. 9 3 4 2 RCCR 1 Rx High Freq Clock Polarity RHCKP 20 9 9 DSP56366 24 Bit Digital Signal Processor Rev 4 TOC 8 Freescale Semiconductor 9 3 4 3 RCCR 1 Rx High Freq Clock Direction RHCKD Bit 23 9 9 9 3 5 ESAI 1 Receive Control Register _1 9 10 9 3 6 ESAI 1 Common Control Register 1 _1 9 10 9 3 7 ESAI 1 Status Register SAISR dera y XU 9 10 9 3 8 ESAI T Receive Shift uot ee Debe d ep SS 9 11 9 3 9 ESAI 1 Receive Data Registers 9 11 9 3 10 ESAI 1 Transmit Shift Registers 9 11 9 3 11 ESAI 1 Transmit Data 9 11 9 3 12 ESAT L lime Slot Register TSR EY ebur he cats ds 9 12 9 3 13 Transmit Slot Mask Registers 1 TSMB 1 9 12 9 3 14 Receive Slot Mask Registers 1 RSMB 1 9 12 94 Operating MOdES x Eae eee Ee 9 13 9 4 Ier a SML Ere te eM 9 13 9 5 GPIO Pins and Registers vule dee 9 13 9 5 1 Port E Control Register PORE 2 Cer edd 9 13 9 5 2 Por
186. 95 42H jues 2 9 5 8 995 4S ues L O 9 995 HYOS jues spioH Programmer Date uondeoaiJ Buunp Jn990 2u s uondeooiJ Buunp Jn990 JOU pip 2u s ejep ue e uonduoseq Application IVS3 000000 19598 82224 611836 IVS3 MSIVS Aydwe eep ppo 5 Eg sJejsi 8J uonduoseg jusueJ jou jtusueJ uonduoseg D 20 ESAI Status Register uonduoseg Figure uoissiuusueJ paom ouAs 4n220 jou pip Su s awed JIUISUEJ uonduoseg ______________ uonduoseq BH 19151694 ejep ppo uonduoseg DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 D 35 Freescale Semiconductor Programming Sheets Application Programmer 0 c r S 9 1 8 6 0L Wo v GS 9 1 6b 0 uonduoseg 894 5
187. A1 GPIO this bit is treated 0 Enable as 1 if HMUX O this bit is treated 1 HA8 HA1 HA8 HA1 as 0 if HEN 0 2 HA9EN Host Address Line 9 0 HA9 HA2 GPIO this bit is treated 0 Enable as 1 if HMUX O this bit is treated 1 HA9 HA2 HA9 HA2 as 0 if HEN 0 3 HCSEN Host Chip Select Enable 0 HCS HA10 GPIO this bit is treated 0 1 HCS HA10 HCS HA10 as 0 if HEN 0 4 HREN Host Request Enable 0 HOREQ HTRQ GPIO this bit is treated 0 HACK HRRQ GPIO as 0 if HEN O 1 HOREQ HTRQ HOREQ HTRQ HACK HRRQ HACK HRRQ 5 HAEN Host Acknowledge Enable 0 HACK HRRQ GPIO this bitis ignored if 0 HDRQ 1 this bit is treated as 0 if HREN 0 1 HACK HRRQ HACK this bit is treated as 0 if HEN 0 6 HEN Host Enable 0 Host Port GPIO 0 1 Host Port Active 8 HROD Host Request Open Drain 0 HOREQ HTRQ HRRQ driven this bit is ignored if 0 1 HOREQ HTRQ HRRQ open drain 0 9 HDSP Host Data Strobe Polarity 0 HDS HRD HWR active low this bitis ignored if 0 1 HDS HRD HWR active high 0 10 HASP Host Address Strobe 0 HAS active low this bit is ignored if 0 Polarity 1 HAS active high 0 11 HMUX Host Multiplxed Bus 0 Separate address and data lines this bitis ignored if 0 1 Multiplexed address data 0 12 HDDS Host Dual Data Strobe 0 Single Data Strobe HDS this bit is ignored if 0 1 Double Data Strobe HWR HRD 0 13 HCSP Host Chip Select Polarity 0 HCS active low this bitis ignored
188. A9 r1 prepare SHI control value in r1 HEN 1 2 0 1 0 10 HCKFR 0 HFIFO 1 HMST 0 HRQE1 HRQEO 01 HIDLE 0 HBIE 0 HTIE 0 HRIE1 HRIEO 00 4MA omr SHI CF If MD MC MB MA 01x0 go to SHI clock freeze MB omr shi_loop If MD MC MB MA 0101 select SPI mode bset HHI2C r1 otherwise select I2C mode shi loop movep r1 x M_HCSR enable SHI HRNE wait for no of words movep 0 HRNE x M_HCSR wait for starting address movep 0 move r0 r1 do a0 LOOP2 wait for HRX not empty movep HRX p Store in Program RAM nop req because of restriction _ 2 bra FINISH SHI CF bset HI2C r1 select I2C mode bset HCKFR r1 enable clock freeze in I2C mode bset HFM0 x M_HCKR enable 100ns noise filter bset HFM1 x M_HCKR enable 100ns noise filter jset 1 MD MC MB MA 0110 go to I2C load bra RESERVED If MD MC MB MA 0100 go to reserved This is the routine that loads from external EPROM DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor A 5 DSP56366 Bootstrap Program MD MC MB MA 0001 EPROMLD move BOOT r2 2 address of external EPROM movep 1 aarl configured for SRAM types of access do 6 LOOP9 read number of words and starting ad
189. AG1OUT TFSL SYNC MODE SYNC MODE TX WORD CLOCK TRANSMITTER INTERNAL TX FRAME CLOCK FRAME RATE DIVIDER TRANSMIT CONTROL LOGIC FRAME SYNC Figure 9 5 ESAI 1 Frame Sync Generator Functional Block Diagram 9 3 3 ESAI 1 Transmit Control Register TCR 1 The read write Transmit Control Register 1 controls the ESAI 1 transmitter section Interrupt enable bits for the transmitter section are provided in this control register Operating modes are also selected in this register 11 10 9 8 7 6 5 4 3 2 1 0 Y FFFF95 TSWS1 TSWSO TMOD1 TMODO TWA TSHFD 5 4 2 TE1 TEO 23 22 21 20 19 18 17 16 15 14 13 12 TLIE TIE TEDIE TEIE TPR TFSR TFSL 5 54 TSWS3 TSWS2 Reserved bit read as zero should be written with zero for future compatibility Figure 9 6 TCR 1 Register Hardware and software reset clear all the bits in the TCR 1 register DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 9 8 Freescale Semiconductor ESAI 1 Programming Model 9 3 4 ESAI 1 Receive Clock Control Register RCCR 1 The read write Receive Clock Control Register RCCR 1 controls the ESAI 1 receiver clock generator bit and frame sync rates word length and number of words per frame for the serial data 11 10 9 8 7 6 5 4 3 2 1 0 Y FFFF98 RDC2 RDC1 RDCO RPSR RPM7 6
190. Address Tracing Enable Master memory Switch Mode MSW1 Memory switch mode 1 APD Address Priority Disable SD Stop Delay MSWO Memory switch mode 0 ABE Asyn Bus Arbitration Enable SEN Stack Extension Enable BRT Bus Release Timing EBD External Bus Disable WRP Extended Stack Wrap Flag TAS TA Synchronize Select MD Operating Mode D EOV Extended Stack Overflow Flag Burst Mode Enable MC Operating Mode C EUN Extended Stack Underflow Flag CDP1 Core Dma Priority 1 MB Operating Mode B XYS Stack Extension Space Select CDPO Core Dma Priority 0 MA Operating Mode A Reserved bit Read as zero should be written with zero for future compatibility 4 2 1 Asynchronous Bus Arbitration Enable ABE Bit 13 The asynchronous bus arbitration mode is activated by setting the ABE bit in the OMR register Hardware reset clears the ABE bit 4 2 2 Address Attribute Priority Disable APD Bit 14 The Address Attribute Priority Disable APD bit is used to turn off the address attribute priority mechanism When this bit is set more than one address attribute pin AA RAS 2 0 may be simultaneously asserted according to its AAR settings The APD bit is cleared by hardware reset 4 2 3 Address Tracing Enable ATE Bit 15 The Address Tracing Enable ATE bit is used to turn on Address Tracing AT Mode When the AT Mode is enabled the DSP56300 Core reflects the addresses of internal fetches and program space moves
191. Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor Host Interface Quick Reference 0 5 Host Interface Quick Reference Table D 4 HDIO8 Programming Model Bit Reset Type Reg Comments HW Num Mnemonic Name Val Function SW IR ST DSP SIDE HCR 0 HRIE Receive Interrupt Enable 0 interrupt disabled 0 1 interrupt enabled 1 HTIE Transmit Interrupt Enable 0 HTRQ interrupt disabled 0 1 HTRQ interrupt enabled 2 HCIE Host Command Interrupt 0 HCP interrupt disabled 0 Enable 1 HCP interrupt enabled 3 HF2 Host Flag 2 0 4 HF3 Host Flag 3 0 7 5 HDM 2 0 Host Mode 000 operation disabled 000 100 DMA operation enabled 001 24 bit host to DSP DMA enabled 010 16 bit host to DSP DMA enabled 011 8 bit host to DSP DMA enabled 101 24 bit DSP to host DMA enabled 110 16 bit DSP to host DMA enabled 111 8 bit DSP to host DMA enabled DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor Host Interface Quick Reference Table 0 4 HDI08 Programming Model continued Bit Reset Type Reg Comments HW Num Mnemonic Name Val Function SW IR ST HPCR 0 HGEN Host GPIO Enable 0 pin disconnected 0 1 GPIO pins active 1 Host Address Line 8 0 HA8 H
192. Control 56 1 Output3 Data 132 SDO5 SDIO Input Output Data 57 RD Output3 Data 133 SDO4 SDI1 Control 58 WR Output3 Data 134 SDO4 SDI1 Input Output Data 59 Control 135 SDO3 SDI2 Control 60 BB Input Output Data 136 SDO3 SDI2 Input Output Data 61 BR Output2 Data 137 SDO2 SDI3 Control 62 Input Data 138 SDO2 SDI3 Input Output Data 63 PINIT Input Data 139 5201 Control 64 SCKR 1 Control 140 SDO1 Input Output Data 65 SCKR 1 Input Output Data 141 5200 Control 66 FSR 1 Control 142 SDOO Input Output Data 67 FSR 1 Input Output Data 143 Control 68 RD WR Control 144 HREQ Input Output Data DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 4 16 Freescale Semiconductor Table 4 10 DSP56366 BSR Bit Definition continued JTAG Boundary Scan Register BSR pu Pin Name Pin Type e P Pin Name Pin Type e 69 Input Data 145 SS Input Data 70 SCKT 1 Control 146 SCK SCL Control 71 SCKT 1 Input Output Data 147 SCK SCL Input Output Data 72 CAS Control 148 MISO SDA Control 73 CAS Output3 Data 149 MISO SDA Input Output Data 74 2 Control 150 MOSI HAO Control 75 2 Output3 Data 151 MOSI HAO Input Output Data DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 4 17 lt a snw lt OKUO ssapacA JTAG B
193. DI2 PC8 5004 5011 PC7 SDO5 SDIO PC6 E DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 8 2 Freescale Semiconductor ESAI Data and Control Pins 8 2 ESAI Data and Control Pins Three to twelve pins are required for operation depending on the operating mode selected and the number of transmitters and receivers enabled The SDOO and 5001 pins are used by transmitters 0 and 1 only The SDO2 SDI3 SDO3 SDD SDO4 SDI1 and SDOS SDIO pins are shared by transmitters 2 to 5 with receivers 0 to 3 The actual mode of operation is selected under software control transmitters operate fully synchronized under control of the same transmitter clock signals receivers operate fully synchronized under control of the same receiver clock signals 8 2 1 Serial Transmit 0 Data Pin SDOO 5000 is used for transmitting data from the TXO serial transmit shift register SDOO is an output when data is being transmitted from the shift register In the on demand mode with an internally generated bit clock the SDOO pin becomes high impedance for a full clock period after the last data bit has been transmitted assuming another data word does not follow immediately If a data word follows immediately there is no high impedance interval SDOO may be programmed as a general purpose I O pin PC11 when the ESAI SDOO function is not being used 8 2 2 Serial Transmit 1 Data Pin 5001 SDOI is used for transmitting data
194. DO3 1 8 12 1 transmits data from the TX3 1 serial transmit shift register when programmed as a transmitter pin or receives serial data to the RX2 1 serial receive shift register when programmed as a receiver pin It is shared with the ESAI SDO3 SDD signal The pin may be used as SDO3_1 SDI2_1 if it is not defined as ESAI SDO3 SDI2 The pin may be used GPIO if not used by the ESAI or ESAI 1 The ESAI 1 Multiplex Control Register EMUXR defines if the pin belongs to the ESAI or to the ESAI 1 9 2 5 Serial Transmit 4 Receive 1 Data Pin 5004 1 SDM 1 5004 1 8 1 transmits data from the 4 1 serial transmit shift register when programmed as a transmitter pin or receives serial data to the 1 serial receive shift register when programmed as a receiver 5204 1 5011 1 may be programmed as a general purpose pin PE7 when the ESAI 1 5004 land 5011 1 functions are not being used DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 9 3 ESAI 1 Programming Model 9 2 6 Serial Transmit 5 Receive 0 Data Pin SDO5 1 SDIO 1 SDOS I SDIO 1 transmits data from the 5 1 serial transmit shift register when programmed as transmitter pin or receives serial data to the RXO 1 serial shift register when programmed as a receiver 58005 1 SDIO 1 may be programmed as a general purpose pin PE6 when the ESAI 1 5005 1 and SDIO 1 functions are not being used 9 2 7 Receiver Serial Clock SCK
195. DSP Core Clock f 1024 X fs 0 1 ACI Pin f 2 256 X fs 1 0 ACI Pin f 2 384 X fs 1 1 ACI Pin f 2 512 X fs 10 5 6 5 Start Block XSB Bit 5 The XSB bit forces the DAX to start a new block When this bit is set the next frame will start with Z preamble and will start a new block even though the current block was not finished This bit is cleared when the new block starts 10 5 6 6 XCTR Reserved Bits Bits 6 23 These XCTR bits are reserved They read as 0 and should be written with 0 for future compatibility 10 5 7 DAX Status Register XSTR The XSTR is a 24 bit read only register that contains the DAX status flags The contents of the XSTR are shown in Figure 10 2 XSTR is cleared by software reset hardware reset an by the stop state The XSTR bits are described in the following paragraphs DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 10 7 DAX Internal Architecture 10 5 7 1 Audio Data Register Empty XADE Bit 0 The XADE status flag indicates that the DAX audio data register XADR and the audio data buffer XADBUFA are empty and ready to receive the next frame s audio data This bit is set at the beginning of every frame transmission more precisely when channel A audio data is transferred from XADBUFA to XADSR When is set and the interrupt is enabled XDIE 1 an audio data register empty interrupt request is sent to the DSP core XADE
196. DSP56300 Core Functional Blocks Instruction cache controller PLL based clock oscillator module Memory In addition the DSP56366 provides a set of on chip peripherals described in Section 1 5 Peripheral Overview 1 4 1 Data ALU The Data ALU performs all the arithmetic and logical operations on data operands in the DSP56300 core The components of the Data ALU are as follows Fully pipelined 24 bit x 24 bit parallel multiplier accumulator MAC Bit field unit comprising a 56 bit parallel barrel shifter fast shift and normalization bit stream generation and parsing Conditional ALU instructions 24 bit or 16 bit arithmetic support under software control Four 24 bit input general purpose registers X1 Y1 and YO Six Data ALU registers A2 Al AO B2 B1 and BO that are concatenated into two general purpose 56 bit accumulators A and B accumulator shifters Two data bus shifter limiter circuits 1 4 1 1 Data ALU Registers The Data ALU registers can be read or written over the X memory data bus XDB and the Y memory data bus YDB as 24 or 48 bit operands or as 16 or 32 bit operands in 16 bit arithmetic mode The source operands for the Data ALU which can be 24 48 or 56 bits 16 32 or 40 bits in 16 bit arithmetic mode always originate from Data ALU registers The results of all Data ALU operations are stored in an accumulator the Data ALU operations
197. DSP56366 24 Bit Digital Signal Processor User Manual Document Number DSP56366UM 08 2006 semiconductor How to Reach Us Home Page www freescale com E mail support freescale com USA Europe or Locations Not Listed Freescale Semiconductor Technical Information Center CH370 1300 N Alma School Road Chandler Arizona 85224 1 800 521 6274 or 1 480 768 2130 support freescale com Europe Middle East and Africa Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen Germany 44 1296 380 456 English 46 8 52200080 English 49 89 92103 559 German 33 1 69 35 48 48 French support freescale com Japan Freescale Semiconductor Japan Ltd Headquarters ARCO Tower 15F 1 8 1 Shimo Meguro Meguro ku Tokyo 153 0064 Japan 0120 191014 or 81 3 5437 9125 support japan freescale com Asia Pacific Freescale Semiconductor Hong Kong Ltd Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 800 2666 8080 support asia freescale com For Literature Requests Only Freescale Semiconductor Literature Distribution Center P O Box 5405 Denver Colorado 80217 1 800 521 6274 or 303 675 2140 Fax 303 675 2150 LDCForFreescaleSemiconductor hibbertgroup com Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products There are no exp
198. DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 1 6 Freescale Semiconductor DSP56300 Core Functional Blocks End of block transfer interrupts Triggering from interrupt lines and all peripherals 1 4 6 PLL based Clock Oscillator The clock generator in the DSP56300 core is composed of two main blocks the PLL which performs clock input division frequency multiplication and skew elimination and the clock generator CLKGEN which performs low power division and clock pulse generation PLL based clocking Allows change of low power divide factor DF without loss of lock Provides output clock with skew elimination Provides a wide range of frequency multiplications 1 to 4096 predivider factors 1 to 16 and a power saving clock divider 2 1 0 to 7 to reduce clock noise The PLL allows the processor to operate at a high internal clock frequency using a low frequency clock input This feature offers two immediate benefits A lower frequency clock input reduces the overall electromagnetic interference generated by a system The ability to oscillate at different frequencies reduces costs by eliminating the need to add additional oscillators to a system 1 4 7 JTAG TAP and OnCE Module The DSP56300 core provides a dedicated user accessible TAP fully compatible with the IEEE 1149 1 Standard Test Access Port and Boundary Scan Architecture Problems associated with testing high density circuit boards
199. Date Application Programmer 0 L 4 r SI 9 2 8 6 OL L vl S 9L IZL Sb 6L Oc L 3015 361 ejep Jo 9J0Jeq 420 9 2446 ujBue pJoM 3015 16 Jo o snouoJuouKs ou s ujBue pJoM uonduoseg uonduoseg pejqeue 01987 192 a peufije y eyeq uonduoseg WML Josey jeuosJeg uoneJedo mw wonduoseq __ pewsed OMEN o 0 1dnuueju uondeox3 mmm 0 peiqesip 1dnujeju uondeox3 apo OGOWL LAONL uondii5Ss q p lqeu Ydnueju 1016 ue 3 9 8 pue Qy Z 8 995 pue 10 p jqes p 1dn u lul 1016 ue 3 uonduoseq v 0 SMSL uonduoseq ou s poued 1Iq E ous o p lqeu ydnueju jusueJ peiqesip 1dnuu lul uonduoseg 1841 uonduoseg 101 1527 L IVSd 000000 3 5 84444 nuaw 1015 0 1013409 1 6 IVS3 HOL uonduosoeg it Control Register ESAI Transm D 16
200. EIE Bit 20 When TEIE is set the DSP is interrupted when both TDE and TUE in the SAISR status register are set When TEIE is cleared this interrupt is disabled Reading the SAISR status register followed by writing to all the data registers of the enabled transmitters clears TUE thus clearing the pending interrupt DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 8 21 ESAI Programming Model 8 3 2 17 TCR Transmit Even Slot Data Interrupt Enable TEDIE Bit 21 The TEDIE control bit is used to enable the transmit even slot data interrupts If TEDIE is set the transmit even slot data interrupts are enabled If TEDIE is cleared the transmit even slot data interrupts are disabled A transmit even slot data interrupt request is generated if TEDIE is set and the TEDE status flag in the SAISR status register is set Even time slots are all even numbered time slots 0 2 4 etc when operating in network mode The zero time slot in the frame is marked by the frame sync signal and is considered to be even Writing data to all the data registers of the enabled transmitters or to TSR clears the TEDE flag thus servicing the interrupt Transmit interrupts with exception have higher priority than transmit even slot data interrupts therefore if exception occurs TUE is set and TEIE is set the ESAI requests an ESAI transmit data with exception interrupt from the interrupt controller 8 3 2 18 TCR Transmit I
201. Encoder on S e c ver ere a dece Seen 10 9 10 5 10 DAX Preamble Generator q s 2i ota xor ERR ERE VR oe REOR XE S 10 9 10 511 DAX Clock esee dunk eret 10 9 10 5 12 DA State Machine core goa den Sh rib Kex alas 10 10 10 6 DAX Programming Considerations 10 10 10 6 1 Initiating A Transmit Session 252 SR E PUR UNS 10 10 10 6 2 Audio Data Register Empty Interrupt Handling 10 10 10 6 3 Block Transferred Interrupt Handling 10 11 10 6 4 DAX operation with DMA 10 11 10 6 5 DAX Operation During Stop ic scudo vx Rc Re OR RON 10 12 107 GPIO PORT D Pins and Registers 10 12 10 7 1 Port D Control Register ser eek QU Fut 10 12 10 7 2 Port D Direction Register PRRD 10 13 10 7 3 Port D Data Register PDRD 10 14 11 Timer Event Counter 11 1 llb quud M RE Eas sui m Su LUE US 11 1 11 2 Timer Event Counter Architecture 11 1 11 2 1 Timer Event Counter Block Di
202. F RPM7 EQU 7 ESAI RPM6 EQU 6 ESAI M RPM5 EQU 5 ESAI M EQU 4 ESAI EQU 3 ESAI RPM2 EQU 2 ESAI DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor B 25 Equates M M RPMO M RLIE M RIE M REDIE M REIE M RPR M RFSR M RFSL M RSWS RSWSA4 M RSWS3 M RSWS2 M RSWS1 M RSWSO M RMOD M RMOD1 M RMODO M RWA M RSHFD M RE M RE3 M RE2 M M REO EQU EQU RCR Register bits EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU 1 ESAI 0 ESAI 23 ESAI 22 ESAI 21 ESAI 20 ESAI 19 ESAI 16 ESAI 15 ESAI 7C00 ESAI MASK 14 ESAI 13 ESAI 12 ESAI 11 ESAI 10 ESAI 300 9 ESAI 8 ESAI ESAI 6 ESAI SF 3 ESAI 2 ESAI i ESAI 0 ESAI TCCR Register bits DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 B 26 Freescale Semiconductor Equates M THCKD EQU 23 ESAI EQU 22 ESAI M EQU 21 ESAI M EQU 20 ESAI M TFSP EQU 19 ESAI M EQU 18 ESAI M TFP EQU 3C000 M TFP3 EQU 17 ESAI 2 EQU 16 ESAI M TFP1 EQU 15 ESAI M TFPO EQU 14 ESAI M TDC EQU 3E00 EQU 13 ESAI M TDC3 EQU 12 ESAI M 2 EQU 11 ESAI M TDC1 EQU 10 ESAI M EQU 9
203. FO is full and IOSR is filled an overrun error occurs and the HROE status bit is set In this case the last received byte is not acknowledged ACK 1 is sent and the word in the IOSR is not transferred to the HRX FIFO This may inform the external master device of the occurrence of an overrun error on the slave side Consequently I C master device may terminate this session by generating a stop event If HCKFR is set when the HRX FIFO is full the SHI holds the clock line to GND not letting the master device write to IOSR which eliminates the possibility of reaching the overrun condition The HREQ output pin if enabled for receive HRQE 1 0 01 is asserted when the IOSR is ready to receive and the HRX FIFO is not full this operation guarantees that the next received data word is stored in the FIFO HREQ is deasserted at the first clock pulse of the next received word The HREQ line may be used to interrupt the external master device Connecting the HREQ line between two SHI equipped DSPs one operating as an master device and the other as an C slave device enables full hardware handshaking 7 7 3 2 Transmit Data In 2 Slave Mode A transmit session is initiated when the personal slave device address has been correctly identified and the R W bit of the received slave device address byte has been set Following a transmit initiation the IOSR is loaded from HTX assuming the latter was not empty and its contents
204. Freescale Semiconductor 4 13 JTAG Boundary Scan Register BSR Table 4 9 JTAG Identification Register Configuration 31 28 27 22 21 12 11 1 Version Customer Part Sequence Manufacturer 1 Information Number Number Identity 0000 000111 0001001 111 00000001 110 1 4 9 JTAG Boundary Scan Register BSR The boundary scan register BSR in the DSP56366 JTAG implementation contains bits for all device signal and clock pins and associated control signals bidirectional pins have a single register bit in the boundary scan register for pin data and are controlled by an associated control bit in the boundary scan register The boundary scan register bit definitions are described in Table 4 10 Table 4 10 DSP56366 BSR Bit Definition Bit BSR Cell Bit BSR Cell Pin 4 Pin Name Pin Type Type SDO4_1 SDI1_1 Control 76 FST 1 Control 1 SDO4_1 SDI1_1 Input Output Data 77 FST 1 Input Output Data 2 IRQA Input Data 78 5005 1 5010 1 Control IRQB Input Data 79 5005 1 5010 1 Input Output Data 4 IRQC Input Data 80 RES Input Data 5 IRQD Input Data 81 Control 023 Input Output Data 82 HADO Input Output Data D22 Input Output Data 83 HAD1 Control D21 Input Output Data 84 HAD1 Input Output Data o D20 Input Output Data 85 HAD2 Control 10 019 Input Output Data 86 HAD2 Input Output Data 11
205. Ground Name Description GNDp PLL Ground GND is a ground dedicated for PLL use The connection should be provided with an extremely low impedance path to ground Vccp should be bypassed to GNDp by a 0 47 uF capacitor located as close as possible to the chip package There is one GNDp connection 4 Quiet Ground GNDg is an isolated ground for the internal processing logic This connection must be tied externally to all other chip ground connections The user must provide adequate external decoupling capacitors There four GNDq connections DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 2 3 Clock and PLL Table 2 3 Grounds continued Ground Name Description GND 4 Address Bus Ground GND is an isolated ground for sections of the address bus I O drivers This connection must be tied externally to all other chip ground connections The user must provide adequate external decoupling capacitors There are four GNDA connections GND 4 Data Bus Ground GND is an isolated ground for sections of the data bus drivers This connection must be tied externally to all other chip ground connections The user must provide adequate external decoupling capacitors There four GNDp connections GNDc 2 Bus Control Ground is an isolated ground for the bus control I O drivers This connection must be tied externally to all other chip ground conn
206. HDRQ 0 HDRQ 1 TREQ RREQ HOREQ signal HTRQ signal signal 0 0 No Interrupts Polling No Interrupts Polling No Interrupts Polling 0 1 RXDF Request Interrupt No Interrupts Polling RXDF Request Interrupt 1 0 TXDE Request Interrupt TXDE Request Interrupt No Interrupts Polling 1 1 RXDF and TXDE Requests Interrupts TXDE Request Interrupt RXDF Request Interrupt Table 6 10 TREQ RREQ Mode HM170 or HM0z0 TREQ RREQ HDRQ 0 HDRQ 1 HOREQ signal HTRQ signal signal 0 0 No DMA request No DMA request No DMA request 0 1 DSP to Host Request RX No DMA request DSP to Host Request RX 1 0 Host to DSP Request TX Host to DSP Request TX No DMA request 1 1 Reserved Reserved Reserved 6 6 1 3 ICR Double Host Request HDRQ Bit 2 The HDRQ bit determines the functions of the HOREQ HTRQ and HACK HRRQ signals as shown in Table 6 11 Table 6 11 HDRQ HOREQ HTRQ HACK HRRQ pin 0 HOREQ signal HACK signal 1 HTRQ signal signal 6 6 1 4 ICR Host Flag 0 HFO Bit 3 The bit is used as a general purpose flag for host to DSP communication may be set or cleared by the host processor and cannot be changed by the DSP core is reflected in the HSR on the DSP side of the HDIOS 6 6 1 5 ICR Host Flag 1 HF1 Bit 4 The bit is used as a general purpose flag for host to DSP communication may be set or cleared by the host processor and cannot be changed
207. HE KI PROIN HIMEN Ua ep eq B 1 B 1 1 Peripheral Addresses cs obe EPA eg px Ue I ERE B 1 B 1 2 ee 1 1 3 Interrupt Priorities L y gt udus 1 1 4 Host Interface Quick 1 1 5 Programming Sheets as ye 1 B2 termal Memory oor etu daa eC o E dau EE B 1 Mterr pt Vector uu s ioca c Mand Aa S d C VIV nta was B 8 DSP56366 24 Bit Digital Signal Processor Rev 4 Freescale Semiconductor TOC 11 B 4 Interrupt Source Priorities within an IPL B 10 B5 Quick Reference saris tem PR eeu ub Pata et Sn B 12 B Programming Sheets edo B 15 DSP56366 24 Bit Digital Signal Processor Rev 4 TOC 12 Freescale Semiconductor List of Figures Figure 1 1 Figure 2 1 Figure 3 1 Figure 3 2 Figure 3 3 Figure 3 4 Figure 3 5 Figure 3 6 Figure 3 7 Figure 3 8 Figure 3 9 Figure 3 10 Figure 3 11 Figure 3 12 Figure 3 13 Figure 3 14 Figure 3 15 Figure 3 16 Figure 4 1 Figure 4 2 Figure 6 1 Figure 6 2 Figure 6 3 Figure 6 4 Figure 6 5 Figure 6 6 Figure 6 7 Figure 6 8 Figure 6 9 Figure 6 10 Figure 6 11 Figure 6 12 Figure 6 13 Figure 6 14 Figure 6 15 Figure 6 16 Figure 7 1 Figure 7 2 Figure 7 3 DSP56366 Block Diagram
208. HTRQ HACK HRRQ Host acknowledge HACK or Host receive request HRRQ Mapping HDIOS registers are mapped into eight consecutive byte locations in the external host bus address space HDIOS acts as a memory or IO mapped peripheral for microprocessors microcontrollers etc Data Word 8 bit Transfer Modes Mixed 8 bit 16 bit and 24 bit data transfers DSP to Host Hostto DSP Host Command Handshaking Protocols Software polled Interrupt driven Interrupts are compatible with most processors including MC68000 8051 HC11 and Hitachi H8 DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 6 2 Freescale Semiconductor Cycle stealing DMA with initialization Dedicated Interrupts Separate interrupt lines for each interrupt source Special host commands force DSP core interrupts under host processor control which are useful for the following Real Time Production Diagnostics HDIO8 Host Port Signals Debugging Window for Program Development Host Control Protocols Interface Capabilities Glueless interface no external logic required to the following Freescale HC11 Hitachi H8 8051 family Thomson P6 family external DMA controllers Minimal glue logic pullups pulldowns required to interface to the following ISA bus Motorola 68K family Intel X86 family 6 3 HDIO8 Host
209. High Frequency Clock Polarity RHCKP Bit 20 The Receiver High Frequency Clock Polarity RHCKP bit controls on which bit clock edge data and frame sync are clocked out and latched in If RHCKP is cleared the data and the frame sync are clocked out on the rising edge of the receive bit clock and the frame sync is latched in on the falling edge of the receive bit clock If RHCKP is set the falling edge of the receive clock is used to clock the data and frame sync out and the rising edge of the receive clock 15 used to latch the frame sync in 8 3 3 8 RCCR Receiver Clock Source Direction RCKD Bit 21 The Receiver Clock Source Direction RCKD bit selects the source of the clock signal used to clock the receive shift register in the asynchronous mode SYN 0 and the IFO OFO flag direction in the synchronous mode SYN 1 In the asynchronous mode when RCKD is set the internal clock source becomes the bit clock for the receive shift registers and word length divider and is the output on the SCKR pin In the asynchronous mode when RCKD is cleared the clock source is external the internal clock generator is disconnected from the SCKR pin and an external clock source may drive this pin DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 8 24 Freescale Semiconductor ESAI Programming Model In the synchronous mode when RCKD is set the SCKR pin becomes the OFO output flag If RCKD is cleared then the SCKR pin becomes the IFO inpu
210. I08 data register selected during a DMA transfer is determined by a 2 bit address counter which is preloaded with the value in HDM 1 0 The address counter substitutes for the address bits of the HDIO8 during a DMA transfer The address counter can be initialized with the INIT bit feature After each DMA transfer on the host data bus the address counter is incremented to the next register When the address counter reaches the highest register RXL or TXL the address counter 15 not incremented but is loaded with the value in HDM 1 0 This allows 8 16 or 24 bit data to be transferred in a circular fashion and eliminates the need DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 6 9 HDIO8 DSP Side Programmer s Model for the DMA controller to supply the 2 HA1 and HAO signals For 16 or 24 bit data transfers the DSP CPU interrupt rate is reduced by a factor of 2 or 3 respectively from the host request rate 1 for every two or three host processor data transfers of one byte each there is only one 24 bit DSP CPU interrupt If HDM1 or HDMO are set the HM 1 0 bits in the ICR register reflect the value of HDM 1 0 The HDM 2 0 bits should be changed only while HEN is cleared in the HPCR 6 5 3 6 HCR Reserved Bits 8 15 These bits are reserved They read as zero and should be written with zero for future compatibility 6 5 4 Host Status Register HSR The HSR is a 16 bit read o
211. IO Audio Clock Input This is the DAX clock input When programmed Disconnected to use an external clock this input supplies the DAX clock The external clock frequency must be 256 384 or 512 times the audio sampling frequency 256 x Fs 384 x Fs or 512 x Fs respectively PDO Input Port D 0 When the DAX is configured as GPIO this signal is output or individually programmable as input output or internally disconnected disconnected The default state after reset is GPIO disconnected This input is 5 V tolerant ADO Output GPIO Digital Audio Data Output This signal is an audio and non audio Disconnected output in the form of AES EBU CP340 and IEC958 data in a biphase mark format PD1 Input Port D 1 When the DAX is configured as GPIO this signal is output or individually programmable as input output or internally disconnected disconnected The default state after reset is GPIO disconnected This input is 5 V tolerant DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 2 21 Timer 2 12 Timer Table 2 14 Timer Signal Signal State during ae Namie Type Reset Signal Description TIOO Input or Input Timer 0 Schmitt Trigger Input Output When timer 0 functions as an Output external event counter or in measurement mode TIOO is used as input When timer 0 functions in watchdog timer or pulse modulation mode TIOO is used as output Th
212. I_1 TIME SLOT REGISTER TSR_1 Y FFFF85 ESAI_1 TRANSMIT DATA REGISTER 5 TX5_1 Y FFFF84 ESAI 1 TRANSMIT DATA REGISTER 4 4 1 Y FFFF83 ESAI_1 TRANSMIT DATA REGISTER 3 TX3_1 Y FFFF82 ESAI_1 TRANSMIT DATA REGISTER 2 2 1 Y FFFF81 ESAI_1 TRANSMIT DATA REGISTER 1 TX1_1 Y FFFF80 ESAI_1 TRANSMIT DATA REGISTER 0 TXO 1 DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 3 18 Freescale Semiconductor 4 Core Configuration 4 1 Introduction This chapter contains DSP56300 core configuration information details specific to the DSP56366 These include the following Operating modes Bootstrap program Interrupt sources and priorities DMA request sources OMR PLL control register AA control registers BSR For more information on specific registers or modules in the DSP56300 core refer to the DSP56300 Family Manual DSP56300FM 4 2 Operating Mode Register OMR Refer to the DSP56300 Family Manual Freescale publication DSP56300FM for a description of the OMR bits DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 4 1 Operating Mode Register OMR Table 4 1 Operating Mode Register OMR SCS EOM COM 6 5 4 3 2 1 Em Patch Enable
213. K Frame XADE l l l XBLK 0608 Figure 10 3 DAX Relative Timing 10 5 7 4 Reserved Bits Bits 3 23 These XSTR bits are reserved They read as 0 and should be written with 0 to ensure compatibility with future device versions DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 10 8 Freescale Semiconductor DAX Internal Architecture 10 5 8 DAX Parity Generator PRTYG The PRTYG generates the parity bit for the subframe being transmitted The generated parity bit ensures that subframe bits four to thirty one will carry an even number of ones and zeroes 10 5 9 DAX Biphase Encoder The DAX biphase encoder encodes each audio and non audio bit into its biphase mark format and shifts this encoded data out to the ADO output pin synchronously to the biphase clock 10 5 10 DAX Preamble Generator The DAX preamble generator automatically generates one of three preambles in the 8 bit preamble shift register at the beginning of each subframe transmission and shifts it out The generated preambles always start with 0 Bit patterns of preambles generated in the preamble generator are shown in Table 10 4 The preamble bits are already in the biphase mark format Table 10 4 Preamble Bit Patterns Preamble Bit Pattern Channel X 00011101 A Y 00011011 B 2 00010111 A first in block There is no programmable control for the preamble selection The first sub
214. KEKE K KOK ek hec K K UK he ec ek KOK ek he e ek hehe ek KOK ec ke he he ke ke hehe ke ke hcec ke ke k k ke ke hcec e ke KOK K ke E EQUATES for DSP56366 interrupts E Last update April 24 2000 k k k k k Kk k k e KUK K e khe he e K KOK e ke he K e ke K he e ke he he e ke he he e ke he he e ke he he e ke ke K e ke he he e ke KOR e e he ke e e ke ke e e e page 132 55 0 0 0 opt mex intequ ident 1 0 1 GDEF I VEC leave user definition as is else Non Maskable interrupts I RESET EQU VEC 00 Hardware RESET I STACK EQU 502 Stack Error I ILL EQU I 504 Illegal Instruction I IINST EQU I VEC 04 Illegal Instruction I DBG EQU I 506 Debug Request I TRAP EQU I VEC 08 Trap I NMI EQU I VEC 0A Non Maskable Interrupt DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor Equates I IROA EQU I 510 IRQA I IROB EQU I 512 IROB I IRQC EQU I 514 IRQC I IROD EQU I 516 IRQD I DMAO EQU I VEC 18 DMA Channel 0 I DMAl EQU I 51 DMA Channel 1 I DMA2 EQU I VEC 1C DMA Channel 2 I DMA3 EQU I_VEC S1E DMA Channel 3 I DMA4 EQU I VEC 20 DMA Channel 4 I EQU VEC 22 DMA Channel 5 I DAXTUE EQU 528 DAX Underrun Error I DAXBLK EQU I 52 DAX Block Transferred I DAXTD EQU 52 DAX Audio Da
215. L HOST INTERFACE 0108 The HDIOS provides a fast 8 bit parallel data port that may be connected directly to the host bus The HDIOS supports a variety of standard buses and can be directly connected to a number of industry standard microcomputers microprocessors DSPs and DMA hardware Table 2 9 Host Interface Signal Name Type State during Signal Description disconnected Reset HO H7 Input Host Data When HDIO8 is programmed to interface a nonmultiplexed output host bus and the HI function is selected these signals are lines 0 7 of the bidirectional tri state data bus HADO HAD7 Input Host Address Data When 08 is programmed to interface a output multiplexed host bus and the HI function is selected these signals are lines 0 7 of the address data bidirectional multiplexed tri state bus PBO PB7 Input output or GPIO Port B 0 7 When the HDIO8 is configured as GPIO these signals are disconnected disconnected individually programmable as input output or internally disconnected The default state after reset for these signals is GPIO disconnected These inputs are 5 V tolerant HAO Input GPIO Host Address Input 0 When the HDIO8 is programmed to interface a disconnected nonmultiplexed host bus and the HI function is selected this signal is line 0 of the host address input bus HAS HAS Input Host Address Strobe When HDIOS
216. Manual Rev 4 Freescale Semiconductor 8 3 ESAI Data and Control Pins 8 2 4 Serial Transmit 3 Receive 2 Data Pin SDO3 SDI2 SDO3 SDI2 is used as the SDO3 signal for transmitting data from the TX3 serial transmit shift register when programmed as a transmitter pin or as the SDI2 signal for receiving serial data to the RX2 serial receive shift register when programmed as a receiver pin SDO3 SDI2 is an input when data is being received by the RX2 shift register SDO3 SDI2 is an output when data is being transmitted from the TX3 shift register In the on demand mode with an internally generated bit clock the SDO3 SDI2 pin becomes high impedance for a full clock period after the last data bit has been transmitted assuming another data word does not follow immediately If a data word follows immediately there is no high impedance interval SDO3 SDI2 may be programmed as a general purpose I O pin PC8 when the ESAI SDO3 and SDI2 functions are not being used 8 2 5 Serial Transmit 4 Receive 1 Data Pin SDO4 SDI1 SDO4 SDIH is used as SDO4 signal for transmitting data from the TX4 serial transmit shift register when programmed as transmitter pin or as the SDII signal for receiving serial data to the serial receive shift register when programmed as a receiver pin SDOA SDII is an input when data is being received by the RX1 shift register SDOA SDII is an output when data is being transmitted from the TX4 shift register In the on
217. N REGISTER PRRC X FFFFBD PORT C GPIO DATA REGISTER DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor D 3 Internal Memory Table D 1 Internal Memory Map continued Peripheral Address Register Name ESAI X FFFFBC ESAI RECEIVE SLOT MASK REGISTER B RSMB X FFFFBB ESAI RECEIVE SLOT MASK REGISTER RSMA X FFFFBA ESAI TRANSMIT SLOT MASK REGISTER B TSMB X FFFFB9 ESAI TRANSMIT SLOT MASK REGISTER A TSMA X FFFFB8 ESAI RECEIVE CLOCK CONTROL REGISTER RCCR X FFFFB7 ESAI RECEIVE CONTROL REGISTER RCR X FFFFB6 ESAI TRANSMIT CLOCK CONTROL REGISTER TCCR X FFFFB5 ESAI TRANSMIT CONTROL REGISTER TCR X FFFFB4 ESAI COMMON CONTROL REGISTER SAICR X FFFFB3 ESAI STATUS REGISTER SAISR X FFFFB2 Reserved X FFFFB1 Reserved X FFFFBO Reserved X FFFFAF Reserved X FFFFAE Reserved X FFFFAD Reserved X FFFFAC Reserved X FFFFAB ESAI RECEIVE DATA REGISTER 3 RX3 ESAI RECEIVE DATA REGISTER 2 RX2 X FFFFAQ ESAI RECEIVE DATA REGISTER 1 RX1 X FFFFA8 ESAI RECEIVE DATA REGISTER 0 X FFFFA7 Reserved X FFFFA6 ESAI TIME SLOT REGISTER TSR 5 ESAI TRANSMIT DATA REGISTER 5 TX5 X FFFFA4 ESAI TRANSMIT DATA REGISTER 4 TX4 X FFFFA3 ESAI TRANSMIT DATA REGISTER TX3 X FFFFA2 ESAI TRANSMIT DATA REGISTER 2
218. O signal The GPIO functionality of port E is controlled by three registers port E control register PCRE port E direction register PRRE and port E data register PDRE These registers are described in Section 9 Enhanced Serial Audio Interface 1 ESAI 1 5 2 5 Timer Event Counter Signals The timer event counter signal TIO when not used as a timer signal can be configured as a GPIO signal The signal is controlled by the appropriate timer control status register TCSR The register is described in Section 11 Timer Event Counter DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 5 2 Freescale Semiconductor 6 Host Interface HDIO8 6 1 Introduction The host interface HDIO8 is a byte wide full duplex double buffered parallel port that can be connected directly to the data bus of a host processor The HDIOS supports a variety of buses and provides glueless connection with a number of industry standard microcomputers microprocessors DSPs and DMA hardware The host bus can operate asynchronously to DSP core clock therefore the HDIOS registers are divided into 2 banks The host register bank is accessible to the external host and the DSP register bank is accessible to the DSP core The HDIOS supports three classes of interfaces Host processor Microcontroller MCU connection interface controller interface General purpose I O GPIO port 6 2 HDIOS8 Features 6 2 1 Interface DSP
219. OM and can be expanded off chip under software control There is an instruction cache made using program RAM The patch mode which uses instruction cache space is used to patch program ROM The memory switch mode is used to increase the size of program RAM as needed switch from X data RAM and or Y data RAM There are on chip ROMs for program memory 40K x 24 bit bootstrap memory 192 words x 24 bit X ROM 32K x 24 bit and Y ROM 8K x 24 bit More information on the internal memory is provided in Section 3 Memory Configuration 1 4 9 Off Chip Memory Expansion Memory can be expanded off chip as follows e Data memory can be expanded to two 16 M x 24 bit word memory spaces in 24 bit address mode 64K in 16 bit address mode Program memory can be expanded to one 16 M x 24 bit word memory space in 24 bit address mode 64K in 16 bit address mode Other features of external memory expansion include the following External memory expansion port Chip select logic glueless interface to static random access memory SRAM On chip dynamic RAM DRAM controller for glueless interface to DRAM Eighteen external address lines 1 5 Peripheral Overview The DSP56366 is designed to perform a wide variety of fixed point digital signal processing functions In addition to the core features previously discussed the DSP56366 provides the following peripherals 8 bit parallel host interface HDIO8 with DMA support to external hos
220. P revA bsdl MOTOROLA SSDT BSDL File Generated Mon Jan 18 10 13 53 1999 Revision History entity DSP56366 is JTAG SOFTWARE generic PHYSICAL PIN MAP string TOFP144 port TDO out bit TDI in bit TMS in bit TCK in bit SCK inout bit SDOO inout bit SDO1 inout bit SDOI23 inout bit PINIT in bit SDOI32 inout bit SVCC linkage bit vector 0 to 1 SGND linkage bit vector 0 to 1 SDOIA41 inout bit SDOI50 inout bit FST inout bit FSR inout bit SCKT inout bit SCKR inout bit HSCKT inout bit HSCKR inout bit QVCC linkage bit vector 0 to 3 QGND linkage bit vector 0 to 3 QVCCH linkage bit vector 0 to 2 HP inout bit vector 0 to 15 ADO inout bit ACI inout bit TIO inout bit HVCC linkage bit HGND linkage bit SS in bit HREQ inout bit RESET in bit PVCC linkage bit PCAP linkage bit PGND linkage bit AA out bit vector 0 to 2 DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor F JTAG BSDL CAS out bit EXTAL in bit CVCC linkage bit vector 0 to 1 CGND linkage bit vector 0 to 1 TA in bit BR buffer bit BB inout bit WR out bit RD out bit BG in bit A out bit vector 0 to 17 AVCC linkage bit vector 0 to 2 AGND linkage bit vector 0 to 3 D inout bit vector 0 to 23 DVCC linkage bit vector 0 to 3 DGND linkage bit vector 0 to 3 MODD in bit MODC in bit MODB in bit MODA in bit MOSI ino
221. Port Signals The host port signals are described in Section 2 Signal Connection Descriptions If the Host Interface functionality is not required the 16 pins may be defined as general purpose I O pins PBO PB15 When the HDIOS is in use only five host port signals HA8 HA9 HCS HOREQ and HACK may be individually programmed as GPIO pins if they are not needed for their HDIO08 function Summary of the HDIOS signals Table 6 1 HDIO8 Signal Summary HDI08 Port Pin Multiplexed address data bus Mode Non Multiplexed bus Mode GPIO Mode HADO HAD7 HADO HAD7 HO H7 PBO PB7 HAS HAO HAS HAS HAO PB8 HA8 HA1 HA8 HA1 PB9 HA9 HA2 HA9 HA2 PB10 HCS HA10 HA10 HCS HCS PB13 DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor HDI08 Block Diagram Table 6 2 Strobe Signals Support signals HDIO8 Port Pin Single strobe bus Dual strobe bus GPIO Mode HRW HRD HRW HRD HRD PB11 HDS HWR HDS HDS HWR HWR PB12 Table 6 3 Host request support signals HDI08 Port Pin Vector required No vector required GPIO Mode HOREQ HTRQ HOREQ HOREQ HTRQ HTRQ PB14 HACK HRRQ HACK HACK HRRQ HRRQ PB15 6 4 HDI08 Block Diagram Figure 6 1 shows the HDIOS registers The top row of registers HCR HSR HDDR HDR HBAR HPCR HOTX HORX can be accessed the DSP core The bottom row of registers ISR ICR CVR IVR RXH RXM RXL and TXH TXM TXL can be accessed by the host
222. QU 9 ESAI M RDF EQU 8 ESAI M ROE EQU 7 ESAI M RFS EQU 6 ESAI M IF2 EQU 2 ESAI EQU l ESAI M IFO EQU 0 ESAI 2 EQUATES for HDIO8 Register Addresses M HOTX EQU SFFFFC7 HOST Transmit Register HOTX DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor B 29 Equates M HORX M HPCR M HSR M HCR M HRIE M HOTIE M HCIE M HF2 M M HODMO HODM1 M HODM2 M HRDF M HOTDE M HCP M HFO M HF1 M DMA M HGEN EQU EQU EQU EQU EQU HCR bits EQU EQU EQU EQU EQU EQU EQU EQU HSR bits EQU EQU EQU EQU EQU EQU HPCR bits EQU M HABEN EQU M HA9EN EQU SFFFFC6 SFFFFC5 SFFFFC4 SFFFFC3 SFFFFC2 0 1 2 3 4 5 6 7 0 1 2 3 4 7 0 1 2 HOST Receive Register HORX HOST Base Address Register HBAR HOST Port Control Register HPCR HOST Status Register HSR HOST Control Register HCR HOST Receive interrupts Enable HOST Transmit Interrupt Enable HOST Command Interrupt Enable HOST Flag 2 HOST Flag 3 HOST DMA Mode Control Bit 0 HOST DMA Mode Control Bit 1 HOST DMA Mode Control Bit 2 HOST Receive Data Full HOST Receive Data Emptiy HOST Command Pending HOST Flag 0 HOST Flag 1 HOST DMA Status HOST Po
223. R 1 SCKR 1 is a bidirectional pin that provides the receivers serial bit clock for the ESAI 1 interface SCKR 1 may be programmed as a general purpose I O pin PEO when the ESAI 1 SCKR 1 function is not being used 9 2 8 Transmitter Serial Clock SCKT 1 SCKT 1 is a bidirectional pin that provides the transmitters serial bit clock for the ESAI 1 interface SCKT 1 may be programmed as a general purpose I O pin PE3 when the ESAI 1 SCKT 1 function is not being used 9 2 9 Frame Sync for Receiver FSR 1 The FSR 1 pinis a bidirectional pin that provides the receivers frame sync signal for the ESAI 1 interface FSR 1 may be programmed as a general purpose I O pin PE1 when the ESAI 1 FSR 1 function is not being used 9 2 10 Frame Sync for Transmitter FST 1 The FST 1 pin is a bidirectional pin that provides the transmitters frame sync signal for the ESAI 1 interface FST 1 may be programmed as a general purpose I O pin 4 when the ESAI 1 FST 1 function is not being used 9 3 ESAI 1 Programming Model The ESAI 1 has the following registers One multiplex control register Five control registers One status register Six transmit data registers Four receive data registers Two transmit slot mask registers Tworeceive slot mask registers One special purpose time slot register DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 9 4 Freescale Semiconductor ESAI 1 Programming Model The ESAI 1 als
224. Register HDDR X FFFFC8 Host Data Register X FFFFC9 HSRC R Operation aceto uar d thes P ee ae he ge Interface Control Register ICR Command Vector Register CVR Interface Status Register ISR Interrupt Vector Register IVR HDI08 Host Request Structure Serial Host Interface Block Diagram SHI Clock Generator napa d ANC Te d UO e wed arcta SHI Programming Model Host Side DSP56366 24 Bit Digital Signal Processor Rev 4 Freescale Semiconductor LOF 1 Figure 7 4 Figure 7 5 Figure 7 6 Figure 7 7 Figure 7 8 Figure 7 9 Figure 7 10 Figure 7 11 Figure 8 1 Figure 8 2 Figure 8 3 Figure 8 4 Figure 8 5 Figure 8 6 Figure 8 7 Figure 8 8 Figure 8 9 Figure 8 10 Figure 8 11 Figure 8 12 Figure 8 13 Figure 8 14 Figure 8 15 Figure 8 16 Figure 8 17 Figure 8 18 Figure 8 19 Figure 8 20 Figure 8 21 Figure 9 1 Figure 9 2 Figure 9 3 Figure 9 4 Figure 9 5 Figure 9 6 Figure 9 7 Figure 9 8 Figure 9 9 Figure 9 10 SHI Programming Model DSP Side 7 4 SHI Register IOSR i wei hap I rege ea 7 6 SPI Data To Clock Timing 7 8 PC Bit Transfer y peus nlla ive e yuqa 7 17 PC Start and Sasso etd unas Aenea quae A sca 7 17
225. Reserved VBA 54 0 2 TIMERO Compare VBA 56 0 2 TIMERO Overflow VBA 58 0 2 TIMER1 Compare VBA 5A 0 2 TIMER1 Overflow VBA 5C 0 2 TIMER2 Compare VBA 5E 0 2 TIMER2 Overflow VBA 60 0 2 Host Receive Data Full VBA 62 0 2 Host Transmit Data Empty VBA 64 0 2 Host Command Default VBA 66 0 2 Reserved VBA 68 0 2 Reserved VBA 6A 0 2 Reserved VBA 6C 0 2 Reserved VBA 6E 0 2 Reserved VBA 70 0 2 ESAI_1 Receive Data VBA 72 0 2 ESAI_1 Receive Even Data VBA 74 0 2 ESAI_1 Receive Data With Exception Status VBA 76 0 2 ESAI_1 Receive Last Slot VBA 78 0 2 ESAI_1 Transmit Data VBA 7A 0 2 ESAI_1 Transmit Even Data VBA 7C 0 2 ESAI_1 Transmit Data with Exception Status VBA 7E 0 2 ESAI_1 Transmit Last Slot VBA 80 0 2 Reserved VBA FE 0 2 Reserved DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor Interrupt Source Priorities within an IPL D 4 Interrupt Source Priorities within an IPL Table D 3 Interrupt Sources Priorities Within an IPL Priority Interrupt Source Level 3 Nonmaskable Highest Hardware RESET Stack Error Illegal Instruction Debug Request Interrupt Trap Lowest Non Maskable Interrupt Levels 0 1 2 Maskable Highest IRQA External Interrupt IRQB External Interrupt IRQC External Interrupt IRQD External Interrupt DMA Channel 0 Interrupt DMA Channel 1 Interrupt DMA Channe
226. SP 0 HDDS 1 HMUX 1 HDSP 0 future compatability When the HPCR register is modified HEN should be cleared Host acknowledge is disabled Host requests are enabled Host chip select input enabled address 9 enable bit has no meaning in non multiplexed bus address 8 enable bit has no meaning non multiplexed bus Host GPIO pins are disabled conditions acknowledge request the following Negative host Negative host Negatice chip select input Single strobe bus R W and DS Non multiplexed bus address strobe polarity has no meaning in non multiplexed bus Negative data stobes polarity Host request is active when enabled This bit should be set to 0 for future compatability When the HPCR register is modified HEN should be cleared Host acknowledge is disabled Host requests are enabled Host chip select input enabled address 9 enable bit has no meaning in non multiplexed bus address 8 enable bit has no meaning in non multiplexed bus Host GPIO pins are disabled conditions acknowledge request select input RD and WR the following Negative host Negatice host Negatice chip Dual strobes bus Multiplexed bus Positive address strobe polarity Negative data stobes polarity DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor ee DSP56366 Bootstrap Program II HROD Host request is active when enabled Spare This bit should be set
227. SR Transmit Frame Sync Flag TFS 13 8 36 SAISR Transmit Underrun Error Flag TUE 14 8 37 SAISR Transmit Data Register Empty TDE Bit 15 8 37 SAISR Transmit Even Data Register Empty TEDE Bit 16 8 37 SAISR Transmit Odd Data Register Empty Bit 17 8 37 ESAI Receive Shift Registers 8 40 ESAI Receive Data Registers RX3 RX2 RX1 RX0 8 40 ESAT Transmit Shift Registers 8 40 ESAI Transmit Data Registers TX5 TX4 TX3 2 0 8 40 DSP56366 24 Bit Digital Signal Processor Rev 4 Freescale Semiconductor TOC 7 8 3 11 ESAT Time Slot Register TSR 8 40 8 3 12 Transmit Slot Mask Registers TSMA TSMB 8 40 8 3 13 Receive Slot Mask Registers RSMA 8 42 84 Operauns Modes sse vd ra 8 43 8 4 1 ESALAfter Reset 226525456 ri Acer et 8 43 8 42 ESAI Initialization 8 43 8 4 3 ESALIntemupt Requests ae REOR ats ar an b usan 8 44 8 4 4 Operating Modes Normal Network and On Demand 8 45 8 4 4 1 Normal Network On Demand Mode Selection
228. TSR to disable transmission ofthe next time slot If TIE is set an ESAI transmit data interrupt request is issued when TODE is set Hardware software ESAI individual and STOP reset clear TODE 23 16 15870 ESAI RECEIVE DATA REGISTER RECEIVE HIGH BYTERECRIVE MIDDLE BYTERECEIVE LOW BYTE READ ONLY 7 0 7070 23 16 15870 SERIAL I RECEIVE RECEIVE HIGH BYTERECRIVE MIDDLE BYTERECEIVE LOW BYTE SHIFT gq lt lt REGISTER 7 0 7070 24 BIT RSWSO MSB LSB 8 BIT DATA 0 0 lt 0 0 LEAST SIGNIFICANT ZERO FILL LSB 12 BIT DATA MSB LSB 16 BIT DATA MSB LSB 20 BIT DATA LSB 24 BIT DATA NOTES 1 Data is received MSB first if RSHFD 0 2 24 bit fractional format ALC 0 3 32 bit mode is not shown a Receive Registers 23 16 15870 ESAI TRANSMIT DATA TRANSMIT HIGH BYTETRANSMIT MIDDLE BYTETRANSMIT LOW BYTE REGISTER WRITE ONLY 7 0 7070 23 16 15870 TRANSMIT HIGH BYTETRANSMIT MIDDLE BYTETRANSMIT LOW BYTE ESAI TRANSMIT SDO SHIFT REGISTER 7 0 7070 LEAST SIGNIFICANT BIT FILL MSB LSB 8 BIT DATA 6 L LSB 12 BIT DATA MSB LSB 16 BIT DATA MSB 20 BIT DATA ESS LS 24 BIT DATA NOTES b Transmit Registers 1 Data is sent MSB first if TSHFD 0 3 32 bit mode is not shown 2 24 bit fractional format ALC 0 4 Data word is left aligned TWA 0 PADC 0 Figure 8 13 ESAI Data Path
229. TUE is set when both the shift register and the HTX register are empty and the external master begins reading the next word When operating in the mode HTUE is set in the falling edge ofthe ACK bit In this case the SHI retransmits the previously transmitted word When operating in the SPI mode HTUE is set at the first clock edge if 1 it is set at the assertion of SS if CPHA 0 DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 7 14 Freescale Semiconductor Serial Host Interface Programming Model If a transmit interrupt occurs with HTUE set the transmit underrun interrupt vector is generated If a transmit interrupt occurs with HTUE cleared the regular transmit data interrupt vector is generated HTUE is cleared by reading the HCSR and then writing to the HTX register HTUE is cleared by hardware reset software reset SHI individual reset and during the stop state 7 4 6 13 HCSR Host Transmit Data Empty HTDE Bit 15 The read only status bit HTDE indicates whether the HTX register is empty and can be written by the DSP HTDE is set when the data word is transferred from HTX to the shift register except in SPI master mode when CPHA 0 see HCKR When in the SPI master mode with CPHA 0 HTDE is set after the end of the data word transmission HTDE is cleared when the DSP writes the HTX either with write instructions or DMA transfers HTDE is set by hardware reset software reset SHI individual
230. The Status Register SAISR is a read only status register used by the DSP to read the status and serial input flags of the ESAI See Figure 8 12 The status bits are described in the following paragraphs DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 8 34 Freescale Semiconductor ESAI Programming Model 11 10 9 8 7 6 5 4 3 2 1 0 X FFFFB3 RODF REDF RDF ROE RFS IF2 IF1 IFO 23 22 21 20 19 18 17 16 15 14 13 12 TODE TEDE TDE TUE TFS Reserved bit read as zero should be written with zero for future compatibility Figure 8 12 SAISR Register 8 3 6 1 SAISR Serial Input Flag 0 IFO Bit 0 The IFO bit is enabled only when the SCKR pin is defined as ESAI in the Port Control Register SYN 1 and RCKD 0 indicating that SCKR is an input flag and the synchronous mode is selected Data present on the SCKR pin is latched during reception of the first received data bit after frame sync is detected The IFO bit is updated with this data when the receiver shift registers are transferred into the receiver data registers IFO reads as a zero when it is not enabled Hardware software ESAI individual and STOP reset clear IFO 8 3 6 2 SAISR Serial Input Flag 1 IF1 Bit 1 The IF1 bit is enabled only when the FSR pin is defined as ESAI in the Port Control Register SYN 1 RFSD 0 and TEBE 0 indicating that FSR is an input flag and
231. V tolerant HDS HDS Input HWR HWR Input PB12 Input output or disconnected GPIO disconnected Host Data Strobe When 0108 is programmed to interface single data strobe host bus and the HI function is selected this signal is the host data strobe HDS Schmitt trigger input The polarity of the data strobe is programmable but is configured as active low HDS following reset Host Write Data When HDIO8 is programmed to interface double data strobe host bus and the HI function is selected this signal is the host write data strobe HWR Schmitt trigger input The polarity of the data strobe is programmable but is configured as active low HWR following reset Port B 12 When the HDIO8 is configured as GPIO this signal is individually programmed as input output or internally disconnected The default state after reset for this signal is GPIO disconnected This input is 5 V tolerant DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 2 10 Freescale Semiconductor PARALLEL HOST INTERFACE HDIO8 Table 2 9 Host Interface continued Signal Name HCS Type Input HA10 Input PB13 Input output or disconnected State during Reset GPIO disconnected Signal Description Host Chip Select When HDIO8 is programmed to interface nonmultiplexed host bus and the HI function is selected this signal is the
232. VE CLOCK CONTROL REGISTER RCCR_1 Y FFFF97 ESAI 1 RECEIVE CONTROL REGISTER 1 Y FFFF96 ESAI 1 TRANSMIT CLOCK CONTROL REGISTER TCCR 1 Y FFFF95 ESAI 1 TRANSMIT CONTROL REGISTER TCR 1 Y FFFF94 ESAI 1 COMMON CONTROL REGISTER SAICR 1 Y FFFF93 ESAI 1 STATUS REGISTER SAISR 1 Y FFFF92 Reserved Y FFFF91 Reserved Y FFFF90 Reserved Y FFFF8F Reserved Y FFFF8E Reserved Y FFFF8D Reserved Y FFFF8C Reserved Y FFFF8B ESAI 1 RECEIVE DATA REGISTER 3 RX3 1 Y FFFF8A ESAI 1 RECEIVE DATA REGISTER 2 2 1 Y FFFF89 ESAI 1 RECEIVE DATA REGISTER 1 1 1 Y FFFF88 ESAI 1 RECEIVE DATA REGISTER 0 RXO 1 Y FFFF87 Reserved Y FFFF86 ESAI 1 TIME SLOT REGISTER 5 1 Y FFFF85 ESAI 1 TRANSMIT DATA REGISTER 5 TX5 1 Y FFFF84 ESAI 1 TRANSMIT DATA REGISTER 4 4 1 Y FFFF83 ESAI_1 TRANSMIT DATA REGISTER 3 TX3_1 Y FFFF82 ESAI_1 TRANSMIT DATA REGISTER 2 TX2_1 Y FFFF81 ESAI_1 TRANSMIT DATA REGISTER 1 TX1_1 Y FFFF80 ESAI_1 TRANSMIT DATA REGISTER 0 TXO 1 DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor Interrupt Vector Addresses D 3 Interrupt Vector Addresses Table D 2 DSP56366 Interrupt Vectors Sahing Aadress interrupt VBA 00 3 Hardware RESET VBA 02 3 Stack Error VBA 04 3 Illegal Instruction VBA 06 3 Debug Request Interrupt VBA 08
233. WR 67 amp RD 68 amp BG 71 amp A 72 73 76 77 78 79 82 83 84 85 88 89 92 93 94 97 98 99 amp AVCC 74 80 86 amp AGND 75 81 87 96 amp D 100 101 102 105 106 107 108 109 110 113 114 115 116 117 118 121 amp 122 123 124 125 128 131 132 133 amp 103 111 119 129 amp DGND 104 112 120 130 amp MODD 134 amp MODC 135 amp MODB 136 amp MODA 137 amp SDO41 1 138 TDO 139 amp TDI 140 amp TCK 141 amp TMS 142 amp MOSI 143 amp SDA 144 attribute TAP SCAN IN of TDI signal is true attribute SCAN OUT of TDO signal is true attribute TAP SCAN MODE of TMS signal is true attribute SCAN CLOCK of signal is 20 0e6 BOTH attribute INSTRUCTION LENGTH of DSP56366 entity is 4 DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor JTAG BSDL attribute INSTRUCTION OPCODE of DSP56366 entity is EXTEST 0000 amp SAMPLE 0001 amp IDCODE 0010 amp CLAMP 0101 amp HIGHZ 0100 amp ENABLE ONCE 0110 amp DEBUG REQUEST 0111 amp BYPASS 1111 attribute INSTRUCTION CAPTURE of DSP56366 entity is 0001 attribute IDCODE REGISTER of DSP56366 entity is 0000 amp version 000111 amp manufacturer s use 0001001111 amp sequ
234. When REI is cleared receiver 1 is disabled by inhibiting data transfer into RX1 If this bit is cleared while receiving a data word the remainder of the word is shifted in and transferred to the RX1 data register If REI is set while some of the other receivers are already in operation the first data word received in RX1 will be invalid and must be discarded 8 3 4 3 RCR ESAI Receiver 2 Enable RE2 Bit 2 When RE2 is set and is cleared the ESAI receiver 2 is enabled and samples data at the SDO3 SDI2 pin TX3 and RX2 should not be enabled at the same time RE2 1 and TE3 1 When RE2 is cleared receiver 2 is disabled by inhibiting data transfer into R X2 If this bit is cleared while receiving a data word the remainder of the word is shifted in and transferred to the RX2 data register If RE2 is set while some ofthe other receivers are already in operation the first data word received in RX2 will be invalid and must be discarded 8 3 4 4 RCR ESAI Receiver 3 Enable RE3 Bit 3 When RE3 is set and TE2 is cleared the ESAI receiver 3 is enabled and samples data at the SDO2 SDI3 pin TX2 and RX3 should not be enabled at the same time RE3 1 and TE2 1 When RE3 is cleared receiver 3 1s disabled by inhibiting data transfer into RX3 Ifthis bit is cleared while receiving a data word the remainder of the word is shifted in and transferred to the RX3 data register If RE3 is set while some ofthe other receivers are already in operation
235. a in the AES EBU CP 340 and IEC958 formats For more information on the DAX refer to Section 10 Digital Audio Transmitter DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 1 10 Freescale Semiconductor 2 Signal Connection Descriptions 2 1 Signal Groupings The input and output signals of the DSP56364 are organized into functional groups which are listed in Table 2 1 and illustrated in Figure 2 1 The DSP56364 is operated from a 3 3 V supply however some of the inputs can tolerate 5 V A special notice for this feature is added to the signal descriptions of those inputs Table 2 1 DSP56364 Functional Signal Groupings Functional Group Power Vcc 20 Table 2 2 Ground GND 18 Table 2 3 Clock and PLL 3 Table 2 4 Address bus 18 Table 2 5 Port Data bus 24 Table 2 6 Bus control 10 Table 2 7 Interrupt and mode control 5 Table 2 8 HDIO8 Port B 16 Table 2 9 SHI 5 Table 2 10 ESAI Port C 12 Table 2 11 ESAI 1 Port E 6 Table 2 12 Digital audio transmitter DAX Port 09 2 Table 2 13 Timer 1 Table 2 14 JTAG OnCE Port 4 Table 2 15 a UO N DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Port A is the external memory interface port including the external address bus data bus and control signals Port B signals the GPIO port signals which are multiplexed with the HDI08 signals Port C signals are t
236. a registers TXH TXM TXL on the host side when both the transmit data register empty TXDE host side and host receive data full HRDF DSP side bits are cleared This transfer operation sets both the TXDE and HRDF flags The HORX register contains valid data when the HRDF bit is set Reading HORX clears HRDF The DSP may program the HRIE bit to cause a host receive data interrupt when HRDF is set Also a DMA channel may be programmed to read the HORX when HRDF is set 6 5 2 Host Transmit Data Register HOTX The 24 bit write only HOTX register is used for DSP to host data transfers Writing to the HOTX register clears the host transfer data empty flag HTDE DSP side The contents of the HOTX register are transferred as 24 bit data to the receive byte registers RXH RXM RXL when both the HTDE flag DSP side and receive data full RXDF flag host side are cleared This transfer operation sets the RXDF and HTDE flags The DSP may setthe HTIE bit to cause a host transmit data interrupt when HTDE is set Also a DMA Channel may be programmed to write to HOTX when HTDE is set To prevent the previous data from being overwritten data should not be written to the HOTX until the HTDE flag is set DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 6 6 Freescale Semiconductor HDIO8 DSP Side Programmer s Model NOTE When writing data to a peripheral device there is a two cycle pipeline delay until any status bits affected by the ope
237. abled by a DSP core DMA Channel If HTDE is set when HTIE is set a host transmit data interrupt request is generated HTDE can also be set by the host processor using the initialize function 6 5 4 3 HSR Host Command Pending HCP Bit 2 The HCP bit indicates that the host has set the HC bit and that a host command interrupt is pending The HCP bit reflects the status of the HC bit in the command vector register CVR HC and HCP are cleared DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 6 10 Freescale Semiconductor HDIO8 DSP Side Programmer s Model by the HDI08 hardware when the interrupt request is serviced by the DSP core The host can clear HC which also clears HCP 6 5 4 4 HSR Host Flags 0 1 HFO HF1 Bits 3 4 and 1 bits are used as a general purpose flags for host to DSP communication and may be set or cleared by the host and reflect the status of host flags and in the ICR register on the host side These two flags are not designated for any specific purpose but are general purpose flags They can be used individually or as encoded pairs in a simple host to DSP communication protocol implemented in both the DSP and the host Processor software 6 5 4 5 HSR Reserved Bits 5 6 8 15 These bits are reserved They read as zero and should be written with zero for future compatibility 6 5 4 6 HSR DMA Status DMA Bit 7 The DMA status bit is set when the DMA
238. agram 11 1 11 2 2 Individual Timer Block Diagram 11 2 11 3 Timer Event Counter Programming 1 11 3 11 3 1 Picstaler Counter et edo etes lon 11 5 11 3 2 Timer Prescaler Load Register IBER 11 5 11 3 2 1 TPLR Prescaler Preload Value PL 20 0 Bits 20 0 11 5 11 3222 TPLR Prescalet Source PS 1 0 Bits 22 21 11 5 11 3 2 3 FEPER Reserved Bit 29 22 uma u pusan 11 6 11 3 3 Timer Prescaler Count Register TPCR 11 6 11 3 3 1 Prescaler Counter Value PC 20 0 Bits 20 0 11 6 11 3 3 2 TPCR Reserved Bits 23 21 11 6 11 3 4 Timer Control Status Register TCSR 11 6 11 3 4 1 TCSR Timer Enable TE BIO 11 6 11 3 4 2 Timer Overflow Interrupt Enable TOIE Bit 11 7 11 3 4 3 Timer Compare Interrupt Enable TCIE Bit2 11 7 11 3 4 4 TCSR Timer Control TC 3 0 Bits 4 7 11 7 11 3 4 5 Inverter INV 11 9 11 3 4 6 TCSR Timer Reload Mode 9
239. al Rev 4 Freescale Semiconductor B 11 Equates EQU EQU EQU EQU EQU EQU EQU 18 PLL Enable Bit 19 PLL Clock Output Disable Bit F00000 PreDivider Factor Bits Mask PDO PD3 20 PreDivider Factor bit 0 21 PreDivider Factor bit 1 22 PreDivider Factor bit 2 23 PreDivider Factor bit 3 EQUATES for BIU M M M M M M M BCR DCR AARO 1 AAR2 AAR3 IDR M BAOW M BAOWO M BAOW1 M BAOW2 M BAOW3 M BAOWA Register Addresses Of BIU EQU EQU EQU EQU EQU EQU EQU SFFFFFB Bus Control Register SFFFFFA DRAM Control Register SFFFFF9 Address Attribute Register 0 SFFFFF8 Address Attribute Register 1 SFFFFF7 Address Attribute Register 2 SFFFFF6 Address Attribute Register 3 SFFFFF5 ID Register Bus Control Register EQU EQU EQU EQU EQU EQU 1 Area 0 Wait Control Mask BAOWO BAOWA 0 Area 0 Wait Control Bit 0 1 Area 0 Wait Control Bit 1 2 Area 0 Wait Control Bit 2 3 Area 0 Wait Control Bit 3 4 Area 0 Wait Control Bit 4 DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor Equates M EQU 3E0 Area 1 Wait Control Mask 1 0 14 BA1WO EQU 5 Area 1 Wait Control Bit 0 BAIW1 EQU 6 Area 1 Wait Control Bit 1 M BA1W2 EQU 7 Area 1 Wait Control Bit 2 BA1W3 EQU 8 Area 1 Wai
240. ale Semiconductor Table 4 6 DSP56366 Interrupt Vectors continued Interrupt Priority Registers NC E Interrupt Source VBA 44 0 2 SHI Receive FIFO Not Empty VBA 46 0 2 Reserved VBA 48 0 2 SHI Receive FIFO Full VBA 4A 0 2 SHI Receive Overrun Error VBA 4C 0 2 SHI Bus Error VBA 4E 0 2 Reserved VBA 50 0 2 Reserved VBA 52 0 2 Reserved VBA 54 0 2 TIMERO Compare VBA 56 0 2 TIMERO Overflow VBA 58 0 2 TIMER1 Compare VBA 5A 0 2 TIMER1 Overflow VBA 5C 0 2 TIMER2 Compare VBA 5E 0 2 TIMER2 Overflow VBA 60 0 2 Host Receive Data Full VBA 62 0 2 Host Transmit Data Empty VBA 64 0 2 Host Command Default VBA 66 0 2 Reserved VBA 68 0 2 Reserved VBA 6A 0 2 Reserved VBA 6C 0 2 Reserved VBA 6E 0 2 Reserved VBA 70 0 2 ESAI_1 Receive Data VBA 72 0 2 ESAI_1 Receive Even Data VBA 74 0 2 ESAI_1 Receive Data With Exception Status VBA 76 0 2 ESAI_1 Receive Last Slot VBA 78 0 2 ESAI_1 Transmit Data VBA 7A 0 2 ESAI_1 Transmit Even Data VBA 7C 0 2 ESAI_1 Transmit Data with Exception Status VBA 7E 0 2 ESAI_1 Transmit Last Slot VBA 80 0 2 Reserved VBA FE 0 2 Reserved DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor DMA Request Sources 4 5 Request Sources The DMA Request Source bits DRSO DRSA bits in the DMA Control Status registers encode the source of DMA req
241. alue the timer is to count is loaded into the TLR When the first timer clock signal is received the counter is loaded with the TLR value The timer DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 11 17 Timer Modes of Operation clock signal can be taken from either the DSP56366 clock divided by two CLK 2 or from the prescaler clock output Each subsequent clock signal increments the counter At the first appropriate transition of the external clock detected on the TIOO signal the TCF bit in the TCSR is set and if the TCIE bit is set a compare interrupt is generated The counter halts The contents of the counter are loaded into the TCR The value of the TCR represents the delay between the setting of the TE bit and the detection of the first clock edge signal on the TIOO signal If the INV bit is set a high to low transition signals the end of the timing period If INV is cleared a low to high transition signals the end of the timing period If the counter overflows the TOF bit 15 set and if 15 set an overflow interrupt is generated The counter contents can be read at any time by reading the TCR 11 4 3 Pulse Width Modulation PWM Mode 7 Bit Settings Mode Characteristics TC2 TC1 TCO Mode Name Kind TIOO Clock 0 1 1 1 7 Pulse Width Modulation PWM Output Internal In this mode the timer generates periodic pulses of a preset widt
242. amming techniques and DMA transfers Memory mapping allows DSP communication with the SHI registers to be accomplished using standard instructions and addressing modes In addition the instruction allows interface to memory and memory to interface data transfers without going through an intermediate register The DMA controller may be used to service the receive or transmit data path The single master configuration allows the DSP to directly connect to dumb peripheral devices For that purpose a programmable baud rate generator is included to generate the clock signal for serial transfers The host side invokes the SHI for communication and data transfer with the DSP through a shift register that may be accessed serially using either the or the SPI bus protocols Figure 7 1 shows the SHI block diagram Host Accessible DSP Accessible DSP Global Clock Data Generator Bus E DMA Data HCSR Bus MISO SDA Controller Logic MOSI HAO Shift Register SS 52 IOSR SSIHAZ HREQ Slave Address Recognition Unit SAN 24 BIT AA0416 Figure 7 1 Serial Host Interface Block Diagram 7 3 SHI Clock Generator The SHI clock generator generates the SHI serial clock if the interface operates in the master mode The clock generator is disabled if the interface operates in the slave mode except in mode when the bit is set in the HCKR register When the SHI operates
243. an instruction that requires more than one external bus cycle for execution For proper BG operation the asynchronous bus arbitration enable bit ABE in the OMR register must be set Input Output Input Bus Busy BB is a bidirectional active low input output BB indicates that the bus is active Only after BB is deasserted can the pending bus master become the bus master and then assert the signal again The bus master may keep BB asserted after ceasing bus activity regardless of whether BR is asserted or deasserted This is called bus parking and allows the current bus master to reuse the bus without rearbitration until another device requires the bus The deassertion of BB is done by an active pull up method i e BB is driven high and then released and held high by an external pull up resistor For proper BB operation the asynchronous bus arbitration enable bit ABE in the OMR register must be set BB requires an external pull up resistor 2 6 Interrupt and Mode Control The interrupt and mode control signals select the chip s operating mode as it comes out of hardware reset After RESET is deasserted these inputs are hardware interrupt request lines DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor Interrupt and Mode Control Table 2 8 Interrupt and Mode Control State during Reset Signal Description Signal Name Type MODA IRQA Input
244. ansfer Done Status 0 Channel Transfer Done Status 1 Channel Transfer Done Status 2 Channel Transfer Done Status 3 Channel Transfer Done Status 4 Channel Transfer Done Status 5 Active State Active Channel Mask DCHO DCH2 Active Channel 0 Active Channel 1 Active Channel 2 DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 B 10 Freescale Semiconductor Equates EQUATES for Phase Locked Loop PLL Register Addresses Of PLL M PCTL EQU SFFFFFD PLL Control Register PLL Control Register M MF EQU Multiplication Factor Bits Mask MFO MF11 M MFO EQU 0 Multiplication Factor bit M 1 EQU 1 Multiplication Factor bit M 2 EQU 2 Multiplication Factor bit M EQU 3 Multiplication Factor bit M EQU 4 Multiplication Factor bit M 5 EQU 5 Multiplication Factor bit M MF6 EQU 6 Multiplication Factor bit 7 EQU 7 Multiplication Factor bit M MF8 EQU 8 Multiplication Factor bit M MF9 EQU 9 Multiplication Factor bit M MF10 EQU 10 Multiplication Factor bit 10 M MF11 EQU 11 Multiplication Factor bit 11 M DF EQU 7000 Division Factor Bits Mask DFO DF2 M DFO EQU 12 Division Factor bit 0 M DF1 EQU 13 Division Factor bit 1 M DF2 EQU 14 Division Factor bit 2 M XTLR EQU 15 XTAL Range select bit M XTLD EQU 16 XTAL Disable Bit M PSTP EQU 17 STOP Processing State Bit DSP56366 24 Bit Digital Signal Processor User Manu
245. anual Rev 4 Freescale Semiconductor 6 13 HDIO8 DSP Side Programmer s Model 6 5 6 9 HPCR Host Request Open Drain HROD Bit 8 The HROD bit controls the output drive of the host request signals In the single host request mode HDRQ 0 in ICR if HROD is cleared and host requests are enabled HREN 1 and HEN 1 in HPCR the HOREQ signal is always driven If HROD is set and host requests are enabled the HOREQ signal is an open drain output In the double host request mode HDRQ 1 in the ICR if HROD is cleared and host requests are enabled HREN 1 and HEN 1 in the HPCR the HTRQ and signals are always driven If HROD is set and host requests are enabled the HTRQ and HRRQ signals are open drain outputs 6 5 6 10 Host Data Strobe Polarity HDSP Bit 9 If the HDSP bit 15 cleared the data strobe signals are configured as active low inputs and data is transferred when the data strobe is low If HDSP is set the data strobe signals are configured as active high inputs and data is transferred when the data strobe is high The data strobe signals are either HDS by itself or HRD and HWR together 6 5 6 11 HPCR Host Address Strobe Polarity HASP Bit 10 If the HASP bit is cleared the address strobe HAS signal is an active low input and the address on the host address data bus is sampled when the HAS signal is low If HASP is set HAS is an active high address strobe input and the address on the host address data
246. are performed in two clock cycles in pipeline fashion so that a new instruction can be initiated in every clock yielding an effective execution rate of one instruction per clock cycle The destination of every arithmetic operation can be used as a source operand for the immediately following arithmetic operation without a time penalty i e without a pipeline stall 1 4 1 2 Multiplier Accumulator MAC The MAC unit comprises the main arithmetic processing unit of the DSP56300 core and performs all of the calculations on data operands In the case of arithmetic instructions the unit accepts as many as three input operands and outputs one 56 bit result of the following form Extension Most Significant Product Least Significant Product EXT MSP LSP The multiplier executes 24 bit x 24 bit parallel fractional multiplies between two s complement signed unsigned or mixed operands The 48 bit product is right justified and added to the 56 bit contents of either DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 1 4 Freescale Semiconductor DSP56300 Core Functional Blocks the A or B accumulator A 56 bit result can be stored as a 24 bit operand The LSP can either be truncated or rounded into the MSP Rounding is performed if specified 1 4 2 Address Generation Unit AGU The AGU performs the effective address calculations using integer arithmetic necessary to address data operands in memory and contains the registers used to
247. as operating in the mode the SHI signals are disabled high impedance state Ifthe SHI was operating in the SPI mode the SHI signals not affected The HCSR status bits and the transmit receive paths are reset to the same state produced by hardware reset or software reset The HCSR and HCKR control bits are not affected NOTE It is recommended that the SHI be disabled before entering the stop state DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 7 25 SHI Programming Considerations NOTES DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 7 26 Freescale Semiconductor 8 Enhanced Serial AUDIO Interface ESAI 8 1 Introduction The Enhanced Serial Audio Interface ESAI provides a full duplex serial port for serial communication with a variety of serial devices including one or more industry standard codecs other DSPs microprocessors and peripherals which implement the Freescale SPI serial protocol The ESAI consists of independent transmitter and receiver sections each section with its own clock generator It is a superset of the 56300 Family ESSI peripheral and of the 56000 Family SAI peripheral NOTE The DSP56366 has two ESAI modules This section describes the ESAI and Section 9 describes the ESAI 1 The ESAI and ESAI 1 share 4 data pins This is described in the ESAI 1 section The ESAI block diagram is shown in Figure 8 1 The ESAI is named s
248. at the received data in the receive data registers of the enabled receivers have arrived during an even time slot when operating in the network mode Even time slots are all even numbered slots 0 2 4 6 etc Time slots are numbered from zero to N 1 where N 15 the number of time slots in the frame The zero time slot is considered even REDF is set when the contents of the receive shift registers are transferred to the receive data registers REDF is cleared when the DSP reads all the enabled receive data registers or cleared by hardware software ESAI individual or STOP resets If is set an ESAI receive even slot data interrupt request is issued when is set 8 3 6 9 SAISR Receive Odd Data Register Full RODF Bit 10 When set RODF indicates that the received data in the receive data registers of the enabled receivers have arrived during an odd time slot when operating in the network mode Odd time slots are all odd numbered slots 1 3 5 etc Time slots are numbered from zero to N 1 where 15 the number of time slots the frame is set when the contents of the receive shift registers are transferred to the receive data registers RODF is cleared when the DSP reads all the enabled receive data registers or cleared by hardware software ESAI individual or STOP resets 8 3 6 10 SAISR Transmit Frame Sync Flag TFS Bit 13 When set TFS indicates that a transmit frame sync occurred in the current time s
249. ating with CPHA 1 The SS line should be kept asserted during a data word transfer If the SS line is deasserted before the end of the data word transfer the transfer is aborted and the received data word is lost 7 7 2 SPI Master Mode The SPI master mode is initiated by enabling the SHI HEN 1 selecting the SPI mode 0 and selecting the master mode of operation HMST 1 Before enabling the SHI as an SPI master device the programmer should program the proper clock rate phase and polarity in HCKR When configured in the SPI master mode the SHI external pins operate as follows SCK SCL is the SCK serial clock output MISO SDA is the MISO serial data input MOSI HAO is the MOSI serial data output SS HA2 is the SS input It should be kept deasserted high for proper operation HREQ is the Host Request input The external slave device can be selected either by using external logic or by activating a GPIO pin connected to its SS pin However the SS input pin of the SPI master device should be held deasserted high for proper operation If the SPI master device SS pin is asserted the host bus error status bit HBER is set If the HBIE bit is also set the SHI issues a request to the DSP interrupt controller to service the SHI bus error interrupt In the SPI master mode the DSP must write to HTX to receive transmit or perform a full duplex data transfer Actually the interface performs
250. b pm a 6 3 G4 HDI08 Block Diagram sgass wae eis e ee ewe Een 6 4 6 5 HDI08 DSP Side Programmer s Model 6 5 DSP56366 24 Bit Digital Signal Processor Rev 4 TOC 2 Freescale Semiconductor 6 5 1 Host Receive Data Register HORM 6 6 6 5 2 Host Transmit Data Register HOT X oss ead aes Rr Ier e 6 6 6 5 3 Host Control Register HCR 6 7 6 5 3 1 HCR Host Receive Interrupt Enable HRIE Bit O 6 7 6 5 3 2 HCR Host Transmit Interrupt Enable HTIE Bit 6 7 6 5 3 3 HCR Host Command Interrupt Enable HCIE BIt 2 6 7 6 5 3 4 HCR Host Flags 2 3 HF2 HF3 Bits 3 4_ 6 8 6 5 3 5 HCR Host DMA Mode Control Bits HDM1 HDM2 Bits 5 7 6 8 6 5 3 6 HCR Reserved Bits 6 10 6 5 4 Host Status Register HSR uu saa oe eR POR ES 6 10 6 5 4 1 HSR Host Receive Data Full 0 6 10 6 5 4 2 HSR Host Transmit Data Empty HTDE Bit 6 10 6 5 4 3 HSR Host Command Pending 2 6 10 6 5 4 4 HSR Host Flags 0 1 HFO HF1 Bits 3 4 6 11 6 5 4 5 HSR Reserved Bits 5 6 8 15
251. be used to service the timers The timer programming model is shown in Figure 11 3 DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 11 3 Timer Event Counter Programming Model 23 7 6 5 4 3 2 1 0 15 14 13 12 Ton lene 23 22 21 20 23 Timer Prescaler Load Register TPLR TPLR FFFF83 Timer Prescaler Count Register TPCR TPLR FFFF82 Timer Control Status Register TCSR TCSRO FFFF8F TCSR1 FFFF8B TCSR2 FFFF87 Timer Load Register TLR TLRO FFFF8E TLR1 FFFF8A TLR2 FFFF86 Timer Compare Register TCPR TCPRO FFFF8D TCPR1 FFFF89 TCPR2 FFFF85 Timer Count Register TCR TCRO FFFF8C TCR1 FFFF88 TCR2 FFFF84 reserved read as 0 should be written with 0 for future compatibility Figure 11 3 Timer Module Programmer s Model DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 11 4 Freescale Semiconductor Timer Event Counter Programming Model 11 3 1 Prescaler Counter The prescaler counter is a 21 bit counter that is decremented on the rising edge of the prescaler input clock The counter is enabled when at least one ofthe three timers is enabled 1 e one or more ofthe timer enable TE bits are set and is using the prescaler output as its source 1 one or more of the PCE bits are set 11 3 2 Timer Prescaler Load Register TPLR The TPLR is a 24 bit read write register that controls
252. be configured to allow the SHI to operate in either SPI or mode Table 2 10 Serial Host Interface Signals Signal Name Signal Type State during Reset Signal Description SCK Input or output SCL Input or output Tri stated SPI Serial Clock The SCK signal is an output when the SPI is configured as a master and a Schmitt trigger input when the SPI is configured as a slave When the SPI is configured as a master the SCK signal is derived from the internal SHI clock generator When the SPI is configured as a slave the SCK signal is an input and the clock signal from the external master synchronizes the data transfer The SCK signal is ignored by the SPI if it is defined as a slave and the slave select SS signal is not asserted In both the master and slave SPI devices data is shifted on one edge of the SCK signal and is sampled on the opposite edge where data is stable Edge polarity is determined by the SPI transfer protocol 2 Serial Clock SCL carries the clock for 12 bus transactions in the 2 mode SCL is a Schmitt trigger input when configured as a slave and an open drain output when configured as a master SCL should be connected to through pull up resistor This signal is tri stated during hardware software and individual reset Thus there is no need for an external pull up in this state This input is 5 V tolerant DSP56366 24 Bit Digital Signa
253. ble 4 2 The operating modes are latched from MODA MODB MODC and MODD pins during reset Each operating mode is briefly described below Except for modes 0 and 8 the operation of all other modes is defined by the Bootstrap ROM source code in Appendix Bootstrap ROM Contents Table 4 2 DSP56366 Operating Modes Mode e i m Description 0 0 0 0 0 CO00000 Expanded mode 1 0 0 0 1 FFO0000 Bootstrap from byte wide memory 2 0 0 1 0 FF0000 Jump to PROM starting address 3 0 0 1 1 FFO0000 Reserved 4 0 1 0 0 FFO0000 Reserved 5 0 1 0 1 FFOOOO Bootstrap from SHI slave SPI mode DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor Operating Modes Table 4 2 DSP56366 Operating Modes continued Mode MOD MOD MOD MOD Reset Description D C B A Vector 6 0 1 1 0 0000 Bootstrap from SHI slave 2 mode HCKFR 1 100ns filter enabled 7 0 1 1 1 FF0000 Bootstrap from SHI slave IC mode HCKR 0 8 1 0 0 0 008000 Expanded mode 9 1 0 0 1 FFO0000 Reserved for Burn in testing A 1 0 1 0 0000 Reserved B 1 0 1 1 FF0000 Reserved C 1 1 0 0 FFOOOO HDIO8 Bootstrap ISA Mode D 1 1 0 1 FF0000 HDIO8 Bootstrap in HC11 non multiplexed mode E 1 1 1 0 FF0000 HDIO8 Bootstrap in 8051 multiplexed bus mode F 1 1 1 1 5 0000 HDIO8 Bootstrap 68302 bus mode
254. bled receivers DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 8 43 Operating Modes 8 4 3 ESAI Interrupt Requests The ESAI can generate eight different interrupt requests ordered from the highest to the lowest priority l ESAI Receive Data with Exception Status Occurs when the receive exception interrupt is enabled REIE 1 in the RCR register at least one of the enabled receive data registers is full RDF 1 and a receiver overrun error has occurred ROE 1 in the SAISR register ROE is cleared by first reading the SAISR and then reading all the enabled receive data registers ESAI Receive Even Data Occurs when the receive even slot data interrupt is enabled REDIE 1 at least one of the enabled receive data registers is full RDF 1 the data is from an even slot REDF 1 and no exception has occurred ROE 0 or REIE 0 Reading all enabled receiver data registers clears and ESAI Receive Data Occurs when the receive interrupt is enabled RIE 1 at least one of the enabled receive data registers is full RDF 1 no exception has occurred ROE 0 REIE 0 and no even slot interrupt has occurred REDF 0 or REDIE 0 Reading all enabled receiver data registers clears RDF ESAI Receive Last Slot Interrupt Occurs if enabled RLIE 1 after the last slot of the frame ended in network mode only regardless of the receive mask register setting The receive
255. bus 8 is sampled when the HAS signal is high 6 5 6 12 Host Multiplexed bus HMUX Bit 11 If the HMUX bit is set the HDIOS latches the lower portion of a multiplexed address data bus In this mode the internal address line values ofthe host registers are taken from the internal latch If HMUX is cleared it indicates that the HDIO8 is connected to a non multiplexed type of bus and the address lines are taken from the HDI08 input signals 6 5 6 13 HPCR Host Dual Data Strobe HDDS Bit 12 If the HDDS bit is cleared the HDIO8 operates in the single strobe bus mode In this mode the bus has a single data strobe signal for both reads and writes If HDDS is set the HDIO8 operates in the dual strobe bus mode In this mode the bus has two separate data strobes one for data reads the other for data writes See Figure 6 7 and Figure 6 8 for more information on the two types of buses HRW HDS In the single strobe bus mode the HDS Data Strobe signal qualifies the access while the HRW Read Write signal specifies the direction of the access Figure 6 7 Single strobe bus DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 6 14 Freescale Semiconductor HDIO8 DSP Side Programmer s Model Write data in HWR Write cycle Data Read data out HRD Read cycle In the dual strobe bus mode there are separate HRD and HWR signals that specify the access as being a read or
256. by the DSP core is reflected in the HSR on the DSP side of the HDIOS DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 6 21 HDIO8 External Host Programmer s Model 6 6 1 6 ICR Host Little Endian HLEND Bit 5 If the HLEND bit is cleared the HDI08 can be accessed by the host in big endian byte order If set the HDIOS can be accessed by the host in little endian byte order If the HLEND bit is cleared the RXH TXH register is located at address 5 the RXM TXM register is located at address 6 and the RXL TXL register is located at address 7 If the HLEND bit is set the RXH TXH register is located at address 7 the RXM TXM register is located at address 6 and the RXL TXL is located at address 5 See Table 6 8 for an illustration of the effect of HLEND The HLEND function is available only if HDM 2 0 000 in the host control register When HLEND is available the ICR bit 6 has no function and should be regarded as reserved Bits 6 and 5 function as read write HM 1 0 bits only when the bits HDM 2 0 100 See Table 6 5 The HMO and bits select the transfer mode of the HDIOS as shown in Table 6 12 Table 6 12 Host Mode Bit Definition HM1 HMO Mode 0 0 Interrupt Mode DMA Off 0 1 DMA Mode 24 Bit 1 0 DMA Mode 16 Bit 1 1 DMA Mode 8 Bit When both HM1 and HMO are cleared the DMA mode is disabled and the interrupt mode is enabled
257. c Enable M BME EQU 12 Mastership Enable M BRE EQU 13 Refresh Enable M BSTR EQU 14 Software Triggered Refresh M_BRF EQU 7F8000 Refresh Rate Bits Mask BRFO BRF7 M BRFO EQU 15 Refresh Rate Bit 0 M BRF1 EQU 16 Refresh Rate Bit 1 BRF2 EQU 17 Refresh Rate Bit 2 M BRF3 EQU 18 Refresh Rate Bit 3 M BRF4 EQU 19 Refresh Rate Bit 4 M BRF5 EQU 20 Refresh Rate Bit 5 M BRF6 EQU 21 Refresh Rate Bit 6 M BRF7 EQU 22 Refresh Rate Bit 7 M BRP EQU 23 Refresh prescaler Address Attribute Registers M BAT EQU 3 External Access Type and Pin Definition Bits Mask BATO BAT1 M BATO EQU 0 External Access Type and Pin Definition Bits 0 M 1 EQU 1 External Access Type and Pin Definition Bits 1 M BAAP EQU 2 Address Attribute Pin Polarity M BPEN EQU 3 Program Space Enable M BXEN EQU 4 X Data Space Enable M BYEN EQU 5 Y Data Space Enable DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 B 14 Freescale Semiconductor Equates M BAM EQU 6 Address Muxing M BPAC EQU 7 Packing Enable M BNC EQU 5 00 Number of Address Bits to Compare Mask BNCO BNC3 M BNCO EQU 8 Number of Address Bits to Compare 0 1 EQU 9 Number of Address Bits to Compare 1 M BNC2 EQU 10 Number of Address Bits to Compare 2 M BNC3 EQU 11 Number of Address Bits to Compare 3 M BAC EQU 5 000 Address to Compare Bits Mask 11 M BACO EQU 12 Address to Compare Bits 0 M 1 EQU 13 Addres
258. c Le ec ec unu pun Joue 20119 unvx Adu 5 uoissiulsueJ 1516 5 0 158 jou 3avx xooja 0043333 X arax osox isox asx XX yx y x x X x 1993092 0 L S 9 Z 8 6 OL LE CL 979 ZL 6 02 Le ec S X 215 Uld IOV 22104 S X Uld IOV paiqesiq 0 S X 992 IOV uexs SI X 201 J Y29010 9102 92JnoS 49019 peiqeu3 peiqeu3 peigesiq peigesiq 0 aiax ug dwa bey jeg eigeua unu pun xvaljainx eiaeua sues Figure D 29 DAX Control and Status Registers DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor D 44 Programming Sheets Application LLL Date PS 1 0 Prescaler Clock Source 00 Internal CLK 2 01 TIOO 10 Reserved 11 Reserved Programmer Sheet 1 of 3 23 22 21 20 19 18 17 16 15 14 13 12 11 40 9 8 7 6 5 4 3 2 1 Prescaler Preload Value PL 0 20 Timer Prescaler Load Register Reserved Program as 0 TPLR FFFF83 Read Write Reset 000000 23 22 21 20 19 1
259. caler Source bits PLO PL20 5 bit 23 bit 6 reserved bit bit 23 6 Transmitter High Frequency Clock Divider 11 TRM 10 V VBA register 6 Vector Base Address register VBA 6 X X Memory Address Bus XAB 6 X Memory Data Bus XDB 6 X Memory Expansion Bus 6 XAB 6 XDB 6 Y Y Memory Address Bus Y AB 6 Y Memory Data Bus YDB 6 Y Memory Expansion Bus 6 YAB 6 YDB 6 Load Value bits DSP56366 24 Bit Digital Signal Processor Rev 4 Freescale Semiconductor Index 5 DSP56366 24 Bit Digital Signal Processor Rev 4 Index 6 Freescale Semiconductor
260. clock is used to latch the data and frame sync in 8 3 1 8 TCCR Transmit Clock Source Direction TCKD Bit 21 The Transmitter Clock Source Direction TCKD bit selects the source of the clock signal used to clock the transmit shift registers in the asynchronous mode SYN 0 and the transmit shift registers and the receive shift registers in the synchronous mode SYN 1 When TCKD is set the internal clock source becomes the bit clock for the transmit shift registers and word length divider and is the output on the SCKT pin When TCKD is cleared the clock source is external the internal clock generator is disconnected from the SCKT pin and an external clock source may drive this pin See Table 8 2 8 3 1 9 TCCR Transmit Frame Sync Signal Direction TFSD Bit 22 TFSD controls the direction of the FST pin When TFSD is cleared FST is an input when TFSD is set FST is an output See Table 8 2 8 3 1 10 TCCR Transmit High Frequency Clock Direction THCKD Bit 23 THCKD controls the direction of the HCKT pin When THCKD 15 cleared HCKT is an input when THCKD is set HCKT 15 an output See Table 8 2 8 3 2 ESAI Transmit Control Register TCR The read write Transmit Control Register TCR controls the ESAI transmitter section Interrupt enable bits for the transmitter section are provided in this control register Operating modes are also selected in this register See Figure 8 5 DSP56366 24 Bit Digital Signal Processor User Manual Rev
261. clock pin THCKD must be set for proper ESAI 1 transmitter section operation Table 9 2 Transmitter Clock Sources Transmitter THCKD TFSD TCKD Bit Clock OUTPUTS Source 0 X X Reserved 1 0 0 SCKT 1 1 0 1 INT SCKT 1 1 1 0 SCKT 1 FST 1 1 1 1 INT FST 1 1 DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 9 6 Freescale Semiconductor ESAI 1 Programming Model RHCKD 1 Foss 6 PRESCALE DIVIDER DIVIDER DIVIDE DIVIDE BY DIVIDE BY DIVIDE BY BY2 1 1 1 OR TO DIVIDE TO DIVIDE RPMO RPM7 RFPO FLAGO OUT FLAGO IN SYNC MODE SYNC MODE INTERNAL BIT CLOCK RSWS4 RSWSO RX WORD RX WORD LENGTH DIVIDER CLOCK RX SHIFT REGISTER TSWS4 TSWSO RCLOCK INTERNAL BIT CLOCK TCLOCK TX WORD TX WORD LENGTH DIVIDER CLOCK TX SHIFT REGISTER TPSR TPMO TPM7 DIVIDE DIVIDE BY DIVIDE BY DIVIDE B BY2 1 1 1 Foss 9 OR TO DIVIDE TO DIVIDE THCKD 1 Notes 1 is the DSP56300 Core internal clock frequency Figure 9 4 ESAI 1 Clock Generator Functional Block Diagram DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 9 7 ESAI 1 Programming Model RDCO RDC4 RFSL RX WORD CLOCK RECEIVER INTERNAL RX FRAME CLOCK FRAME RATE DIVIDER RECEIVE CONTROL LOGIC RECEIVE FRAME SYNC FLAG1 IN FL
262. compatability When the HPCR register is modified HEN should be cleared Host acknowledge is enabled Host requests are enabled Host chip select input enabled address 9 enable bit has no meaning in non multiplexed bus address 8 enable bit has no meaning in non multiplexed bus Host GPIO pins are disabled If MD MC MB MA 1101 go load from HC11 Host If MD MC MB MA 1100 go load from ISA HOST 0101000000011000 HPCR Configure HAP 20 HRP 1 HCSP 0 HDDS 1 HMUX 0 HASP 0 HDSP HROD 0 spare 0 the following conditions Negative host acknowledge Positive host request Negatice chip select input Dual strobes bus RD and WR Non multiplexed bus address strobe polarity has no meaning in non multiplexed bus 0 Negative data stobes polarity Host request is active when enabled This bit should be set to 0 for DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor DSP56366 Bootstrap Program HEN 0 HAEN 0 HREN 1 HCSEN 1 HA9EN 0 0 HGEN 0 bra HDI08CONT HC11HOSTLD movep 0000001000011000 HPCR Configure HAP 0 HRP 0 HCSP 0 HDDS 0 HMUX 0 HASP 0 7 HDSP HROD 0 Spare 0 HEN 0 HAEN 0 HREN 1 HCSEN 1 HA9EN 0 0 HGEN 0 bra lt HDIO8CONT I8051HOSTLD movep 0001110000011110 Configure HAP 20 HRP 20 HC
263. conductor D 32 Programming Sheets Programmer Date Application 4 033 134 pasa pasy LOOWN OSMSYH LSMSS 65 6 VPSMSHY 16 P SH pasy Hd 3138 31033 any 0 4 r S 9 L 8 6 01 I vl ST 91 I LT 81 6I OC Ic cc tc LJ JoAI929M L 4941929 0 O S 1S4 uondiuos q 2 0 Su s L O S 351 0 154 gg u p lltus ejeq o snououuou s awe 154 GSW u peyius 0 uondiuoseg 35 4 uonduoseg 195941 EuosJog JoAlo29 peuBije euuoN 1 0 peubije y 0 uonduoseg uonduos q 4 160v uondeox3 0 0 L uonduoseg 0 0 0 1015 USAF SPO OGOWH S E pe gesip 81611016 u9 3 0
264. corresponding PD 1 bit is not reset and contains undefined data DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 9 14 Freescale Semiconductor ii GPIO Pins and Registers 11 10 9 8 7 6 5 4 3 2 1 0 Y FFFF9D PD11 PD10 PD9 PD8 PD7 PD6 PD4 PD1 PDO 23 22 21 20 19 18 17 16 15 14 13 12 Reserved bit read as zero should be written with zero for future compatibility Figure 9 17 PDRE Register DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 9 15 ssWwr n va lt IImmmsswa Qs OqN n wnwCI a s GPIO Pins and Registers NOTES DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 9 16 Freescale Semiconductor 10 10 1 Digital Audio Transmitter Introduction The Digital Audio Transmitter DA X is a serial audio interface module that outputs digital audio data in the AES EBU CP 340 and IEC958 formats Some of the key features of the DAX are listed below Operates on a frame basis The can handle one frame consisting of two subframes of audio and non audio data at a time Double buffered audio and non audio data The DAX data path is double buffered so the next frame data can be stored in the DAX without affecting the frame currently being transmitted Direct Memory Access Audio data and non audio data can be written t
265. ctor HDI08 External Host Programmer s Model written by the host processor be set by the host processor using the initialize feature be used to assert the external HOREQ signal if the TREQ bit is set Regardless of whether interrupt is enabled TXDE indicates whether the TX registers are full and data can be latched in so that polling techniques may be used by the host processor 6 6 3 3 ISR Transmitter Ready TRDY Bit 2 The TRDY status bit indicates that TXH TXM TXL and the HORX registers are empty TRDY TXDE HRDF If TRDY is set the data that the host processor writes to TXH TXM TXL is immediately transferred to the DSP side of the HDIOS This feature has many applications For example if the host processor issues a host command which causes the DSP core to read the HORX the host processor can be guaranteed that the data it just transferred to the HDIOS is what is being received by the DSP core 6 6 3 4 ISR Host Flag 2 HF2 Bit 3 The HF2 bit in the ISR indicates the state of host flag 2 in the HCR on the DSP side HF2 can be changed only by the DSP see Section 6 5 3 4 Host Flags 2 3 HF2 HF3 Bits 3 4 6 6 3 5 ISR Host Flag 3 HF3 Bit 4 The HF3 bit in the ISR indicates the state of host flag 3 in the HCR on the DSP side HF3 can be changed only by the DSP see Section 6 5 3 4 Host Flags 2 3 HF2 HF3 Bits 3 4 6 6 3 6 ISR Reserved Bits 5 6 These bits are
266. ctor Sheet 5 of 5 Programmer Date G44433 X 110d ZAN SAW 93IN ZAN SAW 63IN OL3IN LLN HILX GILX dLSd 009 ead ead 1 T1d 0 SL OL E 8 6L 0 16 cc 6 CBE 99696460 uo 129 Jo OU oAeu pue 02 H11X SHq 14 930N 1e 2 2 1 L 2 0 1 1019 UOISIAIG dG 0 aq 101284 UOISIAIG 401284 uoislAlpaJd 0dd 101264 UOISIAIpald 344 343 2 002 gt lt 0 471X je1s a ul ejo o 09 0 002 1ndino 201 200 100 L 000 103964 uoneordniniy LLAN LLAIN OJIN SHA 101284 uoneordniniy uy TV 1X3 JOJE IOSE 0 q11X eigesia 1 1 Freescale Semiconductor Programming Sheets Application yous peigeu3 peigeu3 19401 yous peigeu3 peiqesid 1 4015 Buunp uonduinsuo 3018 10 1 2 1050 Tid 015
267. d DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 8 13 ESAI Programming Model 8 3 2 3 TCR ESAI Transmit 2 Enable TE2 Bit 2 TE2 enables the transfer of data from TX2 to the transmit shift register 72 When TE2 15 set and a frame sync is detected the transmit 2 portion of the ESAI is enabled for that frame When TE2 is cleared the transmitter 2 is disabled after completing transmission of data currently in the ESAI transmit shift register Data can be written to 2 when 2 is cleared but the data 15 not transferred to the transmit shift register 2 The SDO2 SDI3 pin is the data input pin for RX3 if TE2 is cleared and in the RCR register is set If both RE3 and TE2 are cleared the transmitter and receiver are disabled and the pin is tri stated Both RE3 and TE2 should not be set at the same time The normal mode transmit enable sequence is to write data to one or more transmit data registers before setting TEx The normal transmit disable sequence is to clear TEx TIE and TEIE after TDE equals one In the network mode the operation of clearing TE2 and setting it again disables the transmitter 2 after completing transmission of the current data word until the beginning of the next frame During that time period the SDO2 SDI3 pin remains in the high impedance state The on demand mode transmit enable sequence can be the same as the normal mode or TE2 can be left enabled
268. d as a transmitter SDO3 is used to transmit data from the TX3 serial transmit shift register When enabled for ESAI_1 operation this is the ESAI_1 Serial Data Output 3 Serial Data Input 2 When programmed as a receiver SDI2 is used to receive serial data into the RX2 serial receive shift register When enabled for ESAI 1 operation this is the ESAI 1 Serial Data Input 2 Port C 8 When the ESAI is configured as GPIO this signal is individually programmable as input output or internally disconnected When enabled for ESAI_1 GPIO this is the Port E 8 signal The default state after reset is GPIO disconnected This input is 5 V tolerant DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor Enhanced Serial Audio Interface Table 2 11 Enhanced Serial Audio Interface Signals continued Signal Name SDO2 SDO2 1 SDI3 SDI3_1 9 9 Signal Type Output Input Input output or disconnected State during Reset GPIO disconnected Signal Description Serial Data Output 2 When programmed as a transmitter SDO2 is used to transmit data from the TX2 serial transmit shift register When enabled for ESAI 1 operation this is the ESAI 1 Serial Data Output 2 Serial Data Input 3 When programmed as a receiver 5013 is used to receive serial data into the RX3 serial receive shift register When enabled for ESAI 1 operation this is the ESAI 1 Se
269. d may be written to again can be 8 12 16 20 24 or 32 bits determined by the slot length control bits in the TCR register Data is shifted out of these registers MSB first if TSHFD 0 and LSB first if TSHFD 1 8 3 10 ESAI Transmit Data Registers TX5 TX4 TX3 2 1 0 5 4 TX3 TX2 and TXO are 24 bit write only registers Data to be transmitted is written into these registers and is automatically transferred to the transmit shift registers see Figure 8 13 and Figure 8 14 The data written 8 12 16 20 or 24 bits should occupy the most significant portion of the TXx according to the ALC control bit setting The unused bits least significant portion and the 8 most significant bits when ALC 1 of the are don t care bits The DSP is interrupted whenever the TXx becomes empty if the transmit data register empty interrupt has been enabled 8 3 11 ESAI Time Slot Register TSR The write only Time Slot Register TSR is effectively a null data register that is used when the data is not to be transmitted in the available transmit time slot The transmit data pins of all the enabled transmitters are in the high impedance state for the respective time slot where TSR has been written The Transmitter External Buffer Enable pin FSR pin when SYN 1 TEBE 1 RFSD 1 disables the external buffers during the slot when the TSR register has been written 8 3 12 Transmit Slot Mask Registers TSMB The Transmit
270. d software reset clear all PRRE bits Table 9 4 PCRE and PRRE Bits Functionality PDE i PE i Port Pin i Function 0 0 disconnected 0 1 GPIO input 1 0 GPIO output 1 1 ESAI 1 11 10 9 8 7 6 5 4 3 2 1 0 Y FFFF9F 11 10 9 PE8 PE7 6 4 PE1 PEO 23 22 21 20 19 18 17 16 15 14 13 12 Reserved bit read as zero should be written with zero for future compatibility Figure 9 15 PCRE Register 11 10 9 8 7 6 5 4 3 2 1 0 Y FFFF9E PDE11 PDE10 PDE9 PDE8 7 PDE6 4 PDE3 PDE1 PDEO 23 22 21 20 19 18 17 16 15 14 13 12 Reserved bit read as zero should be written with zero for future compatibility Figure 9 16 PRRE Register 9 5 3 Port E Data register PDRE The read write 24 bit Port E Data Register see Figure 9 17 is used to read or write data to from ESAI 1 GPIO pins Bits PD 11 0 are used to read or write data from to the corresponding port pins if they are configured as GPIO If a port pin i is configured as GPIO input then the corresponding PD i bit will reflect the value present on this pin If a port pin 1 is configured as a GPIO output then the value written into the corresponding PD i bit will be reflected on this pin If a port pin i is configured as disconnected the
271. d write this register The contents of IVR are placed on the host data bus H0 H7 when both the HOREQ and HACK signals are asserted The contents of this register are initialized to 0F by hardware or software reset which corresponds to the uninitialized interrupt vector in the MC68000 Family 7 6 5 4 3 2 1 0 7 6 5 4 2 1 IVO Figure 6 15 Interrupt Vector Register IVR 6 6 5 Receive Byte Registers RXH RXM RXL The receive byte registers are viewed by the host processor as three 8 bit read only registers These registers are the receive high register RXH the receive middle register RXM and the receive low register RXL They receive data from the high middle and low bytes respectively of the HOTX register and are selected by the external host address inputs HA2 HA1 and HAO during a host processor read operation The memory locations of the receive byte registers are determined by the HLEND bit in the ICR If the HLEND bit is set the RXH is located at address 7 RXM at 6 and RXL at 5 If the HLEND bit is cleared the RXH is located at address 5 RXM at 6 and RXL at 7 When data 15 transferred from the HOTX register to the receive byte registers the receive data register full RXDF bit is set The host processor may program the RREQ bit to assert the external HOREQ HRRQ signal when RXDF is set This indicates that the HDIO8 has a full word either 8 16 or 24 bits for t
272. device address of 1011 HA2 O HAO 7 4 5 SHI Clock Control Register HCKR DSP Side The HCKR is a 24 bit read write register that controls SHI clock generator operation The HCKR bits should be modified only while the SHI is in the individual reset state HEN 0 in the HCSR For proper SHI clock setup please consult the datasheet The programmer should not use the combination HRS 1 and HDM 7 0 00000000 since it may cause synchronization problems and improper operation it is an illegal combination The HCKR bits are cleared during hardware reset or software reset except for CPHA which is set The HCKR is not affected by the stop state The HCKR bits are described in the following paragraphs 7 4 5 1 Clock Phase and Polarity CPHA and CPOL Bits 1 0 The Clock Phase CPHA bit controls the relationship between the data on the master in slave out MISO and master out slave in MOST pins and the clock produced or received at the SCK pin The CPOL bit determines the clock polarity 1 active high 0 active low The clock phase and polarity should be identical for both the master and slave SPI devices CPHA and CPOL are functional only when the SHI operates in the SPI mode and are ignored in the mode The CPHA bit is set and the CPOL bit is cleared during hardware reset and software reset The programmer may select any of four combinations of serial clock SCK phase and polarity when operating in the SPI mode S
273. dress movem r2 a2 Get the 8 LSB from ext P mem 8 a a Shift 8 bit data into A1 _LOOP9 move 1 Starting address for load move 1 1 Save it in r1 a0 holds the number of words do a0 LOOP10 read program words do 43 LOOP11 Each instruction has 3 bytes movem 52 2 Get the 8 LSB from ext P mem 8 a a Shift 8 bit data into A1 _ 11 Go get another byte movem 1 Store 24 bit result in P mem nop pipeline delay LOOP10 and go get another 24 bit word Boot from EPROM done bra FINISH OMR1 XXX RESER IF MD MC MB MA 101x go to RESERVED IF MD MC MB MA 1001 go to BURN MB omr OMR1ISO IF MD MC MB MA 110x go to look for ISA HC11 MA omr I8051HOSTLD If MD MC MB MA 1110 go load from 8051 Host If MD MC MB MA 1111 go load from MC68302 Host This is the routine which loads a program through the HDIO8 host port The program is downloaded from the host MCU with the following rules 1 3 bytes Define the program length 2 3 bytes Define the address to which to start loading the program to 3 3n bytes while n is the program length defined by the 3 first bytes The program words will be stored in contiguous PRAM memory locations starting at the specified starting address After reading the program words program execution starts from the same address where loading started The host MCU may
274. ductor Servicing The Host Interface STATUS roD 7 Host Request ASSERTED EF INIT HLEND HDRQ RREQ ENABLE Figure 6 16 HDIO8 Host Request Structure 6 7 3 Servicing Interrupts If either the HOREQ HTRQ or the HRRQ signal or both are connected to the host processor interrupt inputs the HDIO8 can request service from the host processor by asserting one of these signals The HOREQ HTRQ and or the HRRQ signal is asserted when TXDE 1 and or RXDF 1 and the corresponding enable bit TREQ or RREQ respectively is set This is depicted in Figure 6 16 HOREQ HTRQ and HRRQ are normally connected to the host processor maskable interrupt inputs The host processor acknowledges host interrupts by executing an interrupt service routine The host processor can test RXDF and TXDE to determine the interrupt source The host processor interrupt service routine must read or write the appropriate HDIOS data register to clear the interrupt HOREQ HTRQ and or is deasserted under the following conditions The enabled request is cleared or masked The DSP is reset Ifthe host processor is a member of the MC68000 family there is no need for the additional step when the host processor reads the ISR to determine how to respond to an interrupt generated by the DSP Instead the DSP automatically sources the contents of the IVR on the data bus when the host processor acknowledges the interrupt by asserting HACK The con
275. dulus Select 9 HEN HCSR SHI Enable 10 HFIFO HCSR FIFO Enable Control 12 HFMO0 HFMI HCKR Filter Mode 9 08 9 GPIO 1 HCSR Serial Host Interface Selec tion 11 HIDLE HCSR Idle 13 HMO0 HM 1 HCSR Serial Host Interface Mode 11 HMST HCSR Master Mode 12 Host Receive Data FIFO HRX 6 Receive Data FIFO DSP Side 6 Transmit Data Register HTX 6 Transmit Data Register DSP Side 6 Host Interface 9 1 9 11 12 HREQ Function In SHI Slave Modes 12 HRFF HCSR Host Receive FIFO Full 15 HRIEO HRIE1 HCSR Receive Interrupt Enable 14 HRNE HCSR Host Receive FIFO Not Empty 15 HROE HCSR Host Receive Overrun Error 15 HCSR Host Request Enable 12 HTDE HCSR Host Transmit Data Empty 15 HTIE HCSR Transmit Interrupt Enable 13 HTUE HCSR Host Transmit Underrun Error 14 PC 10 1 16 Bit Transfer 17 Bus Protocol For Host Read Cycle 19 Bus Protocol For Host Write Cycle 18 Data Transfer Formats 18 Master Mode 23 Protocol for Host Write Cycle 18 Receive Data In Master Mode 24 Receive Data In Slave Mode 21 Slave Mode 21 Start and Stop Events 17 DSP56366 24 Bit Digital Signal Processor Rev 4 Index 2 Freescale Semiconductor Transmit Data In Master Mode 24 Transmit Data In Slave Mode 22 Bus Acknowledgment 18 Mode 1 IEC958 10 1 Inter Integrated Circuit Bus 10 1 internal buses 6 Internal Exception Priorities SHI 5 interrupt 6 interrupt and mode control 1 7
276. e 9 12 TSMB 1 Register 9 3 14 Receive Slot Mask Registers RSMA 1 RSMB 1 The Receive Slot Mask Registers RSMA 1 and RSMB 1 are two read write registers used by the receiver in network mode to determine for each slot whether to receive a data word and generate a receiver full condition RDF 1 or to ignore the received data RS MA 1 and RSMB 1 should be considered as each containing half of a 32 bit register RSM 1 See Figure 9 13 and Figure 9 14 Bit number N in RSM 1 RS is an enable disable control bit for receiving data in slot number N DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 9 12 Freescale Semiconductor Operating Modes 11 10 9 8 7 6 5 4 3 2 1 0 Y FFFF9B 8511 510 RS9 RS8 RS7 RS6 RS5 RS4 RS2 RS1 RSO 23 22 21 20 19 18 17 16 15 14 13 12 RS15 514 RS13 RS12 Reserved bit read as zero should be written with zero for future compatibility Figure 9 13 RSMA 1 Register 11 10 9 8 7 6 5 4 3 2 1 0 Y FFFF9C RS27 RS26 RS25 RS24 RS23 RS22 RS21 RS20 2519 RS18 RS17 16 23 22 21 20 19 18 17 16 15 14 13 12 531 2530 RS29 RS28 Reserved bit read as zero should be written with zero for future compatibility Figure 9 14 RSMB 1 Register 9 4 Operating Modes 9 4
277. e Byte Registers Receive Byte Regi sters 7 6 5 4 Read Only Reset Empty Host Transmit Data HLEND 0 017 Transmit Low Byte Transmit Middle Byte Transmit High Byte Not Used Host Transmit Data HLEND 1 017 Transmit Low Byte Transmit Middle Byte Transmit High Byte Not Used Transmit Byte Registers 7 6 5 4 Write Only Transmit Byte Registers Reset Empty Figure D 11 Host Receive and Transmit Byte Registers DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 D 26 Freescale Semiconductor Programming Sheets Date Application 02 49019 IHS 0 S gt 064444 X TANE eo fada 21099 091010 0 0 OH DINH LINH 49019 IHS OL SL 91 8L Oc le G Programmer pessed q jeuonesedo Busu uo YIS ulje uo yry YOS Buje uo 40 1 YIS Buisu uo YOS peiqesip pessed g 9SION IHS YWSH 1
278. e TX5 serial transmit shift register Serial Data Input 0 1 When programmed as a receiver SDIO is used to receive serial data into the RXO serial receive shift register Port E 6 When the ESAI is configured as GPIO this signal is individually programmable as input output or internally disconnected The default state after reset is GPIO disconnected This input cannot tolerate 5 V DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 2 20 Freescale Semiconductor SPDIF Transmitter Digital Audio Interface Table 2 12 Enhanced Serial Audio Interface 1 Signals continued Signal State during 1 Name Signal Type Reset Signal Description 5004 1 Output GPIO Serial Data Output 4 1 When programmed as a transmitter SDO4 disconnected is used to transmit data from the TX4 serial transmit shift register SDI1_1 Input Serial Data Input 1 1 When programmed as a receiver SDI1 is used to receive serial data into the RX1 serial receive shift register Input output or Port E 7 When the ESAI is configured as GPIO this signal is disconnected individually programmable as input output or internally disconnected The default state after reset is GPIO disconnected This input is 5 V tolerant 2 11 SPDIF Transmitter Digital Audio Interface Table 2 13 Digital Audio Interface DAX Signals Signal State During Tm Reset Signal Description ACI Input GP
279. e default mode after reset is GPIO input This can be changed to output or configured as a timer input output through the timer 0 control status register TCSRO If TIOO is not being used it is recommended to either define it as GPIO output immediately at the beginning of operation or leave it defined as GPIO input but connected to Vcc through a pull up resistor in order to ensure a stable logic level at this input This input is 5 V tolerant 2 13 JTAG OnCE Interface Table 2 15 JTAG OnCE Interface Signal Signal State during Reset Signal Description TCK Input Input Test Clock TCK is a test clock input signal used to synchronize the JTAG test logic It has an internal pull up resistor This input is 5 V tolerant TDI Input Input Test Data Input TDI is a test data serial input signal used for test instructions and data TDI is sampled on the rising edge of TCK and has an internal pull up resistor This input is 5 V tolerant TDO Output Tri stated Test Data Output TDO is a test data serial output signal used for test instructions and data TDO is tri statable and is actively driven in the shift IR and shift DR controller states TDO changes on the falling edge of TCK TMS Input Input Test Mode Select 5 is an input signal used to sequence the test controller s state machine TMS is sampled on the rising edge of TCK and has an internal pull up resistor This inpu
280. e e ke he he e ke he he e ke he he e ke he he e ke ke he e e ke he e e e ke e e e page 1327555 0 070 nolist INCLUDE ioequ asm INCLUDE intequ asm list START equ 100 main program starting address PATCH OFSET equ 128 patch offset M PAE equ 23 Patch Enable M PROMS equ Sffafec ROM area Start M PROME equ Sffafff ROM area End org P START move 4M PROMS r0 bset CE sr CacheEnable 1 bset HM PAE omr PatchEnable 1 move 5800000 any external address move 128 n1 128 for 1K ICACHE sector size move M_PROMS PATCH OFSET r2 dup 8 punlock x1 01 initialize TAGs to different values endm plock r2 lock patch s sector start mid end move PATCH DATA START r1 1 replace ROM code by PATCH DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 4 3 Operating Modes PATCH LOOP ENDTEST patch data PATCH DATA START PATCH DATA END k k k hec k k k k k K k K e k e he K KUK K e ke K he e khe he e ke he K KOK K he e K he he ek he he e ke KOK e KOK hee ke he KOK ke K he e k e he e e e ke e e K 4 3 do movem movem nop jsr jmp nop nop nop nop move move move PATCH DATA END PATCH DATA START 1 PATCH LOOP p 51 x0 x0 p r2 4M PROMS ENDTEST 5 m0 6 m1 7 m2 Operating Modes Do loop restriction Start ROM code execution The operating modes are defined as shown in Ta
281. e expects to read a 24 bit word Specifying the number of program words a 24 bit word specifying the address to start loading the program words and then a 24 bit word for each program word to be loaded The program words will be stored in contiguous PRAM memory locations starting at the specified starting address After reading the program words program execution starts from the same address where loading started The Host Interface bootstrap load program may be stopped by Setting the Host Flag 0 HFO This will start execution of the loaded program from the specified starting address If MD MC MB MA 1110 then it loads the program RAM from the Host Interface programmed to operate in the 8051 multiplexed bus mode in double strob pin configuration The HOST 8051 bootstrap code expects accesses that are byte wide DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 A 2 Freescale Semiconductor DSP56366 Bootstrap Program The HOST 8051 bootstrap code expects to read 3 bytes forming a 24 bit word Specifying the number of program words 3 bytes forming a 24 bit word Specifying the address to start loading the program words and then 3 bytes forming 24 bit words for each program word to be loaded The program words will be stored in contiguous PRAM memory locations Starting at the specified starting address After reading the program words program execution starts from the same addr
282. e highest register RXL or TXL the address counter is not incremented but is loaded with the value in HM1 and HMO This allows 8 16 or 24 bit data to be transferred in a circular fashion and eliminates the need for the DMA controller to supply the HA2 HA1 and HAO address signals For 16 or 24 bit data transfers the DSP CPU interrupt rate is reduced by a factor of 2 or 3 respectively DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 6 22 Freescale Semiconductor HDIO8 External Host Programmer s Model from the host request rate i e for every two or three host processor data transfers of one byte each there is only one 24 bit DSP CPU interrupt If either HDM1 or HDMO in register are set bits 6 and 5 become read only bits that reflect the value of HDM 1 0 6 6 1 7 ICR Initialize Bit INIT Bit 7 The INIT bit is used by the host processor to force initialization of the HDIO8 hardware During initialization the HDIO8 transmit and receive control bits are configured Using the INIT bit to initialize the HDI08 hardware may or may not be necessary depending on the software design of the interface The type of initialization done when the INIT bit is set depends the state of TREQ and RREQ in the HDIOS The INIT command which is local to the HDIOS is designed to conveniently configure the 108 into the desired data transfer mode The effect of the INIT command is described in Table 6 13 Whe
283. e stop event This signal is tri stated during hardware software and individual reset Thus there is no need for an external pull up in this state This input is 5 V tolerant MOSI Input or output Tri stated SPI Master Out Slave In When the SPI is configured as a master MOSI is the master data output line The MOSI signal is used in conjunction with the MISO signal for transmitting and receiving serial data MOSI is the slave data input line when the SPI is configured as a slave This signal is a Schmitt trigger input when configured for the SPI Slave mode HAO Input Slave Address 0 This signal uses a Schmitt trigger input when configured for the 12C mode When configured for 12 slave mode the HAO signal is used to form the slave device address is ignored when configured for the IC master mode This signal is tri stated during hardware software and individual reset Thus there is no need for an external pull up in this state This input is 5 V tolerant DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 2 13 Serial Host Interface Table 2 10 Serial Host Interface Signals continued Signal Name Signal Type Input HA2 Input State during Reset Tri stated Signal Description SPI Slave Select This signal is an active low Schmitt trigger input when configured for the SPI mode When configured for t
284. eared its value is 0 DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 ii Freescale Semiconductor The word assert means that a high true active high signal is pulled high to or that a low true active low signal is pulled low to ground The word deassert means that a high true signal is pulled low to ground or that a low true signal is pulled high to High True Low True Signal Conventions Signal Symbol Logic State Signal State Voltage True Asserted Ground PIN False Deasserted Vec PIN True Asserted Vec PIN False Deasserted Ground 1 PINisa generic term for any pin on the chip Ground is an acceptable low voltage level See the appropriate data sheet for the range of acceptable low voltage levels typically a TTL logic low 3 Vcc is an acceptable high voltage level See the appropriate data sheet for the range of acceptable high voltage levels typically a TTL logic high Pins or signals that are asserted low made active when pulled to ground text have an overbar e g RESET is asserted low In code examples have a tilde in front of their names In example below line 3 refers to the 550 pin shown as 550 Sets of pins or signals are indicated by the first and last pins or signals in the set e g HA1 HAS Code examples are displayed in a monospaced font as shown below Example Sample Code Listing BFSET 5000
285. eared If the counter overflows the TOF bit is set and if TOIE is set an overflow interrupt is generated The counter contents can be read at any time by reading the TCR 11 4 1 3 Timer Toggle Mode 2 Bit Settings Mode Characteristics TC2 TC1 TCO TIOO Clock KIND NAME 0 0 1 0 Output Internal 0 Timer Toggle In this mode the timer generates a periodic interrupt timer 0 also toggles the polarity of the TIOO signal Set TE bit in the TCR to clear the counter and enable the timer The value the timer is to count is loaded into the TPCR The counter is loaded with the TLR value when the first timer clock signal is received The TIOO signal is loaded with the value of the INV bit The timer clock signal can be taken from either the DSP56366 clock divided by two CLK 2 or from the prescaler clock output Each subsequent clock signal increments the counter DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 11 14 Freescale Semiconductor Timer Modes of Operation When the counter value matches the value in the TCPR the polarity of the TIOO output signal is inverted The TCF bit in the TCSR is set and a compare interrupt is generated if the TCIE bit is set If the bit is set the counter is loaded with the value of the TLR when the next timer clock is received and the count is resumed If the TRM bit is cleared the counter continues to be incremented on each timer
286. earlier i e together with the last bit of the previous data word 8 3 4 12 Receiver Section Personal Reset RPR Bit 19 The control bit is used to put the receiver section of the ESAI in the personal reset state The transmitter section 15 not affected When is cleared the receiver section may operate normally When RPR is set the receiver section enters the personal reset state immediately When in the personal reset state the status bits are reset to the same state as after hardware reset The control bits are not affected by the personal reset state The receiver data pins are disconnected while in the personal reset state Note that to leave the personal reset state by clearing RPR the procedure described in Section 8 6 ESAI Initialization Examples should be followed DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 8 30 Freescale Semiconductor ESAI Programming Model 8 3 413 RCR Receive Exception Interrupt Enable REIE Bit 20 When is set the DSP 15 interrupted when both RDF and in the SAISR status register are set When REIE is cleared this interrupt is disabled Reading the SAISR status register followed by reading the enabled receivers data registers clears ROE thus clearing the pending interrupt 8 3 4 14 Receive Even Slot Data Interrupt Enable REDIE Bit 21 The REDIE control bit is used to enable the receive even slot data interrupts If REDIE is set the
287. eceive FIFO Full SHI Transmit Data Lowest SHI Receive FIFO Not Empty 7 4 1 SHI Input Output Shift Register IOSR Host Side The variable length Input Output Shift Register IOSR can be viewed as a serial to parallel and parallel to serial buffer in the SHI The IOSR is involved with every data transfer in both directions read and write In compliance with the and SPI bus protocols data is shifted in and out MSB first In 8 bit data transfer modes the most significant byte of the IOSR is used as the shift register In 16 bit data transfer modes the two most significant bytes become the shift register In 24 bit transfer modes the shift register uses all three bytes of the IOSR see Figure 7 5 The IOSR cannot be accessed directly either by the host processor or by the NOTE DSP It is fully controlled by the SHI controller logic DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 7 5 Serial Host Interface Programming Model 23 16 15 8 7 0 Mode of Operation 8 Bit Data Mode 24 Bit Data Mode A Stops Data When Data Mode is Selected T Passes Data When Data Mode is Selected 0420 Figure 7 5 SHI I O Shift Register IOSR 7 4 2 SHI Host Transmit Data Register HTX DSP Side The host transmit data register HTX is used for DSP to Host data transfers The HTX register is 24 bits wide Writing to the HTX register by DSP core instructions or by DMA t
288. eceive data registers are double buffered to allow the DSP and host processor to efficiently transfer data at high speed Memory mapping allows DSP core communication with the HDIOS registers to be accomplished using standard instructions and addressing modes Since the host bus may operate asynchronously with the DSP core clock the HDIOS registers are divided into 2 banks The host side bank is accessible to the external host and the DSP side bank is accessible to the DSP core The HDI08 supports the following three classes of interfaces Host processor MCU connection DMA controller GPIO port Host port pins not in use may be configured as GPIO pins The host interface provides up to 16 GPIO pins These pins can be programmed to function as either GPIO or host interface For more information on the HDI08 see Section 6 Host Interface HD108 1 5 2 General Purpose Input Output GPIO The GPIO port consists of as many as 37 programmable signals all of which are also used by the peripherals HDI08 ESAI ESAI 1 DAX and TEC There are no dedicated GPIO signals The signals are configured as GPIO after hardware reset Register programming techniques for all GPIO functionality among these interfaces are very similar 1 5 3 Triple Timer TEC This section describes a peripheral module composed of a common 21 bit prescaler and three independent and identical general purpose 24 bit timer event counters each one having its ow
289. ections The user must provide adequate external decoupling capacitors There are two connections GNDy Host Ground GND is an isolated ground for the HDO8 I O drivers This connection must be tied externally to all other chip ground connections The user must provide adequate external decoupling capacitors There is one GND connection GNDs 2 SHI ESAI ESAI 1 DAX and Timer Ground GNDs is an isolated ground for the SHI ESAI ESAI 1 DAX and Timer This connection must be tied externally to all other chip ground connections The user must provide adequate external decoupling capacitors There are two GNDg connections 2 4 Clock and PLL Table 2 4 Clock and PLL Signals Signal Name State during Reset Signal Description Type EXTAL Input Input External Clock Input An external clock source must be connected to EXTAL in order to supply the clock to the internal clock generator and PLL This input cannot tolerate 5 V PCAP Input Input PLL Capacitor PCAP is an input connecting an off chip capacitor to the PLL filter Connect one capacitor terminal to PCAP and the other terminal to If the PLL is not used PCAP may be tied to Vcc GND or left floating PINIT NMI Input Input PLL Initial Nonmaskable Interrupt During assertion of RESET the value of PINIT NMI is written into the PLL Enable PEN bit of the PLL control register determining whether the PLL is enabled o
290. ed bit is cleared do not use the BSET command The proper way to clear these bits is to write using a MOVEP instruction a one to the flag to be cleared and a zero to the other flag 11 3 4 13 TCSR Reserved Bits Bits 3 10 14 16 19 22 23 These reserved bits are read as zero and should be written with zero for future compatibility DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 11 11 Timer Modes of Operation 11 3 5 Timer Load Register TLR The TLR is a 24 bit write only register In all modes the counter is preloaded with the TLR value after the TE bit in the TCSR is set and a first event occurs The programmer must initialize the TLR to ensure correct operation in the appropriate timer operating modes Intimer modes if the timer reload mode TRM bit in the TCSR is set the counter is reloaded each time after it has reached the value contained by the timer compare register TCR and the new event occurs n measurement modes if the TRM bit in the TCSR is set and the TE bit in the TCSR is set the counter is reloaded with the value in the TLR on each appropriate edge of the input signal In modes if the bit in the TCSR is set the counter is reloaded each time after it has overflowed and the new event occurs In watchdog modes if the TRM bit in the TCSR is set the counter is reloaded each time after it has reached the value contained by the TCR and the new even
291. ed only in the slave mode it is ignored otherwise If HCKER is set the SHI holds the clock line to GND if it is not ready to send data to the master during a read transfer or if the input FIFO is full when the master attempts to execute a write transfer In this way the master may detect that the slave is not ready for the requested transfer without causing an error condition in the slave When HCKFR is set for transmit sessions the SHI clock generator must be programmed as if to generate the same serial clock as produced by the external master otherwise erroneous operation may result The programmed frequency should be in the range of 1 to 0 75 times the external clock frequency If HCKFR is cleared any attempt from the master to execute a transfer when the slave is not ready results in an overrun or underrun error condition DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 7 11 Serial Host Interface Programming Model It is recommended that an SHI individual reset be generated HEN cleared before changing HCKFR is cleared during hardware reset and software reset 7 4 6 5 HCSR FIFO Enable Control HFIFO Bit 5 The read write control bit HFIFO selects the receive FIFO size When HFIFO is cleared the FIFO has one level When HFIFO is set the FIFO has 10 levels It is recommended that an SHI individual reset be generated HEN cleared before changing HFIFO HFIFO is cleared dur
292. ee Figure 7 6 DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 7 7 Serial Host Interface Programming Model c4 Internal Strobe for Data Capture 0421 Figure 7 6 SPI Data To Clock Timing Diagram If CPOL is cleared it produces a steady state low value at the SCK pin ofthe master device whenever data is not being transferred If the CPOL bit is set it produces a high value at SCK pin of the master device whenever data 15 not being transferred is used with the CPOL bit to select the desired clock to data relationship The bit in general selects the clock edge that captures data and allows it to change states It has its greatest impact on the first bit transmitted MSB in that it does or does not allow a clock transition before the data capture edge When the SHI is in slave mode and CPHA 0 the SS line must be deasserted and asserted by the external master between each successive word transfer SS must remain asserted between successive bytes within a word The DSP core should write the next data word to HTX when HTDE 1 clearing HTDE However the data is transferred to the shift register for transmission only when SS is deasserted HTDE is set when the data is transferred from HTX to the shift register When the SHI is in slave mode and CPHA 1 the SS line may remain asserted between successive word transfers The SS must remain a
293. eed N 1 ESAI bits service time where N is the number of bits in a slot ESAI Transmit Even Data Occurs when the transmit even slot data interrupt 15 enabled TEDIE 1 at least one ofthe enabled transmit data registers is empty TDE 1 the slot is an even slot TEDE 1 and no exception has occurred TUE 0 or TEIE 0 Writing to all the TX registers of the enabled transmitters or to TSR clears this interrupt request DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 8 44 Freescale Semiconductor Operating Modes 8 ESAI Transmit Data Occurs when the transmit interrupt is enabled TIE 1 at least one of the enabled transmit data registers is empty TDE 1 no exception has occurred TUE 0 or TEIE 0 and no even slot interrupt has occurred TEDE 0 or TEDIE 0 Writing to all the TX registers of the enabled transmitters or to the TSR clears this interrupt request 8 4 4 Operating Modes Normal Network and On Demand The ESAI has three basic operating modes and many data operation formats 8 4 4 1 Normal Network On Demand Mode Selection Selecting between the normal mode and network mode is accomplished by clearing or setting the TMODO TMODI bits in the TCR register for the transmitter section and in the RMODO RMODI bits in the RCR register for the receiver section For normal mode the ESAI functions with one data word of I O per frame per enabled transmitter or receiver The normal mode is typically u
294. egister SFFFF88 TIMER1 Count Register Register Addresses Of TIMER2 EQU EQU EQU EQU EQU EQU SFFFF87 TIMER2 Control Status Register SFFFF86 TIMER2 Load Reg SFFFF85 TIMER2 Compare Register SFFFF84 TIMER2 Count Register SFFFF83 TIMER Prescaler Load Register SFFFF82 TIMER Prescalar Count Register Timer Control Status Register Bit Flags EQU EQU EQU 0 Timer Enable 1 Timer Overflow Interrupt Enable 2 Timer Compare Interrupt Enable SFO Timer Control Mask 0 8 Inverter Bit 9 Timer Restart Mode 11 Direction Bit 12 Data Input 13 Data Output 15 Prescaled Clock Enable DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 B 32 Freescale Semiconductor M TOF EQU 20 M TCF EQU 21 M Timer Prescaler PS EQU 5600000 M PSO EQU 21 M PS1 EQU 22 1 Timer Control Bits M TCO EQU 4 M TCI EQU 5 M EQU 6 M EQU 7 end Timer Overflow Flag Timer Compare Flag Register Bit Flags Prescaler Source Mask Timer Control 0 Timer Control 1 Timer Control 2 Timer Control 3 of ioequ asm DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Equates Freescale Semiconductor B 33 Equates NOTES DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 B 34 Freescale Semiconductor Appendix C JTAG BSDL FILENAME 56366TQF
295. egister Full 0 Wait 1 Read Transmit Data Register Empty 0 Wait 1 Write Transmitter Ready 0 1 Data Not in HI Host Flags Read Only Host Request 0 HOREQ Deasserted 1 Asserted 7 6 5 413 2 1 0 HREQ TRDY RXDF Interrupt Status Register ISR 0 0 2 R W Reset 0 Reserved Program as 0 Figure D 9 Host Interrupt Control and Interrupt Status DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 D 24 Freescale Semiconductor Programming Sheets Application Date Programmer Sheet 5 of 6 HOST 0108 Processor Side 3 R W Reset 0F 7 6 5 413 2 1 0 7 5 Interrupt Vector Register IVR Contains the interrupt vector or number Host Vector Contains Host Command Interrupt Address 2 Host Command Handshakes Executing Host Command Interrupts Command Vector Register CVR 1 R W Reset 32 Contains the host command interrupt address Figure D 10 Host Interrupt Vector and Command Vector DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor D 25 Programming Sheets Application Date Programmer Sheet 6 of 6 HOST HDIO8 Processor Side Host Receive Data HLEND 0 017 Receive Low Byte Receive Middle Byte Receive High Byte Not Used 017 Receive Low Byte Receive Middle Byte Receive High Byte Not Used Receiv
296. eive Control Register RCR 1 The read write Receive Control Register RCR 1 controls the ESAI 1 receiver section 11 10 9 8 7 6 5 4 3 2 1 0 Y FFFF97 _ RSWS1 RSWSO RMOD RMOD RWA RSHFD 2 RE1 REO 23 22 21 20 19 18 17 16 15 14 13 12 RLIE RPR RFSL RSWS4 RSWSS3 RSWS2 Reserved bit read as zero should be written with zero for future compatibility Figure 9 8 RCR 1 Register Hardware and software reset clear all the bits in the 1 register 9 3 6 ESAI 1 Common Control Register SAICR 1 The read write Common Control Register SAICR 1 contains control bits for functions that use both the receive and transmit sections ofthe ESAI 1 11 10 9 8 7 6 5 4 3 2 1 0 23 22 21 20 19 18 17 16 15 14 13 12 p gp p pj Reserved bit read as zero should be written with zero for future compatibility Figure 9 9 SAICR 1 Register Hardware and software reset clear all the bits in the SAICR 1 register 9 3 7 ESAI 1 Status Register SAISR 1 The Status Register SAISR 1 is a read only status register used by the DSP to read the status and serial input flags of the ESAI 1 DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 9 10 Freescale Semiconductor ESAI 1 Programming Model 11 10 9 8 7 6 5 4 3 2 1 0 Y FFFF93 RODF REDF
297. eive Interrupt Enable HRIE 1 0 Bits 13 12 The read write control bits HRIE 1 0 are used to enable the SHI receive data interrupts If HRIE 1 0 are cleared receive interrupts are disabled and the HRNE and HRFF bits 17 and 19 see below status bits must be polled to determine if there is data in the receive FIFO If HRIE 1 0 are not cleared receive interrupts are generated according to Table 7 6 HRIE 1 0 are cleared by hardware and software reset Table 7 6 HCSR Receive Interrupt Enable Bits HRIE 1 0 Interrupt Condition 00 Disabled Not applicable 01 Receive FIFO not empty 1 HROE 0 Receive Overrun Error HROE 1 10 Reserved Not applicable 11 Receive FIFO full HRFF 1 and HROE 0 Receive Overrun Error HROE 1 NOTE Clearing HRIE 1 0 masks a pending receive interrupt only after a one instruction cycle delay If HRIE 1 0 are cleared in a long interrupt service routine it is recommended that at least one other instruction separate the instruction that clears HRIE 1 0 and the RTI instruction at the end of the interrupt service routine 7 4 6 12 Host Transmit Underrun Error HTUE Bit 14 The read only status bit HTUE indicates whether a transmit underrun error occurred Transmit underrun errors can occur only when operating in the SPI slave mode or the slave mode when HCKFR is cleared In a master mode transmission takes place on demand and no underrun can occur H
298. emiconductor 8 39 ESAI Programming Model 8 3 7 ESAI Receive Shift Registers The receive shift registers see Figure 8 13 and Figure 8 14 receive the incoming data from the serial receive data pins Data is shifted in by the selected internal external bit clock when the associated frame sync I O is asserted Data is assumed to be received MSB first if RSHFD 0 and LSB first if RSHFD 1 Data is transferred to the ESAI receive data registers after 8 12 16 20 24 or 32 serial clock cycles were counted depending on the slot length control bits in the RCR register 8 3 8 ESAI Receive Data Registers RX3 RX2 RX1 RX3 RX2 and RXO are 24 bit read only registers that accept data from the receive shift registers when they become full see Figure 8 13 and Figure 8 14 The data occupies the most significant portion of the receive data registers according to the ALC control bit setting The unused bits least significant portion and 8 most significant bits when 1 read as zeros The DSP is interrupted whenever RXx becomes full if the associated interrupt is enabled 8 3 9 ESAI Transmit Shift Registers The transmit shift registers contain the data being transmitted see Figure 8 13 and Figure 8 14 Data is shifted out to the serial transmit data pins by the selected internal external bit clock when the associated frame sync I O is asserted The number of bits shifted out before the shift registers are considered empty an
299. emory on the external memory bus where the external byte wide EPROM is located AARV equ D00409 AAR1 selects the EPROM as CE mapped as P from D00000 to SDFFFFF active low PROMADDR equ SFF1000 Starting PROM address MA EQU 0 MB EQU 1 EQU 2 MD EQU 3 DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor A 3 DSP56366 Bootstrap Program 1 M AAR1 EQU SFFFFF8 Address Attribute Register 1 M OGDB EQU SFFFFFC OnCE GDB Register M HPCR EQU SFFFFCA Host Polarity Control Register HSR EQU SFFFFC3 Host Status Register M HORX EQU SFFFFC6 Host Receive Register HRDF EQU 0 Host Receive Data Full HFO EQU 3 Host Flag 0 HEN EQU 6 Host Enable M HRX EQU SFFFF94 SHI Receive FIFO HCSR EQU SFFFF91 SHI Control Status Register M_HCKR EQU SFFFF90 SHI Clock Control Register HRNE EQU 17 SHI FIFO Not Empty flag HI2C EQU 1 SHI I2C Enable Control Bit HCKFR EQU 4 SHI I2C Clock Freeze Control Bit HFMO EQU 12 SHI I2C Filter Mode Bit 0 1 EQU 13 SHI I2C Filter Mode Bit 1 ORG PL ff0000 PL ff0000 bootstrap code starts at 0000 START movep 0 OGDB enable OnCE nop b NOP instructions needed for test procedure nop nop nop nop clr a 0 r5 clear a and init R5 with 0 jset MD omr OMR1XXX If MD MC MB MA 1xxx go to OMR1XXX jset MC omr SHILD If MD MC MB MA 01xx go load from SHI MB omr EPROMLD If MD MC MB MA 0001 go
300. ence number 00000001110 amp manufacturer identity nnus 1149 1 requirement attribute REGISTER ACCESS of DSP56366 entity is ONCE 8 ENABLE ONCE DEBUG REQUEST attribute BOUNDARY LENGTH of DSP56366 entity is 152 attribute BOUNDARY REGISTER of DSP56366 entity is num cell port func safe ccell dis rslt 0 BC control 1 amp 1 BC 6 500411 bidir X 0 1 Z amp 2 BC 1 MODA input X amp 3 BC 1 MODB input X amp 4 BC 1 MODC input X amp 5 BC 1 MODD input X amp 6 BC 6 D 23 bidir i 15 1 Z amp n BC 6 D 22 bidir X 15 L Z amp B BC 6 D 21 bidir X 15 L Z amp 9 BC 6 D 20 bidir X 15 Ly Z amp 10 BC 6 D 19 bidir X 15 L Z amp 11 BC 6 D 18 bidir X 15 d Z amp 12 BC 6 D 17 bidir X I5 gt 2 amp 13 6 D 16 bidir X I5 15 Z amp 14 BC 6 D 15 bidir X 15 19 Z amp 15 BC 1 control 1 amp 16 BC 6 D 14 bidir X 15 1 Z amp 217 BC 6 D 13 bidir X 15 1 Z amp 18 BC 6 D 12 bidir X T5 HE 2 amp 19 BC 6 D 11 bidir X 28 15 Z amp num cell port func safe ccell dis rslt 20 BC 6 D 10 bidir X 28 gt 2 amp 21 BC 6 D 9 bidir X 28 ds 2 amp 22 BC 6 D 8 bidir X 28 17 Z amp 23 BC 6 D 7 bidir X 28 1 Z amp 24 BC 6 D 6 bidir X 28 1 Z amp 125 BC 6 D 5 bidi
301. er is disabled when the TE bit is cleared Which source clock is used for the prescaler is determined by the PS 1 0 bits of the TPLR Timers 1 and 2 can be clocked by the prescaler clock derived from TIOO 11 3 4 11 TCSR Timer Overflow Flag TOF Bit 20 The TOF bit is set to indicate that counter overflow has occurred This bit is cleared by writing a 1 to the TOF bit Writing a 0 to the TOF bit has no effect The bit is also cleared when the timer overflow interrupt is serviced The TOF bit is cleared by the hardware RESET signal the software RESET instruction the STOP instruction or by clearing the TE bit to disable the timer 11 3 4 12 TCSR Timer Compare Flag Bit 21 The bit is set to indicate that the event count is complete In the timer PWM and watchdog modes the bit is set when N M 1 events have been counted N is the value in the compare register and M is the TLR value In the measurement modes the TCF bit is set when the measurement has been completed The TCF bit is cleared by writing a one into the TCF bit Writing a zero into the TCF bit has no effect The bit is also cleared when the timer compare interrupt is serviced The TCF bit is cleared by the hardware RESET signal the software RESET instruction the STOP instruction or by clearing the TE bit to disable the timer NOTE The TOF and TCF bits are cleared by writing a one to the specific bit In order to assure that only the desir
302. er is loaded with the TLR value on the first timer clock signal received from either the DSP56366 clock divided by two CLK 2 or the prescaler clock output Each subsequent clock signal increments the counter On the next signal transition of the same polarity that occurs on TIOO the TCF bit in the TCSR is set and a compare interrupt is generated if the TCIE bit is set The contents of the counter are loaded into the TCR The TCR then contains the value of the time that elapsed between the two signal transitions on the TIOO signal After the second signal transition if the TRM bit is set the TE bit is set to clear the counter and enable the timer The counter is repeatedly loaded and incremented until the timer is disabled If the TRM bit is cleared the counter continues to be incremented until it overflows This process is repeated until the timer is disabled 1 TE 15 cleared If the counter overflows the TOF bit 15 set and if is set an overflow interrupt is generated The counter contents can be read at any time by reading the TCR 11 4 2 4 Measurement Capture Mode 6 Bit Settings Mode Characteristics TC2 TC1 TCO Mode Name Kind TIOO Clock 0 1 1 0 6 Capture Measurement Input Internal In this mode the timer counts the number of clocks that elapse between starting the timer and receiving an external signal Set the TE bit to clear the counter and enable the timer The v
303. er is loaded with the TLR value on the first timer clock received following the next valid transition occurring on the TIOO input pin and the count is resumed If the TRM bit is cleared the counter continues to be incremented on each timer clock This process is repeated until the timer is disabled i e TE is cleared If the counter overflows the TOF bit is set and if TOIE is set an overflow interrupt is generated The counter contents can be read at any time by reading the TCR DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 11 16 Freescale Semiconductor Timer Modes of Operation 11 4 2 3 Measurement Input Period Mode 5 Bit Settings Mode Characteristics 2 TC1 TCO Mode Name Kind TIOO Clock 0 1 0 1 5 Input Period Measurement Input Internal In this mode the timer counts the period between the reception of signal edges of the same polarity across the TIOO signal Set the TE bit to clear the counter and enable the timer The value the timer is to count is loaded into the TLR The value of the INV bit determines whether the period is measured between consecutive low to high 0 to 1 transitions of TIOO or between consecutive high to low 1 to 0 transitions of TIOO If INV is set high to low signal transitions are selected If INV is cleared low to high signal transitions are selected After the first appropriate transition occurs on the TIOO input pin the count
304. er the data word has been transmitted 2 Ifthe data word is right aligned TWA 1 and zero padding is disabled PADC 0 then the first data bit is repeated before the transmission ofthe data word If zero padding is enabled PADC 1 Zeroes are transmitted before the transmission of the data word 8 3 2 14 TCR Reserved Bit Bits 18 This bit is reserved It reads as zero and it should be written with zero for future compatibility 8 3 2 15 TCR Transmit Section Personal Reset TPR Bit 19 The control bit is used to put the transmitter section of the ESAI in the personal reset state The receiver section is not affected When TPR is cleared the transmitter section may operate normally When TPR is set the transmitter section enters the personal reset state immediately When in the personal reset state the status bits are reset to the same state as after hardware reset The control bits are not affected by the personal reset state The transmitter data pins are tri stated while in the personal reset state if a stable logic level is desired the transmitter data pins should be defined as GPIO outputs or external pull up or pull down resistors should be used The transmitter clock outputs drive zeroes while in the personal reset state Note that to leave the personal reset state by clearing TPR the procedure described in Section 8 6 ESAI Initialization Examples should be followed 8 3 2 16 TCR Transmit Exception Interrupt Enable T
305. erface 1 12 Serial Host Interface SHI 10 1 Serial Peripheral Interface Bus 10 1 SHI 10 1 12 1 Block Diagram 2 Clock Control Register DSP Side 7 Clock Generator 2 3 Control Status Register DSP Side 10 Data Size 11 Exception Priorities 5 HCKR Clock Phase and Polarity Controls 7 Divider Modulus Select 9 Prescaler Rate Select 9 HCKR Filter Mode 9 HCSR Bus Error Interrupt Enable 13 FIFO Enable Control 12 Host Request Enable 12 Idle 13 Master Mode 12 Serial Host Interface P C SPI Selection 11 Serial Host Interface Mode 11 SHI Enable 10 Host Receive Data FIFO DSP Side 6 Host Transmit Data Register DSP Side 6 HREQ Function In SHI Slave Modes 12 HSAR Slave Address 7 Slave Address Register 6 I O Shift Register 6 Input Output Shift Register Host Side 5 Internal Architecture 2 Internal Interrupt Priorities 5 Interrupt Vectors 5 Introduction 1 Operation During Stop 25 Programming Considerations 19 Programming Model 3 Programming Model DSP Side 4 Programming Model Host Side 3 Slave Address Register DSP Side 6 SHI Noise Reduction Filter Mode 10 signal groupings 1 signals 1 Size register SZ 6 SP 6 SPI 10 1 HCSR Bus Error 16 Host Busy 16 Host Receive FIFO Full 15 Host Receive FIFO Not Empty 15 Host Receive Overrun Error 15 Host Transmit Data Empty 15 Host Transmit Underrun Error 14 Receive Interrupt Enable 13 14 Master Mode 20 Slave Mode 19 SPI Data To Clock Timing 8 SPI Data To Clock Timing Diagra
306. es I HIO8TX EQU VEC 62 Host Transmit Data Empty I HIO8CM EQU I_VEC S64 Host Command Default I ESAIIRD EQU 570 ESAI 1 Receive Data I_ESAI1RED EQU I 572 ESAI 1 Receive Even Data I_ESAI1RDE EQU I 574 ESAI 1 Receive Data With Exception Status I_ESAI1RLS EQU I 576 ESAI 1 Receive Last Slot I ESAIITD EQU 578 ESAI 1 Transmit Data I ESAIITED EQU I 57 ESAI 1 Transmit Even Data I ESAIITDE EQU I 57 ESAI 1 Transmit Data With Exception Status I_ESAI1TLS EQU I 57 ESAI 1 Transmit Last Slot INTERRUPT ENDING ADDRESS I INTEND EQU I_VEC SFF last address of interrupt vector space k k k k k k k k Kk k k ec KOK K e ke K he e ke he he e ke he K e ke he he e ke he he e ke he K e ke he he e ke he he e ke he he e ke he he e ke he he e ke he he e e ke ke e e e 7 EQUATES for DSP56366 I O registers and ports Last update August 23 2000 k k k k k k k k Kk k KOK k ke ke K KOK K he e K KOK e ke he K e ke KOK e K he he e ke he he e ke K he e ke he UK K ke he K e ke K he e K KOK e ke hehe e e K ke e R k page 132 55 0 0 0 opt mex ioequ ident 1 0 DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 B 4 Freescale Semiconductor Equates EQUATES for I O Port Programming Register Addresses M HDR EQU SFFFFC9 Host port GPIO data Register M HDDR EQU SFFFFC8 Host port GPIO direc
307. escale Semiconductor Programming Sheets Application Date G Port C ESAI 23 11 40 9 Port C Control Register H Pct1 10 Pcs Pcs Pc7 Pce Pcs SPTPTTTTTETE Programmer Sheet 2 of 4 X FFFFBF Read Write Reset 0 E Reserved Program as 0 1 10 9 8 4 3 2 1 23 Port C Direction Register H PDC41 PDC10 PDC8 PDC6 PDC5 PDC4 PDC3 PDC2 PARC H ip TTT wn PT Read Write Reset 0 Reserved Program as 0 PCn 0 amp PDCn 0 Port pin PCn disconnected PCn 1 amp PDCn 0 Port pin PCn configured as input PCn 0 amp PDCn 1 Port pin PCn configured as output PCn 1 amp PDCn 1 gt Port pin configured as ESAI Read Write Reset undefined 23 Port GPIO Data Register H PD11 PD10 PD8 07 PD6 PD5 PD4 JH SCTTTETTTTTEET X FFFFBD E Reserved Program as 0 If port pin n is GPIO input then PDn reflects the value on port pin n if port pin n is GPIO output then value written to PDn is reflected on port pin n Figure D 34 GPIO Port C DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor D 49 Programming Sheets Application Date G p Port DAX Port D Control Register PCRD X FFFFD7 Read Write Reset 0 Programmer Sheet 3 of 4 Port D Direction Register PRRD X FFFFD6 Read Write Reset DES Reserved Prog
308. escale Semiconductor 11 19 Timer Modes of Operation 11 4 4 Watchdog Toggle Mode 10 Bit Settings Mode Characteristics 2 TC1 TCO Mode NAME Kind TIOO Clock 1 0 1 0 10 Toggle Watchdog Output Internal In this mode the timer generates an interrupt at a preset rate Timer 0 also toggles the output on TIOO Set the TE bit to clear the counter and enable the timer The value the timer is to count is loaded into the TPCR The counter is loaded with the TLR value on the first timer clock received from either the DSP56366 internal clock divided by two CLK 2 or the prescaler clock output Each subsequent timer clock increments the counter The TIOO signal is set to the value of the INV bit When the counter equals the value in the TCPR the TCF bit in the TCSR is set and a compare interrupt is generated if the TCIE bit is also set If the TRM bit is set the counter is loaded with the TLR value on the next timer clock and the count is resumed If the bit is cleared the counter continues to be incremented on each subsequent timer clock When counter overflow has occurred the polarity of the TIOO output pin is inverted the TOF bit in the TCSR is set and an overflow interrupt is generated if the TOIE bit is also set The TIOO polarity is determined by the INV bit The counter is reloaded whenever the TLR is written with a new value while the TE bit is set This process is repeated until t
309. ess where loading started The Host Interface bootstrap load program may be stopped by setting the Host Flag 0 This will start execution of the loaded program from the specified starting address The base address of the HDIO8 in multiplexed mode is 0x80 and is not modified by the bootstrap code All the address lines are enabled and should be connected accordingly If MD MC MB MA 1111 then it loads the program RAM from the Host Interface programmed to operate in the MC68302 IMP bus mode in single strob pin configuration The HOST MC68302 bootstrap code expects accesses that are byte wide The HOST MC68302 bootstrap code expects to read 3 bytes forming a 24 bit word Specifying the number of program words 3 bytes forming a 24 bit word Specifying the address to start loading the program words and then 3 bytes forming 24 bit words for each program word to be loaded The program words will be stored in contiguous PRAM memory locations Starting at the specified starting address After reading the program words program execution starts from the same address where loading started The Host Interface bootstrap load program may be stopped by setting the Host Flag 0 This will start execution of the loaded program from the specified starting address page 132 55 0 0 0 opt cex mex mu GENBRALS EQUATES BOOT equ D00000 this is the location in P m
310. et state while all ESAI pins are programmed as GPIO or disconnected and is active only if at least one of the ESAI I O pins is programmed as an ESAI pin 8 4 2 ESAI Initialization The correct way to initialize the ESAI is as follows 1 Hardware software ESAI individual or STOP reset 2 Program ESAI control and time slot registers 3 Write data to all the enabled transmitters 4 Configure at least one pin as ESAI pin During program execution all ESAI pins may be defined as GPIO or disconnected causing the ESAI to stop serial activity and enter the individual reset state All status bits of the interface are set to their reset state however the control bits are not affected This procedure allows the DSP programmer to reset the ESAI separately from the other internal peripherals During individual reset internal DMA accesses to the data registers of the ESAI are not valid and data read is undefined The DSP programmer must use an individual ESAI reset when changing the ESAI control registers except for RLIE TIE RIE 0 5 REO RE3 to ensure proper operation of the interface NOTE If the ESAI receiver section is already operating with some of the receivers enabling additional receivers on the fly 1 e without first putting the ESAI receiver in the personal reset state by setting their REx control bits will result in erroneous data being received as the first data word for the newly ena
311. ext data transfer As a result the master device sends clock pulses for the full data word transfer HREQ is deasserted by the external slave device at the first clock pulse of the next data transfer When deasserted HREQ prevents the clock generation of the next data word transfer until it is asserted again Connecting DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 7 23 SHI Programming Considerations the HREQ line between two SHI equipped DSPs one operating as master device and the other as an slave device enables full hardware handshaking 7 7 41 Receive Data in 2 Master Mode A receive session is initiated if the R W direction bit of the transmitted slave device address byte is set Following a receive initiation data in the SDA line is shifted into IOSR MSB first Following each received byte an acknowledge 0 is sent at the ninth clock pulse via the SDA line if the HIDLE control bit is cleared Data is acknowledged bytewise as required by the PC bus protocol and is transferred to the HRX FIFO when the complete word according to HM 1 0 15 filled into IOSR It is the responsibility of the programmer to select the correct number of bytes in an frame so that they fit in a complete number of words For this purpose the slave device address byte does not count as part of the data therefore it is treated separately If the slave transmitte
312. for output and RCKD 0 for input Flag 1 FSR is enabled when the pin is not configured as external transmitter buffer enable TEBE 0 and its direction is selected by RFSD RFSD 1 for output and RFSD 0 for input Flag 2 HCKR pin direction is selected by RHCKD RHCKD 1 for output and RHCKD 0O for input When programmed as input flags the SCKR FSR and HCKR logic values respectively are latched at the same time as the first bit of the receive data word 1s sampled Because the input was latched the signal on the input flag pin SCKR FSR or HCKR can change without affecting the input flag until the first bit of the next receive data word When the received data words are transferred to the receive data registers the input flag latched values are then transferred to the IFO IF1 and IF2 bits in the SAISR register where they may be read by software When programmed as output flags the SCKR FSR and HCKR logic values are driven by the contents of the OFO 1 and OF2 bits in the SAICR register respectively and are driven when the transmit data registers are transferred to the transmit shift registers The value on SCKR FSR and HCKR is stable from the time the first bit ofthe transmit data word is transmitted until the first bit of the next transmit data word is transmitted Software may change the OF0 OF2 values thus controlling the FSR and HCKR pin values for each transmitted word The normal sequence for setting output flags whe
313. frame to be transmitted immediately after the 15 enabled is the beginning of a block and therefore it has a 7 preamble This is followed by the second subframe which has an preamble After that X and preambles are transmitted alternately until the end of the block transfer 192 frames transmitted See Figure 10 4 for an illustration of the preamble sequence DAX Enabled Here Z gt Y gt X gt Y X gt Y gt X gt Y gt Z gt Y gt gt X gt Y First Block 3884 subframes Second Block Figure 10 4 Preamble sequence 0609 10 5 11 DAX Clock Multiplexer The DAX clock multiplexer selects one of the clock sources and generates the biphase clock 128 x Fs and shift clock 64 x Fs The clock source can be selected from the following options see also Section 10 5 6 4 DAX Clock Input Select XCS 1 0 Bits 3 4 DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 10 9 DAX Programming Considerations The internal DSP core clock assumes 1024 x Fs DAX clock input pin ACI S512 x Fs e clock input pin 384 x Fs e DAX clock input pin ACI 256 x Fs Figure 10 5 shows how each clock is divided to generate the biphase and bit shift clocks DSP Core Clock 1 4 1024 x Fs ACI Pin Biph 256 384 512 X Fs Clock 128 x Fs Bit Shift XCS1 or XCSO Code 64 Fs XCS1 XCSO
314. frequency divided by 4 The value of the INV bit in the TCSR determines whether low to high 0 to 1 transitions or high to low 1 to 0 transitions increment the counter If the INV bit is set high to low transitions increment the counter If the INV bit is cleared low to high transitions increment the counter When the counter matches the value contained in the TCPR the TCF bit in the TCSR is set and a compare interrupt is generated if the TCIE bit is set If the bit 15 set the counter is loaded with the value of the TLR when the next timer clock is received and the count is resumed If TRM bit is cleared the counter continues to be incremented on each timer clock This process is repeated until the timer is disabled 1 TE is cleared If the counter overflows the TOF bit is set and if TOIE is set an overflow interrupt is generated The counter contents can be read at any time by reading the TCR DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 11 15 Timer Modes of Operation 11 4 2 Signal Measurement Modes The following signal measurement modes are provided Measurement input width Measurement input period Measurement capture These functions are available only on timer 0 11 4 2 1 Measurement Accuracy The external signal is synchronized with the internal clock used to increment the counter This synchronization process can cause the number of clocks measured for t
315. ft register 4 When 4 is set and a frame sync is detected the transmit 4 portion of the ESAI is enabled for that frame When TE4 is cleared the transmitter 4 is disabled after completing transmission of data currently in the ESAI transmit shift register Data can be written to TX4 when TE4 is cleared but the data is not transferred to the transmit shift register 4 DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 8 14 Freescale Semiconductor ESAI Programming Model The SDO4 SDII pin is the data input pin for RX1 if TE4 is cleared and REI in register is set If both and are cleared the transmitter and receiver are disabled and the pin is tri stated Both REI and 4 should not be set at the same time The normal mode transmit enable sequence is to write data to one or more transmit data registers before setting TEx The normal transmit disable sequence is to clear TEx TIE and TEIE after TDE equals one In the network mode the operation of clearing TE4 and setting it again disables the transmitter 4 after completing transmission of the current data word until the beginning of the next frame During that time period the SDO4 SDI pin remains in the high impedance state The on demand mode transmit enable sequence can be the same as the normal mode or 4 can be left enabled 8 3 2 6 TCR ESAI Transmit 5 Enable TE5 Bit 5 TES enables the transfer of data from TX5 to the transmit shift re
316. generate the addresses It implements four types of arithmetic linear modulo multiple wrap around modulo and reverse carry The AGU operates in parallel with other chip resources to minimize address generation overhead The AGU is divided into two halves each with its own Address ALU Each Address ALU has four sets of register triplets and each register triplet is composed of an address register an offset register and a modifier register The two Address ALUS are identical Each contains a 24 bit full adder called an offset adder A second full adder called a modulo adder adds the summed result of the first full adder to a modulo value that is stored in its respective modifier register A third full adder called a reverse carry adder is also provided The offset adder and the reverse carry adder are in parallel and share common inputs The only difference between them is that the carry propagates in opposite directions Test logic determines which of the three summed results of the full adders is output Each Address ALU can update one address register from its respective address register file during one instruction cycle The contents ofthe associated modifier register specifies the type of arithmetic to be used in the address register update calculation The modifier value is decoded in the Address ALU 1 4 3 Program Control Unit PCU The PCU performs instruction prefetch instruction decoding hardware DO loop control and except
317. gh Frequency Clock Direction RHCKD Bit 23 The Receiver High Frequency Clock Direction RHCKD bit selects the source of the receiver high frequency clock when in the asynchronous mode SYN 0 and the IF2 OF2 flag direction in the synchronous mode SYN 1 In the asynchronous mode when RHCKD is set the internal clock generator becomes the source of the receiver high frequency clock and is the output on the HCKR pin In the asynchronous mode when RHCKD is cleared the receiver high frequency clock source is external the internal clock generator is disconnected from the HCKR pin and an external clock source may drive this pin When RHCKD is cleared HCKR is an input when RHCKD is set HCKR is an output In the synchronous mode when RHCKD is set the HCKR pin becomes the OF2 output flag If RHCKD is cleared then the HCKR pin becomes the IF2 input flag See Table 8 1 and Table 8 9 Table 8 9 HCKR Pin Definition Table Control Bits HCKR PIN SYN RHCKD 0 0 HCKR input 0 1 HCKR output 1 0 IF2 1 1 OF2 8 3 4 ESAI Receive Control Register RCR The read write Receive Control Register RCR controls the ESAI receiver section Interrupt enable bits for the receivers are provided in this control register The receivers are enabled in this register 0 1 2 or 3 receivers can be enabled if the input data pin is not used by a transmitter Operating modes are also selected in this register
318. gister 5 When TES is set and a frame sync is detected the transmit 5 portion of the ESAI is enabled for that frame When TES is cleared the transmitter 5 is disabled after completing transmission of data currently in the ESAI transmit shift register Data can be written to TX5 when TES is cleared but the data is not transferred to the transmit shift register 5 The SDOS SDIO pin is the data input pin for RXO if TES is cleared and REO in register is set If both REO and TES are cleared the transmitter and receiver are disabled and the pin is tri stated Both REO and 5 should not be set at the same time The normal mode transmit enable sequence is to write data to one or more transmit data registers before setting TEx The normal transmit disable sequence is to clear TEx TIE and TEIE after TDE equals one In the network mode the operation of clearing 5 and setting it again disables the transmitter 5 after completing transmission of the current data word until the beginning of the next frame During that time period the SDOS SDIO pin remains in the high impedance state The on demand mode transmit enable sequence can be the same as the normal mode or 5 be left enabled 8 3 2 7 TCR Transmit Shift Direction TSHFD Bit 6 The TSHFD bit causes the transmit shift registers to shift data out MSB first when TSHFD equals zero LSB first when TSHFD equals one see Figure 8 13 and Figure 8 14 8 3 2 8 TCR Tran
319. gnored when the SHI operates in the slave mode except for when HCKFR is set The HRS bit is cleared during hardware reset and software reset NOTE Use the equations in the SHI datasheet to determine the value of HRS for the specific serial clock frequency required 7 4 5 3 HCKR Divider Modulus Select HDM 7 0 Bits 10 3 The HDM 7 0 bits specify the divide ratio of the clock generator divider A divide ratio between 1 and 256 HDM 7 0 00 to SFF may be selected When the SHI operates in the slave mode the HDM 7 0 bits are ignored except for when is set The HDM 7 0 bits are cleared during hardware reset and software reset NOTE Use the equations in the SHI datasheet to determine the value of HDM 7 0 for the specific serial clock frequency required 7 4 5 4 HCKR Reserved Bits Bits 23 14 11 These bits in HCKR are reserved They are read as zero and should be written with zero for future compatibility 7 4 5 5 HCKR Filter Mode HFM 1 0 Bits 13 12 The read write control bits HFM 1 0 specify the operational mode of the noise reduction filters as described in Table 7 3 The filters are designed to eliminate undesired spikes that might occur on the clock and data in lines and allow the SHI to operate in noisy environments when required One filter is located in the input path of the SCK SCL line and the other is located in the input path of the data line 1 e the SDA line when in mode
320. grammed as an output this signal can serve as a high frequency sample clock e g for external DACs or as an additional system clock Port C 5 When the ESAI is configured as GPIO this signal is individually programmable as input output or internally disconnected The default state after reset is GPIO disconnected This input is 5 V tolerant FSR PC1 Input or output Input output or disconnected GPIO disconnected Frame Sync for Receiver This is the receiver frame sync input output signal In the asynchronous mode SYN 0 the FSR pin operates as the frame sync input or output used by all the enabled receivers In the synchronous mode SYN 1 it operates as either the serial flag 1 pin TEBE 0 or as the transmitter external buffer enable control 1 RFSD 1 When this pin is configured as serial flag pin its direction is determined by the RFSD bit in the RCCR register When configured as the output flag OF1 this pin will reflect the value of the OF1 bit in the SAICR register and the data in the OF1 bit will show up at the pin synchronized to the frame sync in normal mode or the slot in network mode When configured as the input flag IF1 the data value at the pin will be stored in the IF1 bit in the SAISR register synchronized by the frame sync in normal mode or the slot in network mode Port C 1 When the ESAI is configured as GPIO this signal is individually programmable as inpu
321. h This function is available only on timer 0 Set the TE bit to clear the counter and enable the timer The value the timer is to count is loaded into the TPCR When first timer clock 15 received from either the DSP56366 internal clock divided by two CLK 2 or the prescaler clock output the counter is loaded with the TLR value Each subsequent timer clock increments the counter When the counter equals the value in the TCPR the TIOO output pin is toggled and the TCF bit in the TCSR is set The contents of the counter are placed into the TCR Ifthe TCIE bit is set a compare interrupt is generated The counter continues to be incremented on each timer clock If counter overflow has occurred the TIOO output pin 15 toggled the TOF bit in TCSR is set and an overflow interrupt is generated if the bit is set If the bit is set the counter is loaded with the TLR value on the next timer clock and the count is resumed If the TRM bit is cleared the counter continues to be incremented on each timer clock This process is repeated until the timer is disabled by clearing the TE bit TIOO signal polarity is determined by the value of the INV bit When the counter is started by setting the TE bit the TIOO signal assumes the value ofthe INV bit On each subsequent toggling of the TIOO signal the polarity ofthe TIOO signal is reversed For example if the INV bit is set the TIOO signal generates the following signal 1010 If the INV bit
322. hardware reset The contents of the Bootstrap ROM are defined by the Bootstrap ROM source code in Appendix A Bootstrap ROM Contents 3 1 4 Dynamic Memory Configuration Switching The internal memory configuration is altered by re mapping RAM modules from Y and X data memory into program memory space and vice versa The contents of the switched RAM modules are preserved The memory can be dynamically switched from one configuration to another by changing the MS MSWO or MSWI bits in OMR The address ranges that are directly affected by the switch operation are specified in Table 3 2 The memory switch can be accomplished provided that the affected address ranges are not being accessed during the instruction cycle in which the switch operation takes place Accordingly the following condition must be observed for trouble free dynamic switching NOTE No accesses including instruction fetches to or from the affected address ranges in program and data memories are allowed during the switch cycle NOTE The switch cycle actually occurs 3 instruction cycles after the instruction that modifies the MS MSWO MSWI bits Any sequence that complies with the switch condition is valid For example if the program flow executes in the address range that 1s not affected by the switch the switch condition can be met very easily In this case a switch can be accomplished by just changing the MS MSWO MSW bits in OMR in the regular program flow
323. have their register files programmed to the addresses in the internal X I O memory range the top 128 locations of the X data memory space and internal Y I O memory range 48 locations of the Y data memory space as shown in Table 3 4 Table 3 4 Internal Memory Peripheral Address Register Name IPR X FFFFFF INTERRUPT PRIORITY REGISTER CORE X FFFFFE PRIORITY REGISTER PERIPHERAL IPR P PLL X FFFFFD PLL CONTROL REGISTER PCTL ONCE X FFFFFC ONCE GDB REGISTER OGDB BIU X FFFFFB BUS CONTROL REGISTER BCR X FFFFFA DRAM CONTROL REGISTER DCR X FFFFF9 ADDRESS ATTRIBUTE REGISTER 0 AARO X FFFFF8 ADDRESS ATTRIBUTE REGISTER 1 AAR1 X FFFFF7 ADDRESS ATTRIBUTE REGISTER 2 AAR2 X FFFFF6 ADDRESS ATTRIBUTE REGISTER AAR3 pin not available X FFFFF5 ID REGISTER IDR DMA X FFFFF4 DMA STATUS REGISTER DSTR X FFFFF3 DMA OFFSET REGISTER 0 DORO X FFFFF2 DMA OFFSET REGISTER 1 DOR1 X FFFFF1 DMA OFFSET REGISTER 2 DOR2 X FFFFFO DMA OFFSET REGISTER 3 DOR3 DMAO X FFFFEF SOURCE ADDRESS REGISTER DSRO X FFFFEE DMA DESTINATION ADDRESS REGISTER DDRO X SFFFFED DMA COUNTER X FFFFEC DMA CONTROL REGISTER DCRO DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 3 12 Freescale Semiconductor Table 3 4 Internal Memory Map continued
324. he DA Gee ates 8 42 PERC ERE DEO ae Md 8 48 eT e Pa e E Ue esten ada a qus CT CS 8 48 Register akana stem s UA S 8 49 ESAI vie Tee D basi pha uu tatus 9 2 EMUXE RSSISIeE Sra de SORS ah d a ds 9 5 I Register K hoo a usq aqa reatu 9 6 ESAI 1 Clock Generator Functional Block Diagram 9 7 ESAI 1 Frame Sync Generator Functional Block Diagram 9 8 TOR o usn beatas do apr tete taco Fata Obl a td 9 8 L Register xs tie E pe LEE 9 9 RER V RG det qfi Xu gt d ticis 9 10 SAICR JORGOISIQE 44 Dee cor prat e MENU S dba a 9 10 Ep SLE Pa E Edi dte edu e 9 11 DSP56366 24 Bit Digital Signal Processor Rev 4 LOF 2 Freescale Semiconductor Figure9 11 TSMA 1 R gistet vet qna Mia Sng YEARS 9 12 Fipure9 12 2 acea accu aos 9 12 Pipure9 I129 TiRGgister c oro CEPR EO ER RR RE Ep uu E Ee pb is 9 13 Fig re 9 14 I R gister ned bg ees aa tet ud PERMITS 9
325. he GPIO port signals which are multiplexed with the ESAI signals Port E signals are the GPIO port signals which are multiplexed with the ESAI_1 signals Port D signals are the GPIO port signals which are multiplexed with the DAX signals Freescale Semiconductor 2 1 Signal Groupings ON CHIP EMULATION PORT A ADDRESS BUS 0 17 S VCCA 8 GNDA 4 gt PORT A DATA BUS 00 023 lt gt VCCD 4 GNDD 4 PORT A BUS CONTROL AAO0 AA2 RASO RAS2 RD WR amp BR BG VCCC 2 gt GNDC 2 P INTERRUPT AND MODE CONTROL MODA IRQA MODB IRQB MODC IRQC MODD IRQD RESET PLL AND CLOCK EXTAL PINIT NMI PCAP VCCP GNDP QUIET POWER VCCQH 3 VCCQL 4 gt GNDQ 4 SPDIF TRANSMITTER DAX ADO PD1 4 ACI PDO TIMER 0 TIOO TIO g gt DSP56366 Port B Port C Port E Port D anaes JTAG PORT TDO TMS PARALLEL HOST PORT HDIOS8 gt HAD 7 0 7 lt HAS HAO 8 lt 1 PB9 lt PB10 i PB11 HDS HWR PB12 lt lt HCS HA10 PB13 PB14 PB15 VCCH SERIAL
326. he RCKD bit in the RCCR register When configured as the output flag this pin will reflect the value of the OFO bit in the SAICR register and the data in the OFO bit will show up at the pin synchronized to the frame sync in normal mode or the slot in network mode When configured as the input flag IFO the data value at the pin will be stored in the IFO bit in the SAISR register synchronized by the frame sync in normal mode or the slot in network mode Port E 0 When the ESAI is configured as GPIO this signal is individually programmable as input output or internally disconnected The default state after reset is GPIO disconnected This input cannot tolerate 5 V SCKT 1 PES Input or output Input output or disconnected GPIO disconnected Transmitter Serial Clock 1 This signal provides the serial bit rate clock for the ESAI SCKT is a clock input or output used by all enabled transmitters and receivers in synchronous mode or by all enabled transmitters in asynchronous mode Port E 3 When the ESAI is configured as GPIO this signal is individually programmable as input output or internally disconnected The default state after reset is GPIO disconnected This input cannot tolerate 5 V 5005 1 SDIO 1 6 Output Input Input output or disconnected GPIO disconnected Serial Data Output 5 1 When programmed as a transmitter SDO5 is used to transmit data from th
327. he SPI Slave mode this signal is used to enable the SPI slave for transfer When configured for the SPI master mode this signal should be kept deasserted pulled high If it is asserted while configured as SPI master a bus error condition is flagged If SS is deasserted the SHI ignores SCK clocks and keeps the MISO output signal in the high impedance state Slave Address 2 This signal uses a Schmitt trigger input when configured for the 2 mode When configured for the IC Slave mode the HA2 signal is used to form the slave device address is ignored in the IC master mode This signal is tri stated during hardware software and individual reset Thus there is no need for an external pull up in this state This input is 5 V tolerant Input or Output Tri stated Host Request This signal is an active low Schmitt trigger input when configured for the master mode but an active low output when configured for the slave mode When configured for the slave mode HREQ is asserted to indicate that the SHI is ready for the next data word transfer and deasserted at the first clock pulse of the new data word transfer When configured for the master mode HREQ is an input When asserted by the external slave device it will trigger the start of the data word transfer by the master After finishing the data word transfer the master will await the next assertion of HREQ to proceed to the next transfer
328. he Serial Host Interface SHI The SHI operates in the SPI slave mode with 24 bit word width The bootstrap code expects to read a 24 bit word specifying the number of program words a 24 bit word specifying the address to start loading the program words and then a 24 bit word for each program word to be loaded The program words will be stored in contiguous PRAM memory locations starting at the specified starting address After reading the program words program execution starts from the same address where loading started DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 4 5 Interrupt Priority Registers Mode 6 Mode 7 Mode 8 Mode 9 Mode A Mode B Mode C Mode D Mode E Mode F 4 4 Table 4 3 DSP56366 Mode Descriptions Same as Mode 5 except SHI interface operates in the 2 slave mode with HCKFR set to 1 and the 100ns filter enabled Same as Mode 5 except SHI interface operates in the 2 slave mode with HCKFR set to 0 The DSP starts fetching instructions beginning at address 008000 Memory accesses are performed using SRAM memory access type with 31 wait states and no address attributes selected Reserved Used for Burn In testing Reserved Reserved Instructions are loaded through the HDIO8 which is configured to interface with an ISA bus The HOST ISA bootstrap code expects to read a 24 bit word specifying the number of program words a 24 bit word specifying the address
329. he XCA bit is transmitted as the thirty first bit Bit 30 of the channel A subframe in the next frame 10 5 4 4 DAX Channel B Validity XVB Bit 13 The value of the XVB bit is transmitted as the twenty ninth bit Bit 28 of the channel B subframe in the next frame 10 5 4 5 DAX Channel B User Data XUB Bit 14 The value of the XUB bit is transmitted as the thirtieth bit Bit 29 of the channel B subframe in the next frame 10 5 4 6 DAX Channel B Channel Status XCB Bit 15 The value of the XCB bit is transmitted as the thirty first bit Bit 30 of the channel B subframe in the next frame 10 5 4 7 XNADR Reserved Bits Bits 0 9 16 23 These XNADR bits are reserved They read as 0 and should be written with 0 to ensure compatibility with future device versions 10 5 5 Non Audio Data Buffer XNADBUF The XNADBUF is 3 bit register that temporarily holds channel B non audio data X VB and XCB for the current transmission while the channel A data is being transmitted This mechanism provides programmers more instruction cycles to store the next frame s non audio data to the XCB XUB XVB XUA and bits in the XNADR The data in the XNADBUF register is transferred to the XADSR along with the contents of the XADBUF register at the beginning of channel B transmission NOTE The XNADBUF register is not directly accessible by DSP instructions 10 5 6 DAX Control Register XCTR The XCTR is a 24 bit read wri
330. he host processor When the host reads the receive byte register at host address 7 the RXDF bit is cleared 6 6 6 Transmit Byte Registers TXH TXM TXL The transmit byte registers are viewed as three 8 bit write only registers by the host processor These registers are the transmit high register TXH the transmit middle register and the transmit low register TXL These registers send data to the high middle and low bytes respectively of the HORX register and are selected by the external host address inputs 2 and HAO during a host processor write operation If the HLEND bit in the ICR is cleared the TXH is located at address 5 TXM at 6 and TXL at 7 If the HLEND bit in the ICR is set the TXH is located at address 7 TXM at 6 and TXL at 5 Data may be written into the transmit byte registers when the transmit data register empty TXDE bit is set The host processor may program the TREQ bit to assert the external HOREQ HTRQ signal when TXDE is set This informs the host processor that the transmit byte registers are empty Writing to the data register at host address 7 clears the TXDE bit The contents of the transmit byte registers are transferred as 24 bit data to the HORX register when both TXDE and the HRDF bit are cleared This transfer operation sets and HRDF DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 6 26 Freescale Semiconductor HDIO8 External Host Programmer s Model
331. he selected signal value to vary from the actual signal value by plus or minus one counter clock cycle 11 4 2 2 Measurement Input Width Mode 4 Bit Settings Mode Characteristics TC3 TC2 TC1 TCO Mode Name Kind TIOO Clock 0 1 0 0 4 Input Width Measurement Input Internal In this mode the timer 0 counts the number of clocks that occur between opposite edges of an input signal Set the TE bit to clear the counter and enable the timer Load the timer s count value into the TLR After the first appropriate transition as determined by the INV bit occurs on the TIOO input pin the counter is loaded with the TLR value on the first timer clock signal received either from the DSP56366 clock divided by two CLK 2 or from the prescaler clock input Each subsequent clock signal increments the counter If the INV bit is set the timer starts on the first high to low 1 to 0 signal transition on the TIOO signal If the INV bit is cleared the timer starts on the first low to high 0 to 1 transition on the TIOO signal When the first transition opposite in polarity to the INV bit setting occurs on the TIOO signal the counter stops The TCF bit in the TCSR is set and a compare interrupt is generated if the TCIE bit is set The value of the counter which measures the width of the TIOO pulse is loaded into the TCR The TCR can be read to determine the external signal pulse width If the TRM bit is set the count
332. he timer is disabled by clearing the TE bit The counter contents can be read at any time by reading the TCR register NOTE In this mode internal logic preserves the TIOO value and direction for an additional 2 5 internal clock cycles after the DSP56366 hardware RESET signal is asserted This ensures that a valid RESET signal is generated when the TIOO signal is used to reset the DSP56366 11 4 5 Reserved Modes Modes 8 11 12 13 14 and 15 are reserved 11 4 6 Special Cases The following special cases apply during wait and stop state 11 4 6 1 Timer Behavior during Wait Timer clocks are active during the execution of the WAIT instruction and timer activity is undisturbed If a timer interrupt is generated the DSP56366 leaves the wait state and services the interrupt DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 11 20 Freescale Semiconductor Timer Modes of Operation 11 4 6 2 Timer Behavior during Stop During the execution of the STOP instruction the timer clocks are disabled timer activity is stopped and the TIOO signal is disconnected Any external changes that happen to the TIOO signal is ignored when the DSP56366 is the stop state To ensure correct operation the timers should be disabled before the DSP56366 is placed into the stop state 11 4 7 DMA Trigger Each timer can also be used to trigger DMA transfers For this to occur a DMA channel must be programmed to be triggered by a timer e
333. host communication protocol implemented in both the DSP and the host processor software 6 5 3 5 HCR Host DMA Mode Control Bits HDMO HDM1 HDM2 Bits 5 7 The HDM 2 0 bits are used to enable the HDIO8 DMA mode operation The HDI08 DMA mode supports external DMA controller devices connected to the HDIOS8 on the Host side This mode should not be confused with the operation of the on chip DMA controller With HDM 2 0 cleared the HDIOS does not support DMA mode operation and the TREQ and RREQ control bits are used for host processor interrupt control via the external HOREQ output signal or HRREQ and HTREQ output signals if HDREQ in the ICR is set Also in the non DMA mode the HACK input signal is used for the MC68000 Family vectored interrupt acknowledge input If HDM 2 0 are not all cleared the HDIOS operates as described in Table 6 5 Table 6 5 HDN 2 0 Functionality HDM Mode 2 1 0 Description ICR 0 0 0 DMA operation disabled INIT HLEND HF1 HDRQ TREQ RREQ 1 O 0 DMA Operation Enabled the ICR to enable DMA transfers DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 6 8 Freescale Semiconductor HDIO8 DSP Side Programmer s Model Table 6 5 HDM 2 0 Functionality continued HDM Mode 2 1 0 Description ICR 0 0 1 DMA Mode Data Output Transfers Enabled 24 Bit words
334. ial flag pin its direction is determined by the RCKD bit in the RCCR register When configured as the output flag this pin will reflect the value of the OFO bit in the SAICR register and the data in the OFO bit will show up at the pin synchronized to the frame sync in normal mode or the slot in network mode When configured as the input flag IFO the data value at the pin will be stored in the IFO bit in the SAISR register synchronized by the frame sync in normal mode or the slot in network mode Port C 0 When the ESAI is configured as GPIO this signal is individually programmable as input output or internally disconnected The default state after reset is GPIO disconnected This input is 5 V tolerant SCKT Input or output Input output or disconnected GPIO disconnected Transmitter Serial Clock This signal provides the serial bit rate clock for the ESAI SCKT is a clock input or output used by all enabled transmitters and receivers in synchronous mode or by all enabled transmitters in asynchronous mode Port C 3 When the ESAI is configured as GPIO this signal is individually programmable as input output or internally disconnected The default state after reset is GPIO disconnected This input is 5 V tolerant DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 2 16 Freescale Semiconductor Enhanced Serial Audio Interface Table 2 11 Enhanced Serial
335. ication Date 23 22 21 20 19 18 17 16 15 14 13 12 11109 8 7 6 5 4 3 2 1 O0 Programmer Sheet 3 of 3 Timer Reload Value Timer Load Register TLRO FFFF8E Write Only TLR1 FFFF8A Write Only TLR2 FFFF86 Write Only Reset XXXXXX 23 22 21 20 19 18 17 16 15 14 13 12 11 40 9 8 7 6 5 4 3 2 1 0 Value Compared to Counter Value Timer Compare Register TCPRO FFFF8D Read Write TCPR1 FFFF89 Read Write TCPR2 FFFF85 Read Write Reset XXXXXX 23 22 21 20 19 18 17 16 15 14 13 12 41 40 9 8 7 6 5 4 3 2 1 0 Timer Count Value Timer Count Register TCRO FFFF8C Read Only TCR1 FFFF88 Read Only TCR2 FFFF84 Read Only Reset 000000 Figure D 32 Timer Load Compare and Count Registers DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor D 47 Programming Sheets Application Date Port B 0108 Programmer Sheet 1 of 4 Host Data 15 14 1 1 Direction Register DR15 DR14 DR13 DR12 DR11 DR10 HDDR X FFFFC8 Read Write Reset 0 DRx 1 is Output DRx 0 PBx is Input Host Data 15 11 Register D15 013 012 011 010 HDR X FFFFC9 Reset Undefined Dx holds value of corresponding HDI08 GPIO pin Function depends on HDDR See the HDIO8 HPCR Register Figure D 8 for additional Port B GPIO control bits Figure D 33 GPIO Port B DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 D 48 Fre
336. ider determines the word transfer rate one word 15 transferred per frame sync during the frame sync time slot as shown in Figure 8 6 In network mode it is possible to transfer a word for every time slot as shown in Figure 8 6 For more details see Section 8 4 Operating Modes In order to comply with AC 97 specifications RSWS4 RSWSO should be set to 00011 20 bit slot 20 bit word RFSL and RFSR should be cleared and RDC4 RDCO should be set to 0C 13 words in frame Table 8 10 ESAI Receive Network Mode Selection RMOD1 RMODO RDC4 RDCO Receiver Network Mode 0 0 0 1F Normal Mode 0 1 0 On Demand Mode 0 1 1 1F Network Mode 1 0 X Reserved 1 1 0C AC97 8 3 4 9 Receiver Slot and Word Select RSWS4 RSWSO Bits 10 14 RSWS4 RSWS0 bits are used to select the length of the slot and the length of the data words being received via the ESAI The word length must be equal to or shorter than the slot length The possible combinations are shown in Table 8 11 See also the ESAI data path programming model in Figure 8 13 and Figure 8 14 DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 8 28 Freescale Semiconductor ESAI Programming Model Table 8 11 ESAI Receive Slot and Word Length Selection RSWS4 RSWS3 RSWS2 RSWS1 RSWSO SLOT LENGTH WORD LENGTH
337. igh M SHL EQU sc SHI Interrupt Priority Level Mask M_SHLO EQU 2 SHI Interrupt Priority Level low M_SHL1 EQU 3 SHI Interrupt Priority Level high M_HDL EQU 30 HDIO8 Interrupt Priority Level Mask M_HDLO EQU 4 HDIO8 Interrupt Priority Level low M_HDL1 EQU 5 HDIO8 Interrupt Priority Level high M_DAL EQU 5 0 DAX Interrupt Priority Level Mask M DALO EQU 6 DAX Interrupt Priority Level low DAL1 EQU 7 DAX Interrupt Priority Level high M TAL EQU 300 Timer Interrupt Priority Level Mask M TALO EQU 8 Timer Interrupt Priority Level low M TAL1 EQU 9 Timer Interrupt Priority Level high M ESIL EQU 5 00 ESAI 1 Interrupt Priority Level Mask M ESL10 EQU 0 ESAI 1 Interrupt Priority Level low M ESL11 EQU 1 ESAI 1 Interrupt Priority Level high EQUATES for Direct Memory Access DMA DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor B 7 Equates Register Addresses O DMA M DSTR EQU SFFFFF4 DMA Status Register M DORO EQU SFFFFF3 DMA Offset Register 0 M DORI EQU SFFFFF2 DMA Offset Register 1 M DOR2 EQU SFFFFF1 DMA Offset Register 2 M DOR3 EQU SFFFFFO DMA Offset Register 3 Register Addresses Of DMAO DSRO EQU SFFFFEF DMAO Source Address Register M DDRO EQU SFFFFEE DMAO Destination Address Register M_DCOO EQU SFFFFED DMAO Counter M DCRO EQU SFFFFEC DMAO Control Register Register Addresses Of DMA1
338. il a stop event is detected When operating in the slave SPI mode HBUSY is set while SS is asserted When operating in the master SPI mode HBUSY is set if the HTX register is not empty or if the IOSR is not empty HBUSY is cleared otherwise HBUSY is cleared by hardware reset software reset SHI individual reset and during the stop state 7 5 Characteristics Of The SPI Bus The SPI bus consists of two serial data lines MISO and MOSTI a clock line SCK and a Slave Select line SS During an SPI transfer a byte is shifted out one data pin while a different byte is simultaneously shifted in through a second data pin It can be viewed as two 8 bit shift registers connected together in a circular manner with one shift register on the master side and the other on the slave side Thus the data bytes in the master device and slave device are exchanged The MISO and MOSI data pins are used for transmitting and receiving serial data When the SPI is configured as a master MISO is the master data input line and MOSI is the master data output line When the SPI is configured as a slave device MISO is the slave data output line and MOSI is the slave data input line Clock control logic allows a selection of clock polarity and a choice of two fundamentally different clocking protocols to accommodate most available synchronous serial peripheral devices When the SPI is configured as a master the control bits in the HCKR select the appropriate clock rate
339. in 5002 1 5013 1 9 3 9 2 4 Serial Transmit 3 Receive 2 Data PIn SDO3 1 5012 1 9 3 9 2 5 Serial Transmit 4 Receive 1 Data Pin 5004 1 5011 1 9 3 9 2 6 Serial Transmit 5 Receive 0 Data Pin 5005 1 5010 1 9 4 9 2 7 Receiver Serial Clock SCKR 1 9 4 9 2 8 Transmitter Serial Clock SCKT 1 9 4 9 2 9 Frame Sync for Receiver FSR utem be EP a S PIDE Ree ds 9 4 9 2 10 Frame Sync for Transmitter 1 9 4 03 ESAL T Programming Model Ca adie caute SN de 9 4 9 3 1 ESAI 1 Multiplex Control Register EMUXR 9 5 9 3 2 ESAI 1 Transmitter Clock Control Register _1 9 5 9 3 2 1 TCCR 1 Tx High Freq Clock Divider Bits 14 17 9 6 9 3 2 2 TCCR 1 Tx High Freq Clock Polarity 20 9 6 9 3 2 3 TCCR 1 Tx High Freq Clock Direction THCKD 23 9 6 9 3 3 ESAI 1 Transmit Control Register TCR 1 9 8 9 3 4 ESAI 1 Receive Clock Control Register 1 9 9 9 3 4 1 RCCR 1 Rx High Freq Clock Divider RFP3 RFPO Bits 14 17 9 9
340. individually programmed as input output or internally disconnected The default state after reset for this signal is GPIO disconnected This input is 5 V tolerant DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor Serial Host Interface Table 2 9 Host Interface continued Signal Name Type PM HACK Input GPIO HACK HRRQ Output HRRQ PB15 Input output or disconnected Signal Description Host Acknowledge When HDIO8 is programmed to interface a single disconnected host request host bus and the HI function is selected this signal is the host acknowledge HACK Schmitt trigger input The polarity of the host acknowledge is programmable but is configured as active low HACK after reset Receive Host Request When 0108 is programmed to interface a double host request host bus and the HI function is selected this signal is the receive host request HRRQ output The polarity of the host request is programmable but is configured as active low HRRQ after reset The host request may be programmed as a driven or open drain output Port B 15 When the HDIO8 is configured as GPIO this signal is individually programmed as input output or internally disconnected The default state after reset for this signal is GPIO disconnected This input is 5 V tolerant 2 8 Serial Host Interface The SHI has five I O signals that can
341. ing hardware reset and software reset 7 4 6 6 HCSR Master Mode HMST Bit 6 The read write control bit HMST determines the SHI operating mode If HMST is set the interface operates in the master mode If HMST is cleared the interface operates in the slave mode The SHI supports a single master configuration in both and SPI modes When configured as an SPI master the SHI drives the SCK line and controls the direction of the data lines MOSI and MISO The SS line must be held deasserted in the SPI master mode if the SS line is asserted when the SHI is in SPI master mode a bus error is generated the HCSR HBER bit is set see Section 7 4 6 18 Host Bus Error 1 21 When configured as an master the SHI controls the bus by generating start events clock pulses and stop events for transmission and reception of serial data It is recommended that an SHI individual reset be generated HEN cleared before changing HMST HMST is cleared during hardware reset and software reset 7 4 6 7 HCSR Host Request Enable HRQE 1 0 Bits 8 7 The read write control bits HRQE 1 0 are used to control the HREQ When HRQE 1 0 are cleared the HREQ pin is disabled and held in the high impedance state If either of HRQE 1 0 are set and the SHI is in a master mode the HREQ pin becomes an input controlling SCK deasserting HREQ suspends SCK If either of HRQE 1 0 are set and the SHI is in a slave mode HREQ becomes an
342. ins Disconnected 1 GPIO Pin Enable Host Address Line 8 Enable 0 GPIO 1 HA8 HA8 Host Address Line 9 Enable 0 GPIO 1 HA9 Host Chip Select Enable 0 E HCS HAIO GPIO 1 HCS HA10 HCS if HMUX 0 1 AE HCS HA10 HC10 if HMUX 1 Host Request Enable 0 E HOREQ HACK GPIO 1 HOREQ HOREQ if HDRQ 0 Host Acknowledge Enable 0 HACK GPIO If 4 HREN 1 HACK HACK Host Enable 0 HDIO8 Disable Pins GPIO 1 HDIO8 Enable Figure D 8 Host Base Address and Host Port Control DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor D 23 Programming Sheets Application Date Programmer Sheet 4 of 6 HOST HDIO8 Processor Side Receive Request Enable DMA Off 0 Interrupts Disabled 1 Interrupts Enabled DMA On 0 Host gt DSP 1 DSP gt Host Transmit Request Enable DMA Off 0 Interrupts Disabled 1 Interrupts Enabled DMA On 0 gt Host 1 Host DSP HOREQ HTRQ HOREQ HACK HTRQ HRRQ Host Flags Write Only Host Little Endian Initialize Write Only 0 No Action 1 Initialize 2 4 0 HDN 2 0 000 HDRQ TREQ For HM 1 0 bits see Table 6 12 in Section 6 HDM 2 0 100 TREQ RREQ HDM1 and or HDMO 1 TREQ RREQ Interrupt Control Register ICR 0 R W eset 0 Receive Data R
343. interrupts are disabled 6 5 3 3 HCR Host Command Interrupt Enable HCIE Bit 2 The HCIE bit is used to enable the host command interrupt request When the host command pending HCP status bit in the HSR is set a host command interrupt request occurs if HCIE is set If HCIE is cleared HCP interrupts are disabled The interrupt address is determined by the host command vector register CVR NOTE Host interrupt request priorities If more than one interrupt request source is asserted and enabled e g HRDF 1 HCP 1 HRIE 1 and HCIE 1 the HDIOS generates interrupt requests according to the following table DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 6 7 HDIO8 DSP Side Programmer s Model Table 6 4 HDI08 IRQ Priority Interrupt Source Highest Host Command 1 Transmit Data HTDE 1 Lowest Receive Data HRDF 1 6 5 3 4 HCR Host Flags 2 3 HF2 HF3 Bits 3 4 HF2 and HF3 bits are used as a general purpose flags for DSP to host communication HF2 and HF3 may be set or cleared by the DSP core HF2 and HF3 are reflected in the interface status register ISR on the host side such that if they are modified by the DSP software the host processor can read the modified values by reading the ISR These two flags are not designated for any specific purpose but are general purpose flags They can be used individually or as encoded pairs in a simple DSP to
344. iods 8 2 9 Frame Sync for Receiver FSR FSR is a bidirectional pin providing the receivers frame sync signal for the ESAI interface The direction of this pin is determined by the RFSD bit in RCR register In the asynchronous mode SYN 0 the FSR pin operates as the frame sync input or output used by all the enabled receivers In the synchronous mode SYN 1 it operates as either the serial flag 1 pin TEBE 0 or as the transmitter external buffer enable control TEBE 1 RFSD 1 For further information on pin mode and definition see Table 8 8 and on receiver clock signals see Table 8 1 When this pin is configured as serial flag pin its direction is determined by the RFSD bit in the RCCR register When configured as the output flag this pin reflects the value of the OF1 bit in the SAICR register and the data in the bit shows up at the pin synchronized to the frame sync being used by the transmitter and receiver sections When configured as the input flag the data value at the pin is stored in the IF1 bit in the SAISR register synchronized by the frame sync in normal mode or the slot in network mode FSR may be programmed as a general purpose I O pin PC1 when the ESAI FSR function is not being used DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 8 6 Freescale Semiconductor ESAI Programming Model 8 2 10 Frame Sync for Transmitter FST FST is a bidirectional pin providing the frame sync f
345. ion processing The PCU implements a seven stage pipeline and controls the different processing states of the DSP56300 core The PCU consists of the following three hardware blocks Program decode controller PDC Program address generator PAG Program interrupt controller PIC The PDC decodes the 24 bit instruction loaded into the instruction latch and generates all signals necessary for pipeline control The PAG contains all the hardware needed for program address generation system stack and loop control The PIC arbitrates among all interrupt requests internal interrupts as well as the five external requests IRQA IRQB IRQC IRQD and NMI and generates the appropriate interrupt vector address PCU features include the following Position independent code support Addressing modes optimized for DSP applications including immediate offsets On chip instruction cache controller On chip memory expandable hardware stack DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 1 5 DSP56300 Core Functional Blocks Nested hardware DO loops Fast auto return interrupts The PCU implements its functions using the following registers PC program counter register SR Status register LA loop address register LC loop counter register VBA vector base address register SZ stack size register SP stack pointer OMR operating mode register
346. is already full HRFF is set When a receive overrun error occurs the shift register is not transferred to the FIFO If a receive interrupt occurs with HROE set the receive overrun interrupt vector is generated If a receive interrupt occurs with HROE cleared the regular receive data interrupt vector is generated HROE is cleared by reading the HCSR with HROE set followed by reading HRX HROE is cleared by hardware reset software reset SHI individual reset and during the stop state DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 7 15 Characteristics Of The SPI Bus 7 4 6 18 Host Bus Error HBER Bit 21 The read only status bit HBER indicates when set that an SHI bus error occurred when operating as a master HMST set In mode HBER is set if the transmitter does not receive an acknowledge after a byte 1s transferred then a stop event is generated and transmission is suspended In SPI mode HBER is set if SS is asserted then transmission is suspended at the end of transmission ofthe current word HBER is cleared only by hardware reset software reset SHI individual reset and during the stop state 7 4 6 19 HCSR Host Busy HBUSY Bit 22 The read only status bit HBUSY indicates that the bus is busy when in the mode or that SHI itself is busy when in the SPI mode When operating in the mode HBUSY is set after the SHI detects a start event and remains set unt
347. is programmed to interface a multiplexed host bus and the HI function is selected this signal is the host address strobe HAS Schmitt trigger input The polarity of the address strobe is programmable but is configured active low HAS following reset PB8 Input output or Port B 8 When the HDIO8 is configured as GPIO this signal is individually disconnected programmed as input output or internally disconnected The default state after reset for this signal is GPIO disconnected This input is 5 V tolerant HA1 Input GPIO Host Address Input 1 When the HDIO8 is programmed to interface disconnected nonmultiplexed host bus and the HI function is selected this signal is line 1 of the host address HA1 input bus HA8 Input Host Address 8 When HDI08 is programmed to interface a multiplexed host bus and the HI function is selected this signal is line 8 of the host address HA8 input bus PB9 Input output or Port B 9 When the HDIO8 is configured as GPIO this signal is individually programmed as input output or internally disconnected The default state after reset for this signal is GPIO disconnected This input is 5 V tolerant DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor PARALLEL HOST INTERFACE HDIO8 Table 2 9 Host Interface continued Signal Name HA2 Type Input HA9 Input PB10 Input Output or Disconnected State d
348. isconnected This input cannot tolerate 5 V FST 1 4 Input or output Input output or disconnected GPIO disconnected Frame Sync for Transmitter 1 This is the transmitter frame sync input output signal For synchronous mode this signal is the frame sync for both transmitters and receivers For asynchronous mode FST is the frame sync for the transmitters only The direction is determined by the transmitter frame sync direction TFSD bit in the ESAI transmit clock control register TCCR Port E 4 When the ESAI is configured as GPIO this signal is individually programmable as input output or internally disconnected The default state after reset is GPIO disconnected This input cannot tolerate 5 V DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 2 19 Enhanced Serial Audio Interface 1 Table 2 12 Enhanced Serial Audio Interface 1 Signals continued Signal Name SCKR 1 PEO Signal Type Input or output Input output or disconnected State during Reset GPIO disconnected Signal Description Receiver Serial Clock 1 SCKR provides the receiver serial bit clock for the ESAI The SCKR operates as a clock input or output used by all the enabled receivers in the asynchronous mode SYN 0 or as serial flag 0 pin in the synchronous mode SYN 1 When this pin is configured as serial flag pin its direction is determined by t
349. ister TPCR 11 3 3 1 TPCR Prescaler Counter Value PC 20 0 Bits 20 0 These 21 bits contain the current value of the prescaler counter 11 3 3 2 TPCR Reserved Bits 23 21 These reserved bits are read as zero and should be written with zero for future compatibility 11 3 4 Timer Control Status Register TCSR The TCSR is a 24 bit read write register controlling the timer and reflecting its status 11 341 TCSR Timer Enable TE Bit 0 The timer enable TE bit is used to enable or disable the timer Setting TE enables the timer and clears the timer counter The counter starts counting according to the mode selected by the timer control TC 3 0 bit values DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 11 6 Freescale Semiconductor Timer Event Counter Programming Model Clearing the TE bit disables the timer The TE bit is cleared by the hardware RESET signal or the software RESET instruction NOTE When timer 0 is disabled and TIOO is not in GPIO mode the pin is tri stated To prevent undesired spikes on TIOO when Timer 0 is switched from tri state to an active state TIOO should be tied to the power supply with a pullup or pulldown resistor 11 3 4 Timer Overflow Interrupt Enable TOIE Bit 1 The TOIE bit is used to enable the timer overflow interrupts Setting TOIE enables overflow interrupt generation The timer counter can hold a maximum value of FFFFFF When the counter value is at the maximum
350. k divided by two CLK 2 or the prescaler clock output Each subsequent timer clock increments the counter When the counter matches the value of the TCPR the TCF bit in the TCSR is set and a compare interrupt is generated if the TCIE bit is also set If the bit is set the counter 15 loaded with the TLR value on the next timer clock and the count is resumed If the TRM bit 15 cleared the counter continues to be incremented on each subsequent timer clock This process is repeated until the timer is disabled 1 TE 15 cleared If the counter overflows the TOF bit is set and if is set an overflow interrupt is generated Timer 0 also generates an output pulse on the TIOO signal with a pulse width equal to the timer clock period The pulse polarity is determined by the value of the INV bit If the INV bit is set the pulse polarity is high logical 1 If the INV bit is cleared the pulse polarity is low logical 0 The counter contents can be read at any time by reading the TCR The counter is reloaded whenever the TLR is written with a new value while the TE bit is set NOTE In this mode internal logic preserves the TIOO value and direction for an additional 2 5 internal clock cycles after the DSP56366 hardware RESET signal is asserted This ensures that a valid RESET signal is generated when the TIOO signal is used to reset the DSP56366 DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Fre
351. l 6 5 5 2 HBAR Reserved Bits 8 15 These bits are reserved They read as zero and should be written with zero for future compatibility HAD 0 7 Latch A 3 7 HAS HA 8 10 Chip select Base Address 8 bits register DSP Peripheral data bus COMPARATOR BA 3 7 Figure 6 5 Self Chip Select logic 6 5 6 Host Port Control Register HPCR The HPCR is a 16 bit read write control register used by the DSP to control the HDI08 operating mode The initialization values for the HPCR bits are described in Section 6 5 9 DSP Side Registers After Reset The HPCR bits are described in the following paragraphs 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HRP HCSP HDDS HASP HDSP HROD HEN HAEN HREN HABEN HGEN Reserved bit Read as 0 Should be written with 0 for future compatibility Figure 6 6 Host Port Control Register HPCR X FFFFC4 NOTE To assure proper operation of the HDI08 the HPCR bits HAP HCSP HDDS HMUX HASP HDSP HROD HAEN and HREN should be changed only if HEN is cleared Also the HPCR bits HAP HRP HCSP HDDS HMUX HASP HDSP HROD HAEN HREN HCSEN HA9EN and HASEN should not be set when HEN is set or simultaneously with setting HEN 6 5 6 1 HPCR Host GPIO Port Enable HGEN Bit 0 If the HGEN bit is set pins configured GPIO are enabled If this bit
352. l pull up pull down resistors until the signals are configured for operation The registers cleared are the HPCR HDDR HDR Selection between GPIO and HDIOS is made by clearing HPCR bits 6 through 1 GPIO or setting these bits for HDIO8 functionality If the HDI08 is in GPIO mode HDDR configures each corresponding signal in the HDR as an input signal if the HDDR bit is cleared or as an output signal if the HDDR bit is set see Section 6 5 7 Data direction register HDDR and Section 6 5 8 Host Data Register HDR DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 6 27 Servicing The Host Interface 6 7 Servicing The Host Interface The HDIOS can be serviced by using one of the following protocols Polling Interrupts 6 7 1 HDIOS8 Host Processor Data Transfer To the host processor the HDIOS8 appears as a contiguous block of static RAM To transfer data between itself and the HDIO8 the host processor performs the following steps 1 Asserts the HDIOS address to select the register to be read or written 2 Selects the direction of the data transfer If it is writing the host processor drives the data on the bus 3 Strobes the data transfer 6 7 2 Polling In the polling mode of operation the HOREQ HTRQ signal is not connected to the host processor and HACK must be deasserted to ensure IVR data is not being driven on H0 H7 when other registers are being polled The
353. l 2 Interrupt DMA Channel 3 Interrupt DMA Channel 4 Interrupt DMA Channel 5 Interrupt ESAI Receive Data with Exception Status ESAI Receive Even Data ESAI Receive Data ESAI Receive Last Slot ESAI Transmit Data with Exception Status ESAI Transmit Last Slot ESAI Transmit Even Data ESAI Transmit Data SHI Bus Error SHI Receive Overrun Error SHI Transmit Underrun Error SHI Receive FIFO Full SHI Transmit Data SHI Receive FIFO Not Empty HOST Command Interrupt HOST Receive Data Interrupt DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 D 10 Freescale Semiconductor Table D 3 Interrupt Sources Priorities Within an IPL continued Interrupt Source Priorities within an IPL Priority Interrupt Source HOST Transmit Data Interrupt DAX Transmit Underrun Error DAX Block Transferred DAX Transmit Register Empty TIMERO Overflow Interrupt TIMERO Compare Interrupt TIMER1 Overflow Interrupt TIMER1 Compare Interrupt 2 Overflow Interrupt TIMER2 Compare Interrupt ESAI 1 Receive Data with Exception Status 5 1 Receive Even Data ESAI 1 Receive Data 5 1 Receive Last Slot ESAI 1 Transmit Data with Exception Status ESAI 1 Transmit Last Slot ESAI 1 Transmit Even Data Lowest ESAI 1 Transmit Data DSP56366 24
354. l A is written to XADR and moves to XADBUFA Then channel B is written to XADR and when XADBUFB empties XADR moves into it XADBUFA moves to the shift register XADSR when XADSR has shifted out its last bit After channel A audio and non audio data has been shifted out XADBUFB moves into XADSR and channel B audio and non audio shift begins The frame non audio data stored in XNADR is transferred to the XADSR for channel A and to the XNADBUF registers for channel B at the beginning of a frame transmission This is called an upload The DAX audio data register empty XADE flag is set when XADR and XADBUFA are empty and if the audio data register empty interrupt is enabled XDIE 1 an interrupt request is sent to the DSP core The interrupt handling routine then sends the non audio data bits to XNADR and the next frame of audio data to XADR two subframes At the beginning of a frame transmission one of the 8 bit channel A preambles Z preamble for the first subframe in a block or X preamble otherwise is generated in the preamble generator and then shifted out to the ADO pin in the first eight time slots The preamble is generated in biphase mark format The twenty four audio and three non audio data bits in the XADSR are shifted out to the biphase encoder which shifts them out through the ADO pin in the biphase mark format in the next 54 time slots The parity generator calculates an even parity over the 27 bits of audio and non audio
355. l Audio Transmitter DA X 1 serial transmitter capable of supporting the SPDIF IEC958 CP 340 and AES EBU digital audio formats Pins of unused peripherals except SHI may be programmed as GPIO lines 144 pin plastic TQFP package 1 3 DSP56366 Audio Processor Architecture This section defines the DSP56366 audio processor architecture The audio processor is composed of the following units The DSP56300 core is composed of the Data ALU Address Generation Unit Program Controller Instruction Cache Controller DMA Controller PLL based clock oscillator Memory Module Interface Peripheral Module Interface and the On Chip Emulator OnCE The DSP56300 core is described in the document DSP56300 24 Bit Digital Signal Processor Family Manual Freescale publication DSP56300FM Memory modules Peripheral modules The peripheral modules are defined in the following sections Memory sizes in the block diagram are defaults Memory may be differently partitioned according to the memory mode of the chip See Section 1 4 8 On Chip Memory for more details about memory size 1 4 DSP56300 Core Functional Blocks The DSP56300 core provides the following functional blocks Data arithmetic logic unit Data ALU Address generation unit AGU Program control unit PCU Businterface unit BIU DMA controller with six channels DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 1 3
356. l Processor User Manual Rev 4 Freescale Semiconductor Serial Host Interface Table 2 10 Serial Host Interface Signals continued Signal Name State during Signal Type Reset Signal Description MISO Input or output Tri stated SPI Master In Slave Out When the SPI is configured as a master MISO is the master data input line The MISO signal is used in conjunction with the MOSI signal for transmitting and receiving serial data This signal is a Schmitt trigger input when configured for the SPI Master mode an output when configured for the SPI Slave mode and tri stated if configured for the SPI Slave mode when SS is deasserted An external pull up resistor is not required for SPI operation SDA Input or Data and Acknowledge In 2 mode SDA is a Schmitt trigger input open drain when receiving and an open drain output when transmitting SDA should be output connected to through a pull up resistor SDA carries the data for 2 transactions The data SDA must be stable during the high period of SCL The data in SDA is only allowed to change when SCL is low When the bus is free SDA is high The SDA line is only allowed to change during the time SCL is high in the case of start and stop events A high to low transition of the SDA line while SCL is high is a unique situation and is defined as the start event A low to high transition of SDA while SCL is high is a unique situation defined as th
357. l Signal Processor User Manual Rev 4 10 14 Freescale Semiconductor 11 Timer Event Counter 11 1 Introduction This section describes the internal timer event counter in the DSP56366 Each ofthe three timers timer 0 1 and 2 can use internal clocking to interrupt the DSP56366 or trigger transfers after a specified number of events clocks In addition timer 0 provides external access via the bidirectional signal TIOO When the TIOO pin is configured as an input timer 0 can count or capture events or measure the width or period of an external signal When TIOO is configured as an output timer 0 can function as a timer a watchdog timer or a pulse width modulator TIOO can also function as a GPIO signal 11 2 Timer Event Counter Architecture The timer module is composed of a common 21 bit prescaler and three independent general purpose 24 bit timer event counters each having its own register set 11 2 1 Timer Event Counter Block Diagram Figure 11 1 shows a block diagram of the timer event counter This module includes a 24 bit timer prescaler load register TPLR a 24 bit timer prescaler count register TPCR a 21 bit prescaler clock counter and three timers Each of the three timers may use the prescaler clock as its clock source DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 11 1 Timer Event Counter Architecture GDB 24 24 TPCR 24 Timer Prescaler Timer Presca
358. le Generator DAX State Control DAX Machine Signals Clocks DSP Core Clock Figure 10 1 Digital Audio Transmitter DAX Block Diagram 10 2 Signals The DAX has two signal lines DAX Digital Audio Output ADO PD1 The ADO pin sends audio and non audio data in the AES EBU CP340 and IEC958 formats in a biphase mark format The ADO pin may also be used as a GPIO pin PD1 if the DAX is not operational DAX Clock Input ACI PD0 When the DAX clock is configured to be supplied externally the external clock is applied to the ACI pin The frequency of the external clock must be 256 times 384 times or 512 times the audio sampling frequency 256 x Fs 384 x Fs or 512 x Fs The ACI pin may also be used as a GPIO pin PDO when the DAX is disabled or when operating from the internal DSP clock 10 3 DAX Functional Overview The DAX consists of the following Audio data register XADR Two audio data buffers XADBUFA and XADBUFB Non audio data register XNADR Non audio data buffer XNADBUF Audio and non audio data shift register XADSR Control register XCTR Status register XSTR DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 10 2 Freescale Semiconductor DAX Programming Model e Parity generator PRTYG Preamble generator encoder Clock multiplexer Control state machine XADR XADBUFA XADBUFB and XADSR creates a FIFO like data path Channe
359. ler Load Register Count Register Timer 0 21 bit Prescaler Timer 1 Counter Timer 2 CLK 2 TIOO 0673 Figure 11 1 Timer Event Counter Block Diagram 11 2 2 Individual Timer Block Diagram Figure 11 2 shows the structure of an individual timer module The three timers are identical in structure but only timer 0 is externally accessible Each timer includes a 24 bit counter a 24 bit read write timer control and status register TCSR a 24 bit read only timer count register TCR a 24 bit write only timer load register TLR a 24 bit read write timer compare register TCPR and logic for clock selection and interrupt DMA trigger generation The timer mode is controlled by the TC 3 0 bits ofthe timer control status register TCSR Timer modes are described in Section 11 4 Timer Modes of Operation DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 11 2 Freescale Semiconductor Timer Event Counter Programming Model GDB 24 Control Status Load Count Compare Register Register Register Register 24 24 24 Timer Control Counter Logic Timer interrupt DMA request TIO 2 prescaler CLK Timer 0 only AA0676 Figure 11 2 Timer Block Diagram 11 3 Timer Event Counter Programming Model The DSP56366 views each timer as a memory mapped peripheral with four registers occupying four 24 bit words in the X data memory space Either standard polled or interrupt programming techniques can
360. lock generation of the next data word transfer until it is asserted again Connecting the HREQ line between two SHI equipped DSPs one operating as an SPI master device and the other as an SPI slave device enables full hardware handshaking if 1 For 0 HREQ should be disabled by clearing HRQE 1 0 7 7 53 IC Slave Mode The slave mode is entered by enabling the SHI HEN 1 selecting the mode 1 and selecting the slave mode of operation HMST 0 In this operational mode the contents of HCKR are ignored When configured in the slave mode the SHI external pins operate as follows SCK SCL is the SCL serial clock input MISO SDA is the SDA open drain serial data line MOSI HAO is the HAO slave device address input SS HA2 is the HA2 slave device address input HREQ is the Host Request output When the SHI is enabled and configured in the slave mode the SHI controller inspects the SDA and SCL lines to detect a start event Upon detection of the start event the SHI receives the slave device address byte and enables the slave device address recognition unit If the slave device address byte was not identified as its personal address the SHI controller fails to acknowledge this byte by not driving low the SDA line at the ninth clock pulse 1 However it continues to poll the SDA and SCL lines to detect a new start event If the personal slave device address was co
361. lot TFS is set at the start of the first time slot in the frame and cleared during all other time slots Data written to a transmit data register during the time slot when TFS is set is transmitted in network mode if the transmitter is enabled DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 8 36 Freescale Semiconductor ESAI Programming Model during the second time slot in the frame TFS is useful in network mode to identify the start of a frame TFS is cleared by hardware software ESAI individual or STOP reset TFS is valid only if at least one transmitter is enabled i e one or more of TE TE2 TE4 and TES are set NOTE In normal mode TFS always reads as a one when transmitting data because there is only one time slot per frame the frame sync time slot 8 3 6 11 X SAISR Transmit Underrun Error Flag TUE Bit 14 TUE 15 set when at least one of the enabled serial transmit shift registers is empty no new data to be transmitted and a transmit time slot occurs When a transmit underrun error occurs the previous data which is still present in the TX registers that were not written is retransmitted If TEIE is set an ESAI transmit data with exception underrun error interrupt request is issued when TUE is set Hardware software ESAI individual and STOP reset clear TUE TUE is also cleared by reading the SAISR with TUE set followed by writing to all the enabled transmit data registers or
362. ly synchronized to the internal clock and its frequency should be lower than the internal operating frequency divided by 4 CLK 4 To ensure proper operation the TC 3 0 bits should be changed only when the timer is disabled when the TE bit in the TCSR has been cleared DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 11 7 Timer Event Counter Programming Model Table 11 2 Timer Control Bits for Timer 0 Bit Settings Mode Characteristics TC Mone Mode Function TIO0 Clock 0 0 0 0 0 Timer and GPIO GPIO Internal 0 0 0 1 1 Timer pulse Output Internal 0 0 1 0 2 Timer toggle Output Internal 0 0 1 1 3 Event counter Input External 0 1 0 0 4 Input width measurement Input Internal 0 1 0 1 5 Input period measurement Input Internal 0 1 1 0 6 Capture event Input Internal 0 1 1 1 7 Pulse width modulation Output Internal 1 0 0 0 8 Reserved 1 0 0 1 9 Watchdog pulse Output Internal 1 0 1 0 10 Watchdog toggle Output Internal 1 0 1 1 11 Reserved 1 1 0 0 12 Reserved 1 1 0 1 13 zm 1 1 1 0 14 Reserved m 1 1 1 1 15 Reserved 1 The GPIO function is enabled only if all of the TC 3 0 bits are zero Table 11 3 Timer Control Bits for Timers 1 and 2 TC3 TC2 TC1 TCO Clock Mode 0 0 0 0 Internal Timer 0 0 0 1 Reserved 0 0 1 X Reserved 0
363. m Lists related documentation needed to use this chip and describes the organization of this manual SECTION 2 SIGNAL CONNECTION DESCRIPTIONS Describes the signals on the DSP56366 pins and how these signals are grouped into interfaces SECTION 3 MEMORY CONFIGURATION Describes the DSP56366 memory spaces RAM and ROM configuration memory configurations and their bit settings and memory maps SECTION 4 CORE CONFIGURATION Describes the registers used to configure the DSP56300 core when programming the DSP56366 in particular the interrupt vector locations and the operation of the interrupt priority registers Explains the operating modes and how they affect the processor s program and data memories SECTION 5 GENERAL PURPOSE INPUT OUTPUT GPIO Describes the DSP56366 GPIO capability and the programming model for the GPIO signals operation registers and control DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor SECTION 6 HOST INTERFACE HDIO8 Describes the HDIOS parallel host interface SECTION 7 SERIAL HOST INTERFACE SHI Describes the serial input output interface providing a path for communication and program coefficient data transfers between the DSP and an external host processor The SHI can also communicate with other serial peripheral devices SECTION 8 ENHANCED SERIAL AUDIO INTERFACE ESAI Describes one of the full duplex serial port for serial co
364. m 8 SPI Mode 1 SR register 6 SRAM interfacing 8 SS 6 Stack Counter register SC 6 Stack Pointer SP 6 Status Register SR 6 System Stack SS 6 SZ register 6 T TAP 7 DSP56366 24 Bit Digital Signal Processor Rev 4 Index 4 Freescale Semiconductor TCO TC3 bits 7 TCF 11 TCIE bit 7 TCPR 12 TCR 12 TCSR register 6 bit 0 Timer Enable bit TE 6 bit 2 Timer Compare Interrupt Enable bit TCIE 7 bits 4 7 Timer Control bits TC0 TC3 7 bit 13 Data Output bit DO 10 reserved bits bits 3 10 14 16 19 22 23 11 TE bit 6 Test Access Port TAP 7 Timer 1 22 timer special cases 20 Timer GPIO 2 Timer Compare Interrupt Enable bit TCIE 7 Timer Control bits TC0 TC3 7 Timer Control Status Register TCSR 6 Timer Enable bit TE 6 timer mode mode 0 GPIO 13 mode 1 timer pulse 14 mode 2 timer toggle 14 mode 3 timer event counter 15 mode 4 measurement input width 16 mode 5 measurement input period 17 mode 6 measurement capture 17 mode 7 pulse width modulation 18 mode 8 reserved 19 mode 9 watchdog pulse 19 20 modes 1 15 reserved 20 Timer module architecture 1 Timer Prescaler Count Register TPCR 6 Timer Prescaler Load Register TPLR 5 TLR 12 TOF 11 TOIE 7 TPCR register 6 bits 0 20 Prescaler PCO PC20 6 bit 21 23 bits 6 Counter Value bits reserved bits bits 21 23 6 TPLR register 5 bits 0 20 PLO PL20 5 bits 21 22 Pres
365. mand Effect Cn od ox Ie ed 6 23 Host Request Status HREO si od exuere Sata SES E Re ed aa tea 6 25 Host Side Registers After 6 27 SEIT Interrupt IU 7 5 SHI Internal Interrupt Priorities 7 5 SHI Noise Reduction Filter Mode 7 10 SHI Data SIZE Sau yu supa alee etes wea 7 11 Function In SHI Slave Modes 7 12 HCSR Receive Interrupt Enable 7 14 Receiver Clock Sources asynchronous mode only 8 5 Transmitter Clock Sources uses a ERA NEA EXE RA ce 8 6 Transmitter High Frequency Clock Divider 8 11 Transmit Network Mode Selection 8 16 ESAI Transmit Slot and Word Length Selection 8 18 Receiver High Frequency Clock 8 24 SCKR Pin Definition Table 8 25 FSR Pm Definition Table scese ag ve p ast Rs 8 25 HCKR Pin D finition Table casta pasasha hu Daaka datae un 8 26 ESAI Receive Network Mode Selection 8 28
366. mber N The data is not transferred from the receive shift registers to the receive data registers and neither the RDF nor the ROE flags are set This means that during a disabled slot no receiver full interrupt is generated The DSP is interrupted only for enabled slots When bit number N in the RSM is set the receive sequence is as usual data which is shifted into the enabled receivers shift registers is transferred to the receive data registers and the RDF flag is set Data written to the RSM affects the next received frame The frame being received is not affected by this data and would comply to the last RSM setting Data read from RSM returns the last written data After hardware or software reset the RSM register is preset to FFFFFFFF which means that all 32 possible slots are enabled for data reception DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 8 42 Freescale Semiconductor Operating Modes NOTE When operating in normal mode bit 0 of the mask register must be set to one otherwise no input is received 8 4 Operating Modes ESAI operating mode are selected by the ESAI control registers TCCR TCR RCCR RCR and SAICR The main operating mode are described in the following paragraphs 8 4 1 ESAI After Reset Hardware or software reset clears the port control register bits and the port direction control register bits which configure all ESAI I O pins as disconnected The ESAI is in the individual res
367. mined by the RCKD bit in the RCCR register The SCKR operates as a clock input or output used by all the enabled receivers in the asynchronous mode SYN 0 or as serial flag 0 pin in the synchronous mode SYN 1 DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 8 4 Freescale Semiconductor ESAI Data and Control Pins When this pin is configured as serial flag pin its direction is determined by the RCKD bit in the RCCR register When configured as the output flag OFO this pin reflects the value of the OFO bit in the SAICR register and the data in the OFO bit shows up at the pin synchronized to the frame sync being used by the transmitter and receiver sections When this pin is configured as the input flag IFO the data value at the pin is stored in the bit in the SAISR register synchronized by the frame sync in normal mode or the slot in network mode SCKR may be programmed as a general purpose I O pin when the ESAI SCKR function is not being used NOTE Although the external ESAI serial clock can be independent of and asynchronous to the DSP system clock the DSP clock frequency must be at least three times the external ESAI serial clock frequency and each ESAI serial clock phase must exceed the minimum of 1 5 DSP clock periods For more information on pin mode and definition see Table 8 7 and on receiver clock signals see Table 8 1 Table 8 1 Receiver Clock Sources asynchronous mode only
368. ming Sheets Sheet 3 of 3 Programmer Date Application 0 S x X L64444 X aad BuuH parsiH 3riHgnuH snjejg o43uo2 eL SL 2 jou HSOI X LH SS 5109 IHS sng ON jue e 05 146 ydnueju ss eBpejwouyxoe paiqesip 10419 ON ON uonduos q 145 smejs peigesip IHS 40443 unJJ9AQ 9419293 JSOH uonduoseg snes peesj 2 peiqeue 1dnui lul 10129 sng 0214 2 ISOH p lqesipidnu lui Jou3 sng snes pees pe qeu3 2 1 JSOH 5015 5 1 L dois pe qesig 2 4 221 0 18491 OF sng sng yg snjeis uogdusseg _ aayaH 31dIH yg smeis pees penlesey 10443 1 pc 9 ejep yq 8 21043 eAie2es 0 3OSH 3 L
369. mmand Vector default vector 2A 7 HC Host Command 0 nohost command pending cleared HDIO8 0 0 0 1 host command pending hardware when the HC int req is serviced RXH M L 7 0 Host Receive Data empty Register TXH M L 7 0 Host Transmit Data empty Register IVR 7 0 IV7 IVO Interrupt Register 68000 family vector register D 6 Programming Sheets The worksheets shown on the following pages contain listings of major programmable registers for the DSP56366 The programming sheets are grouped into the following order Central Processor Host Interface HDIO8 Serial Host Interface SHI Two Enhanced Serial Audio Interfaces ESAI and ESAI 1 Digital Audio Interface DAX Timer Event Controller TEC GPIO Ports B E Each sheet provides room to write in the value of each bit and the hexadecimal value for each register Programmers can photocopy these sheets and reuse them for each application development project For details on the instruction set of the DSP56300 family chips see the DSP56300 Family Manual DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor D 15 Programming Sheets Application Programmer Sheet 1 of 5 Central Processor Zero Negative Unnormalized U 2 Acc 47 xnor Acc 46 Extension Limit FFT Scaling S Acc 46 xor Acc 45 Interrupt Mask Scaling Mode 1 0 Exceptions Masked S 1 0 Scaling Mode 00 0
370. mmer braun ao jn vn n m i foo s s o 0 L r S 9 L 8 6 OL L vL SL 992 L 44 00 YOON 10 19 eosoJud seyioeds uonduoseq 0 2 pessed q Jajeosaid 9 Aq JeuoneJedo JejeoseJd g Aq uonduoseq z 1 LLLLL 00000 SJOPIAIP 9UJEJJ uonduoseg 91 L 45 0 9 asas 6L 0c ec c ZL 8b Jo Buisu uo Jo eBpe uo ynoyoo D Jo uo jo uo noy5o O 9j6J 5196 pesn eoJnos uonduoseq 0 61 000000 195944 864444 493316 043002 320 2 9AI928M IVS3 YOY uonduoseg uoneJedo JadoJd 40 195 eq JSN uonduoseq 1 Receive Clock Control Register Figure D 24 ESAI DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 D 39 Freescale Semiconductor Date Application Programming Sheets 193 3IQ3H ae J9AI929M L paqesip 1941929 0 1015 1S4 uonduos q 6 0 38 20 2446
371. mmunication with a variety of serial devices SECTION 9 ENHANCED SERIAL AUDIO INTERFACE 1 ESAI 1 Describes the second full duplex serial port for serial communication with a variety of serial devices SECTION 10 DIGITAL AUDIO TRANSMITTER DAX Describes the full duplex serial port for serial communication with a variety of serial devices SECTION 11 TRIPLE TIMER MODULE TEC APPENDIX A BOOTSTRAP PROGRAM Lists the bootstrap code used for the DSP56366 APPENDIX B EQUATES Lists equates for the DSP56366 APPENDIX C JTAG BSDL LISTING Provides the BSDL listing for the DSP56366 APPENDIX D PROGRAMMING REFERENCE Lists peripheral addresses interrupt addresses and interrupt priorities for the DSP56366 Contains programming sheets listing the contents of the major DSP56366 registers for programmer reference Manual Conventions The following conventions are used in this manual Bits within registers are always listed from most significant bit MSB to least significant bit LSB When several related bits are discussed they are referenced as AA n m where n gt m For purposes of description the bits are presented as if they are contiguous within a register However this is not always the case Refer to the programming model diagrams or to the programmer s sheets to see the exact location of bits within a register When a bit is described as set its value is 1 When a bit is described as cl
372. mode of operation is enabled and is cleared when the DMA mode is disabled The DMA mode is enabled under the following conditions HCR bits HDM 2 0 100 and the host processor has enabled the DMA mode by setting either or both the ICR bits 1 and HMO Either or both of the HCR bits HDM1 and have been set When the DMA bit is zero the channel not in use can be used for polled or interrupt operation by the DSP 6 5 5 Host Base Address Register HBAR The HBAR is used in multiplexed bus modes This register selects the base address where the host side registers are mapped into the bus address space The address from the host bus is compared with the base address as programmed in the base address register If the addresses match an internal chip select is generated The use of this register by the chip selectlogic is shown in Figure 6 5 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 9 BAS 4 Reserved bit Read as 0 Should be written with O for future compatibility Figure 6 4 Host Base Address Register HBAR 5 6 5 5 1 HBAR Base Address BA 10 3 Bits 0 7 These bits define the base address where the host side registers are mapped into the bus address space DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 6 11 HDIO8 DSP Side Programmer s Mode
373. n register set Each timer can use internal or external clocking and can interrupt the DSP after a specified number of events clocks Timer 0 can signal an external device after counting internal events Each timer can also be used to trigger DMA transfers after a specified number of events clocks occurred One timer Timer 0 connects to the external world through one bidirectional pin TIOO When TIOO is configured as input the timer functions as an external event counter or can measure external pulse width signal period When TIOO is used as output the timer is functioning as either a timer a watchdog or a Pulse Width Modulator When the TIOO pin is not used by the timer it can be used as a General Purpose Input Output Pin Refer to Section 11 Timer Event Counter DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 1 9 Peripheral Overview 1 5 4 Enhanced Serial Audio Interface ESAI The ESAI provides a full duplex serial port for serial communication with a variety of serial devices including one or more industry standard codecs other DSPs microprocessors and peripherals that implement the Freescale SPI serial protocol The ESAI consists of independent transmitter and receiver sections each with its own clock generator It is a superset of the DSP56300 family ESSI peripheral and of the DSP56000 family SAI peripheral For more information on the refer to Section 8 Enhanced Serial AUDIO
374. n the host sets the INIT bit the HDIO8 hardware executes the INIT command The interface hardware clears the INIT bit after the command has been executed Table 6 13 INIT Command Effect TREQ RREQ After INIT Execution Transfer Direction Initialized 0 0 INIT 0 None 0 1 INIT 0 RXDF 0 HTDE 1 DSP to Host 1 O INIT 0 TXDE 1 HRDF 0 Host to DSP 1 1 INIT 0 RXDF 0 HTDE 1 TXDE 1 HRDF 0 Host to from DSP 6 6 2 Command Vector Register CVR The CVR 15 used by the host processor to cause the DSP core to execute an interrupt The host command feature is independent of any of the data transfer mechanisms in the HDIOS It can be used to invoke execution of any of the 128 possible interrupt routines in the DSP core 7 6 5 4 3 2 1 0 HC HV6 HV5 HV4 HV3 HV2 HV1 HVO Figure 6 13 Command Vector Register CVR 6 6 2 1 CVR Host Vector HV 6 0 Bits 0 6 The seven HV bits select the host command interrupt address to be used by the host command interrupt logic When the host command interrupt is recognized by the DSP interrupt control logic the address of the interrupt routine taken is 2 HV The host can write HC and HV in the same write cycle DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 6 23 HDIO8 External Host Programmer s Model The host processor can select the starting address of any of the 128 possible interrupt routines in
375. n transmitting data is as follows wait for TDE transmitter empty to be set first write the flags and then write the transmit data to the transmit registers and OF2 are double buffered so that the flag states appear on the pins when the transmit data 1s transferred to the transmit shift register 1 e the flags are synchronous with the data 85 GPIO Pins and Registers The GPIO functionality of the ESAI port is controlled by three registers Port C control register PCRC Port C direction register PRRC and Port C data register PDRC 8 5 1 Port C Control Register PCRC The read write 24 bit Port C Control Register PCRC in conjunction with the Port C Direction Register PRRC controls the functionality of the ESAI GPIO pins Each of the PC 11 0 bits controls the functionality of the corresponding port pin See Table 8 12 for the port pin configurations Hardware and software reset clear all PCRC bits 8 5 2 Port C Direction Register PRRC The read write 24 bit Port C Direction Register PRRC in conjunction with the Port C Control Register PCRC controls the functionality of the ESAI GPIO pins Table 8 12 describes the port pin configurations Hardware and software reset clear all PRRC bits DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 8 47 GPIO Pins and Registers Table 8 12 PCRC and PRRC Bits Functionality
376. nd receiver sections may use common clock and synchronization signals synchronous operating mode or they may have their own separate clock and sync signals asynchronous operating mode The SYN bit in the SAICR register selects synchronous or asynchronous operation Since the ESAI is designed to operate either synchronously or asynchronously separate receive and transmit interrupts are provided When SYN is cleared the ESAI transmitter and receiver clocks and frame sync sources are independent If SYN is set the ESAI transmitter and receiver clocks and frame sync come from the transmitter section either external or internal sources DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 8 45 Operating Modes Data clock and frame sync signals can be generated internally by the DSP or may be obtained from external sources If internally generated the ESAI clock generator is used to derive high frequency clock bit clock and frame sync signals from the DSP internal system clock 8 4 4 3 Frame Sync Selection The frame sync can be either a bit long or word long signal The transmitter frame format is defined by the TFSL bit in the TCR register The receiver frame format is defined by the RFSL bit in the RCR register 1 In the word long frame sync format the frame sync signal is asserted during the entire word data transfer period This frame sync length is compatible with Freescale codecs SPI serial peri
377. nductor GPIO PORT D Pins and Registers PCRD Port D Control Register X 3FFFFD7 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 ILI IE C IE ILI LL C read as zero should be written with zero for future compatibility 10 7 2 Port D Direction Register PRRD The read write 24 bit Port D Direction Register controls the direction of the DAX GPIO pins When port pin i is configured as GPIO 1 controls the port pin direction When is set the GPIO port pin i is configured as output When PDC i is cleared the GPIO port pin i is configured as input Hardware and software reset clear all PRRD bits Table 10 6 describes the port pin configurations PRRD Port D Direction Register X FFFFD6 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 rITTITITTITITITITLILIIIIIII1 Pre read as zero should be written with zero for future compatibility Figure 10 7 Port D Direction Register PRRD Table 10 6 DAX Port GPIO Control Register Functionality PDC1 PC1 ADO PD1 PDCO PCO ACI PDO pin DAX state 0 0 Disconnected 0 0 Disconnected Personal Reset 0 0 Disconnected 0 1 PDO Input Personal Reset 0 0 Disconnected 1 0 PDO Output Personal Reset 0 0 Disconnected 1 1 ACI Enabled 0 1 PD1 Input 0 0 Disconnected Personal Reset 0 1 PD1 Input 0 1 PDO Input Personal Reset 0 1 PD1 Input 1 0 PDO Output Personal Reset 0
378. ng a word with no new data in HTX a stop event is generated determines the acknowledge that the receiver sends after correct reception of a byte If is cleared the reception is acknowledged by sending a 0 bit on the SDA line at ACK clock tick If HIDLE is set the reception is not acknowledged a 1 bit is sent It is used to signal an end of data to a slave transmitter by not generating an ACK on the last byte As a result the slave transmitter must release the SDA line to allow the master to generate the stop event If the SHI completes receiving a word and the HRX FIFO is full the clock is suspended before transmitting an ACK While HIDLE is cleared the bus is busy that 15 the start event was sent but no stop event was generated Setting HIDLE causes a stop event after receiving the current word HIDLE is set while the SHI is not in the master mode while the chip is in the stop state and during hardware reset software reset and individual reset NOTE Programmers should take care to ensure that all DMA channel service to HTX is disabled before setting HIDLE 7 4 6 9 HCSR Bus Error Interrupt Enable HBIE Bit 10 The read write control bit HBIE is used to enable the SHI bus error interrupt If HBIE is cleared bus error interrupts are disabled and the HBER status bit must be polled to determine if an SHI bus error occurred If both HBIE and HBER are set the SHI requests an SHI bus error interrupt service f
379. nly status register used by the DSP to read the status and flags of the HDIOS It cannot be directly accessed by the host processor The initialization values for the HSR bits are described in Section 6 5 9 DSP Side Registers After Reset The HSR bits are described in the following paragraphs DMA HCP HTDE HRDF Reserved bit Read as 0 Should be written with O for future compatibility Figure 6 3 Host Status Register HSR X FFFFC3 6 5 4 1 HSR Host Receive Data Full HRDF Bit 0 The HRDF bit indicates that the host receive data register HORX contains data from the host processor HRDF is set when data is transferred from the TXH TXM TXL registers to the HORX register HRDF 15 cleared when is read by the DSP core If HRDF is set the HDIOS generates a receive data full DMA request if enabled by a DSP core DMA Channel If HRDF is set when HRIE is set a host receive data interrupt request is generated HRDF can also be cleared by the host processor using the initialize function 6 5 4 2 HSR Host Transmit Data Empty HTDE Bit 1 The HTDE bit indicates that the host transmit data register HOTX is empty and can be written by the DSP HTDE is set when the HOTX register is transferred to the RXH RXM RXL registers HTDE is cleared when HOTX is written by the DSP core If HTDE is set the HDIOS generates a transmit data empty DMA request if en
380. nterrupt Enable TIE Bit 22 The DSP is interrupted when TIE and the TDE flag in the SAISR status register are set When TIE is cleared this interrupt is disabled Writing data to all the data registers ofthe enabled transmitters or to TSR clears TDE thus clearing the interrupt Transmit interrupts with exception have higher priority than normal transmit data interrupts therefore if exception occurs TUE is set and TEIE is set the ESAI requests an ESAI transmit data with exception interrupt from the interrupt controller 8 3 2 19 TCR Transmit Last Slot Interrupt Enable Bit 23 TLIE enables an interrupt at the beginning of last slot of a frame in network mode When TLIE is set the DSP is interrupted at the start of the last slot in a frame in network mode regardless of the transmit mask register setting When TLIE is cleared the transmit last slot interrupt is disabled TLIE is disabled when TDC 4 0 00000 on demand mode The use of the transmit last slot interrupt is described in Section 8 4 3 ESAI Interrupt Requests 8 3 3 ESAI Receive Clock Control Register RCCR The read write Receive Clock Control Register RCCR controls the ESAI receiver clock generator bit and frame sync rates word length and number of words per frame for the serial data The RCCR control bits are described in the following paragraphs see Figure 8 8 11 10 9 8 7 6 5 4 3 2 1 0 X FFFFB8 RDC2 RPSR 7 6
381. o contains the GPIO Port E functionality described in Section 9 5 GPIO Pins and Registers The following paragraphs give detailed descriptions of bits in the ESAI 1 registers that differ in functionality from their descriptions in the ESAI Programming Model 9 3 1 ESAI 1 Multiplex Control Register EMUXR The read write ESAI 1 Multiplex Control Register EMUXR controls which peripheral ESAI or ESAI 1 is using the shared pins 11 10 9 8 7 6 5 4 3 2 1 0 Y FFFFAF EMUX2 EMUX1 23 22 21 20 19 18 17 16 15 14 13 12 Reserved bit read as zero should be written with zero for future compatibility Figure 9 2 EMUXR Register Hardware and software reset clear all the bits ofthe EMUXR register The selection of ESAI ESAI 1 pins is shown in Table 9 1 Table 9 1 EMUXR ESA ESAI 1 Pin Selection EMUXR bit ESAI pin ESAI 1 pin EMUXO 0 SDOO PC11 disconnected EMUXO 1 disconnected SDOO 1 PE11 EMUX1 0 SDO1 PC10 disconnected EMUX1 1 disconnected SDO 1 1 PE10 EMUX2 0 SDO2 SDI3 PC9 disconnected EMUX2 1 disconnected 5 2 1 SDI3 1 EMUX3 0 SDO3 SDI2 PC8 disconnected EMUX3 1 disconnected SDO3_1 SDI2_1 9 3 2 ESAI_1 Transmitter Clock Control Register TCCR_1 The read write Transmitter Clock Control Register TCCR_1 controls the ESAI 1 transmitter cl
382. o the using DMA Programmable clock source Users can select the DA X clock source and this selection configures the DAX to operate in slave or master mode Supports both master mode and slave mode in a digital audio network f the user selects divided DSP core clock the DAX will operate in the master mode If the user selects an external clock source the DAX will operate in the slave mode GPIO Each ofthe two DAX pins can be configured as either GPIO or as specific DA X pin Each pin is independent of the other However at least one of the two pins must be selected as a DAX pin to release the DAX from reset The accessible DAX registers are all mapped in the X I O memory space This allows programmers to access the DAX using standard instructions and addressing modes Interrupts generated by the DAX can be handled with a fast interrupt for cases in which the non audio data does not change from frame to frame When the interrupts are disabled they can still be served by DMA or by a polling technique block diagram of the DAX is shown in Figure 10 1 NOTE The shaded registers in Figure 10 1 are directly accessible by DSP instructions DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 10 1 DAX Signals Global Data Bus DMA Bus m 23 0 23 0 XSTR XNADR XADR XCTR XADBUFA XADBUFB 26 23 0 LU ADO Encoder Preamb
383. ock generator bit and frame sync rates the bit rate and high frequency clock sources and the directions of the FST_1 and SCKT 1 signals In synchronous mode the bit clock defined for the transmitter determines the receiver bit clock as well TCCR_1 also controls the number of words per frame for the serial data Hardware and software reset clear all the bits of the TCCR 1 register DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 9 5 ESAI 1 Programming Model 11 10 9 8 7 6 5 4 3 2 1 0 Y FFFF96 TDC2 TDC1 TPSR 7 TPM6 TPM5 2 TPM1 TPMO 23 22 21 20 19 18 17 16 15 14 13 12 TFSD TCKD TFSP TCKP 2 TDC4 TDC3 Figure 9 3 TCCR 1 Register 9 3 2 1 TCCR 1 Tx High Freq Clock Divider Bits 14 17 Since the ESAI 1 does not have the transmitter high frequency clock pin the TFP3 TFPO bits simply specify an additional division ratio in the clock divider chain See Figure 9 4 9 3 2 2 TCCR 1 Tx High Freq Clock Polarity THCKP Bit 20 The ESAI 1 does not have the transmitter high frequency clock pin It it recommended that THCKP should be kept cleared 9 3 2 3 TCCR 1 Tx High Freq Clock Direction THCKD Bit 23 The ESAI 1 does not have the transmitter high frequency
384. ode 7 22 7 1 4 PC Master Mode 7 23 7 7 41 Receive Data Master 7 24 7 1 4 2 Transmit Data In PC Master 7 24 7 7 5 SHI Operation During DSP Stop 7 25 8 Enhanced Serial AUDIO Interface ESAI 8 1 Bl 2 03 o oed ost ed be usa att bd eeu un ak uhaqqa bee od 8 1 S2 and Control PINS 25 TC RU up a 8 3 8 2 1 Serial Transmit 0 Data Pin SDO0 8 3 8 2 2 Serial Transmit 1 Data Pin SDO1 8 3 8 2 3 Serial Transmit 2 Receive 3 Data Pin 5902 5013 8 3 8 2 4 Serial Transmit 3 Receive 2 Data Pin 5 3 6 00 8 4 8 2 5 Serial Transmit 4 Receive 1 Data Pin 52004 53 1 8 4 8 2 6 Serial Transmit 5 Receive 0 Data Pin 005 8 10 8 4 8 2 7 Receiver Seral Clock SEKR 6452 utes Sort MU V4 8 2 8 Transmitter Serial Glock SCKT 8 5 8 2 9 Frame Sync for Receiver PSR ez Seu RS a NA Rr VE a 8 6 DSP56366 24 Bit Digital
385. ode Interrupt Priority Level low M_IDL1 EQU 10 IRQD Mode Interrupt Priority Level high M IDL2 EQU 11 IRQD Mode Trigger Mode M DOL EQU 3000 DMAO Interrupt priority Level Mask M DOLO EQU 12 DMAO Interrupt Priority Level low DOL1 EQU 13 DMAO Interrupt Priority Level high M DIL EQU C000 DMA1 Interrupt Priority Level Mask M D1LO EQU 14 DMA1 Interrupt Priority Level low M D1L1 EQU 15 DMA1 Interrupt Priority Level high M D2L EQU 30000 DMA2 Interrupt priority Level Mask M D2LO EQU 16 DMA2 Interrupt Priority Level low M D2L1 EQU 17 DMA2 Interrupt Priority Level high M D3L EQU C0000 DMA3 Interrupt Priority Level Mask M D3LO EQU 18 DMA3 Interrupt Priority Level low EQU 19 DMA3 Interrupt Priority Level high M DAL EQU 300000 DMA4 Interrupt priority Level Mask DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 B 6 Freescale Semiconductor Equates M DALO EQU 20 DMA4 Interrupt Priority Level low D4L1 EQU 21 DMA4 Interrupt Priority Level high M D5L EQU C00000 DMA5 Interrupt priority Level Mask D5LO EQU 22 DMA5 Interrupt Priority Level low 511 EQU 23 DMA5 Interrupt Priority Level high Interrupt Priority Register Peripheral M ESL EQU 3 ESAI Interrupt Priority Level Mask M ESLO EQU 0 ESAI Interrupt Priority Level low M ESL1 EQU 1 ESAI Interrupt Priority Level h
386. onality HDDR HDR Dxx DRxx GPIO pin non GPIO 0 Read only bit The value read is the binary value of Read only bit Does not contain significant data the pin The corresponding pin is configured as an input 1 Read write bit The value written is the value read Read write bit The value written is the value read The corresponding pin is configured as an output and is driven with the data written to Dxx Defined by the selected configuration 6 5 9 DSP Side Registers After Reset Table 6 7 shows the results of the four reset types on the bits in each of the HDIO8 registers accessible by the DSP core The hardware reset HW is caused by the RESET signal The software reset SW is caused by executing the RESET instruction The individual reset IR is caused by clearing the HEN bit HPCR bit 6 The stop reset ST 18 caused by executing the STOP instruction DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 6 16 Freescale Semiconductor HDIO8 DSP Side Programmer s Model Table 6 7 DSP Side Registers after Reset Reset Type Register Register Name Data HW SW IR ST Reset Reset Reset Reset HCR All bits 0 0 HPCR All bits 0 0 HSR HF 1 0 0 0 HCP 0 0 0 0 HTDE 1 1 1 1 HRDF 0 0 0 0 DMA 0 0 HBAR BA 10 3 80 80 HDDR DR 15 0 0 0 HDR D 15 0 EN HORX HORX 23 0 empty emp
387. onductor Figure D 25 ESAI 1 Receive Control Register DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 D 40 Programming Sheets ESSEN m ERE SL Programmer 0 pues EN uondioseg 0 2 40 a uonduoseg snouoJuou S snouoJupou sy uondioseaq NAS ud HS4 slonuoo uonduoseg SL yo o yo uonduoseg Application O O Date 000000 39594 v63344 4ejsiBeM 2 UOWWOD IVS3 5 IVS3 uonduoseg Figure 0 26 ESAI 1 Common Control Register DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 D 41 Freescale Semiconductor Programming Sheets Date Application Programmer 3834 Buunp Jn290 pip 2u s Buunp Jn990 JOU 2u s UnJJ9AO JOAISDSI ON 0 ejep ue e uonduoseq qas 000000 19598 64444 53035 IVS3 Sacre sJejsiDeJ jlusuei E sJejsi eJ jluJsuei uonduoseg sJejsiDeJ jusueJ
388. or both the transmitters and receivers in the synchronous mode SYN 1 and for the transmitters only in asynchronous mode SYN 0 see Table 8 2 The direction of this pin 15 determined by the TFSD bit in the TCR register When configured as an output this pin 15 the internally generated frame sync signal When configured as an input this pin receives an external frame sync signal for the transmitters and the receivers in synchronous mode FST may be programmed as a general purpose I O when the ESAI FST function is not being used 8 2 11 High Frequency Clock for Transmitter HCKT HCKT is a bidirectional pin providing the transmitters high frequency clock for the ESAI interface The direction of this pin is determined by the THCKD bit in the TCCR register In the asynchronous mode SYN 0 the HCKT pin operates as the high frequency clock input or output used by all enabled transmitters In the synchronous mode SYN 1 it operates as the high frequency clock input or output used by all enabled transmitters and receivers When programmed as input this pin is used as an alternative high frequency clock source to the ESAI transmitter rather than the DSP main clock When programmed as output it can serve as a high frequency sample clock to external DACS for example or as an additional system clock See Table 8 2 HCKT may be programmed as a general purpose I O pin PC5 when the ESAI HCKT function is not being used 8 2 12 High
389. ost Busy HBUSY M HBER EQU 21 SHI Bus Error HBER M HROE EQU 20 SHI Receive Overrun Error HROE M HRFF EQU 19 SHI Receivr FIFO Full HRFF M HRNE EQU 15 SHI Receive FIFO Not Empty HRNE M HTDE EQU 15 SHI Host Transmit data Empty HTDE M HTUE EQU 14 SHI Host Transmit Underrun Error HTUE M HRIE1 EQU 13 SHI Receive Interrupt Enable HRIE1 M HRIEO EQU 12 SHI Receive Interrupt Enable HRIEO M HTIE EQU 11 SHI Transmit Interrupt Enable HTIE M HBIE EQU 10 SHI Bus Error Interrupt Enable HBIE M HIDLE EQU 9 SHI Idle HIDLE M HROE1 EQU 8 SHI Host Request Enable HRQE1 M HRQEO EQU 7 SHI Host Request Enable HRQEO M HMST EQU 6 SHI Master Mode HMST M HFIFO EQU 5 SHI FIFO Enable Control HFIFO M HCKFR EQU 4 SHI Clock Freeze HCKFR M EQU 3 SHI Serial Host Interface Mode 1 M HMO EQU 2 SHI Serial Host Interface Mode HMO M HI2C EQU 1 I2c SPI Selection HI2C M HEN EQU 0 SHI Host Enable HEN DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor B 19 Equates control bits in HCKR M EQU 13 SHI Filter Model HFM1 M HFMO EQU 12 SHI Filter Model M HDM7 EQU 10 SHI Divider Modulus Select HDM7 M HDM6 EQU 9 SHI Divider Modulus Select HDM6 M HDM5 EQU 8 SHI Divider Modulus Select HDM5 M HDM4 EQU 7 SHI Divider Modulus Select HDM4 M HDM3 EQU 6 SHI Divider Modulus Select HDM3
390. oundary Scan Register BSR NOTES DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 4 18 Freescale Semiconductor 5 General Purpose Input Output 5 1 Introduction The DSP56362 provides up to 37 bidirectional signals that can be configured as GPIO signals or as peripheral dedicated signals No dedicated GPIO signals are provided All of these signals are GPIO by default after reset The techniques for register programming for all GPIO functionality is very similar between these interfaces This section describes how signals may be used as GPIO 5 2 Programming Model The signals description section of this manual describes the special uses of these signals in detail There are five groups of these signals which can be controlled separately or as groups Port B up to 16 GPIO signals shared with the HDIOS signals Port C 12 GPIO signals shared with the ESAI signals Port D two GPIO signals shared with the DAX signals Port E 10 signals shared with the ESAI 1 signals Timer one GPIO signal shared with the timer event counter signal 5 2 1 Port B Signals and Registers When HDIOS is disabled all 16 HDI08 signals can be used as GPIO When HDIOS is enabled five HA8 HA9 HCS HOREQ and HACK of the 16 port B signals if not used as a HDIO8 signal can be configured as GPIO signals The GPIO functionality of port B 15 controlled by three registers host port control register HPCR host por
391. ounter value is reached if the timer compare interrupt is enabled Note that any of the three timers can be placed in GPIO mode to generate internal interrupts but only timer 0 provides actual external GPIO access on the TIOO signal Set TE bit to clear the counter and enable the timer Load the value the timer is to count into the TCPR The counter is loaded with the TLR value when the first timer clock signal is received The timer clock can be taken from either the DSP56366 clock divided by two CLK 2 or from the prescaler clock output Each subsequent clock signal increments the counter When the counter equals the TCPR value the TCF bit in TCSR is set and a compare interrupt is generated if the TCIE bit is set If the bit in the TCSR 15 set the counter 15 reloaded with the TLR value at the next timer clock and the count is resumed If the bit is cleared the counter continues to be incremented on each timer clock signal This process is repeated until the timer is disabled 1 TE 15 cleared If the counter overflows the TOF bit 15 set and if is set an overflow interrupt is generated The counter contents can be read at any time by reading the TCR DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 11 13 Timer Modes of Operation 11 4 1 2 Timer Pulse Mode 1 Bit Settings Mode Characteristics 2 TC1 TCO TIOO Clock KIND NAME 0 0 0 1 Outp
392. pherals serial A D and D A converters shift registers and telecommunication PCM serial I O 2 In the bit long frame sync format the frame sync signal is asserted for one bit clock immediately before the data transfer period This frame sync length is compatible with Intel and National components codecs and telecommunication PCM serial I O The relative timing of the word length frame sync as referred to the data word is specified by the TFSR bit in the TCR register for the transmitter section and by the RFSR bit in the RCR register for the receive section The word length frame sync may be generated or expected with the first bit of the data word or with the last bit of the previous word TFSR and RFSR are ignored when a bit length frame sync is selected Polarity of the frame sync signal may be defined as positive asserted high or negative asserted low The TFSP bit in the TCCR register specifies the polarity of the frame sync for the transmitter section The RFSP bit in the RCCR register specifies the polarity of the frame sync for the receiver section The ESAI receiver looks for a receive frame sync leading edge trailing edge if RFSP is set only when the previous frame is completed If the frame sync goes high before the frame is completed or before the last bit of the frame is received in the case of a bit frame sync or a word length frame sync with set the current frame sync is not recognized and the receiver is inte
393. present in the OFO bit is written to the OFO pin at the beginning of the frame in normal mode or at the beginning of the next time slot in network mode 8 3 5 2 SAICR Serial Output Flag 1 OF1 Bit 1 The Serial Output Flag 1 is a data bit used to hold data to be send to the pin When the ESAI is in the synchronous clock mode SYN 1 the FSR pin is configured as the ESAI flag 1 If the receiver frame sync direction bit RFSD is set and the TEBE bit is cleared the FSR pin is the output flag OF1 and data present in the OF bit is written to the OF1 pin at the beginning of the frame in normal mode or at the beginning of the next time slot in network mode 8 3 5 3 SAICR Serial Output Flag 2 OF2 Bit 2 The Serial Output Flag 2 OF2 is a data bit used to hold data to be send to the OF2 pin When the ESAI is in the synchronous clock mode SYN 1 the HCKR pin is configured as the ESAI flag 2 If the receiver high frequency clock direction bit RHCKD is set the HCKR pin is the output flag OF2 and data present in the OF2 bit is written to the OF2 pin at the beginning of the frame in normal mode or at the beginning of the next time slot in network mode 8 3 5 4 SAICR Reserved Bits Bits 3 5 9 23 These bits are reserved They read as zero and they should be written with zero for future compatibility 8 3 5 5 SAICR Synchronous Mode Selection SYN Bit 6 The Synchronous Mode Selection SYN bit controls whether the receive
394. pt Priority Priority Interrupt highest DAX transmit underrun error DAX block transferred lowest DAX audio data register empty 10 5 DAX Internal Architecture Hardware components shown in Figure 10 1 are described in the following sections The DAX programming model is illustrated in Figure 10 2 XCTR Control Register X FFFFDO 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 a XNADR Non Audio Data Register X FFFFD1 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 LII DL LII mem 00 101 1 XADRA Audio Data Register A X F FFFD2 and XADRB Audio Data Register B X F FFFD3 23 XSTR Status Register X FFFFD4 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 CIL LII LO C LIE LI CI I I Ir p cr esee Figure 10 2 DAX Programming Model DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 10 4 Freescale Semiconductor DAX Internal Architecture 10 5 1 Audio Data Register XADR XADR is a 24 bit write only register One frame of audio data which is to be transmitted in the next frame slot 15 transferred to this register Successive write accesses to this register will store channel A and channel B alternately in XADBUFA and in XADBUFB respectively When XADR and XADBUFA are empty XADE bit in the XSTR is set and if the audio data register empty interrupt is enabled XDIE 1 an interrupt request is sent to the DSP core When channel B is transferred to XADR
395. put and bidirectional pins are disabled high impedance the HCSR status bits and the transmit receive paths are reset to the same state produced by hardware reset or software reset The individual reset state 15 entered following a one instruction cycle delay after clearing HEN 7 4 6 2 HCSR C SPI Selection HI C Bit 1 The read write control bit selects whether the SHI operates in the or SPI modes When HI C is cleared the SHI operates in the SPI mode When is set the SHI operates in the mode affects the functionality of the SHI pins as described in Section 2 Signal Connection Descriptions It is recommended that an SHI individual reset be generated HEN cleared before changing HPC is cleared during hardware reset and software reset 7 4 6 3 HCSR Serial Host Interface Mode HM 1 0 Bits 3 2 The read write control bits HM 1 0 select the size of the data words to be transferred as shown in Table 7 4 HM 1 0 should be modified only when the SHI is idle HBUSY 0 HM 1 0 are cleared during hardware reset and software reset Table 7 4 5 Data Size HM1 HMO Description 0 0 8 bit data 0 1 16 bit data 1 0 24 bit data 1 1 Reserved 7 4 6 4 HCSR 1 Clock Freeze HCKFR Bit 4 The read write control bit HCKFR determines the behavior of the SHI when the SHI is unable to service the master request when operating in the slave mode The HCKFR bit is us
396. quest HOREQ signal when the receive data register full RXDF status bit in the ISR is set If RREQ is cleared RXDF requests are disabled If RREQ is set the host request signal HOREQ or is asserted if RXDF is set In the DMA modes where HDM 2 0 100 and HM1z0 HM0z0 RREQ must be set and TREQ must be cleared to direct DMA transfers from DSP to host In the other DMA modes RREQ is ignored Table 6 9 summarizes the effect of RREQ and TREQ on the HOREQ HTRQ and HRRQ signals 6 6 1 2 ICR Transmit Request Enable TREQ Bit 1 In interrupt mode HDM 2 0 000 or HM 1 0 00 TREQ is used to enable host transmit data requests via the host request HOREQ HTRQ signal when the transmit data register empty TXDE status bit in the ISR is set If TREQ 15 cleared TXDE requests are disabled If TREQ is set the host request signal HOREQ or HTRQ is asserted if TXDE is set In the DMA modes where HDM 2 0 100 and HM1z0 or HM0z0 TREQ must set and RREQ must be cleared to direct DMA transfers from host to DSP In the other DMA modes TREQ is ignored Table 6 9 summarizes the effect of RREQ and TREQ on the HOREQ HTRQ and HRRQ signals DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 6 20 Freescale Semiconductor HDI08 External Host Programmer s Model Table 6 9 TREQ RREQ Interrupt Mode HDM 2 0 000 or HM 1 0 00
397. r SAICR 1 ESAI 1 Status Register SAISR 1 ESAI 1 ESAI 1 ESAI 1 ESAI 1 ESAI 1 ESAI 1 ESAI 1 ESAI 1 ESAI 1 ESAI 1 ESAI 1 Receive Data Register 3 Receive Data Register 2 Receive Data Register 1 Receive Data Register 0 Time Slo Transmit Transmit Transmit Transmit Transmit Transmit Data Data Data Data Data Data Register Register Register Register Register Register 5 RX3 1 RX2 1 RX1 1 RXO 1 t Register TSR 1 TX5 1 1 TX3_1 TX2 1 TXl 1 TXO _1 EQUATES for ESAI M_RSMB M_RSMA M_TSMB M TSMA M RCCR SFFFFBC SFFFFBB SFFFFBA SFFFFB9 SFFFFB8 ESAI Receive Slot Mask Register B RSMB ESAI Receive Slot Mask Register A RSMA ESAI Transmit Slot Mask Register B TSMB ESAI Transmit Slot Mask Register A TSMA ESAI Receive Clock Control Register RCCR DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor B 21 Equates M EQU M TCCR EQU M TCR EQU M SAICR EQU M SAISR EQU M TX2 EQU M EQU M TXO EQU RSMB M RS31 EQU M RS30 EQU M RS29 EQU M RS28 EQU M RS27 EQU M RS26 EQU M RS25 EQU M RS24 EQU M RS23 EQU M RS22 EQU 7 SFFFFB6 SFFFFB5 SFFFFB4 SFFFFB3 SFFFFAA SFFFFA9 SFFFFA8 SFFFFA6 SFFFFAS SFFFFA4 SFFFFA3 SFFFFA2 SFFFFAL
398. r X 28 1 Z amp 26 BC 6 D 4 bidir X 28 1 Z amp 27 BC 6 D 3 bidir X 28 17 2 amp DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 4 Freescale Semiconductor JTAG BSDL 28 BC 1 control 1 amp 29 BC 6 D 2 bidir X 28 15 2 amp 30 BC 6 D 13 4 bidir X 28 l1 2 amp 31 BC 6 D 0 bidir X 28 1 2 amp 1 32 1 17 output3 X 35 l1 2 amp 1 33 1 16 output3 X 35 1 2 amp 34 1 15 output3 ac 35 l 2 amp 35 BC 1 control 1 amp 36 BC 1 A 14 output3 Ky 357 15 7 amp 137 1 13 output3 X 35 l 2 amp 38 BC 1 A 12 output3 22 35 T Z amp 39 BC 1 A 11 output3 X 35 T Z amp num cell port func safe ccell dis rslt 40 1 10 output3 X 35 i 2 amp 41 1 9 output3 X 35 T Z amp 42 BC 1 A 8 output3 X 45 Ll 7 amp 43 BC 1 A 7 output3 X 45 gt 2 amp 44 BC 1 A 6 output3 X 45 T Z amp 45 BC y control 1 amp 46 BC 1 A 5 output3 X 45 Ly Z amp 47 1 4 output3 X 45 Ly Z amp 48 BC 1 A 3 output3 X 45 l1 2 amp 49 BC 1 A 2 output3 X 45 T 2 amp 50 BC 1 A 1 output3 X 45 l1 2 amp ET BC 1 A 0 output3 X 45 T 2 amp 52 BC 1 input amp 53 BC 157 control
399. r Manual Rev 4 Freescale Semiconductor 7 19 SHI Programming Considerations If a write to HTX occurs its contents are transferred to IOSR between data word transfers The IOSR data is shifted out via MISO and received data is shifted in via MOST The DSP may write HTX with either DSP instructions or DMA transfers if the HTDE status bit is set If no writes to HTX occur the contents of HTX are not transferred to IOSR so the data shifted out when receiving 15 the data present in the IOSR at the time The HRX FIFO contains valid receive data which the DSP can read with either DSP instructions or DMA transfers 1f the HRNE status bit is set The HREQ output pin if enabled for receive HRQE 1 0 01 is asserted when the IOSR is ready for receive and the HRX FIFO is not full this operation guarantees that the next received data word is stored in the FIFO The HREQ output pin if enabled for transmit HRQE 1 0 10 is asserted when the IOSR is loaded from HTX with a new data word to transfer If HREQ 15 enabled for both transmit and receive HRQE 1 0 11 it 15 asserted when the receive and transmit conditions are both true HREQ is deasserted at the first clock pulse of the next data word transfer The HREQ line may be used to interrupt the external master device Connecting the HREQ line between two SHI equipped DSPs one operating as an SPI master device and the other as an SPI slave device enables full hardware handshaking if oper
400. r and transmitter sections of the ESAI operate synchronously or asynchronously with respect to each other see Figure 8 11 When SYN is cleared the asynchronous mode is chosen and independent clock and frame sync signals are used for DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 8 32 Freescale Semiconductor ESAI Programming Model the transmit and receive sections When SYN is set the synchronous mode is chosen and the transmit and receive sections use common clock and frame sync signals When in the synchronous mode SYN 1 the transmit and receive sections use the transmitter section clock generator as the source of the clock and frame sync for both sections Also the receiver clock pins SCKR FSR and HCKR now operate as I O flags See Table 8 7 Table 8 8 and Table 8 9 for the effects of SYN on the receiver clock pins 8 3 5 6 SAICR Transmit External Buffer Enable TEBE Bit 7 The Transmitter External Buffer Enable TEBE bit controls the function of the FSR pin when in the synchronous mode If the ESAI is configured for operation in the synchronous mode SYN 1 and TEBE is set while FSR pin is configured as an output RFSD 1 the FSR pin functions as the transmitter external buffer enable control to enable the use external buffers on the transmitter outputs If TEBE 15 cleared then the FSR pin functions as the serial I O flag 1 See Table 8 8 for a summary of the effects of TEBE on the FSR pin 8 3 5 7
401. r disabled After RESET de assertion and during normal instruction processing the PINIT NMI Schmitt trigger input is a negative edge triggered nonmaskable interrupt NMI request internally synchronized to internal system clock This input cannot tolerate 5 V DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 2 4 Freescale Semiconductor External Memory Expansion Port Port A 2 5 External Memory Expansion Port Port A When the DSP56364 enters a low power standby mode stop or wait it releases bus mastership and tri states the relevant port A signals AO A17 DO 023 50 AA2 RAS2 RD WR BB CAS 2 5 1 External Address Bus Table 2 5 External Address Bus Signals State during Reset Signal Description Signal Name Type 0 17 Output Tri stated Address Bus When the DSP is the bus master A17 are active high outputs that specify the address for external program and data memory accesses Otherwise the signals are tri stated To minimize power dissipation A17 do not change state when external memory spaces are not being accessed 2 5 2 External Data Bus Table 2 6 External Data Bus Signals Signal Name Type State during Reset Signal Description 00 023 Input Output Tri stated Data Bus When the DSP is the bus master DO D23 are active high bidirectional input outputs that provide the bidirectional data bus
402. r is acknowledged it should transmit the next data byte In order to terminate the receive session the programmer should set the HIDLE bit at the last required data word As a result the last byte of the next received data word is not acknowledged the slave transmitter releases the SDA line and the SHI generates the stop event and terminates the session In a receive session only the receive path is enabled and the HTX to IOSR transfers are inhibited If the HRNE status bit is set the HRX FIFO contains valid data which may be read by the DSP with either DSP instructions or DMA transfers When the HRX FIFO is full the SHI suspends the serial clock just before acknowledge In this case the clock 15 reactivated when the FIFO is read the SHI gives an 0 and proceeds receiving 7 7 4 2 Transmit Data In I2C Master Mode A transmit session is initiated if the R W direction bit of the transmitted slave device address byte is cleared Following a transmit initiation the IOSR is loaded from HTX assuming HTX is not empty and its contents are shifted out MSB first on the SDA line Following each transmitted byte the SHI controller samples the SDA line at the ninth clock pulse and inspects the ACK status If the transmitted byte was acknowledged ACK 0 the SHI controller continues transmitting the next byte However if it was not acknowledged ACK 1 the HBER status bit is set to inform the DSP side that a bus error or overrun or any
403. ram as 0 PCn 0 amp PDCn 0 Port pin PDn disconnected PCn 1 amp PDCn 0 gt Port pin PDn configured as input PCn 0 amp PDCn 1 Port pin PDn configured as output PCn 1 amp PDCn 1 gt Port pin configured as X Read Write Reset 5 4 Port D GPIO Data PBRD 22 PDRD H 01010 eserved Program as 0 If port pin n is GPIO input then PDn reflects the value on port pin n if port pin n is GPIO output then value written to PDn is reflected on port pin n Figure D 35 GPIO Port D DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 D 50 Freescale Semiconductor Programming Sheets Application Date G Port E ESAI 1 23 11 40 9 Port E Control Register H 522 Programmer Sheet 4 of 4 Y FFFF9F Read Write Reset 0 Reserved Program as 0 ll 10 9 5 4 3 2 1 Port E Direction Register epee Ies Read Write Reset 0 P uM Program as 0 PCn 0 amp PDCn 0 Port pin PEn disconnected PCn 1 amp PDCn 0 Port pin PEn configured as input PCn 0 amp PDCn 1 Port pin PEn configured as output PCn 1 amp PDCn 1 Port pin configured as ESAI 1 Port E GPIO Data Register PDRE Y FFFF9D Read Write Reset undefined eserved Program as 0 If port pin n is GPIO input then PDn reflects the value on port pin n if port pin n is GPIO output then value written to PDn
404. ransfers clears the HTDE flag The DSP may program the HTIE bit to cause a host transmit data interrupt when HTDE is set see Section 7 4 6 10 HCSR Transmit Interrupt Enable HTIE Bit 11 Data should not be written to the HTX until HTDE is set in order to prevent overwriting the previous data HTX is reset to the empty state when in stop mode and during hardware reset software reset and individual reset In the 8 bit data transfer mode the most significant byte of the HTX is transmitted in the 16 bit mode the two most significant bytes and in the 24 bit mode all the contents of HTX is transferred 7 4 3 SHI Host Receive Data FIFO HRX DSP Side The 24 bit host receive data FIFO HRX is a 10 word deep First In First Out FIFO register used for Host to DSP data transfers The serial data is received via the shift register and then loaded into the HRX In the 8 bit data transfer mode the most significant byte of the shift register is transferred to the HRX the other bits are cleared in the 16 bit mode the two most significant bytes are transferred the least significant byte is cleared and in the 24 bit mode all 24 bits are transferred to the HRX The HRX may be read by the DSP while the FIFO is being loaded from the shift register Reading all data from HRX clears the HRNE flag The HRX may be read by DSP core instructions or by DMA transfers The HRX FIFO is reset to the empty state when the chip is in stop mode and during hardware
405. ration are updated Ifthe programmer reads any of those status bits within the next two cycles the bit will not reflect its current status See the DSP56300 Family Manual Freescale publication DSP56300FM for further details 6 5 3 Host Control Register HCR HCR is 16 bit read write control register used by the DSP core to control the HDIO08 operating mode The initialization values for the HCR bits are described in Section 6 5 9 DSP Side Registers After Reset The HCR bits are described in the following paragraphs 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HDM2 2 HTIE Reserved bit Read as 0 Should be written with O for future compatibility Figure 6 2 Host Control Register X FFFFC2 6 5 3 1 HCR Host Receive Interrupt Enable HRIE Bit 0 The HRIE bit is used to enable the host receive data interrupt request When the host receive data full status bit in the host status register HSR is set a host receive data interrupt request occurs if HRIE is set If HRIE is cleared HRDF interrupts are disabled 6 5 3 2 HCR Host Transmit Interrupt Enable HTIE Bit 1 The HTIE bit is used to enable the host transmit data empty interrupt request When the host transmit data empty HTDE status bit in the HSR is set a host transmit data interrupt request occurs if HTIE is set If HTIE is cleared HTDE
406. receive even slot data interrupts are enabled If REDIE is cleared the receive even slot data interrupts are disabled A receive even slot data interrupt request is generated if REDIE is set and the status flag in the SAISR status register is set Even time slots are all even numbered time slots 0 2 4 etc when operating in network mode The zero time slot is marked by the frame sync signal and is considered to be even Reading all the data registers of the enabled receivers clears the REDF flag thus servicing the interrupt Receive interrupts with exception have higher priority than receive even slot data interrupts therefore if exception occurs ROE is set and REIE is set the ESAI requests an ESAI receive data with exception interrupt from the interrupt controller 8 3 4 15 RCR Receive Interrupt Enable RIE Bit 22 The DSP is interrupted when RIE and the RDF flag in the SAISR status register are set When RIE is cleared this interrupt is disabled Reading the receive data registers of the enabled receivers clears RDF thus clearing the interrupt Receive interrupts with exception have higher priority than normal receive data interrupts therefore if exception occurs ROE is set and REIE is set the ESAI requests an ESAI receive data with exception interrupt from the interrupt controller 8 3 4 16 RCR Receive Last Slot Interrupt Enable Bit 23 RLIE enables an interrupt after the last slot of a frame ended in netwo
407. red as GPIO pin according to the value of HDDR and HDR registers 6 5 6 5 HPCR Host Request Enable HREN Bit 4 The HREN bit controls the host request signals If HREN is set and the HDIOS is in the single host request mode HDRQ 0 in the ICR HOREQ HTRQ is configured as the host request HOREQ output If HREN is set in the double host request mode HDRQ 1 in the ICR HOREQ HTRQ is configured as the host transmit request HTRQ output and HACK HRRQ as the host receive request HRRQ output If HREN is cleared HOREQ HTRQ and HACK HRRQ are configured as GPIO pins according to the value of HDDR and HDR registers 6 5 6 6 HPCR Host Acknowledge Enable HAEN Bit 5 The HAEN bit controls the HACK signal In the single host request mode HDRQ 0 in the ICR if HAEN and HREN are both set HACK HRRQ is configured as the host acknowledge HACK input If HAEN or HREN is cleared HACK HRRQ is configured as a GPIO pin according to the value of HDDR and HDR registers In the double host request mode HDRQ 1 in ICR HAEN is ignored 6 5 6 7 HPCR Host Enable HEN Bit 6 If the HEN bit is set the HDIOS operation is enabled as Host Interface If cleared the HDIOS is not active and all the HDIOS pins are configured as GPIO pins according to the value of HDDR and HDR registers 6 5 6 8 HPCR Reserved Bit 7 This bit is reserved It reads as zero and should be written with zero for future compatibility DSP56366 24 Bit Digital Signal Processor User M
408. red in the FIFO by two consecutive MOVEP instructions to XADR Ifthe non audio bits are not changed from frame to frame this procedure can be handled within a fast interrupt routine Storing the next frame s audio data in the FIFO clears the XADE bit in the XSTR 10 6 3 Block Transferred Interrupt Handling An interrupt with the XBLK vector indicates the end of a block transmission and may require some computation to provide the next non audio data structures that are to be transmitted within the next block Within the routine the next audio data can be stored in the FIFO by two consecutive MOVEP instructions to XADR and the next non audio data can be stored in the XNADR XBLK interrupt occurs only if the XBIE bit in XCTR is set If XBIE is cleared a XADE interrupt vector will take place 10 6 4 DAX operation with DMA During DMA transfers the XDIE bit of the XCTR must be cleared to avoid XADE interrupt services by the DSP core The initialization appearing in Section 10 6 1 Initiating A Transmit Session is relevant for DMA operation DMA transfers can be performed with or without changing non audio bits from frame to frame Table 10 5 describes two examples of DMA configuration Table 10 5 Examples of DMA configuration Register Non audio data bits change Non audio data bits do not change DCR2 DE 1 Enable DMA channel DE 1 Enable DMA channel DIE 1 Enable DMA interrupt DIE 1 Enable DMA interrupt DTM
409. register when the HACK signal is high 6 5 7 Data direction register HDDR The HDDR controls the direction of the data flow for each of HDIOS pins configured as Even when the HDIOS is used as the host interface some of its unused signals may be configured as GPIO pins For information on the HDI08 GPIO configuration options see Section 6 6 8 General Purpose INPUT OUTPUT GPIO If bit DRxx is set the corresponding HDI08 pin is configured as an output signal If bit DRxx is cleared the corresponding HDIOS pin is configured as an input signal See Table 6 6 DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 6 15 HDIO8 DSP Side Programmer s Model 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DR15 DR14 DR13 DR12 DR11 DR10 DR9 DR8 DR7 DR6 DRS DRA DR3 DR2 DR1 DRO Figure 6 9 Host Data Direction Register HDDR X FFFFC8 6 5 8 Host Data Register HDR The HDR register holds the data value of the corresponding bits of the HDI08 pins which are configured as GPIO pins The functionality of the Dxx bit depends on the corresponding HDDR bit DRxx See Table 6 6 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 015 014 013 012 011 010 09 08 07 06 05 04 03 02 01 00 Figure 6 10 Host Data Register X FFFFC9 Table 6 6 HDR and HDDR Functi
410. reload operation In timer 0 3 and watchdog 9 10 modes the counter is preloaded with the TLR value after the TE bit is set and the first internal or external clock signal is received If the TRM bit is set the counter is reloaded each time after it reaches the value contained by the TCR In PWM mode 7 the counter is reloaded each time counter overflow occurs In measurement 4 5 modes if the and the TE bits are set the counter is preloaded with the TLR value on each appropriate edge of the input signal If the TRM bit is cleared the counter operates as a free running counter and is incremented on each incoming event The TRM bit is cleared by the hardware RESET signal or the software RESET instruction 11 3 4 7 TCSR Direction DIR Bit 11 The DIR bit determines the behavior of the TIOO signal when it is used as a GPIO pin When the DIR bit is set the TIOO signal is an output when the DIR bit is cleared the TIOO signal is an input The TIOO signal can be used as a only when the TC 3 0 bits are all cleared If any of the TC 3 0 bits are set then the GPIO mode is disabled and the DIR bit has no effect The DIR bit is cleared by the hardware RESET signal or the software RESET instruction This bit is not in use for timers 1 and 2 It should be left cleared 11 3 4 8 Data Input DI Bit 12 The DI bit reflects the value ofthe TIOO signal If the INV bit is set the value ofthe TIOO signal is inverted
411. request input during normal instruction processing MODA MODB MODC and MODD select one of 16 initial chip operating modes latched into OMR when the RESET signal is deasserted This input is 5 V tolerant MODD IRQD Input Input Mode Select D External Interrupt Request D MODD IRQD is an active low Schmitt trigger input internally synchronized to the DSP clock MODD IRQD selects the initial chip operating mode during hardware reset and becomes a level sensitive or negative edge triggered maskable interrupt request input during normal instruction processing MODA MODB MODC and MODD select one of 16 initial chip operating modes latched into OMR when the RESET signal is deasserted This input is 5 V tolerant RESET Input Input Reset RESET is an active low Schmitt trigger input When asserted the chip is placed in the Reset state and the internal phase generator is reset The Schmitt trigger input allows a slowly rising input such as a capacitor charging to reset the chip reliably When the RESET signal is deasserted the initial chip operating mode is latched from the MODA MODB and MODD inputs The RESET signal must be asserted during power up A stable EXTAL signal must be supplied while RESET is being asserted This input is 5 V tolerant DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 2 8 Freescale Semiconductor 2 7 PARALLEL HOST INTERFACE HDIO8 PARALLE
412. reserved They read as zero and should be written with zero for future compatibility 6 6 3 7 ISR Host Request HREQ Bit 7 The HREQ bit indicates the status of the external host request output signal HOREQ if HDRQ is cleared If HDRQ is set it indicates the status of the external transmit and receive request output signals HTRQ and HRRQ Table 6 14 Host Request Status HREQ HREQ Status HDRQ 0 Status HDRQ 1 0 HOREQ deasserted no host processor interrupt is HTRQ and deasserted no host processor requested interrupts are requested 1 HOREQ asserted a host processor interrupt is HTRQ and or HRRQ asserted host processor requested interrupts are requested The HREQ bit may be set from either or both of two conditions either the receive byte registers are full or the transmit byte registers are empty These conditions are indicated by the ISR RXDF and TXDE status bits respectively If the interrupt source has been enabled by the associated request enable bit in the ICR HREQ is set if one or more of the two enabled interrupt sources is set DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 6 25 HDIO8 External Host Programmer s Model 6 6 4 Interrupt Vector Register IVR The IVR is an 8 bit read write register which typically contains the interrupt vector number used with 68000 Family processor vectored interrupts Only the host processor can read an
413. reset software reset and individual reset 7 4 4 SHI Slave Address Register HSAR DSP Side The 24 bit slave address register HSAR is used when the SHI operates in the slave mode and is ignored in the other operational modes HSAR holds five bits of the 7 bit slave device address The SHI also acknowledges the general call address specified by the protocol eight zeroes comprising a 7 bit address and a R W bit but treats any following data bytes as regular data That is the SHI does not differentiate between its dedicated address and the general call address HSAR cannot be accessed by the host processor DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 7 6 Freescale Semiconductor Serial Host Interface Programming Model 7 4 4 1 HSAR Reserved Bits Bits 19 17 0 These bits are reserved They read as zero and should be written with zero for future compatibility 7 4 4 2 HSAR Slave Address HA 6 3 HA1 Bits 23 20 18 Part of the slave device address is stored in the read write HA 6 3 HAI bits of HSAR The full 7 bit slave device address is formed by combining the HA 6 3 bits with the HAO and HA2 pins to obtain the HA 6 0 slave device address The full 7 bit slave device address is compared to the received address byte whenever an master device initiates an ZC bus transfer During hardware reset or software reset HA 6 3 1011 and HA1 is cleared this results in a default slave
414. ress or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document Freescale Semiconductor reserves the right to make changes without further notice to any products herein Freescale Semiconductor makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters that may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Freescale Semiconductor does not convey any license under its patent rights nor the rights of others Freescale Semiconductor products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur Should Buyer purchase or use Freescale Semicond
415. rial Data Input 3 Port C 9 When the ESAI is configured as GPIO this signal is individually programmable as input output or internally disconnected When enabled for ESAI_1 GPIO this is the Port E 9 signal The default state after reset is GPIO disconnected This input is 5 V tolerant 001 SDO1 1 PC10 PE10 Output Input output or disconnected GPIO disconnected Serial Data Output 1 SDO 1 is used to transmit data from the TX1 serial transmit shift register When enabled for ESAI 1 operation this is the ESAI 1 Serial Data Output 1 Port C 10 When the ESAI is configured as GPIO this signal is individually programmable as input output or internally disconnected When enabled for ESAI 1 GPIO this is the Port E 10 signal The default state after reset is GPIO disconnected This input is 5 V tolerant 000 SDOO 1 PC11 PE11 Output Input output or disconnected GPIO disconnected Serial Data Output 0 SDOO is used to transmit data from the TXO serial transmit shift register When enabled for ESAI 1 operation this is the ESAI 1 Serial Data Output 0 Port C 11 When the ESAI is configured as GPIO this signal is individually programmable as input output or internally disconnected When enabled for ESAI_1 GPIO this is the Port E 11 signal The default state after reset is GPIO disconnected This input is 5 V tolerant DSP56366 24 Bit Digital
416. rk mode only When RLIE is set the DSP is interrupted after the last slot in a frame ended regardless ofthe receive mask register setting When RLIE is cleared the receive last slot interrupt is disabled Hardware and software reset clear RLIE RLIE is disabled when RDC 4 0 00000 on demand mode The use of the receive last slot interrupt is described in Section 8 4 3 ESAI Interrupt Requests 8 3 5 ESAI Common Control Register SAICR The read write Common Control Register SAICR contains control bits for functions that affect both the receive and transmit sections of the ESAI See Figure 8 10 DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 8 31 ESAI Programming Model 11 10 9 8 7 6 5 4 3 2 1 0 X FFFFB4 ALC TEBE SYN OF2 OF1 OFO 23 22 21 20 19 18 17 16 15 14 13 12 Reserved bit read as zero should be written with zero for future compatibility Figure 8 10 SAICR Register Hardware and software reset clear all the bits in the SAICR register 8 3 5 1 SAICR Serial Output Flag 0 Bit The Serial Output Flag 0 is data bit used to hold data to be send to the OFO pin When the ESAI is in the synchronous clock mode SYN 1 the SCKR pin is configured as the ESAI flag 0 If the receiver serial clock direction bit RCKD is set the SCKR pin is the output flag and data
417. rnal Interrupt DMA Channel 0 Interrupt DMA Channel 1 Interrupt DMA Channel 2 Interrupt DMA Channel 3 Interrupt DMA Channel 4 Interrupt DMA Channel 5 Interrupt ESAI Receive Data with Exception Status ESAI Receive Even Data ESAI Receive Data ESAI Receive Last Slot ESAI Transmit Data with Exception Status ESAI Transmit Last Slot ESAI Transmit Even Data ESAI Transmit Data SHI Bus Error SHI Receive Overrun Error SHI Transmit Underrun Error DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor Interrupt Priority Registers Table 4 5 Interrupt Sources Priorities Within an IPL continued Priority Interrupt Source SHI Receive FIFO Full SHI Transmit Data SHI Receive FIFO Not Empty HOST Command Interrupt HOST Receive Data Interrupt HOST Transmit Data Interrupt DAX Transmit Underrun Error DAX Block Transferred DAX Transmit Register Empty TIMERO Overflow Interrupt TIMERO Compare Interrupt TIMER1 Overflow Interrupt TIMER1 Compare Interrupt TIMER2 Overflow Interrupt TIMER2 Compare Interrupt ESAI_1 Receive Data with Exception Status 5 1 Receive Even Data ESAI 1 Receive Data ESAI_1 Receive Last Slot ESAI 1 Transmit Data with Exception Status ESAI 1 Transmit Last Slot ESAI 1 Transmit Even Data
418. rnally disabled until the next frame sync Frames do not have to be adjacent i e a new frame sync does not have to immediately follow the previous frame Gaps of arbitrary periods can occur between frames Enabled transmitters are tri stated during these gaps When operating in the synchronous mode SYN 1 all clocks including the frame sync are generated by the transmitter section 8 4 4 4 Shift Direction Selection Some data formats such as those used by codecs specify MSB first while other data formats such as the AES EBU digital audio interface specify LSB first The MSB LSB first selection is made by programming RSHFD bit in the RCR register for the receiver section and by programming the TSHFD bit in the TCR register for the transmitter section 8 4 5 Serial Flags Three ESAI pins FSR SCKR and HCKR are available as serial I O flags when the ESAI is operating in the synchronous mode SYN 1 Their operation is controlled by RCKD RFSD TEBE bits in the RCR DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 8 46 Freescale Semiconductor GPIO Pins and Registers RCCR and SAICR registers The output data bits OF2 and and the input data bits 122 IF1 and are double buffered to from the HCKR FSR and SCKR pins Double buffering the flags keeps them in sync with the TX and RX data lines Each flag can be separately programmed Flag 0 SCKR pin direction is selected by RCKD RCKD 1
419. rom the interrupt controller HBIE is cleared by hardware reset and software reset NOTE Clearing HBIE masks a pending bus error interrupt only after a one instruction cycle delay If HBIE is cleared in a long interrupt service routine it is recommended that at least one other instruction separate the instruction that clears HBIE and the RTI instruction at the end of the interrupt service routine 7 4 6 10 Transmit Interrupt Enable HTIE Bit 11 The read write control bit HTIE is used to enable the SHI transmit data interrupts If HTIE is cleared transmit interrupts are disabled and the HTDE status bit must be polled to determine if HTX is empty If both HTIE and HTDE are set and HTUE is cleared the SHI requests an SHI transmit data interrupt service from the interrupt controller If both HTIE and HTUE are set the SHI requests an SHI DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 7 13 Serial Host Interface Programming Model transmit underrun error interrupt service from the interrupt controller HTIE is cleared by hardware reset and software reset NOTE Clearing HTIE masks a pending transmit interrupt only after a one instruction cycle delay If HTIE is cleared in a long interrupt service routine it is recommended that at least one other instruction separate the instruction that clears HTIE and the RTI instruction at the end of the interrupt service routine 7 4 6 11 HCSR Rec
420. rrectly identified the slave device address byte is acknowledged ACK 0 is sent and receive transmit session is initiated according to the eighth bit of the received slave device address byte i e the R W bit 7 7 3 1 Receive Data in 12 Slave Mode A receive session is initiated when the personal slave device address has been correctly identified and the R W bit of the received slave device address byte has been cleared Following a receive initiation data in the SDA line is shifted into IOSR MSB first Following each received byte an acknowledge ACK 0 is sent at the ninth clock pulse via the SDA line Data is acknowledged bytewise as required by the bus protocol and is transferred to HRX FIFO when the complete word according to HM 1 0 is filled into IOSR It is the responsibility of the programmer to select the correct number of bytes in an frame so that they fit in a complete number of words For this purpose the slave device address byte does not count as part of the data therefore it is treated separately DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 7 21 SHI Programming Considerations In a receive session only the receive path is enabled and HTX to IOSR transfers are inhibited The HRX FIFO contains valid data which may be read by the DSP with either DSP instructions or DMA transfers if the status bit is set If HCKFR is cleared when the HRX FI
421. rrupt enabled 1 TREQ Transmit Request Enable 0 HTRQ interrupt disabled 0 1 HTRQinterrupt enabled 2 HDRQ Double Host Request 0 HOREQ HTRQ HOREQ available if 0 HACK HRRQ HACK HDM2 HDMO0 000 1 HOREQ HTRQ HTRQ HACK HRRQ HRRQ 3 HFO Host Flag 0 0 4 1 Host Flag 1 0 5 HLEND Host Little Endian 0 Big Endian order available if 0 1 Little Endian order HDM2 HDMO0 000 6 5 HM1 HMO Host Mode Control 00 Interrupt Mode available if 00 01 24 bit DMA enabled HDM2 HDMO 100 10 16 bit DMA enabled 11 8 bit DMA enabled 7 INIT Initialize 1 Reset data paths according to cleared by HDIO8 0 TREQ and RREQ hardware DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 D 14 Freescale Semiconductor Programming Sheets Table 0 4 HDI08 Programming Model continued Bit Reset Type Reg Comments HW Num Mnemonic Name Val Function SW IR ST ISR 0 RXDF Receive Data Register Full 0 hostreceive register is empty 0 0 0 1 host receive register is full 1 TXDE Transmit Data Register 1 host transmit register empty 1 1 1 Empty o host transmit register full 2 TRDY Transmitter Ready 1 transmit 6 deep is empty 1 1 1 transmit FIFO is not empty 0 3 HF2 Host Flag2 0 5 4 HF3 Host Flag3 0 7 Host Request 0 HOREQ pin is deasserted 0 0 0 1 pin is asserted if enabled CVR 6 0 HV6 HVO Host Co
422. rt Enable HOST Address 8 Enable HOST Address 9 Enable DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 B 30 Freescale Semiconductor Equates M HCSEN EQU 3 HOST Chip Select Enable M HREN EQU 4 HOST Request Enable M HAEN EQU 5 HOST Acknowledge Enable M HOEN EQU 6 HOST Enable M HROD EQU 8 HOST Request Open Dranin mode M HDSP EQU 9 HOST Data Strobe Polarity M HASP EQU a HOST Address Strobe Polarity M HMUX EQU b HOST Multiplexed bus select M HDDS EQU c HOST Double Single Strobe select M HCSP EQU d HOST Chip Select Polarity M HRP EQU e HOST Request Polarity M HAP EQU Sf HOST Acknowledge Polarity HBAR BITS M BA EQU SFF M BA10 EQU 7 9 EQU 6 EQU 5 M BA7 EQU 4 M 6 EQU 3 M BA5 EQU 2 M BA4 EQU 1 M EQU 0 EQUATES for TIMER Register Addresses Of TIMERO DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor B 31 Equates M TCSRO M TLRO M TCPRO M TCRO M TCSR1 M M TCPR1 M TCR1 M TCSR2 M TLR2 M TCPR2 M TCR2 M TPLR M TPCR M TOIE M TCIE EQU EQU EQU EQU SFFFF8F TIMERO Control Status Register SFFFF8E TIMERO Load Reg SFFFF8D TIMERO Compare Register SFFFF8C TIMERO Count Register Register Addresses Of TIMER1 EQU EQU EQU EQU SFFFF8B TIMER1 Control Status Register SFFFF8A TIMER1 Load Reg SFFFF89 TIMER1 Compare R
423. rved Y FFFFA9 Reserved Y FFFFA8 Reserved Y FFFFA7 Reserved Y FFFFA6 Reserved 5 Reserved Y FFFFA4 Reserved Y FFFFA3 Reserved Y FFFFA2 Reserved Y FFFFA1 Reserved Y FFFFAO Reserved PORTE Y FFFF9F PORT E CONTROL REGISTER PCRE PORT E DIRECTION REGISTER PPRE Y FFFF9D PORT E GPIO DATA REGISTER PDRE DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor Internal Memory Map Table 3 4 Internal Memory Map continued Peripheral Address Register Name ESAI 1 Y FFFF9C ESAI_1 RECEIVE SLOT MASK REGISTER B RSMB_1 Y FFFF9B ESAI 1 RECEIVE SLOT MASK REGISTER A RSMA 1 Y FFFF9A ESAI 1 TRANSMIT SLOT MASK REGISTER B TSMB 1 Y FFFF99 ESAI 1 TRANSMIT SLOT MASK REGISTER A TSMA 1 Y FFFF98 ESAI 1 RECEIVE CLOCK CONTROL REGISTER RCCR Y FFFF97 ESAI 1 RECEIVE CONTROL REGISTER 1 Y FFFF96 ESAI 1 TRANSMIT CLOCK CONTROL REGISTER TCCR 1 Y FFFF95 ESAI 1 TRANSMIT CONTROL REGISTER TCR 1 Y FFFF94 ESAI 1 COMMON CONTROL REGISTER 5 1 Y FFFF93 ESAI 1 STATUS REGISTER SAISR 1 Y FFFF92 Reserved Y FFFF91 Reserved Y FFFF90 Reserved Y FFFF8F Reserved Y FFFF8E Reserved Y FFFF8D Reserved Y FFFF8C Reserved Y FFFF8B ESAI 1 RECEIVE DATA REGISTER 3 RX3 1 Y FFFF8A ESAI 1 RECEIVE DATA REGISTER 2 RX2 1 Y FFFF89 ESAI_1 RECEIVE DATA REGISTER 1 RX1_1 Y FFFF88 ESAI_1 RECEIVE DATA REGISTER 0 RXO 1 Y FFFF87 Reserved Y FFFF86 ESA
424. s From now on ESAI can be serviced either by polling interrupts or DMA Operation proceeds as follows For internally generated clock and frame sync these signals are active immediately after ESAI 15 enabled step 3 above Datais received only when one of the receive enable REx bits is set and after the occurrence of frame sync signal either internally or externally generated Datais transmitted only when the transmitter enable TEx bit is set and after the occurrence of frame sync signal either internally or externally generated The transmitter outputs remain tri stated after TEx bit 15 set until the frame sync occurs 8 6 2 Initializing Just the ESAI Transmitter Section 115 assumed that the ESAI is operational that is at least one is defined as ESAI pin transmitter section should be in its personal reset state 1 DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 8 49 ESAI Initialization Examples 8 6 3 Configure the control registers TCCR and TCR according to the operating mode making sure to clear the transmitter enable bits TES TPR must remain set Take the transmitter section out of the personal reset state by clearing TPR Write first data to the transmitters which will be used during operation This step is needed even if DMA is used to service the transmitters Enable the transmitters by setting their TE bits
425. s to Compare Bits 1 M BAC2 EQU 14 Address to Compare Bits 2 M BAC3 EQU 15 Address to Compare Bits 3 M EQU 16 Address to Compare Bits 4 M BAC5 EQU 17 Address to Compare Bits 5 M BAC6 EQU 18 Address to Compare Bits 6 7 EQU 19 Address to Compare Bits 7 M BAC8 EQU 20 Address to Compare Bits 8 M BAC9 EQU 21 Address to Compare Bits 9 M BAC10 EQU 22 Address to Compare Bits 10 M 11 EQU 23 Address to Compare Bits 11 control and status bits in SR M C EQU Carry M V EQU 1 Overflow 2 2 Zero MN EQU 3 Negative MU EQU 4 Unnormalized ME EQU 5 Extension ML EQU 6 Limit DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor B 15 Equates M CDP M CDPO EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU 7 Scaling Bit 8 Interupt Mask Bit 0 9 Interupt Mask Bit 1 10 Scaling Mode Bit O 11 Scaling Mode Bit 1 13 Sixteen Bit Compatibility 14 Double Precision Multiply 15 DO Loop Flag 16 DO Forever Flag 17 Sixteen Bit Arithmetic 19 Instruction Cache Enable 20 Arithmetic Saturation 21 Rounding Mode c00000 mask for CORE DMA priority bits in SR 22 bit 0 of priority bits in SR 23 bit 1 of priority bits in SR control and status bits in OMR EQU EQU EQU 0 Operating Mode A 1 Operating Mode B 2 Operating Mode C
426. s transferred to XADSR at the same time that the three bits of non audio data V bit U bit and C bit for channel A in the DAX non audio data register are transferred to the three highest order bits of the XADSR At the beginning of the channel B transmission audio and non audio data for channel B are transferred from the XADBUFB and the XNADBUF to the XADSR for shifting The data in the XADSR is shifted toward the lowest order bit at the fifth to thirty first bit slot of each subframe transmission This register 1s not directly accessible by DSP instructions 10 5 4 DAX Non Audio Data Register XNADR The XNADR is a 24 bit write only register It holds the three bits of non audio data for each subframe XNADR can be accessed by core instructions or by DMA The contents of the XNADR are shown in Figure 10 2 XNADR is not affected by any of the DAX reset states The XNADR bits are described in the following paragraphs 10 5 4 1 DAX Channel A Validity XVA Bit 10 The value of the XVA bit is transmitted as the twenty ninth bit Bit 28 of channel A subframe in the next frame DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 10 5 DAX Internal Architecture 10 5 4 Channel A User Data XUA Bit 11 The value of the XUA bit is transmitted as the thirtieth bit Bit 29 of the channel A subframe in the next frame 10 5 4 3 DAX Channel A Channel Status XCA Bit 12 The value of t
427. sed to transfer data to from a single device For the network mode 2 to 32 time slots per frame may be selected During each frame 0 to 32 data words of I O may be received transmitted In either case the transfers are periodic The frame sync signal indicates the first time slot in the frame Network mode is typically used in time division multiplexed TDM networks of codecs DSPs with multiple words per frame or multi channel devices Selecting the network mode and setting the frame rate divider to zero DC 00000 selects the on demand mode This special case does not generate a periodic frame sync A frame sync pulse is generated only when data is available to transmit The on demand mode requires that the transmit frame sync be internal output and the receive frame sync be external input Therefore for simplex operation the synchronous mode could be used however for full duplex operation the asynchronous mode must be used Data transmission that is data driven is enabled by writing data into each TX Although the ESAI is double buffered only one word can be written to each TX even ifthe transmit shift register is empty The receive and transmit interrupts function as usual using TDE and RDF however transmit underruns are impossible for on demand transmission and are disabled 8 4 4 2 Synchronous Asynchronous Operating Modes The transmit and receive sections of the ESAI may be synchronous or asynchronous i e the transmitter a
428. served X FFFFCC Reserved X FFFFCB Reserved X FFFFCA Reserved PORT B 9 HOST PORT GPIO DATA REGISTER X FFFFC8 HOST PORT GPIO DIRECTION REGISTER HDDR DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 3 13 Internal Memory Map Table 3 4 Internal Memory Map continued Peripheral Address Register Name HDIO8 X FFFFC7 HOST TRANSMIT REGISTER HOTX X FFFFC6 HOST RECEIVE REGISTER HORX 5 HOST BASE ADDRESS REGISTER HBAR X FFFFC4 HOST PORT CONTROL REGISTER HPCR X FFFFC3 HOST STATUS REGISTER HSR 2 HOST CONTROL REGISTER HCR X FFFFC1 Reserved X FFFFCO Reserved PORT C X FFFFBF PORT C CONTROL REGISTER PCRC X FFFFBE PORT C DIRECTION REGISTER PRRC X FFFFBD PORT C GPIO DATA REGISTER DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 3 14 Freescale Semiconductor Internal Memory Table 3 4 Internal Memory Map continued Peripheral Address Register Name ESAI X FFFFBC ESAI RECEIVE SLOT MASK REGISTER B RSMB X FFFFBB ESAI RECEIVE SLOT MASK REGISTER A RSMA X FFFFBA ESAI TRANSMIT SLOT MASK REGISTER B TSMB X FFFFB9 ESAI TRANSMIT SLOT MASK REGISTER A TSMA X FFFFB8 ESAI RECEIVE CLOCK CONTROL REGISTER RCCR X FFFFB7 ESAI RECEIVE CONTROL REGISTER RCR X
429. signal The external clock is internally synchronized to the internal clock The external clock frequency must be lower than the DSP56366 internal operating frequency divided by 4 CLK 4 The PS 1 0 bits are cleared by the hardware RESET signal or the software RESET instruction NOTE To ensure proper operation change the PS 1 0 bits only when the prescaler counter is disabled Disable the prescaler counter by clearing the TE bit in the TCSR of each of three timers DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 11 5 Timer Event Counter Programming Model Table 11 1 Prescaler Source Selection PS1 PSO PRESCALER CLOCK SOURCE 0 0 Internal CLK 2 0 1 TIOO 1 0 Reserved 1 1 Reserved 11 3 2 3 Reserved Bit 23 This reserved bit is read as zero and should be written with zero for future compatibility 11 3 3 Timer Prescaler Count Register TPCR The TPCR is a 24 bit read only register that reflects the current value in the prescaler counter See Figure 11 5 23 22 21 20 19 18 17 16 15 14 13 12 20 19 PC18 17 16 PC15 14 PC13 PC12 11 10 9 8 7 6 5 4 3 2 1 0 PC11 PC10 PC9 PC8 PC7 PC6 5 PC2 PC1 PCO reserved read as 0 should be written with for future compatibility Figure 11 5 Time Prescaler Count Reg
430. simultaneous data receive and transmit The status bits of both receive and transmit paths are active however the programmer may disable undesired interrupts and ignore irrelevant status bits In a data transfer the HTX is transferred to IOSR clock pulses are generated the IOSR data is shifted out via MOSI and received data is shifted in via MISO The DSP programmer may write HTX if the HTDE status bit is set with either DSP instructions or DMA transfers to initiate the transfer of the next word The HRX FIFO contains valid receive data which the DSP can read with either DSP instructions or DMA transfers if the status bit is set DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 7 20 Freescale Semiconductor SHI Programming Considerations It is recommended that an SHI individual reset HEN cleared be generated before beginning data reception in order to reset the receive FIFO to its initial empty state e g when switching from transmit to receive data The HREQ input pin is ignored by the SPI master device if the HRQE 1 0 bits are cleared and considered if any of them is set When asserted by the slave device HREQ indicates that the external slave device is ready for the next data transfer As a result the SPI master sends clock pulses for the full data word transfer is deasserted by the external slave device at the first clock pulse of the new data transfer When deasserted HREQ prevents the c
431. smit Word Alignment Control TWA Bit 7 The Transmitter Word Alignment Control bit defines the alignment of the data word in relation to the slot This is relevant for the cases where the word length is shorter than the slot length If TWA is cleared the data word is left aligned in the slot frame during transmission If TWA is set the data word is right aligned in the slot frame during transmission Since the data word is shorter than the slot length the data word is extended until achieving the slot length according to the following rule 1 Ifthe data word is left aligned 0 and zero padding is disabled PADC 0 then the last data bit is repeated after the data word has been transmitted If zero padding is enabled PADC 1 Zeroes are transmitted after the data word has been transmitted DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 8 15 ESAI Programming Model 2 Ifthe data word is right aligned TWA 1 and zero padding is disabled PADC 0 then the first data bit is repeated before the transmission ofthe data word If zero padding is enabled PADC 1 Zeroes are transmitted before the transmission of the data word 8 3 2 9 TCR Transmit Network Mode Control TMOD1 TMODO Bits 8 9 The TMODI and bits are used to define the network mode of ESAI transmitters according to Table 8 4 In the normal mode the frame rate divider determines the word transfer rate
432. ssed by the DSP core The ISR bits are described in the following paragraphs 7 6 5 4 3 2 1 0 HREQ HF2 TRDY TXDE RXDF Reserved bit Read as 0 Should be written with O for future compatibility Figure 6 14 Interface Status Register ISR 6 6 3 1 ISR Receive Data Register Full RXDF Bit 0 The RXDF bit indicates that the receive byte registers RXH RXM RXL contain data from the DSP core and may be read by the host processor RXDF is set when the contents of HOTX is transferred to the receive byte registers RXDF is cleared when the receive data RXL or RXH according to HLEND bit register is read by the host processor RXDF can be cleared by the host processor using the initialize function RXDF may be used to assert the external signal if the RREQ bit is set Regardless of whether the RXDF interrupt is enabled RXDF indicates whether the RX registers are full and data can be latched out so that polling techniques may be used by the host processor 6 6 3 2 ISR Transmit Data Register Empty TXDE Bit 1 The TXDE bit indicates that the transmit byte registers TXH TXM TXL are empty and can be written by the host processor TXDE is set when the contents of the transmit byte registers are transferred to the HORX register TXDE 15 cleared when the transmit TXL or TXH according to HLEND bit register is DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 6 24 Freescale Semicondu
433. sserted between successive bytes within a word The DSP core should write the next data word to HTX when HTDE 1 clearing HTDE The HTX data is transferred to the shift register for transmission as soon as the shift register is empty HTDE is set when the data is transferred from HTX to the shift register When the SHI is in master mode and CPHA 0 the DSP core should write the next data word to HTX when HTDE 1 clearing HTDE The data is transferred immediately to the shift register for transmission HTDE is set only at the end of the data word transmission NOTE The master is responsible for deasserting and asserting the slave device SS line between word transmissions DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 7 8 Freescale Semiconductor Serial Host Interface Programming Model When the SHI is in master mode and CPHA 1 the DSP core should write the next data word to HTX when HTDE 1 clearing HTDE The HTX data is transferred to the shift register for transmission as soon as the shift register is empty HTDE 15 set when the data 15 transferred from HTX to the shift register 7 4 5 2 HCKR Prescaler Rate Select HRS Bit 2 The HRS bit controls a prescaler in series with the clock generator divider This bit is used to extend the range ofthe divider when slower clock rates are desired When HRS is set the prescaler is bypassed When HRS is cleared the fixed divide by eight prescaler is operational HRS is i
434. st be set otherwise no output is generated 8 3 13 Receive Slot Mask Registers RSMA RSMB The Receive Slot Mask Registers RSMA and RSMB are two read write registers used by the receiver in network mode to determine for each slot whether to receive a data word and generate a receiver full condition RDF 1 or to ignore the received data RSMA and should be considered as each containing half of a 32 bit register RSM See Figure 8 17 and Figure 8 18 Bit number N in RSM RS is an enable disable control bit for receiving data in slot number N 11 10 9 8 7 6 5 4 3 2 1 0 X FFFFBB RS11 RS10 RS9 RS8 RS7 RS6 RS5 RS4 RS2 RS1 RSO 23 22 21 20 19 18 17 16 15 14 13 12 RS15 RS14 RS13 RS12 Reserved bit read as zero should be written with zero for future compatibility Figure 8 17 RSMA Register 11 10 9 8 7 6 5 4 3 2 1 0 X FFFFBC RS27 RS26 RS25 RS24 RS23 RS22 RS21 RS20 RS19 RS18 RS17 RS16 23 22 21 20 19 18 17 16 15 14 13 12 RS31 RS30 RS29 RS28 Reserved bit read as zero should be written with zero for future compatibility Figure 8 18 RSMB Register When bit number N in the RSM register is cleared the data from the enabled receivers input pins are shifted into their receive shift registers during slot nu
435. stination Memory Space 1 M DAM EQU 3 0 DMA Address Mode Mask DAM5 DAMO M DAMO EQU 4 DMA Address Mode O0 M 1 EQU 5 DMA Address Mode 1 M DAM2 EQU 6 DMA Address Mode 2 M DAN3 EQU 7 DMA Address Mode 3 M DAMA EQU 8 DMA Address Mode 4 M DAM5 EQU 9 DMA Address Mode 5 M D3D EQU 10 DMA Three Dimensional Mode M DRS EQU SF800 DMA Request Source Mask DRSO DRS4 M_DRSO EQU 11 DMA Request Source bit 0 DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor B 9 Equates M DRS1 EQU M DRS2 EQU M DRS3 EQU DRS4 EQU M DCON EQU M DPR EQU M DIE EQU M DE EQU 12 13 14 15 16 60000 17 18 38000 19 20 21 22 23 DMA Request Source bit 1 DMA Request Source bit 2 DMA Request Source bit 3 DMA Request Source bit 4 DMA DMA DMA DMA 0 DMA DMA DMA DMA DMA DMA DMA Status Register M DTD EQU M DTDO EQU M EQU M EQU M EQU 3F 5 00 10 12 Continuous Mode Channel Priority Channel Priority Level low Channel Priority Level high Transfer Mode Mask DTM2 DTMO Transfer Mode 0 Transfer Mode 1 Transfer Mode 2 Interrupt Enable bit Channel Enable bit Channel Transfer Done Status MASK DTDO DTD5 DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA Channel Tr
436. sue ras Se 3554 2 3 GTO BQ 2 3 Clock BEL un s ertet d bres ade Re 2 4 External Memory Expansion 2 5 External Address BUS 2 5 Bx fetal Data BUS usuy z dd dE P a RR da 2 5 External Bus uas chet URS als Mew duel Vnde s huy eure e AA ger 2 5 Interrupt and Mode Controlere Fe 2 7 PARALLEL HOST INTERFACE HDIO8 2 9 Serial Host Interface xsi 9 ce Ss asa d e EROR a ae RC a u 2 12 Enhanced Serial Audio Interface o eo Pace DIAS AS ERR 2 15 Enhanced Serial Audio Interface 2 19 SPDIF Transmitter Digital Audio 2 2 TIMET aga a Gah Larne eite 2 22 JTAG ONCE Interface os lascio 2 22 Memory Configuration 3 1 DSP56366 24 Bit Digital Signal Processor Rev 4 Freescale Semiconductor TOC 1 3 1 Data and Program Memory Maps 3 1 3 1 1 Reset ved Memory Spaces Swat dts ati ad
437. t TEDE indicates that data should be written to all the TX registers of the enabled transmitters or to the time slot register TSR TEDE is cleared when the DSP writes to all the transmit data registers of the enabled transmitters or when the DSP writes to the TSR to disable transmission of the next time slot If TIE is set an ESAI transmit data interrupt request 15 issued when is set Hardware software ESAI individual and STOP reset clear 8 3 6 14 SAISR Transmit Odd Data Register Empty TODE Bit 17 When set indicates that the enabled transmitter data registers became empty at the beginning of an odd time slot Odd time slots are all odd numbered slots 1 3 5 etc Time slots are numbered from zero to N 1 where N is the number of time slots in the frame This flag is set when the contents ofthe transmit data register of all the enabled transmitters are transferred to the transmit shift registers it is also set for a DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 8 37 ESAI Programming Model TSR disabled time slot period in network mode as if data were being transmitted after the TSR was written When set TODE indicates that data should be written to all the TX registers of the enabled transmitters or to the time slot register TSR TODE is cleared when the DSP writes to all the transmit data registers of the enabled transmitters or when the DSP writes to the
438. t output or internally disconnected The default state after reset is GPIO disconnected This input is 5 V tolerant DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 2 15 Enhanced Serial Audio Interface Table 2 11 Enhanced Serial Audio Interface Signals continued Signal Name FST PC4 Signal Type Input or output Input output or disconnected State during Reset GPIO disconnected Signal Description Frame Sync for Transmitter This is the transmitter frame sync input output signal For synchronous mode this signal is the frame sync for both transmitters and receivers For asynchronous mode FST is the frame sync for the transmitters only The direction is determined by the transmitter frame sync direction TFSD bit in the ESAI transmit clock control register TCCR Port C 4 When the ESAI is configured as GPIO this signal is individually programmable as input output or internally disconnected The default state after reset is GPIO disconnected This input is 5 V tolerant SCKR PCO Input or output Input output or disconnected GPIO disconnected Receiver Serial Clock SCKR provides the receiver serial bit clock for the ESAI The SCKR operates as a clock input or output used by all the enabled receivers in the asynchronous mode SYN 0 or as serial flag 0 pin in the synchronous mode SYN 1 When this pin is configured as ser
439. t Clock Polarity TCKP Bit 18 The Transmitter Clock Polarity TCKP bit controls on which bit clock edge data and frame sync are clocked out and latched in If TCKP is cleared the data and the frame sync are clocked out on the rising edge of the transmit bit clock and latched in on the falling edge of the transmit bit clock If TCKP is set the falling edge of the transmit clock is used to clock the data out and frame sync and the rising edge of the transmit clock is used to latch the data and frame sync in 8 3 1 6 TCCR Transmit Frame Sync Polarity TFSP Bit 19 The Transmitter Frame Sync Polarity TFSP bit determines the polarity of the transmit frame sync signal When TFSP is cleared the frame sync signal polarity is positive i e the frame start is indicated by high level on the frame sync pin When TFSP is set the frame sync signal polarity is negative i e the frame start is indicated by a low level on the frame sync pin 8 3 1 7 TCCR Transmit High Frequency Clock Polarity THCKP Bit 20 The Transmitter High Frequency Clock Polarity THCKP bit controls on which bit clock edge data and frame sync are clocked out and latched in If THCKP is cleared the data and the frame sync are clocked out on the rising edge of the transmit bit clock and latched in on the falling edge of the transmit bit clock If THCKP is set the falling edge of the transmit clock is used to clock the data out and frame sync and the rising edge of the transmit
440. t Control Bit 3 BA1W4 EQU 9 Area 1 Wait Control Bit 4 M BAZW EQU 51 00 Area 2 Wait Control Mask BA2W0 BA2W2 M BA2WO EQU 10 Area 2 Wait Control Bit 0 M BA2W1 EQU 11 Area 2 Wait Control Bit 1 M BA2W2 EQU 12 Area 2 Wait Control Bit 2 M BA3W EQU 000 Area 3 Wait Control Mask BA3W0 BA3W3 M BA3WO EQU 13 Area 3 Wait Control Bit 0 BA3W1 EQU 14 Area 3 Wait Control Bit 1 M BA3W2 EQU 15 Area 3 Wait Control Bit 2 M BDFW EQU 51 0000 Default Area Wait Control Mask BDFWO BDFWA M BDFWO EQU 16 Default Area Wait Control bit 0 M BDFW1 EQU 17 Default Area Wait Control bit 1 M BDFW2 EQU 18 Default Area Wait Control bit 2 M BDFW3 EQU 19 Default Area Wait Control bit 3 M BDFW4 EQU 20 Default Area Wait Control bit 4 M BBS EQU 21 Bus State M BLH EQU 22 Bus Lock Hold M BRH EQU 23 Bus Request Hold DRAM Control Register M BCW EQU 3 In Page Wait States Bits Mask BCWO BCW1 M BCWO EQU 0 In Page Wait States Bit 0 M EQU 1 In Page Wait States Bit 1 M BRW EQU 5 Out Of Page Wait States Bits Mask BRWO BRW1 DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor B 13 Equates M BRWO EQU 2 Out of Page Wait States bit 0 EQU 3 Out of Page Wait States bit 1 M BPS EQU 300 DRAM Page Size Bits Mask 5 51 M BPSO EQU 4 DRAM Page Size Bits 0 M BPS1 EQU 5 DRAM Page Size Bits 1 M BPLE EQU 11 Page Logi
441. t E Direction Register PRRE 9 14 9 5 3 Port E Data register PDRE suyuna ieu uu quia ia wg PENES 9 14 10 Digital Audio Transmitter 10 1 de talo etre efe NE 10 1 uo 13d pre EIU Indo e EO CN SEEMS IM QU dee ss 10 2 10 3 DA Functional OVerview occ 925 edt Sees RE qa i hh CERE 10 2 10 4 DAX Programming Model 10 3 105 DA X Internal Architecture uu do e SL rect UR e RR a OD LE RC 10 4 10 5 1 DAX Audio Data Register XADR 10 5 10 5 2 DAX Audio Data Buffers XADBUFA XADBUFB 10 5 10 5 3 DAX Audio Data Shift Register 5 10 5 10 5 4 DAX Non Audio Data Register 10 5 10 5 4 1 DAX Channel A Validity XVA Bit 10 10 5 10 5 4 2 DAX Channel A User Data XUA Bit 11 10 6 10 5 4 3 DAX Channel A Channel Status XCA Bit 12 10 6 10 5 4 4 DAX Channel B Validity 13 10 6 10 5 4 5 DAX Channel User Data XUB Bit 14 10 6 10 5 4 6 DAX Channel B Channel S
442. t GPIO data register HDR and host port GPIO direction register HDDR These registers are described in Section 6 Host Interface HDIO8 of this document 5 2 2 Port C Signals and Registers Each ofthe 12 port C signals not used as an ESAI signal can be configured individually as a GPIO signal The GPIO functionality of port C is controlled by three registers port C control register PCRC port C direction register PRRC and port C data register PDRC These registers are described in Section 8 Enhanced Serial AUDIO Interface ESAT 5 2 3 Port D Signals and Registers Each of the two Port D signals not used as a DAX signal can be configured individually as a GPIO signal The GPIO functionality of Port D is controlled by three registers Port D control register PCRD Port D direction register PRRD and Port D data register PDRD These registers are described in Section 10 Digital Audio Transmitter DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 5 1 Programming Model 5 2 4 Port E Signals and Registers Port E has 10 signals shared with the ESAI 1 Six ofthe ESAI 1 signals have their own pin so each of the six signals if not used as an ESAI 1 signal can be configured individually as GPIO signal The other four ESAI 1 signals share pins with the ESAI For these shared pins if the pin is not being used by the Port C and the ESAI 1 then it may be used as a Port E GPI
443. t flag See Table 8 1 and Table 8 7 Table 8 7 SCKR Pin Definition Table Control Bits SCKR PIN SYN RCKD 0 0 SCKR input 0 1 SCKR output 1 0 IFO 1 1 OFO 8 3 3 9 RCCR Receiver Frame Sync Signal Direction RFSD Bit 22 The Receiver Frame Sync Signal Direction RFSD bit selects the source of the receiver frame sync signal when in the asynchronous mode SYN 0 and the IF1 OF 1 Transmitter Buffer Enable flag direction in the synchronous mode SYN 1 In the asynchronous mode when RFSD is set the internal clock generator becomes the source of the receiver frame sync and is the output on the FSR pin In the asynchronous mode when RFSD is cleared the receiver frame sync source is external the internal clock generator is disconnected from the FSR pin and an external clock source may drive this pin In the synchronous mode when RFSD is set the FSR pin becomes the OF 1 output flag or the Transmitter Buffer Enable according to the TEBE control bit If RFSD is cleared then the FSR pin becomes the IF1 input flag See Table 8 1 and Table 8 8 Table 8 8 FSR Pin Definition Table Control Bits FSR Pin SYN TEBE RFSD 0 X 0 FSR input 0 X 1 FSR output 1 0 0 IF1 1 0 1 OF1 1 1 0 reserved 1 1 1 Transmitter Buffer Enable DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 8 25 ESAI Programming Model 8 3 3 10 RCCR Receiver Hi
444. t is 5 V tolerant DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 2 22 Freescale Semiconductor 3 Memory Configuration 3 1 Data and Program Memory Maps The on chip memory configuration of the DSP56366 is affected by the state of the CE Cache Enable MSWO0 MSWI and MS Memory Switch control bits in the OMR register and by the SC bit in the Status Register The internal data and program memory configurations are shown in Table 3 1 The address ranges for the internal memory are shown in Table 3 2 and Table 3 3 The memory maps for each memory configuration are shown in Figure 3 1 to Figure 3 16 Table 3 1 Internal Memory Configurations Bit Settings Memory Sizes 24 bit words MSWi Mswo MS SC Cache ROM ROM RAM RAM ROM ROM X X 0 0 0 3K n a 40K 192 13K 7K 32K 8K X X 1 0 0 2K 1K 40K 192 13K 7K 32K 8K 0 0 0 1 0 10K n a 40K 192 8K 5K 32K 8K 0 1 0 1 0 8K n a 40K 192 8K 7K 32K 8K 1 0 0 1 0 5K n a 40K 192 11K 7K 32K 8K 0 0 1 1 0 9K 1K 40K 192 8K 5K 32K 8K 0 1 1 1 0 7K 1K 40K 192 8K 7K 32K 8K 1 0 1 1 0 4K 1K 40K 192 11K 7K 32K 8K X X 0 0 1 3K n a n a n a 13K 7K 32K 8K X X 1 0 1 2K 1K n a n a 13K 7K 32K 8K 0 0 0 1 1 10K n a n a n a 8K 5 32K 8K 0 1 0 1 1 8K n a n a n a 8K 7K 32K 8K 1 0 0 1 1 5K n a n a n a 11K 7K 32K 8K 0 0 1 1 1 9K 1K n a n a 8K 5K 32K 8K 0 1 1 1 1 7K 1K n a n a 8K 7K 32K 8K 1 0 1 1 1 4K 1K n a
445. t occurs In this mode the counter is also reloaded whenever the TLR 15 written with a new value while the TE bit in the TCSR is set modes if the bit in the TCSR is cleared TRM 0 the counter operates as free running counter 11 3 6 Timer Compare Register The TCPR is a 24 bit read write register that contains the value to be compared to the counter value These two values are compared every timer clock after the TE bit in the TCSR is set When the values match the timer compare flag bit is set and an interrupt is generated if interrupts are enabled if the timer compare interrupt enable TCIE bit in the TCSR is set The programmer must initialize the TCPR to ensure correct operation in the appropriate timer operating modes The TCPR is ignored in measurement modes 11 3 7 Timer Count Register TCR The TCR is a 24 bit read only register In timer and watchdog modes the counter s contents can be read at any time by reading the TCR register In measurement modes the TCR is loaded with the current value of the counter on the appropriate edge of the input signal and its value can be read to determine the width period or delay of the leading edge ofthe input signal When the timer is in measurement modes the TIOO signal is used for the input signal 11 4 Timer Modes of Operation Each timer has various operational modes that meet a variety of system requirements These modes are as follows Timer
446. t ten times the tolerable spike width before enabling the SHI setting the HEN bit in the HCSR Similarly after changing the bit in the HCSR or the CPOL bit in the HCKR while the filter mode bits are in non bypass mode HFM 1 0 not equal to 00 the programmer should wait at least ten times the tolerable spike width before enabling the SHI setting HEN in the HCSR 7 4 6 SHI Control Status Register HCSR DSP Side The HCSR is a 24 bit register that controls the SHI operation and reflects its status The control bits are read write The status bits are read only The bits are described in the following paragraphs When in the stop state or during individual reset the HCSR status bits are reset to their hardware reset state while the control bits are not affected 7 4 6 1 HCSR Host Enable HEN Bit 0 The read write control bit HEN when set enables the SHI When HEN is cleared the SHI is disabled that is It is in the individual reset state see below The HCKR and HCSR control bits are not affected when HEN is cleared When operating in master mode HEN should be cleared only when the SHI is idle HBUSY 0 HEN is cleared during hardware reset and software reset DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 7 10 Freescale Semiconductor Serial Host Interface Programming Model 7 4 6 1 1 SHI Individual Reset While the SHI is in the individual reset state SHI input pins are inhibited out
447. ta Empty I ESAIRD EQU VEC 30 ESAI Receive Data I ESAIRED EQU VEC 32 ESAI Receive Even Data I ESAIRDE EQU VEC 34 ESAI Receive Data With Exception Status DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor I ESAIRLS EQU I ESAITD EQU I ESAITED EQU I ESAITDE EQU I ESAITLS EQU I VEC 36 I VEC 38 I VEC 3A I VEC 3C I_VEC 3E ESAI ESAI ESAI ESAI ESAI Receive Last Slot Transmit Data Transmit Even Data Transmit Data With Exception Status Transmit Last Slot SHI Interrupts I SHITD EQU I SHITUE EQU I SHIRFF EQU I SHIROE EQU I VEC 40 I VEC 42 I SHIRNE EQU I 544 I VEC 48 I VEC 4A I SHIBER EQU I 54 SHI SHI Transmit Data Transmit Underrun Error SHI Receive FIFO Not Empty SHI SHI SHI Receive FIFO Full Receive Overrun Error Bus Error I TIMOOF EQU I I EQU I I TIMIOF EQU I I TIM2C EQU I I TIM2OF EQU I I EQU 54 556 558 5 EC S5C EC S5E TIMER TIMER TIMER TIMER TIMER TIMER 0 compare 0 overflow 1 compare 1 overflow 2 compare 2 overflow I HIOSRX EQU 560 Host R eceive Data Full DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Equates Freescale Semiconductor Equat
448. tae Cot d E ES 6 3 Table 6 2 Strobe signals Support signals 6 4 Table 6 3 Host request support signals 6 4 Table 6 4 RO Lu e D ES s 6 8 Table 6 5 ao NP i e xr kuya s u 6 8 Table 6 6 HDR and HDDR Functionality 6 16 Table 6 7 DSP Side Registers after Reset 6 17 Table 6 8 HDI08 Host Side Register 6 19 Table 6 9 TREQ RREQ Interrupt Mode HDM 2 0 000 or HM 1 0 00 6 21 Table 6 10 DMA Mode HM1 40 or 6 21 SHBRO PRSE MR eS a et P e werd 6 21 DSP56366 24 Bit Digital Signal Processor Rev 4 Freescale Semiconductor LOT 1 Table 6 12 Table 6 13 Table 6 14 Table 6 15 Table 7 1 Table 7 2 Table 7 3 Table 7 4 Table 7 5 Table 7 6 Table 8 1 Table 8 2 Table 8 3 Table 8 4 Table 8 5 Table 8 6 Table 8 7 Table 8 8 Table 8 9 Table 8 10 Table 8 11 Table 8 12 Table 9 1 Table 9 2 Table 9 3 Table 9 4 Table 10 1 Table 10 2 Table 10 3 Table 10 4 Table 10 5 Table 10 6 Table 11 1 Table 11 2 Table 11 3 Table 11 4 Table D 1 Table D 2 Table D 3 Table D 4 Host Mode Bit Definition 6 22 INIT Com
449. tatus XCB Bit 15 _ 10 6 10 5 4 7 XNADR Reserved Bits Bits 0 9 16 23 10 6 10 5 5 DAX Non Audio Data Buffer 10 6 10 5 6 DAX Control Register XC TR P E re e e Rea to E 10 6 10 5 6 1 Audio Data Register Empty Interrupt Enable XDIE Bit 0 10 7 10 5 6 2 Underrun Error Interrupt Enable XUIE Bit 1 10 7 10 5 6 3 Block Transferred Interrupt Enable XBIE Bit 2 10 7 10 5 6 4 DAX Clock Input Select XCS 1 0 Bits 3 4 10 7 10 5 6 5 DAX Start Block XSB BIt5 10 7 10 5 6 6 XCTR Reserved Bits BIfs6 23_ _ _ 10 7 10 5 7 DAX Status Register US DR een oie ee tha a de uis qun 10 7 10 5 7 1 DAX Audio Data Register Empty 0 10 8 DSP56366 24 Bit Digital Signal Processor Rev 4 Freescale Semiconductor TOC 9 10 5 7 2 DAX Transmit Underrun Error Flag XAUR Bit 1 10 8 10 5 7 3 DAX Block Transfer Flag XBLK Bit2 10 8 10 5 7 4 Reserved Bits Bits 3 23 225542825942 er D RET Y d 10 8 10 5 8 DAX Parity Generator PRIYG 22552 Rape AER RR RR 10 9 10 5 9 DAX Biphase
450. te register that controls the DAX operation The contents of the XCTR are shown in Figure 10 2 XCTR is cleared by software reset and hardware reset The XCTR bits are described in the following paragraphs DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 10 6 Freescale Semiconductor DAX Internal Architecture 10 5 6 1 Audio Data Register Empty Interrupt Enable XDIE Bit 0 When the XDIE bit is set the audio data register empty interrupt is enabled and sends an interrupt request signal to the DSP if the XADE status bit is set When XDIE bit is cleared this interrupt is disabled 10 5 6 2 Underrun Error Interrupt Enable XUIE Bit 1 When the XUIE bit is set the underrun error interrupt is enabled and sends an interrupt request signal to the DSP if the XAUR status bit is set When XUIE bit 15 cleared this interrupt is disabled 10 5 6 3 Block Transferred Interrupt Enable XBIE Bit 2 When the XBIE bit is set the block transferred interrupt is enabled and sends an interrupt request signal to the DSP ifthe XBLK and XADE status bits are set When XBIE bit is cleared this interrupt is disabled 10 5 6 4 DAX Clock Input Select XCS 1 0 Bits 3 4 The XCS 1 0 bits select the source of the DAX clock and or its frequency Table 10 3 shows the configurations selected by these bits These bits should be changed only when the DAX is disabled Table 10 3 Clock Source Selection XCS1 XCSO DAX Clock Source 0 0
451. tents of the IVR are placed on the host data bus while HOREQ and HACK are simultaneously asserted The IVR data tells the MC680XX host processor which interrupt routine to execute to service the DSP DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 6 29 Servicing The Host Interface DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 6 30 Freescale Semiconductor 7 7 1 Serial Host Interface Introduction The Serial Host Interface SHI is a serial I O interface that provides a path for communication and program coefficient data transfers between the DSP and an external host processor The SHI can also communicate with other serial peripheral devices The SHI supports two well known and widely used synchronous serial buses the Freescale Serial Peripheral Interface SPI bus and the Philips Inter Integrated Circuit Control PC bus The SHI supports either bus protocol as either a slave or a single master device To minimize DSP overhead the SHI supports 8 bit 16 bit and 24 bit data transfers The SHI has a 1 or 10 word receive FIFO that permits receiving up to 30 bytes before generating a receive interrupt reducing the overhead for data reception When configured in the SPI mode the SHI can perform the following functions Identify its slave selection in slave mode Simultaneously transmit shift out and receive shift in serial data Directly operate with 8 16 and 24 bit
452. the DSP by writing the interrupt routine address divided by 2 into the HV bits The host processor can thus force execution of any of the existing interrupt handlers IRQA IRQB etc and can use any of the reserved or otherwise unused addresses provided they have been pre programmed in the DSP HV 6 0 is set to 32 vector location 0064 by hardware software individual and stop resets 6 6 2 2 CVR Host Command Bit HC Bit 7 The HC bit is used by the host processor to handshake the execution of host command interrupts Normally the host processor sets HC to request the host command interrupt from the DSP core When the host command interrupt is acknowledged by the DSP core the HC bit is cleared by the HDIO8 hardware The host processor can read the state of HC to determine when the host command has been accepted After setting HC the host must not write to the again until HC is cleared by the 108 hardware Setting HC causes the host command pending HCP in the HSR to be set The host can write to the HC and HV bits in the same write cycle 6 6 3 Interface Status Register ISR The ISR is an 8 bit read only status register used by the host processor to interrogate the status and flags of the HDIO8 The host processor can write to this address without affecting the internal state ofthe HDI08 which is useful if the user desires to access all of the HDIOS registers by stepping through the HDI08 addresses The ISR cannot be acce
453. the prescaler divide factor 1 the number that the prescaler counter will load and begin counting from and the source for the prescaler input clock See Figure 11 4 23 22 21 20 19 18 17 16 15 14 13 12 PS1 PSO PL20 PL19 PL18 PL17 PL16 PL15 PL14 PL13 PL12 11 10 9 8 7 6 5 4 3 2 1 0 PL11 PL10 PL9 PL8 PL7 PL6 PL5 PL4 PL3 PL2 PL1 PLO reserved read as 0 should be written with for future compatibility Figure 11 4 Timer Prescaler Load Register TPLR 11 3 21 Prescaler Preload Value PL 20 0 Bits 20 0 These 21 bits contain the prescaler preload value This value is loaded into the prescaler counter when the counter value reaches zero or the counter switches state from disabled to enabled If PL 20 0 then the prescaler counts 1 source clock cycles before generating prescaler clock pulse Therefore the prescaler divide factor preload value 1 The PL 20 0 bits are cleared by the hardware RESET signal or the software RESET instruction 11 3 2 2 Prescaler Source PS 1 0 Bits 22 21 The two prescaler source PS bits control the source of the prescaler clock Table 9 1 summarizes PS bit functionality The prescaler s use of the TIOO signal is not affected by the TCSR settings of timer 0 If the prescaler source clock is external the prescaler counter is incremented by signal transitions on the TIOO
454. the synchronous mode is selected Data present on the FSR pin is latched during reception of the first received data bit after frame sync is detected The IF 1 bit is updated with this data when the receiver shift registers are transferred into the receiver data registers 1 reads as a zero when it is not enabled Hardware software ESAI individual and STOP reset clear IF1 8 3 6 3 SAISR Serial Input Flag 2 IF2 Bit 2 The IF2 bit is enabled only when the HCKR pin is defined as ESAI in the Port Control Register SYN 1 and RHCKD 09 indicating that HCKR is an input flag and the synchronous mode is selected Data present on the HCKR pin is latched during reception of the first received data bit after frame sync is detected The IF2 bit is updated with this data when the receive shift registers are transferred into the receiver data registers IF2 reads as a zero when it is not enabled Hardware software ESAI individual and STOP reset clear IF2 8 3 6 4 SAISR Reserved Bits Bits 3 5 11 12 18 23 These bits are reserved for future use They read as zero 8 3 6 5 SAISR Receive Frame Sync Flag RFS Bit 6 When set RFS indicates that a receive frame sync occurred during reception of the words in the receiver data registers This indicates that the data words are from the first slot in the frame When RFS 15 clear and DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 8 35 ESAI Programming Model
455. tion Register EQU SFFFFBF Port C Control Register EQU SFFFFBE Port C Direction Register M PDRC EQU SFFFFBD Port C GPIO Data Register M EQU SFFFFD7 Port D Control register M PRRD EQU SFFFFD6 Port D Direction Data Register M PDRD EQU SFFFFD5 Port D GPIO Data Register M PCRE EQU SFFFF9F Port E Control register M PRRE EQU SFFFF9E Port E Direction Data Register M PDRE EQU SFFFF9D Port E GPIO Data Register M OGDB EQU SFFFFFC OnCE GDB Register 2 EQUATES for Exception Processing Register Addresses M IPRC EQU SFFFFFF Interrupt Priority Register Core M_IPRP EQU SFFFFFE Interrupt Priority Register Peripheral Interrupt Priority Register Core IPRC M IAL EQU 7 IRQA Mode Mask M IALO EQU 0 IRQA Mode Interrupt Priority Level low DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor B 5 Equates M IAL1 EQU 1 IRQA Mode Interrupt Priority Level high M IAL2 EQU 2 IRQA Mode Trigger Mode M IBL EQU 38 IRQB Mode Mask M_IBLO EQU 3 Mode Interrupt Priority Level low M_IBL1 EQU 4 IRQB Mode Interrupt Priority Level high M IBL2 EQU 5 Mode Trigger Mode M ICL EQU 1CO IRQC Mode Mask M ICLO EQU 6 IRQC Mode Interrupt Priority Level low M ICL1 EQU 7 IRQC Mode Interrupt Priority Level high M ICL2 EQU 8 IRQC Mode Trigger Mode M IDL EQU SE00 IRQD Mode Mask M IDLO EQU 9 IRQD M
456. tri stated BR is asserted when the DSP requests bus mastership BR is deasserted when the DSP no longer needs the bus BR may be asserted or deasserted independent of whether the DSP56364 is a bus master or a bus slave Bus parking allows BR to be deasserted even though the DSP56364 is the bus master See the description of bus parking in the BB signal description The bus request hold BRH bit in the BCR allows BR to be asserted under software control even though the DSP does not need the bus BR is typically sent to an external bus arbitrator that controls the priority parking and tenure of each master on the same external bus BR is only affected by DSP requests for the external bus never for the internal bus During hardware reset BR is deasserted and the arbitration is reset to the bus slave state DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor Interrupt and Mode Control Table 2 7 External Bus Control Signals continued Signal Name BG Type Input State during Reset Ignored Input Signal Description Bus Grant BG is an active low input BG is asserted by an external bus arbitration circuit when the DSP56364 becomes the next bus master When BG is asserted the DSP56364 must wait until BB is deasserted before taking bus mastership When BG is deasserted bus mastership is typically given up at the end of the current bus cycle This may occur in the middle of
457. ts As many as 37 user configurable general purpose input output GPIO signals counter TEC module containing three independent timers Memory switch mode in on chip memory Four external interrupt mode control lines and one external non maskable interrupt line Enhanced serial audio interface ESAT with up to four receivers and up to six transmitters master or slave using the 125 Sony AC97 network and other programmable protocols A second enhanced serial audio interface ESAI 1 with 6 dedicated pins Serial host interface SHI using SPI and PC protocols with multi master capability 10 word receive FIFO and support for 8 16 and 24 bit words Digital audio transmitter DA X a serial transmitter capable of supporting the SPDIF IEC958 CP 340 and AES EBU digital audio formats DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 1 8 Freescale Semiconductor Peripheral Overview 1 5 1 Host Interface 0108 The host interface HDIO8 is a byte wide full duplex double buffered parallel port that can be connected directly to the data bus of a host processor The HDIOS supports a variety of buses and provides glueless connection with a number of industry standard DSPs microcomputers microprocessors and DMA hardware The DSP core treats the HDIO8 as a memory mapped peripheral using either standard polled or interrupt programming techniques Separate transmit and r
458. ty empty empty HOTX HOTX 23 0 empty empty empty empty Note A long dash denotes that the register value is not affected by the specified reset 6 5 10 Host Interface DSP Core Interrupts The HDIO08 may request interrupt service from either the DSP core or the host processor The DSP core interrupts are internal and do not require the use external interrupt pin When the appropriate interrupt enable bit in the HCR is set an interrupt condition caused by the host processor sets the appropriate bit in the HSR generating an interrupt request to the DSP core The DSP core acknowledges interrupts caused by the host processor by jumping to the appropriate interrupt service routine The three possible interrupts are as follows Hostcommand Transmit data register empty Receive data register full Although there is a set of vectors reserved for host command use the host command can access any interrupt vector in the interrupt vector table The DSP interrupt service routine must read or write the appropriate HDI08 register clearing HRDF or for example to clear the interrupt In the case of host command interrupts the interrupt acknowledge from the DSP core program controller clears the pending interrupt condition Figure 6 11 illustrates the HSR HCR operation DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 6 17 HDIO8 External Host Programmer s Model ENABLE
459. uctions and addressing modes In addition the MOVEP instruction allows direct data transfers between the DSP memory and the HDIOS registers or vice versa The HOTX and HORX registers may be serviced by the on chip DMA controller for data transfers DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 6 5 HDIOS8 DSP Side Programmer s Model The eight host processor registers consists of two data registers and six control registers All registers can be accessed by the DSP core but not by the external processor Data registers are 24 bit registers used for high speed data transfer to and from the DSP They are as follows Host Data Receive Register HORX Host Data Transmit Register HOTX The control registers 16 bit registers used to control the HDIO8 functions The eight MSBs in the control registers are read by the DSP as zero The control registers are as follows Host control register Host status register HSR Host base address register HBAR Host port control register HPCR Host GPIO data direction register HDDR Host GPIO data register HDR Hardware and software reset disable the HDIO8 After reset the HDIOS signals are configured as GPIO with all pins disconnected 6 5 1 Host Receive Data Register HORX The 24 bit read only HORX register is used for host to DSP data transfers The HORX register is loaded with 24 bit data from the transmit dat
460. uctor products for any such unintended or unauthorized application Buyer shall indemnify and hold Freescale Semiconductor and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners Freescale Semiconductor Inc 2006 All rights reserved Contents 1 1 1 1 2 1 3 1 4 1 4 1 1 4 1 1 1 4 1 2 1 4 2 1 4 3 1 4 4 1 4 5 1 4 6 1 4 7 1 4 8 1 4 9 1 5 1 5 1 1 5 2 1 5 3 1 5 4 1 5 5 1 5 6 1 5 7 2 2 1 2 2 2 3 2 4 215 2 5 1 2 552 2 5 3 2 6 Deh 2 8 2 9 2 10 2 11 2 12 2 13 56366 1 u u DER EEE aya uq gy a 1 1 Introduction uas oed ix tus peut Paten SORA 1 1 DSP56300 Core Description 5252 E uses x a re 1 2 DSP56366 Audio Processor Architecture 1 3 DSP56300 Core Functional Blocks 1 3 Datt EU
461. uests used to trigger the DMA transfers The DMA request sources may be the internal peripherals or external devices requesting service through the IRQA IRQB IRQC and IRQD pins The DMA Request Sources are shown in Table 4 7 Table 4 7 DMA Request Sources DMA Request Source Bits Requesting Device DRSA DRSO 00000 External IRQA pin 00001 External IRQB pin 00010 External IRQC pin 00011 External IRQD pin 00100 Transfer Done from DMA channel 0 00101 Transfer Done from DMA channel 1 00110 Transfer Done from DMA channel 2 00111 Transfer Done from DMA channel 3 01000 Transfer Done from DMA channel 4 01001 Transfer Done from DMA channel 5 01010 DAX Transmit Data 01011 ESAI Receive Data RDF 1 01100 ESAI Transmit Data TDE 1 01101 SHI HTX Empty 01110 SHI FIFO Not Empty 01111 SHI FIFO Full 10000 HDIO8 Receive Data 10001 HDIO8 Transmit Data 10010 TIMERO TCF 1 10011 TIMER1 TCF 1 10100 TIMER2 TCF 1 10101 ESAI_1 Receive Data RDF 1 10110 ESAI_1 Transmit Data TDE 1 10111 11111 Reserved DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 4 12 Freescale Semiconductor PLL Initialization 4 6 PLL Initialization 4 6 1 PLL Multiplication Factor MFO MF11 The DSP56366 PLL multiplication factor is set to 6 during hardware reset i e the Multiplication Factor Bits MFO MF11 in PLL Control Register PCTL are set to 005
462. uring Reset GPIO disconnected Signal Description Host Address Input 2 When the HDIO8 is programmed to interface a non multiplexed host bus and the HI function is selected this signal is line 2 of the host address HA2 input bus Host Address 9 When HDI08 is programmed to interface a multiplexed host bus and the HI function is selected this signal is line 9 of the host address HA9 input bus Port B 10 When the HDIO8 is configured as GPIO this signal is individually programmed as input output or internally disconnected The default state after reset for this signal is GPIO disconnected This input is 5 V tolerant HRW Input HRD HRD Input PB11 Input Output or Disconnected GPIO disconnected Host Read Write When HDIO8 is programmed to interface a single data strobe host bus and the HI function is selected this signal is the Host Read Write HRW input Host Read Data When HDIO8 is programmed to interface double data strobe host bus and the HI function is selected this signal is the host read data strobe HRD Schmitt trigger input The polarity of the data strobe is programmable but is configured as active low HRD after reset Port B 11 When the HDIO8 is configured as GPIO this signal is individually programmed as input output or internally disconnected The default state after reset for this signal is GPIO disconnected This input is 5
463. using the information in this section The ESAI 1 block diagram is shown in Figure 9 1 The ESAI 1 shares 4 pins with the ESAI The ESAI 1 does not have the two high frequency clock pins but otherwise it is identical to the DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 9 1 Introduction GDB DDB RSMB 1 TSMB 1 RCR TCR SAICR 1 SAISR 1 TSR 1 522 TXO 1 Register TX1 1 Register TX2 1 i Shift 8 RX3 1 BE EN 1 hift ES RX2 1 Dax 1 Shift RX1 1 4 i TX5_1 VYYYYYYYY Clock Frame Sync Generators and RCLK Control Logic TCLK Shift Register PE3 SCKT 1 PE4 FST 1 PEO SCKR_1 PE1 FSR_1 RXO 1 SE Figure 9 1 ESAI 1 Block Diagram SDOO 1 PE11 shared with SDOO 11 p SDO1_1 PE10 shared with SDO1 PC10 SDO2_1 SDI3_1 shared with SDO2 SDI3 PC9 1 8002 1 shared with 5003 5012 8 5 04 1 SDI 1 PE7 5005 1 SDIO 1 PE6 DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 9 2 Freescale Semiconductor ESAI 1 Data and Control Pins 9 2 ESAI 1 Data and Control Pins ESAI 1 has 6 dedicated pins and shares 4 pins with the ESAI
464. ut Internal 1 Timer Pulse In this mode the timer generates a compare interrupt when the timer count reaches a preset value In addition timer 0 provides an external pulse on its TIOO signal Set the TE bit to clear the counter and enable the timer The value to which the timer is to count is loaded into the TCPR The counter is loaded with the TLR value when the first timer clock signal is received The TIOO signal is loaded with the value of the INV bit The timer clock signal can be taken from either the DSP56366 clock divided by two CLK 2 or from the prescaler clock output Each subsequent clock signal increments the counter When the counter matches the TCPR value the TCF bit in TCSR is set and a compare interrupt is generated if the TCIE bit is set The polarity of the TIOO signal is inverted for one timer clock period If the TRM bit is set the counter is loaded with the TLR value on the next timer clock and the count is resumed If the TRM bit is cleared the counter continues to be incremented on each timer clock This process is repeated until the TE bit is cleared disabling the timer The value of the TLR sets the delay between starting the timer and the generation of the output pulse To generate successive output pulses with a delay of X clocks between signals the TLR value should be set to X 2 and the TRM bit should be set This process is repeated until the timer is disabled 1 TE is cl
465. ut bit SDA inout bit SDO41 1 inout bit 50050 1 inout bit FST 1 inout bit FSR 1 inout bit SCKR 1 inout bit SCKT 1 inout bit use STD 1149 1 1994 all attribute COMPONENT CONFORMANCE of DSP56366 entity is STD 1149 1 1993 attribute PIN MAP of DSP56366 entity is PHYSICAL PIN MAP constant TOFP144 PIN MAP STRING SCK 1 amp SS 2 amp HREQ 3 amp SDOO 4 amp SDOl 5 amp SDOI23 6 amp SDOI32 7 amp SVCC 8 25 amp SGND 9 26 amp SDOIA1 10 amp 500150 11 amp FST 12 amp FSR 13 amp SCKT 14 amp SCKR 15 amp HSCKT 16 amp HSCKR 17 amp OVCC 18 56 91 126 amp OGND 19 54 90 127 amp DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 C 2 Freescale Semiconductor JTAG BSDL QVCCH 20 49 95 amp HP 43 42 41 40 37 36 35 34 33 32 81 22 21 89 24 23 amp ADO 27 amp ACI 28 amp TIO 29 amp HVCC 38 amp HGND 39 amp RESET 44 amp 45 amp PCAP 46 amp PGND 47 amp 5 050 1 48 amp FST 1 50 amp AA 70 69 51 amp CAS 52 amp SCKT 1 53 amp EXTAL 55 amp CVCC 57 65 amp CGND 58 66 amp FSR 1 59 amp SCKR 1 60 amp PINIT 61 amp TA Gos Wig BR 63 amp BB 64 amp
466. vent The timer issues a DMA trigger on every event in all modes of operation The DMA channel does not have the capability to save multiple DMA triggers generated by the timer To ensure that all DMA triggers are serviced the user must provide for the preceding DMA trigger to be serviced before the next trigger 15 received by the DMA channel DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 11 21 Timer Modes of Operation NOTES DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 11 22 Freescale Semiconductor Appendix Bootstrap ROM Contents A 1 DSP56366 Bootstrap Program BOOTSTRAP CODE FOR DSP56366 Rev 0 silicon C Copyright 1999 Motorola Inc Revision 0 0 1999 JAN 26 Modified from 56362 RevA regular boot rev01l asm Change the length of xram and the length of yram in burn in code Change the address of the reserved area in the 2 Program ROM to 5 0 SFFAFFF Revision 0 1 1999 MAR 29 Enabled 100ns I2C filter in bootstrap mode 0110 Added 5 instructions after OnCE enable This is the Bootstrap program contained in the DSP56366 192 word Boot ROM This program can load any program RAM segment from an external EPROM from the Host Interface or from the SHI serial interface If MD MC MB MA x000 then the Boot ROM is bypassed and the DSP56366 will start fetching instructions beginning with address C00000 MD 0 or 0
467. where TSR 1 has been written The Transmitter External Buffer Enable pin FSR 1 pin when SYN 1 TEBE 1 RFSD 1 disables the external buffers during the slot when the TSR 1 register has been written 9 3 13 Transmit Slot Mask Registers TSMA 1 TSMB 1 The Transmit Slot Mask Registers TSMA_1 and TSMB 1 are two read write registers used by the transmitters in network mode to determine for each slot whether to transmit a data word and generate a transmitter empty condition TDE 1 or to tri state the transmitter data pins TSMA 1 and TSMB 1 should each be considered as containing half a 32 bit register TSM 1 See Figure 9 11 and Figure 9 12 Bit number N in TSM 1 TS is the enable disable control bit for transmission in slot number N 11 10 9 8 7 6 5 4 3 2 1 0 Y FFFF99 TS11 TS10 TS9 TS8 TS7 TS6 TS5 TS4 TS3 TS2 TS1 TSO 23 22 21 20 19 18 17 16 15 14 13 12 TS15 514 TS13 TS12 Reserved bit read as zero should be written with zero for future compatibility Figure 9 11 TSMA 1 Register 11 10 9 8 7 6 5 4 3 2 1 0 Y FFFF9A TS27 526 TS25 524 TS23 TS22 521 TS20 519 TS18 TS17 TS16 23 22 21 20 19 18 17 16 15 14 13 12 TS31 TS30 TS29 528 Reserved bit read as zero should be written with zero for future compatibility Figur
468. write access respectively Figure 6 8 Dual strobes bus 6 5 6 14 HPCR Host Chip Select Polarity HCSP Bit 13 If the HCSP bit is cleared the chip select HCS signal is configured as an active low input and the HDI08 is selected when the HCS signal is low If HCSP is set HCS is configured as an active high input and the HDI08 is selected when the HCS signal is high This bit is ignored in the multiplexed mode 6 5 6 15 HPCR Host Request Polarity HRP Bit 14 The HRP bit controls the polarity of the host request signals In the single host request mode HDRQ 0 in the ICR if HRP is cleared and host requests are enabled HREN 1 and HEN 1 in HPCR the signal is an active low output If 15 set and host requests are enabled the HOREQ signal is an active high output In the double host request mode HDRQ 1 in the ICR if is cleared and host requests are enabled HREN 1 and HEN 1 in the HPCR the HTRQ and HRRQ signals are active low outputs If is set and host requests are enabled the HTRQ and signals are active high outputs 6 5 6 16 HPCR Host Acknowledge Polarity HAP Bit 15 If the HAP bit is cleared the host acknowledge HACK signal is configured as an active low input and the HDIOS drives the contents of the HIVR register onto the host bus when the HACK signal is low If HAP is set HACK is configured as an active high input and the HDIOS8 outputs the contents of the HIVR
469. ynchronous because all serial transfers are synchronized to a clock Additional synchronization signals are used to delineate the word frames The normal mode of operation is used to transfer data at a periodic rate one word per period The network mode is similar in that it is also intended for periodic transfers however it supports up to 32 words time slots per period This mode can be used to build time division multiplexed TDM networks In contrast the on demand mode is intended for non periodic transfers of data and to transfer data serially at high speed when the data becomes available This mode offers a subset of the SPI protocol DSP56366 24 Bit Digital Signal Processor User Manual Rev 4 Freescale Semiconductor 8 1 Introduction VYYYYYYYY RSMA RSMB TSMA TSMB RCR TCCR TCR SAICR SAISR Clock Frame Sync Generators and Control Logic PC3 SCKT FST PC5 HCKT PCO SCKR PC1 FSR PC2 HCKR RCLK GDB DDB TCLK 17 1 s Cw E 4 Shift Register O hift Register TX2 Shift Register 4 gt lt Co Shift Register RX2 TX4 Shift Registe RX1 p Shift Registe A RXO Figure 8 1 ESAI Block Diagram x 000 11 E 001 PC10 DW SDO2 SDI3 PC9 gt SDOS S

Freescale Semiconductor DSP56366 User's Manual

Contents

Download Pdf Manuals

Related Search

Related Contents