Fairchild SEMICONDUCTOR AN-7502 User's Manual
Contents
1. Ro is approximately equal to 1 g for Rg very much greater than 1 g y gm transconductance of driving MOSFET transistor Turn Off Ro Rs 2002 Fairchild Semiconductor Corporation Application Note 7502 Rev A1 Application Note 7502 Case 3 Common Source Gate Drive Figure B 3 Rp A 10V l E VDD LE ov FIGURE B 3 COMMON SOURCE GATE DRIVE CIRCUIT Turn On Ro Rp drain to ground capacitance of driving device adds to Cas of driven MOSFET Turn Off Ro rps on Of driving MOSFET when Rp is very much greater than Rpsion 2002 Fairchild Semiconductor Corporation Application Note 7502 Rev A1 TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks ACEx FAST MICROWIRE SILENT SWITCHER UHC Bottomless FASTr OPTOLOGIC SMART START UltraFET CoolFET FRFET OPTOPLANAR SPM VCX CROSSVOLT GlobalOptoisolator PACMAN STAR POWER DenseTrench GTO POP Stealth DOME HiSeC Power247 SuperSOT 3 EcoSPARK PC PowerTrench SuperSOT 6 E CMOS ISOPLANAR QFET SuperSOT 8 EnSigna LittleF ET qs SyncFET FACT MicroFET QT Optoelectronics TinyLogic FACT Quiet Series MicroPak Quiet Series TruTranslation STAR POWER is used under license DISCLAIMER2. FAIRCHILD aS ee SEMICONDUCTOR Application Note The examination of power MOSFET voltage and current waveforms during switching transitions reveals that the device characterization now practiced by industry is inade quate In this Note device waveforms are explained by con sidering the interaction of a vertical JFET driven in cascode from a lateral MOSFET in combination with the interelec trode capacitances Particular attention is given to the drain voltage waveform and its dual slope nature The three terminal capacitances now published by the industry are shown to be valid only for zero drain current For cases where the gate drive is a voltage step generator with inter nal fixed resistance the drain voltage characteristics are inferred from the gate current drive behavior and compared to observed waveforms The nature of the asymmetric switching times is explained A waveform family is proposed as a more descriptive and accurate method of characterization This new format is a plot of drain voltage and gate voltage versus normalized time A family of curves is presented for a constant load resistance with Vps varied Gate drive during switching transitions is a constant current with voltage compliance limits of O and 10 volts Time is normalized by the value of gate driving current The normalization shows excellent agreement with data over five orders of magnitude and is bounded on one extreme by gate propagation
3. nient It is quite another matter however to build a bidirectional current drive that is accurate across the many decades of both current and time required to establish experimental verification Six States To completely characterize power MOSFET switching wave forms the six states that a device assumes Figure 6 must be addressed STATE MOS JFET Turn on 1 Off Off Turn on 2 Active Active Turn on 3 Active Saturated Turn off 4 Saturated Saturated Turn off 5 Active Saturated Turn off 6 Active Active The term saturated is taken to mean a constant low voltage drain source condition Ig i t nm v t v t lG TURN ON Igt v g i t Ig 0 lt te lt T i t t lG TURN OFF v t 2va S i t Ig T lt t lt 2T FIGURE 6 STEP CURRENT FORCING FUNCTION Equivalent Circuit The lumped parameter model of Figure 3 with the cascode connected JFET can now be reduced to the linear equiva lent circuit of Figure 7 and the six device states investigated from full off to full on GATE 9 OMJ Vx V o DRAIN lG CDs SOURCE LEGEND Vcs Gate Voltage Cps Drain Source Capacitance Vx JFET Driving Voltage gn MOSFET Transconductance Vp Drain Voltage gmg JFET Transconductance Ces Gate Source R Drain Load Resistance Capacitance Cx MOSFET Feedback lG Constant Current Amplitude Capacitance FIGURE 7 POWER
4. FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY FUNCTION OR DESIGN FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS NOR THE RIGHTS OF OTHERS LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTENAPPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or 2 A critical component is any component of a life systems which a are intended for surgical implant into support device or system whose failure to perform can the body or b support or sustain life or c whose be reasonably expected to cause the failure of the life failure to perform when properly used in accordance support device or system or to affect its safety or with instructions for use provided in the labeling can be effectiveness reasonably expected to result in significant injury to the user PRODUCT STATUS DEFINITIONS Definition of Terms Advance Information Formative or This datasheet contains the design specifications for In Design product development Specifications may change in any manner without notice Preliminary First Production This datasheet contains preliminary data and supplementary dat
5. Figure A 2 shows ig t and ip t for a typical power MOSFET driven by a step gate voltage For truly resistive switching realize that these waveforms are only mirror images of their voltage counterparts valt and vp t Using Figure A 2 applicable gate currents for each of the device states may be listed CURRENT gt TIME gt FIGURE A 2 ig t AND ip t FOR A TYPICAL POWER MOSFET DRIVEN BY A STEP GATE VOLTAGE 2002 Fairchild Semiconductor Corporation Application Note 7502 Rev A1 Application Note 7502 Turn On State 1 MOS Off JFET Off IpK1 Va Ro State 2 MOS Active JFET Active IpK2 Va VasctH Ro State 3 MOS Active JFET Saturated IpK3 Va Vavsat Ro Turn Off State 4 MOS Saturated JFET Saturated IpK4 Va Ro State 5 MOS Active JFET Saturated IpKs Vasat Ro State 6 MOS Active JFET Active IpKe Vacsat Ro The equivalent circuit of Figure A 1 predicts that dVp dt gMRL Vg VastHye T1 where T1 RoCes 1 gm 9gmJ ROCx Note that gyRL VG Vas TH is usually an order of magnitude greater than Vpp indicating that the drain voltage is discharg ing toward a very large negative value The device operation then is on the early almost linear portion of the exponential where e YT approximates unity The drain current of Figure A 2 and hence the drain voltage does indeed exhibit a linear decrease with time Thus for state 2 Von Vokl Cas Cx 1 gm
6. MOSFET EQUIVALENT CIRCUIT State 1 MOS Off JFET Off In a power MOSFET device no drain current will flow until the device s gate threshold voltage Vgg TH is reached Dur ing this time the gate s current drive is only charging the gate source capacitance More accurately lg is charging Ciss Ciss Cas Cap Cps shorted the capacitance designation published by the industry The current generators gyjVcq and gyyVx are open circuits for zero drain current and R is presumed to be so low as to represent a short circuit generally true for practical applica tions This is academic however since Cas is very much larger that Cx The time to reach threshold then is simply Ciss Vgs TH This Ig 2002 Fairchild Semiconductor Corporation Application Note 7502 Rev A1 Application Note 7502 State 2 MOS Active JFET Active This state graphically illustrates the dramatic influence that the JFET has on the power MOSFET drain voltage wave form Instead of having to discharge Cx from Vpp to ground the lateral MOSFET need only swing Vx to ground a much smaller voltage thanks to the grounded gate JFET Since the interaction of Ry with the device capacitances has a second order effect on the drain voltage the equivalent circuit of Fig ure 7 predicts a drain voltage change of dVc dt gmRilc lCas Cx 1 gw9mu In all but the smallest power MOSFET devices C is several thousand picofarads and gy gmy is of th
7. Vok Vp NK VoysarOx o oS Ia Va VersanRo Vg Ia Va VersanRo Ro Von Vol Cas Cx 1 gm 9mI gMRLIg 2002 Fairchild Semiconductor Corporation Application Note 7502 Rev A1 Application Note 7502 Experimental Verification Since the switching equations for step currents and voltages differ only by gate current magnitudes for the same device type one would expect a plot of switching time versus 1 Ro to be of the same form as those obtained for a step current drive This is exactly the case as Figure 10 is merely a vari ation of Figure 8 Using the relationships of Table 1 the observed differences between Figures 7 and 9 can be pin pointed The two sets of experimental curves confirm that on the basis of the short circuit drive current Vg R o equal ling the constant Ig tp on tR tp off and te will all be longer as predicted by the ratios of the gate drive currents of Table 1 Notice also that tr te switching symmetry is dis rupted by the use of a step voltage with source resistance Ro For states 2 and 6 the time ratio is tTURN ON _ VG SAT tTURN OFF VG Vas TH For states 3 and 5 the time ratio is tTURN ON _ VG SAT tTURN OFF VG VG SAT Utilization of available maximum gate drive voltage and cur rent can be optimized for fastest power MOSFET switching speed through the use of constant current gate drive at the expense of increased gate drive circuit complexity 10 RFM15N15
8. acterization curves Experimental Verification Since the switching equations for step currents and voltages differ only by gate current magnitudes for the same device type one would expect a plot of switching time versus 1 Ro to be of the same form as those obtained for a step current drive This is exactly the case as Figure 10 is merely a vari ation of Figure 8 Using the relationships of Table 1 the observed differences between Figures 7 and 9 can be pin pointed The two sets of experimental curves confirm that on the basis of the short circuit drive current V Ro equal ling the constant Iq tD on R tD off and tr will all be longer as predicted by the ratios of the gate drive currents of Table 1 Notice also that tp te switching symmetry is dis rupted by the use of a step voltage with source resistance R For states 2 and 6 the time ratio is TABLE 1 COMMON SWITCHING EQUATIONS CONSTANT CURRENT STATE 1 MOS OFF JFET OFF CONSTANT VOLTAGE fe Ciss VGS TH STATE 2 ACTIVE ACTIVE 1 t Ro Ciss In 1 Vas tHyVel Ig Vg Vas tH Ro Voo VpK Cas Cx 1 O omy gMRLIg STATE 3 ACTIVE SATURATED Ia Va Varsan Ro Vg Ia Va Varsan Ro Ro Vok Voy NK Vosaex o o oS STATE 4 SATURATED SATURATED leaa O LE Cx VG Va saT a STATE 5 ACTIVE SATURATED STATE 6 ACTIVE ACTIVE t Ro Cag Cx In VG Va saT Ig Va Varsan Ro Va Ig Va Varsan Ro Ro
9. data sheet capacitances of little use for esti mating switching times The classical method of defining switching time by 10 and 90 is a poor representation for power MOSFETs because of the dual slope nature of the drain waveforms Switching influences are masked because the 10 level is controlled by one mechanism and the 90 level by another Device comparisons based on the classical switching definition can be very misleading Appendix A Analysis for Resistive Step Voltage Inputs Step Voltage Gate Drive To obtain the necessary relationships six device switching states must be examined using the same device equivalent circuit as was used for the constant gate current case but with the forcing function replaced wlth a step voltage with internal resistance R Figure A 1 LEGEND Gate Voltage Drain Source Capacitance JFET Driving Voltage MOSFET Transconductance Drain Voltage JFET Transconductance Cas Gate Source Ft lt r foal Drain Load Resistance Capacitance Cx MOSFET Feedback lg Constant Current Amplitude Capacitance FIGURE A 1 POWER MOSFET EQUIVALENT CIRCUIT State 1 Mos Off JFET Off As before both current generators are open circuits reducing the equivalent circuit to simply charging Cigs through Ro t RoCissin 1 1 VestHy Va State 2 Mos Active JFET Active Before proceeding it is wise to examine an actual device response and make use of available simplifications
10. effects and on the other by transition time self heating typically tens of nanoseconds to hundreds of microseconds Device Models The keystone of an understanding of power MOSFET switching performance is the realization that the active device is bimodal and must be described using a model that accounts for the dual nature Buried in today s power MOS FET devices is the equivalent of a depletion layer JFET that contributes significantly to switching speed Figure 1 is a cross sectional view of a typical power MOSFET with MOS FET JFET symbols superimposed on the structure Figure 2 is obtained by taking the lateral MOS and vertical JFET from this conception and adding all the possible node to node capacitances Computed values of the six capaci tances for a typical device structure suggest that device behavior may be adequately modeled using only three capacitors in the manner of Figure 3 This is the model to be employed for analysis and study Power MOSFET Switching Waveforms A New Insight October 1999 AN 7502 J SOURCE METAL POLY GATE GLASS GATE OXIDE en en ereer 10 VOLTS DEPLETION EDGE ee AQ VOLTS n DRAIN I l l l l om ben l FIGURE 1 CROSS SECTION VIEW OF MOSFET SHOWING EQUIVALENT MOS TRANSISTOR AND JFET c6 c2 E3 DRAIN GATE jpam c4 c5 c1 SOURCE FIGURE2 MOSTRANSISTOR WITH CASCODE CONNECTED JFET AND ALL CAPACITORS Cx GATE it DRAIN I Cos Ces SOURCE FI
11. gmI 9mRL pKe t where IpKa Va Vascth Ro State 3 Mos Active JFET Saturated Because of the Miller effect the gate voltage and hence the gate current is almost constant during the tail time The equivalent circuit then predicts dVp gmRLlG Iq dt Cas 1 gMRL Cx Cx Ig IpKg Va Vavsat Ro Vok Vprsat Cx IPK3 and t State 4 Mos Saturated JFET Saturated Turn off Both equivalent circuit generators are short circuits and the gate drive is discharging Cy in parallel with Cas through Ro t Ro Cgg Cx In Ve Vecsat l IpK4 Va Ro State 5 Mos Active JFET Saturated The JFET current generator V xgmy iS operative VpK Vp sat Cx IPK5 t IpK5 Vacsat y Ro State 6 Mos Active JFET Active The Miller effect is now reduced by the activation of Vagny and the equivalent circuit predicts Von VokI Cgs Cx 1 gm gmo OMRL IPAK6 IpaKe Va saTy Ro Appendix B Estimating Ro for Some Typical Gate Drive Circuits Case 1 Typical Pulse Generator Drive Figure B 1 VGEN VDD RL TL TE fi 5 A I 5 4 5 4 5 4 5 4 5 5 5 4 FIGURE B 1 TYPICAL PULSE GENERATOR DRIVE CIRCUIT Turn On and Turn Off Ro RaenRas Raen Res For the typical case where RGen 50Q and a coaxial cable termination of 50 ohms Ro 25Q and VG VgEn 2 Case 2 Voltage Follower Gate Drive Figure B 2 FIGURE B 2 VOLTAGE FOLLOWER GATE DRIVE CIRCUIT Turn On
12. 91 5 6 271 375 0 72 2002 Fairchild Semiconductor Corporation Application Note 7502 Rev A1 Application Note 7502 For peak gate voltages other than 10 volts and load resis tances other than BVpss Ip max the equations of Table 1 may be used in conjunction with slope estimates from the characterization curves for Cy and Cas Cx 1 gm 9mv at the appropriate drain current level Characterization Curve Limits The switching time range over which the characterization can be applied is very impressive For gate currents of the order of microamperes device dissipation is the limiting factor For gate currents of the order of amperes the device response will be slowed by gate propagation delay This delay of course degrades the linear switching relationship to gate current How ever as Figure 12 graphically shows the characterization is valid across five decades of gate current and switching time allowing all but a very few switching applications to be described by the characterization curves of Figure 9 104 RFM15N15 tp OFF x en 4 tR o 103 4 tF A wN tp ON a zZ 102 fe ta W no 2 491 O 10 10 je GATE CURRENT Ig MICROAMPERES FIGURE 12 FIVE DECADES OF LINEAR RESPONSE Conclusions The viability of the proposed characterization curves using con stant current has been demonstrated and the limits of applica tion defined The existence of a vertical JFET in a power MOSFET makes
13. GURE 3 FIGURE 2 SIMPLIFIED Gate Drive Constant Voltage or Constant Current Before moving on to the study of the equivalent circuit states of the model a gate drive forcing function which is easy to represent relates to reality and best illustrates device behavior must be chosen The choice may be immediately narrowed to two 1 An instantaneous step voltage with internal resistance R Figure 5 2 An instantaneous step current with infinite internal resis tance Figure 6 2002 Fairchild Semiconductor Corporation Application Note 7502 Rev A1 Application Note 7502 lt GATE VOLTAGE DRAIN fF i VOLTAGE Ji STATES VOLTAGE gt lg CONSTANT VD SAT TIME gt FIGURE 4 IDEALIZED POWER MOSFET WAVEFORMS Va ona i t c v t t IpK Vg Ro TURN ON v t Vg 1 e t RoC i t Vg e RoC Ro TURN OFF v t Vg e Rol i t Vg et RoC t Re lpk Ve Ro i t FIGURE 5 STEP VOLTAGE FORCING FUNCTION Power MOSFET devices are highly capacitive in nature hence simple capacitor responses to the forcing functions offer a good vehicle for comparison The advantageous choice is immediately obvious Figure 6 Voltage time responses dominated by capacitance are straight lines when constant current is used The slope of these lines is proportional to current and inversely proportional to capaci tance Analytically then constant current is most conve
14. Vpp 75V Ip 7 5A Ro gt Q Ve 10V t MICROSECONDS 1 10 100 1000 Ig MILLIAMPERES FIGURE 8 CONSTANT GATE CURRENT SWITCHING TIME Figure 9 is such a plot for the RFM15N15 power MOSFET With such a plot a designer can estimate device switching performance under any resistive gate drain conditions 2002 Fairchild Semiconductor Corporation Application Note 7502 Rev A1 Application Note 7502 100 75 no no a 50 m RFM15N15 z Ir 1mA xe Vg 10 VOLTS 25 RL Vpss p RMs 0 20l7 lG 40l7 Ig 60I7 Ig 80l7 Ig TIME microseconds FIGURE 9 NORMALIZED RFM15N15 SWITCHING WAVE FORMS FOR CANSTANT GATE CURRENT DRIVE Step Voltage Gate Drive The majority of power MOSFET applications employ a step gate voltage input with a finite source resistance Ro Often Ro for turn on is not the same as Ro for turn off How can switching times for these situations be estimated using the switching characterization curves just described The analy sis for resistive step voltage inputs which is complex because the gate current is no longer constrained to be con stant but is a function of device gate voltage response is covered in Appendix A A second shorter appendix B has been added to illustrate the estimation of Ro for some practi cal gate drive circuits Table 1 summarizes the common switching equations and indicates the appropriate 1G to be used in each state for relating step voltage drives to the char
15. Vpp 75V Ip 7 5A Vea 10V g 1 z fo o Wu n fe ra Q 01 DATA THEORY D OFF tR o A x 0 01 FIGURE 10 CONSTANT GATE VOLTAGE SWITCHING TIME Using the Characterization Curve Figure 9 To estimate the switching times for an RFM15N15 power MOSFET under the conditions VG 10V Vpp 75V Ro 100 ohms and R 10 ohms precedes as follows State 1 MOS Off JFET Off This time can be estimated without recourse to the curves t 100 1200 x 10 In 1 1 4 10 t 61ns State 2 amp 6 MOS Active JFET Active Ig 10 4 100 60mA curve divisions x I us 9 t AIT HS TH 150ns 60 60 State 3 MOS Active JFET Saturated lg 10 7 100 30mA curve divisions x I us 14 cs OU OME Es x 467ns 30 30 State 4 MOS Saturated JFET Saturated Cas Cx gate voltage slope test current 1 5 x 10 s 5 volts 10mA 3000pF t 100 3000 x 10 12 In 10 6 6 t 125ns State 5 MOS Active JFET Saturated Ig 6 6 100 66mA curve divisions x I us 8 pa SUNS AVISION ITUS 121ns 66 66 Figure 11 shows RFM15N15 waveforms using the conditions specified in the example 75 RFM15N15 Vpp 75 VOLTS RL 10 OHMS VG 10 VOLTS Ro 100 OHMS DRAIN VOLTAGE VOLTS 1 5 3 TIME MICROSECONDS FIGURE 11 STEP GATE VOLTAGE INPUT TO AN RFM15N15 CALCULATED MEASURED STATE TIME TIME RATIO tc ns tm ns tc tm 1 61 60 1 02 2 3 617 670 0 92 4 125 137 0
16. a will be published at a later date Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design No Identification Needed Full Production This datasheet contains final specifications Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor The datasheet is printed for reference information only
17. e order of 3 1 Power MOSFET devices exhibit a high dVp dt switching rate because of the cascode connected JFET not because Crss Crass Cap is a small value as zero drain current data sheet capacitance values might lead one to believe If Crss were in actuality small long drain voltage tails would not exist The tail response is a direct result of JFET satura tion In order to delineate the transition from state 2 to state 3 a drain voltage at which the transition occurs must be defined Vp is the knee voltage at which linear extrapola tions of drain voltage slopes intersect The time duration of state 2 is to tg Vpop VoK Cas Cx 1 gm gm9 l 9mRLlIG State 3 MOS Active JFET Saturated When the JFET saturates the gyyVx current generator becomes a short circuit and the equivalent circuit predicts dVp at gyRLlc Ces Cx 1 gMRU I This is the Miller effect so often referred to in older texts that describe the behavior of grounded cathode vacuum tube amplifier circuits Allowing for the fact that 1 gn RL is approximately equal to gyR_ and Cy 1 gnR_ is very much larger than Cas the expression for drain voltage tail time is ta t5 Vok Vo sat Cx Iq State 4 MOS Saturated JFET Saturated Turn Off In this state in addition to gyjyVx being shorted the gyyVcG cur rent generator is shorted and Ig is occupied with charging Cx and Cg in parallel from the peak value of Vg to Vasat The time required for t
18. his is t4 Vg VarsaT Cas Cx Iq Since a value for Cag may be measured independently of switching time the method described is the simplest way of determining Cy On turn off the state time equations are equally applicable but in reverse order states 5 and 6 see the idealized wave form of Figure 4 Experimental Verification The four switching states just analyzed indicate that for a given device all four switching state times are inversely pro portional to the magnitude of the gate drive current Figure 8 illustrates the switching performance of a typical power MOSFET across three decades of gate drive current and time In each case the data slope is almost a perfect 1 A New Device Characterization Figure 8 could not be a reasonable device data sheet pre sentation because it does not give the designer any informa tion on a typical value for Cy nor does it convey how Vpx gM 9M Gmy and Ve sat vary with drain current What would be of enormous value to the designer is a plot of Vp t Ve t for selected values of Vpp and Ip within device ratings A reasonable characterization would be as follows 1 The x axis would be normalized in terms of gate current drive 2 The y axis would be normalized in terms of percent maximum rated BVpss 0 to 100 3 RL BVpss ID max would define the drain load resistance 4 Four plots of Vp t Va t at 100 75 50 and 25 BVpss max would be shown RFM15N15
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