Home

Epson S1C63558 User's Manual

1. SEGO SEG1 SEG2 SEG3 SEG39 COMO DO DO DO DO O DO GOM E FOOOH F002H Ei F004H p F006H DI F04EH COM2 D2 D2 D2 D2 O D2 LPAGE COM3 D3 D3 D3 D3 0O D3 0 COM4 DO DO DO DO O DO COMS xi F001H ud F003H e F005H F007H El FO4FH COM6 D2 D2 D2 D2 O D2 D3 D3 D3 D3 003 _ COMO DO DO DO DO E F100H ET F102H E F104H El F106H _ E F14EH COM2 D2 D2 D2 D2 0O D2 LPAGE D3 D3 D3 D3 103 1 4 DO DO DO DO COMS i F101H El F103H ES F105H F107H _ E F14FH COM6 D2 D2 D2 D2 0O D2 D3 D3 D3 D3 0O D3 Unused DO F200H DO F202H DO F204H DO F206H O DO F24EH b When 1 8 duty is selected 51 63558 TECHNICAL MANUAL EPSON 51 CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION LCD Driver
2. Timing chart The timing chart for the clock synchronous system transmission is shown in Figure 4 11 6 4 TXEN RXEN TXTRG RD m RXTRG RD I TXTRG WR I RXTRG WR f SCLK SCLK SOUT 1 2 4 5 6 7 1 4 5 06 07 Interrupt A TRXD 7 ist data Interrupt 4 a Transmit timing for master mode c Receive timing for master mode TXEN RXEN TXTRG RD RXTRG RD z TXTRG WR RXTRG WR SCLK 501 HEFEEEEHE SOUT Do D1 2 D3 b4 D5 De b7 2 3 04 0506 7 SADY 3RXD 7F Tst data 7 SRDY Interrupt Interrupt Transmit timing for slave mode d Receive timing for slave mode Fig 4 11 6 4 Timing chart clock synchronous system transmission 51 63558 TECHNICAL MANUAL EPSON 85 CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Serial Interface 4 11 7 Operation of asynchronous transfer Asynchronous transfer is a mode that transfers by adding a start bit and a stop bit to the front and the back of each piece of serial converted data In this mode there is no need to use a clock that is fully synchronized clock on the transmit side and the receive side but rather transmi
3. Item Symbol Condition Min Typ Max Unit LCD drive voltage Connect 1 load resistor between Vss 1 2 Vc23 1 2 Vc23 V without panel load x0 95 0 1 Vc23 Connect 1 MQ load resistor LCO 3 0 1 95 V between Vss and Vc23 1 0 3 1 1 98 without panel load 0 3 2 2 01 LC0 3 3 2 04 LC0 3 4 2 07 LC0 3 5 2 10 0 3 6 2 13 0 3 7 2 16 0 3 8 0 88 219 x1 12 0 3 2 22 LC0 3z 10 2 25 LCO 3 11 2 28 LCO 3 12 2 31 LC0O 3 13 2 34 LCO 3 14 2 37 LCO 3 15 2 40 Vc4 Connect 1 MQ load resistor between Vss and Vc4 3 2 gt 3 2 V without panel load x0 95 5 Connect 1 MQ load resistor between Vss and Vcs 2 Vc23 2 Vc3 V without panel load x0 95 SVD voltage Vsvp1 SVDS0 3 0 internal 2 20 V Ta 25 C SVDS0 3 1 2 20 SVDS0 3 2 2 20 SVDS0 3 3 2 20 SVDS0 3 4 2 20 SVDS0 3 5 2 30 SVDS0 3 6 2 40 SVDS0 3 7 Typ 2 50 Typ SVDS0 3 8 x0 93 2 60 x1 07 SVDS0 3 9 2 70 SVDS0 3 10 2 80 SVDS0 3 11 2 90 SVDS0 3 12 3 00 SVDS0 3 13 3 10 SVDS0 3 14 3 20 SVDS0 3 15 3 30 SVD voltage external 3 Vsvp2 SVDSO 3 0 external Ta 25 C 0 85 0 95 1 05 V SVD circuit response time 25 100 us Current consumption During HALT LCD power OFF 1 2 1 5 3 uA Ta 25
4. SEGO SEG1 SEG2 SEG3 SEG47 COMO DO DO DO DO DO COM1 D1 D1 D1 D1 D1 FOOOH F002H F004H F006H FO5EH COM2 D2 D2 D2 D2 D2 LPAGE D3 D3 D3 D3 D3 0 COM4 DO DO DO DO DO COM5 D1 D1 D1 D1 D1 F001H F003H F005H F007H FO5FH COM6 D2 D2 D2 D2 D2 D3 D3 D3 D3 D3 COMO DO DO DO DO DO COM1 D1 D1 D1 D1 D1 F100H F102H F104H F106H F15EH COM2 D2 D2 D2 D2 D2 LPAGE D3 D3 D3 03 _ D3 1 COM4 DO DO DO DO DO COM5 D1 D1 D1 D1 D1 F101H F103H F105H F107H F15FH COM6 D2 D2 D2 D2 D2 D3 D3 D3 03 _ D3 _ DO F200H DO F202H DO F204H DO F206H C DO F25EH c When 1 8 duty 48 x 8 mask option is selected Fig 4 7 5 1 Correspondence between display memory and LCD dot matrix When a bit in the display memory is set to 1 the corresponding LCD dot goes ON and when it is set to 0 the dot goes OFF At 1 17 1 16 duty drive all data of COM0 COM16 15 is output At 1 8 duty drive data only corresponding to COMO0 COM7 is output However since the display memory has capacity for two screens it is designed so that the memory for COM8 COM15 shown in Figure 4 7 5 1 a can also be used as 15 Select either FOOOH FO5FH or F100H F15FH for the area to be displayed to be output from COM
5. Register Address Comment D3 D2 D1 DO Init 1 1 0 CLKCHG 0 OSC3 05 1 CPU clock switch LKCH D FFOOH Ree ummy OSCC 0 On Off OSC3 oscillation On Off RW R RW 0 3 2 Unused 0 General purpose register TPS 0 MB DRS TPS 0 Pulse Tone pulse mode selection FF10H 0 3 2 Unused RW R RW MB 0 33 3 66 6 40 60 Make Break ratio DRS 0 20pps 10pps Dialing pulse rate selection PTS3 0 7 Pause time selection initial value 4 sec PTS3 PTS2 PTS1 PTSO PTS 1 PTS3 0 0 4 5 6 7 FF11H Time sec x 1 2 3 4 5 6 7 RW 51 0 PTS3 0 8 9 10 11 12 13 14 15 50 0 Time sec 8 9 10 11 12 14 15 FTS3 0 71 Flash time selection initial value 563 ms FTS3 FTS2 FTS1 FTSO FTS2 1 FTS3 0 0 1 2 3 4 5 6 7 FF12H Time ms 94 188 281 375 469 563 656 RW FTS1 1 FTS3 0 8 9 10 11 12 13 14 15 FTSO 0 i Time ms 750 844 938 1031 1125 1219 1313 1406 CHFO CHDO CRMO CTMO CHFO 0 HFO DC output R13 should be et at 1 FF13H CHDO 0 HDO DC RI2 output selection R12 should be fixed at 1 RW CRMO 0 XRMUTE DC R11 output selection R11 should be fixed at 1 CTMO 0 DC _ R10 output selection R10 should be fixed at 1 HF 0 Yes No Hand free HF HOLD PAUSE FLASH FF14H is HOLD 0 On Off Hold line function RW w PAUSE 3 0 Yes N
6. Register Address D3 D2 D1 DO Name Init 1 0 IK Enable Disable SKo3 sikoz sikoo 105 0 Enable Disable FF20H SIK02 0 Enable Disable Xon Xie E 01 0 Enable Disable interrupt selection register SIK00 0 Enable Disable 42 i J 02 01 a 2 High Low 2 High Low 2 High Low J KCP03 1 VI m KCP03 02 01 1 F FF22H n NS K00 K093 input comparison register RW 01 1 1 i E IK1 Enable Disable sik11 919 0 Enable Disable FF24H SIK12 0 Enable Disable kiirii adedi 2 ski 0 Enable Disable interrupt selection register SIK10 0 Enable Disable J K12 Kt1 K10 High Fras HEN Ki 2 High screed input port dat k11 2 High Low 10 2 High Low KCP13 12 11 KCP10 1 2 7 12 1 el FF26H 10 input comparison register RW KCP11 1 4 KCP10 1 i f ROSHIZ Hi Z tput FOUTE 0 FOUT FOUTE 1 Hi 1 ROSHIZ Ro2HIZ RotHiz 109 0 Quipu RO2HIZ 0 Hi Z Output RO2 PTOUT 0 TOUT PTOUT 1 Hi z control RW RO1HIZ 0 Hi Z Output R01 BZOUT 0 B
7. o Address 2 NM ENDE fel Interrupt selection Interrupt mask T register SIKOO 10 i i register EIKO 1 Address Ek Address MN oun D moo 2 2 2 221 13 ede i P AA Fig 4 4 2 1 Input interrupt circuit configuration 28 EPSON 51 63558 TECHNICAL MANUAL CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Input Ports The interrupt selection register SIK and input comparison register KCP are individually set for the input ports K00 K03 and K10 K13 and can specify the terminals for generating interrupt and interrupt timing The interrupt selection registers SIK00 SIKO03 SIK10 SIK13 select what input of K00 K03 and K10 K13 to use for the interrupt Writing 1 into an interrupt selection register incorporates that input port into the interrupt generation conditions The changing the input port where the interrupt selection register has been set to 0 does not affect the generation of the interrupt The input interrupt timing can select that the interrupt be generated at the rising edge of the input or that it be generated at the falling edge according to the set value of the input comparison registers 00 KCP03 KCP10 KCP13 By setting these two conditions the interrupt for K00 K03 or K10 K13 is generated when input ports in which an interrupt has been en
8. AVDD AVsS 5 RING FSK demodulator gt gt FSKIN FB 4 E PME CDIN Carrier detection circuit RDIN E hi 77 enerator VREF Reference voltage g BWDN generation circuit lt Fig 4 15 1 2 FSK core configuration The external terminals of the FSK demodulator are as follows AVDD AVss Power terminals for the FSK block Supply power respectively as AVDD VDD AVss Vss TIP Inverted input terminal of the input amplifier RING Non inverted input terminal of the input amplifier FB Feedback output terminal of the input amplifier BPOUT Output terminal of the band pass filter CDIN Input terminal for carrier signal detection RDIN Input terminal for ring signal detection RDRC I O terminal for connecting an RC network VRFF Reference voltage 1 2VDD output terminal The basic external connection diagram is shown in Figure 4 15 1 3 1000pF 10k Protection 7 RING Network RING 1000pF 10k 470k FB 1 RDIN O2uF 4 4 O2uF m T 0 1uF 5 270k CDIN RDRC 0 2uF eee 0 1 AVDD VDD AVss Vss Fig 4 15 1 3 Basic external connection diagram example for Bellcore 51 63558 TECHNICAL MANUAL EPSON 137 CHAPTER 4 PERI
9. PTDO3 13 PTDO 12 PTDO1 11 00 10 Preset Reload amp Interrupt generation Fig 4 10 2 1 Basic operation timing of down counter 66 EPSON 51 63558 TECHNICAL MANUAL CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Programmable Timer 4 10 3 Counter mode The programmable timer can operate in two counter modes timer mode and event counter mode It can be selected by software 1 Timer mode The timer mode counts down using the prescaler output as an input clock In this mode the program mable timer operates as a periodical timer using the OSC1 or OSC3 oscillation clock as a clock source Timer 0 can operate in both the timer mode and the event counter mode The mode can be switched using the timer 0 counter mode selection register EVCNT When the EVCNT register is set to 0 timer 0 operates in the timer mode Timer 1 operates only in the timer mode At initial reset this mode is set Refer to Section 4 10 2 Setting of initial value and counting down for basic operation and control The input clock in the timer mode is generated by the prescaler built into the programmable timer The prescaler generates the input clock by dividing the OSC1 or OSC3 oscillation clock Refer to the next section for setting
10. 11 Not Use 2 Use 3 INPUT PORT PULL UP RESISTOR e 00 1 With Resistor 2 Gate Direct e K01 711 With Resistor 2 Gate Direct e K02 1 With Resistor 2 Gate Direct 1 With Resistor 2 Gate Direct e K10 711 With Resistor 2 Gate Direct 1 With Resistor 2 Gate Direct e K12 1 With Resistor 2 Gate Direct e K13 711 With Resistor 2 Gate Direct 4 OUTPUT PORT OUTPUT SPECIFICATION ROO 11 Complementary 2 Nch OpenDrain R01 1 Complementary 2 Nch OpenDrain e R02 C 1 Complementary 2 Nch OpenDrain e R03 C 1 Complementary 2 Nch OpenDrain e R10 1 Complementary 2 Nch OpenDrain e R11 11 Complementary 2 Nch OpenDrain e R12 11 Complementary 2 Nch OpenDrain e R13 1 Complementary 2 Nch OpenDrain e R20 L 1 Complementary 2 Nch OpenDrain e R21 11 Complementary 2 Nch OpenDrain e R22 1 Complementary 2 Nch OpenDrain R23 11 Complementary 2 Nch OpenDrain EPSON 51 63558 TECHNICAL MANUAL 5 PORT OUTPUT SPECIFICATION NNNNNNNNNNNNNNNN 712 Nch OpenDrain Nch OpenDrain Nch OpenDrain Nch OpenDrain Nch OpenDrain Nch OpenDrain Nch OpenDrain Nch OpenDrain Nch OpenDrain Nch OpenDrain Nch OpenDrain Nch OpenDrain Nch OpenDrain Nch OpenDrain Nch OpenDrain Nch OpenDrain 72 Gate Direct 2 Gate Direct 12 Gate Direct 2 Gate Direct 2 Gate Direct 72 Gate Direct 2 Gate Direct e POO 1 Complementary 01 1
11. gt ROO XBZ 256 Hz One shot buzzer Buzzer output R00 R01 XBZ control circuit control circuit output circuit R01 BZ BZSHT ft BZE BZOUT XBZOUT BZSTP SHTPW Fig 4 12 1 1 Configuration of sound generator 4 12 2 Buzzer output circuit The 51 63558 uses the 01 BZ and ROO XBZ terminals for outputting buzzer signals To drive piezoelectric buzzer with one terminal use the BZ signal output from the 01 BZ terminal The piezo electric buzzer should be driven via a bipolar transistor Since the RO1 BZ terminal goes High level when the buzzer signal is stopped use a PNP transistor as shown in Figure 4 12 2 1 VDD VDD R01 BZ Vss Fig 4 12 2 1 Buzzer output circuit using the ROI BZ terminal The 51 63558 allows direct driving of a piezoelectric buzzer using both the 01 BZ and ROO 2 terminals In this case a piezoelectric buzzer should be connected to these terminals via protection resistors 100 as shown in Figure 4 12 2 2 R01 BZ ROO XBZ Fig 4 12 2 2 Direct driving a piezoelectric buzzer using the ROI BZ R00 XBZ terminals 100 EPSON 51 63558 TECHNICAL MANUAL CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Sound Generator 4 12 3 Control of buzzer output The R01 and R00 terminals for buzzer output set as general purpose output ports at initial reset
12. Do not write 0 0000B to the register because it may cause a malfunction At initial reset the inter digit pause time is set to 750 msec IDP 1000B The following summarizes initial setting items that must be set before outputting dial pulses 1 Set to pulse mode TPS 1 2 Select a pulse rate 10 pps or 20 pps using DRS 3 Select a make ratio 40 60 or 33 3 66 6 using MB 4 Select inter digit pause time 94 msec to 1 406 msec using The following explains how to output dial pulses and the circuit operation First write 1 to the HSON register 18 D3 so the dialer is in off hook status As a result the DP terminal goes High VDD level Next write digit of the dial number to be transmitted to the TCD3 TCD0 register FF17H Table 4 14 5 2 shows the relationship of write data and pulse counts Table 4 14 5 2 Pulse count selection TCD code Pulse count TCD code Pulse count D3 D2 D1 DO D3 D2 D1 DO0 Unavailable 11010 10 8 010101 1 1101011 9 0101110 2 1101110 10 010111 3 1 0 1 1 11 0111010 4 1111010 12 0111011 5 1111011 13 0111110 6 1111110 14 0111111 T 1111111 15 Do not write 0 0000 to the TCD register because it may cause a malfunction For a dial number between 1 to 9 the number is used for the pulse count as is Dial number 0 represents 10 p
13. FR output P23 terminal When 1 17 duty is selected CL output P22 terminal FR output P23 terminal When 1 16 duty is selected CL output P22 terminal FR output P23 terminal When 1 8 duty is selected Fig 4 6 5 1 Output waveforms of CL and FR signals 51 63558 TECHNICAL MANUAL EPSON 43 CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION I O Ports 4 6 6 I O memory of I O ports Tables 4 6 6 1 a and b show the I O addresses and the control bits for the I O ports Table 4 6 6 1 a Control bits of I O ports Register Address D3 D2 D1 DO Init 1 0 locos 1002 IOCO 1000 Bai FF40H 00 03 I O control register RW 0 01 0 Output Input OC00 0 Output Input PULOS PULO2 PULOO irm FF41H 1 On oft 00 03 pull up control register PULOO 1 On Off 1 Po Poi poo 703 po FF42H Po2 2 High Low P01 32 High Low 00 2 High Low C13 0 Output Input P13 I O control register General purpose register when SIF clock sync slave is selected C12 0 Output Input P12 T O control register General purpose r
14. 8 Hz interrupt request 4 A A A A A A 2 Hz interrupt request 1 Hz interrupt request A Fig 4 8 3 1 Timing chart of clock timer As shown in Figure 4 8 3 1 interrupt is generated at the falling edge of the frequencies 32 Hz 8 Hz 2 Hz 1 Hz At this time the corresponding interrupt factor flag ITO IT1 IT2 IT3 is set to 1 Selection of whether to mask the separate interrupts can be made with the interrupt mask registers EITO EIT1 EIT2 EIT3 However regardless of the interrupt mask register setting the interrupt factor flag is set to 1 at the falling edge of the corresponding signal 58 EPSON 51 63558 TECHNICAL MANUAL CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Clock Timer 4 8 4 I O memory of clock timer Table 4 8 4 1 shows the I O addresses and the control bits for the clock timer Table 4 8 4 1 Control bits of clock timer Register Address Comment D3 D2 D1 DO Name Init 1 1 0 0 3 e Unused 0 0 0 3 2 Unused FF78H m TMRST 3 Reset Reset Invalid Clock timer reset writing w AN TMRUN 0 Run Stop Clock timer Run Stop TM3 0 Clock timer data 16 Hz IMO TM2 0 Clock timer data 32 Hz PECARI TM1 0 Clock timer data 64 Hz n TMO 0 Clock timer data 128 Hz TM7 0 Clock timer data 1 Hz TM TM6 TMS TM6 0 Clock timer data 2 Hz
15. tsa1 lt Sampling 1 clock e 1 Eu Erroneous start bit detection signal r Ulisa a 164 EPSON 51 63558 TECHNICAL MANUAL CHAPTER 7 ELECTRICAL CHARACTERISTICS 7 7 FSK Demodulator Characteristics Unless otherwise specified 5 0 Vss 0V fCLK 3 579545MHz Ta 20 to 70 C Item Symbol Condition Min Typ Max _ Unit Transfer rate TRATE 1188 1200 1212 Bell202 mark logic 1 fBi 1188 1200 1212 Hz frequency Bell202 space logic 0 2178 2200 2222 Hz frequency ITU T V 23 mark logic 1 fvi 1280 1300 1320 Hz frequency ITU T V 23 space logic 0 0 2068 2100 2132 Hz frequency Signal to noise ratio SNR 20 dB Band pass filter gain 1 300Hz 92 dB 1200Hz 42 7 dB 1700Hz 42 8 dB 2200Hz 42 7 3000Hz 22 4 4000Hz 3 7 gt 10000 2 20 0 Carrier detection ON CDon Vpp 5 0V 51 48 dBm sensitivity 2 Carrier detection OFF CDorr Vpp 5 0V 57 54 dBm sensitivity 2 Input clock frequency fCLK 0 1 3 579545 0 1 MHz Input AC impedance RIN 5 0 between TIP RING pin and VREF 70 100 130 FSKON set up time tsup 20 ms Carrier detection response tcDON 3 6 25 9 ms time tcDOFF 5 7 5 10 Value measured between TIP RING and BPOUT 2 The following expressions can be us
16. 19 lZ Output 2 2 FF32H R12HIZ 0 Hi Z Output RI2 CHDO 0 HDO CHDO 1 Hi z control RW R11HIZ 0 Hi Z Output R11 CRMO 0 XRMUTE CRMO 1 Hi z control R10HIZ 0 Hi Z Output RIO CTMO 0 XTMUTE CTMO 1 Hi z control R13 R12 R11 R10 R13 1 High Low R13 output port data CHFO 0 Fix at 1 when is used FF33H XRMUTE XTMUTE R12 1 High Low R12 output port data CHDO 0 Fix at 1 when HDO is used BIN R11 1 High Low R11 output port data 0 Fix at 1 when XRMUTE is used R10 1 High Low RIO output port data CTMO 0 Fix at 1 when XTMUTE is used R23HIZ Hi Z tput R22HIZ ReoHiz 129 0 R22HIZ 0 Hi Z Output FF34H R20 R23 Hi z control RW 21 2 0 Hi Z Output R20HIZ 0 Hi Z Output J R2 1 High L R23 R22 R21 R20 3 ij W R22 1 High Low FF35H R20 R23 output port data BN R21 1 High Low R20 1 High Low 0 0 0 io e Unused FF65H 0 3 2 Unused R BZOUT 0 BZ DC 01 output selection RO1 should be fixed at 1 XBZOUT 0 XBZ DC ROO output selection ROO should be fixed at 1 CHSEL Prour cKSEL1 CKSELO CHSEL 0 TOUT output channel selection FFCiH PTOUT 0 On output control RW CKSEL1 0 OSC3 OSC1 Prescaler 1 source clock selection CKSELO 0 OSC3 05 1 Prescaler 0 source clock selection Initial value at initial reset 2 Not set in the circuit 3 Constantly 0
17. 5 0 Clock timer data 4 Hz TM4 0 Clock timer data 8 Hz EIT3 0 Enable Mask Interrupt mask register Clock timer 1 Hz Bile EH SS EIT2 0 Enable Mask Interrupt mask register Clock timer 2 Hz FFEBH 0 Enable Mask Interrupt mask register Clock timer 8 Hz RN EITO 0 Enable Mask Interrupt mask register Clock timer 32 Hz IT3 0 R R Interrupt factor flag Clock timer 1 Hz m 2 0 Yes No Interrupt factor flag Clock timer 2 Hz 0 w B Interrupt factor flag Clock timer 8 Hz RW ITO 0 Reset Invalid Interrupt factor flag Clock timer 32 Hz Initial value at initial reset 2 Not set in the circuit 3 Constantly 0 when being read TMO TM7 Timer data FF79H FF7AH The 128 1 Hz timer data of the clock timer can be read out with these registers These eight bits are read only and writing operations are invalid By reading the low order data FF79H the high order data is held until reading or for 0 48 1 5 msec one of shorter of them At initial reset the timer data is initialized to 00H TMRST Clock timer reset FF78H D1 This bit resets the clock timer When 1 is written Clock timer reset When 0 is written No operation Reading Always 0 The clock timer is reset by writing 1 to TMRST When the clock timer is reset in the RUN status opera tion restarts immediately Also in the STOP status the reset data is main
18. 6 p To peripheral circuits Clock OSC3 switch gt oscillation circuit A CPU clock selection signal Oscillation circuit control signal VD A Oscillation system voltage regulator Fig 4 3 1 1 Oscillation system block diagram 4 3 2 OSCI oscillation circuit The OSC1 crystal oscillation circuit generates the main clock for the CPU and the peripheral circuits The oscillation frequency is 32 768 kHz Figure 4 3 2 1 is the block diagram of the OSC1 oscillation circuit Cex Ke gt 5 1 gt TOCPU M and peripheral circuits 8L is X xa C DX Q Vss Be Vss Fig 4 3 2 1 8 oscillation circuit As shown in Figure 4 3 2 1 the crystal oscillation circuit can be configured simply by connecting the crystal oscillator X tal of 32 768 kHz Typ between the OSC1 and OSC2 terminals and the trimmer capacitor between the OSC1 and Vss terminals 1C63558 TECHNICAL MANUAL EPSON 25 CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Oscillation Circuit 4 3 3 OSC3 oscillation circuit The 51 63558 has built in the OSC3 oscillation circuit that generates the CPU s sub clock 3 58 MHz for high speed operation and the source clock for peripheral circuits needing a high speed clock program mable timer FOUT output To configure a ceramic oscillation circuit a ceramic os
19. and 1 registers Table 4 5 4 2 FOUT clock frequency FOFQ1 FOFQO Clock frequency 1 1 foc 1 0 fosci 0 1 fosci x 1 8 0 0 fosci x 1 64 fosci Clock that is output from the OSCI oscillation circuit fosc3 Clock that is output from the OSC3 oscillation circuit When fOSC3 is selected for the FOUT signal frequency it is necessary to control the OSC3 oscillation circuit before output Refer to Section 4 3 Oscillation Circuit for the control and notes Figure 4 5 4 2 shows the output waveform of the FOUT signal 1C63558 TECHNICAL MANUAL EPSON 35 CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Output Ports ROSHIZ register Fix at 0 RO3 register Fix at 1 FOUTE register 0 ex 0 FOUT output Fig 4 5 4 2 Output waveform of FOUT signal XTMUTE R10 The R10 terminal can output an XTMUTE signal The XTMUTE signal is the transmitter mute signal used for the telephone function To output the XTMUTE signal set the R10 port as the XTMUTE output by writing 1 to the CTMO register and fix the R10 register at 1 and the R10HIZ register at 0 Use the CTMUTE register for controlling the XTMUTE signal output Refer to Section 4 14 Telephone Function for details of the signal and controlling method XRMUTE R11 The R11 terminal can output an XRMUTE signal The XRMUTE signal is th
20. Input comparison register Interrupt selection register Lr ITO T5 EITO sm ISW1 prop EISW1 ISW10 EISW10 Fig 4 16 1 Configuration of the interrupt circuit 146 EPSON 51 63558 TECHNICAL MANUAL CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Interrupt and HALT 4 16 1 Interrupt factor Table 4 16 1 1 shows the factors for generating interrupt requests The interrupt flags are set to 1 depending on the corresponding interrupt factors The CPU operation is interrupted when an interrupt factor flag is set to 1 if the following conditions are established The corresponding mask register is 1 enabled The interrupt flag is 1 ET The interrupt factor flag is reset to 0 when 1 is written At initial reset the interrupt factor flags are reset to 0 Since the watchdog timer s interrupt is NMI the interrupt is generated regardless of the setting above and no interrupt factor flag is provided Table 4 16 1 1 Interrupt factors Interrupt factor Interrupt factor flag Dialer dialing cycle completion ID FFF9H DO Ring detection falling edge or rising edge IRDET FFFAH DO Carrier detection falling edge or rising edge ICDET FFFAH D1 Programmable timer 1 counter 0 FFF2H D
21. 13FFH Y gt 4 bits Fig 3 3 1 Configuration of data RAM 3 4 Data ROM The data ROM is a mask ROM for loading various static data such as a character generator and has a capacity of 2 048 words x 4 bits The data ROM is assigned to addresses 8000H to 87FFH on the data memory map and the data can be read using the same data memory access instructions as the RAM 51 63558 TECHNICAL MANUAL EPSON 13 CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Memory CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION The peripheral circuits of S1C63558 timer I O etc are interfaced with the CPU in the memory mapped I O method Thus all the peripheral circuits can be controlled by accessing the I O memory on the memory map using the memory operation instructions The following sections explain the detailed operation of each peripheral circuit 4 1 Memory The 51 63558 data memory consists of 5 120 word RAM 2 048 word data 816 bit display memory and 97 word peripheral I O memory Figure 4 1 1 shows the overall memory map of the 51 63558 and Tables 4 1 1 a h the peripheral circuits I O space memory maps 0000H 1400H 8000H 8800H F000H FFFFH RAM area Unused area Data ROM area Unused area memory area FOOOH F25EH _ Fig 4 1 1 Memory Display memory area Unused area Peripheral I O area
22. Unused FFF5H 0 3 2 Yes No _ Unused R RW 0 3 2 W Unused 0 Reset Invalid Interrupt factor flag 10 13 IT m ITO IT3 0 R R Interrupt factor flag Clock timer 1 Hz FFF6H IT2 0 Yes No Interrupt factor flag Clock timer 2 Hz RW 0 W W Interrupt factor flag Clock timer 8 Hz ITO 0 Reset Invalid Interrupt factor flag Clock timer 32 Hz 0 3 2 R R Unused 0 o I9Wi ISWIO 0 3 es i FFF7H 1 20 _ nuse R RW ISW1 0 W Interrupt factor flag Stopwatch timer 1 Hz ISW10 0 Reset Invalid Interrupt factor flag Stopwatch timer 10 Hz 51 63558 TECHNICAL MANUAL EPSON 21 CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Memory Table 4 1 1 h I O memory map F FF8H FF FAH Register Address Comment D3 D2 D1 DO Init 1 0 0 3 2 R Unused FFF8H 1 ISTAS oos ISERS 0 Yes No _ Interrupt factor flag Serial I F 2 error R BN ISTRS 0 W Interrupt factor flag Serial I F 2 transmit completion ISRCS 0 Reset Invalid Interrupt factor flag Serial I F 2 receive completion 3 2 R R Unused 0 0 0 ID PA FFF9H 0 3 32 Yes No Unused R BIN 0 3 2 W W Unused ID 0 Reset Invalid Interrupt factor flag Dialer 3 2 0 0 IRDET ICDET 2 Ny ont FFFAH ML d RW IRDET 0 w
23. 15 Do not write 0 0000 to the PTS register because it may cause a malfunction The specified pause time will be inserted when 1 is written to the PAUSE bit FF14HeD1 At initial reset this register is set to 0100 4 seconds FTSO FTS3 Flash time selection FF12H Selects a flash time from among the 15 types shown in Table 4 14 10 3 Table 4 14 10 3 Selection of flash times FTS Flash time FTS Flash time D3 D2 D1 DO msec 03 02 01 00 msec 0 10 1010 Unavailable 14010 0 750 010 1 94 11010 1 844 0101110 188 140110 938 0101111 281 110111 1031 0111010 375 11110 0 1125 0111011 469 11110 1 1219 0111110 563 111110 1313 0111111 656 1 1 1 l 1406 Do not write 0 0000B to the FTS register because it may cause a malfunction The specified flash time will be inserted when 1 is written to the FLASH bit 14 0 At initial reset this register is set to 0110B 563 msec HOLD Hold line function FF14H D2 Controls the hold line function and HDO signal output When 1 is written ON High level output on R12 terminal When 0 is written OFF Low level output on R12 terminal Reading Valid This register controls the HDO signal output to the R12 terminal when the HDO function has been selected The HDO output function is set by writing 1 to the CHDO register FF13He D2 In this case the
24. Cac y R03 FOUT eee L rT R10 XTMUTE R11 XRMUTE Piezo e O O E R12 HDO rct Cres Coil R13 HFO O 2 20 03 0 425 2 8 22maq a ro VSS 1 ELEI gt 00 OF gt gt gt x o o em v o eu Hn S 8 OG Of Of o 2 Ld gt Speech Network Hook Switch ON i A gt OFF Rectifier RINGo LAN Protection Network 4 470k epo at T 1 A meo o HL oai E 33k dau T 777 X tal Crystal oscillator 32 768 kHz 34 KQ Trimmer capacitor 5 25 pF CR Ceramic oscillator 3 58 MHz Cac Gate capacitor 30 pF Drain capacitor 30 pF C1 C7 Capacitor 0 2 UF Cp Capacitor 10 uF CRES RESET terminal capacitor 0 1 UF Note The table is simply an example and is not guaranteed to work 1C63558 TECHNICAL MANUAL EPSON 159 CHAPTER 7 ELECTRICAL CHARACTERISTICS CHAPTER 7 ELECTRICAL CHARACTERISTICS 7 1 Absolute Maximum Rating Vss 0V Item Symbol Rated value Unit Supply voltage VDD 0 5 to 7 0 V Input voltage 1 VI 0 5 to VDD 0 3 V Input voltage 2 VIOSC 0 5 to 0 3 V Permissible total output current 1 10 mA Operating temperature Topr 20 to 70 Storage temperature Tstg 65 to 150 Soldering temperature time Tsol 260 C 10sec lead section E Permissible dissipation 2
25. Note Memory is not implemented in unused areas within the memory map Further some non imple mentation areas and unused access prohibition areas exist in the display memory area and the peripheral I O area If the program that accesses these areas is generated its operation cannot be guaranteed Refer to Section 4 7 5 Display memory for the display memory and the I O memory maps shown in Tables 4 1 1 a h for the peripheral I O area 14 EPSON 1C63558 TECHNICAL MANUAL CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Memory Table 4 1 1 a I O memory FFOOH FF 18H Register Address Comment D3 D2 D1 DO Name Init 1 0 CLKCHG 0 OSC3 05 1 CPU clock switch LKCH D FFOOH iia lta i OSCC 0 On Off OSC3 oscillation On Off RW R RW 0 3 2 Unused Dummy 0 General purpose register SVDS3 0 71 SVD criteria voltage setting SVDS3 SVDS2 SVDS1 SVDSO 0 SVDS3 0 0 1 2 3 4 5 6 7 FFO4H Voltage V 2 20 1 05 2 20 2 20 2 20 2 20 2 30 2 40 2 50 RW SVDS1 0 SVDS3 0 8 9 10 1 12 13 14 15 SVDS0 0 Voltage V 2 60 2 70 2 80 2 90 3 00 3 10 3 20 3 30 0 3 2 Unused 0 SVDDT SVDON b FFOSH 0 3 2 Unused R RW SVDDT 0 Low Normal SVD evaluation data SVDON 0 On Off SVD circuit On Off RO3 output selecti
26. 01 0 Enable Disable SIK00 0 Enable Disable KCP03 1 E n KCPOt 0 SS FF22H ae Ua K00 K03 input comparison register RW KCP01 1 L 2 _1 i f Enable Disable siki2 sikio SI S 0 Enable Disable FF24H SIK12 0 Enable Disable E E EEE xi a Sik11 0 Enable Disable interrupt selection register SIK10 0 Enable Disable KCP1 1 E fq KCP13 KCP12 KCP11 KCP10 pus 1 E NS FF26H Ua K10 K13 input comparison register BIN KCP11 1 4 KCP10 1 3 2 Unused 0 o avetcplcpetcr 9 FF67H 0 3 2 Unused R RW RDETCP 0 L RDET comparison register CDETCP 0 CDET comparison register 3 2 S 0 0 EPT EIPTO eo aie FFE2H id R RW EIPT1 0 Enable Mask Interrupt mask register Programmable timer 1 EIPTO 0 Enable Mask Interrupt mask register Programmable timer 0 0 43 2 Unused EISER EISTR EISR 0 S SR EISER 0 Enable Mask Interrupt mask register Serial I F 1 error R RW EISTR 0 Enable Mask Interrupt mask register Serial I F 1 transmit completion EISRC 0 Enable Mask _ Interrupt mask register Serial I F 1 receive completion 3 2 Unused 0 0 iban FFE4H 7 x R RW 0 3 2 Unused EIKO 0 Enable Mask Interrupt mask register K00 K03 3 2 S 0 0 5 R RW 0 3 2 Unused EIK1 0 Enable Mask Interrupt mask registe
27. 1153 03 EPSON CMOS 4 BIT SINGLE CHIP MICROCOMPUTER S1C63558 Technical Manual 1C63558 Technical Hardware Limm o SAVING SEIKO EPSON CORPORATION NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson Seiko Epson reserves the right to make changes to this material without notice Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and further there is no representation that this material is applicable to products requiring high level reliability such as medical products Moreover no license to any intellectual property rights is granted by implication or otherwise and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from the Ministry of International Trade and Industry or other approval from another government agency SEIKO EPSON CORPORATION 2001 All rights reserved Revisions and Additions for this manual Chapter Section Page Item Contents 2 2 1 2 8 Table 2 1 2 1 LCD drive voltage when
28. 2 Not set in the circuit ID RDETCP CDETCP EIRDET EICDET IRDET ICDET EIPT1 EIPTO IPT1 IPTO EISER EISTR EISRC EISERS EISTRS EISRCS ISER ISTR ISRC ISERS ISTRS ISRCS 3 Constantly 0 when being read Interrupt mask register FFE9H DO Interrupt factor flag FFF9H DO Refer to Section 4 14 Telephone Function RDETP CDET comparison registers FF67H D1 DO Interrupt mask registers FFEAH D1 DO Interrupt factor flags FFFAH D1 DO Refer to Section 4 15 FSK Demodulator Interrupt mask registers FFE2H D1 DO Interrupt factor flags FFF2H D1 DO Refer to Section 4 10 Programmable Timer Interrupt mask registers FFE3H D2 DO Interrupt mask registers FFE8H D2 DO Interrupt factor flags FFF3H D2 DO Interrupt factor flags FFF8H D2 DO Refer to Section 4 11 Serial Interface 150 EPSON 1C63558 TECHNICAL MANUAL CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Interrupt and HALT KCP03 KCP00 KCP13 KCP10 Input comparison registers FF22H FF26H SIK03 SIKOO SIK13 SIK10 Interrupt selection registers FF20H FF24H EIKO EIK1 Interrupt mask registers FFE4H DO FFE5H DO IKO IK1 Interrupt factor flags FFFAH DO FFF5H DO Refer to Section 4 4 Input Ports Interrupt mask registers FFE6H IT3 ITO Interrupt factor flags FFF6H Refer to Section 4 8 Clock Timer EISW1 EISW10 Interrupt mask registers FFE7H D1 DO ISW1 ISW10
29. 5 6 404 2118 110 4 874 356 20 P23 520 2118 50 COMIO SEG46 1874 453 81 SEGIS 520 2118 111 VDD 874 471 21 P22 635 2118 51 COMII SEG45 1874 568 82 SEG14 635 2118 112 RESET 874 587 22 21 751 2118 52 COMI2Z SEG44 1874 684 83 5 751 2118 113 TEST 874 702 23 P20 866 2118 53 COM13 SEG43 1874 799 84 SEGI2 866 2118 114 TONE 874 818 24 P13 982 2118 54 COMIM SEG42 1874 915 85 11 982 2118 115 DP 874 933 25 12 1097 2118 55 COMI5 SEG41 1874 1030 86 SEGIO 1097 2118 116 R23 874 1049 26 P11 1213 2118 56 COM16 SEG40 1874 1146 87 SEG9 1213 2118 117 R22 874 1164 27 P10 1351 2118 57 SEG39 1874 1261 88 SEG8 1351 2118 118 R21 874 1280 28 P03 1490 2118 58 SEG38 1874 1400 89 SEG7 1490 2118 119 R20 874 1419 29 P02 1629 2118 59 SEG37 1874 1538 90 SEG6 1629 2118 120 R13 874 1557 30 01 1767 2118 60 SEG36 1874 1677 91 SEGS 1767 2118 121 R12 874 1696 61 SEG35 1874 1815 122 R11 874 1834 1 Mask option 172 EPSON 51 63558 TECHNICAL MANUAL EPSON International Sales Operations AMERICA ASIA EPSON ELECTRONICS AMERICA INC EPSON CHINA CO LTD HEADQUARTERS 23F Beijing Silver Tower 2 North RD DongSanHuan 150 River Oaks Parkwa
30. RW w RW ENON 0 On Off Envelope On Off BZE 0 Enable Disable Buzzer output enable 0 3 2 Unused 0 BZSTP 25 3 Stop Invalid 1 shot buzzer stop writing FF6DH BZSHT 0 Trigger Invalid 1 shot buzzer trigger writing R RW Busy Ready I shot buzzer status reading SHTPW 0 1 125 31 2556 1 shot buzzer pulse width setting o ezro Bzrai gzroo BZFQ2 1 0 0 1 2 3 FF6EH BZFQ2 0 Frequency Hz 40960 32768 27307 2340 6 R RW BZFQ1 0 frequency BZFQ2 1 0 4 5 6 7 2 00 0 21 selection Frequency Hz 2048 0 1638 4 1365 3 1170 3 0 3 2 Unused 0 BDTY2 BDTY1 BDTYO BDTY2 0 L FF6FH Buzzer signal duty ratio selection R RW o refer to main manual BDTYO 0 x ow 2 Unused SMD 0 0 1 0 SMD1 5 00 ESIF SMD1 0 J Serial VF 1 Mode Clk sync master Clk sync slave FF70H SMD1 0 2 3 R RW SMDO 0 mode selection Mode Async 7 bit Async 8 bit ESIF 0 SIF VO Serial I F 1 enable P1x port function selection EPR PMD scsi scso EPR 0 Enable Disable wi I F 1 enable tegister FF71H PMD 0 Odd Even Serial I F 1 parity mode selection RW 5651 0 1 clock 5 51 01 0 1 2 3 SCS0 0 source selection Mode 1200 600bps 2400bps RXTRG 0 Run Stop Serial I F 1 receive status reading RXTRG RXEN TXTRG TXEN Trigger Serial I F 1 receive trigger writing FF72H RXEN 0 Enable Disable Serial I F 1 receive enable TXTR
31. Therefore the RO1 terminal must be set as the BZ output terminal by writing 1 to the BZOUT register before controlling buzzer output Furthermore the data register RO1 for the RO1 output port should be fixed at 1 and the high impedance register RO1HIZ at 0 When direct driving a piezoelectric buzzer the ROO terminal must be set as the XBZ output terminal similar to the R01 terminal Write 1 to the XBZOUT register to set the XBZ output Also in this case the data register 00 for the R00 output port should be fixed at 1 and the high impedance register ROOHIZ at 0 The buzzer signals generated by the sound generator are output from the BZ R01 and XBZ R00 terminals by writing 1 to the buzzer output enable register BZE When 0 is written to the BZE register the BZ R01 terminal goes High VDD and XBZ R00 terminal goes Low Vss RO1HIZ register 0 ROOHIZ register 0 R01 register 1 ROO register x BZOUT register O 1 o XBZOUT register 0 1 p BZE register 0 R01 BZ port lul ROO XBZ port Fig 4 12 3 1 Buzzer signal output timing chart Note Since the BZ and XBZ signals are generated asynchronous to the BZE register hazards may be produced when the signal goes ON OFF due to the setting of the BZE register 1C63558 TECHNICAL MANUAL
32. lt Precautions for Visible Radiation when bare chip is mounted gt Visible radiation causes semiconductor devices to change the electrical characteristics It may cause this IC to malfunction When developing products which use this IC consider the following precau tions to prevent malfunctions caused by visible radiations 1 Design the product and implement the IC on the board so that it is shielded from visible radiation in actual use 2 The inspection process of the product needs an environment that shields the IC from visible radiation 3 As well as the face of the IC shield the back and side too 158 EPSON 51 63558 TECHNICAL AMANUAL CHAPTER 6 BASIC EXTERNAL WIRING DIAGRAM CHAPTER 6 BASIC EXTERNAL WIRING DIAGRAM LCD panel 40 x 17 Input B HS P K00 K03 9 2 K10 K13 S CA P00 POS C1 P10 SIN ec C2 P11 yo P12 SCLK TEST P13 SRDY VoD P20 AVDD zz 21 2 51 63558 23 The potential of the substrate 0501 1 back of the chip is Vss X tal K ROO XBZ QUSE R01 BZ OSC3 R02 TOUT
33. 0 Refer to Section 4 14 Telephone Function for controlling the XTMUTE output When using the R10 output port for a general purpose output fix this register at 0 At initial reset this register is set to 0 1C63558 TECHNICAL MANUAL EPSON 39 CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Output Ports CRMO R11 output selection register FF13H D1 Selects the R11 terminal function When 1 is written XRMUTE output When 0 is written General purpose DC output Reading Valid When using the R11 terminal for the XRMUTE output write 1 to this register Furthermore fix the R11 register at 1 and the R11HIZ register at 0 Refer to Section 4 14 Telephone Function for controlling the XRMUTE output When using the R11 output port for a general purpose output fix this register at 0 At initial reset this register is set to 0 CHDO R12 output selection register FF13H D2 Selects the R12 terminal function When 1 is written HDO output When 0 is written General purpose DC output Reading Valid When using the R12 terminal for the HDO output write 1 to this register Furthermore fix the R12 register at 1 and the R12HIZ register at 0 Refer to Section 4 14 Telephone Function for controlling the HDO output When using the R12 output port for a general purpose output fix this register at 0 At initial reset this register is set to 0 CHFO R13 output selection register FF13H D3 Sel
34. 0 is written the watchdog timer does not count and does not generate the interrupt NMI At initial reset this register is set to 1 WDRST Watchdog timer reset FF07H DO Resets the watchdog timer When 1 is written Watchdog timer is reset When 0 is written No operation Reading Always 0 When 1 is written to WDRST the watchdog timer is reset and restarts immediately after that When 0 is written no operation results This bit is dedicated for writing and is always 0 for reading 4 2 4 Programming notes 1 When the watchdog timer is being used the software must reset it within 3 second cycles 2 Because the watchdog timer is set in operation state by initial reset set the watchdog timer to disabled state not used before generating an interrupt NMI if it is not used 24 EPSON 1C63558 TECHNICAL MANUAL CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Oscillation Circuit 4 3 Oscillation Circuit 4 3 1 Configuration of oscillation circuit The 51 63558 has two oscillation circuits OSC1 and OSC3 OSC1 is a crystal oscillation circuit that supplies the operating clock to the CPU and peripheral circuits OSC3 is a ceramic oscillation circuit When processing with the S1C63558 requires high speed operation the CPU operating clock can be switched from OSC1 to OSC3 by the software Figure 4 3 1 1 is the block diagram of this oscillation system OSC1 oscillation circuit Divider
35. 1 At initial reset these registers are all set to 1 XBZOUT ROO output selection register FF65H DO Selects the R00 terminal function When 1 is written XBZ output When 0 is written General purpose DC output Reading Valid When using the ROO terminal for the XBZ output write 1 to this register Furthermore fix the ROO register at 1 and the ROOHIZ register at 0 Refer to Section 4 12 Sound Generator for controlling the XBZ output When using the ROO output port for a general purpose output fix this register at 0 At initial reset this register is set to 0 BZOUT R01 output selection register FF65H D1 Selects the R01 terminal function When 1 is written BZ output When 0 is written General purpose DC output Reading Valid When using the R01 terminal for the BZ output write 1 to this register Furthermore fix the R01 register at 1 and the RO1HIZ register at 0 Refer to Section 4 12 Sound Generator for controlling the BZ output When using the R01 output port for a general purpose output fix this register at 0 At initial reset this register is set to 0 38 EPSON 1C63558 TECHNICAL MANUAL CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Output Ports PTOUT TOUT output control register FFC1H D2 Controls the TOUT output When 1 is written TOUT output ON When 0 is written TOUT output OFF Reading Valid By writing 1 to the PTOUT register when the R02 register
36. 50 EPSON 1C63558 TECHNICAL MANUAL CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION LCD Driver 4 7 5 Display memory The display memory is allocated to FOOOH F25EH in the data memory area and the addresses and the data bits correspond to COM and SEG outputs as shown in Figure 4 7 5 1 SEGO SEG1 SEG2 SEG3 SEG39 COMO DO DO DO DO DO DH FOOOH Di F002H F004H DI FOO6H FO4EH COM2 D2 D2 D2 D2 D2 COM3 D3 D3 D3 D3 D3 COM4 DO DO DO DO DO PH F001H pa F003H 005 E F007H 23 F04FH COM6 D2 D2 D2 D2 D2 8 ops D3 D3 D3 D3 o COM8 DO DO DO DO DO cow 100 p1 F102H F104H F106H i F14EH COM10 D2 D2 D2 D2 D2 11 D3 J D3 J D3 J D3 J D3 12 DO DO DO DO DO eels F101H te F103H D1 F105H F107H DI F14FH COM14 D2 D2 D2 D2 D2 15 D3 J D3 J D3 J D3 J D3 _ L COM16 DO F200H DO F202H DO F204H DO F206H DO F24EH Memory address Data bit a When 1 17 or 1 16 duty is selected
37. As soon as the SVDON register is reset to 0 the result is loaded to the SVDDT latch and the SVD circuit goes OFF To obtain a stable detection result the SVD circuit must be ON for at least 100 psec So to obtain the SVD detection result follow the programming sequence below 1 Set SVDON to 1 2 Maintain for 100 psec minimum 3 Set SVDON to 0 4 Read SVDDT When the SVD circuit is ON the IC draws a large current so keep the SVD circuit off unless it is 4 13 4 I O memory of SVD circuit Table 4 13 4 1 shows the I O addresses and the control bits for the SVD circuit Table 4 13 4 1 Control bits of SVD circuit Register Address Comment D3 D2 D1 DO Name Init 1 0 71 SVD criteria voltage setting SVDS3 SVDS2 SVDS1 SVDSO SVDS3 0 0 1 2 3 4 5 6 7 Voltage V 2 20 1 05 2 20 2 20 2 20 2 20 2 30 2 40 2 50 RW SVDS1 0 SVDS3 0 8 9 10 1 102 13 14 15 SVDSO 0 Voltage V 2 60 2 70 2 80 2 90 3 00 310 3 20 3 30 0 3 2 Unused SVDDT 0 Low Normal SVD evaluation data SVDON 0 On Off SVD circuit On Off FFO4H FFOSH Initial value at initial reset 2 Not set in the circuit 3 Constantly 0 when being read SVDS3 SVDS0 SVD criteria voltage setting register FF04H Criteria voltage for SVD is set as shown in Table 4 13 3 1 At initial reset this register is set to 0 SVDON SVD control ON OFF register FF05H DO Turns the SVD circuit ON and OFF Wh
38. Comment Init 1 0 Unused No Unused Interrupt factor flag Programmable timer 1 Invalid Interrupt factor flag Programmable timer 0 Unused _ No Interrupt factor flag Serial I F 1 error W Interrupt factor flag Serial I F 1 transmit completion Invalid Interrupt factor flag Serial I F 1 receive completion Unused _ No Unused W Unused Invalid Interrupt factor flag K00 K03 Unused _ No Unused Unused Invalid Interrupt factor flag K10 K13 Interrupt factor flag Clock timer 1 Hz No Interrupt factor flag Clock timer 2 Hz W Interrupt factor flag Clock timer 8 Hz Invalid Interrupt factor flag Clock timer 32 Hz Unused No _ Unused W Interrupt factor flag Stopwatch timer 1 Hz Invalid Interrupt factor flag Stopwatch timer 10 Hz R Unused No _ Interrupt factor flag Serial I F 2 error Interrupt factor flag Serial I F 2 transmit completion Invalid Interrupt factor flag Serial I F 2 receive completion IRDET ICDET Unused _ No Unused W Unused Invalid Interrupt factor flag Dialer Unused No Unused Interrupt factor flag FSK demodulator ring detection Invalid Interrupt factor flag FSK demodulator carrier detection Initial value at initial reset
39. Complementary e P02 1 Complementary P03 1 Complementary e P10 1 Complementary e P11 1 Complementary e P12 L 1 Complementary P13 1 Complementary P20 1 Complementary e P21 L 1 Complementary P22 1 Complementary P23 1 Complementary e P30 L 1 Complementary P31 1 Complementary e P32 1 Complementary P33 L 1 Complementary IN 6 PORT PULL UP RESISTOR POx __ 1 With Resistor 1 With Resistor P20 1 With Resistor e P21 1 With Resistor e P22 1 With Resistor P23 1 With Resistor 1 With Resistor 7 DP PORT OUTPUT SPECIFICATION 1 Complementary 2 Nch OpenDrain 8 SVD EXTERNAL VOLTAGE DETECTION 1 Not Use _ 2 Use 9 LCD DRIVER SPECIFICATION 1 40 seg 17 com 2 48 seg 8 10 FSK INTERNAL FEEDBACK RESISTOR 1 Use 2 Not Use CHAPTER 1 OUTLINE 51 63558 TECHNICAL MANUAL EPSON CHAPTER 2 POWER SUPPLY AND INITIAL RESET CHAPTER 2 POWER SUPPLY AND INITIAL RESET 2 1 Power Supply 51 63558 operating power voltage is as follows Supply voltage 2 2 V to 5 5 V The 51 63558 operates by applying a single power supply within the above range between and Vss The 51 63558 itself generates the voltage necessary for all the internal circuits by the built in power supply circuits shown in Table 2 1 1 Table 2 1 1 Power supply circuits Circuit Power supply circuit Output vo
40. Interrupt factor flag FSK demodulator ring detection ICDET 0 Reset Invalid Interrupt factor flag FSK demodulator carrier detection 22 EPSON 51 63558 TECHNICAL MANUAL CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Watchdog Timer 4 2 Watchdog Timer 4 2 1 Configuration of watchdog timer The 51 63558 has a built in watchdog timer that operates with a 256 Hz divided clock from the OSC1 as the source clock The watchdog timer starts operating after initial reset however it can be stopped by the software The watchdog timer must be reset cyclically by the software while it operates If the watchdog timer is not reset in at least 3 4 seconds it generates a non maskable interrupt NMI to the CPU Figure 4 2 1 1 is the block diagram of the watchdog timer Non maskable interrupt NMI OSC1 dividing signal 256 Hz Watchdog timer gt gt Watchdog timer enable signal Watchdog timer reset signal Fig 4 2 1 1 Watchdog timer block diagram The watchdog timer contains a 10 bit binary counter and generates the non maskable interrupt when the last stage of the counter 0 25 Hz overflows Watchdog timer reset processing in the program s main routine enables detection of program overrun such as when the main routine s watchdog timer processing is bypassed Ordinarily this routine is incorporated where periodic processing takes place just as for the timer interrupt routine The watchdog timer operates in the HALT mode If a HA
41. PERIPHERAL CIRCUITS AND OPERATION Memory Table 4 1 1 d I O memory map FF4EH FF67H Register Address Comment D3 D2 D1 DO Init 1 0 P33 2 High Low P33 I O port data P33 P32 P31 P30 General purpose register when SIF clock sync slave is selected XSRDYS XSCLKS SOUTS SINS P32 2 High Low P32 port data General purpose register when SIF clock sync is selected P31 2 High Low P31 T O port data ESIFS 0 RW General purpose register when SIF is selected P30 2 High Low P30 TO port data ESIFS 0 General purpose register when SIF is selected 0 3 2 Unused SMDIS 0S 0 1 0 SMD1S SMDOS ESIFS SMD1S 0 J Serial VF 2 Mode Clk sync master Clk sync slave FF58H SMDI1S 0S 2 3 R R W 5 005 0 J mode selection Mode Async 7 bit Async 8 bit ESIFS 0 SIF lO Serial I F 2 enable P3x port function selection EPRS PMDS scsis 5 508 EPRS 0 Enable Disable Serial I F 2 parity enable register FF59H PMDS 0 Odd Even Serial I F 2 parity mode selection RW 56515 0 SIF 2 clock SCSIS 0S 0 1 2 3 SCS0S 0 source selection Mode 1200 600bps 2400bps RXTRGS 0 Run Stop Serial I F 2 receive status reading RXTRGS RXENS TXTRGS TXENS Trigger Serial I F 2 receive trigger
42. SWDO0 SWDT7 Stopwatch timer data FF7DH FF7EH The 1 100 sec and the 1 10 sec data BCD can be read from SWD0 SWD3 SWD4 SWUT respec tively These eight bits are read only and writing operations are invalid At initial reset the timer data is initialized to 00H SWRST Stopwatch timer reset FF7CH D1 When 1 is written Stopwatch timer reset When 0 is written No operation Reading Always 0 The stopwatch timer is reset by writing 1 to SWRST timer data is set to 0 When the stopwatch timer is reset in the RUN status operation restarts immediately Also in the STOP status the reset data is maintained No operation results when 0 is written to SWRST This bit is write only and so is always 0 at reading SWRUN Stopwatch timer RUN STOP control register FF7CH DO Controls RUN STOP of the stopwatch timer When 1 is written RUN When 0 is written STOP Reading Valid The stopwatch timer enters the RUN status when 1 is written to the SWRUN register and the STOP status when 0 is written In the STOP status the timer data is maintained until the next RUN status or the timer is reset Also when the STOP status changes to the RUN status the data that is maintained can be used for resuming the count 1C63558 TECHNICAL MANUAL EPSON 63 CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Stopwatch Timer When data of the counter is read at run mode proper reading may not be obtained due to the c
43. The input and output modes of the I O ports are set with these registers When 1 is written Output mode When 0 is written Input mode Reading Valid The input and output modes of the I O ports are set in 1 bit unit Writing 1 to the I O control register makes the corresponding I O port enter the output mode and writing 0 induces the input mode At initial reset these registers are all set to 0 so the I O ports are in the input mode The I O control registers of the port which are set for the special output P22 P23 or input output of the serial interface 10 13 or P30 P33 become general purpose registers that do not affect the input output PULOO PULO3 PO port pull up control register FF41H PUL10 PUL13 P1 port pull up control register FF45H PUL20 PUL23 P2 port pull up control register FF49H PULS30 PUL33 port pull up control register FF4DH The pull up during the input mode are set with these registers When 1 is written Pull up ON When 0 is written Pull up OFF Reading Valid The built in pull up resistor which is turned ON during input mode is set to enable in 1 bit units The pull up resistor is included into the ports selected by the mask option By writing 1 to the pull up control register the corresponding I O ports are pulled up during input mode while writing 0 turns the pull up function OFF At initial reset these registers are all set to 1 so the pull up function i
44. an interrupt occurs Use the interrupt for setting the next digit number The pause and flash functions are executed by writing 1 to the PAUSE and FLASH bits and will generate an interrupt after the period of time set in 1 has passed It is not necessary to turn the function OFF 114 EPSON 51 63558 TECHNICAL MANUAL CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Telephone Function 3 Interrupt The dialing pause and flash functions generate an interrupt when their operation has finished At this time the interrupt factor flag ID FFF9H 00 is set to 1 An interrupt request to the CPU will be generated when the interrupt mask register EID FFE9H D0 is set to 1 and will be masked when EID is set to 0 However the interrupt factor flag ID will be set to 1 when the above function has completed even if the interrupt is masked The end of operations can also be checked by scanning the ID flag The ID flag is reset to 0 by writing 1 The ID flag must be cleared to 0 before starting the next interrupt Figure 4 14 3 2 shows an example of dialing pulse transmission procedure START y 1 Setting Write 1000 Select Pulse mode to FF10H Make ratio 40 60 Y Dialing rate 10 pps Write 0110 em to IDP Inter digit pause time 563 ms Wri T 111 bx EE Flash time 656 ms y Write 0010 to PTS time 2 sec Sas Executin
45. in pulse mode registers because it may cause a malfunction 3 The pause function control bit PAUSE FF14H D1 and the flash function control bit FLASH FF14H 00 are write only so software cannot control these functions on address FF14H using an ALU instruction AND OR Furthermore be aware that the pause function or the flash function is canceled when 0 is written to the PAUSE bit FF14HeD1 or the FLASH bit FF14He FSK demodulator 1 When starting the FSK demodulator operation the OSC3 oscillation circuit must be turned ON and the CPU operating clock must be switched to the OSC3 clock The OSCS oscillation circuit takes a maximum 5 msec for oscillation stabilization after turning the circuit ON Consequently allow an adequate waiting time after turning ON the OSC3 oscillation before starting the FSK operation Note that the oscillation start time will vary somewhat depending on the oscillator and on the externally attached parts 2 In order to decrease current consumption the FSK demodulator and the OSC3 oscillation circuit should be turned OFF when their operations are not necessary 3 When detecting a carrier the FSK demodulator may output invalid data at the rising edge of the CDET signal In this case the first byte received to the serial interface 2 may result in a parity error or a framing error As this byte is generally used as a leader code ignore the error in the processing Interrupt 1 The
46. temporarily stops the counting up of the high order data by carry from the low order data at the point where the low order data has been read and consequently the time during which the high order data is held is the shorter of the two indicated here following 1 Period until it reads the high order data 2 0 48 1 5 msec Varies due to the read timing Note Since the low order data is not held when the high order data has previously been read the low order data should be read first 51 63558 TECHNICAL MANUAL EPSON 57 CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Clock Timer 4 8 3 Interrupt function The clock timer can cause interrupts at the falling edge of 32 Hz 8 Hz 2 Hz and 1 Hz signals Software can set whether to mask any of these frequencies Figure 4 8 3 1 is the timing chart of the clock timer Address Bit Frequency Clock timer timing chart bze Haz RR D2 32Hz D3 16Hz DO 8 Hz D1 4 Hz FF7AH D2 2 Hz D3 1 Hz
47. the serial interface shifts to the receive enabled status and shifts to the receive disabled status when 0 is written Set RXEN RXENS to 0 when making the initial settings of the serial interface and similar operations At initial reset this register is set to 0 RXTRG Serial interface 1 receive trigger status FF72H D3 RXTRGS Serial interface 2 receive trigger status FF5AH D3 Functions as the receive start trigger or preparation for the following data receiving and the operation status indicator during receiving during stop When 1 is read During receiving When 0 is read During stop When 1 is written Start receiving following data receiving preparation When 0 is written Invalid RXTRG RXTRGS has a slightly different operation in the clock synchronous system and the asynchronous system The RXTRG RXTRGS in the clock synchronous system is used as the trigger for starting receive opera tion Write 1 into RXTRG RXTRGS to start receiving at the point where the receive data has been read and the following receive preparation has been done In the slave mode SRDY becomes 0 at the point where 1 has been written into into the RXTRG RXTRGS In the asynchronous system RXTRG RXTRGS is used for preparation of the following data receiving Read the received data located in the receive data buffer and write 1 into RXTRG RXTRGS to inform that the receive data buffer has shifted to empty When 1 has not been
48. use a separate instruction for switching the OSC3 oscillation OFF An error in the CPU operation can result if this processing is performed at the same time by the one instruction 4 3 5 Clock frequency and instruction execution time Table 4 3 5 1 shows the instruction execution time according to each frequency of the system clock Table 4 3 5 1 Clock frequency and instruction execution time Instruction execution time usec 1 cycle instruction 2 cycle instruction 3 cycle instruction OSC1 32 768 kHz 61 122 183 OSC3 3 58 MHz 0 56 1 12 1 68 Clock frequency 26 EPSON 1C63558 TECHNICAL MANUAL CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Oscillation Circuit 4 3 6 I O memory of oscillation circuit Table 4 3 6 1 shows the I O address and the control bits for the oscillation circuit Table 4 3 6 1 Control bits of oscillation circuit Address Register Comment D3 D2 D1 DO Init 1 1 0 CLKCHG 0 0563 05 1 CPU clock switch LKCH D FFOOH BERGHE ESO 0 OSCC 0 On Off OSC3 oscillation On Off 3 2 RW R RW 0 Unused Dummy 0 General purpose register Initial value at initial reset 2 Not set in the circuit 3 Constantly 0 when being read OSCC OSC3 oscillation control register FFOOH D2 Controls oscillation ON OFF for the OSC3 oscillation circuit When 1 is written OSC3 oscillation ON When 0 is written OSC3 oscillation O
49. 1 MHz 1C63558 TECHNICAL MANUAL EPSON 155 CHAPTER 5 SUMMARY NOTES Sound generator 1 Since the BZ and XBZ signals are generated asynchronous to the BZE register hazards may be pro duced when the signal goes ON OFF due to the setting of the BZE register 2 The one shot output is only valid when the normal buzzer output is OFF BZE 0 and will be invalid when the normal buzzer output is ON BZE 1 3 Since the BZ and XBZ signals are the special outputs of the RO1 and ROO ports it is necessary to set the high impedance control registers RO1HIZ ROOHIZ to 0 the data registers R01 ROO to 1 and the output selection registers BZOUT XBZOUT to 1 before setting the BZE register to 1 SVD circuit 1 To obtain a stable detection result the SVD circuit must be ON for at least 100 usec So to obtain the SVD detection result follow the programming sequence below 1 Set SVDON to 1 3 Set SVDON to 0 2 Maintain for 100 usec minimum 4 Read SVDDT 2 The SVD circuit should normally be turned OFF because SVD operation increase current consumption Telephone function 1 It is necessary to turn the OSC3 oscillation on prior to a dialing operation in tone mode because the tone mode uses the OSC3 3 58 MHZ clock However it increases current consumption Therefore turn the OSC3 oscillation off after finishing the dialling operation in tone mode 2 Do not write 0 0000B to the IDP FTS PTS or TCD
50. 10 Hz signals generated by the 25 256 sec and 26 256 sec inter vals in the ratio of 4 6 to generate a 1 Hz signal The count up intervals are 25 256 sec and 26 256 sec which do not amount to an accurate 1 10 sec 4 9 3 Interrupt function The stopwatch timers SWD0 SWD3 and SWD4 SWD7 through their respective overflows can generate 10 Hz approximate 10 Hz and 1 Hz interrupts Figure 4 9 3 1 shows the timing chart for the stopwatch timer Address Bit Stopwatch timer SWDO 3 timing chart DO FF7DH 2 1 100sec BCD D2 D3 10 Hz Interrupt request A A A Address Bit Stopwatch timer SWD4 7 timing chart DO m 1 10sec BCD D2 D3 1 Hz Interrupt request A A A Fig 4 9 3 1 Timing chart for stopwatch timer The stopwatch interrupts are generated by the overflow of their respective counters SWD0 SWDS and SWD4 SWD7 changing 9 to 0 At this time the corresponding interrupt factor flags ISW10 and ISW1 are set to 1 The respective interrupts can be masked separately using the interrupt mask registers EISW10 and EISW1 However regardless of the se
51. 16 0110H Stack pointer SP1 SP1 8 Undefined Stack pointer SP2 SP2 8 Undefined Zero flag 2 1 Undefined Carry flag 1 Undefined Interrupt flag I 1 0 Extension flag E 1 0 Queue register Q 16 Undefined 10 EPSON 51 63558 TECHNICAL MANUAL CHAPTER 2 POWER SUPPLY AND INITIAL RESET 2 2 4 Terminal settings at initial resetting The output port R terminals and I O port P terminals are shared with special output terminals and input output terminals of the serial interface These functions are selected by the software At initial reset these terminals are set to the general purpose output port terminals and I O port terminals Set them according to the system in the initial routine In addition take care of the initial status of output terminals when designing a system Table 2 2 4 1 shows the list of the shared terminal settings Table 2 2 4 1 a List of shared terminal settings Rxx Terminal Terminal status Special output name at initial reset FOUT TOUT BZ 2 XRMUTE XTMUTE ROO R00 HIGH output XBZ RO R01 HIGH output BZ RO2 R02 HIGH output TOUT R03 R03 HIGH output FOUT RIO R10 HIGH output XTMUTE R11 R11 HIGH output XRMUTE R12 R12 HIGH output HDO R13 HIGH output HFO R20 R23 R20 R23 HIGH output Table 2 2 4 1 b List of shared terminal settings Pxx Terminal Terminal status Special output Serial I F 2 nam
52. 2 Simultaneous low input to terminals 00 03 Another way of executing initial reset externally is to input a low signal simultaneously to the input ports 00 03 selected with the mask option Since this initial reset passes through the noise reject circuit maintain the specified input port terminals at low level for at least 1 5 msec when the oscillation frequency fOsci is 32 768 kHz during normal opera tion The noise reject circuit does not operate immediately after turning the power on until the oscillation circuit starts oscillating Therefore maintain the specified input port terminals at low level for at least 1 5 msec when the oscillation frequency fOsci is 32 768 kHz after oscillation starts Table 2 2 2 1 shows the combinations of input ports 00 03 that can be selected with the mask option Table 2 2 2 1 Combinations of input ports 1 Notuse 2 K00 K01 K02 K03 3 K00 K01 K02 4 K00 K01 When for instance mask option 2 K00 K01 K02 K03 is selected initial reset is executed when the signals input to the four ports 00 03 are all low at the same time When 3 or 4 is selected the initial reset is done when a key entry including a combination of selected input ports is made Further the time authorize circuit can be selected with the mask option The time authorize circuit checks the input time of the simultaneous low input and performs initial reset if that time is the defined time 1
53. 20 23 HIGH output R20 R23 R20 R23 R20 R23 20 23 R20 R23 20 23 R20 R23 R20 R23 When using the output port as the special output port the data register must be fixed at 1 and the high impedance control register must be fixd at 0 data output 4 5 2 Mask option Output specifications of the output ports can be selected with the mask option Either complementary output or N channel open drain output can be selected individually 1 bit units However when N channel open drain output is selected do not apply a voltage exceeding the power supply voltage to the output port 1C63558 TECHNICAL MANUAL EPSON 33 CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Output Ports 4 5 3 High impedance control The terminal output status of the output ports can be set to a high impedance status This control is done using the high impedance control register RxxHIZ corresponding to each output port Rxx When 1 is written to the high impedance control register the corresponding output port terminal goes into high impedance status When 0 is written the port outputs a signal according to the data register 4 5 4 Special output In addition to the regular DC output special output can be selected for the output ports R00 R03 and R10 R13 as shown in Table 4 5 4 1 with the software Figure 4 5 4 1 shows the configuration of the 00 03 and R10 R13 output ports Table 4 5 4 1 Speci
54. 4 10 4 1 Selection of prescaler division ratio PTPS11 PTPS10 PTPSO1 500 Prescaler division ratio 1 1 Source clock 256 1 0 Source clock 32 0 1 Source clock 4 0 0 Source clock 1 By writing 1 to the register PTRUNO timer 0 PTRUNI timer 1 the prescaler inputs the source clock and outputs the clock divided by the selected division ratio The counter starts counting down by inputting the clock 68 EPSON 51 63558 TECHNICAL MANUAL CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Programmable Timer 4 10 5 Interrupt function The programmable timer can generate an interrupt due to an underflow of the timer 0 and timer 1 See Figure 4 10 2 1 for the interrupt timing An underflow of timer 0 and timer 1 sets the corresponding interrupt factor flag IPTO timer 0 or IPT1 timer 1 to 1 and generates an interrupt The interrupt can also be masked by setting the correspond ing interrupt mask register EIPTO timer 0 or EIPT1 timer 1 However the interrupt factor flag is set to 1 by an underflow of the corresponding timer regardless of the interrupt mask register setting 4 10 6 Setting of TOUT output The programmable timer can generate a TOUT signal due to an underflow of timer 0 or timer 1 The TOUT signal is generated by dividing the underflows in 1 2 It is possible to select which timer s under flow is to be used by the TOUT output channel selection register CHSEL When 0 is written
55. 4 6 3 I O control registers and input output mode esee 42 4 6 4 Pull up during input mode er ey re t PE OR RSEN 42 4 6 5 Special Outputs CE rro terere et pe een 43 4 6 6 I O memory Of VO Poris esson osiva r eb cere Ries 44 4 6 7 Programming mOlesac aai an annon pede HE WE 48 LCD Driver COMO COM16 0 9 222202004000 49 4 7 1 Configuration of LCD driver 4 7 2 Mask option esse 4 7 3 Power supply for LCD driving 4 7 4 LCD display control ON OFF and switching of duty 49 4 7 3 Display memory aie FO o REFERS Fre o EEAS 4 7 6 LCD contrast adjustment 4 7 7 I O memory of LCD driver 4 7 0 EVO SPAMMING NOLES ctt mere e Ya re RP ESSE Clock Time kasise en E eie ieu eite ee 4 8 1 Configuration of clock timer esee 57 4 8 2 Data reading and hold function 57 4 8 3 Interrupt function e 4 8 4 I O memory of clock timer 458 9 dream prea Ayr nerd ME d E 61 4 9 1 Configuration of stopwatch timer esses eee 61 49D GOUNTUD Or Em 61 2 9 3 Interrupt JUNCUON eoe Rx te 62 4 9 4 memory of stopwatch timer 63 4 9 5 Programming NOLES ctiain GRE OI Pete E EE
56. 51 63558 TECHNICAL MANUAL 170 CHAPTER 9 PAD LAYOUT CHAPTER 9 PAD LAYOUT 9 1 Diagram of Pad Layout 30 25 20 15 10 5 1 Die 122 120 35 115 40 Y 110 45 0 0 5 3 105 50 100 55 95 60 65 70 75 80 85 90 y lt 4 01 Chip thickness 400 um Pad opening 100 1C63558 TECHNICAL MANUAL EPSON 171 CHAPTER 9 PAD LAYOUT 9 2 Pad Coordinates Unit um No Pad name X Y No Pad name X Y No Pad name X Y No Pad name X Y 1 R10 1767 2118 31 POO 1874 1834 62 SEG34 1767 2118 92 SEG4 874 1815 2 R03 1629 2118 32 K13 1874 1696 63
57. 60 0 Reading Valid The make ratio make break of the dialing pulses that are generated from the DP generator is set When 1 is written to the MB register 33 3 66 6 is set When 0 is written 40 0 60 0 is set The DP generator produces the dialing pulses as Make High period is before Break Low period This selection is valid only for pulse mode At initial reset this register is set to 0 DRS Dialing pulse rate selection FF10H DO Selects a dialing pulse rate for pulse mode When 1 is written 20 pps pulses per second When 0 is written 10 pps pulses per second Reading Valid The pulse rate number of pulses per second for the dialing pulses that are generated from the DP generator is set When 1 is written to the DRS register 20 pps is set When 0 is written 10 pps is set This selection is valid only for pulse mode At initial reset this register is set to 0 1C63558 TECHNICAL MANUAL EPSON 129 CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Telephone Function 50 53 Pause time selection FF11H Selects a pause time from among the 15 types shown in Table 4 14 10 2 Table 4 14 10 2 Selection of pause times D3 518 DO Pause time sec D3 2518 1150 Pause time sec Unavailable 1401010 8 01010 1 1 1101011 9 0101110 2 1101110 10 0111 3 1 0 1 1 11 0111010 4 1111010 12 0111011 5 111101 13 0111110 6 11111410 14 0 411 1 1 7
58. 63558 has a telephone function built in This function includes DTMF Dual Tone Multi Fre quency DP Dialing pulse Pause Flash Hold line Mute control Hook switch control and Handfree control The configuration of the telephone function is shown in Figure 4 14 1 1 3 58 MHz p Frequency DTME oscillator divider gt generator o HS QOH gt 3 a Control DP 4 gt w registers enerator Is 9 9 i I O XRMUTE R11 Interrupt t Mute circuit generator XTMUTE R10 Telephone 32 kHz gt Frequency timing R12 R13 O HFO R13 oscillator divider generator registers 4QO HDO R12 Fig 4 14 1 1 Configuration of tone pulse dialer This dialer has built in a DTMF generator for generating tones and a DP generator for generating dial pulses Either DTMF mode or DP mode can be selected by software In the DTMF mode the DTMF generator uses the OSC3 3 58 MHz clock to generate the tone signal set by software signal tone or dual tone and outputs it to the TONE terminal In the DP mode the DP generator uses the 5 1 32 kHz clock to generate the dial pulses for the number set by software to the DP terminal The push button matrix is config
59. At initial reset this register is set to 1000B 750 msec 1C63558 TECHNICAL MANUAL EPSON 131 CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Telephone Function SINR DTMF row frequencies output enable FF16H D1 Enables or disables the DTMF row frequency output When 1 is written Enabled When 0 is written Disabled Reading Valid This register is used to set the tone output mode with the SINC register Write 1 to this register when performing dual tone output or single tone ROW frequency output At initial reset this register is set to 1 SINC DTMF column frequencies output enable FF16H DO Enables or disables the DTMF column frequency output When 1 is written Enabled When 0 is written Disabled Reading Valid This register is used to set the tone output mode with the SINR register Write 1 to this register when performing dual tone output or single tone COL frequency output At initial reset this register is set to 1 Table 4 14 10 5 lists the tone output selection using the and SINC registers Table 4 14 10 5 Selection of tone output some Tone output 0 0 DC level 1 2 55 0 1 COL frequency 1 0 ROW frequency 1 1 Dual tone output Tables 4 14 10 6 a and b list the frequencies set by the TCD register FF17H when single tone output is selected Table 4 14 10 6 Single tone COL frequencies SINR 0 SINC 1 TCD code TCD code D2
60. C 32 kHz crystal oscillation LCD power ON 1 2 4 8 uA During execution LCD power ON 1 2 10 19 uA 32 kHz crystal oscillation During HALT LCD power ON 1 150 300 uA 3 58 MHz ceramic oscillation During execution LCD power ON 1 600 800 uA 3 58 MHz ceramic oscillation SVD circuit current during supply voltage detection 1 15 uA 2 2 to 5 5 V SVD circuit current during external voltage detection 0 5 6 uA 2 2 to 5 5 V DTMF circuit current 5 5 4 1 4 2 5 DTMF circuit current 3 0 4 1 2 2 0 mA FSK circuit current 5 5 4 1 8 2 5 mA FSK circuit current 3 0 V 4 1 0 1 5 mA Without panel load The SVD circuit is OFF 2 0 3 Please input the voltage which is within the range between Vss VDD into the SVD terminal 4 OSC3 oscillation current and CPU operating current with a 3 58 MHz clock are included 162 EPSON 51 63558 TECHNICAL MANUAL CHAPTER 7 ELECTRICAL CHARACTERISTICS 7 5 Oscillation Characteristics The oscillation characteristics change depending on the conditions components used board pattern etc Use the following characteristics as reference values OSC1 crystal oscillation circuit Unless otherwise specified 3 0 Vss 0V fosc1 32 768kHz CG 25pF Cp built in Ta 20 to 70 C Item Symbol Condition Min Typ Max Unit Oscillation start voltage Vsta _ tsta lt 3sec VDD 2 2 V Oscillation sto
61. Controls the handfree function and HFO signal output When 1 is written ON High level output on R13 terminal When 0 is written OFF Low level output on R13 terminal Reading Valid This register controls the HFO signal output to the R13 terminal when the HFO function has been se lected The output function is set by writing 1 to the CHFO register FF13He In this case the R13 register must be fixed at 1 and the R13HIZ register at 0 When 1 is written to the HF register the R13 terminal goes High VDD level When 0 is written the HFO R13 terminal goes Low Vss level At initial reset this register is set to 0 IDPO IDP3 Inter digit pause time selection FF15H Select an inter digit pause time for the pulse mode from among the 15 types shown in Table 4 14 10 4 Table 4 14 10 4 Selection of inter digit pause times IDP Inter digit pause IDP Inter digit pause D3 D2 D1 DO time msec 03 0201 00 time msec 0 01 010 Unavailable 110100 750 1 94 11010 1 844 0101110 188 110110 938 1 281 11011 1031 011100 375 1111010 1125 0 1 0141 469 1 1 041 1219 0 1 110 563 1111140 1313 Oo 1 1 1 656 1 1 1 l1 1406 Do not write 0 0000B to the IDP register because it may cause a malfunction The specified inter digit pause time will be inserted after each dialing pulse digit This selection is valid only for pulse mode
62. Disable 0 Enable Disable 2 High Low 7 ba 10 input port data 2 High Low 1 p ES 1 E K10 K13 input comparison register 1 d E 2 Unused Unused Unused Enable Mask Interrupt mask register K00 K03 Unused Unused Unused Enable Mask Interrupt mask register K10 K 13 R Unused Yes No Unused QW 4 Unused Reset Invalid Interrupt factor flag K00 K03 R Unused Yes No Unused Unused Reset Invalid Interrupt factor flag K10 K13 Initial value at initial reset 2 Not set in the circuit 3 Constantly 0 when being read K00 K03 KO port input port data FF21H K10 K13 K1 port input port data FF25H Input data of the input port terminals can be read with these registers When 1 is read High level When 0 is read Low level Writing Invalid The reading is 1 when the terminal voltage of the eight bits of the input ports 00 03 K10 K13 goes high VDD and 0 when the voltage goes low Vss These bits are dedicated for reading so writing cannot be done 30 EPSON 1C63558 TECHNICAL MANUAL CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Input Ports SIKOO SIKO3 KO port interrupt selection register FF20H SIK10 SIK13 K1 port interrupt selection register FF24H Selects the ports to be used for the K00 K03 and K10 K13 input interrupts When 1 is written Enable
63. EPSON 101 CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Sound Generator 4 12 4 Setting of buzzer frequency and sound level The divided signal of the OSC1 oscillation clock 32 768 kHz is used for the buzzer BZ XBZ signals and it is set up such that 8 types of frequencies can be selected by changing this division ratio Frequency selection is done by setting the buzzer frequency selection registers BZFO0 BZFQ2 as shown in Table 412 41 Table 4 12 4 1 Buzzer signal frequency setting BZFQ2 BZFQ1 BZFQO Buzzer frequency Hz 0 0 0 4096 0 0 0 1 3276 8 0 1 0 2730 7 0 1 1 2340 6 1 0 0 2048 0 1 0 1 1638 4 1 1 0 1365 3 1 1 1 1170 3 The buzzer sound level is changed by controlling the duty ratio of the buzzer signal The duty ratio can be selected from among the 8 types shown in Table 4 12 4 2 according to the setting of the buzzer duty selection registers BDTYO BDTY2 Table 4 12 4 2 Duty ratio setting Duty ratio by buzzer frequency Hz Level BDTY2 BDTY1 BDTYO 4096 0 3276 8 2730 7 2340 6 2048 0 1638 4 1365 3 1170 3 Level 1 Max 0 0 0 8 16 8 20 12 24 12 28 Level 2 0 0 1 7 16 7 20 11 24 11 28 Level 3 0 1 0 6 16 6 20 10 24 10 28 Level 4 0 1 1 5 16 5 20 9 24 9 28 Level 5 1 0 0 4 16 4 20 8 24 8 28 Level 6 1 0 1 3 16 3 20 7 24 7 28 Level 7 1 1 0 2 16 2 20 6 24 6 28 Level 8 Min 1 1 1 1 16 1 20 5 24 5 28 When the HIGH level output time has been made TH and when the LOW level
64. EPSON 51 63558 TECHNICAL MANUAL CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Sound Generator BDTYO BDTY2 Duty level selection register FF6FH D0 D2 Selects the duty ratio of the buzzer signal as shown in Table 4 12 7 3 Table 4 12 7 3 Duty ratio setting Duty ratio by buzzer frequency Hz Level BDTY2 BDTY1 BDTYO 4096 0 3276 8 2730 7 2340 6 2048 0 1638 4 1365 3 1170 3 Level 1 Max 0 0 0 8 16 8 20 12 24 12 28 Level 2 0 0 1 7 16 7 20 11 24 11 28 Level 3 0 1 0 6 16 6 20 10 24 10 28 Level 4 0 1 1 5 16 5 20 9 24 9 28 Level 5 1 0 0 4 16 4 20 8 24 8 28 Level 6 1 0 1 3 16 3 20 7 24 7 28 Level 7 1 1 0 2 16 2 20 6 24 6 28 Level 8 Min 1 1 1 1 16 1 20 5 24 5 28 The sound level of this buzzer can be set by selecting this duty ratio However when the envelope has been set to ON ENON 1 this setting becomes invalid At initial reset this register is set to 0 ENRST Envelope reset FF6CH D2 Resets the envelope When 1 is written Reset When 0 is written No operation Reading Always 0 Writing 1 into ENRST resets envelope and the duty ratio becomes maximum If an envelope has not been added ENON 0 and if no buzzer signal is being output the reset becomes invalid Writing 0 is also invalid This bit is dedicated for writing and is always 0 for reading ENON Envelope ON OFF control register FF6CH D1 Controls the addition of an envelope onto the buzzer signal W
65. HDO signal output is possible by software R13 61 O Output port switching to signal output is possible by software R20 R23 60 57 Output port COMO0 COM7 45 38 O LCD common output pin 1 8 1 16 1 17 can be selected by software 8 16 115 123 LCD common output pin 5 47 5 40 or LCD segment output pin mask option SEGO SEG39 37 33 31 2 128 124 LCD segment output pin SVD 107 I SVD external voltage input pin DP 56 O j Dial pulse output pin TONE 55 O DTMF output pin RESET 53 I Initial reset input pin TEST 54 I Testing input pin AVDD 80 Power supply pin for FSK demodulator AVss 76 Power supply for FSK demodulator RDIN 74 I Ring detection input pin TIP 79 78 RING input pin FB 77 amplifier output pin BPOUT 72 O Band pass filter output pin CDIN 71 Carrier detection input pin RDRC 73 IO pin for connecting RC network VREF 75 O Reference voltage output pin 1 2 VDD EPSON 51 63558 TECHNICAL MANUAL CHAPTER 1 OUTLINE 1 5 Mask Option Mask options shown below are provided for the 51 63558 Several hardware specifications are prepared in each mask option and one of them can be selected according to the application The function option generator FOG63558 that has been prepared as the development software tool of S1C63558 is used for this selection Mask pattern of the IC is finally generated based on the data
66. Interface Clock synchronous master mode In this mode the internal clock is utilized as a synchronous clock for the built in shift registers and 8 bit clock synchronous serial transfers can be performed with this serial interface as the master The synchronous clock is also output from the SCLK terminal which enables control of the external slave side serial I O device Since the SRDY terminal is not utilized in this mode it can be used as an I O port Figure 4 11 3 1 a shows the connection example of input output terminals in the clock synchronous master mode Clock synchronous slave mode In this mode a synchronous clock from the external master side serial input output device is utilized and 8 bit clock synchronous serial transfers can be performed with this serial interface as the slave The synchronous clock is input to the SCLK terminal and is utilized by this interface as the synchro nous clock Furthermore the SRDY signal indicating the transmit receive ready status is output from the SRDY terminal in accordance with the serial interface operating status In the slave mode the settings for registers SCSO and SCS1 used to select the clock source are invalid Figure 4 11 3 1 b shows the connection example of input output terminals in the clock synchronous slave mode 7 bit asynchronous mode In this mode 7 bit asynchronous transfer can be performed Parity check during data reception and addition of parity bit odd even none
67. Interrupt factor flags FFF7H D1 DO Refer to Section 4 9 Stopwatch Timer 4 16 5 Programming notes 1 The interrupt factor flags are set when the interrupt condition is established even if the interrupt mask registers are set to 0 2 After an interrupt occurs the same interrupt will occur again if the interrupt enabled state I flag 1 is set or the RETI instruction is executed unless the interrupt factor flag is reset Therefore be sure to reset write 1 to the interrupt factor flag in the interrupt service routine before shifting to the interrupt enabled state 3 After an initial reset all the interrupts including NMI are masked until both the stack pointers SP1 and SP2 set with the software Be sure to set the SP1 and SP2 in the initialize routine Further when re setting the stack pointer the SP1 and SP2 must be set as a pair When one of them is set all the interrupts including NMI are masked and interrupts cannot be accepted until the other one is set 1C63558 TECHNICAL MANUAL EPSON 151 CHAPTER 5 SUMMARY NOTES CHAPTER 5 SUMMARY OF NOTES 5 1 Notes for Low Current Consumption The 51 63558 contains control registers for each of the circuits so that current consumption can be reduced These control registers reduce the current consumption through programs that operate the circuits at the minimum levels The following lists the circuits that can control operation and their control registe
68. Interrupt mask register Stopwatch timer 1 Hz EISW10 0 Enable Mask Interrupt mask register Stopwatch timer 10 Hz 0 3 2 Unused 0 EISERS EISTRS EISRCS FFE8H EISERS 0 Enable Mask Interrupt mask register Serial I F 2 error R BN EISTRS 0 Enable Mask Interrupt mask register Serial I F 2 transmit completion EISRCS 0 Enable Mask Interrupt mask register Serial I F 2 receive completion 0 3 2 Unused 0 0 o ED ne FFE9H 7 nol R RW 0 3 2 Unused EID 0 Enable Mask Interrupt mask register Dialer 0 3 2 Unused 0 0 EIRDET EICDET 2402 Mig FFEAH z eH R RW EIRDET 0 Enable Mask Interrupt mask register FSK demodulator ring detection EICDET 0 Enable Mask Interrupt mask register FSK demodulator carrier detection 3 P 0 o ito 0 FFFoH 0 3 2 Yes No R RW 0 W Interrupt factor flag Programmable timer 1 IPTO 0 Reset Invalid Interrupt factor flag Programmable timer 0 0 3 2 R R Unused 0 ISER ISTR ISRC FFF3H ISER 0 Yes No Interrupt factor flag Serial I F 1 error R RW ISTR 0 W Interrupt factor flag Serial I F 1 transmit completion ISRC 0 Reset Invalid Interrupt factor flag Serial I F 1 receive completion 9 2 0 0 0 1 i z 2 FFF4H D EA 288 1 20 _ nuse R BIN 0 3 2 W W Unused 0 0 Reset Invalid Interrupt factor flag 00 03 3 a 0 0 0 0
69. J Selector gt 1 16 Selector gt 1 186 nous clock circuit Atos ble timer 1 rogrammable timer 1 12 underflow signal Clock synchronous slave mode SCLK Fig 4 11 4 1 Division of the synchronous clock Table 4 11 4 2 shows an examples of transfer rates and OSC3 oscillation frequencies when the clock source is set to programmable timer Table 4 11 4 2 oscillation frequencies and transfer rates Transfer rate fosc3 3 580 MHz bps PSC1X RLD1X 9 600 0 1 1 OCH 4 800 0 1 1 17H 2 400 0 1 1 2FH 1 200 0 1 1 5DH 600 0 1 1 BAH 300 1 1 4 5DH 150 1 1 4 BAH When the demultiplied signal of the OSC3 oscillation circuit is made the clock source it is necessary to turn the OSC3 oscillation ON prior to using the serial interface A time interval of several msec to several 10 msec from the turning ON of the OSC3 oscillation circuit to until the oscillation stabilizes is necessary due to the oscillation element that is used Consequently you should allow an adequate waiting time after turning ON of the OSC3 oscillation before starting transmit ting receiving of serial interface The oscillation start time will vary somewhat depending on the oscillator and on the externally attached parts Refer to the oscillation start time example indicated in Chapter 7 Electrical Characteristics At initial reset the OSC3 oscillation circuit is set to OFF status 80 EPS
70. Low level input voltage 3 RESET TEST 0 0 1 V Low level input voltage 4 RDIN RDRC 0 0 25 V High level input current Vin 3 0V K00 03 K10 13 RDIN RDRC 0 0 5 00 03 10 13 20 23 30 33 RESET TEST SVD Low level input current 1 VILI Vss K00 03 K10 13 RDIN RDRC 0 5 0 uA No Pull up 00 03 10 13 20 23 P30 33 RESET TEST SVD Low level input current 2 2 VIL2 Vss K00 03 10 13 16 10 6 uA With Pull up P00 03 10 13 20 23 30 33 RESET TEST High level output current 0 9 R00 03 10 13 20 23 1 00 03 10 13 20 23 30 33 Low level output current 0 1 R00 03 10 13 20 23 RDRC 3 00 03 10 13 20 23 30 33 Common output current Tou2 2 5 0 05 COMO 16 25 uA 1 12 VOL2 Vss 0 05V 25 uA Segment output current VoH3 VC5 0 05V SEGO 39 10 HA IOL3 VoL3 Vss 0 05V 10 Unless otherwise specified 5 0 Vss 0V fosc1 32 768kHz Ta 20 to 70 C Vp1 Vci Vc23 VC4 VCs are internal voltage C1 C7 0 2UF Item Symbol Condition Min Typ Max Unit High level input voltage 1 K00 03 10 13 0 8 VDD VDD V 00 03 P10 13 P20 23 30 33 High level input voltage 2 2 RESET TEST 0 9 Vpp V High level input voltage 3 RDIN RDRC 0 75
71. Ports Serial interface 1 enable register FF70H DO Selects function for P10 P13 When 1 is written Serial interface 1 input output port When 0 is written I O port Reading Valid When using the serial interface 1 write 1 to this register and when 10 13 are used as the I O port write 0 The terminal configuration within P10 P13 that are used for the serial interface 1 is decided by the transfer mode 7 bit asynchronous 8 bit asynchronous clock synclonous slave clock synchronous master selected with the SMD1 and SMD0 registers In the clock synchronous slave mode all the 10 13 ports are set to the serial interface 1 input output port In the clock synchronous master mode 10 12 are set to the serial interface 1 input output port and P13 can be used as the I O port In the 8 7 bit asynchronous mode P10 and P11 are set to the serial interface 1 input output port and P12 and P13 can be used as the I O port At initial reset this register is set to 0 ESIFS Serial interface 2 enable register FF58H DO Selects function for P30 P33 When 1 is written Serial interface 2 input output port When 0 is written I O port Reading Valid When using the serial interface 2 write 1 to this register and when P30 P33 are used as the I O port write 0 The terminal configuration within P30 P33 that are used for the serial interface 2 is decided by the transfer mode 7 bit asynchron
72. R10 R11 R12 and R13 correspond to the XTMUTE XRMUTE HDO and HFO outputs respectively At initial reset these registers are all set to 1 CTMO R10 output selection register FF13H DO Selects the R10 terminal function When 1 is written XTMUTE output When 0 is written General purpose DC output Reading Valid When using the R10 terminal for the XTMUTE output write 1 to this register Furthermore fix the R10 register at 1 and the R10HIZ register at 0 The XTMUTE output is controlled by the CTMUT register 18 D0 At initial reset this register is set to 0 CRMO R11 output selection register FF13H D1 Selects the R11 terminal function When 1 is written XRMUTE output When 0 is written General purpose DC output Reading Valid When using the R11 terminal for the XRMUTE output write 1 to this register Furthermore fix the R11 register at 1 and the R11HIZ register at 0 The XRMUTE output is controlled by the CRMUT register FF18He D1 At initial reset this register is set to 0 CHDO R12 output selection register FF13H D2 Selects the R12 terminal function When 1 is written HDO output When 0 is written General purpose DC output Reading Valid When using the R12 terminal for the HDO output write 1 to this register Furthermore fix the R12 register at 1 and the R12HIZ register at 0 The HDO output is controlled by the HOLD register FFI4H 02 At initial reset th
73. RLD13 RLD12 RLD11 RLD10 BLD12 0 FFC6H RLD11 0 Programmable timer reload data low order 4 bits bl RLDIO 0 LSB RLD17 0 71 MSB RLD17 RLD16 RLD15 RLD14 RLD16 0 FFC7H RLD15 0 Programmable timer reload data high order 4 bits ic RLD14 0 LSB PTD03 0 71 MSB PTDO3 PTDO2 PTDO1 PTDOO PTDO2 0 FFC8H aa Programmable timer 0 data low order 4 bits PTDO1 0 n 000 0 LSB PTDO7 0 71 MSB PTDO7 PTDO6 PTD05 PTD04 PTD06 0 PTDOS 0 Programmable timer 0 data high order 4 bits 004 0 LSB PTD13 0 71 MSB PTD13 PTD12 PTD11 PTD10 PTD12 0 FFCAH PTD11 0 Programmable timer 1 data low order 4 bits PTD10 0 LSB PTD17 0 71 MSB PTD17 PTD16 PTD15 PTD14 PTD16 0 FFCBH PTD15 0 Programmable timer 1 data high order 4 bits n 014 0 LSB 0 3 2 Unused 0 0 0 3 2 Unused FFE2H i i 0 Enable Mask Interrupt mask register Programmable timer 1 amp PTO 0 Enable Mask Interrupt mask register Programmable timer 0 0 3 32 R Unused 0 0 3 2 Yes No Unused 0 i w B w Interrupt factor fla Programmable timer 1 g Prog R PTO 0 Reset Invalid Interrupt factor flag Programmable timer 0 Initial value at initial reset 2 Not set in the circuit 3 Constantly 0 when being read 51 63558 TECHNICAL MANUAL EPSON 71 CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Programmable Timer CKSELO Prescaler 0 source clock selection register
74. TPS FF10H D3 Write to TCD FF17H Write to FLASH FF14HeDO DP 1 4 tip TONE XRMUTE R11 tun XTMUTE R10 Interrupt request Flash time trie Flash pause time tior Inter digit pause time Mute hold time Fig 4 14 7 1 Flash execution timing chart 124 EPSON 51 63558 TECHNICAL MANUAL CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Telephone Function FLASH is a write only bit and is used as the trigger for a flash operation When the FLASH bit is set to 1 the DP terminal goes Low level until the flash time set by the FTS register has passed then the DP terminal returns to High level After that 938 msec of the flash pause time is taken and an interrupt occurs At the same time the FLASH bit is automatically cleared to 0 by the interrupt Thus the flash function requires start control only The flash function uses the same interrupt system as the dialing completion Therefore the interrupt factor flag ID must be reset before executing the flash function 4 14 8 Hold line The hold line function can assert the XTMUTE signal while holding the current communication line open This function can be controlled using the HOLD register When 1 is written to the HOLD register the communication line is held open and the XTMUTE signal goes Low level When 0 is wr
75. XTMUTE R12 1 High Low R12 output port data CHDO 0 Fix at 1 when HDO is used RW R11 1 High Low R11 output port data CRMO 0 Fix at 1 when XRMUTE is used R10 1 High Low R10 output port data 0 Fix at 1 when XTMUTE is used 3 2 Unused 0 0 ED FFE9H x ok R RW 0 3 2 Unused EID 0 Enable Mask Interrupt mask register Dialer B ES 0 3 2 R Unused 3 2 FFF9H 0 2 Yes No Unused R RW 0 3 2 W W Unused ID 0 Reset Invalid Interrupt factor flag Dialer 1 Initial value at initial reset 2 Not set in the circuit 3 Constantly 0 when being read 51 63558 TECHNICAL MANUAL EPSON 127 CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Telephone Function R10HIZ R13HIZ R1 port high impedance control register FF32H Controls high impedance output of the output port When 1 is written High impedance When 0 is written Data output Reading Valid When using the XTMUTE XRMUTE and outputs fix these registers at 0 RIOHIZ R11 HIZ R12HIZ and R13HIZ correspond to the XTMUTE XRMUTE HDO and HFO outputs respectively At initial reset these registers are set to 0 R10 R13 R1 output port data register FF33H Set the output data for the output ports When 1 is written High level output When 0 is written Low level output Reading Valid When using the XTMUTE XRMUTE HDO and HFO outputs fix these registers at 1
76. and operation for initialization and transmitting receiving in case of asynchronous data transfer See 4 11 8 Interrupt function for the serial interface interrupts Initialization of serial interface The below initialization must be done in cases of asynchronous system transfer 1 Setting of transmitting receiving disable To set the serial interface into a status in which both transmitting and receiving are disabled 0 must be written to both the transmit enable register TXEN and the receive enable register RXEN Fix these two registers to a disable status until data transfer actually begins 2 Port selection Because serial interface input output terminals SIN and SOUT are set as I O port terminals P10 and P11 at initial reset 1 must be written to the serial interface enable register ESIF in order to set these terminals for serial interface use SCLK and SRDY terminals set in the clock synchronous mode are not used in the asynchronous mode These terminals function as I O port terminals P12 and P13 3 Setting of transfer mode Select the asynchronous mode by writing the data as indicated below to the two bits of the mode selection registers SMD0 and SMD1 7 bit mode SMDO0 0 SMDI 1 8 bit mode SMD0 1 SMD1 1 86 EPSON 1C63558 TECHNICAL MANUAL CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Serial Interface 4 Parity bit selection When checking and adding parity bits write 1 into the parity ena
77. be 1 and the high impedance control register RO2HIZ must always be 0 data output state At initial reset this register is set to 0 74 EPSON 1C63558 TECHNICAL MANUAL CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Programmable Timer EIPTO Timer 0 interrupt mask register FFE2H DO EIPT1 Timer 1 interrupt mask register FFE2H D1 These registers are used to select whether to mask the programmable timer interrupt or not When 1 is written Enabled When 0 is written Masked Reading Valid Timer 0 and timer 1 interrupts can be masked individually by the interrupt mask registers EIPTO timer 0 and timer 1 At initial reset these registers are set to 0 IPTO Timer 0 interrupt factor flag FFF2H DO IPT1 Timer 1 interrupt factor flag FFF2H D1 These flags indicate the status of the programmable timer interrupt When 1 is read Interrupt has occurred When 0 is read Interrupt has not occurred When 1 is written Flag is reset When 0 is written Invalid The interrupt factor flags IPTO and correspond to timer 0 and timer 1 interrupts respectively The software can judge from these flags whether there is a programmable timer interrupt However even if the interrupt is masked the flags are set to 1 by the underflows of the corresponding counters These flags are reset to 0 by writing 1 to them After an interrupt occurs the same interrupt will occur again if the interrupt enable
78. carrier detection and interrupt eese 4 15 4 Inputting FSK d l cric etr i n Sr RO reine RE sex 4 15 5 I O memory of FSK demodulator 4 15 6 Programming notes 4 10 Interrupt and HALT e coto eire er decies AAG Interrupt JACOT cotto et aep d orae NS 4 10 2 a EH Es 4 10 3 InterFupt VeClO ete 4 16 4 I O memory of interrupt es 4 16 Prora mMM NOTES eoa TE E ava HERO OUR O CHAPTER 5 SumMARY OF NOTES 152 5 1 Notes for Low Current 7 152 5 2 Summary of Notes by 0 153 2 9 157 CHAPTER 6 Basic EXTERNAL WIRING DIAGRAM 159 CHAPTER 7 ELECTRICAL CHARACTERISTICS 160 7 1 Absolute Maximum Rating 7 2 Recommended Operating Conditions 160 7535 CHAVGCLETISIICS esee ise teo 161 7 4 Analog Circuit Characteristics and Power Current Consumption 162 729 Oscdillatnomn Characteristic eter aereo Reo 163 7 6 Serial Interface 1 2 AC Characteristics ecce 164 7 7 FSK Demodulator Characteristics cie tnter ete terere dern n 165 1C63558 TECHNICAL MANUAL EPSON iii 5 7 8 Telephone Function Characteristics esee 16
79. data buffer can be read out Since the sift register is provided separately from this buffer reading can be done during a receive opera tion in the asynchronous mode The buffer function is not used in the clock synchronous mode Read the data after waiting for a receive completion interrupt When performing parity check in the 7 bit asynchronous mode 0 is loaded into the 8th bit TRXD7 TRXD7S that corresponds to the parity bit The serial data input from the SIN terminal is level converted making the High VDD level bit 1 and the Low Vss level bit 0 and is then loaded into this buffer At initial reset the buffer content is undefined OER Serial interface 1 overrun error flag FF73H DO OERS Serial interface 2 overrun error flag FF5BH DO Indicates the generation of an overrun error When 1 is read Error When 0 is read No error When 1 is written Reset to 0 When 0 is written Invalid OER OERS is an error flag that indicates the generation of an overrun error and becomes 1 when an error has been generated An overrun error is generated when a receiving of data has completed prior to writing 1 to RXTRG RXTRGS in the asynchronous mode OER OERS is reset to 0 by writing 1 OER OERS is set to 0 at initial reset or when RXEN RXENS is set to 0 PER Serial interface 1 parity error flag FF73H D1 PERS Serial interface 2 parity error flag FF5BH D1 Indicates the generation of a parit
80. dividers are provided for the row group and column group The actual generated frequen cies are listed in Table 4 14 4 2 They may include an error within tolerance due to the dividing method Table 4 14 4 2 Standard vs actual frequency Tone output frequency Hz ROW COL Standard ancy Error ROWI 697 701 32 0 62 ROW2 770 711 45 0 19 ROW3 852 857 17 0 61 ROW4 941 935 10 0 63 COLI 1209 1215 88 0 57 COL2 1336 1331 68 0 32 COL3 1477 1471 85 0 35 COL4 1633 1645 01 0 74 Errors do not include oscillator drift 116 EPSON 51 63558 TECHNICAL MANUAL CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Telephone Function The row group and column group dividers can be operated individually The software can select one of them to output a single tone signal as well as a dual tone signal output Use the SINR FF16HeD1 and SINC 16 registers for this control Table 4 14 4 3 Tone output selection bide Tone output 0 0 DC level 1 2 55 0 1 COL frequency 1 0 ROW frequency 1 1 Dual tone output At initial reset dual tone output is set The divided frequencies are converted into a tone signal through the sine wave ROM and the D A converter then the tone signal is output from the TONE terminal The items to set before outputting a tone signal may be summarized as follows 1 Setting tone mode It is not
81. during transmitting can be specified and data processed in 7 bits with or without parity Since this mode employs the internal clock the SCLK terminal is not used Furthermore since the SRDY terminal is not utilized either both of these terminals can be used as I O ports Figure 4 11 3 1 c shows the connection example of input output terminals in the asynchronous mode 8 bit asynchronous 8 bit mode In this mode 8 bit asynchronous transfer can be performed Parity check during data reception and addition of parity bit odd even none during transmitting can be specified and data processed in 8 bits with or without parity Since this mode employs the internal clock the SCLK terminal is not used Furthermore since the SRDY terminal is not utilized either both of these terminals can be used as I O ports Figure 4 11 3 1 c shows the connection example of input output terminals in the asynchronous mode S1C63558 External 51 63558 External serial device serial device SIN P10 Data input SIN P10 Data input SOUT P11 Data output SOUT P11 Data output SCLK P12 _ CLOCK input SCLK P12 4 4 CLOCK output Input port Kxx 4 34 READY output SRDY P13 1 0 READY input a Clock synchronous master mode b Clock synchronous slave mode S1C63558 Exte
82. example for Bellcore 4 15 4 Inputting FSK data The FSK demodulator starts operating when 1 is written to FSKON FF66He 03 Normally it should be set to 0 to decrease current consumption if not necessary The following settings are necessary before starting the FSK demodulator operation 1 Setting the serial interface 2 The demodulated data is loaded to the data register of the serial interface 2 Therefore transfer conditions transfer rate bit width parity condition must be set before receiving FSK data When the FSK demodulator is turned ON FSKON 1 the input line of the serial interface 2 is switched from P30 to the FSK demodulator output The I O terminals P30 P33 including P30 used for the serial interface 2 functions as the general I O port terminals while FSKON is 1 Refer to Section 4 11 Serial Interface for controlling the serial interface 2 2 Controlling the OSC3 oscillation circuit The FSK demodulator uses the OSC3 clock as the operating clock Therefore the OSC oscillation circuit must be turned ON and the CPU operating clock must be switched to OSC3 It takes a maximum 5 msec for oscillation stabilization after turning the OSC3 oscillation circuit ON Do not turn the FSK demodulator ON in this period Refer to Section 4 3 Oscillation Circuit for controlling the OSC3 oscillation circuit 140 EPSON 51 63558 TECHNICAL MANUAL CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION FSK Demodulato
83. interface 2 parity enable register FF59H D3 Selects the parity function When 1 is written With parity When 0 is written Non parity Reading Valid Selects whether or not to check parity of the received data and to add a parity bit to the transmitting data When 1 is written to EPR EPRS the most significant bit of the received data is considered to be the parity bit and a parity check is executed A parity bit is added to the transmitting data When 0 is written neither checking is done nor is a parity bit added Parity is valid only in asynchronous mode and the EPR EPRS setting becomes invalid in the clock synchronous mode At initial reset this register is set to 0 PMD Serial interface 1 parity mode selection register FF71H D2 PMDS Serial interface 2 parity mode selection register FF59H D2 Selects odd parity even parity When 1 is written Odd parity When 0 is written Even parity Reading Valid When 1 is written to PMD PMDS odd parity is selected and even parity is selected when 0 is written The parity check and addition of a parity bit is only valid when 1 has been written to EPR EPRS When 0 has been written to EPR EPRS the parity setting by PMD PMDS becomes invalid At initial reset this register is set to 0 TXEN Serial interface 1 transmit enable register FF72H DO TXENS Serial interface 2 transmit enable register FF5AH DO Sets the serial interface to the transmit enabled
84. interrupt factor flags are set when the interrupt condition is established even if the interrupt mask registers are set to 0 2 After an interrupt occurs the same interrupt will occur again if the interrupt enabled state I flag 1 is set or the RETI instruction is executed unless the interrupt factor flag is reset Therefore be sure to reset write 1 to the interrupt factor flag in the interrupt service routine before shifting to the interrupt enabled state 3 After an initial reset all the interrupts including NMI are masked until both the stack pointers SP1 and SP2 are set with the software Be sure to set the SP1 and SP2 in the initialize routine Further when re setting the stack pointer the SP1 and SP2 must be set as a pair When one of them is set all the interrupts including NMI are masked and interrupts cannot be accepted until the other one is set 156 EPSON 1C63558 TECHNICAL AMANUAL CHAPTER 5 SUMMARY NOTES 5 3 Precautions on Mounting lt Oscillation Circuit gt Oscillation characteristics change depending on conditions board pattern components used etc In particular when a ceramic oscillator or crystal oscillator is used use the oscillator manufacturer s recommended values for constants such as capacitance and resistance Disturbances of the oscillation clock due to noise may cause a malfunction Consider the following points to prevent this 1 Components which are connected to th
85. interrupt will be masked However even in this case the interrupt factor flag is set to 1 when the interrupt condition is met Figure 4 15 3 1 shows the relationship between the detection bit and the comparison register Comparison register RDETCP CDETCP 0 0 With the above setting the ring detection carrier detection interrupt is generated under the following conditions RDET CDET bit 1 RDET CDET 0 0 Initial value 2 RDET CDET 1 0 Ring detection interrupt generation The interrupt is generated when the contents of RDET are unmatched with the comparison register RDETCP By copying the RDET bit to the RDETCP register the ring detection interrupt changes its generation timing to the falling edge RDETCP CDETCP 1 0 3 RDET CDET 0 0 gt Ring detection interrupt generation The interrupt is generated at the falling edge Reset RDETCP and CDETCP in the initial status RDETCP CDETCP 0 0 4 RDET CDET 0 1 Carrier interrupt generation The interrupt is generated when the contents of CDET are unmatched with the comparison register CDETCP By copying the CDET bit to the CDETCP register the carrier detection interrupt changes its generation timing to the falling edge RDETCP CDETCP 0 1 5 RDET CDET 0 0 Carrier detection interrupt gen
86. kQ 2 The K13 terminal functions as the clock input terminal for the programmable timer and the input signal is shared with the input port and the programmable timer Therefore when the K13 terminal is set to the clock input terminal for the programmable timer take care of the interrupt setting 51 63558 TECHNICAL MANUAL EPSON 153 CHAPTER 5 SUMMARY NOTES Output port 1 When using an output port 00 03 R10 R13 for special output fix the corresponding data register 00 03 R10 R13 at 1 and the high impedance control register ROOHIZ ROS3HIZ R10HIZ R13HIZ at 0 data output Be aware that the output terminal is fixed at a low Vss level the same as the DC output if 0 is written to the data registers when the special output has been selected Be aware that the output terminal shifts into high impedance status when 1 is written to the high impedance control register 2 A hazard may occur when the TOUT FOUT BZ or XBZ signal is turned ON and OFF 3 When foscs is selected for the FOUT signal frequency it is necessary to control the OSC3 oscillation circuit before output Refer to Section 4 3 Oscillation Circuit for the control and notes port 1 When in the input mode I O ports are changed from low to high by pull up resistor the rise of the waveform is delayed on account of the time constant of the pull up resistor and input gate capaci tance Hence when fetching input ports set an ap
87. necessary if the mode has not be changed after an initial reset 2 Selecting a tone output method single tone dual tone SINR and SINC are used 3 Turning the OSC3 oscillation circuit ON OSCC 1 Note Note The OSC3 oscillation needs at least 5 msec until it is stabilized after the OSC3 oscillation circuit is turned ON Therefore dialing operations must be started after taking an interval of at least 5 msec from activation of the OSC3 oscillation circuit Since the oscillation stabilization time varies de pending on the external oscillator s characteristic and operating conditions allow ample margin for the interval Further the OSC3 oscillation circuit increases current consumption so it should be turned OFF when the DTMF generator is not used or the CPU does not need high speed processing The following explains how to output the tone signal and the circuit operation First write 1 to the HSON register FF18H D3 so the dialer is in off hook status As a result the DP terminal goes High Vpp level Next write the ROW COL data of the pushbutton to be transmitted to the TCD3 TCD0 register FF17H Table 4 14 4 4 shows the relationship of write data and tone frequencies Table 4 14 4 4 Tone frequency selection Tone frequency TCD gode Tone frequency Key D3 D2 D1 DO symbol D3 D2 D1 DO symbol 01010 0 1 0 0 0 ROW3 COL2 8 010 0 1 RO
88. of output specifications are available complementary output and N channel open drain output Figure 4 5 1 1 shows the configuration of the output port Address High impedance 4 5 ib control register EE ed 2 Mask option 4 5 Data register H Rxx Address V 4 Vss Fig 4 5 1 1 Configuration of output port The R00 to R03 output terminals are shared with the buzer clock outputs XBZ BZ TOUT FOUT The R10 to R13 output terminals are shared with the tone pulse dialer outputs XTMUTE XRMUTE HDO HFO These functions are selected by the software At initial reset these are all set to the general purpose output port Table 4 5 1 1 shows the setting of the output terminals by function selection Table 4 5 1 1 Function setting of output terminals Terminal Terminal status Special output name at initial reset FOUT TOUT BZ XBZ HFO HDO _ XRMUTE XTMUTE ROO ROO HIGH output ROO ROO ROO XBZ ROO ROO ROO ROO R01 R01 HIGH output R01 ROI BZ R01 ROI R01 ROL ROL R02 R02 HIGH output R02 TOUT R02 R02 R02 R02 R02 R02 R03 R03 HIGH output FOUT R03 R03 R03 R03 R03 R03 R03 R10 R10 HIGH output R10 R10 R10 R10 R10 R10 R10 XTMUTE R11 R11 HIGH output R11 R11 R11 R11 R11 R11 XRMUTE R11 R12 R12 HIGH output R12 R12 R12 R12 R12 HDO R12 R12 R13 R13 HIGH output R13 R13 R13 R13 HFO R13 R13 R13 R20 R23
89. output sass 101 4 12 4 Setting of buzzer frequency and sound level sess 102 4 12 5 Digital envelope iso eise e tee xa teen er eias 103 4 12 6 One shot output m 4 12 7 I O memory of sound generator eese 105 4 12 5 Programming NOLES vea ecciesie ee RH eee poss YET 108 4 13 SVD Supply Voltage Detection Circuit 109 4 13 1 Configuration of SVD circuit un 109 4 13 2 Mask option m 4 13 3 SVD operation wes LOD 4 13 4 1 O memory Of SVD Circuit sairaan ated 110 4 13 5 PYOSTAMIMING NOLES eiie HPOO 111 4 14 Telephone Function Tone Pulse Dialer 222 0000000 00000 eerte 112 4 14 1 Configuration of tone pulse dialer 4 14 2 Mask option sss 4 14 3 Operation of telephone function 4 14 4 Tone mode DTMF rinena saneceeibietiatecw eoe 414 5 Pulse mode DP soisi aeia o eO A OX E EY Ee ME AEE 4 14 6 Pause 0500 4 14 7 Flash 4 14 6 Hold line nae 4 14 9 Interrupt EC 4 14 10 I O memory of telephone function eese 4 I IIProeramming notes erroe d tr be it XP FAD FSK Demodulator eoe 4 15 1 Configuration of FSK demodulator 4 15 2 Mask option essent 4 15 3 Ring
90. output time has been made TL due to the ratio of the pulse width to the pulse synchronization the duty ratio becomes TL TH TL for negative polarity or TH TH TL for positive polarity When BDTY0 BDTY2 have all been set to 0 the duty ratio becomes maximum and the sound level also becomes maximum Conversely when BDTY0 BDTY2 have all been set to 1 the duty ratio becomes minimum and the sound level also becomes minimum The duty ratio that can be set is different depending on the frequency that has been set so see Table 4 12 4 2 TH TL _ TL TH Level 1 Max Level 1 Max Level 2 Level 2 Level 3 1 Level 3 Level 4 Level 4 Level 5 Level 5 Level 6 1 Level 6 Level 7 Level 7 Level 8 Min Level 8 Min a Negative polarity b Positive polarity Fig 4 12 4 1 Duty ratio of the buzzer signal waveform Note When a digital envelope has been added to the buzzer signal the BDTYO BDTYO settings will be invalid due to the control of the duty ratio 102 EPSON 1C63558 TECHNICAL MANUAL CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Sound Generator 4 12 5 Digital envelope A digital envelope for duty control can be added to the buzzer sig
91. register when CL output is selected RW 21 0 Output Input P21 I O control register OC 20 0 Output Input P20 I O control register PUL23 1 On Off P23 pull up control register EXLCDC 0 General purpose register when FR output is selected FF49H PUL22 1 On Off P22 pull up control register EXLCDC 0 General purpose register when CL output is selected RW PUL21 1 On Off P21 pull up control register PUL20 1 On Off _ P20 pull up control register P23 2 High Low P23 I O port data EXLCDC 0 General purpose register when FR output is selected 22 32 High Low P22 I O port data EXLCDC 0 General purpose register when CL output is selected RW P21 2 High Low P21I O port data P20 2 High Low 20 I O port data Initial value at initial reset 2 Not set in the circuit 3 Constantly 0 when being read 44 EPSON 51 63558 TECHNICAL MANUAL CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION I O Ports Table 4 6 6 1 b Control bits of I O ports Register Address Comment D3 D2 D1 DO Init 1 Output P33 control register General purpose register when SIF clock sync slave is selected 10C33 10C32 10C31 10 30 10032 0 Output Input P32 I O control register General purpose register when SIF clock sync is selected FFACH 10631 0 Output Input P31 T O control register ESIFS 0 General purpose register when SIF is selected 10030 0 Ou
92. start control only The pause function uses the same interrupt system as the dialing completion Therefore the interrupt factor flag ID must be reset before executing the pause function 51 63558 TECHNICAL MANUAL EPSON 123 CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Telephone Function 4 14 7 Flash The flash function pulls down the DP terminal to Low level for a predetermined period of time to temporarily restore the telephone to on hook status The flash time should be set to the FTS3 FTSO register FF12H Table 4 14 7 1 lists the available flash time Table 4 14 7 1 Flash time selection FTS Flash time FTS Flash time D3 D2 D1 DO msec D3 D2 D1 DO msec Unavailable 1 0 0 0 750 0 0 0 1 94 11010 1 844 0101110 188 110110 938 0101111 281 110111 1031 0111010 375 1111010 1125 0111011 469 1 1 0 1 1219 0111110 563 11110 1313 0111111 656 1 1 1 1406 Do not write 0 0000 to the FTS register because it may cause a malfunction At initial reset the flash time is set to 563 msec Writing data to the FTS register just defines the flash time The actual flash operation will be activated when the FLASH bit FF14He D0 is set to 1 Figure 4 14 7 1 shows a timing chart of the flash function HSON FF18H D3 Data bus Flash 1 Flash 2 Pulse mode ol Tone mode i Write to
93. state not used before generating an interrupt NMI if it is not used Oscillation circuit 1 It takes at least 5 msec from the time the OSC3 oscillation circuit goes ON until the oscillation stabi lizes Consequently when switching the CPU operation clock from OSC1 to OSC3 do this after a minimum of 5 msec have elapsed since the OSC3 oscillation went ON Further the oscillation stabilization time varies depending on the external oscillator characteristics and conditions of use so allow ample margin when setting the wait time 2 When switching the clock form OSC3 to OSC1 use a separate instruction for switching the OSC3 oscillation OFF An error in the CPU operation can result if this processing is performed at the same time by the one instruction 3 The internal operating voltage of is fixed at 2 2 V So it is not necessary to control the operating voltage regardless of the operating clock selected Input port 1 When input ports are changed from low to high by pull up resistors the rise of the waveform is delayed on account of the time constant of the pull up resistor and input gate capacitance Hence when fetching input ports set an appropriate waiting time Particular care needs to be taken of the key scan during key matrix configuration Make this waiting time the amount of time or more calcu lated by the following expression 10xCxR C terminal capacitance 5 pF parasitic capacitance pF R pull up resistance 330
94. status When 1 is written Transmit enabled When 0 is written Transmit disabled Reading Valid When 1 is written to TXEN TXENS the serial interface shifts to the transmit enabled status and shifts to the transmit disabled status when 0 is written Set TXEN TXENS to 0 when making the initial settings of the serial interface and similar operations At initial reset this register is set to 0 TXTRG Serial interface 1 transmit trigger status FF72H D1 TXTRGS Serial interface 2 transmit trigger status FF5AH D1 Functions as the transmit start trigger and the operation status indicator transmitting stop status When 1 is read During transmitting When 0 is read During stop When 1 is written Start transmitting When 0 is written Invalid Starts transmitting when 1 is written to TXTRG TXTRGS after writing the transmitting data TXTRG TXTRGS can be read as the status When set to 1 it indicates transmitting operation and 0 indicates transmitting stop At initial reset TXTRG TXTRGS is set to 0 1C63558 TECHNICAL MANUAL EPSON 95 CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Serial Interface RXEN Serial interface 1 receive enable register FF72H D2 RXENS Serial interface 2 receive enable register FF5AH D2 Sets the serial interface to the receive enabled status When 1 is written Receive enabled When 0 is written Receive disabled Reading Valid When 1 is written to RXEN RXENS
95. the operating voltage regardless of the operating clock selected 1C63558 TECHNICAL MANUAL EPSON 27 CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Input Ports 4 4 Input Ports K00 K03 and K10 K13 4 4 1 Configuration of input ports The 51 63558 has eight bits general purpose input ports Each of the input port terminals K00 K03 K10 K13 provides internal pull up resistor Pull up resistor can be selected for each bit with the mask option Figure 4 4 1 1 shows the configuration of input port VDD Interrupt request O AN a E Address e Vss _ Mask option Fig 4 4 1 1 Configuration of input port Selection of With pull up resistor with the mask option suits input from the push switch key matrix and so forth When Gate direct is selected the port can be used for slide switch input and interfacing with other LSIs 4 4 2 Interrupt function All eight bits of the input ports K00 K03 K10 K13 provide the interrupt function The conditions for issuing an interrupt can be set by the software Further whether to mask the interrupt function can be selected by the software Figure 4 4 2 1 shows the configuration of K00 K03 10 13 interrupt circuit KOO 10 8 lt ME Address MEE E Address Input comparison y register KCPOO 10 f Interrupt factor Interrupt i Mia flag IKO 1 o9 up i request
96. timer 1 individually The set input clock is used for the count clock during operation in the timer mode When the timer 0 is used in the event counter mode the following settings become invalid The input clock is set in the following sequence 1 Selection of source clock Select the source clock input to each prescaler from either OSC1 or OSC3 This selection is done using the source clock selection registers CKSELO timer 0 and CKSEL1 timer 1 when 0 is written to the register OSC1 is selected and when 1 is written OSC3 is selected When the OSC3 oscillation clock is selected for the clock source it is necessary to turn the OSC3 oscillation ON prior to using the programmable timer However the OSC3 oscillation circuit requires a time at least 5 msec from turning the circuit ON until the oscillation stabilizes Therefore allow an adequate interval from turning the OSC3 oscillation circuit ON to starting the programmable timer Refer to Section 4 3 Oscillation Circuit for the control and notes of the OSC3 oscillation circuit At initial reset the OSC3 oscillation circuit is set in the OFF state 2 Selection of prescaler division ratio Select the division ratio for each prescaler from among 4 types This selection is done using the prescaler division ratio selection registers 500 501 timer 0 and PTPS10 PTPS11 timer 1 Table 4 10 4 1 shows the correspondence between the setting value and the division ratio Table
97. to 2 sec or more If using this function make sure that the specified ports do not go low at the same time during ordinary operation 2 2 3 Internal register at initial resetting Initial reset initializes the CPU as shown in Table 2 2 3 1 The registers and flags which are not initialized by initial reset should be initialized in the program if necessary In particular the stack pointers SP1 and SP2 must be set as a pair because all the interrupts including NMI are masked after initial reset until both the SP1 and SP2 stack pointers are set with software When data is written to the EXT register the E flag is set and the following instruction will be executed in the extended addressing mode If an instruction which does not permit extended operation is used as the following instruction the operation is not guaranteed Therefore do not write data to the EXT register for initialization only Refer to the 51C63000 Core CPU Manual for extended addressing and usable instructions Table 2 2 3 1 Initial values CPU core Peripheral circuits Name Symbol Number of bits Setting value Name Number of bits Setting value Data register A A 4 Undefined RAM 4 Undefined Data register B B 4 Undefined Display memory 4 Undefined Extension register EXT EXT 8 Undefined Other pheripheral circuits Index register x 16 Undefined See Section 4 1 Memory Map Index register Y Y 16 Undefined Program counter PC
98. to the CHSEL register timer 0 is selected and when 1 is written timer 1 is selected Figure 4 10 6 1 shows the TOUT signal waveform when the channel is changed CHSEL _0 1 Timer 0 underflow _ Timer 1 underflow 1 TOUT output R02 Fig 4 10 6 1 TOUT signal waveform at channel change The TOUT signal can be output from the 02 output port terminal Programmable clocks can be supplied to external devices Figure 4 10 6 2 shows the configuration of the output port 02 a TOUT A4 Register I Prour Register R02 Register RO2HIZ Fig 4 10 6 2 Configuration of RO2 R02 TOUT Data bus The output of a TOUT signal is controlled by the PTOUT register When 1 is written to the PTOUT register the TOUT signal is output from the R02 output port terminal and when 0 is written the terminal goes to a high VDD level However the data register R02 must always be 1 and the high impedance control register ROZHIZ must always be 0 data output state Since the TOUT signal is generated asynchronously from the PTOUT register a hazard within 1 2 cycle is generated when the signal is turned ON and OFF by setting the register Figure 4 10 6 3 shows the output waveform of the TOUT signal RO2HIZ register Fix at 0 02 register Fix at 1 PTOUT register 0 1 T
99. transmit enable disable status When 1 is written to this register to set the transmitting enable status clock input to the shift register is enabled and the system is ready to transmit data In the clock synchronous mode synchronous clock input output from the SCLK terminal is also enabled The transmit control bit TXTRG is used as the trigger to start transmitting data Data to be transmitted is written to the transmit data shift register and when transmitting prepara tions a recomplete 1 is written to TXTRG whereupon data transmitting begins When interrupt has been enabled an interrupt is generated when the transmission is completed If there is subsequent data to be transmitted it can be sent using this interrupt In addition TXTRG can be read as a status bit When set to 1 it indicates transmitting operation and 0 indicates transmitting stop For details on timing see the timing chart which gives the timing for each mode When not transmitting set TXEN to 0 to disable transmition Receive enable register receive control bit For receiving control use the receive enable register RXEN and receive control bit RXTRG Receive enable register RXEN is used to set receiving enable disable status When 1 is written into this register to set the receiving enable status clock input to the shift register is enabled and the system is ready to receive data In the clock synchronous mode synchronous clock input output from the S
100. when being read 51 63558 TECHNICAL MANUAL EPSON 37 CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Output Ports ROOHIZ RO3HIZ RO port high impedance control register FF30H R10HIZ R13HIZ R1 port high impedance control register FF32H R20HIZ R23HIZ R2 port high impedance control register FF34H Controls high impedance output of the output port When 1 is written High impedance When 0 is written Data output Reading Valid By writing 0 to the high impedance control register the corresponding output terminal outputs accord ing to the data register When 1 is written it shifts into high impedance status When an output port 00 03 R10 R13 is used for special output fix the corresponding high imped ance control register at 0 data output At initial reset these registers are set to 0 R00 R03 RO output port data register FF31H R10 R13 R1 output port data register FF33H R20 R23 R2 output port data register FF35H Set the output data for the output ports When 1 is written High level output When 0 is written Low level output Reading Valid The output port terminals output the data written in the corresponding data registers without changing it When 1 is written to the register the output port terminal goes high VDD and when 0 is written the output port terminal goes low Vss When an output port 00 03 R10 R13 is used for special output fix the corresponding data register at
101. written to RXTRG RXTRGS the overrun error flag OER is set to 1 at the point where the following receiving has been completed When the receiving has been completed between the operation to read the received data and the operation to write 1 into RXTRG RXTRGS an overrun error occurs In addition RXTRG RXTRGS can be read as the status In either clock synchronous mode or asynchro nous mode when RXTRG RXTRGS is set to 1 it indicates receiving operation and when set to 0 it indicates that receiving has stopped At initial reset RXTRG RXTRGS is set to 0 TRXDO TRXDT7 Serial interface 1 transmit receive data FF74H FF75H TRXDOS TRXD7S Serial interface 2 transmit receive data FF5CH FF5DH During transmitting Transmitting data is set When 1 is written High level When 0 is written Low level Write the transmitting data prior to starting transmition In the case of continuous transmitting wait for the transmit completion interrupt then write the data The TRXD7 TRXD7S becomes invalid for the 7 bit asynchronous mode Converted serial data for which the bits set at 1 as High VDD level and for which the bits set at 0 as Low 55 level are output from the SOUT terminal 96 EPSON 1C63558 TECHNICAL MANUAL CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Serial Interface During receiving The received data is stored When 1 is read High level When 0 is read Low level The data from the receive
102. 0 03 0 Output Input locos 10002 IOCO 10000 Dui 10 02 0 Output Input FF40H 00 03 I O control register RW 10 01 0 Output Input 10 00 0 Output Input PULOS PULO2 PULO1 PULOO Eus S FF41H 5 rol regis um PULO1 1 On 00 03 pull up control register PULOO 1 On Of i 2 High L P02 P01 00 3 i P02 2 High Low FF42H 00 03 I O port data RW P01 2 High Low 00 2 High Low 16 5 51 63558 TECHNICAL MANUAL CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Memory Table 4 1 1 I O memory map FF44H FF4DH Register Address Comment D3 D2 D1 DO Name Init 1 0 OC13 0 Output Input P13 T O control register General purpose register when SIF clock sync slave is selected 10019 1 10042 ait OC12 0 Output Input P12 T O control register General purpose register when SIF clock sync is selected OC11 0 Output Input P11 T O control register ESIF 0 RW General purpose register when SIF is selected OC10 0 Output Input P10 T O control register ESIF 0 General purpose register when SIF is selected PUL13 1 On Off P13 pull up control register General purpose register when SIF clock sync slave is selected PUL13 PUL12 PUL11 PUL10 PUL12 1 On Off P12 pull u
103. 0 COM7 terminals using the LPAGE register It can switch the screen in an instant At initial reset the data memory content becomes undefined hence there is need to initialize using the software The display memory has read write capability and the addresses that have not been used for LCD display can be used as general purpose registers FO50H FO5FH F150H F15FH F250H F252H F254H F25EH can be used as general purpose registers except when 48 8 is selected by mask option Note When a program that access no memory mounted area FOGOH FOFFH F160H F1FFH F201H F203H F25FH is made the operation is not guaranteed 52 EPSON 1C63558 TECHNICAL MANUAL CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION LCD Driver 4 7 6 LCD contrast adjustment In the 51 63558 the LCD contrast can be adjusted by the software It is realized by controlling the voltages VC25 VC4 and VC5 output from the LCD system voltage circuit When these voltages are supplied to the externally expanded LCD driver the expanded LCD contrast is adjusted at the same time The contrast be adjusted to 16 levels as shown in Table 4 7 6 1 Table 4 7 6 1 LCD contrast e 0 0 amp R o w el amp Re ee wn CO CO CO OF memme ooo o 15 LC3 LC2 LCO cc Contrast
104. 0 Odd Even Serial I F 1 parity mode selection SCS1 0 7 SIF 1 clock sCs1 0 0 1 2 3 SCSO 0 source selection Mode 1200bps 600bps 2400bps RXTRG 0 Run Stop Serial I F 1 receive status reading TXTRG Trigger Serial I F 1 receive trigger writing FF72H RXEN 0 Enable Disable Serial I F 1 receive enable TXTRG 0 Run Stop Serial I F 1 transmit status reading Trigger Serial I F 1 transmit trigger writing TXEN 0 Enable Disable Serial 1 transmit enable 0 3 2 Unused FER 0 Error error Serial I F 1 framing error flag status reading Reset Serial I F 1 framing error flag reset writing FF73H PER 0 Error error Serial I F 1 parity error flag status reading Reset Serial I F 1 parity error flag reset writing R RW OER 0 Error error Serial I F 1 overrun error flag status reading Reset Serial I F 1 overrun error flag reset writing TRXD 2 High Li 7 TRXD3 TRXD2 TRXD1 TRXDO 9 i TRXD2 2 High Low 5 FF74H Serial I F 1 transmit receive data low order 4 bits RW TRXD1 2 High Low TRXDO 2 High Low JLSB TRXD7 2 High L MSB TRXD7 TRXD6 TRXD5 TRXD4 i TRXD6 2 High Low F E gt FF75H Serial I F 1 transmit receive data high order 4 bits RW TRXD5 2 High Low TRXD4 2 High Low J 0 3 e Unused EISER EISTR EISR FFE3H 0 3 5 SRO EISER 0 Enable Mask Interrupt mask register Serial I F 1 error R RW EI
105. 0 P13 20 23 and P30 P33 4 6 1 Configuration of I O ports The 51 63558 has 16 bits general purpose I O ports Figure 4 6 1 1 shows the configuration of the I O port Au Fig 4 6 1 1 Configuration of I O port gt Pull up control Address _p gt _ register PUL d gt 4 5 a Address z 6 bat 2 a ata Address register 4 PXX control patie m Mask option The I O port terminals 10 P13 P30 P33 are shared with the input output terminals of the serial interface 1 and 2 The P22 and P23 terminals are shared with the special output CL FR terminals The software can select these functions to be used At initial reset these are all set to the I O port Table 4 6 1 1 shows the setting of the input output terminals by function selection Table 4 6 1 1 Function setting of input output terminals Terminal Terminal status Special output Serial I F 1 2 name at initial reset CL FR Async Clk sync Master Clk sync Slave 00 03 P00 P03 Input amp Pull up 00 03 P00 P03 00 03 00 03 P00 P03 P10 P10 Input amp Pull up P10 P10 SIND SIN SINC Pll P11 Input amp Pull up Pll Pll SOUT O SOUT O SOUT O P12 2 Input amp Pull up P12 P
106. 1 63558 TECHNICAL MANUAL CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Memory Table 4 1 1 I O memory map FFE2H FFF7H Register Address Comment D3 D2 Di DO Init 1 0 3 2 5 0 0 EIPTO 4 FFE2H aon R RW 0 Enable Mask Interrupt mask register Programmable timer 1 EIPTO 0 Enable Mask Interrupt mask register Programmable timer 0 0 3 2 Unused 0 EISER EISTR EISRC FFE3H EISER 0 Enable Mask Interrupt mask register Serial I F 1 error R RW EISTR 0 Enable Mask Interrupt mask register Serial I F 1 transmit completion EISRC 0 Enable Mask Interrupt mask register Serial I F 1 receive completion 0 3 2 Unused 0 0 o Eko ae FFE4H uh R RW 0 3 2 Unused EIKO 0 Enable Mask Interrupt mask register 00 03 3 2 5 0 0 i ce FFE5H R R RW 0 3 2 Unused EIK1 0 Enable Mask Interrupt mask register K10 K13 EIT3 EIT3 0 Enable Mask Interrupt mask onn Clock 1 Hz FFEGH EIT2 0 Enable Mask Interrupt mask register Clock timer 2 Hz RW 0 Enable Mask Interrupt mask register Clock timer 8 Hz EITO 0 Enable Mask Interrupt mask register Clock timer 32 Hz 0 3 2 Unused 0 0 EISWi 9 10 gt l a FFE7H 0 3 2 Unused R RW EISW1 0 Enable Mask
107. 1 shows the configuration of the serial interface 1 The serial interface 2 has the same configuration except for the terminals Data bus T Serial I O control Received Error detection Interrupt Interrupt amp status register data buffer circuit gt control circuit request Y Y Serial input Received data Transmitting data Serial output SIN P1 0 control circuit gt shift register shift register gt control circuit SOUT P1 1 t Start bit EE gt READY output gt SRDY detection circuit Clock control circuit SRDY P1 3 onl kK control circuit 410503 OSC3 oscillation circuit SCLK P12 O4 4 Programmable timer 1 underflow signal Fig 4 11 1 1 Configuration of serial interface Serial interface input output terminals SIN SOUT SCLK and SRDY are shared with the I O ports P10 P13 In order to utilize these terminals for the serial interface input output terminals proper settings have to be made with registers ESIF SMDO and SMD1 At initial reset these terminals are set as I O port terminals The direction of I O port terminals set for serial interface input output terminals are determined by the signal and transfer mode for each terminal Furthermore the settings for the corresponding I O control registers for t
108. 12 P12 SCLK O SCLK Input amp Pull up P13 P13 P13 P13 SRDY O P20 P20 Input amp Pull up P20 P20 P20 P20 P20 P21 P21 Input amp Pull up P21 P21 P21 P21 P21 P22 P22 Input amp Pull up CL P22 P22 P22 P22 23 P23 Input amp Pull up P23 FR P23 P23 P23 P30 P30 Input amp Pull up P30 P30 SIN SIN SINC P31 P31 Input amp Pull up P31 P31 SOUT O SOUT O SOUT O P32 P32 Input amp Pull up P32 P32 P32 SCLK O SCLK P33 P33 Input amp Pull up P33 P33 P33 P33 SRDY O When these ports are used as I O ports the ports can be set to either input mode or output mode indi When with pull up resistor is selected by the mask option high impedance when gate direct is set vidually in 1 bit unit Modes can be set by writing data to the I O control registers Refer to Section 4 11 Serial Interface for control of the serial interface 51 63558 TECHNICAL MANUAL EPSON 41 CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION I O Ports 4 6 2 Mask option In the I O ports the output specification during output mode can be selected from complementary output and N channel open drain output by mask option They are selected in 1 bit units When N channel open drain output is selected do not apply a voltage exceeding the power supply voltage to the port The mask option also allows selection of whether the pull up resistor is used or not during input mode They are sel
109. 120 words x 4 bits Clock Timer Data ROM 2 048 words x 4 bits Programmable M0 7 L r 2 r LCD Driver Timer Counter SEG47 40 1 COM8 16 Lk _ 40 SEG x 17 COM m K00 K03 Vei Input Port 10 p EN n lt _ TEST E pel Controller S I ROO RO3 Output Port R10 R13 SVD 1 SVD R20 R23 Sound 4 1 Telephone Generator DP 1 Function 4 1 00 VOPot 4 P30 P33 di f 5 Demodulator iu Interface 1 CDIN RDIN D p Serial VREF EEE gt Interface 2 1 Mask option Fig 1 2 1 Block diagram 2 EPSON 51 63558 TECHNICAL MANUAL 1 3 Pin Layout Diagram QFP15 128pin 97 51 63558 CHAPTER 1 OUTLINE 128 1 32 No Pin name No Pin name No Pin name No Pin name 1 N C 33 SEG4 65 N C 97 N C 2 SEG34 34 SEG3 66 R10 98 POO 3 SEG33 35 SEG2 6
110. 3 with the voltage regulator incorporated in itself and generates three other voltages by boosting or reducing the voltage Vc23 Table 4 7 3 1 shows the 1 Vc23 VC4 and VC5 voltage values and boost reduce status Table 4 7 3 1 LCD drive voltage when generated internally LCD drive voltage Boost reduce status Voltage value V Vc2 x 0 5 1 13 Vc23 Vc2 standard 2 25 4 2 1 5 3 38 Vcs Vc2x2 4 50 Note The LCD drive voltage can be adjusted by the software see Section 4 7 6 Values in the table are typical values 4 7 4 LCD display control ON OFF and switching of duty 1 Display ON OFF control 51 63558 incorporates the ALON and ALOFF registers to blink display When 1 is written to ALON all the dots go ON and when 1 is written to ALOFF all the dots go OFF At such a time an ON waveform or an OFF waveform is output from SEG terminals When 0 is written to these registers normal display is performed Furthermore when 1 is written to both of the ALON and ALOFF ALON all ON has priority over the ALOFF all OFF 51 63558 TECHNICAL MANUAL EPSON 49 CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION LCD Driver 2 Switching of drive duty In the 51 63558 the drive duty can be set to 1 17 1 16 or 1 8 by the software This setting is done using the LDUTY1 and LDUTYO registers as shown in Table 4 7 4 1 Table 4 7 4 1 LCD drive duty setting LDUTY1 LDUTYO 1 0 1 0 0
111. 307 2340 6 RW BZFQ1 0 frequency 7 2 1 0 4 5 6 7 BZFQO 0 selection Frequency Hz 2048 0 1638 4 1365 3 1170 3 0 3 2 Unused 0 BDTY2 BDTY1 BDTYO BDTY2 0 FF6FH Buzzer signal duty ratio selection R R W BDTY1 0 refer to main manual BDTYO 0 Initial value at initial reset 2 Not set in the circuit 3 Constantly 0 when being read ROOHIZ RO1HIZ ROO RO1 port high impedance control register FF30H DO D1 Controls high impedance output of the output port When 1 is written High impedance When 0 is written Data output Reading Valid When using the BZ and XBZ outputs fix the registers at 0 RO1HIZ corresponds to the BZ output and ROOHIZ corresponds to the XBZ output At initial reset these registers are set to 0 ROO R01 ROO R01 output port data register FF31H DO D1 Set the output data for the output ports When 1 is written High level output When 0 is written Low level output Reading Valid When using the BZ and XBZ outputs fix the registers at 1 01 corresponds to the BZ output and ROO corresponds to the XBZ output At initial reset these registers are all set to 1 1C63558 TECHNICAL MANUAL EPSON 105 CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Sound Generator XBZOUT ROO output selection register FF65H DO Selects the ROO terminal function When 1 is written XBZ output When 0 is written General purpose DC output Readin
112. 4 1 1 0 COL 11011 75 1 0 1 B 1 1 0 ROW2 COL3 76 1 0 D 1 7 1 1 1 1 Writing data to this register triggers the start of the tone output When single tone output is selected either the ROW frequency or COL frequency corresponding to the written data is output as a tone signal When dual tone output is selected the specified ROW and COL frequencies are output after they are composed CRMUT Receive mute control FF18H D1 Controls the receive mute When 1 is written Receive mute output When 0 is written Low level output on XRMUTE R11 terminal Reading Valid When 0 is written to the CRMUTE register the XRMUTE R11 terminal is pulled down to Low Vss level to mute the receive line When the CRMUTE register is set to 1 the XRMUTE R11 terminal is controlled by the hardware and will be Low Vss level during a dialing pulse cycle or a flash cycle At initial reset this register is set to 1 1C63558 TECHNICAL MANUAL EPSON 133 CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Telephone Function CTMUT Transmit mute control FF18H DO Controls the transmit mute When 1 is written Transmit mute output When 0 is written Low level output on XTMUTE R10 terminal Reading Valid When 0 is wri
113. 6 Chatter entibus etae peteret 166 7 10 Characteristic Curves reference value eese 167 CHAPTER 8 PACKAGE 169 97 Plastic Package sse teet trei ed een uda ts 169 8 2 Ceramic Package for Test Samples 170 CHAPTER 9 PAD LAYOUT 171 97 Diagram of Pad Layout 3 ptite ice eet evi eee 171 922 Pad COOFQi les RR A 172 5 51 63558 TECHNICAL MANUAL CHAPTER 1 OUTLINE CHAPTER 1 OUTLINE The 51C63558 is a microcomputer which has a high performance 4 bit CPU 51 63000 as the core CPU ROM 8 192 words x 13 bits RAM 5 120 words x 4 bits serial interface watchdog timer program mable timer time base counters 2 systems SVD circuit a dot matrix LCD driver that can drive a maximum 40 segments x 17 commons DTMF DP generator FSK demodulator and sound generator built in The 51 63558 features high speed operation and low current consumption in an operating voltage range 2 2 V to 5 5 V this makes it suitable for applications working with batteries It is also suitable for caller ID and portable data bank systems because it has a large capacity of RAM built in 1 1 Features OSC1 oscillation circuit 32 768 kHz Typ crystal oscillation circuit OSC3 oscillation circuit 3 58 MHz Typ ceramic oscillation circuit Instruction set 1 Basic instruction 46 types 411 instructions with
114. 6 E0C63557 51663557 0 5251 51605251 E0C63358 S1C63358 E0C63558 S1C63558 0 6 366 S1C6P366 E0C63567 S1C63567 E0C63404 S1C63404 E0C63F567 S1C6F567 E0C63406 S1C63406 E0C63658 S1C63658 E0C63408 S1C63408 0 63666 S1C63666 0 63 408 S1C6F408 0 63 666 S1C6F666 E0C63454 S1C63454 E0C63A08 S1C63A08 E0C63455 S1C63455 E0C63B07 S1C63B07 E0C63458 S1C63458 0 63 08 S1C63B08 E0C63466 S1C63466 0 63 58 S1C63B58 0 63 466 S1C6P466 Comparison table between new and previous number of development tools Development tools for the S1C63 Family Development tools for the 51 63 88 Family Previous No New No Previous No New No ADP63366 S5U1C63366X ADS00002 S5U1C88000X1 ADP63466 S5U1C63466X GWH00002 S5U1C88000W2 ASM63 S5U1C63000A URMO00002 S5U1C88000W1 GAM63001 S5U1C63000G ICE63 S5U1C63000H1 PRC63001 S5U1C63001P PRC63002 S5U1C63002P PRC63004 S5U1C63004P PRC63005 S5U1C63005P PRC63006 S5U1C63006P PRC63007 S5U1C63007P URS63366 S5U1C63366Y 5 CONTENTS CHAPTER 1 OUTLINE 1 bh Features oeni ret echt in RUP v PME te 1 1 2 BIOCKDIGBFOHU R 2 L3 Pin Layout Diagram ee 3 TA 4 Led Maske re ENDE eroe ERR 2 CHAPTER 2 P
115. 7 R03 99 K13 4 SEG32 36 SEGI 68 R02 100 K12 5 SEG31 37 SEGO 69 01 101 6 SEG30 38 70 ROO 102 K10 7 SEG29 39 COM6 71 CDIN 103 8 SEG28 40 5 72 BPOUT 104 K02 9 SEG27 41 73 RDRC 105 01 10 SEG26 42 COM3 74 RDIN 106 KOO 11 SEG25 43 COM2 75 VREF 107 SVD 12 SEG24 44 76 AVSS 108 VCI 13 SEG23 45 COMO TI FB 109 14 22 46 Vss 78 RING 110 4 15 5 21 47 5 79 111 Vcs 16 SEG20 48 OSC2 80 AVDD 112 CC 17 SEGI9 49 81 P33 113 CB 18 SEG18 50 OSC3 82 P32 114 CA 19 SEGI7 51 OSC4 83 P31 115 COMS SEG47 20 SEGI6 52 VDD 84 P30 116 COM9 SEG47 21 SEG15 53 RESET 85 P23 117 COM10 SEG46 22 SEG14 54 TEST 86 P22 118 COM11 SEG45 23 SEG13 55 TONE 87 P21 119 COM12 SEG44 24 SEG12 56 DP 88 P20 120 COM13 SEG43 25 SEGII 57 R23 89 P13 121 COM14 SEG42 26 SEGIO 58 R22 90 P12 122 15 5 41 27 SEG9 59 R21 91 P11 123 COM16 SEG40 28 SEG8 60 R20 92 P10 124 SEG39 29 SEG7 61 R13 93 P03 125 SEG38 30 SEG6 62 R12 94 P02 126 SEG37 31 SEG5 63 R11 95 POL 127 SEG36 32 N C 64 N C 96 N C 128 SEG35 Mask option Fig 1 3 1 Pin layout diagram N C No Connection 51 63558 TECHNICAL MANUAL EPSON CHAPTER 1 OUTLINE 1 4 Pin Description Table 1 4 1 Pin description Pin na
116. ALT functions that considerably reduce the current consumption when it is not necessary The CPU enters HALT status when the HALT instruction is executed In HALT status the operation of the CPU is stopped However timers continue counting since the oscillation circuit operates Reactivating the CPU from HALT status is done by generating a hardware interrupt request including NMI 51 63558 TECHNICAL MANUAL EPSON 145 CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Interrupt and HALT ID EID IRDET m EIRDET ICDET EICDET Watchdog timer NMI request IPTO m IPT1 EIPT1 ISER EISER ISRC EISRC n ISTR IX EISTR 5 7 5 EISERS ISRCS EISRCS ISTRS 1 EISTRS 7 Interrupt Program vector counter generation low order 4 bits circuit IKO EIKO Ey S 1 i 122 gt int Interrupt request Interrupt flag L Interrupt factor flag Interrupt mask register ER J iA De gd
117. CD all Off control FF61H ALON 0 All On Normal LCD all On control RW LPAGE O F100 F15F F000 F05F Display memory area selection when 1 8 duty is selected General purpose register when 1 16 1 17 duty is selected LC3 2 7 LCD contrast adjustment LC3 LC2 LC1 LCO LC2 2 LC3 0 0 15 FF62H i RW 2 Contrast Light Dark LCO 2 3 2 0 o pzout xezout FF65H 0 3 2 Unused R RW BZOUT 0 BZ DC RO1 output selection ROI should be fixed at 1 XBZOUT O0 XBZ DC ROO output selection ROO should be fixed at 1 FSKON 0 ff FSK demodulator On Off FSKON 0 0 0 emodulator On FF66H 0 3 2 Unused RW R RDET 4 Ring NoRing Ring detection bit CDET 0 Carrier_ No Carrier Carrier detection bit 3 002 0 o 0 3 2 Unused FF67H i i R RW RDETCP 0 RDET comparison register CDETCP 0 t E CDET comparison register 18 EPSON 51 63558 TECHNICAL MANUAL CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Memory Table 4 1 1 e I O memory map FF6CH FF7AH Register Address Comment D3 D2 D1 DO Name Init 1 0 ENRTM ENRST ENON BZE ENRTM 0 1sec 0 5 Envelope releasing time selection FF6CH ENRST 3 Reset Reset Invalid Envelope reset writing
118. CD driver signal control ALOFF ALON LPAGE ALOFF 1 AllOff Normal LCD all Off control FF61H ALON 0 All On Normal LCD all On control RW LPAGE 0 F100 F15F F000 F05F Display memory area selection when 1 8 duty is selected General purpose register when 1 16 1 17 duty is selected 3 5 SMD1 0 0 1 0 SMD1 SMDO 0 VF 1 M ee master Clk sync slave FF70H SMDI 0 2 3 R RW SMDO 0 J mode selection Mode Async 7 bit Async 8 bit ESIF 0 SIF VO Serial VF 1 enable P1x port function selection Initial value at initial reset 2 Not set in the circuit 3 Constantly 0 when being read 1 Selection of port function EXLCDC Expanded LCD driver signal control register FF61H D3 Sets P22 and P23 to the CL signal and the FR signal output ports When 1 is written CL FR signal output When 0 is written I O port Reading Valid When setting P22 to the CL LCD synchronous signal output and P23 to the FR LCD frame signal output write 1 to this register and when they are used as I O ports write 0 The CL and FR signals are output from the P22 terminal and P23 terminal immediately after the functions are switched by the EXLCDC register In this case the control registers for P22 and P23 can be used as general purpose registers that do not affect the output At initial reset this register is set to 0 51 63558 TECHNICAL MANUAL EPSON 45 CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION I O
119. CLK terminal is also enabled With the above setting receiving begins and serial data input from the SIN terminal goes to the shift register The operation of the receive control bit RXTRG is slightly different depending on whether a clock synchronous system or an asynchronous system is being used In the clock synchronous system the receive control bit is used as the trigger to start receiving data When received data has been read and the preparation for next data receiving is completed write 1 into RXTRG to start receiving When 1 is written to RXTRG in slave mode SRDY switches to 0 1C63558 TECHNICAL MANUAL EPSON 81 CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Serial Interface In an asynchronous system RXTRG is used to prepare for next data receiving After reading the received data from the receive data buffer write 1 into RXTRG to signify that the receive data buffer is empty If 1 is not written into RXTRG the overrun error flag OER will be set to 1 when the next receiving operation is completed An overrun error will be generated when receiving is completed between reading the received data and the writing of 1 to RXTRG In addition RXTRG can be read as a status bit In either clock synchronous mode or asynchronous mode when RXTRG is set to 1 it indicates receiving operation and when set to 0 it indicates that receiving has stopped For details on timing see the timing chart which give
120. D1 Do frequency Hz 55155151156 COL4 1645 01 COLI 1215 88 COL2 1331 68 COL3 1471 85 COLI 1215 88 COL2 1331 68 COL3 1471 85 COLI 1215 88 COL frequency Hz COL2 1331 68 COL3 1471 85 COL2 1331 68 COL3 1471 85 COLI 1215 88 COL4 1645 01 COL4 1645 01 COL4 1645 01 D3 Slololololololo loo o o Table 4 14 10 6 b Single tone ROW frequencies SINR 1 SINC 0 TCD code ROW frequency TCD code ROW frequency D3 D2 D1 DO Hz D3 D2 D1 DO Hz ROWI 701 32 1 01 0 0 857 17 0 0 0141 ROWI 701 32 1 0 0141 857 17 0101110 ROWI 701 32 1101110 ROW4 935 10 0 0 1 1 1 701 32 1 0 1 1 ROW4 935 10 0111010 2 771 45 1114100 ROW4 935 10 0 1 01 1 ROW2 771 45 1 1 0 1 ROW 771 45 0111110 2 771 45 1 1 1 0 ROW4 935 10 0 1 1 1 ROW3 857 17 1 1 1 1 ROW3 857 17 132 EPSON 1C63558 TECHNICAL MANUAL CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Telephone Function TCDO TCD3 Telephone code for dialing FF17H By writing code to this register the dialer starts outputting the corresponding dial pulses in pulse mode or tone signals in tone mode When the output is finished an interrupt occurs At initial reset this register is se
121. Drive Common terminal duty used 1 8 COM0 COM7 1 16 15 1 17 COMO0 COMI6 Maximum segment number 320 40 x 8 640 40 x 16 680 40 x 17 When 48 x 8 mask option is selected 384 48 x 8 Invalid Invalid When 48 segments 8 commons is selected by mask option 8 16 are changed to SEG47 SEG40 Therefore 8 156 cannot be used In this case be sure to set the drive duty to 1 8 by the software Table 4 7 4 2 shows the frame frequencies corresponding to the OSC1 oscillation frequency and drive duty Table 4 7 4 2 Frame frequency OSC1 oscillation frequency 32 768 kHz When 1 8 duty is selected 32 Hz When 1 16 duty is selected 32 Hz When 1 17 duty is selected 30 12 Hz Figure 4 7 4 1 shows the dynamic drive waveform for 1 4 bias Drive duty 1 8 01 146 0 1 147 0 1 23 e 7 0 23 e 15 0 23 e 16 0 3 8 15 8 16 Frame signal 32 Hz COMO COM1 COM2 SEGO SEG1 7 4 0 When fosc1 32 768 kHz Vcs Vc4 Vc23 Vc2 Io Vss Vcs Vc4 Vc23 Vc2 Vc3 Vss Vcs Vc4 Vc23 Vc2 Vc3 Vss Vcs Vc4 Vc2 Vc3 Vci Vss Vcs Vc4 Vc2 Vc3 Vci Vss Fig 4 7 4 1 Drive waveform for 1 4 bias
122. FE9H DO Enables or disables the generation of an interrupt for the CPU When 1 is written Enabled When 0 is written Disabled Reading Valid EID is the interrupt mask register corresponding to the dialing interrupt factor Interrupts set to 1 are enabled and interrupts set to 0 are disabled At initial reset this register is set to 0 134 EPSON 1C63558 TECHNICAL MANUAL CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Telephone Function ID Interrupt factor flag FFF9H DO Indicates the dialing interrupt generation status When 1 is read Interrupt has occurred When 0 is read Interrupt has not occurred When 1 is written Flag is reset When 0 is written Invalid The interrupt factor flag ID is set to 1 when a dialing interrupt factor occurs when a dialing output pause or flash cycle is completed After executing a dialing function dialing number pause flash this flag must be reset Otherwise the next dialing function can not be executed The interrupt factor flag is reset to 0 by writing 1 After an interrupt occurs the same interrupt will occur again if the interrupt enabled state I flag 1 is set or the RETI instruction is executed unless the interrupt factor flag is reset Therefore be sure to reset write 1 to the interrupt factor flag in the interrupt service routine before shifting to the interrupt enabled state At initial reset this flag is set to 0 4 14 11 Programming not
123. FF Reading Valid When it is necessary to operate the CPU at high speed set OSCC to 1 At other times set it to 0 to reduce current consumption At initial reset this register is set to 0 CLKCHG CPU system clock switching register FFOOH D3 The CPU s operation clock is selected with this register When 1 is written OSC3 clock is selected When 0 is written OSC1 clock is selected Reading Valid When the CPU clock is to be OSC3 set CLKCHG to 1 for OSC1 set CLKCHG to 0 After turning the OSC3 oscillation ON OSCC 1 switching of the clock should be done after waiting 5 msec or more At initial reset this register is set to 0 4 3 7 Programming notes 1 It takes at least 5 msec from the time the OSC3 oscillation circuit goes ON until the oscillation stabi lizes Consequently when switching the CPU operation clock from OSC1 to OSC3 do this after a minimum of 5 msec have elapsed since the OSC3 oscillation went ON Further the oscillation stabilization time varies depending on the external oscillator characteristics and conditions of use so allow ample margin when setting the wait time 2 When switching the clock form OSC3 to OSC1 use a separate instruction for switching the OSC3 oscillation OFF An error in the CPU operation can result if this processing is performed at the same time by the one instruction 3 The internal operating voltage of VD1 is fixed at 2 2 V So it is not necessary to control
124. FFC1H DO CKSEL1 Prescaler 1 source clock selection register FFC1H D1 Selects the source clock of the prescaler When 1 is written OSC3 clock When 0 is written OSC1 clock Reading Valid The source clock for the prescaler is selected from OSC1 or OSC3 When 0 is written to the CKSELO register the OSC1 clock is selected as the input clock for the prescaler 0 for timer 0 and when 1 is written the OSC3 clock is selected Same as above the source clock for prescaler 1 is selected by the CKSEL1 register When the event counter mode is selected to timer 0 the setting of the CKSELO register becomes invalid At initial reset these registers are set to 0 500 PTPSO1 Timer 0 prescaler division ratio selection register FFC2H D2 D3 PTPS10 PTPS11 Timer 1 prescaler division ratio selection register FFC3H D2 D3 Selects the division ratio of the prescaler Two bits of PTPS00 and 501 are the prescaler division ratio selection register for timer 0 and two bits of PTPS10 and PTPS11 are for timer 1 The prescaler division ratios that can be set by these registers are shown in Table 4 10 8 2 Table 4 10 8 2 Selection of prescaler division ratio PTPS11 PTPS10 PTPSO1 500 Prescaler division ratio 1 1 Source clock 256 1 0 Source clock 32 0 1 Source clock 4 0 0 Source clock 1 When the event counter mode is selected to timer 0 the setting of the 500 501 becom
125. G 0 Run Stop Serial I F 1 transmit status reading R W Trigger Serial I F 1 transmit trigger writing TXEN 0 Enable Disable Serial I F 1 transmit enable 0 3 2 Unused 0 FER PER OER FER 0 Error No error Serial I F 1 framing error flag status reading Reset Serial I F 1 framing error flag reset writing FF73H PER 0 Error error Serial I F 1 parity error flag status reading Reset Serial I F 1 parity error flag reset writing R RW OER 0 Error error Serial I F 1 overrun error flag status reading Reset Serial I F 1 overrun error flag reset writing TRXDS TRXD2 TRXD1 TRXDO We ka i FF74H 2 9 Serial I F 1 transmit receive data low order 4 bits RW RXD1 2 High Low TRXDO 2 High Low LSB Em TRXD7 TRXD6 TRXD5 TRXD4 TRXD7 High Low 75 Migh Low Serial I F 1 transmit receive data high order 4 bit m TRXD5 32 High Low eria 1 high order 4 bits TRXD4 2 High Low J 3 _ 2 0 0 0 SIFTM cae 76 7 R RW 0 3 2 Unused SIFTM 0 Serial I F test mode disabled Do not change 3 2 Unused 0 o twrst TRuN 0 FF78H 0 3 2 Unused R w RW TMRST 3 Reset Reset Invalid Clock timer reset writing TMRUN 0 Run Stop Clock timer Run Stop TM3 TMO TM3 0 Clock data 16 Hz FF79H TM2 0 Clock timer data 32 Hz R TM1 0 Clock timer data 64 Hz TMO 0 Clock timer data 128 Hz 7 TM6
126. G39 24 0899 LL lot Fison lot Non implementation area Read write disabled us i E implemented 2 implemented FOFFH F1FFH 0 Unused area Reading Always 0 Writing Operation b When 48 x 8 is selected COM0 COM7 COM0 COM7 D3 D2 D1 DO D3 D2 D1 DO FOOOH 2 1 COMO SEGO 100 2 COM1 COMO SEGO F001H 7 6 5 COM4 SEGO 101 COM6 5 SEGO F002H 2 COMO SEG1 102 2 1 COMO SEG1 COM7 COM6 5 4 SEG1 F103H 6 5 SEG1 F004H 2 1 COMO SEG2 F104H 2 1 COMO SEG2 F05DH COM7 6 5 SEG46 F15DH COM7 COM6 5 COM4 SEG46 FO5EH 2 1 COMO SEG47 F15EH 2 1 COMO SEG47 F05FH COM6 5 SEG47 F15FH COM6 5 COM4 SEG47 FO60H F160H Not ma lot 1 implemented Cd TFT implemented FOFFH F1FFH Fig 4 7 7 1 Display memory map 54 EPSON 51 63558 TECHNICAL MANUAL CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION LCD Driver LPWR LCD power control ON OFF register FF60H DO Turns the LCD system voltage circuit O
127. I Programmable timer 0 counter 0 IPTO FFF2H DO Serial interface 1 receive error ISER FFF3H D2 Serial interface 1 receive completion ISRC FFF3H D0 Serial interface 1 transmit completion ISTR FFF3H DI Serial interface 2 receive error ISERS FFF8H D2 Serial interface 2 receive completion ISRCS FFF8H DO Serial interface 2 transmit completion ISTRS FFF8H DI K00 K03 input falling edge or rising edge 0 FFFA4H DO K10 K13 input falling edge or rising edge FFFSH DO Clock timer 1 Hz falling edge IT3 FFF6H D3 Clock timer 2 Hz falling edge IT2 FFF6H D2 Clock timer 8 Hz falling edge ITI FFF6H D1 Clock timer 32 Hz falling edge ITO FFF6H DO Stopwatch timer 1 Hz ISWI FFF7H DI1 Stopwatch timer 10 Hz ISW10 FFF7H DO Note After an interrupt occurs the same interrupt will occur again if the interrupt enabled state I flag 1 is set or the RETI instruction is executed unless the interrupt factor flag is reset Therefore be sure to reset write 1 to the interrupt factor flag in the interrupt service routine before shifting to the interrupt enabled state 1C63558 TECHNICAL MANUAL EPSON 147 CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Interrupt and HALT 4 16 2 Interrupt mask The interrupt factor flags can be masked by the corresponding interrupt mask registers The interrupt mask registers are read write registers They are enabled interrupt authori
128. IZ RO2HIZ RotHiz 109 0 pe eee RO2HIZ 0 Hi Z Output RO2 PTOUT 0 TOUT PTOUT 1 Hi z control NE 0 Hi Z Output RO1 BZOUT 0 BZ BZOUT 1 Hi z control ROOHIZ 0 Hi Z Output ROO XBZOUT 0 XBZ XBZOUT 1 Hi z control R03 R02 R01 R00 R03 1 High Low R03 output port data FOUTE 0 Fix at 1 when FOUT is used FF31H FOUT TOUT BZ XBZ Roe 1 High Low R02 output port data PTOUT 0 Fix at 1 when TOUT is used RW R01 1 High Low ROl output port data BZOUT O Fix at 1 when BZ is used R00 1 High Low ROO output port data XBZOUT O Fix at 1 when XBZ is used 3 2 o o pzout xszour 0 b FF65H 0 3 2 Unused R RW BZOUT 0 BZ DC RO1 output selection RO1 should be fixed at 1 XBZOUT 0 XBZ DC 00 output selection ROO should be fixed at 1 ENATM ENRST ENON BZE ENRTM 0 1sec Dione Envelope releasing timg selection FF6CH ENRST 3 Reset Reset Invalid Envelope reset writing RW w RW ENON 0 On Off Envelope On Off BZE 0 Enable Disable Buzzer output enable 0 3 2 Unused 0 BZSTP SHTPW p7cqp 3 Stop Invalid 1 shot buzzer stop writing FF6DH BZSHT 0 Trigger Invalid 1 shot buzzer trigger writing R RW Busy Ready I shot buzzer status reading SHTPW O0 125msec 31 25msec I shot buzzer pulse width setting 0 BZFQ2 BZFQ1 2 00 a ie 5 BZFQ2 1 0 0 1 2 3 FF6EH BZFQ2 0 1 Buzzer Frequency Hz 4096 0 32768 27
129. LD 0 On Off Hold line function RW w PAUSE 3 0 Yes No Pause function FLASH 3 0 Yes No Flash function IDP 1 71 Inter digit pause selection for dial pulse initial value 750 ms IDP3 IDP2 IDP1 IDPO a 0 IDP3 0 0 P FF15H Time ms 94 188 281 375 469 563 656 RW IDP1 0 IDP 0 8 9 10 12 13 14 15 IDPO 0 Time ms 750 844 938 1031 1125 1219 1313 1406 CTO 0 SINR SINC CTO 0 Off Continuous tone output On Off FF16H 0 3 2 Unused RW R RW SINR 1 Enable Disable DTMF row frequency output enable SINC 1 Enable Disable DTMF column frequency output enable TCD3 0 7 Telephone code for dialing TCD3 TCD2 TCD1 TCDO TCD3 0 0 1 2 3 4 5 6 7 TCD2 0 DTMF RiCa RiICD RiC2 RIC3 R2C2 R2C3 R3C1 FF17H DP x 1 2 3 4 5 6 T TCD1 TCD3 0 8 9 10 12 13 14 15 R W TCDO 0 DTMF R3C2 R3C3 RaC2 R4C3 R4C1 R2C4 R3C4 _ DP 8 9 10 11 12 13 14 15 HSON ff Hook switch On Off SON 0 Of On Hook switch Om FF18H 0 3 2 Unused RW R RW CRMUT 1 Mute 0 Receive mute control CTMUT 1 Mute 0 Transmit mute control Remarks 1 Initial value at initial reset 3 Constantly 0 when being read 2 Not set in the circuit 4 Depends on the input status of the RDIN terminal 51 63558 TECHNICAL MANUAL EPSON 15 CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Memory Table 4 1 1 b I O memory F F20H F F 42H
130. LT status continues for 3 4 seconds the non maskable interrupt releases the HALT status 4 2 2 Interrupt function If the watchdog timer is not reset periodically the non maskable interrupt NMI is generated to the core CPU Since this interrupt cannot be masked it is accepted even in the interrupt disable status I flag 0 However it is not accepted when the CPU is in the interrupt mask state until SP1 and SP2 are set as a pair such as after initial reset or during re setting the stack pointer The interrupt vector of NMI is assigned to 0100H in the program memory 1C63558 TECHNICAL MANUAL EPSON 23 CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Watchdog Timer 4 2 3 I O memory of watchdog timer Table 4 2 3 1 shows the I O address and control bits for the watchdog timer Table 4 2 3 1 Control bits of watchdog timer Register a D3 D2 D1 DO Name Init 1 0 Comment 0 3 2 Unused WDEN 1 Enable Disable Watchdog timer enable RW w WDRST 3 Reset Reset Invalid Watchdog timer reset writing Initial value at initial reset 2 Not set in the circuit 3 Constantly 0 when being read WDEN Watchdog timer enable register FF07H D1 Selects whether the watchdog timer is used enabled or not disabled When 1 is written Enabled When 0 is written Disabled Reading Valid When 1 is written to the WDEN register the watchdog timer starts count operation When
131. N LPAGE All Off Normal LCD all Off control AllOn Normal LCD all On control F100 F15F FO00 FOSF Display memory area selection when 1 8 duty is selected General purpose register when 1 16 1 17 duty is selected LCD contrast adjustment LC3 0 0 15 Contrast Light Dark Initial value at initial reset 2 Not set in the circuit 3 Constantly 0 when being read a When 40 x 17 is selected COMO COM7 COM8 COM15 COM16 D3 D2 D1 DO D3 D2 D1 DO D3 D2 D1 DO FOOOH 2 1 COMO SEGO F100H 11 10 09 8 SEGO F200H 0 0 0 16 SEGO F001H COM6 5 SEGO F101H 15 14 13 12 SEGO 201 F002H 2 1 COMO SEG1 F102H 11 10 09 COM8 SEG1 F202H 0 0 0 16 SEG1 F003H 7 6 5 COM4 SEG1 F103H COM15 14 13 12 SEG1 F203H F004H 2 1 COMO SEG2 F104H COM11 COM10 9 8 SEG2 E mE MC EN EE bog HE comm Ba 1 4 F24CH 0 0 16 SEG38 FO4DH COM7 6 5 SEG38 14 15 14 COM13 12 SEG38 F24DH FO4EH 2 COMO SEG39 14 11 10 9 COMB SEG39 F24EH 0 0 0 16 SEG39 COM6 5 SEG39 F14FH 15 COM14 13 12 SE
132. N and OFF When 1 is written ON When 0 is written OFF Reading Valid When 1 is written to the LPWR register the LCD system voltage circuit goes ON and generates the LCD drive voltage When 0 is written all the LCD drive voltages go to Vss level It takes about 100 msec for the LCD drive voltage to stabilize after starting up the LCD system voltage circuit by writing 1 to the LPWR register At initial reset this register is set to 0 LDUTYO LDUTY1 LCD drive duty switching register FF60H D2 D3 Selects the LCD drive duty Table 4 7 7 2 Drive duty setting mmon terminal Maximum ment When 48 x 8 mask option a i 1 1 8 COM0 COM7 320 40 x 8 384 48 x 8 0 1 1 16 15 640 40 x 16 Invalid 0 0 1 17 COMO0 COMI6 680 40 x 17 Invalid At initial reset this register is set to 0 When 48 x 8 is selected by mask option reset to 1 8 duty ALON LCD all ON control register FF61H D1 Displays the all LCD dots ON When 1 is written All LCD dots displayed When 0 is written Normal display Reading Valid By writing 1 to the ALON register all the LCD dots goes ON and when 0 is written it returns to normal display This function outputs an ON waveform to the SEG terminals and does not affect the content of the display memory ALON has priority over ALOFF At initial reset this register is set to 0 ALOFF LCD all OFF control register FF61H D2 Fa
133. N pull up control register when SIF is selected PUL33 1 On Off P33 pull up control register General purpose register when SIF clock sync slave is selected PUL33 PUL32 PUL30 PUL32 1 On Off P32 pull up control register General purpose register when SIF clock sync master is selected FF4DH SCLK 1 pull up control register when SIF clock sync slave is selected PUL31 1 On Off P31 pull up control register ESIFS 0 RW General purpose register when SIF is selected PUL30 1 On Off P30 pull up control register ESIFS 0 SIN pull up control register when SIF is selected SMDIS 0S 0 1 a SMD1S SMDOS ESIFS e 0 2 VF 2 master Clk sync slave FF58H SMDIS 0S 2 3 R R W 5 005 0 _ mode selection Mode Async 7 bit Async 8 bit ESIFS 0 SIF VO Serial I F 2 enable P3x port function selection EPRS PMDS scsis scsos EPRS 0 Enable Disable SUM I F 2 parity enable register FF59H PMDS 0 Odd Even Seria I F 2 parity mode selection 56515 0 SIF 2 clock SCS1S 08 0 1 2 3 5 505 0 _ source selection Mode 12006 600bps 2400bps RXTRGS 0 Run Stop Serial I F 2 receive status reading RXENS TXTRGS Trigger Serial I F 2 receive trigger writing FFSAH RXENS 0 Enable Disable Serial I F 2 receive enable TXTRGS 0 Run Stop Serial I F 2 transmit status reading RW Trigger Serial I F 2 transmit trigger writing TXENS 0 Enable Disable Serial I F 2 transmit enable 0 3 2 Unuse
134. ON 1C63558 TECHNICAL MANUAL CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Serial Interface 4 11 5 Transmit receive control Below is a description of the registers which handle transmit receive control With respect to transmit receive control procedures and operations please refer to the following sections in which these are discussed on a mode by mode basis Shift register and receive data buffer Exclusive shift registers for transmitting and receiving are installed in this serial interface Conse quently duplex communication simultaneous transmit and receive is possible when the asynchronous system is selected Data being transmitted are written to TRXDO TRXD7 and converted to serial through the shift register and is output from the SOUT terminal In the reception section a receive data buffer is installed separate from the shift register Data being received are input to the SIN terminal and is converted to parallel through the shift register and written to the receive data buffer Since the receive data buffer can be read even during serial input operation the continuous data is received efficiently However since buffer functions are not used in clock synchronous mode be sure to read out data before the next data reception begins Transmit enable register and transmit control bit For transmit control use the transmit enable register TXEN and transmit control bit TXTRG The transmit enable register TXEN is used to set the
135. OPERATION Serial Interface Receive error During receiving the following three types of errors can be detected by an interrupt 1 Parity error When writing 1 to the EPR register to select with parity check a parity check vertical parity check is executed during receiving After each data bit is sent a parity check bit is sent The parity check bit is a 0 or a 1 Even parity checking will cause the sum of the parity bit and the other bits to be even Odd parity causes the sum to be odd This is checked on the receiving side The parity check is performed when data received in the shift register is transferred to the receive data buffer It checks whether the parity check bit is a 1 or a 0 the sum of the bits including the parity bit and the parity set in the PMD register match When it does not match it is recognized as an parity error and the parity error flag PER and the error interrupt factor flag ISER is set to 1 When interrupt has been enabled an error interrupt is generated at this point The PER flag is reset to 0 by writing 1 Even when this error has been generated the received data corresponding to the error is trans ferred in the receive data buffer and the receive operation also continues The received data at this point cannot assured because of the parity error 2 Framing error In asynchronous transfer synchronization is adopted for each character at the start bit 0 and the stop bit 1 When receiv
136. OS C3 sie cie ee rore xr d ee mm rA HERR 26 4 3 4 Switching the CPU operating clock essen 26 4 3 5 Clock frequency and instruction execution time esse 4 3 6 memory of oscillation circuit eene 43 7 Programming Roles esso t pesi a e is rers 4 4 Input Ports K00 K03 and K10 K13 4 4 1 Configuration of input ports GAD Interrupt JUNCTION 44 3 Mask e teo nre xn ed Ie D EEG EE eis 4 4 4 memory of input POTHS 4312 Programming Roles cisci tnr E RUD UR ROTEN POM I 4 5 Output Ports RO0 RO3 RIO R13 and R20 R23 4 5 1 Configuration of output ports esee 4 5 2 MASK OPTION toi datas donacio erue EE ceres 1C63558 TECHNICAL MANUAL EPSON i 5 4 6 4 7 4 8 4 9 4 10 41 4 12 4 5 3 Hieh impedance Control 34 4 5 4 Special Output uiu itn t te i oin bet 34 4 5 5 1 0 memory of Output POTUS sirere aeneae eter ce deor e re ded 37 wun ae neat 40 I O Ports POO P03 P10 P13 20 23 and 30 33 41 4 6 I Configuration Of T O poris retten etie ient 41 4 6 2 VI anro E 42
137. OUT output Fig 4 10 6 3 Output waveform of the TOUT signal 51 63558 TECHNICAL MANUAL EPSON 69 CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Programmable Timer 4 10 7 Transfer rate setting for serial interface The signal that is made from underflows of timer 1 by dividing them in 1 2 can be used as the clock source for the serial interface The programmable timer outputs the clock to the serial interface by setting timer 1 into RUN state PTRUN 1 It is not necessary to control with the PTOUT register PTRUN1 Timer 1 underflow LEUTE TEE TIL TIL ILI I I I Source clock for serial I F Fig 4 10 7 1 Synchronous clock of serial interface A setting value for the RLD1X register according to a transfer rate is calculated by the following expres sion RLD1X fosc 32 bps division ratio of the prescaler 1 fosc Oscillation frequency OSC1 OSC3 bps Transfer rate 00H can be set to RLD1X Be aware that the maximum clock frequency for the serial interface is limited to 1 MHz when OSC3 is used as the clock source 70 EPSON 1C63558 TECHNICAL MANUAL 4 10 8 I O memory of programmable timer CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Programmable Timer Table 4 10 8 1 shows the I O addresses and the control bits for the programmable timer Table 4 10 8 1 Co
138. OWER SUPPLY AND INITIAL RESET 8 221 POWOT SUPPLY 8 2 1 1 Voltage lt gt for oscillation circuit and internal circuits 2 1 2 Voltage Vci Vc5 for LCD driving eese 2 2 Initial Reset iss a a 9 2 2 1 Reset terminal RESET oe oce hei oer rre 9 2 2 2 Simultaneous low input to terminals sss 10 2 2 3 Internal register at initial resetting sese 10 2 2 4 Terminal settings at initial resetting eese 11 2 3 dou Terminal TEST casus cte etes a Ls 11 12 2 12 225 12 33 12 Det Data 13 CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION 14 41 Memory Map ioco Hr erro epu reus 14 42 Watchdog Timer see t ere tur 23 4 2 1 Configuration of watchdog timer eene 23 4 2 2 Interrupt function esses 4 2 3 I O memory of watchdog timer 42 4 Propramming NOLES a Gre MPH E ETE ds 4 2 Oscillation recti terreri RE Eee 4 3 1 Configuration of oscillation circuit esee 25 4 3 2 OSCI oscillation esse tre tete E terre reete e 25 43 3
139. PHERAL CIRCUITS AND OPERATION FSK Demodulator 4 15 2 Mask option The gain of the input amplifier shown in Figure 4 15 1 2 is fixed at 1 0dB when the internal feedback resistor is used Use of this internal feedback resistor can be selected by mask option When Use is selected FB TIP RING Fig 4 15 2 1 Circuit configuration when the internal feedback resistor is used The gain is fixed at 1 0dB Leave the FB terminal open When Not use is selected example of differential input VREF Ra Re 500pF Ro TIP 4 2 RING Amp 500pF R3 Rs VREF Fig 4 15 2 2 Circuit configuration when the internal feedback resistor is not used example of differential input The gain of the amplifier can be changed with external resistors 500 resistor is recommended for R1 R5 and Re and approximately 200 kQ for and R4 The gain can be found with the following formula R5 Re GAmp Ri R2 In case of R1 R2 R3 R4 R5 Ro When Not use is selected example of single end input FB RF 500pF RIN I RING Amp V VREF eee eee Fig 4 15 2 3 Circuit configuration when the internal feedback resistor is not used example of single end input The gain of the amplifier can be changed with externa
140. Pp 250 The permissible total output current is the sum total of the current average current that simultaneously flows from the output pin or is drawn in 2 Incase of plastic package QFP15 128pin 7 2 Recommended Operating Conditions Ta 20 to 70 C Item Symbol Condition Min Typ Max Unit Supply voltage VDD Vss 0V OSC3 oscillation OFF 2 2 3 9 V OSC3 oscillation ON 22 5 5 V When DTMF is used 2 5 5 5 V When FSK is used 2 5 5 5 V Oscillation frequency fosc Crystal oscillation 32 768 kHz foscs Ceramic oscillation 3 58 36 MHz SVD terminal input voltage SVD SVDXVDp Vss 0V 0 5 5 V 160 EPSON 51 63558 TECHNICAL MANUAL 7 3 DC Characteristics Unless otherwise specified CHAPTER 7 ELECTRICAL CHARACTERISTICS 3 0 Vss 0V fosc1 32 768kHz Ta 20 to 70 C Vp1 Vci Vc23 VC4 VCs are internal voltage C1 C720 20F Item Symbol Condition Min Typ Max Unit Highlevelinput voltage 1 K00 03 K10 13 0 8 00 03 10 13 20 23 30 33 High level input voltage 2 2 RESET TEST 0 9 Vpp V High level input voltage 3 RDIN RDRC 0 75 Vpp V Low level input voltage 1 K00 03 K10 13 0 0 2 V Low level input voltage 2 _ VIL2 00 03 P10 13 20 23 30 33 0 0 4 V
141. R12 register must be fixed at 1 and the R12HIZ register at 0 When 1 is written to the HOLD register the XTMUTE R10 terminal goes Low Vss level and the HDO R12 terminal goes High VDD level When 0 is written the XTMUTE R10 terminal goes High Vpp level and the HDO R12 terminal goes Low Vss level At initial reset this register is set to 0 130 EPSON 1C63558 TECHNICAL MANUAL CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Telephone Function PAUSE Pause function FF14H D1 Executes the pause function When 1 is written Execute pause function When 0 is written Cancel pause function Reading Always 0 Writing 1 to PAUSE executes the pause function The pause time set by the PTS register is inserted to the DP output signal An interrupt occurs when the pause is released and the PAUSE bit is automatically cleared to 0 This bit is write only and so is always 0 at reading FLASH Flash function FF14H DO Executes the flash function When 1 is written Execute flash function When 0 is written Cancel flash function Reading Always 0 Writing 1 to FLASH executes the flash function The DP XRMUTE R11 and XTMUTE R10 terminals go Low Vss level during the flash period set by the FTS register and then an interrupt occurs At the same time the FLASH bit is automatically cleared to 0 by the interrupt This bit is write only and so is always 0 at reading HF Handfree FF14H D3
142. SEG33 1629 2118 93 SEG3 874 1677 3 R02 1490 2118 33 K12 1874 1557 64 SEG32 1490 2118 94 SEG2 874 1538 4 ROI 1351 2118 34 K11 1874 1419 65 SEG31 1351 2118 95 SEG1 874 1400 5 R00 1213 2118 35 K10 1874 1280 66 SEG30 1213 2118 96 SEGO 874 1261 6 CDIN 1097 2118 36 1874 1164 67 SEG29 1097 2118 97 COM7 874 1146 7 BPOUT 982 2118 37 K02 1874 1049 68 SEG28 982 2118 98 COM6 874 1030 8 RDRC 866 2118 38 01 1874 933 69 SEG27 866 2118 99 5 874 915 9 RDIN 751 2118 39 1874 818 70 26 751 2118 100 4 874 799 0 VREF 635 2118 40 SVD 1874 702 71 SEG25 635 2118 101 COM3 874 684 1 AVss 520 2118 41 1874 587 72 SEG24 520 2118 102 COM2 874 568 2 FB 404 2118 42 Vc23 1874 471 73 SEG23 404 2118 103 COMI 874 453 3 RING 289 2118 43 1874 356 74 SEG22 289 2118 104 COMO 874 337 4 TIP 173 2118 44 Vos 1874 240 75 SEG21 173 2118 105 Vss 874 222 5 AVDD 58 2118 45 cc 1874 125 76 SEG20 58 2118 106 OSCI 874 106 6 P33 58 2118 46 CB 1874 9 77 SEGI9 58 2118 107 OSC2 874 9 7 P32 173 2118 47 CA 1874 106 78 SEGIS 173 2118 108 874 125 8 P31 289 2118 48 COM8 SEG47 1874 222 79 SEGI7 289 2118 109 OSC3 874 240 9 P30 404 2118 49 COM9 SEG47 1874 337 80
143. STO PTRUNO cool division ratio Division ratio 1 1 1 4 1 32 1 256 FFC2H selection RW w RW PTRSTO 3 2 Reset Invalid Timer 0 reset reload PTRUNO 0 Run Stop Timer 0 Run Stop PTPS11 0 Prescaler 1 PTPS11 10 0 1 2 3 PTPS11 PTPS10 PTRST1 PTRUN1 PTPS10 0 division ratio Division ratio 11 1 4 1 32 1 256 FFC3H selection RW w RW PTRST1 3 2 Reset Invalid Timer 1 reset reload PTRUN1 0 Run Stop Timer 1 Run Stop RLDO3 RLDO2 RLDO1 RLDOO nee we RLD02 0 BLDO1 0 Programmable timer 0 reload data low order 4 bits EN RLDOO 0 LSB RLDO7 RLDO6 RLD05 RLDO4 1 ins FFC5H RLDOS 0 Programmable timer 0 reload data high order 4 bits RLD04 0 _ LSB RLD13 RLD12 RLD11 RLD10 att M FFC6H ALD 0 Programmable timer 1 reload data low order 4 bits ad RLD10 0 _ LSB RLD17 RLD16 RLD15 RLD14 ee MSE FFC7H RLDIS 0 Programmable timer 1 reload data high order 4 bits RLD14 0 LSB PTDO3 PTDO2 PTDO1 PTDOO FFC8H PTDO1 0 Programmable timer 0 data low order 4 bits R PTDOO 0 _ LSB PTDO7 PTDO6 PTD05 PTD04 MSH FFC9H Programmable timer 0 data high order 4 bits R PTD05 0 PTD04 0 _ LSB PTD13 PTD12 PTD11 PTD10 8 i oe PTD12 0 FFCAH Programmable timer 1 data low order 4 bits R PTD11 0 PTD10 0 LSB PTD17 PTD16 PTD15 PTD14 d 15 0 Programmable timer 1 data high order 4 bits R PTD14 0 _ LSB 20 EPSON 5
144. STR 0 Enable Mask Interrupt mask register Serial I F 1 transmit completion EISRC 0 Enable Mask Interrupt mask register Serial I F 1 receive completion 0 3 2 Unused 0 EISERS EISTRS EISRCS EISERS 0 Enable Mask Interrupt mask register Serial I F 2 error R RW EISTRS 0 Enable Mask Interrupt mask register Serial I F 2 transmit completion EISRCS 0 Enable Mask _ Interrupt mask register Serial I F 2 receive completion 3 2 R R Unused o iser istr isre Unse 0 Yes No factor flag Serial I F 1 error RW ISTR 0 W Interrupt factor flag Serial I F 1 transmit completion ISRC 0 Reset Invalid Interrupt factor flag Serial I F 1 receive completion 3 2 R R Unused o isERs istrs ics 0 SM LB ISERS 0 Yes No _ Interrupt factor flag Serial I F 2 error R RW ISTRS 0 W W Interrupt factor flag Serial I F 2 transmit completion ISRCS 0 Reset Invalid Interrupt factor flag Serial I F 2 receive completion Initial value at initial reset 2 Not set in the circuit 3 Constantly 0 when being read Serial interface 1 enable register P1 port function selection FF70H DO ESIFS Serial interface 2 enable register port function selection FF58H DO Sets P10 P13 to the input output port for the serial interface When 1 is written Serial interface W
145. T IEEE EE 64 Programmable Tete o UR NE Up HE 65 4 10 1 Configuration of programmable timer esset 65 4 10 2 Setting of initial value and counting down eee 66 4 10 3 Counter mode 4 10 4 Setting of input clock in timer mode see 68 4 10 5 Interrupt fuHcliOn isis teras etes echte aa 69 4 10 6 Seiting of TOUT oulp l 2 tiens itii Gne eee ERG 69 4 10 7 Transfer rate setting for serial interface esse 70 4 10 8 I O memory of programmable timer 4 10 9 Programming notes Serial IntevfaCe u s a 4 11 1 Configuration of serial interface eee AT 2 iyu 4 11 3 Transfer modes sc nee eterne oe o ERR 4 11 4 Clock source 4 11 5 Transmitsreceive Control iso eire rri haer Hh e ER 4 11 6 Operation of clock synchronous transfer esee 82 4 11 7 Operation of asynchronous 86 4 7 L3 IMC PIUDE PUNCH ON HEY MPG IO dern 90 4 11 91 memory of serial interface eet Gass 92 411 10 Programming NOS 99 Sound TAE cm 100 4 12 1 Configuration of sound generator 100 2 12 2 Buzzer output Circuit a aee co ee ca etre deerant io Rr da 100 EPSON 1C63558 TECHNICAL MANUAL CONTENTS 4 12 3 Control Of buzzer
146. TD is 94 msec and can be prolonged using the CTO register FF16H When the register is set to 1 before writing data to the TCD register the tone output continues until 0 is written to the CTO register However the tone signal will be output for 94 msec even if the CTO register is set to 0 before 94 msec duration time has passed The tone duration time when the CTO register is set to 0 is 94 msec When the tone signal has been output completely the TONE terminal returns to Low level then a 94 msec of inter digit pause will be inserted An interrupt occurs when the inter digit pause time has passed It allows transmission of the next tone The XTMUTE R10 terminal keeps on Low level for 4 msec of mute hold time tMH after the inter digit pause is released If the next tone output does not start in this period the XTMUTE R10 terminal returns to High level When the next tone output starts in the mute hold period the XTMUTE R10 terminal will stay in Low level Note that the CTMUT register 18 D0 and CRMUT register FF18H D1 must be set to 1 when the above mute function XTMUTE and XRMUTE control is used 118 EPSON 1C63558 TECHNICAL MANUAL CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Telephone Function The following summarizes a dialing procedure in the tone mode 1 Write 1 to the HSON register 2 Write 1 to the CTO register note 3 Write the dial tone data to the TCD register tone ou
147. TMS n an ee re FF7AH oc mne ata 2 Hz R TM5 0 Clock timer data 4 Hz 4 0 Clock timer data 8 Hz 51 63558 TECHNICAL MANUAL EPSON 19 CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Memory Table 4 1 1 f I O memory map FF7CH FFCBH Register Address a Comment D3 D2 D1 DO Init 1 1 0 3 2 o o swrst swrun 0 FF7CH 0 3 2 Unused w RW SWRST 3 Reset Reset Invalid Stopwatch timer reset writing SWRUN 0 Run Stop Stopwatch timer Run Stop SWD3 SWD2 SWD1 SWDO Rh ac di FF7DH topwatch timer data R SWD1 0 BCD 1 100 sec SWDO 0 SWD7 SWD6 SWD5 SWD4 ma 2 See niet dais FF7EH opwatch timer data R SWD5 0 BCD 1 10 sec SWD4 0 Jd 0 3 2 Unused 0 EVCNT FCSEL PLPOL FFCOH E i o EVCNT 0 Event Timer Timer 0 counter mode selection R RW FCSEL 0 With No NR Timer 0 function selection for event counter mode PLPOL 0 EE V 0 pulse polarity selection for event counter mode CHSEL PTOUT CKSEL1 CKSELO CHSEL 0 Timer TOUT output channel selection PTOUT 0 On Off TOUT output control RW CKSEL1 0 OSC3 05 1 Prescaler 1 source clock selection CKSELO 0 OSC3 05 1 Prescaler 0 source clock selection 501 0 Prescaler 0 501 00 0 1 2 3 801 PTPS00 PTR
148. TRUN1 Timer 1 RUN STOP control register FFC3H DO Controls the RUN STOP of the counter When 1 is written RUN When 0 is written STOP Reading Valid The counter in timer 0 starts counting down by writing 1 to the PTRUNO register and stops by writing 0 In STOP status the counter data is maintained until the counter is reset or is set in the next RUN status When STOP status changes to RUN status the data that has been maintained can be used for resuming the count Same as above the timer 1 counter is controlled by the PTRUNI register At initial reset these registers are set to 0 CHSEL TOUT output channel selection register FFC1H D3 Selects the channel used for TOUT signal output When 1 is written Timer 1 When 0 is written Timer 0 Reading Valid This register selects which timer s underflow timer 0 or timer 1 is used to generate a TOUT signal When 0 is written to the CHSEL register timer 0 is selected and when 1 is written timer 1 is selected At initial reset this register is set to 0 PTOUT TOUT output control register FFC1H D2 Turns TOUT signal output ON and OFF When 1 is written ON When 0 is written OFF Reading Valid PTOUT is the output control register for the TOUT signal When 1 is written to the register the TOUT signal is output from the output port terminal R02 and when 0 is written the terminal goes to a high VDD level However the data register R02 must always
149. The table was revised generated internally 4 4 7 3 49 Table 4 7 3 1 LCD drive voltage when The table was revised generated internally information of the product number change Starting April 1 2001 the product number has been changed as listed below Please use the new product number when you place an order For further information please contact Epson sales representative Configuration of product number Devices S1 63158 0 01 00 Packing specification Specification Package D die form F QFP Model number Model name C microcomputer digital products Product classification S1 semiconductor Development tools 5501 63000 1 1 00 Packing specification Version 1 Version 1 2 Tool type A1 Assembler Package 1 Corresponding model number 63000 common to S1C63 Family Tool classification C microcomputer use Product classification S5U1 development tool for semiconductor products 1 For details about tool types see the tables below In some manuals tool types are represented by one digit 2 Actual versions are not written in the manuals Comparison table between new and previous number 1C63 Family processors 51 63 Family peripheral products Previous No New No Previous No New No Previous No New No E0C63158 S1C63158 E0C63467 S1C63467 0 5250 S1C05250 E0C63256 5166325
150. Vpp Vpp V Low level input voltage 1 K00 03 K10 13 0 0 2 V Low level input voltage 2 2 00 03 P10 13 20 23 30 33 0 0 4 V Low level input voltage 3 RESET TEST 0 0 1 V Low level input voltage 4 _ VIL4 RDIN RDRC 0 0 25 V High level input current Vin 5 0V K00 03 K10 13 RDIN RDRC 0 0 5 00 03 10 13 20 23 30 33 RESET TEST SVD Low level input current 1 VILI Vss K00 03 K10 13 RDIN RDRC 0 5 0 uA No Pull up 00 03 10 13 20 23 30 33 RESET TEST SVD Low level input current 2 2 VIL2 Vss K00 03 10 13 25 15 10 uA With Pull up P00 03 10 13 20 23 30 33 5 5 High level output current 0 9 R00 03 10 13 20 23 3 mA 00 03 10 13 20 23 30 33 Low level output current 0 1 R00 03 810 13 820 23 RDRC 7 5 00 03 10 13 20 23 30 33 Common output current 2 2 5 0 05 COMO 16 25 uA IoL2 VOL2 Vss 0 05V 25 uA Segment output current VouszVcs 0 05V SEGO 39 10 IOL3 VoL3 Vss 0 05V 10 51 63558 TECHNICAL MANUAL EPSON 161 CHAPTER 7 ELECTRICAL CHARACTERISTICS 7 4 Analog Circuit Characteristics and Power Current Consumption Unless otherwise specified 3 Vss 0V fosc1 32 768kHz CG 25pF 20 to 70 C Vpi Vci Vc23 VCc4 VCs are internal voltage C1 C720 2uF
151. WI COLI 11010 1 ROW3 COL3 0 07 1 0 COL2 2 1 0 1 0 ROW4 COL2 0 010 1 1 ROWI COL3 797 110 1 1 ROW4 COL3 01110 0 ROW2 COLI 4 11110 0 ROWA COLI iid 011 0 1 ROW2 COL2 i 11110 1 ROW2 B 0 1 1 0 ROW2 COL3 6 1111140 ROWA oO 1 7 141 1 1 141 ROW3 Writing data to this register triggers the start of the tone output When single tone output is selected either the ROW frequency or COL frequency corresponding to the written data is output as a tone signal When dual tone output is selected the specified ROW and COL frequencies are output after they are composed Figure 4 14 4 2 shows a timing chart for tone output 51 63558 TECHNICAL MANUAL EPSON 117 CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Telephone Function HSON FF18H D3 Data bus Write to TCD FF17H DP TONE P trip tnP trip XRMUTE R11 x MH XTMUTE R10 Interrupt request tro Tone duration time trip Tone inter digit pause time Mute hold time Fig 4 14 4 2 Tone output timing chart By writing data to the TCD register the TONE terminal outputs the specified tone signal At the same time the XTMUTE R10 terminal goes Low level The minimum tone duration time t
152. When 0 is written Disable Reading Valid Enables the interrupt for the input ports K00 K03 K10 K13 for which 1 has been written into the interrupt selection registers SIK00 SIKO03 SIK10 SIK13 The input port set for 0 does not affect the interrupt generation condition At initial reset these registers are set to 0 KCP00 KCP03 port input comparison register FF22H KCP10 KCP13 K1 port input comparison register FF26H Interrupt conditions for terminals K00 K03 and K10 K13 can be set with these registers When 1 is written Falling edge When 0 is written Rising edge Reading Valid The interrupt conditions can be set for the rising or falling edge of input for each of the eight bits 00 and K10 K13 through the input comparison registers KCP00 KCP03 and 10 13 For KCP00 KCP03 a comparison is done only with the ports that are enabled by the interrupt among K00 K03 by means of the SIKOO SIK03 registers For KCP10 KCP13 a comparison is done only with the ports that are enabled by the interrupt among K10 K13 by means of the SIK10 SIK13 registers At initial reset these registers are set to 0 EIKO KO input interrupt mask register FFE4H DO EIK1 K1 input interrupt mask register FFEBH DO Masking the interrupt of the input port can be selected with these registers When 1 is written Enable When 0 is written Mask Reading Valid With these registers masking of the input port in
153. Z BZOUT 1 Hi z control ROOHIZ 0 Hi Z Output ROO XBZOUT 0 XBZ XBZOUT 1 Hi z control R03 R02 R01 R00 R03 1 High Low R03 output port data FOUTE 0 Fix at 1 when FOUT is used FF31H FOUT TOUT BZ XBZ R02 1 High Low R02 output port data PTOUT 0 Fix at 1 when TOUT is used RW R01 1 High Low RO1 output port data BZOUT 0 Fix at 1 when BZ is used R00 1 High Low ROO output port data XBZOUT 0 Fix at 1 when XBZ is used RISHIZ RIZHIZ RHHIZ RIOHIZ R13HIZ 0 Output R13 CHFO 0 HFO 1 HER control FF32H R12HIZ 0 Hi Z Output R12 CHDO 0 HDO CHDO 1 Hi z control 11 7 0 Hi Z Output R11 CRMO 0 KRMUTE CRMO 1 Hi z control RIOHIZ 0 Hi Z Output RIO CTMO 0 XTMUTE CTMO 1 Hi z control R13 R12 R11 R10 R13 1 High Low output port data 0 Fix at 1 when is used FF33H XRMUTE XTMUTE R12 1 High Low R12 output port data CHDO 0 Fix at 1 when HDO is used BN R11 1 High Low output port data 0 Fix at 1 when XRMUTE is used R10 1 High Low R10 output port data CTMO 0 Fix at 1 when XTMUTE is used R23HIZ Hi Z tput R22HIZ RetHIz 123 0 re R22HIZ 0 Hi Z Output 5 FF34H R20 R23 Hi z control RW 21 2 0 Hi Z Output R20HIZ 0 Hi Z Output ret mo R 1 High Low R22 1 High Low FF35H i R20 R23 output port data RW R21 1 High Low R20 1 High Low 1
154. a parity error or flaming error is generated during receiving in the asynchronous mode the receiving error interrupt factor flag ISER is set to 1 prior to the receive completion interrupt factor flag ISRC for the time indicated in Table 4 11 10 1 Consequently when an error is generated you should reset the receiving complete interrupt factor flag ISRC to 0 by providing a wait time in error processing routines and similar routines When an overrun error is generated the receiving complete interrupt factor flag ISRC is not set to 1 and a receiving complete interrupt is not generated Table 4 11 10 1 Time difference between ISER and ISRC on error generation Clock source Time difference fosc3 n 1 2 cycles of fosc3 n Programmable timer 1 cycle of timer 1 underflow 5 When the demultiplied signal of the OSC3 oscillation circuit is made the clock source it is necessary to turn the OSC3 oscillation ON prior to using the serial interface time interval of 5 msec from the turning ON of the OSC3 oscillation circuit to until the oscillation stabilizes is necessary due to the oscillation element that is used Consequently you should allow an adequate waiting time after turning ON of the OSC3 oscillation before starting transmitting receiv ing of serial interface The oscillation start time will vary somewhat depending on the oscillator and on the externally attached parts Refer to the oscillation start time example indi
155. abled by the input selection registers and the contents of the input com parison registers have been changed from matching to no matching The interrupt mask registers EIKO EIK1 enable the interrupt mask to be selected for K00 K03 and 10 K13 When the interrupt is generated the interrupt factor flag IK1 is set to 1 Figure 4 4 2 2 shows an example of an interrupt for K00 K03 Interrupt selection register Input comparison register SIKO3 SIKO2 SIKO1 SIKOO KCP02 KCPO1 KCPOO 1 1 1 0 1 0 1 0 With the above setting the interrupt of 00 is generated under the following condition Input port 1 K02 1 0 1 0 Initial value Y 2 K02 1 0 1 1 Y 3 K02 0 0 1 1 Interrupt generation Because interrupt is set to disable interrupt will be generated when no matching occurs between the 4 K02 contents of the 3 bits 01 and the 3 bits input 0 1 1 1 comparison register 1 Fig 4 4 2 2 Example of interrupt of 00 03 interrupt is disabled by the interrupt selection register 5 00 so that an interrupt does not occur at 2 At 3 changes to 0 the data of the terminals that are interrupt enabled no longer match the data of the input comparison reg
156. al output Terminal Special output Output control register R13 HFO CHFO R12 HDO CHDO R11 XRMUTE CRMO R10 XTMUTE CTMO R03 FOUT FOUTE R02 TOUT PTOUT R01 BZ BZOUT R00 XBZ XBZOUT FOUT 4 4 Register 1 Register T FOUTE CHFO Register R03 Register R13 R03 J 1 FOUT R13 HFO Register Register ROSHIZ R13HIZ TOUT 4 HDO 4 Register T Register T PTOUT CHDO Register R02 Register R12 gt m L TOUT ne HDO Register Register 2 RO2HIZ R12HIZ 8 2 1 8 XRMUTE 7 egister egis BZOUT CRMO Register gt R01 Register R11 R01 BZ R11 XRMUTE Register Register RO1HIZ R11HIZ XBZ XTMUTE Register T T XBZOUT CTMO Register gt o _ Roo Register R10 ROO XBZ R10 XTMUTE Register Register NA ROOHIZ R10HIZ Fig 4 5 4 1 a Configuration of ROO R03 output ports Fig 4 5 4 1 b Configuration of RIO R13 output ports At initial reset the output port data register is set to 1 and the high impedance control register is set to 0 Cons
157. all Addressing mode 8 types Instruction execution time During operation at 32 768 kHz 61 psec 122 sec 183 psec During operation at 3 58 MHz 0 56 psec 1 12 psec 1 68 psec ROM capacity Code 8 192 words x 13 bits Data ROM 2 048 words x 4 bits 8K bits RAM Data memory 5 120 words x 4 bits Display memory 816 bits 192 words x 4 bits 48 x 1 bit WP UU 8 bits Pull up resistors may be supplemented 1 Qutp lt 12bits Itis possible to switch the 8 bits to special output 2 enn l6bits Itis possible to switch the 2 bits to special output and the 4 bits to serial I F input output 2 Serial interface eee 2 ch 8 bit clock synchronous or asynchronous system is selectable LCD driver interes 40 segments x 8 16 or 17 commons 2 48 segments x 8 commons 1 Time base counter 2 systems Clock timer stopwatch timer Programmable timer Built in 2 inputs x 8 bits with event counter function Watchdog timer Built in DTMF generator Built in DP generator Built in FSK demodulator Built in Compatible with ITU T V 23 Bell 202 Sound generator With envelope and 1 shot output functions Supply
158. ammable timer can be read from these latches The low order 4 bits of the count data in timer 0 can be read from 00 03 and the high order data can be read from PTD04 PTDO7 Similarly for timer 1 the low order 4 bits can be read from PTD10 PTD13 and the high order data can be read from PTD14 PTD17 Since the high order 4 bits are held by reading the low order 4 bits be sure to read the low order 4 bits first Since these latches are exclusively for reading the writing operation is invalid At initial reset these counter data are set to 00H 1C63558 TECHNICAL MANUAL EPSON 73 CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Programmable Timer PTRSTO Timer 0 reset reload FFC2H D1 PTRST1 Timer 1 reset reload FFC3H D1 Resets the timer and presets reload data to the counter When 1 is written Reset When 0 is written No operation Reading Always 0 By writing 1 to PTRSTO the reload data in the reload register PLD00 PLDO7 is preset to the counter in timer 0 Similarly the reload data in PLD10 PLD17 is preset to the counter in timer 1 by PTRST1 When the counter is preset in the RUN status the counter restarts immediately after presetting In the case of STOP status the reload data is preset to the counter and is maintained No operation results when 0 is written Since these bits are exclusively for writing always set to 0 during reading PTRUNO Timer 0 RUN STOP control register FFC2H DO P
159. and XTMUTE R10 terminals will stay in Low level Note that the CTMUT register FF18H D0 and CRMUT register 18 D1 must be set to 1 when the above mute function XTMUTE and XRMUTE control is used The following summarizes a dialing procedure in the pulse mode 1 Write 1 to the HSON register 2 Write a dial number to the TCD register pulse output starts 3 Reset the interrupt factor flag after an interrupt has occurred 4 Repeat steps 2 to 3 for the number of dial digits Communication 5 Write 0 to the HSON register after communication is finished 1C63558 TECHNICAL MANUAL EPSON 121 CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Telephone Function 4 14 6 Pause This dialer allows insertion of a pause within 1 to 15 seconds between each two digits of tone signals or pulses The pause time should be set to the 53 50 register FF11H as shown in Table 4 14 6 1 before dialing Table 4 14 6 1 Pause time selection D3 Bel Pause time sec 55 2518 po Pause time sec Unavailable 1101010 8 0 0 011 1 1 0 0 1 9 0 1 0 2 110 1 0 10 010111 3 1 01 11 1 11 0111010 4 11141010 12 0 1 0 1 5 1 1 0 1 13 0111110 6 1 11 1 0 14 0 1 1 1 7 1 1 141 15 Do not write 0 0000 to the PTS register because it may cause a malfunction At initial reset the pause time is set to 4 seconds Writing data to the PTS regis
160. arry from low order digits SWD0 SWDJ9 into high order digits SWD4 SWD i e in case SWDO SWD3 and SWD4 SWD7 reading span the timing of the carry To avoid this occurrence perform the reading after suspending the counter once and then set the SWRUN to 1 again Moreover it is required that the suspension period not exceed 976 psec 1 4 cycle of 256 Hz At initial reset this register is set to 0 EISW10 10Hz interrupt mask register FFE7H DO EISW1 1Hz interrupt mask register FFE7H D1 These registers are used to select whether to mask the stopwatch timer interrupt When 1 is written Enabled When 0 is written Masked Reading Valid The interrupt mask registers EISW10 EISW1 are used to select whether to mask the interrupt to the separate frequencies 10 Hz 1 Hz At initial reset these registers are set to 0 ISW10 10 Hz interrupt factor flag FFF7H DO ISW1 1Hzinterrupt factor flag FFF7H D1 These flags indicate the status of the stopwatch timer interrupt When 1 is read Interrupt has occurred When 0 is read Interrupt has not occurred When 1 is written Flag is reset When 0 is written Invalid The interrupt factor flags ISW10 and ISW1 correspond to 10 Hz and 1 Hz stopwatch timer interrupts respectively The software can judge from these flags whether there is a stopwatch timer interrupt However even if the interrupt is masked the flags are set to 1 by the overflow of the corresponding coun
161. ately following the inter digit pause See the timing chart in Figure 4 14 5 2 2 Pause interrupt When the pause function is executed an interrupt occurs when the pause time 1 to 15 sec set by the PTS register has passed after writing 1 to the PAUSE bit See the timing chart in Figure 4 14 6 1 3 Flash interrupt When the flash function is executed 938 msec of a flash pause is made when the flash time 94 to 1 406 msec set by the FTS register has passed after writing 1 to the FLASH bit A flash interrupt occurs immediately following the flash pause See the timing chart in Figure 4 14 7 1 The interrupt factor flag ID D0 is set to 1 when an interrupt occurs The interrupt request will be delivered to the CPU only when the interrupt mask register EID FFE9H D0 is set to 1 If the EID register is set to 0 the interrupt request will be masked However the ID flag will be set at the above Iming regardless of the EID register setting So operation status can also be checked by reading the ID flag The ID flag is reset by writing 1 It must be reset for the next interrupt after an interrupt has occurred 126 EPSON 1C63558 TECHNICAL MANUAL CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Telephone Function 4 14 10 I O memory of telephone function Table 4 14 10 1 shows the I O address and the control bits for the telephone function Table 4 14 10 1 Control bits of telephone function
162. ation is not assumed in the S1C63558 3 2 Code ROM The built in code ROM is a mask ROM for loading programs and has a capacity of 8 192 steps x 13 bits The core CPU can linearly access the program space up to step FFFFH from step 0000H however the program area of the 51 63558 is step 0000H to step 1FFFH The program start address after initial reset is assigned to step 0110H The non maskable interrupt NMI vector and hardware interrupt vectors are allocated to step 0100H and steps 0104 010 respectively 0000H Program area 1C63558 ROM program area 0100H NMI vector 1FFFH M m 2000H Hardware 010EH interrupt vectors Eee 51 63000 core CPU program space 01 10H Program start address FFFFH Unused area Y Program area 13 bits Fig 3 2 1 Configuration of code ROM 3 3 RAM The RAM is a data memory for storing various kinds of data and has a capacity of 5 120 words x 4 bits The RAM area is assigned to addresses 0000H to 13FFH on the data memory map Addresses 0100H to O1FFH are 4 bit 16 bit data accessible areas and in other areas it is only possible to access 4 bit data When programming keep the following points in mind 1 Part of the RAM area is used as a stack area for subroutine call and register evacuation so pay attention not to overlap the data area and stack area 2 The 51 63000 core CPU handles the stack using the stac
163. ble register EPR to set to with parity check As a result of this setting in the 7 bit asynchronous mode it has a 7 bits data parity bit configuration and in the 8 bit asynchronous mode it has an 8 bits data parity bit configuration In this case parity checking for receiving and adding a party bit for transmitting is done automatically in hardware Moreover when with parity check has been selected odd or even parity must be further selected in the parity mode selection register PMD When 0 is written to the PMD register to select without parity check in the 7 bit asynchronous mode data configuration is set to 7 bits data no parity and in the 8 bit asynchronous mode no parity it is set to 8 bits data no parity and parity checking and parity bit adding will not be done 5 Clock source selection Select the clock source by writing data to the two bits of the clock source selection registers 5 50 and 5 51 See Table 4 11 4 1 6 Clock source control When the programmable timer is selected for the clock source set transfer rate on the programma ble timer side See 4 10 Programmable Timer When the divided signal of OSC3 oscillation circuit is selected for the clock source be sure that the OSC3 oscillation circuit is turned ON prior to commencing data transfer See 4 3 Oscillation Circuit Data transmit procedure The control procedure and operation during transmitting is as follows 1 Write 0 in the transmi
164. cated in Chapter 7 Electrical Chracteristics At initial reset the OSC3 oscillation circuit is set to OFF status 6 Be aware that the maximum clock frequency for the serial interface is limited to 1 MHz 7 After an interrupt occurs the same interrupt will occur again if the interrupt enabled state I flag 1 is set or the RETI instruction is executed unless the interrupt factor flag is reset Therefore be sure to reset write 1 to the interrupt factor flag in the interrupt service routine before shifting to the interrupt enabled state 1C63558 TECHNICAL MANUAL EPSON 99 CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Sound Generator 4 12 Sound Generator 4 12 1 Configuration of sound generator The 51 63558 has a built in sound generator for generating buzzer signals Hence generated buzzer signals be output from the ROO XBZ and 01 BZ terminals Aside permitting the respective setting of the buzzer signal frequency and sound level to 8 stages it permits the adding of a digital envelope by means of duty ratio control It also has a one shot output function for outputting key operated sounds Figure 4 12 1 1 shows the configuration of the sound generator BZFQO BZFQ 2 BDTYO BDTY 2 ENON Y Y Y Programmable Duty ratio Envelope 4 ENRST dividing circuit control circuit addition circuit ENRTM fosc1
165. cillator and two capacitors gate and drain capacitance are required Figure 4 3 3 1 is the block diagram of the OSC3 oscillation circuit 9 and some peripheral circuits o 5 2 oc Oscillation circuit control signal Vss Fig 4 3 3 1 OSC3 oscillation circuit As shown in Figure 4 3 3 1 the ceramic oscillation circuit can be configured by connecting the ceramic oscillator 3 58 MHz between the OSC3 and OSC4 terminals capacitor CGC between the OSC3 and OSC4 terminals and capacitor CDC between the OSC4 and Vss terminals For both and CDC connect capacitors that are about 30 pF To reduce current consumption of the OSC3 oscillation circuit oscillation can be stopped by the software OSCC register 4 3 4 Switching the CPU operating clock The CPU system clock is switched to OSC1 or OSC3 by the software CLKCHG register When OSC3 is to be used as the CPU system clock first turn the OSC3 oscillation ON and switch the clock after waiting 5 msec or more for oscillation stabilization When switching from OSC3 to OSC1 turn the OSC3 oscillation circuit OFF after switching the clock OSCI gt gt OSC3 OSC3 1 Set OSCC to 1 OSC3 oscillation ON 1 Set CLKCHG to 0 OSC3 OSC1 2 Maintain 5 msec or more 2 Set OSCC to 0 OSC3 oscillation OFF 3 Set CLKCHG to 1 OSC1 OSC3 Note When switching the clock form OSC3 to OSC1
166. created by the FOG63558 Refer to the 55U1C63558D Manual for the FOG63558 Functions selectable with S1C63558 mask options 1 External reset by simultaneous LOW input to the input port K00 K03 This function resets the IC when several keys are pressed simultaneously The mask option is used to select whether this function is used or not Further when the function is used a combination of the input ports K00 K03 which are connected to the keys to be pressed simultaneously can be selected Refer to Section 2 2 2 Simultaneous low input to terminals 00 03 for details 2 Time authorize circuit for the simultaneous LOW input reset function When using the external reset function shown in 1 above using the time authorize circuit or not can be selected by the mask option The reset function works only when the input time of simultaneous LOW is more than the rule time if the time authorize circuit is being used Refer to Section 2 2 2 Simultaneous low input to terminals 00 03 for details 3 Input port pull up resistor The mask option is used to select whether the pull up resistor is supplemented to the input ports or not It is possible to select for each bit of the input ports Refer to Section 4 4 3 Mask option for details 4 Output specification of the output port Either complementary output or N channel open drain output can be selected as the output specifica tion for the output ports The selection is d
167. cted by mask option SCLK pull up is effective only in the slave mode In the master mode the PUL12 PUL32 register be used as a general purpose register At initial reset these registers are set to 1 and the lines are pulled up SMDO SMD1 Serial interface 1 mode selection register FF70H D1 D2 SMDOS SMD1S Serial interface 2 mode selection register FF58H D1 D2 Set the transfer modes as shown in Table 4 11 9 2 Table 4 11 9 2 Transfer mode settings SMD1 SMD1S SMDO SMDOS Mode 1 1 8 bit asynchronous 1 0 7 bit asynchronous 0 1 Clock synchronous slave 0 0 Clock synchronous master This register can also read out At initial reset this register is set to 0 5 50 SCS1 Serial interface 1 clock source selection register FF71H DO D1 5 505 SCS1S Serial interface 2 clock source selection register FF59H DO D1 Select the clock source as shown in Table 4 11 9 3 Table 4 11 9 3 Clock source selection SCS1 SCSO Clock source Programmable timer fosc3 93 2400 bps fosc3 372 600 bps fosc3 186 1200 bps O This register can also be read out In the clock synchronous slave mode setting of this register is invalid At initial reset this register is set to 0 94 EPSON 51 63558 TECHNICAL MANUAL CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Serial Interface EPR Serial interface 1 parity enable register FF71H D3 EPRS Serial
168. cuit 4 Mask option VoD BP Time Mask optio Y authorize 2 circuit gt 2 Internal i circuit gt initial i E reset Q RESET 4 Fig 2 2 1 Configuration of initial reset circuit 2 2 1 Reset terminal RESET Initial reset can be executed externally by setting the reset terminal to a low level Vss After that the initial reset is released by setting the reset terminal to a high level VDD and the CPU starts operating The reset input signal is maintained by the RS latch and becomes the internal initial reset signal The RS latch is designed to be released by a 2 Hz signal high that is divided by the OSC1 clock Therefore in normal operation a maximum of 250 msec when fosc1 32 768 kHz is needed until the internal initial reset is released after the reset terminal goes to high level Be sure to maintain a reset input of 0 1 msec or more However when turning the power on the reset terminal should be set at a low level as in the timing shown in Figure 2 2 1 1 22V VDD 2 0 msec or more RESET 0 5 VDD 0 1 or less low level Power on Fig 2 2 1 1 Initial reset at power on The reset terminal should be set to 0 1 VDD or less low level until the supply voltage becomes 2 2 V or more After that a level of 0 5 VDD or less should be maintained more than 2 0 msec 1C63558 TECHNICAL MANUAL EPSON 9 CHAPTER 2 POWER SUPPLY AND INITIAL RESET 2 2
169. d FERS PERS OERS FERS 0 Error error Serial I F 2 framing error flag status reading Reset Serial I F 2 framing error flag reset writing FF5BH PERS 0 Error error Serial I F 2 parity error flag status reading Reset Serial I F 2 parity error flag reset writing R RW OERS 0 Error error Serial I F 2 overrun error flag status reading Reset Serial I F 2 overrun error flag reset writing FF5CH 6 Serial I F 2 transmit receive data low order 4 bits RW TRXD1S 2 High Low TRXDOS 2 High Low LSB gt pa a a FF5DH TRXDsS 2 High Low Serial I F 2 transmit receive data high order 4 bits TRXD4S 2 High Low Initial value at initial reset 2 Not set in the circuit 3 Constantly 0 when being read 92 EPSON 51 63558 TECHNICAL MANUAL CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Serial Interface Table 4 11 9 1 b Serial interface control bits Register Address D3 D2 D1 DO Name Init 1 0 0 3 2 Unused SMDI 0 0 1 Mode Clk sync master Clk sync slave FF70H SMD1 0 Serial I F SMD1 0 2 4 R SMDO 0 _ mode selection Mode Async 7 bit Async 8 bit ESIF 0 SIF VO Serial I F 1 enable P1x port function selection EPR PMD scsi scso EPR 0 Enable Disable UM I F 1 parity enable FF71H PMD
170. d state I flag 1 is set or the RETI instruction is executed unless the interrupt factor flag is reset Therefore be sure to reset write 1 to the interrupt factor flag in the interrupt service routine before shifting to the interrupt enabled state At initial reset these flags set to 0 1C63558 TECHNICAL MANUAL EPSON 75 CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Programmable Timer 4 10 9 Programming notes 1 When reading counter data be sure to read the low order 4 bits PTD00 PTD03 PTD10 PTD13 first Furthermore the high order 4 bits PID04 PTD07 PTD14 PTD17 should be read within 0 73 msec when fosci is 32 768 kHz of reading the low order 4 bits PID00 PTD03 PTD10 PTD13 2 The programmable timer actually enters RUN STOP status in synchronization with the falling edge of the input clock after writing to the PTRUNO PTRUNI register Consequently when 0 is written to the PTRUNO PTRUNI register the timer enters STOP status at the point where the counter is decremented 1 The PTRUNO PTRUNI register maintains 1 for reading until the timer actually stops Figure 4 10 9 1 shows the timing chart for the RUN STOP control Input clock PTRUNO PTRUN1 RD n4 RUN 0 STOP PTRUNO PTRUN1 WR l writing l writing PTDOX PTD1X 42H Ja1H 4oHYsFH sEH Fig 4 10 9 1 Timing chart for RUN STOP control Itis the same even in the ev
171. de DTMF In tone mode the dialer outputs a tone pushbutton dial signal This mode is set by default at initial reset To change the mode from pulse mode to this mode write 0 to the TPS register 10 The PB tone signal generates two different frequencies that are determined by the pushed button in the push button matrix as shown in Table 4 14 4 1 Table 4 14 4 1 PB frequency combination Frequency COL1 COL2 COL4 Hz 1209 1336 1477 1633 5 1 2 3 Unused a 6 Unused PX 7 8 9 Unused peu 0 Unused The row and column frequencies and the compound tone signal are generated by the DTMF Dual Tone Multi Frequency generator Figure 4 14 4 1 shows the block diagram of the DTMF generator Data bus e Row group Sine wave 8 58 Frequency programmable pattern gt a oscillator divider gt divider ROM converter 4 1 4 gt O TONE Control SINR Column group Sine wave D A ble gt tt c registers SINC gt M ROM converter vs re i Fig 4 14 4 1 DTMF generator block diagram As shown in Figure 4 14 4 1 the DTMF generator generates each frequency by dividing the OSC3 3 58 MHz clock Therefore the OSC3 oscillation circuit must be turned ON before using the DTMF generator it is not necessary to switch the CPU system clock to OSC3 Two frequency
172. de outs the all LCD dots When 1 is written All LCD dots fade out When 0 is written Normal display Reading Valid By writing 1 to the ALOFF register all the LCD dots goes OFF and when 0 is written it returns to normal display This function outputs an OFF waveform to the SEG terminals and does not affect the content of the display memory At initial reset this register is set to 1 51 63558 TECHNICAL MANUAL EPSON 55 CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION LCD Driver LPAGE LCD display memory selection register FF61H DO Selects the display memory area at 1 8 duty drive When 1 is written F100H F14FH when 40 x 17 is selected FIOOH F15FH when 48 x 8 is selected When 0 is written F000H F0A4FH when 40 x 17 is selected FO00H F05FH when 48 x 8 is selected Reading Valid By writing 1 to the LPAGE register the data set in F100H F14FH F15FH the second half of the display memory is displayed and when 0 is written the data set in FOOOH F04FH FO5FH the first half of the display memory is displayed This function is valid only when 1 8 duty is selected and when 1 16 or 1 17 duty is selected this register can be used as a general purpose register At initial reset this register is set to 0 LC3 LCO LCD contrast adjustment register FF62H Adjusts the LCD contrast LC3 LCO 00008 light LC3 LCO 1111B dark At room temperature use setting number 7 or 8 as standard At initial rese
173. demodulator input amplifier The gain of the FSK demodulator input amplifier can be either fixed at 1 using the internal feedback resistor or varied using external resistors Refer to Section 4 15 2 Mask option for details 10 Output specification of other special output terminals The following special output terminals are shared with the output R terminals or the I O P terminals Consequently the output specification complementary output or N channel open drain output of the shared terminal applies to the special output Special output signal Shared port XBZ BZ TOUT FOUT Output ports R00 R03 XRMUTE XTMUTE HDO HFO Output ports R10 R13 Serial interface input output I O ports P10 P13 CL FR I O ports P22 P23 lt Mask option list gt The following is the option list for the 51 63558 Multiple selections are available in each option item as indicated in the option list Refer to Chapter 4 Peripheral Circuits and Operation to select the specifica tions that meet the application system Be sure to select the specifications for unused functions too according to the instruction provided Use fog63558 the S5U1C63000A package for this selection Refer to the S5U1C63558D Manual for details 1 MULTIPLE KEY ENTRY RESET COMBINATION 711 Not Use 2 Use K00 K01 K02 K03 3 Use K00 K01 02 gt 714 Use K00 01 gt gt 2 MULTIPLE KEY ENTRY RESET TIME AUTHORIZE
174. dial number can be preset It produces dial pulses by means of a count down until it is equal to 0 The pulse specification can be set by software and the timing control circuit controls the down counter according to the settings The software can set a pulse rate make ratio and an inter digit pause time The pulse rate is a number of output pulses per second and can be selected to be either 10 pps DRS 0 or 20 pps DRS 1 using the DRS register At initial reset it is set to 10 pps DRS 0 The make ratio M B is the ratio of the make period High to the break period Low It can be selected to either 40 60 MB 0 33 3 66 6 MB 1 using the MB register FF10HeD1 At initial reset it is set to 40 60 MB 0 51 63558 TECHNICAL MANUAL EPSON 119 CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Telephone Function The inter digit pause time is the interval between digits of a dial number It can be selected from among 15 types within 94 msec to 1 406 msec using the IDP3 IDPO register FF15H as shown in Table 4 14 5 1 Table 4 14 5 1 Selection of inter digit pause time IDP Inter digit pause IDP Inter digit pause D3 D2 D1 DO time msec D3 D2 D1 DO time msec Unavailable 14010 750 01010 1 94 1101011 844 0101110 188 110 110 938 010111 281 1 0 1 l 1031 0111010 375 1111010 1125 0 1 0 1 469 1 1 0 1 1219 0 1 1 0 563 1 1 11 0 1313 0 1 1 1 656 1 1 1 1 1406
175. during 1 MHz operation Condition 3 0 Vss 0V 20 to 70 C 0 8 ViLi 0 2Vpp 0 8 VoL 0 2 Vpp Item Symbol Min Unit Transmitting data output delay time tssd 500 ns Receiving data input set up time tsss 400 ns Receiving data input hold time tssh 200 ns 3 Note that the maximum clock frequency is limited to 1 MHz lt Master mode gt VOH 4 SCLK OUT VoL y tsmd SOUT ve X is tsms tsmh SIN VIL1 Slave mode VIH1 5 SCLK IN Yita y SOUT VoH X SIN Asynchronous system Condition 2 2 to 5 5V Vss 0V 20 to 70 C Item Symbol Min Unit Start bit detection error time 1 tsai 0 U16 8 Erroneous start bit detection range time 2 tsa2 9t 16 10t 16 5 Start bit detection error time is logical delay time from inputting the start bit until internal sampling begins operating Time as far as AC is excluded 2 Erroneous start bit detection range time is a logical range to detect whether a LOW level start bit has been input again after a start bit has been detected and the internal sampling clock has started When a HIGH level is detected the start bit detection circuit is reset and goes into a wait status until the next start bit Time as far as AC is excluded Start bit SIN A X 7 Stop bit
176. e OSC1 OSC2 OSC3 and OSC4 terminals such as oscillators resistors and capacitors should be connected in the shortest line Sample Vss pattern OSC3 2 As shown in the right hand figure make a Vss pattern as large as possible at circumscription of the OSC1 OSC2 OSC3 and OSC4 terminals and the components connected to these terminals Furthermore do not use this Vss pattern for any purpose other than the oscillation system In order to prevent unstable operation of the oscillation circuit due to current leak between OSC1 OSC3 and VDD please keep enough distance between OSC1 OSC3 and VDD or other signals on the board pattern Reset Circuit The power on reset signal which is input to the RESET terminal changes depending on conditions power rise time components used board pattern etc Decide the time constant of the capacitor and resistor after enough tests have been completed with the application product When the built in pull up resistor is added to the RESET terminal by mask option take into consider ation dispersion of the resistance for setting the constant In order to prevent any occurrences of unnecessary resetting caused by noise during operating components such as capacitors and resistors should be connected to the RESET terminal in the shortest line Power Supply Circuit Sudden power supply variation due to noise may cause malfunction Consider the following poin
177. e RO1 terminal can output a BZ signal The BZ signal is the buzzer signal that is output from the sound generator To output the BZ signal set the 01 port as the BZ output by writing 1 to the BZOUT register and fix the R01 register at 1 and the RO1HIZ register at 0 Use the BZE register for controlling ON OFF the BZ signal output Refer to Section 4 12 Sound Generator for details of the buzzer signal and controlling method TOUT R02 The R02 terminal can output a TOUT signal The TOUT signal is the clock that is output from the programmable timer and can be used to provide a clock signal to an external device To output the TOUT signal fix the R02 register at 1 and the RO2HIZ register at 0 and turn the signal ON and OFF using the PTOUT register It is however necessary to control the programmable timer Refer to Section 4 10 Programmable Timer for details of the TOUT signal and controlling method FOUT R03 The R03 terminal can output an FOUT signal The FOUT signal is a clock fosci or foscs3 that is output from the oscillation circuit or a clock that the fosci clock has divided in the internal circuit and can be used to provide a clock signal to an external device To output the FOUT signal fix the R03 register at 1 and the RO3HIZ register at 0 and turn the signal ON and OFF using the FOUTE register The frequency of the output clock may be selected from among 4 types shown in Table 4 5 4 2 by setting the
178. e at initial reset CL FR Async Clk sync Master Clk sync Slave 00 03 PO0 PO3 Input amp Pull up 1 P10 P10 Input amp Pull up 1 SIN I SIN I SIN I Pll P11 Input amp Pull up 1 SOUT O SOUT O SOUT O P12 P12 Input amp Pull up 1 SCLK O SCLK P13 P13 Input amp Pull up 1 SRDY O P20 P20 Input amp Pull up 1 P21 P21 Input amp Pull up 1 P22 P22 Input amp Pull up 1 CL P23 P23 Input amp Pull up 1 FR P30 P30 Input amp Pull up 1 SIN SING SING P31 P31 Input amp Pull up 1 SOUT O SOUT O SOUT O P32 P32 Input amp Pull up 1 SCLK O SCLK P33 P33 Input amp Pull up 1 SRDY O 1 When with pull up is selected by mask option high impedance when gate direct is selected 2 The 0 I O terminals are used for serial I F 1 and the P30 P33 I O terminals are for serial I F 2 For setting procedure of the functions see explanations for each of the peripheral circuits 2 3 Test Terminal TEST This is the terminal used for the factory inspection of the IC During normal operation connect the TEST terminal to VDD 51 63558 TECHNICAL MANUAL EPSON 11 CHAPTER 3 CPU ROM RAM CHAPTER CPU ROM RAM 3 1 CPU The 51C63558 has 4 bit core CPU 51 63000 built in as its CPU part Refer to the S1C63000 Core CPU Manual for the 51 63000 Note The SLP instruction cannot be used because the SLEEP oper
179. e receiver mute signal used for the telephone function To output the XRMUTE signal set the R11 port as the XRMUTE output by writing 1 to the CRMO register and fix the R11 register at 1 and the R11HIZ register at 0 Use the CRMUTE register for controlling the XRMUTE signal output Refer to Section 4 14 Telephone Function for details of the signal and controlling method HDO R12 The R12 terminal can output a HDO signal The HDO signal is the hold line signal used for the telephone function To output the HDO signal set the R12 port as the HDO output by writing 1 to the CHDO register and fix the R12 register at 1 and the R12HIZ register at 0 Use the HOLD register for controlling the HDO signal output Refer to Section 4 14 Telephone Function for details of the signal and controlling method HFO R13 The R13 terminal can output a HFO signal The HFO signal is the hand free signal used for the telephone function To output the HFO signal set the R13 port as the HFO output by writing 1 to the CHFO register and fix the R13 register at 1 and the R13HIZ register at 0 Use the HF register for controlling the HFO signal output Refer to Section 4 14 Telephone Function for details of the signal and controlling method 36 EPSON 1C63558 TECHNICAL MANUAL CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Output Ports 4 5 5 I O memory of output ports Table 4 5 5 1 shows the I O addresses and control bits for the output po
180. ected in 1 bit units or 4 bit units depending on the terminal group Ports to be selected in 1 bit units P20 P21 P22 P23 Ports to be selected in 4 bit units 00 03 P10 P13 P30 P33 When without pull up during the input mode is selected take care that the floating status does not occur This option is effective even when I O ports are used for special output or input output of the serial interface 4 6 3 I O control registers and input output mode Input or output mode can be set for the I O ports by writing data into the corresponding I O control registers IOCxx To set the input mode write 0 to the I O control register When an I O port is set to input mode it becomes high impedance status and works as an input port However when the pull up explained in the following section has been set by software the input line is pulled up only during this input mode To set the output mode write 1 is to the I O control register When an I O port is set to output mode it works as an output port it outputs a high level VDD when the port output data is 1 and a low level Vss when the port output data is 0 If perform the read out in each mode when output mode the register value is read out and when input mode the port value is read out At initial reset the I O control registers set to 0 and the I O ports enter the input mode The I O control registers of the ports that are set as special output or input
181. ects the R13 terminal function When 1 is written HFO output When 0 is written General purpose DC output Reading Valid When using the R13 terminal for the output write 1 to this register Furthermore fix the R13 register at 1 and the R13HIZ register at 0 Refer to Section 4 14 Telephone Function for controlling the HFO output When using the R13 output port for a general purpose output fix this register at 0 At initial reset this register is set to 0 4 5 6 Programming notes 1 When using an output port 00 03 10 13 for special output fix the corresponding data register ROO RO3 R10 R13 at 1 and the high impedance control register ROOHIZ ROS3HIZ R10HIZ R13HIZ at 0 data output Be aware that the output terminal is fixed at a low Vss level the same as the DC output if 0 is written to the data registers when the special output has been selected Be aware that the output terminal shifts into high impedance status when 1 is written to the high impedance control register 2 A hazard may occur when the TOUT FOUT BZ or XBZ signal is turned ON and OFF 3 When foscs is selected for the FOUT signal frequency it is necessary to control the OSC3 oscillation circuit before output Refer to Section 4 3 Oscillation Circuit for the control and notes 40 EPSON 1C63558 TECHNICAL MANUAL CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION I O Ports 4 6 I O Ports 00 03 P1
182. ed to calculate the typical values dBm of CDon and CDorr when an external resistor RTR 10kQ Typ is connected in series with the pin and the RING pin 100k gt dBm CDorr 54 20log P x E 100k CDOon 51 20log Rin 100k RTR 100k dBm In addition the following expressions can be used to calculate the sensitivity of CDon CDorr when an external feedback resistor is used for the input amplifier mask option R5 R6 GAmp R2 R4 R5 R6 see Figure 4 15 2 2 Ri R2 51 20log PP x R dBm CDorr 54 20log 22 dBm 5 Rs 5 R5 Band pass filter gain Typ value Timing chart 50 40 30 20 1st RING 2nd RING g 10 Input 1011010 DATA 5 0 acu 40 RDET 20 FSKON tsuP 30 CDET tcpon gt 44 tcporr 40 FSKIN 101010 1 DATA 50 0 1000 2000 3000 4000 Frequency Hz 51 63558 TECHNICAL MANUAL EPSON 165 CHAPTER 7 ELECTRICAL CHARACTERISTICS 7 8 Telephone Function Characteristics Unless otherwise specified 3 0 Vss 0V fCLK 3 579545MHz Ta 20 to 70 C Item Symbol Condition Min Typ Max Unit Flash pause time 938 ms Mute hold
183. egister when SIF clock sync is selected OC11 0 Output Input P11 T O control register ESIF 0 General purpose register when SIF is selected OC10 0 Output Input PIOI O control register ESIF 0 General purpose register when SIF is selected PUL13 1 On Off P13 pull up control register General purpose register when SIF clock sync slave is selected PUL13 PUL12 PUL11 PUL10 PUL12 1 On Off P12 pull up control register General purpose register when SIF clock sync master is selected FF45H SCLK 1 pull up control register when SIF clock sync slave is selected PUL11 1 On Off P11 pull up control register ESIF 0 R W General purpose register when SIF is selected PUL10 1 On Off P10 pull up control register ESIF 0 SIN pull up control register when SIF is selected P13 2 High Low P13 T O port data P13 Pi2 P11 P10 General purpose register when SIF clock sync slave is selected XSRDY XSCLK SOUT SIN P12 32 High Low PI2I O port data General purpose register when SIF clock sync is selected 11 2 High Low P11 I O port data ESIF 0 RW General purpose register when SIF is selected P10 2 High Low P10 T O port data ESIF 0 General purpose register when SIF is selected 0C23 0 Output Input P23 T O control register EXLCDC 0 10 23 10622 10621 IOC20 General purpose register when FR output is selected FFA48H OC22 0 Output Input P22 I O control register EXLCDC 0 General purpose
184. elected by the mask options of P11 P12 and P13 Either complementary output or N channel open drain output can be selected as the output specification However when N channel open drain output is selected do not apply a voltage exceeding the power supply voltage to the terminal Furthermore the pull up resistor for the SIN terminal and the SCLK terminal for clock synchronous slave mode that are used as input terminals can be selected by the mask options of P10 and P12 When without pull up is selected take care that the floating status does not occur 4 11 3 Transfer modes There are four transfer modes for the serial interface and mode selection is made by setting the two bits of the mode selection registers SMD0 and SMD1 as shown in the table below Table 4 11 3 1 Transfer modes SMD1 SMD1S SMDO SMDOS Mode 1 1 8 bit asynchronous 1 0 7 bit asynchronous 0 1 Clock synchronous slave 0 0 Clock synchronous master Table 4 11 3 2 Terminal settings corresponding to each transfer mode Mode SIN SOUT SCLK SRDY Asynchronous 8 bit Input Output P12 Asynchronous 7 bit Input Output P12 Clock synchronous slave Input Output Input Output Clock synchronous master Input Output Output At initial reset transfer mode is set to clock synchronous master mode 78 EPSON 51 63558 TECHNICAL MANUAL CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Serial
185. en 1 is written SVD circuit ON When 0 is written SVD circuit OFF Reading Valid When the SVDON register is set to 1 source voltage detection is executed by the SVD circuit As soon as SVDON is reset to 0 the result is loaded to the SVDDT latch To obtain a stable detection result the SVD circuit must be ON for at least 100 psec At initial reset this register is set to 0 SVDDT SVD data FF05H D1 This is the result of supply voltage detection When 0 is read Supply voltage VDD Vss gt Criteria voltage When 1 is read Supply voltage VDD Vss lt Criteria voltage Writing Invalid The result of supply voltage detection at time of SVDON is set to 0 can be read from this latch At initial reset SVDDT is set to 0 110 EPSON 51 63558 TECHNICAL MANUAL CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION SVD Circuit 4 13 5 Programming notes 1 To obtain a stable detection result the SVD circuit must be ON for at least 100 sec So to obtain the SVD detection result follow the programming sequence below 1 Set SVDON to 1 2 Maintain for 100 psec minimum 3 Set SVDON to 0 4 Read SVDDT 2 The SVD circuit should normally be turned OFF because SVD operation increase current consump tion 51 63558 TECHNICAL MANUAL EPSON 111 CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Telephone Function 4 14 Telephone Function Tone Pulse Dialer 4 14 1 Configuration of tone pulse dialer 51
186. en OFF Reading Valid The FSK demodulator goes ON by writing 1 to FSKON At the same time the data input line of the serial interface 2 is switched from the P30 terminal to the FSK demodulator output The P3x terminals function as general I O port terminals regardless of the ESIFS setting When starting the FSK demodulator operation the OSC3 oscillation circuit must be turned ON and the CPU operating clock must be switched to the OSC3 clock The FSK demodulator goes OFF by writing 0 to FSKON The P3x terminals can be set to the I O terminals used for the serial interface 2 The FSK demodulator should be activated only when it is needed in order to decrease current consump tion At initial reset this register is set to 0 RDET Ring detection bit FF66H D1 Indicates the ring detection status When 1 is read Ring is detected When 0 is read Ring is not detected Writing Invalid A ring signal is being input when RDIT is 1 When the ring input is completed returns to 0 This bit is dedicated for reading so writing can not be done The bit valeu at initial reset depends on the input status of the RDIN terminal 142 EPSON 51 63558 TECHNICAL MANUAL CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION FSK Demodulator Carrier detection bit FF66H DO Indicates the carrier detection status When 1 is read Carrier is detected When 0 is read Carrier is not detected Writing In
187. ent counter mode Therefore be aware that the counter does not enter RUN STOP status if a clock is not input after setting the RUN STOP control register PTRUNO 3 Since the TOUT signal is generated asynchronously from the PTOUT register a hazard within 1 2 cycle is generated when the signal is turned ON and OFF by setting the register 4 When the OSC3 oscillation clock is selected for the clock source it is necessary to turn the OSC3 oscillation ON prior to using the programmable timer However the OSC3 oscillation circuit requires a time at least 5 msec from turning the circuit ON until the oscillation stabilizes Therefore allow an adequate interval from turning the OSC3 oscillation circuit ON to starting the programmable timer Refer to Section 4 3 Oscillation Circuit for the control and notes of the OSC3 oscillation circuit At initial reset the OSC3 oscillation circuit is set in the OFF state 5 After an interrupt occurs the same interrupt will occur again if the interrupt enabled state I flag 1 is set or the RETI instruction is executed unless the interrupt factor flag is reset Therefore be sure to reset write 1 to the interrupt factor flag in the interrupt service routine before shifting to the interrupt enabled state 76 EPSON 51 63558 TECHNICAL MANUAL CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Serial Interface 4 11 Serial Interface 4 11 1 Configuration of serial interface The 51 63558 incorpo
188. equently the output terminal goes high VDD When using the output port 00 03 10 13 as the special output port fix the data register 00 03 10 13 at 1 and the high impedance control register ROOHIZ ROSHIZ R10HIZ R13HIZ at 0 data output The respective signal should be turned ON and OFF using the special output control register 34 EPSON 1C63558 TECHNICAL MANUAL CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Output Ports Note Be aware that the output terminal is fixed at a low Vss level the same as the DC output if 0 is written to the ROO RO3 and R10 R13 registers when the special output has been selected Be aware that the output terminal shifts into high impedance status when 1 is written to the high impedance control register ROOHIZ ROSHIZ R10HIZ R13HIZ A hazard may occur when the special output signal is turned ON and OFF by software XBZ R00 The 00 terminal can output an XBZ signal The XBZ signal is the buzzer inverted signal that is output from the sound generator and can be used to drive a piezoelectric buzzer with the BZ signal To output the XBZ signal set the R00 port as the XBZ output by writing 1 to the XBZOUT register and fix the ROO register at 1 and the ROOHIZ register at 0 Use the BZE register for controlling ON OFF the XBZ signal output Refer to Section 4 12 Sound Generator for details of the buzzer signal and controlling method BZ R01 Th
189. er and the receive operation also continues Furthermore when the timing for writing 1 to RXTRG and the timing for the received data transfer to the receive data buffer overlap it will be recognized as an overrun error 51 63558 TECHNICAL MANUAL EPSON 89 CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Serial Interface Timing chart Figure 4 11 7 4 show the asynchronous transfer timing chart TXEN TXTRG RD TXTRG WR I Sumpling clock SOUT 7 In 8 bit mode Non parity Interrupt 4 a Transmit timing RXEN RXTRG RD LJ RXTRG WR Sumpling 1 2 3 4 5 6 07 In 8 bit mode Non parity TRXD DO D1 D2 D3 D4 D5 D6 D7 DO0 D1 D2 D3 D4 D5 D6 D7 1st data 2st data OER control signal OER Interrupt A A 4 b Receive timing Fig 4 11 7 4 Timing chart asynchronous transfer 4 11 8 Interrupt function This serial interface includes a function that generates the below indicated three types of interrupts Transmitting complete interrupt Receiving complete interrupt Error interrupt The interrupt factor flag ISxx and the inter
190. er delivery compatible with ITU T V 23 Bell 202 Figures 4 15 1 1 and 4 15 1 2 show the block diagram of the FSK demodulator and the configuration of FSK core block respectively EIRDET Interrupt mask register Ring detection RDETCP interrupt IRDET RDET comparison register Interrupt factor flag CDETCP Carrier detection ICDET C CDET comparison register interrupt Interrupt factor flag EIRDET i Interrupt mask register FSK core F FOSC3 BUR OSC3 oscillation circuit 4 AVDD m AVss z RDET 5 RDET d BBE i Lo RING Ring detection bit CDET CDET BPOUT d Carrier detection bit CDIN RDIN FSKON FSKON PWDN lt FSK control register MUX VREF nr PEE FSKIN A OUT TRXD7S TRXDOS i B i Transmit receive data register P3 P30 Serial interface 2 SIF 2 enable ESIES SIF 2 enable register Fig 4 15 1 1 FSK demodulator block diagram 136 EPSON 51 63558 TECHNICAL MANUAL CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION FSK Demodulator
191. eration The interrupt is generated at the falling edge Fig 4 15 3 1 Relationship between the detection bit and the comparison register 1C63558 TECHNICAL MANUAL EPSON 139 CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION FSK Demodulator Since the value of both RDIT and CDET is the same as the comparison register an interrupt does not occur at 1 When a ring is input the ring detection interrupt will be generated since RDIT changes 0 to 1 and no longer matches the contents of RDETCP at 2 To generate an interrupt when a ring input is completed write 1 to RDETCP Copying the bit to RDETCP changes the interrupt timing so that the interrupt will occur when the RDET changes from the current status In Figure 4 15 3 1 the RDET bit has been copied to RDETCP immediately after 2 so an interrupt occurs again when RDET returns from 1 to 0 As the same as ring detection interrupt the carrier detection interrupt will be generated at 4 and 5 since no matching occurs between CDET and CDETCP Figure 4 15 3 2 shows the timing chart for the interrupt generation example for Bellcore 1st RING 2nd RING Input WA 41101010 1 DATA RDET FSKON CDET FSKIN 101010 1 DATA RDETCP CDETCP Interrupt 4 4 4 4 2 3 4 5 Step of Figure 4 15 3 1 Fig 4 15 3 2 Timing chart for interrupt generation
192. erial interface When performing clock synchronous transfer the following initial settings must be made 1 Setting of transmitting receiving disable To set the serial interface into a status in which both transmitting and receiving are disabled 0 must be written to both the transmit enable register TXEN and the receive enable register RXEN Fix these two registers to a disable status until data transfer actually begins 2 Port selection Because serial interface input output ports SIN SOUT SCLK and SRDY are set as I O port terminals 10 13 at initial reset 1 must be written to the serial interface enable register ESIF in order to set these terminals for serial interface use 3 Setting of transfer mode Select the clock synchronous mode by writing the data as indicated below to the two bits of the mode selection registers S MD0 and SMD1 Master mode SMDO 0 SMD1 0 Slave mode SMD0 1 SMD1 0 82 EPSON 51 63558 TECHNICAL MANUAL CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Serial Interface 4 Clock source selection In the master mode select the synchronous clock source by writing data to the two bits of the clock source selection registers SCSO and SCS1 See Table 4 11 4 1 This selection is not necessary in the slave mode The parity enable register EPR is also assigned to this address however since parity is not neces sary in the clock synchronous mode parity check will not take place regardless of
193. es 1 It is necessary to turn the OSC3 oscillation on prior to a dialing operation in tone mode because the tone mode uses the OSC3 3 58 MHz clock However it increases current consumption Therefore turn the OSC3 oscillation off after finishing the dialling operation in tone mode 2 Do not write 0 0000B to the IDP FTS PTS or TCD in pulse mode registers because it may cause a malfunction 3 The pause function control bit PAUSE FF14H D1 and the flash function control bit FLASH FF14He D0 are write only so software cannot control these functions on address FF14H using an ALU instruction AND OR Furthermore be aware that the pause function or the flash function is canceled when 0 is written to the PAUSE bit FF14HeD1 or the FLASH bit D0 4 After an interrupt occurs the same interrupt will occur again if the interrupt enabled state I flag 1 is set or the RETI instruction is executed unless the interrupt factor flag is reset Therefore be sure to reset write 1 to the interrupt factor flag in the interrupt service routine before shifting to the interrupt enabled state 1C63558 TECHNICAL MANUAL EPSON 135 CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION FSK Demodulator 4 15 FSK Demodulator 4 15 1 Configuration of FSK demodulator The 51 63558 has a built in FSK Frequency Shift Keying demodulator that interfaces to various calling information delivery services such as calling numb
194. es invalid At initial reset these registers are set to 0 EVCNT Timer 0 counter mode selection register FFCOH D2 Selects a counter mode for timer 0 When 1 is written Event counter mode When 0 is written Timer mode Reading Valid The counter mode for timer 0 is selected from either the event counter mode or timer mode When 1 is written to the EVCNT register the event counter mode is selected and when 0 is written the timer mode is selected At initial reset this register is set to 0 72 EPSON 51 63558 TECHNICAL MANUAL CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Programmable Timer FCSEL Timer 0 function selection register FFCOH D1 Selects whether the noise rejector of the clock input circuit will be used or not in the event counter mode When 1 is written With noise rejecter When 0 is written Without noise rejecter Reading Valid When 1 is written to the FCSEL register the noise rejecter is used and counting is done by an external clock K13 with 0 98 msec or more pulse width The noise rejecter allows the counter to input the clock at the second falling edge of the internal 2 048 Hz signal after changing the input level of the K13 input port terminal Consequently the pulse width of noise that can reliably be rejected is 0 48 msec or less fosci 32 768 kHz When 0 is written to the FCSEL register the noise rejector is not used and the counting is done directly by an external cl
195. factor flag FFF6H D3 These flags indicate the status of the clock timer interrupt When 1 is read Interrupt has occurred When 0 is read Interrupt has not occurred When 1 is written Flag is reset When 0 is written Invalid The interrupt factor flags ITO IT1 IT2 IT3 correspond to the clock timer interrupts of the respective frequencies 32 Hz 8 Hz 2 Hz 1 Hz The software can judge from these flags whether there is a clock timer interrupt However even if the interrupt is masked the flags are set to 1 at the falling edge of the signal These flags are reset to 0 by writing 1 to them After an interrupt occurs the same interrupt will occur again if the interrupt enabled state I flag 1 is set or the RETI instruction is executed unless the interrupt factor flag is reset Therefore be sure to reset write 1 to the interrupt factor flag in the interrupt service routine before shifting to the interrupt enabled state At initial reset these flags are set to 0 4 8 5 Programming notes 1 Be sure to read timer data in the order of low order data TM0 TM3 then high order data TM4 7 2 After interrupt occurs the same interrupt will occur again if the interrupt enabled state I flag 1 is set or the RETI instruction is executed unless the interrupt factor flag is reset Therefore be sure to reset write 1 to the interrupt factor flag in the interrupt service routine before shifting t
196. flag 1 an interrupt will be generated to the CPU When the interrupt mask register EISER has been set to 0 and interrupt has been disabled an interrupt is not generated to the CPU Even in this case the interrupt factor flag ISER is set to 1 The interrupt factor flag ISER is reset to 0 by writing 1 Since all three types of errors result in the same interrupt factor you should identify the error that has been generated by the error flags PER parity error OER overrun error and FER framing error 1C63558 TECHNICAL MANUAL EPSON 91 CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Serial Interface 4 11 9 I O memory of serial interface Tables 4 11 9 1 a and b show the serial interface control bits and their addresses Table 4 11 9 1 a Serial interface control bits Register Address Comment D3 D2 D1 DO Name Init 1 0 PUL13 1 On Off P13 pull up control register General purpose register when SIF clock sync slave is selected PUL13 PUL12 PUL11 PUL10 PUL12 1 On Off P12 pull up control register General purpose register when SIF clock sync master is selected FF45H SCLK 1 pull up control when SIF clock sync slave is selected PUL11 1 On Off P11 pull up control register ESIF 0 General purpose register when SIF is selected PUL10 1 On Off P10 pull up control register ESIF 0 SI
197. for the synchronous clock to be input from the SCLK terminal TXTRG 1 The transmitting data of the shift register shifts one bit at a time at each falling edge of the synchronous clock and is output from the SOUT terminal When 1 the final bit MSB is output the SOUT terminal is Yes maintained at that level until the next transmitting No be gins Transmit complete Yes The transmitting complete interrupt factor flag ISTR is set to 1 at the point where the data transmitting of the shift register is completed When interrupt has been enabled a transmitting End complete interrupt is generated at this point Set the following transmitting data using this interrupt N In case of master mode Yes TXEN lt 0 Fig 4 11 6 2 Transmit procedure in clock synchronous mode 6 Repeat steps 3 to 5 for the number of bytes of transmitting data and then set the transmit disable status by writing 0 to the transmit enable register TXEN when the transmitting is completed 1C63558 TECHNICAL MANUAL EPSON 83 CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Serial Interface Data receive procedure The control procedure and operation during receiving is as follows Data receiving 1 Write 0 the receive enable register RXEN and transmit enable register TXEN to reset the serial interface 2 Write 1 in the receive enable register RXEN to set i
198. g Valid When using the ROO terminal for the XBZ output write 1 to this register Furthermore fix the ROO register at 1 and the ROOHIZ register at 0 At initial reset this register is set to 0 BZOUT R01 output selection register FF65H D1 Selects the R01 terminal function When 1 is written BZ output When 0 is written General purpose DC output Reading Valid When using the 01 terminal for the BZ output write 1 to this register Furthermore fix the 01 register at 1 and the RO1HIZ register at 0 At initial reset this register is set to 0 BZE BZ output control register FF6CH DO Controls the buzzer signal output When 1 is written Buzzer output ON When 0 is written Buzzer output OFF Reading Valid When 1 is written to BZE the BZ signal is output from the BZ R01 terminal and the XBZ signal is output from the XBZ ROO terminal When 0 is written the buzzer signals go OFF At initial reset this register is set to 0 BZFQ0 BZFQ2 Buzzer frequency selection register FF6EH D0 D2 Selects the buzzer signal frequency Table 4 12 7 2 Buzzer signal frequency setting BZFQ2 BZFQ1 BZFQO Buzzer frequency Hz 0 0 0 4096 0 0 0 1 3276 8 0 1 0 2730 7 0 1 1 2340 6 1 0 0 2048 0 1 0 1 1638 4 1 1 0 1365 3 1 1 1 1170 3 Select the buzzer frequency from among the above 8 types that have divided the oscillation clock At initial reset this register is set to 0 106
199. g et HSON 1 Off hook 5 y 5 Dial number 5 a acca EUR S 3 Interrupt gt Yes Reset ID Reset interrupt factor flag ID to 0 for next operation Fig 4 14 3 2 Flow chart of dialing pulse transmission In the setting step 1000B is written to address FF10H to set pulse DP mode the make ratio 40 60 and the dialing rate 10 pps Then data is written to IDP FF15H PTS FF11H and FTS FF12H to set an inter digit pause time pause time and flash time These settings are not necessary when using the initial set values of IDP PTS and FTS In the executing step 1 is written to HSON FF18HeD3 to set off hook This makes the DP terminal go to a High VDD level and connects the telephone line Then 0101B dialling number 5 is written to TCD FF17H to start the dialing operation The DP terminal outputs 5 pulses according to the condition set At the same time the XTMUTE and XRMUTE signals become active if the R10 and R11 terminals have been set as those signal output ports In the actual application this step should include the processing for fetching the hook switch status and for push button inputs When a series of pulses has been transmitted an interrupt occurs The next digit process can be started after resetting writing 1 to the interrupt factor flag ID 51 63558 TECHNICAL MANUAL EPSON 115 CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Telephone Function 4 14 4 Tone mo
200. has been set to 1 and the RO2HIZ register has been set to 0 the TOUT signal is output from the R02 terminal When 0 is written the R02 termi nal goes high VDD When using the R02 output port for general purpose output fix this register at 0 At initial reset this register is set to 0 FOUTE FOUT output control register FFO6H D3 Controls the FOUT output When 1 is written FOUT output ON When 0 is written FOUT output OFF Reading Valid By writing 1 to the FOUTE register when the R03 register has been set to 1 and the RO3HIZ register has been set to 0 an FOUT signal is output from the R03 terminal When 0 is written the R03 terminal goes high VDD When using the 03 output port for general purpose output fix this register at 0 At initial reset this register is set to 0 0 FOFQ1 FOUT frequency selection register FFO6H DO D1 Selects a frequency of the FOUT signal Table 4 5 5 2 FOUT clock frequency FOFQ1 FOFQO Clock frequency 1 1 foc 1 0 fosci 0 1 fosci x 1 8 0 0 fosci x 1 64 At initial reset this register is set to 0 CTMO R10 output selection register FF13H DO Selects the R10 terminal function When 1 is written XTMUTE output When 0 is written General purpose DC output Reading Valid When using the R10 terminal for the XTMUTE output write 1 to this register Furthermore fix the R10 register at 1 and the R10HIZ register at
201. he I O ports become invalid 1C63558 TECHNICAL MANUAL EPSON 77 CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Serial Interface Table 4 11 1 1 Configuration of input output terminals Terminal When serial interface is selected P10 SIN Pil SOUT P12 SCLK P13 SRDY The terminals used may vary depending on the transfer mode SIN and SOUT are serial data input and output terminals which function identically in clock synchronous system and asynchronous system SCLK is exclusively for use with clock synchronous system and func tions as a synchronous clock input output terminal SRDY is exclusively for use in clock synchronous slave mode and functions as a send receive ready signal output terminal When asynchronous system is selected since SCLK and SRDY are superfluous the I O port terminals P12 and P13 can be used as I O ports In the same way when clock synchronous master mode is selected since SRDY is superfluous the I O port terminal P13 can be used as I O port 4 11 2 Mask option Since the input output terminals of the serial interface is shared with the I O ports P10 P13 the mask option that selects the output specification for the I O port is also applied to the serial interface The output specification of the terminals SOUT SCLK for clock synchronous master mode and SRDY for clock synchronous slave mode that are used as output in the input output port of the serial interface is respectively s
202. he counter SWD0 SWD3 for the input clock In count up every 1 10 sec and generated 1 Hz signal Figure 4 9 2 1 shows the count up pattern of the stopwatch timer SWD4 7 count up pattern SWD4 7 count value 0 1 2 3 4 5 6 7 8 9 0 Counting time esc 26 26 25 25 26 26 25 25 26 26 Tie s 256 256 256 256 256 256 256 256 256 256 signal generation 26 25 4 1 256 x6 256 x sec SWDO 3 count up pattern 1 1 SWD0 3 count value 0 1 2 3 4 5 6 7 8 9 0 Approximate Counting time sec 3 2 3 2 3 2 3 2 3 2 10 Hz 256 256 256 256 256 256 256 256 256 256 signal 25 generation 25 ra SWDO 3 count up pattern2 4 SWDO 3 count value 0 1 2 3 4 5 6 7 8 9 0 Approximate Counting time sec 3 3 3 2 3 2 3 2 3 2 10 Hz 256 256 256 256 256 256 256 256 256 256 signal 26 generation 256 596 Fig 4 9 2 1 Count up pattern of stopwatch timer 1C63558 TECHNICAL MANUAL EPSON 61 CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Stopwatch Timer SWD0 SWD3 generates an approximated 10 Hz signal from the basic 256 Hz signal fosci dividing clock The count up intervals are 2 256 sec and 3 256 sec so that finally two patterns are generated 25 256 sec and 26 256 sec intervals Consequently these patterns do not amount to an accurate 1 100 sec SWD4 SWD7 counts the approximated
203. hen 0 is written I O port Reading Valid 1C63558 TECHNICAL MANUAL EPSON 93 CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Serial Interface ESIF is the serial interface 1 the ESIFS is the serial interface 2 enable registers and 10 13 P30 P33 terminals become serial input output terminals SIN SOUT SCLK SRDY when 1 is written and they become I O port terminals when 0 is written Also see Table 4 11 3 2 for the terminal settings according to the transfer modes At initial reset this register is set to 0 Note After setting ESIF to 1 wait at least 10 usec before starting actual data transfer since a hazard may be generated from the P12 SCLK terminal when ESIF is set to 1 Also setting ESIFS to 1 may cause a hazard to be generated from the P32 SCLK terminal so a 10 usec or more interval is also needed here PUL10 Serial interface 1 SIN pull up control register FF45H DO PUL12 Serial interface 1 SCLK pull up control register FF45H D2 PUL30 Serial interface 2 SIN pull up control register FFADH DO PUL32 Serial interface 2 SCLK pull up control register FFADH D2 Sets the pull up of the SIN terminal and the SCLK terminals in the slave mode When 1 is written Pull up ON When 0 is written Pull up OFF Reading Valid Sets the pull up resistor built into the SIN P10 P30 and SCLK P12 P32 terminals to ON or OFF Pull up resistor is only built in the port sele
204. hen 1 is written ON When 0 is written OFF Reading Valid Writing 1 into the ENON causes an envelope to be added during buzzer signal output When a 0 has been written an envelope is not added At initial reset this register is set to 0 ENRTM Envelope releasing time selection register FF6CH D3 Selects the envelope releasing time that is added to the buzzer signal When 1 is written 1 0 sec 125 msec x 7 875 msec When 0 is written 0 5 sec 62 5 msec x 7 437 5 msec Reading Valid The releasing time of the digital envelope is determined by the time for converting the duty ratio When 1 has been written in ENRTM it becomes 125 msec 8 Hz units and when 0 has been written it becomes 62 5 msec 16 Hz units At initial reset this register is set to 0 1C63558 TECHNICAL MANUAL EPSON 107 CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Sound Generator SHTPW One shot buzzer pulse width setting register FF6DH DO Selects the output time of the one shot buzzer When 1 is written 125 msec When 0 is written 31 25 msec Reading Valid Writing 1 into SHTPW causes the one short output time to be set at 125 msec and writing 0 causes it to be set to 31 25 msec It does not affect normal buzzer output At initial reset this register is set to 0 BZSHT One shot buzzer trigger status FF6DH D1 Controls the one shot buzzer output When writing When 1 is written Trigger When 0 is wr
205. how they are set 5 Clock source control When the master mode is selected and programmable timer for the clock source is selected set transfer rate on the programmable timer side See 4 10 Programmable Timer When the divided signal of OSC3 oscillation circuit is selected for the clock source be sure that the OSC3 oscillation circuit is turned ON prior to commencing data transfer See 4 3 Oscillation Circuit Note that the frequency of the serial interface clock is limited to a maximum of 1 MHz Data transmit procedure The control procedure and operation during transmitting is as follows 1 Write 0 in the transmit enable register TXEN and the receive enable register RXEN to reset the serial interface 2 Write 1 in the transmit enable register TXEN to set into the transmitting enable status 3 Write the transmitting data into TRXDO TRXD7 4 In case of the master mode confirm the receive Data transmitting ready status on the slave side external serial input output device if necessary Wait until it reaches the TXEN lt 0 RXEN lt 0 receive ready status 5 Write 1 in the transmit control bit TXTRG and start transmitting TXEN 1 Set transmitting data to TRXDO TRXD7 In the master mode this control causes the synchro nous clock to change to enable and to be provided to the shift register for transmitting and output from the SCLK terminal In the slave mode it waits
206. i 125 4 msec t02 07 62 5 msec 12 17 125 msec Fig 4 12 5 1 Timing chart for digital envelope 51 63558 TECHNICAL MANUAL EPSON 103 CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Sound Generator 4 12 6 One shot output The sound generator has a one shot output function for outputting a short duration buzzer signal for key operation sounds and similar effects Either 125 msec or 31 25 msec can be selected by SHTPW register for one shot buzzer signal output time The output of the one shot buzzer is controlled by writing 1 into the one shot buzzer trigger BZSHT When this trigger has been assigned a buzzer signal in synchronization with the internal 256 Hz signal is output from the BZ and XBZ terminals Thereafter when the set time has elapsed a buzzer signal in synchronization with the 256 Hz signal goes off in the same manner as for the start of output The BZSHT also permits reading When BZSHT is 1 the one shot output circuit is in operation during one shot output and when it is 0 it shows that the circuit is in the ready outputtable status In addition it can also terminate one shot output prior to the elapsing of the set time This is done by writing a 1 into the one shot buzzer stop BZSTP In this case as well the buzzer signal goes OFF in synchronization with the 256 Hz signal When 1 is written to BZSHT again during a one shot output a new one shot output for 125 msec or 31 25 msec starts from that point i
207. ing Road Caohejing Shanghai CHINA Phone 21 6485 5552 Fax 21 6485 0775 EPSON HONG KONG LTD 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Phone 852 2585 4600 Fax 852 2827 4346 Telex 65542 EPSCO HX EPSON TAIWAN TECHNOLOGY amp TRADING LTD 10F No 287 Nanking East Road Sec 3 Taipei Phone 02 2717 7360 Telex 24444 EPSONTB Fax 02 2712 9164 HSINCHU OFFICE 13F 3 No 295 Kuang Fu Road Sec 2 HsinChu 300 Phone 03 573 9900 Fax 03 573 9169 EPSON SINGAPORE PTE LTD No 1 Temasek Avenue 36 00 Millenia Tower SINGAPORE 039192 Phone 65 337 7911 Fax 65 334 2716 SEIKO EPSON CORPORATION KOREA OFFICE 50F KLI 63 Bldg 60 Yoido dong Youngdeungpo Ku Seoul 150 763 KOREA Phone 02 784 6027 Fax 02 767 3677 SEIKO EPSON CORPORATION ELECTRONIC DEVICES MARKETING DIVISION Electronic Device Marketing Department IC Marketing amp Engineering Group 421 8 Hino Hino shi Tokyo 191 8501 JAPAN Phone 81 0 42 587 5816 Fax 81 0 42 587 5624 ED International Marketing Department Europe amp U S A 421 8 Hino Hino shi Tokyo 191 8501 JAPAN Phone 81 0 42 587 5812 Fax 81 0 42 587 5564 ED International Marketing Department Asia 421 8 Hino Hino shi Tokyo 191 8501 JAPAN Phone 81 0 42 587 5814 Fax 81 0 42 587 5110 In pursuit of Saving Technology Epson electronic devices Our lineup of semiconductors liquid crystal displays and quartz devices assists in c
208. ing has been done with the stop bit set at 0 the serial interface judges the synchronization to be off and a framing error is generated When this error is gener ated the framing error flag FER and the error interrupt factor flag ISER are set to 1 When interrupt has been enabled an error interrupt is generated at this point The FER flag is reset to 0 by writing 1 Even when this error has been generated the received data for it is loaded into the receive data buffer and the receive operation also continues However even when it does not become a framing error with the following data receipt such data cannot be assured Even when this error has been generated the received data corresponding to the error is trans ferred in the receive data buffer and the receive operation also continues However even when it does not become a framing error with the following data receiving such data cannot be assured 3 Overrun error When the next data is received before 1 is written to RXTRG an overrun error will be generated because the previous receive data will be overwritten When this error is generated the overrun error flag OER and the error interrupt factor flag ISER are set to 1 When interrupt has been enabled an error interrupt is generated at this point The OER flag is reset to 0 by writing 1 into it Even when this error has been generated the received data corresponding to the error is trans ferred in the receive data buff
209. ing the special outputs select the special output function using the EXLCDC register The data registers I O control registers and pull up control registers of the ports set in the special output can be used as general purpose registers that do not affect the output When 1 is written to the EXLCDC register P22 is set to the CL output port and P23 is set to the FR output port The CL and FR signals are LCD synchronous signal CL and LCD flame signal FR for externally expanded LCD driver and are output from the P22 terminal and P23 terminal when the functions are switched by the EXLCDC register The following tables show the frequencies of the CL and FR signals Table 4 6 5 1 CL signal frequency OSC1 oscillation frequency 32 768 kHz When 1 8 duty is selected 512 Hz When 1 16 duty is selected 1 024 Hz When 1 17 duty is selected 1 024 Hz Table 4 6 5 2 FR signal frequency OSC1 oscillation frequency 32 768 kHz When 1 8 duty is selected 32 Hz When 1 16 duty is selected 32 Hz When 1 17 duty is selected 30 12 Hz Refer to Section 4 7 LCD Driver for control of the LCD drive duty Note A hazard may occur when the CL signal or FR signal is turned ON or OFF when the port function is switched Figure 4 6 5 1 shows the output waveforms of CL and FR signals CL output P22 terminal
210. ion can select whether or not to use with the mask option 4 13 3 SVD operation The SVD circuit compares the criteria voltage set by software and the supply voltage VDD terminal Vss terminal or the external voltage SVD terminal Vss terminal and sets its results into the SVDDT latch By reading the data of this SVDDT latch it can be determined by means of software whether the supply voltage is normal or has dropped The criteria voltage can be set for the 12 types shown in Table 4 13 3 1 by the SVDS3 SVDS0 registers When 0 is written to the SVDS3 SVDSO register the supply voltage detection voltage is set to 2 20 V However when External voltage detection is selected by mask option the SVD circuit does not compare the supply voltage terminal Vss terminal but compares between the external voltage SVD termi nal Vss terminal input from the SVD terminal and 1 05 V Table 4 13 3 1 Criteria voltage setting SVDS3 SVDS2 SVDS1 SVDSO rm SVDS3 SVDS2 SVDS1 SVDSO can y 0 1 1 1 2 50 1 1 1 1 3 30 0 1 1 0 2 40 1 1 1 0 3 20 0 1 0 1 2 30 1 1 0 1 310 0 1 0 0 2 20 1 1 0 0 3 00 0 0 1 1 2 20 1 0 1 1 2 90 0 0 1 0 2 20 1 0 1 0 2 80 0 0 0 1 2 20 1 0 0 1 270 0 0 0 0 2 20 1 05 1 0 0 0 2 60 51 63558 TECHNICAL MANUAL EPSON 109 CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION SVD Circuit When the SVDON register is set to 1 source voltage or external voltage detection by the SVD circuit is executed
211. is register is set to 0 128 EPSON 1C63558 TECHNICAL MANUAL CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Telephone Function CHFO R13 output selection register FF13H D3 Selects the R13 terminal function When 1 is written HFO output When 0 is written General purpose DC output Reading Valid When using the R13 terminal for the HFO output write 1 to this register Furthermore fix the R13 register at 1 and the R13HIZ register at 0 The output is controlled by the HF register 14 At initial reset this register is set to 0 OSCC OSC3 oscillation control FFOOH D2 Controls the OSC3 oscillation When 1 is written OSC3 oscillation ON When 0 is written OSC3 oscillation OFF Reading Valid When it is necessary to activate the DTMF generator or to operate the CPU at high speed set OSCC to 1 At other times set it to 0 to reduce current consumption At initial reset this register is set to 0 TPS Tone Pulse mode selection FF10H D3 Selects a dialing mode When 1 is written Pulse mode When 0 is written Tone mode Reading Valid When 1 is witten to the TPS register pulse mode outputs dial pulses is selected When 0 is written tone mode outputs tone signals is selected At initial reset this register is set to 0 MB Make Break ratio selection FF10H D1 Selects a make ratio for pulse mode When 1 is written 33 3 66 6 When 0 is written 40 0
212. isters so that interrupt occurs As already explained the condition for the interrupt to occur is the change in the port data and contents of the input comparison registers from matching to no matching Hence in 4 when the no matching status changes to another no matching status an interrupt does not occur Further terminals that have been masked for interrupt do not affect the conditions for interrupt generation 4 4 3 Mask option Internal pull up resistor be selected for each of the eight bits of the input ports 00 03 10 13 with the input port mask option When Gate direct is selected take care that the floating status does not occur for the input Select With pull up resistor for input ports that are not being used 51 63558 TECHNICAL MANUAL EPSON 29 CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Input Ports 4 4 4 I O memory of input ports Table 4 4 4 1 shows the I O addresses and the control bits for the input ports Table 4 4 4 1 Control bits of input ports Register Address D3 D2 D1 DO Init Enable Disable Enable Disable Enable Disable Enable Disable K00 K03 interrupt selection register High Low xs 00 03 input port data High Low 1 u fq 1 a E K00 K093 input comparison register 1 d i 0 Enable Disable K10 K13 interrupt selection register 0 Enable
213. itten No operation Writing 1 into BZSHT causes the one short output circuit to operate and a buzzer signal to be output This output is automatically turned OFF after the time set by SHTPW has elapsed The one shot output is only valid when the normal buzzer output is OFF BZE 0 and will be invalid when the normal buzzer output is ON BZE 1 When a re trigger is assigned during a one shot output the one shot output time set with SHTPW is measured again from that point time extension When reading When 1 is read BUSY When 0 is read READY During reading BZSHT shows the operation status of the one shot output circuit During one shot output BZSHT becomes 1 and the output goes OFF it shifts to 0 At initial reset this bit is set to 0 BZSTP One shot buzzer stop FF6DH D2 Stops the one shot buzzer output When 1 is written Stop When 0 is written No operation Reading Always 0 Writing 1 into BZSTP permits the one shot buzzer output to be turned OFF prior to the elapsing of the time set by SHTPW Writing 0 is invalid and writing 1 is also invalid except during one shot output This bit is dedicated for writing and is always 0 for reading 4 12 8 Programming notes 1 Since the BZ and XBZ signals are generated asynchronous to the BZE register hazards may be pro duced when the signal goes ON OFF due to the setting of the BZE register 2 The one shot output is only valid when the normal buzze
214. itten the XTMUTE signal returns to High level The R12 terminal can be used to output the HDO signal that indicates hold status To use the HDO signal set the R12 port for the HDO output by writing 1 to the CHDO register FF13He D2 The R12 terminal will output the HDO signal by controlling the HOLD register In this case the output port data register R12 must be fixed at 1 and the high impedance control register at 0 Note that the HDO signal will be fixed at Low level if the R12 register is set to 0 Figure 4 14 8 1 shows a timing chart of the hold line function HSON 0 FF18H D3 Data bus Hold ON Hold OFF Write to HOLD FF14H D2 XRMUTE R11 nan XTMUTE R10 i HDO R12 0 Fig 4 14 8 1 Hold line execution timing chart 51 63558 TECHNICAL MANUAL EPSON 125 CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Telephone Function 4 14 9 Interrupt The dialer has three types of interrupt generation functions 1 Dialing interrupt Tone mode In the tone mode 94 msec of an inter digit pause is made after a tone signal mim 94 msec can be prolonged by the CTO register is output completely A dialing interrupt occurs immediately follow ing the inter digit pause See the timing chart in Figure 4 14 4 2 Pulse mode In the pulse mode the inter digit pause set by the IDP register is made after a dial pulse digit is output completely A dialing interrupt occurs immedi
215. ivided clock output from the prescaler Timer data 128 16 Hz and 8 1 Hz be read out by the software Figure 4 8 1 1 is the block diagram for the clock timer Data bus Clock timer OSC1 256Hz pO _ oscillation circuit H Divider J39 128 Hz 16 Hz gt 8Hz 1Hz fosc1 kaon oss 22 Hz 8 Hz 2 Hz 1 Hz Clock timer reset signal Interrupt gt Interrupt control request Clock timer RUN STOP signal Fig 4 8 1 1 Block diagram for the clock timer Ordinarily this clock timer is used for all types of timing functions such as clocks 4 8 2 Data reading and hold function The 8 bits timer data are allocated to the address FF79H and FF7AH lt FF79H gt TMO 128 Hz D1 TM1 64Hz D2 TM2 32Hz D3 TM3 16 Hz lt FF7AH gt DO TM4 8 Hz D1 5 4 Hz D2 TM6 2 Hz 03 TM7 1 Hz Since the clock timer data has been allocated to two addresses a carry is generated from the low order data within the count TM0 TMG 128 16 Hz to the high order data TM4 TMT7 8 1 Hz When this carry is generated between the reading of the low order data and the high order data a content combining the two does not become the correct value the low order data is read as FFH and the high order data becomes the value that is counted up 1 from that point The high order data hold function in the S1C63558 is designed to operate to avoid this This function
216. k pointer for 4 bit data SP2 and the stack pointer for 16 bit data SP1 16 bit data are accessed in stack handling by SP1 therefore this stack area should be allocated to the area where 4 bit 16 bit access is possible 0100H to 01 The stack pointers SP1 and SP2 change cyclically within their respective range the range of SP1 is 0000H to 03FFH and the range of SP2 is 0000H to OOFFH Therefore pay attention to the SP1 value because it may be set to 0200H or more exceeding the 4 bit 16 bit accessible range in the S1C63558 or it may be set to OOFFH or less Memory accesses except for stack operations by SP1 are 4 bit data access After initial reset all the interrupts including NMI are masked until both the stack pointers SP1 and SP2 are set by software Further if either SP1 or SP2 is re set when both are set already the interrupts including NMI are masked again until the other is re set Therefore the settings of SP1 and SP2 must be done as a pair 12 EPSON 1C63558 TECHNICAL MANUAL CHAPTER 3 CPU ROM RAM 3 Subroutine calls use 4 words for PC evacuation in the stack area for 16 bit data SP1 Interrupts use 4 words for PC evacuation in the stack area for 16 bit data SP1 and 1 word for F register evacua tion in the stack area for 4 bit data 0000H 4 4 bit access area O0FFH SP2 stack area 0100 4 4 16 bit access area O1FFH SP1 stack area y 0200H L 4bit access area Data area
217. l resistors resistor of approximately 500 is recommended for RIN and Rr The gain can be found with the following formula 138 5 51 63558 TECHNICAL MANUAL CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION FSK Demodulator 4 15 3 Ring carrier detection and interrupt The FSK block has a ring detection circuit and a carrier detection circuit built in When a ring signal is input the ring detection circuit sets the bit FF66H D1 to 1 while the signal is being input In the same way when a carrier is input the carrier detection circuit sets the CDET bit FF66H D0 to 1 Further the interrupt can be generated at the rising edge or falling edge of these detection signals The edge selection can be made by the comparison register RDETCP 67 D1 comparison register CDETCP FF67H 00 When the register is set to 0 the interrupt is generated at the rising edge When set to 1 the interrupt is generated at the falling edge When the interrupt condition is met the corresponding interrupt factor flag the ring detection interrupt RDET the carrier detection interrupt ICDET is set to 1 In this case when the corresponding interrupt mask register the ring detection interrupt EIRDET the carrier detection interrupt EICDET has been set to 1 an interrupt request is generated to the CPU When the interrupt mask register is set to 0 the
218. light A Y dark Setting the LC3 LCO register affects the VC23 voltage and other voltages change according to the 23 As a result the LCD contrast is adjusted The supply voltage Vpp within the range from 2 2 to 2 5 V affects the Vc23 voltage Ordinarily VC23 is 2 4 V when 2 5 to 5 5 V in the highest contrast setting No 15 in Table 4 7 6 1 note however that Vc23 will be 0 1 V when VDD 2 2 to 2 5 V At room temperature use setting number 7 or 8 as standard Since the contents of LCO LC3 are undefined at initial reset initialize it by the software 1C63558 TECHNICAL MANUAL EPSON 53 CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION LCD Driver 4 7 7 I O memory of LCD driver Table 4 7 7 1 shows the I O addresses and the control bits for the LCD driver Figure 4 7 7 1 shows the display memory map Table 4 7 7 1 LCD driver control bits Register Address 1 0 LCD drive duty LDUTY1 0 0 1 2 3 LDUTY1 LDUTYO Dummy LPWR switch Duty II 1716 1 8 General purpose register On Off LCD power On Off Enable Disable Expanded LCD driver signal control EXLCDC ALOFF ALO
219. lt foscs PLPOL EVCNT CKSEL1 Pulse polarity setting Event counter mode setting Interrupt Interrupt j control circuit 4 Programmable timer 1 Reload data register RLD10 RLD17 Output 7 j NECS TOUT R02 O put port 1 2 Selector oo Clock i i 8 bi Underflow Li Prescaler gt control it circuit down counter signal PTOUT Prescaler i CHSEL setting 510 Data buffer PTPS11 PTD10 PTD17 Serial interface lt 12 bag PENES DUSCHE MU SNC Sd DOT PU ONES Fig 4 10 1 1 Configuration of programmable timer Data bus 1C63558 TECHNICAL MANUAL EPSON 65 CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Programmable Timer 4 10 2 Setting of initial value and counting down Timers 0 and 1 each have a down counter and reload data register The reload data registers RLDOO RLDO7 timer 0 and RLD10 RLD17 timer 1 are used to set the initial value to the down counter By writing 1 to the timer reset bit PTRSTO timer 0 or PTRST1 timer 1 the down counter loads the initial value set in the reload register RLD Therefore down counting is executed from the stored initial value by the input clock The registers PTRUNO timer 0 PTRUNI timer 1 are provided to control the RUN STOP for
220. ltage Oscillation and internal circuits Oscillation system voltage regulator LCD driver LCD system voltage circuit 5 FSK demodulator Analog system power supply AVDD AVDD Note Do not drive external loads with the output voltage from the internal power supply circuits See Chapter 7 Electrical Characteristics for voltage values and drive capability VDD L gt T AVDD Internal circuits VD1 Oscillation system Oscillation voltage regulator circuit OSC1 4 Vc23 bd pq Ves 5 LCD system voltage circuit 0 1 LCD driver EO SEGO 39 cc x AVss Vss gt External power supply rE Fig 2 1 1 Configuration of power supply 2 1 1 Voltage lt gt for oscillation circuit and internal circuits is a voltage for the oscillation circuit and the internal logic circuits and is generated by the oscillation system voltage regulator for stabilizing the oscillation The voltage is fixed at 2 1 V so it is not necessary to control by software 2 1 2 Voltage Vci Vc5 for LCD driving Vc25 and Vcs are the LCD 1 4 bias drive voltages generated by the LCD system voltage circuit These four output voltages can only be supplied to the externally expanded LCD driver The LCD system voltage circui
221. me Pin No yo Function VDD 52 Power supply pin Vss 46 Power supply VDI 49 Oscillation system regulated voltage output pin Vci Vcs 108 111 LCD system power supply pin 1 4 bias generated internally CA CC 114 112 LCD system boosting reducing capacitor connecting OSCI 47 I Crystal oscillation input pin OSC2 48 O Crystal oscillation output pin OSC3 50 I Ceramic oscillation input pin OSC4 51 O oscillation output pin K00 K03 106 103 Input port K10 K13 102 99 I Input port P00 P03 98 95 93 IO port 0 92 89 IO port switching to serial I F 1 input output is possible by software P20 88 IO port P21 87 IO port P22 86 IO port switching to CL signal output is possible by software P23 85 port switching to FR signal output is possible by software P30 P33 84 81 IO port switching to serial I F 2 input output is possible by software ROO 70 O Output port switching to XBZ signal output is possible by software ROI 69 O Output port switching to BZ signal output is possible by software R02 68 Output port switching to TOUT signal output is possible by software R03 67 Output port switching to FOUT signal output is possible by software R10 66 Output port switching to XTMUTE signal output is possible by software RII 63 Output port switching to XRMUTE signal output is possible by software R12 62 O Output port switching to
222. n case of master mode RXTRG lt 1 46 No ISRC 1 Yes Received data reading from TRXDO TRXD7 Receiving complete Yes RXEN 0 End Fig 4 11 6 3 Receiving procedure in clock synchronous mode 84 EPSON 1C63558 TECHNICAL MANUAL CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Serial Interface Transmit receive ready SRDY signal When this serial interface is used in the clock synchronous slave mode external clock input an SRDY signal is output to indicate whether or not this serial interface can transmit receive to the master side external serial input output device This signal is output from the SRDY terminal and when this interface enters the transmit or receive enable READY status it becomes 0 Low level and be comes 1 High level when there is a BUSY status such as during transmit receive operation The SRDY signal changes the 1 to 0 immediately after writing 1 into the transmit control bit TXTRG or the receive control bit RXTRG and returns from 0 to 1 at the point where the first synchronous clock has been input falling edge When you have set in the master mode control the transfer by inputting the same signal from the slave side using the input port or I O port At this time since the SRDY terminal is not set and instead P13 functions as the I O port you can apply this port for said control
223. n synchronization with the 256 Hz signal The one shot output cannot add an envelope for short durations However the sound level can be set by selecting the duty ratio and the frequency can also be set One shot output is invalid during normal buzzer output during BZE 1 Figure 4 12 6 1 shows timing chart for one shot output 256 Hz RO1HIZ register ROOHIZ register g 01 register 1 ROO register 1 BZOUT register 1 XBZOUT register 1 BZE register p SHTPW register 1 BZSHT w _ IL BZSHT R BZSTP mE R01 BZ port ROO XBZ port Fig 4 12 6 1 Timing chart for one shot output 104 EPSON 1C63558 TECHNICAL MANUAL CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Sound Generator 4 12 7 I O memory of sound generator Table 4 12 7 1 shows the I O addresses and the control bits for the sound generator Table 4 12 7 1 Control bits of sound generator Register Address Comment D3 D2 Di DO Init 1 0 03 17 Hi Z tput FOUTE 0 FOUT FOUTE 1 Hi rol ROSH
224. nal The envelope can be controlled by staged changing of the same duty envelope as detailed in Table 4 12 4 2 in the preceding item from level 1 maximum to level 8 minimum The addition of an envelope to the buzzer signal can be done by writing 1 into ENON but when 0 has been written it is not added When a buzzer signal output is begun writing 1 into BZE after setting ENON the duty ratio shifts to level 1 maximum and changes in stages to level 8 When attenuated down to level 8 minimum it is retained at that level The duty ratio can be returned to maximum by writing 1 into register ENRST during output of a envelope attached buzzer signal The envelope attenuation time time for changing of the duty ratio can be selected by the register ENRTM The time for a 1 stage level change is 62 5 msec 16 Hz when 0 has been written into ENRTM and 125 msec 8 Hz when to 1 has been written However there is also a max 4 msec error from envelope ON up to the first change Figure 4 12 5 1 shows the timing chart of the digital envelope a No change of duty level BZFQ0 2 1 ENRST I d ENRTM BZE a BZ signal Level i Max m 2 1 duty ratio 3 E tol L to 5 t03 gt e t13 6 t04 gt H e 14 7 t05 gt e 015 8 Min Wes t r 0 0 tol 62 5 4 msec tl
225. ng interrupt enable mask is set to 1 and the CPU is set to interrupt enabled status I flag 1 an interrupt will be generated to the CPU Regardless of the interrupt mask register setting the interrupt factor flag will be set to 1 by the occurrence of an interrupt generation condition The interrupt factor flag is reset to 0 by writing 1 After an interrupt occurs the same interrupt will occur again if the interrupt enabled state I flag 1 is set or the RETI instruction is executed unless the interrupt factor flag is reset Therefore be sure to reset write 1 to the interrupt factor flag in the interrupt service routine before shifting to the interrupt enabled state At initial reset these flags are set to 0 98 EPSON 1C63558 TECHNICAL MANUAL CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Serial Interface 4 11 10 Programming notes 1 Be sure to initialize the serial interface mode in the transmit receive disabled status TXEN RXEN 0 2 Do not perform double trigger writing 1 to when the serial interface is in the transmitting receiving operation 3 In the clock synchronous mode since one clock line SCLK is shared for both transmitting and receiving transmitting and receiving cannot be performed simultaneously Half duplex only is possible in clock synchronous mode Consequently be sure not to write 1 to RXTRG TXTRG when TXTRG RXTRG is 1 4 When
226. not to write 1 to TXTRG when TXTRG is 1 4 When a parity error or flaming error is generated during receiving in the asynchronous mode the receiving error interrupt factor flag ISER is set to 1 prior to the receive completion interrupt factor flag ISRC for the time indicated in Table 4 11 10 1 Consequently when an error is generated you should reset the receiving complete interrupt factor flag ISRC to 0 by providing a wait time in error processing routines and similar routines When an overrun error is generated the receiving complete interrupt factor flag ISRC is not set to 1 and a receiving complete interrupt is not generated Table 5 2 1 Time difference between ISER and ISRC on error generation Clock source Time difference fosc3 n 1 2 cycles of fosc3 n Programmable timer 1 cycle of timer 1 underflow 5 When the demultiplied signal of the OSC3 oscillation circuit is made the clock source it is necessary to turn the OSC3 oscillation ON prior to using the serial interface A time interval of 5 msec from the turning ON of the OSC3 oscillation circuit to until the oscillation stabilizes is necessary due to the oscillation element that is used Consequently you should allow an adequate waiting time after turning ON of the OSC3 oscillation before starting transmitting receiving of serial interface 6 Be aware that the maximum clock frequency for the serial interface is limited to
227. nterrupt for the CPU When 1 is written Enabled When 0 is written Disabled Reading Valid EISRC EISRCS EISTR EISTRS and EISER EISERS are interrupt mask registers that respectively corre spond to the interrupt factors for receivie completion transmit completion and receive error Interrupts set to 1 are enabled and interrupts set to 0 are disabled At initial reset these registers are set to 0 ISRC ISTR ISER Serial interface 1 interrupt factor flags FFF3H DO D1 D2 ISRCS ISTRS ISERS Serial interface 2 interrupt factor flags FFF8H DO D1 D2 Indicates the serial interface interrupt generation status When 1 is read Interrupt has occurred When 0 is read Interrupt has not occurred When 1 is written Flag is reset When 0 is written Invalid ISRC ISRCS ISTR ISTRS and ISER ISERS are interrupt factor flags that respectively correspond to the interrupts for receivie completion transmit completion and receive error and are set to 1 by generation of each factor Transmit completion interrupt factor is generated at the point where the data transmition of the shift register has been completed Receive completion interrupt factor is generated at the point where the received data has been transferred into the receive data buffer Receive error interrupt factor is generated when a parity error framing error or overrun error has been detected during data receiving When set in this manner if the correspondi
228. nto the receiving enable status 3 In case of the master mode confirm the transmit ready status on the slave side external serial input output device if necessary Wait until it reaches the transmit ready status 4 Write 1 in the receive control bit RXTRG and start receiving In the master mode this control causes the synchro nous clock to change to enable and is provided to the shift register for receiving and output from the SCLK terminal In the slave mode it waits for the synchronous clock to be input from the SCLK terminal The received data input from the SIN terminal is successively incorpo rated into the shift register in synchronization with the rising edge of the synchronous clock At the point where the data of the 8th bit has been incorporated at the final 8th rising edge of the synchronous clock the content of the shift register is sent to the receive data buffer and the receiving complete interrupt factor flag ISRC is set to 1 When interrupt has been enabled a receiving complete interrupt is generated at this point 5 Read the received data from TRXDO TRXD7 using receiving complete interrupt 6 Repeat steps 3 to 5 for the number of bytes of receiving data and then set the receive disable status by writing 0 to the receive enable register RXEN when the receiving is completed RXEN lt 0 TXEN 0 RXEN 1 No Transmitter ready I
229. ntrol bits of programmable timer Address Register 7 Comment D3 D2 D1 DO Init 1 0 0 3 2 Unused EVCNT 0 Event Timer Timer 0 counter mode selection FCSEL 0 With NR No NR Timer 0 function selection for event counter mode R PW PLPOL 0 na Timer 0 pulse polarity selection for event counter mode CHSEL 0 Timer Timer TOUT output channel selection CHSEL TOUT PTOUT 0 On Off TOUT output control CKSEL1 0 OSC3 OSC1 Prescaler 1 source clock selection SM CKSELO 0 OSC3 OSC1 Prescaler 0 source clock selection 501 0 7 Prescaler 0 501 0010 1 2 3 PTPS01 PTPS00 PTRSTO PTRUNO 00 0 1 Division ratio 11 1 4 1 32 1 256 2 PTRSTO 3 2 Reset Invalid Timer 0 reset reload ae wW RN PTRUNO 0 Run Stop Timer 0 Run Stop PTPS11 0 71 Prescaler 1 PTPS11 PTPS10 PTRST1 PTRUN1 510 0 divi ion rane 4 a D FFC3H PTRST1 3 2 Reset Invalid Timer 1 reset reload RW wW PUN PTRUN1 0 Run Stop Timer 1 Run Stop RLD03 0 71 MSB RLDO3 RLDO2 RLDO1 RLDOO RLDO2 0 FFC4H RLDO1 0 Programmable timer 0 reload data low order 4 bits RW RLDOO 0 LSB RLD07 0 71 MSB RLDO7 RLDO6 RLD05 RLDO4 RLDOG 0 5 RLDOS 0 Programmable timer 0 reload data high order 4 bits FAY RLDO4 LSB RLD13 0 71 MSB
230. o Pause FLASH 3 0 Yes No jFlash function IDP 1 71 Inter digit pause selection for dial pulse initial value 750 ms IDP3 IDP2 IDP1 IDPO 0 IDP3 0 0 a FF15H Time ms x 94 188 281 375 469 563 656 RW 0 HDP3 0 8 9 10 11 12 13 14 15 IDPO 0 i Time ms 750 844 938 1031 1125 1219 1313 1406 CTO 0 On Off Continuous tone output On Off 0 3 2 Unused SINR Enable Disable DTMF row frequency output enable SINC 1 Enable Disable DTMF column frequency output enable TCD3 0 Telephone code for dialing TCD3 TCD3 0 0 1 2 3 4 5 6 7 TCD2 0 DTMF R2C2 R2C3 R3C1 FF17H DP x 1 2 3 4 5 6 7 Tobi 0 TCD3 0 8 9 10 1 12 13 14 15 RW 0 DTMF R3C2 R3C3 R4C2 R4C3 RAC 1 R2C4 R3C4 _ DP 8 9 10 11 12 13 14 15 HSON 0 ff Hook switch On Off Hson o S FF18H 0 3 2 Unused RW R RW CRMUT 1 Mute 0 Receive mute control CTMUT 1 Mute 0 Transmit mute control R13HIZ 0 Hi Z tput R13 CHFO 0 HFO CHFO 1 Hi trol RIGHIZ 1 2 119 2 Pis us FF32H R12HIZ 0 Hi Z Output R12 CHDO 0 HDO CHDO 1 Hi z control RW R11HIZ 0 Hi Z Output R11 CRMO 0 KRMUTE CRMO 1 Hi z control R10HIZ 0 Hi Z Output RIO CTMO 0 XTMUTE CTMO 1 Hi z control R13 R12 R11 R10 R13 1 High Low output port data CHFO 0 Fix at 1 when is used FF33H HDO XRMUTE
231. o has an event counter function using the K13 input port terminal Figure 4 10 1 1 shows the configuration of the programmable timer The programmable timer is designed to count down from the initial value set in the counter with soft ware An underflow according to the initial value occurs by counting down and is used for the following functions Presetting the initial value to the counter to generate the periodical underflow signal Generating an interrupt Generating a TOUT signal output from the R02 output port terminal Generating the synchronous clock source for the serial interface timer 1 underflow is used and it is possible to set the transfer rate K18 OH Input port Programmable timer 0 K13 Reload data register RLDOD RLOO Cr Timer 0 Run Stop n PTRUNG 7 Clock E O Prescaler gt control san i Undertow circuit Selector circuit down counter signal rN 2 048 Prescaler t LT Hz Setting CKSELO Divider 500 Data buffer Timer 1 Run Stop i PTPS01 PTD00 PTD07 PTRUN1 Timer function setting s Selector 04 cu
232. o the interrupt enabled state 60 EPSON 51 63558 TECHNICAL MANUAL CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Stopwatch Timer 4 9 Stopwatch Timer 4 9 1 Configuration of stopwatch timer The 51 63558 has 1 100 sec unit and 1 10 sec unit stopwatch timer built in The stopwatch timer is configured with a 2 levels 4 bit BCD counter which has an input clock approximating 100 Hz signal signal divided from OSC1 to the closest 100 Hz and data be read in units of 4 bits by software Figure 4 9 1 1 shows the configuration of the stopwatch timer 4 Data bus Stopwatch i OSC1 LLL oscillation circuit gt Divider J9 SWDO0 3 SWD4 7 fosc1 ocurre 10 Hz 1 Hz Stopwatch timer reset signal Interrupt Interrupt i i trol request Stopwatch timer RUN STOP signal Cono q Fig 4 9 1 1 Configuration of stopwatch timer The stopwatch timer can be used as a separate timer from the clock timer In particular digital watch stopwatch functions can be realized easily with software 4 9 2 Count up pattern The stopwatch timer is configured of 4 bit BCD counters SWD0 SWD3 and SWD4 SWD7 The counter SWD0 SWD3 at the stage preceding the stopwatch timer has an approximated 100 Hz signal for the input clock It counts up every 1 100 sec and generates an approximated 10 Hz signal The counter SWD4 SWD7 has an approximated 10 Hz signal generated by t
233. ock input to the K13 input port terminal Setting of this register is effective only when timer 0 is used in the event counter mode At initial reset this register is set to 0 PLPOL Timer 0 pulse polarity selection register FFCOH DO Selects the count pulse polarity in the event counter mode When 1 is written Rising edge When 0 is written Falling edge Reading Valid The count timing in the event counter mode timer 0 is selected from either the falling edge of the external clock input to the K13 input port terminal or the rising edge When 0 is written to the PLPOL register the falling edge is selected and when 1 is written the rising edge is selected Setting of this register is effective only when timer 0 is used in the event counter mode At initial reset this register is set to 0 RLDOO RLDO7 Timer 0 reload data register FFC4H FFC5H RLD10 RLD17 Timer 1 reload data register FFC6H FFC7H Sets the initial value for the counter The reload data written in this register is loaded to the respective counters The counter counts down using the data as the initial value for counting Reload data is loaded to the counter when the counter is reset by writing 1 to the PTRSTO or PTRST1 register or when counter underflow occurs At initial reset these registers set to 00H 00 07 Timer 0 counter data FFC8H FFC9H PTD10 PTD17 Timer 1 counter data FFCAH FFCBH Count data in the progr
234. on RO3 should be fixed at 1 FOUTE o 0 FOUT 06 MS 6 de PUE TEN BN FOFQ1 0 P dp FOFQI 0 0 1 2 3 FOFQO 0 selection Frequency fosci 64 fosci 8 fosci fosc3 3 2 Unused 0 0 WDEN WDRST ra 2 FFO7H E NR R RW w WDEN 1 Enable Disable Watchdog timer enable WDRST 3 Reset Reset Invalid Watchdog timer reset writing TPS 0 MB DRS TS 0 Pulse Tone Tone pulse mode selection 1 0 3 2 Unused RW R RW MB 0 33 3 66 6 40 60 Make Break ratio selection DRS 0 20pps 10pps Dialing pulse rate selection PTS3 0 71 Pause time selection initial value 4 sec PTS3 52 PTS1 50 PTS2 1 PTS3 0 0 1 2 3 4 5 6 7 FF11H Time sec 1 2 3 4 5 6 7 RW PTS1 0 PTS3 0 8 9 10 Tl 12 13 14 50 0 Time sec 8 9 10 11 12 13 14 FTS3 0 71 Flash time selection initial value 563 ms FTS3 FTS2 FTS1 FTSO FTS2 1 FTS3 0 0 1 2 3 4 5 6 7 FF12H Time ms x 94 188 281 375 469 563 656 RW FTS1 1 FTS2 0 8 9 10 ll 12 13 14 15 50 0 Time ms 750 844 938 1031 1125 1219 1313 1406 0 DC 13 output selection should be fixed at 1 FF13H CHRO CARO GHD CONG CHDO 0 HDO DC 12 output selection R12 should be fixed at 1 RW CRMO 0 XRMUTE DC output selection R11 should be fixed at 1 CTMO 0 DC 10 selection R10 should be fixed at 1 HF Y N Hand fi HF HOLD PAUSE FLASH d FF14H HO
235. one in 1 bit units Refer to Section 4 5 2 Mask option for details 5 Output specification pull up resistor of the I O ports Either complementary output or N channel open drain output can be selected as the output specifica tion when the I O ports are in the output mode The selection is done in 1 bit units Further whether or not the pull up resistors working in the input mode are supplemented can be selected The selection is done in 1 bit units or 4 bit units depending on the I O port 1 bit unit P20 P21 P22 P23 4 bit unit PO0 P03 10 13 P30 P33 Refer to Section 4 6 2 Mask option for details 6 Configuration of the LCD segment The COM8 COM16 terminals allow selection of terminal specification between COM outputs and SEG45 SEG40 outputs Refer to Section 4 7 2 Mask option for details 7 External voltage detection of SVD circuit External voltage SVD terminal Vss terminal detection can be selected in addition to supply voltage VDD terminal Vss terminal detection The SVD terminal is used to input the external voltage to be detected Refer to Section 4 13 2 Mask option for details 1C63558 TECHNICAL MANUAL EPSON 5 CHAPTER 1 OUTLINE 8 Output specification of the DP terminal Either complementary output or N channel open drain output can be selected as the output specifica tion for the DP dial pulse output terminal Refer to Section 4 14 2 Mask option for details 9 Gain of FSK
236. ous 8 bit asynchronous clock synclonous slave clock synchronous master selected with the SMD1S and SMDOS registers In the clock synchronous slave mode all the P30 P33 ports are set to the serial interface 2 input output port In the clock synchronous master mode P30 P32 are set to the serial interface 2 input output port and P33 can be used as the I O port In the 8 7 bit asynchronous mode P30 and P31 are set to the serial interface 2 input output port and P32 and P33 can be used as the I O port At initial reset this register is set to 0 2 I O port control 00 03 PO I O port data register FF42H P10 P13 P1 I O port data register FF46H 20 23 P2 1 0 port data register FF4AH P30 P33 I O port data register FF4EH I O port data can be read and output data can be set through these registers When writing data When 1 is written High level When 0 is written Low level When an I O port is set to the output mode the written data is output unchanged from the I O port terminal When 1 is written as the port data the port terminal goes high VDD and when 0 is written the terminal goes low Vss Port data can be written also in the input mode When reading data When 1 is read High level When 0 is read Low level The terminal voltage level of the I O port is read out When the I O port is in the input mode the voltage level being input to the port terminal can be read out in the outp
237. output for the serial interface can be used as general purpose registers that do not affect the I O control See Table 4 6 1 1 4 6 4 Pull up during input mode A pull up resistor that operates during the input mode is built into each I O port of the S1C63558 Mask option can set the use or non use of this pull up The pull up resistor becomes effective by writing 1 to the pull up control register PULxx that corre sponds to each port and the input line is pulled up during the input mode When 0 has been written no pull up is done At initial reset the pull up control registers are set to 1 The pull up control registers of the ports in which without pull up have been selected can be used as general purpose registers Even when with pull up has been selected the pull up control registers of the ports that are set as special output or output for the serial interface can be used as general purpose registers that do not affect the pull up control See Table 4 6 1 1 The pull up control registers of the port that are set as input for the serial interface function the same as the I O port 42 EPSON 1C63558 TECHNICAL MANUAL CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION I O Ports 4 6 5 Special outputs CL FR The I O ports P22 and P23 can be used as special output ports that output CL and FR signals by switch ing the function with software Since P22 and P23 are set to I O port input mode at initial reset when us
238. p control register General purpose register when SIF clock sync master is selected FF45H SCLK I pull up control register when SIF clock sync slave is selected PUL11 1 On Off P11 pull up control register ESIF 0 R W General purpose register when SIF is selected PUL10 1 On Off P10 pull up control register ESIF 0 SIN pull up control register when SIF is selected P13 2 High Low P13 I O port data P13 P12 P11 P10 General purpose register when SIF clock sync slave is selected XSRDY XSCLK SOUT SIN P12 32 High Low PI2I O port data FF46H General purpose register when SIF clock sync is selected P11 2 High Low P11 T O port data ESIF 0 RW General purpose register when SIF is selected P10 32 High Low P10 port data ESIF 0 General purpose register when SIF is selected 23 0 Output Input P23 T O control register EXLCDC 0 lOC23 10 22 IOC21 10C20 General purpose register when FR output is selected FF48H 22 0 Output Input 221 control register EXLCDC 0 General purpose register when CL output is selected R W 21 0 Output Input P21 T O control register C20 0 Output Input P20 T O control register PUL23 1 On Off 23 pull up control register EXLCDC 0 PUL23 PUL22 PUL21 PUL20 General purpose register when FR output is selected FF49H PUL22 1 On Off P22 pull up control register EXLCDC 0 General purpose register when CL output is selected R W PUL21 1 On Off P21 p
239. p voltage Vstp lt 10 22 Built in capacitance drain Including the parasitic capacitance inside the IC in chip 14 pF Frequency voltage deviation Af AV 2 2 to 5 5V 10 ppm Frequency IC deviation Af AIC 10 10 Frequency adjustment range Af ACG 5 to 25pF 10 20 ppm Harmonic oscillation start voltage Vhho Cc 5pF VDD 5 5 Permitted leak resistance Rleak Between 5 and Vss 200 MQ OSC3 ceramic oscillation circuit Unless otherwise specified 3 0 Vss 0V Ceramic oscillator 3 58MHz Cac Cpc 30pF Ta 20 to 70 C Item Symbol Condition Min Typ Unit Oscillation start voltage Vsta VDD 2 2 2 Oscillation start time tsta 2 2 to 5 5V 5 ms Oscillation stop voltage Vstp VDD 2 2 51 63558 TECHNICAL MANUAL EPSON 163 CHAPTER 7 ELECTRICAL CHARACTERISTICS 7 6 Serial Interface 1 2 AC Characteristics 1 Clock synchronous master mode during 1 MHz operation Condition 3 0 Vss 0V 20 to 70 C 0 8 0 2 0 8 VoL 0 2 Vpp Item Symbol Min Unit Transmitting data output delay time tsmd 200 ns Receiving data input set up time tsms 400 ns Receiving data input hold time tsmh 200 ns Note that the maximum clock frequency is limited to 1 MHz 2 Clock synchronous slave mode
240. procedure is the most important concept This procedure contains three steps 1 setting 2 executing and 3 interrupt 1 Setting Every function has its control registers It is necessary to set the appropriate control registers before execution Table 4 14 3 1 lists the relations of functions and control registers Table 4 14 3 1 Control registers and default setting Function Control register Initial setting DTMF TPS FF10H D3 Tone mode SINC SINR FF16H Dual tone DP TPS FF10H D3 Tone mode MB FF10H D1 40 60 DRS FF10H DO 10 pps IDP3 IDPO 15 750 ms PAUSE PTS3 PTSO 4 sec FLASH FTS3 FTSO FF12H 563 ms See Section 4 14 10 I O memory of telephone function for details of each control register Operating mode This dialer has built in a DTMF generator for generating tones and a DP generator for generating dial pulses Two basic operating modes are provided tone mode and pulse mode The mode can be switched by software TPS register This setting must be performed prior to the dial processing At initial reset tone mode is set The following operating condition should be set according to the operating mode Tone mode Selecting single tone or dual tone output Pulse mode Setting a make ratio 40 60 or 33 3 66 6 Setting a pulse rate 10 pps or 20 pps e Setting an inter digit pause time 94 msec to 1 406 msec selected from among 15 types Details will be discus
241. propriate wait time Particular care needs to be taken of the key scan during key matrix configuration Make this waiting time the amount of time or more calculated by the following expression 10xCxR C terminal capacitance 5 pF parasitic capacitance pF R pull up resistance 330 kQ 2 When special output CL FR has been selected a hazard may occur when the signal is turned ON or OFF LCD driver 1 When a program that access no memory mounted area F050H FOFFH F150H F1FFH F201H F203H F24FH is made the operation is not guaranteed 2 Because at initial reset the contents of display memory and LC3 LCO LCD contrast are undefined there is need to initialize by the software Furthermore take care of the registers LPWR and ALOFF because these are set so that the display goes OFF 3 The COM8 COM16 terminals can be set as the SEG47 SEG40 terminals by mask option In this case only 1 8 drive duty can be selected so a dot matrix type LCD with a maximum of 384 48 x 8 dots can be driven When 48 segments x 8 commons is selected COM terminals change to SEG terminals as follows 16 gt 5 40 COM15 gt SEG41 14 gt 5 42 COMI13 gt SEG43 12 SEG44 COM11 SEG45 10 gt 5 46 COM9 SEG47 8 SEG47 This option is valid on the PRC board however the SEG47 SEG40 terminals are separately provided Therefore be aware that the COM8 COM 16 terminals cannot be changed to the SEG47 SEG40 Clock
242. r Data input procedure example for Bellcore is shown below 7 8 9 FSK receiving no 1st RDET v yes OSCC lt 1 5 msec wait CLKCHG lt 1 FSKON lt 1 RXENS lt 1 gt yes Receiving error no no 22 yes Received data reading from TRXDO TRXD7 RXTRGS lt 1 Error processing 0 yes RXENS 0 FSKON 0 CLKCHG lt 0 OSCC lt 0 gt END Fig 4 15 4 1 Data input flow example for Bellcore Detect the falling edge RDET 0 of the first ring input The ring detection interrupt can be used Turn the OSC3 oscillation circuit ON by writing 1 to OSCC After waiting 5 msec or more switch the CPU operating clock from OSC1 to OSC3 by writing 1 to CLKCHG Turn the FSK demodulator ON by writing 1 to FSKON Enable the serial interface 2 to receive data by writing 1 to RXENS Read data from TRXDOS TRXD7S after waiting for the receiving interrupt of the serial interface 2 After reading data reset the overrun error check by writing 1 to RXTRGS Repeat this step until the carrier stops and a carrier detection interrupt is generated Disable data receiving by writing 0 to RXENS after the carrier stop detection interrupt is generated Turn the FSK demodulator OFF by writing 0 to FSKON Switch the CPU operating clock from OSC3 to OSC1 by writing 0
243. r 10 13 EIT3 EIT2 EI EITO EIT3 0 Enable Mask Interrupt mask register Clock fn 1 Hz EIT2 0 Enable Mask Interrupt mask register Clock timer 2 Hz RW 0 Enable Mask Interrupt mask register Clock timer 8 Hz EITO 0 Enable Mask _ Interrupt mask register Clock timer 32 Hz 3 2 S 0 EISW10 FFE7H nuse R RW EISW1 0 Enable Mask Interrupt mask register Stopwatch timer 1 Hz EISW10 0 Enable Mask Interrupt mask register Stopwatch timer 10 Hz 0 3 e Unused EISERS EISTRS EISR FFE8H 0 SPRS EISERS 0 Enable Mask Interrupt mask register Serial I F 2 error R RW EISTRS 0 Enable Mask Interrupt mask register Serial I F 2 transmit completion EISRCS 0 Enable Mask Interrupt mask register Serial I F 2 receive completion 0 0 0 4 2 FFEQH edi R 0 3 2 Unused EID 0 Enable Mask Interrupt mask register Dialer 3 2 Unused 0 0 EIRDET EICDET 41722 FFEAH nuse R RW EIRDET 0 Enable Mask Interrupt mask register FSK demodulator ring detection EICDET 0 Enable Mask Interrupt mask register FSK demodulator carrier detection Initial value at initial reset 2 Not set in the circuit 3 Constantly 0 when being read 1C63558 TECHNICAL MANUAL EPSON 149 CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Interrupt and HALT Table 4 16 4 1 b Control bits of interrupt 2 Register D1
244. r flag ISTR is set to 1 The interrupt factor flag ISTR is reset to 0 by writing 1 The following transmitting data be set and the transmitting can be started writing 1 to after this interrupt factor occurs Receive completion interrupt This interrupt factor is generated at the point where receiving has been completed and the receive data incorporated into the shift register has been transferred into the receive data buffer and it sets the interrupt factor flag ISRC to 1 When set in this manner if the corresponding interrupt mask register EISRC is set to 1 and the CPU is set to interrupt enabled status I flag 1 an interrupt will be generated to the CPU When the interrupt mask register EISRC has been set to 0 and interrupt has been disabled no interrupt is generated to the CPU Even in this case the interrupt factor flag ISRC is set to 1 The interrupt factor flag ISRC is reset to 0 by writing 1 The generation of this interrupt factor allows reading of the received data Also the interrupt factor flag ISRC is set to 1 when a parity error or framing error is generated Error interrupt This interrupt factor is generated at the point where a parity error framing error or overrun error is detected during receiving and it sets the interrupt factor flag ISER to 1 When set in this manner if the corresponding interrupt mask register EISER is set to 1 and the CPU is set to interrupt enabled status I
245. r output is OFF BZE 0 and will be invalid when the normal buzzer output is ON BZE 1 3 Since the BZ XBZ signals are the special outputs of the R01 and ROO ports it is necessary to set the high impedance control registers RO1HIZ ROOHIZ to 0 the data registers R01 ROO to 1 and the output selection registers BZOUT XBZOUT to 1 before setting the BZE register to 1 108 EPSON 51 63558 TECHNICAL MANUAL CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION SVD Circuit 4 13 SVD Supply Voltage Detection Circuit 4 13 1 Configuration of SVD circuit 51 63558 has a built in SVD supply voltage detection circuit so that the software can find when the source voltage lowers It is possible to check an external voltage drop other than the supply voltage by mask option Turning the SVD circuit ON OFF and the SVD criteria voltage setting can be done with software Figure 4 13 1 1 shows the configuration of the SVD circuit t SVD S Detection output terminal O SVD circuit gt SVDDT gt SVDON 4 2 5 itari SVDS3 9 SVDSO Fig 4 13 1 1 Configuration of SVD circuit 4 13 2 Mask option Besides the supply voltage VDD terminal Vss terminal drop detection the SVD circuit can detect the external voltage SVD terminal Vss terminal input from the SVD terminal by comparing it with the detected voltage 1 05 V This funct
246. rates 2 channels SIF 1 SIF 2 of full duplex serial interface circuits when asynchronous system is selected that allows the user to select either clock synchronous system or asynchronous system The data transfer method can be selected in software When the clock synchronous system is selected 8 bit data transfer is possible When the asynchronous system is selected either 7 bit or 8 bit data transfer is possible and a parity check of received data and the addition of a parity bit for transmitting data can automatically be done by selecting in software Differences between SIF 1 and SIF 2 SIF 1 and SIF 2 are independently separated serial interface blocks that have the same functions and circuit configurations The serial I O terminals and control registers are assigned as follows Serial I O terminals SIF 1 P10 P13 SIF 2 P30 P33 Control register addresses SIF 1 FF70H FF75H FFE3H FFF3H SIF 2 gt gt FF58H FF5DH FFE8H FFF8H To distinguish the control bits of SIF 1 from SIF 2 S is added to the end of the name for the SIF 2 control bits Example SIF 1 gt ESIF SIF 2 gt ESIFS When using the FSK demodulator SIF 2 is used for data input SIF 1 cannot be used for this purpose Note Explanation made in this section is only for SIF 1 Be aware that S for the SIF 2 control bits is omitted Further the serial I O terminal names are explained using 10 13 Figure 4 11 1
247. ration the OSC3 oscillation circuit must be turned ON and the CPU operating clock must be switched to the OSC3 clock The OSC3 oscillation circuit takes a maximum 5 msec for oscillation stabilization after turning the circuit ON Consequently allow an adequate waiting time after turning ON the OSC3 oscillation before starting the FSK operation Note that the oscillation start time will vary somewhat depending on the oscillator and on the externally attached parts 2 In order to decrease current consumption the FSK demodulator and the OSC3 oscillation circuit should be turned OFF when their operations are not necessary 3 When detecting a carrier the FSK demodulator may output invalid data at the rising edge of the CDET signal In this case the first byte received to the serial interface 2 may result in a parity error or a framing error As this byte is generally used as a leader code ignore the error in the processing 4 After an interrupt occurs the same interrupt will occur again if the interrupt enabled state I flag 1 is set or the RETI instruction is executed unless the interrupt factor flag is reset Therefore be sure to reset write 1 to the interrupt factor flag in the interrupt service routine before shifting to the interrupt enabled state 144 EPSON 1C63558 TECHNICAL MANUAL CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Interrupt and HALT 4 16 Interrupt and HALT Interrupt types gt The 51 63558 pro
248. re disabled At initial reset these registers are set to 0 IRDET ICDET Interrupt factor flags FFFAH D1 00 Indicates the FSK interrupt generation status When 1 is read Interrupt has occurred When 0 is read Interrupt has not occurred When 1 is written Flag is reset When 0 is written Invalid IRDET and ICDET are interrupt factor flags that respectively correspond to the interrupts for ring detection and carrier detection and are set to 1 by generation of each factor When set in this manner if the corresponding interrupt enable mask is set to 1 and the CPU is set to interrupt enabled status I flag 1 an interrupt will be generated to the CPU Regardless of the interrupt mask register setting the interrupt factor flag will be set to 1 by the occur rence of an interrupt generation condition 1C63558 TECHNICAL MANUAL EPSON 143 CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION FSK Demodulator The interrupt factor flag is reset to 0 by writing 1 After an interrupt occurs the same interrupt will occur again if the interrupt enabled state I flag 1 is set or the RETI instruction is executed unless the interrupt factor flag is reset Therefore be sure to reset write 1 to the interrupt factor flag in the interrupt service routine before shifting to the interrupt enabled state At initial reset these flags set to 0 4 15 6 Programming notes 1 When starting the FSK demodulator ope
249. reating the products of our customers dreams Epson IS energy savings 51 63558 Technical Manual SEIKO EPSON CORPORATION EPSON Electronic Devices Website First issue November 1998 Printed October 2001 in Japan DA
250. rnal serial device SIN P10 Data input SOUT P11 Data output c Asynchronous 7 bit 8 bit mode Fig 4 11 3 1 Connection examples of serial interface I O terminals 51 63558 TECHNICAL MANUAL EPSON 79 CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Serial Interface 4 11 4 Clock source There are four clock sources and selection is made by setting the two bits of the clock source selection register SCSO and SCS1 as shown in table below Table 4 11 4 1 Clock source SCS1 SCSO Clock source Programmable timer 93 2400 bps fosc3 372 600 bps foscs 186 1200 bps O This register setting is invalid in clock synchronous slave mode and the external clock input from the SCLK terminal is used When the programmable timer is selected the programmable timer 1 underflow signal is divided by 1 2 and this signal used as the clock source With respect to the transfer rate setting see 4 10 Program mable Timer At initial reset the synchronous clock is set to fosc3 186 Whichever clock is selected the signal is further divided by 1 16 and then used as the synchronous clock Furthermore external clock input is used as is for SCLK in clock synchronous slave mode 1 93 OSC3 fosca H 372 7 Synchro oscillation gt gt Divider 7
251. rrupt flag ISRC is set to RXEN 0 1 When interrupt has been enabled receiving complete interrupt is gener End ated at this point When an overrun error is generated the interrupt factor 2 flag ISRC is not set to 1 and a receiv Fig 4 11 7 3 Receiving procedure in asynchronous mode ing complete interrupt is not gener ated If with parity check has been selected a parity check is executed when data is transferred into the receive data buffer from the shift register and if a parity error is detected the error interrupt factor flag is set to 1 When the interrupt has been enabled an error interrupt is generated at this point just as in the framing error mentioned above 4 Read the received data from TRXDO TRXD using receiving complete interrupt 5 Write 1 to the receive control bit RXTRG to inform that the receive data has been read out When the following data is received prior to writing 1 to RXTRG it is recognized as an overrun error and the error interrupt factor flag is set to 1 When the interrupt has been enabled an error interrupt is generated at this point just as in the framing error and parity error mentioned above 6 Repeat steps 3 to 5 for the number of bytes of receiving data and then set the receive disable status by writing 0 to the receive enable register RXEN when the receiving is completed 88 EPSON 1C63558 TECHNICAL MANUAL CHAPTER 4 PERIPHERAL CIRCUITS AND
252. rs Refer to these when programming Table 5 1 1 Circuits and control registers Circuit and item Control register CPU HALT instruction CPU operating frequency CLKCHG OSCC LCD system voltage circuit LPWR SVD circuit SVDON FSK demodulator FSKON Refer to Chapter 7 Electrical Characteristics for current consumption Below are the circuit statuses at initial reset CPU Operating status CPU operating frequency Low speed side CLKCHG 0 OSC3 oscillation circuit is in OFF status OSCC 0 LCD system voltage circuit OFF status LPWR 0 SVD circuit OFF status SVDON 0 FSK demodulator OFF status FSKON 0 Also be careful about panel selection because the current consumption can differ by the order of several pA on account of the LCD panel characteristics 152 EPSON 51 63558 TECHNICAL AMANUAL CHAPTER 5 SUMMARY NOTES 5 2 Summary of Notes by Function Here the cautionary notes are summed up by function category Keep these notes well in mind when programming Memory and stack 1 Memory is not implemented in unused areas within the memory map Further some non implemen tation areas and unused access prohibition areas exist in the display memory area and the peripheral I O area If the program that accesses these areas is generated its operation cannot be guaranteed Refer to Section 4 7 5 Display memory for the display memory and the I O memory maps
253. rts Table 4 5 5 1 Control bits of output ports Register Address D3 D2 D1 DO Init 1 0 FOUTE 0 FOUT DC 03 output selection should be fixed at 1 FFO6H 0 3 2 Unused FOFQi 0 Bre NM FOFQL 0 0 1 2 3 FOFQO 0 selection Frequency fosci 64 fosci 8 fosci fosc3 CHFO 0 HFO DC R13 output selection should be fixed at 1 HF HD RM TM FF13H CHFO SABO CRMO GIMO CHDO 0 HDO DC R12 output selection R12 should be fixed at 1 RW CRMO 0 XRMUTE R11 output selection R11 should be fixed at 1 CTMO 0 DC R10 output selection R10 should be fixed at 1 adi uie Z 9 2 Output R03 FOUTE 0 FOUT FOUTE 1 Hi z control FF30H RO2HIZ 0 Hi Z Output R02 PTOUT 0 TOUT PTOUT 1 Hi z control M ROIHIZ Hi Z Output R01 BZOUT 0 BZ BZOUT 1 Hi z control ROOHIZ 0 Hi Z Output ROO XBZOUT 0 XBZ XBZOUT 1 Hi z control R03 R02 R01 R00 R03 1 High Low R03 output port data FOUTE O Fix at 1 when FOUT is used FF31H FOUT TOUT BZ XBZ R02 1 High Low R02 output port data PTOUT 0 Fix at 1 when TOUT is used RW R01 1 High Low ROl output port data BZOUT 0 Fix at 1 when BZ is used R00 1 High Low ROO output port data XBZOUT O Fix at 1 when XBZ is used R13HIZ Hi Z tput R13 CHFO 0 HFO CHFO 1 Hi 1 RISHIZ
254. rupt mask register EISxx for the respective interrupt factors are provided and then the interrupt can be disabled enabled by the software Figure 4 11 8 1 shows the configuration of the serial interface interrupt circuit 90 EPSON 1C63558 TECHNICAL MANUAL CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Serial Interface Error generation gt Interrupt factor Address aS Interrupt mask Addres gt register EISER p Receive completion Interrupt factor A flag ISRC ddress Interrupt request a 5 Interrupt mask Address register EISRC completion iad Interrupt factor Address ne D Interrupt mask lt s v Address register EISTR Fig 4 11 8 1 Configuration of serial interface interrupt circuit Transmit completion interrupt This interrupt factor is generated at the point where the sending of the data written into the shift register has been completed and sets the interrupt factor flag ISTR to 1 When set in this manner if the corresponding interrupt mask register EISTR is set to 1 and the CPU is set to interrupt enabled status I flag 1 an interrupt will be generated to the CPU When the interrupt mask register EISTR has been set to 0 and interrupt has been disabled no interrupt is generated to the CPU Even in this case the interrupt facto
255. s reference value High level output current Pxx Rxx BZ Ta 70 C Max value V 1 0 0 8 0 6 0 4 0 2 loH mA 3 0 V 5 0 V 8 Low level output current Pxx Rxx BZ Ta 70 C Min value 14 5 0 V 12 10 Vpop 3 0 V lot mA 51 63558 TECHNICAL MANUAL EPSON 167 CHAPTER 7 ELECTRICAL CHARACTERISTICS High level output current SEGxx Ta 70 C Max value V 1 0 0 8 0 6 0 4 0 2 0 0 0 0 0 1 0 2 0 3 0 4 A 0 5 T 9 0 6 3 0 V 0 7 0 8 VpD 5 0 V 0 9 1 0 Low level output current SEGxx Ta 70 C Min value VpD 5 0 V 2 0 Vpb 3 0 V 1 8 1 6 1 4 T 12 a 1 0 2 0 8 0 6 0 4 0 2 0 0 0 0 0 2 0 4 0 6 0 8 1 0 VoL V 168 EPSON 51 63558 TECHNICAL MANUAL CHAPTER 8 PACKAGE CHAPTER 8 PACKAGE 8 1 Plastic Package QFP15 128pin 97 128 Unit mm 0 12519 5 1 dimensions are subject to change without notice 169 51 63558 TECHNICAL MANUAL EPSON 8 8 2 Ceramic Package for Test Samples Unit mm 32 04 29 028 97 J 2 i 0 8 02 EPSON
256. s set to ON The pull up control registers of the ports in which the pull up resistor is not included become the general purpose register The registers of the ports that are set as special output or output for the serial interface can also be used as general purpose registers that do not affect the pull up control The pull up control registers of the port that are set as input for the serial interface function the same as the I O port 51 63558 TECHNICAL MANUAL EPSON 47 CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION I O Ports 4 6 7 Programming notes 1 When in the input mode I O ports are changed from low to high by pull up resistor the rise of the waveform is delayed on account of the time constant of the pull up resistor and input gate capaci tance Hence when fetching input ports set an appropriate wait time Particular care needs to be taken of the key scan during key matrix configuration Make this waiting time the amount of time or more calculated by the following expression 10xCxR C terminal capacitance 5 pF parasitic capacitance pF R pull up resistance 330 kQ 2 When special output CL FR has been selected a hazard may occur when the signal is turned ON or OFF 48 EPSON 51 63558 TECHNICAL MANUAL CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION LCD Driver 47 LCD Driver COM0 COMIG6 SEGO SEG39 4 7 1 Configuration of LCD driver 51 63558 has 17 common terminals COM0 COM16 and 40 segment
257. s the timing for each mode When you do not receive set RXEN to 0 to disable receiving 4 11 6 Operation of clock synchronous transfer Clock synchronous transfer involves the transfer of 8 bit data by synchronizing it to eight clocks The same synchronous clock is used by both the transmitting and receiving sides When the serial interface is used in the master mode the clock signal selected using 5 50 and SCS1 is further divided by 1 16 and employed as the synchronous clock This signal is then sent via the SCLK terminal to the slave side external serial I O device When used in the slave mode the clock input to the SCLK terminal from the master side external serial input output device is used as the synchronous clock In the clock synchronous mode since one clock line SCLK is shared for both transmitting and receiving transmitting and receiving cannot be performed simultaneously Half duplex only is possible in clock synchronous mode Transfer data is fixed at 8 bits and both transmitting and receiving are conducted with the LSB bit 0 coming first sik LI LU UU UU LSB MSB Data XDOXD1 D2XD3XD4 D5 D6XD7 Fig 4 11 6 1 Transfer data configuration using clock synchronous mode Below is a description of initialization when performing clock synchronous transfer transmit receive control procedures and operations With respect to serial interface interrupt see 4 11 8 Interrupt function Initialization of s
258. sed later The tone mode uses the OSC3 3 58 MHz clock so the OSC3 oscillation must be turned ON OSCC 1 prior to dialing However it is not necessary to switch the CPU system clock to OSC3 When executing the pause or flash function the period of time should be set Pause time 1 to 15 sec 1 sec units selected from among 15 types Flash time 94 msec to 1 406 msec selected from among 15 types Furthermore to use the R10 to R13 terminals for the XTMUTE XRMUTE HDO and HFO outputs the output port functions must be switched to the dialer using the CTMO CRMO CHDO and CHFO registers by writing 1 This switching should be followed the procedure shown in Figure 4 14 3 1 sample XTMUTE XRMUTE outputs The high impedance control registers RTOHIZ R13HIZ must be fixed at 0 and the data registers R10 R13 at 1 before writing 1 to the CTMO CRMO CHDO and CHFO registers Also the mute control registers CTMUT CRMUT should be set to 1 1C63558 TECHNICAL MANUAL EPSON 113 CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Telephone Function R10HIZ g R11HIZ o R10 register 1 R11 register 1 CTMO FF13H D0 qs ov CRMO FF13H9D1 1 T CTMUT FF18H DO ES CRMUT FF18H D1 qs ES R10 XTMUTE output Hz R11 XAMUTE output Hiz T Fig 4 14 3 1 Output
259. shown in Tables 4 1 1 a h for the peripheral I O area 2 Part of the RAM area is used as a stack area for subroutine call and register evacuation so pay attention not to overlap the data area and stack area 3 The 51 63000 core CPU handles the stack using the stack pointer for 4 bit data SP2 and the stack pointer for 16 bit data SP1 16 bit data are accessed in stack handling by SP1 therefore this stack area should be allocated to the area where 4 bit 16 bit access is possible 0100H to 01FFH The stack pointers SP1 and SP2 change cyclically within their respective range the range of SP1 is 0000H to 03FFH and the range of SP2 is 0000H to 00 Therefore pay attention to the SP1 value because it may be set to 0200H or more exceeding the 4 bit 16 bit accessible range in the 51 63558 or it may be set to OOFFH or less Memory accesses except for stack operations by SP1 are 4 bit data access After initial reset all the interrupts including NMI are masked until both the stack pointers SP1 and SP2 are set by software Further if either SP1 or SP2 is re set when both are set already the interrupts including NMI are masked again until the other is re set Therefore the settings of SP1 and SP2 must be done as a pair Watchdog timer 1 When the watchdog timer is being used the software must reset it within 3 second cycles 2 Because the watchdog timer is set in operation state by initial reset set the watchdog timer to disabled
260. ssion is done while adopting the synchronization at the start stop bits that have attached before and after each piece of data The RS 232C interface functions can be easily realized by selecting this transfer mode This interface has separate transmit and receive shift registers and is designed to permit full duplex transmission to be done simultaneously for transmitting and receiving For transfer data in the 7 bit asynchronous mode either 7 bits data no parity or 7 bits data parity bit can be selected In the 8 bit asynchronous mode either 8 bits data no parity or 8 bits data parity bit can be selected Parity can be even or odd and parity checking of received data and adding a party bit to transmitting data will be done automatically Thereafter it is not necessary to be conscious of parity itself in the program The start bit and stop bit are respectively fixed at one bit and data is transmitted and received by placing the LSB bit 0 at the front Samping Le 7bit data s1 DO D1 D2 D3 D4 D5 D6 s2 7bit data parity s1 DO D1 02 D3 D4 D5 D6 p 52 8bit data s1 DO D1 D2 D3 D4 D5 06 07 52 8bit data parity s1 DO D1 D2 D3 D4 D5 D6 D7 p 52 51 Start bit Low level 1 bit s2 Stop bit High level 1 bit Parity bit Fig 4 11 7 1 Transfer data configuration for asynchronous system Here following we will explain the control sequence
261. st be 0 98 msec or more to count reliably The noise rejecter allows the counter to input the clock at the second falling edge of the internal 2 048 Hz signal after changing the input level of the K13 input port terminal Consequently the pulse width of noise that can reliably be rejected is 0 48 msec or less fosci 32 768 kHz Figure 4 10 3 2 shows the count down timing with noise rejecter 1C63558 TECHNICAL MANUAL EPSON 67 CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Programmable Timer 2 048 Hz 1 K13 input imn e Counter input dedic n 1 n2 n3 When fosct is 32 768 kHz 2 When PLPOL register is set to 0 Fig 4 10 3 2 Count down timing with noise rejecter The operation of the event counter mode is the same as the timer mode except it uses the K13 input as the clock Refer to Section 4 10 2 Setting of initial value and counting down for basic operation and control 4 10 4 Setting of input clock in timer mode Timer 0 and timer 1 each include a prescaler The prescalers generate the input clock for each timer by dividing the source clock supplied from the OSC1 or OSC3 oscillation circuit The source clock OSC1 or OSC3 and the division ratio of the prescaler can be selected with software for timer 0 and
262. t LC3 LCO are undefined 4 7 8 Programming notes 1 When a program that access no memory mounted area F060H FOFFH F160H F1FFH F201H F203H F25FH is made the operation is not guaranteed 2 Because at initial reset the contents of display memory and LC3 LCO LCD contrast are undefined there is need to initialize by the software Furthermore take care of the registers LPWR and ALOFF because these are set so that the display goes OFF 3 The COM8 COM16 terminals can be set as the SEG47 SEG40 terminals by mask option In this case only 1 8 drive duty can be selected so a dot matrix type LCD with a maximum of 384 48 x 8 dots can be driven When 48 segments x 8 commons is selected COM terminals change to SEG terminals as follows 16 gt SEG40 COMI5 gt SEG41 14 gt 5 42 13 gt SEG43 COMI2 gt SEG44 COM11 gt SEG45 10 gt 5 46 COM9 SEG47 8 SEG47 This option is valid on the PRC board however the SEG47 SEG40 terminals are separately provided Therefore be aware that the COM8 COM 16 terminals cannot be changed to the SEG47 SEG40 56 EPSON 1C63558 TECHNICAL MANUAL CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Clock Timer 4 8 Clock Timer 4 8 1 Configuration of clock timer The 51 63558 has a built in clock timer that uses OSC1 crystal oscillator as the source oscillator The clock timer is configured of an 8 bit binary counter that serves as the input clock fosci d
263. t enable register TXEN to reset the m Data transmitting serial interface 2 Write 1 in the transmit enable register TXEN to set into TXEN lt 0 the transmitting enable status 3 Write the transmitting data into TRXDO TRXD7 TXEN 1 Also when 7 bit data is selected the TRXD7 data be comes invalid Set transmitting data to TRXDO TRXD7 4 Write 1 in the transmit control bit TXTRG and start transmitting TXTRG 1 This control causes the shift clock to change to enable and a start bit LOW is output to the SOUT terminal in 17 synchronize to its rising edge The transmitting data set to the shift register is shifted one bit at a time at each Yes rising edge of the clock thereafter and is output from the No Transmit complete SOUT terminal After the data output it outputs a stop bit HIGH and HIGH level is maintained until the next Yes start bit is output TXEN lt 0 The transmitting complete interrupt factor flag ISTR is set End D to 1 at the point where the data transmitting is com pleted When interrupt has been enabled a transmitting complete interrupt is generated at this point Set the following transmitting data using this interrupt Fig 4 11 7 2 Transmit procedure in asynchronous mode 5 Repeat steps 3 to 4 for the number of bytes of trans mitting data and then set the transmit disable status by wri
264. t generates VC23 with the voltage regulator built in and generates three other voltages by boosting or reducing the voltage of Vc23 Table 2 1 2 1 shows the Vc1 Vc23 Vc4 and VC5 voltage values and boost reduce status Table 2 1 2 1 LCD drive voltage when generated internally LCD drive voltage Boost reduce status Voltage value V Vci 2 0 5 1 13 N The LCD dri rive voltage can uo standard 205 be adjusted by the software 2 15 3 38 see Section 4 7 5 Values Vos Vc2 x 2 4 50 in the above table are typical values Refer to Section 4 7 LCD Driver for control of the LCD drive voltage 8 EPSON 51 63558 TECHNICAL MANUAL CHAPTER 2 POWER SUPPLY AND INITIAL RESET 2 2 Initial Reset To initialize the S1C63558 circuits initial reset must be executed There are two ways of doing this 1 External initial reset by the RESET terminal 2 External initial reset by simultaneous low input to terminals 00 mask option setting The circuits are initialized by either 1 or 2 When the power is turned on be sure to initialize using the reset function It is not guaranteed that the circuits are initialized by only turning the power on Figure 2 2 1 shows the configuration of the initial reset circuit OSC1 O osci 1 Hz oscillation P Divider 2 Hz OSC2 C _eir
265. t to 0000B The following shows the register settings for each mode 1 Pulse mode In this mode write data for a dial number 1 9 0 to this register Table 4 14 10 7 lists the relationship of writing codes and pulse counts Table 4 14 10 7 Relationship of code sand pulse counts TCD code TCD code D3ID2 D1lDO Pulse count 53152151100 Pulse count 0 01 0 0 Unavailable 1101010 8 0101011 1 1 0 0 1 9 0 0 1 0 2 1 0 1 0 10 0101111 3 4 1 01 0 12 5 1 1 0 1 13 0 1 110 6 111110 14 111 1 7 1 1 1 l 15 Do not write 0 0000B to the TCD register because it may cause a malfunction For a dial number between 1 to 9 the number is used for the pulse count as is Dial number 0 represents 10 pulses so write 10 1010B to the TCD register 2 Tone mode In this mode write data for a push button ROW COL to this register Table 4 14 10 8 lists the relationship of writing codes and tone frequencies Table 4 14 10 8 Relationship of codes and tone frequencies TCD code Ke TCD code Ke D3 D2 D1 po 009 frequency dns D3 D2 D1 po 1009 frequency 52 0 A 00 0 ROW3 COL2 8 0 1 COLD 71 1 0 0 1 ROW3 COL 9 o o 1 0o OWLCOL 2 1 0 1 0 ROWA4COL2 o o 1 1 OWLCOL 3 1 0 1 1 ROWA4COL3 0 1 0 0 ROW2
266. tained No operation results when 0 is written to TMRST This bit is write only and so is always 0 at reading TMRUN Clock timer RUN STOP control register FF78H DO Controls RUN STOP of the clock timer When 1 is written RUN When 0 is written STOP Reading Valid The clock timer enters the RUN status when 1 is written to the TMRUN register and the STOP status when 0 is written In the STOP status the timer data is maintained until the next RUN status or the timer is reset Also when the STOP status changes to the RUN status the data that is maintained can be used for resuming the count At initial reset this register is set to 0 1C63558 TECHNICAL MANUAL EPSON 59 CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Clock Timer EITO 32 Hz interrupt mask register FFE6H DO EIT1 8 Hz interrupt mask register FFE6H D1 EIT2 2 Hz interrupt mask register FFE6H D2 EIT3 1 Hz interrupt mask register FFE6H D3 These registers are used to select whether to mask the clock timer interrupt When 1 is written Enabled When 0 is written Masked Reading Valid The interrupt mask registers EITO EIT2 EIT3 are used to select whether to mask the interrupt to the separate frequencies 32 Hz 8 Hz 2 Hz 1 Hz At initial reset these registers are set to 0 ITO 32 Hz interrupt factor flag FFF6H DO IT1 8Hz interrupt factor flag FFF6H D1 IT2 2Hz interrupt factor flag FFF6H D2 IT3 1Hzinterrupt
267. ter just defines the pause time The actual pause operation will be activated when the PAUSE bit FF14HeD1 is set to 1 Figure 4 14 6 1 shows the timing chart of the pause function HSON FF18H D3 Data bus Pause 3 Write to TCD FF17H Write to PAUSE FF14H9 D1 DP top tes 7 j tua XRMUTE R11 XTMUTE R10 Interrupt 1 i request top Inter digit pause time Mute hold time tps Pause time Fig 4 14 6 1 a Pause execution timing chart in pulse mode 122 EPSON 1C63558 TECHNICAL MANUAL HSON FF18H D3 Data bus CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Telephone Function Write to TCD FF17H Write to PAUSE FF14H D1 DP TONE tro tPs trip XRMUTE R11 XTMUTE R10 Interrupt tH tud request tro Tone duration time tre Tone inter digit pause time Mute hold time tps Pause time Fig 4 14 6 1 b Pause execution timing chart in tone mode PAUSE is a write only bit and is used as the trigger for a pause insertion When the pause time that is set to the PTS register has passed from the writing of the PAUSE bit an interrupt occurs At the same time the PAUSE bit is automatically cleared to 0 by the interrupt Thus the pause function requires
268. terminal setting procedure 2 Executing After setting write the corresponding control register to start the execution Table 4 14 3 2 lists control registers for executing Table 4 14 3 2 Control registers and executing function Functions Control registers Executing function DTMF TCD3 TCDO FF17H Dialing tone CTO FF16H D3 Continuous tone output ON OFF HSON FF18H D3 Hook switch ON OFF DP TCD3 TCDO FF17H Dialing pulse HSON FFI8H D3 Hook switch ON OFF Pause PAUSE FF14H D1 Pause Flash FLASH 14 Flash Hold line HOLD 14 2 Hold line Handfree HF FF14H D3 Handfree See Section 4 14 10 I O memory of telephone function for details of each control register The hook switch HSON continuous tone output CTO hold line HOLD and handfree HF functions and their timings are controlled by software These functions do not generate interrupts The HSON that controls the hook switch must be turned ON off hook before executing the tele phone function Actual handset operations are not taken into the dialer The HSON register allows on hook dialing The hook switch should be connected to an input port Kxx and get the switch status using an input interrupt By setting data for the dial number 1 digit to the TCD register after setting HSON to off hook the dialer output the dialing tone or dialing pulses according to the condition set in 1 When the output is completed
269. terminals SEGO SEG39 so that it can drive a dot matrix type LCD with a maximum of 680 40 x 17 dots The driving method is 1 17 duty 1 16 duty or 1 8 duty dynamic drive with four voltages 1 4 bias Vc1 Vc23 and VC5 LCD display ON OFF can be controlled by the software 4 7 2 Mask option The COM8 COM16 terminals can be set as the SEG47 SEG40 terminals by mask option In this case only 1 8 drive duty can be selected so a dot matrix type LCD with a maximum of 384 48 x 8 dots can be driven When 48 segments x 8 commons is selected COM terminals change to SEG terminals as follows 16 gt 5 40 15 gt 5 41 14 gt 5 42 COMI3 gt SEG43 COM12 gt SEG44 COM11 gt SEG45 10 gt 5 46 9 gt 5 47 8 gt 5 47 This option is valid on the PRC board however the SEG47 SEG40 terminals are separately provided Therefore be aware that the COM8 COM16 terminals cannot be changed to the SEG47 SEG40 4 7 3 Power supply for LCD driving and Vcs are the LCD 1 4 bias drive voltages generated by the LCD system voltage circuit These four output voltages can only be supplied to the externally expanded LCD driver Turning the LCD system voltage circuit ON or OFF is controlled with the LPWR register When LPWR is set to 1 the LCD system voltage circuit outputs the LCD drive voltages Vc1 Vc23 Vc4 and Vcs to the LCD driver The LCD system voltage circuit generates VC2
270. terrupt can be selected for each of the two systems 00 10 13 At initial reset these registers are set to 0 IK0 KO input interrupt factor flag FFFAH DO IK1 K1 input interrupt factor flag FFF5H DO These flags indicate the occurrence of input interrupt When 1 is read Interrupt has occurred When 0 is read Interrupt has not occurred When 1 is written Flag is reset When 0 is written Invalid The interrupt factor flags IKO and are associated with K00 K03 and K10 K13 respectively From the status of these flags the software can decide whether an input interrupt has occurred The interrupt factor flag is set to 1 when the interrupt condition is established regardless of the interrupt mask register setting However the interrupt does not occur to the CPU when the interrupt is masked These flags are reset to 0 by writing 1 to them After an interrupt occurs the same interrupt will occur again if the interrupt enabled state I flag 1 is set or the RETI instruction is executed unless the interrupt factor flag is reset Therefore be sure to reset write 1 to the interrupt factor flag in the interrupt service routine before shifting to the interrupt enabled state At initial reset these flags set to 0 1C63558 TECHNICAL MANUAL EPSON 31 CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Input Ports 4 4 5 Programming notes 1 When input ports are changed from low to high b
271. ters These flags are reset to 0 by writing 1 to them After an interrupt occurs the same interrupt will occur again if the interrupt enabled state I flag 1 is set or the RETI instruction is executed unless the interrupt factor flag is reset Therefore be sure to reset write 1 to the interrupt factor flag in the interrupt service routine before shifting to the interrupt enabled state At initial reset these flags set to 0 4 9 5 Programming notes 1 When data of the counter is read at run mode perform the reading after suspending the counter once and then set SWRUN to 1 again Moreover it is required that the suspension period not exceed 976 usec 1 4 cycle of 256 Hz 2 After an interrupt occurs the same interrupt will occur again if the interrupt enabled state I flag 1 is set or the RETI instruction is executed unless the interrupt factor flag is reset Therefore be sure to reset write 1 to the interrupt factor flag in the interrupt service routine before shifting to the interrupt enabled state 64 EPSON 1C63558 TECHNICAL MANUAL CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Programmable Timer 4 10 Programmable Timer 4 10 1 Configuration of programmable timer The 51 63558 has two 8 bit programmable timer systems timer 0 and timer 1 built in Timer 0 and timer 1 are composed of 8 bit presettable down counters and they can be used as 8 bit x 2 channel programmable timers Timer 0 als
272. the input clock 2 Event counter mode The timer 0 has an event counter function that counts an external clock input to the input port K13 This function is selected by writing 1 to the timer 0 counter mode selection register EVCNT The timer 1 operates only in the timer mode and cannot be used as an event counter In the event counter mode the clock is supplied to timer 0 from outside of the IC therefore the settings of the timer 0 prescaler division ratio selection registers 500 501 and the settings of the timer 0 source clock selection register CKSELO become invalid Count down timing can be selected from either the falling or rising edge of the input clock using the timer 0 pulse polarity selection register PLPOL When 0 is written to the PLPOL register the falling edge is selected and when 1 is written the rising edge is selected The count down timing is shown in Figure 4 10 3 1 EVCNT 1 PTRUNO _ PLPOL 0 1 input titi Count data n 1 2 n3 4 5 6 Fig 4 10 3 1 Timing chart in event counter mode The event counter mode also includes a noise reject function to eliminate noise such as chattering on the external clock K13 input signal This function is selected by writing 1 to the timer 0 function selection register FCSEL When with noise rejector is selected an input pulse width for both low and high levels mu
273. time 4 ms Make ratio M B Selected by software 1 2 2 3 Dial puls rate DR Selected by software 10 20 Make time 10 1 2 33 2 ms 20pps M B 1 2 16 6 ms 10 2 3 39 1 ms 20pps M B 2 3 19 5 ms Break time 10 1 2 66 4 ms 20pps M B 1 2 33 2 ms 10 2 3 58 6 ms 20pps M B 2 3 29 3 ms Tone output DC level VTDC 0 5 Vpp Vss V ROW single tone VR Vpp 3V RL 10kQ 92 mVrms output voltage 5 5 RL 10kQ 168 mVrms COL single tone Vpp 3V RL 10kO 122 mVrms output voltage 5 5 RL 10kQ 224 mVrms Tone output voltage ratio dBcR Vpp 3V RL 10kQ 2 5 dB 5 5 RL 10kQ 25 Tone load resistor RIL 2 5 to 5 5V 7 kQ Tone distortion ratio THD 2 5 to 5 5V RL 10kQ 6 Tone output frequency fRowi 701 32 Hz fRow2 711 45 Hz fRow3 857 17 2 fRow4 935 10 Hz fcoLi 1215 88 Hz 2 1331 68 Hz fCoL3 1471 85 Hz 4 1645 01 Hz Tone output time trp 94 ms Tone inter digit pause time 94 ms Tone output cycle tr trp trip 188 ms 7 9 Timing Chart System clock switching OSCC e 5 msec min 2 instruction execution m Y time or longer CLKCHG 166 EPSON 51 63558 TECHNICAL MANUAL CHAPTER 7 ELECTRICAL CHARACTERISTICS 7 10 Characteristic Curve
274. timer Be sure to read timer data in the order of low order data TM0 TM3 then high order data TM4 TM7 Stopwatch timer When data of the counter is read at run mode perform the reading after suspending the counter once and then set SWRUN to 1 again Moreover it is required that the suspension period not exceed 976 usec 1 4 cycle of 256 Hz Programmable timer 1 When reading counter data be sure to read the low order 4 bits 00 03 PTD10 PTD193 first Furthermore the high order 4 bits PID04 PTDO7 PTD14 PTD17 should be read within 0 73 msec when fosci is 32 768 kHz of reading the low order 4 bits PID00 PTD03 PTD10 PTD13 154 EPSON 51 63558 TECHNICAL AMANUAL CHAPTER 5 SUMMARY NOTES 2 The programmable timer actually enters RUN STOP status in synchronization with the falling edge of the input clock after writing to the register Consequently when 0 is written to the PTRUNO PTRUNI register the timer enters STOP status at the point where the counter is decremented 1 The PTRUNO PTRUN1 register maintains 1 for reading until the timer actually stops Figure 5 2 1 shows the timing chart for the RUN STOP control Input clock PTRUNO PTRUN1 RD 1 RUN 0 STOP PTRUNO PTRUN 1 WR K writing Y writing PTDOX PTD1X 42H 41H 40H 3FH 3EH 3DH Fig 5 2 1 Timing chart for RUN STOP control It is the same e
275. timers 0 and 1 By writing 1 to the register after presetting the reload data to the down counter the down counter starts counting down Writing 0 stops the input count clock and the down counter stops counting This control RUN STOP does not affect the counter data The counter maintains its data while stopped and can restart counting continuing from that data The counter data be read via the data buffers PTD00 PTDO7 timer 0 and PTD10 PTD17 timer 1 in optional timing However the counter has the data hold function the same as the clock timer that holds the high order data when the low order data is read in order to prevent the borrowing operation between low and high order reading therefore be sure to read the low order data first The counter reloads the initial value set in the reload data register RLD when an underflow occurs through the count down It continues counting down from the initial value after reloading In addition to reloading the counter this underflow signal controls the interrupt generation pulse TOUT signal output and clock supplying to the serial interface PTRUNO 1 221 PTRSTO 1 RLD00 07 10 17 A6H Input clock UI PTDO7 17 PTDO6 16 PTDOS 15 PTD04 14 1 m y
276. ting 0 to the transmit enable register TXEN when the transmitting is completed 51 63558 TECHNICAL MANUAL EPSON 87 CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Serial Interface Data receive procedure The control procedure and operation during receiving is as follows 1 Write 0 in the receive enable register D 2 RXEN to set the receiving disable status ala receiving and to reset the respective PER OER FER flags that indicate parity overrun RXEN 0 and framing errors Resets error flags 2 Write 1 in the receive enable register PER OER and FER RXEN to set into the receiving enable status RXEN I 3 The shift clock will change to enable from the point where the start bit LOW has been input from the SIN terminal and the receive data will be synchronized to the rising edge follow ing the second clock and will thus be successively incorporated into the shift register After data bits have been incorporated the stop bit is checked and if it is not HIGH it becomes a framing error and the error interrupt factor flag ISER is set to RXTRG 1 1 When interrupt has been enabled an error interrupt is generated at this point When receiving is completed data in the shift register is transferred to the receive data buffer and the receiving Received data reading from TRXD0 TRXD7 Eir r procesem complete inte
277. to CLKCHG 10 Turn the OSC3 oscillation circuit OFF by writing 0 to OSCC 1C63558 TECHNICAL MANUAL EPSON 141 CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION FSK Demodulator 4 15 5 I O memory of FSK demodulator Table 4 15 5 1 shows the I O address and control bits for the FSK demodulator Table 4 15 5 1 Control bits of FSK demodulator Register D2 D1 DO Init 1 0 Comment FSKON On Off FSK demodulator On Off 0 3 Unused RW R RDET 4 Ring NoRing Ring detection bit CDET 0 Carrier No Carrier Carrier detection bit 0 0 0 3 2 Unused FF67H 0 3 2 _ Unused R RW RDETCP 0 L d RDET comparison register CDETCP 0 J CDET comparison register 3E NUNC FFEAH R RW EIRDET 0 Enable Mask Interrupt mask register FSK demodulator ring detection EICDET 0 Enable Mask Interrupt mask register FSK demodulator carrier detection 7 03 Unused FFFAH 0 3 2 Yes No Unused R RW IRDET 0 W Interrupt factor flag FSK demodulator ring detection ICDET 0 Reset Invalid Interrupt factor flag FSK demodulator carrier detection Initial value at initial reset 2 Not set in the circuit 3 Constantly 0 when being read 4 Depends on the input status of the RDIN terminal FSKON FSK demodulator control register FF66H D3 Turns the FSK demodulator ON and OFF When 1 is written ON When 0 is writt
278. tput Input P30 T O control register ESIFS 0 General purpose register when SIF is selected PUL33 1 On Off P33 pull up control register General purpose register when SIF clock sync slave is selected PUL33 PUL32 PUL31 PUL30 PUL32 1 On Off P32 pull up control register General purpose register when SIF clock sync master is selected SCLK 1 pull up control register when SIF clock sync slave is selected PUL31 1 On Off P31 pull up control register ESIFS 0 R W RW General purpose register when SIF is selected PUL30 1 On Off P30 pull up control register ESIFS 0 SIN pull up control register when SIF is selected P33 2 High Low P33 I O port data P33 P32 P31 P30 General purpose register when SIF clock sync slave is selected XSRDYS XSCLKS SOUTS SINS P32 32 High Low P32I O port data General purpose register when SIF clock sync is selected P31 2 High Low P31 I O port data ESIFS 0 RW General purpose register when SIF is selected P30 2 High Low P30 I O port data ESIFS 0 General purpose register when SIF is selected 3 EE SMDIS 05 0 1 0 SMD1S 5 005 Boc 0 12 VF 2 ME master Clk sync slave FF58H SMDIS 0S 2 3 R R W SMDOS 0 J mode selection Mode Async 7 bit Async 8 bit ESIFS 0 SIF VO Serial VF 2 enable P3x port function selection EXLCDC 0 Enable Disable Expanded L
279. tput is started 4 Count the tone duration time and then write 0 to the CTO register note 5 Reset the interrupt factor flag after an interrupt has occurred 6 Repeat steps 2 to 5 for the number of dial digits Communication 7 Write 0 to the HSON register after communication is finished Note The CTO register in 2 and 4 should be controlled if more than 94 msec tone duration time is required It is not necessary when outputting a tone for 94 msec 4 14 5 Pulse mode DP The pulse mode outputs dial pulses By specifying a dial number using software the DP generator generates the pulse pattern and outputs it from the DP terminal At initial reset the dialer is set in tone mode To change the mode to the pulse mode write 1 to the TPS register 10 D3 Figure 4 14 5 1 shows the block diagram of the DP generator 32kHz lFrequency Programmable oscillator divider gt down counter O DP gt 3 t 5 a 9 to Control Timing control a registers gt circuit Fig 4 14 5 1 DP generator block diagram The DP generator uses the OSC1 32 kHz clock for generating dial pulses In this mode it is not necessary to control the OSC3 oscillation circuit as in the tone mode In the pulse mode the specified dial number 1 to 9 represents the number of pulses 0 represents 10 pulses The DP generator has a built in programmable down counter in which a
280. ts to prevent this 1 The power supply should be connected to the VDD and Vss terminals with patterns as short and large as possible 2 When connecting between the VDD and Vss terminals with a bypass capacitor the terminals should be connected as short as possible Bypass capacitor connection example VDD VDD a 1 55 1 55 3 Components which are connected to the and Vci Vcs terminals such as capacitors should be connected in the shortest line In particular the 5 voltages affect the display quality Do not connect anything to the Vci Vcs terminals when the LCD driver is not used 51 63558 TECHNICAL MANUAL EPSON 157 CHAPTER 5 SUMMARY OF NOTES lt Arrangement of Signal Lines gt In order to prevent generation of electromagnetic induction noise caused by mutual inductance do not arrange a large current signal line near the circuits that are sensitive to noise such as the oscilla tion unit When a signal line is parallel with a high speed line in long distance or intersects a high speed line noise may generated by mutual interference between the signals and it may cause a malfunction Do not arrange a high speed signal line especially near circuits that are sensitive to noise such as the oscillation unit Prohibited pattern OSC4 OSC3 Vss Large current signal line High speed signal line
281. tten to the CTMUTE register the XTMUTE R10 terminal is pulled down to Low Vss level to mute the transmit line When the CTMUTE register is set to 1 the XTMUTE R10 terminal is controlled by the hardware and will be Low Vss level during a dialing pulse cycle flash cycle dialing tone cycle or a hold line cycle At initial reset this register is set to 1 Hook switch ON OFF FF18H DO Controls the hook switch When 1 is written Hook OFF When 0 is written Hook ON Reading Valid When the HSON register is set to 1 the DP terminal goes High VDD level and the hook switch goes to off hook status At initial reset this register is set to 0 CTO Continuous output tone selection FF16H D3 Selects the tone duration time to continuous output or not When 1 is written Continuous When 0 is written 94 msec Reading Valid This register is used to decide the tone duration time The minimum value of tone duration time is 94 msec When the CTO register is set to 1 a tone signal will be output until the CTO register is changed to 0 If the period CTO is changed from 1 to 0 that is controlled by the CTO register is less than 94 msec the duration time will be prolonged to 94 msec When the CTO register is set to 0 a tone signal will be output with the minimum time 94 msec This setting is valid only for tone mode At initial reset this register is set to 0 EID Interrupt mask register F
282. tting of the interrupt mask registers the interrupt factor flags are set to 1 by the overflow of their corresponding counters 62 EPSON 51 63558 TECHNICAL MANUAL CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Stopwatch Timer 4 9 4 I O memory of stopwatch timer Table 4 9 4 1 shows the I O addresses and the control bits for the stopwatch timer Table 4 9 4 1 Control bits of stopwatch timer Register Address D3 D2 D1 DO Init 1 0 0 3 2 Unused 0 0 SWRST SWRUN 0 3 Unused FF7CH SWRST 3 Reset Reset Invalid Stopwatch timer reset writing R w PAM SWRUN 0 Run Stop Stopwatch timer Run Stop SWD3 SWD2 SWD1 SWD SWOS FF7DH i SWD2 0 Stopwatch timer data H SWD1 0 BCD 1 100 sec SWDO 0 2 SWD7 0 7 EEN SWF 5406 SWD4 SWD6 0 Stopwatch timer data SWD5 0 BCD 1 10 sec swo4 0 J 0 3 2 Unused 0 0 EISW10 0 3 Unused FFE7H i EISW1 0 Enable Mask Interrupt mask register Stopwatch timer 1 Hz EISW10 0 Enable Mask Interrupt mask register Stopwatch timer 10 Hz 0 3 2 R Unused 0 0 0 3 2 Yes No Unused 7 Se tcc ROR aa ISW1 0 W Interrupt factor flag Stopwatch timer 1 Hz R ISW10 0 Reset Invalid Interrupt factor flag Stopwatch timer 10 Hz Initial value at initial reset 2 Not set in the circuit 3 Constantly 0 when being read
283. ull up control register PUL20 1 On Off P20 pull up control register P23 P22 P23 2 High Low P23 I O port data EXLCDC 0 FR CL 21 20 General purpose register when FR output is selected 22 32 High Low P2210 port data EXLCDC 0 General purpose register when CL output is selected R W P21 2 High Low 21 T O port data P20 2 High Low P20 T O port data C33 0 Output Input P33 T O control register ioc33 IOC32 10 1 100390 General purpose register when SIF clock sync slave is selected OC32 0 Output Input P32 T O control register FF4CH General purpose register when SIF clock sync is selected 0631 0 Output Input P31 T O control register ESIFS 0 General purpose register when SIF is selected PAY C30 0 Output Input P30 T O control register ESIFS 0 General purpose register when SIF is selected PUL33 1 On Off P33 pull up control register General purpose register when SIF clock sync slave is selected PUL33 PUL32 PUL31 PUL30 PUL32 1 On Off P32 pull up control register General purpose register when SIF clock sync master is selected FFADH SCLK 1 pull up control register when SIF clock sync slave is selected PUL31 1 On Off P31 pull up control register ESIFS 0 R W General purpose register when SIF is selected PUL30 1 On Off P30 pull up control register ESIFS 0 SIN pull up control register when SIF is selected 51 63558 TECHNICAL MANUAL EPSON 17 CHAPTER 4
284. ulses so write 10 1010B to the TCD register Writing data to the TCD register triggers the start of the pulse output Figure 4 14 5 2 shows a pulse output timing chart 120 EPSON 51 63558 TECHNICAL MANUAL CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Telephone Function HSON FF18H D3 Data bus Wite to TCD FF17H DP Pod ML a gt Break tipP 10 tipp 141 nu gt e XRMUTE R11 DI XTMUTE R10 Interrupt request tiop Inter digit pause time Mute hold time Fig 4 14 5 2 Pulse output timing chart When data is written to the TCD register the specified number of pulses are output from the DP terminal At the same time XRMUTE R11 and XTMUTE R10 terminals go Low level When the pulses have been output completely the DP terminal returns to High level then the specified inter digit pause will be inserted An interrupt occurs when the inter digit pause time has passed It allows transmission of the next dial pulses The XRMUTE R11 and XTMUTE R10 terminals keep on Low level for 4 msec of mute hold time tMH after the inter digit pause is released If the next pulse output does not start in this period the XRMUTE R11 and XTMUTE R10 terminals return to High level When the next pulse output starts in the mute hold period the XRMUTE R11
285. ured using the input and output ports The hook switch should be connected to an input port The hook switch can be controlled by software this makes it possible to start calling even if the telephone is on hook Besides the above terminals The R10 to R13 terminals can be used as an XTMUTE transmitter mute signal output XRMUTE receiver mute signal output HDO hold line signal output and HFO hand free signal output These terminal functions can be configured by software See Section 4 5 Output Port This dialer has a built in interrupt circuit that can generate an interrupt when execution of a dial signal output a pause function or a flash function is completed 112 EPSON 1C63558 TECHNICAL MANUAL CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Telephone Function 4 14 2 Mask option Output specifications for the DP terminal is selected from between complementary output and Nch open drain output by mask option Since the R10 to R13 terminals are used for XTMUTE XRMUTE HDO and HFO outputs the output specifications of the output ports R10 R13 apply to their output specifications Either complementary output or Nch open drain output can be selected for each terminal by the output port mask option However even when Nch open drain output is selected voltage exceeding source voltage must not be applied to the output terminals 4 14 3 Operation of telephone function To realize the operation of the telephone function dialing
286. ut mode the register value can be read 46 EPSON 1C63558 TECHNICAL MANUAL CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION I O Ports When the terminal voltage is high VDD the port data that can be read is 1 and when the terminal voltage is low Vss the data is 0 When with pull up resistor has been selected with the mask option and the PUL register is set to 1 the built in pull up resister goes ON during input mode so that the I O port terminal is pulled up The data registers of the port which are set for the special output P22 P23 or input output of the serial interface 10 13 or P30 P33 become general purpose registers that do not affect the input output Note When in the input mode I O ports are changed from low to high by pull up resistor the rise of the waveform is delayed on account of the time constant of the pull up resistor and input gate capaci tance Hence when fetching input ports set an appropriate wait time Particular care needs to be taken of the key scan during key matrix configuration Make this waiting time the amount of time or more calculated by the following expression 10xCxR C terminal capacitance 5 pF parasitic capacitance pF pull up resistance 330 00 PO port I O control register FF40H 10 13 P1 port I O control register FF44H IOC20 1OC23 P2 port I O control register FF48H 0 3 port I O control register FF4CH
287. valid CDET goes 1 when a carrier is input When the carrier is stopped CDET returns to 0 This bit is dedicated for reading so writing can not be done At initial reset this bit is set to 0 RDETCP RDET comparison register FF67H D1 Sets a generation condition for the ring detection interrupt When 1 is written RDET falling edge When 0 is written RDET rising edge Reading Valid When RDETCP is set to 1 the ring detection interrupt is generated at the falling edge of the signal When RDETCP is 0 the interrupt is generated at the rising edge At initial reset this register is set to 0 CDETCP comparison register FF67H DO Sets a generation condition for the carrier detection interrupt When 1 is written CDET falling edge When 0 is written CDET rising edge Reading Valid When CDETCP is set to 1 the carrier detection interrupt is generated at the falling edge of the signal When CDETCP is 0 the interrupt is generated at the rising edge At initial reset this register is set to 0 EIRDET EICDET Interrupt mask registers FFEAH D1 DO Enables or disables the generation of an interrupt for the CPU When 1 is written Enabled When 0 is written Disabled Reading Valid EIRDET and EICDET are interrupt mask registers that respectively correspond to the interrupt factors for ring detection and carrier detection Interrupts set to 1 are enabled and interrupts set to 0 a
288. ven in the event counter mode Therefore be aware that the counter does not enter RUN STOP status if a clock is not input after setting the RUN STOP control register PTRUNO 3 Since the TOUT signal is generated asynchronously from the PTOUT register a hazard within 1 2 cycle is generated when the signal is turned ON and OFF by setting the register 4 When the OSC3 oscillation clock is selected for the clock source it is necessary to turn the OSC3 oscillation ON prior to using the programmable timer However the OSC3 oscillation circuit requires a time at least 5 msec from turning the circuit ON until the oscillation stabilizes Therefore allow an adequate interval from turning the OSC3 oscillation circuit ON to starting the programmable timer Refer to Section 4 3 Oscillation Circuit for the control and notes of the OSC3 oscillation circuit At initial reset the OSC3 oscillation circuit is set in the OFF state Serial interface 1 2 1 Be sure to initialize the serial interface mode in the transmit receive disabled status TXEN RXEN 0 2 Do not perform double trigger writing 1 to TXTRG RXTRG when the serial interface is in the transmitting receiving operation 3 In the clock synchronous mode since one clock line SCLK is shared for both transmitting and receiving transmitting and receiving cannot be performed simultaneously Half duplex only is possible in clock synchronous mode Consequently be sure
289. vides the following interrupt functions External interrupt Input interrupt 2 systems Internal interrupt Watchdog timer interrupt NMI 1 system D Programmable timer interrupt 2 systems Serial interface interrupt 6 systems Timer interrupt 4 systems Stopwatch timer interrupt 2 systems Dialing interrupt 1 system FSK interrupt 2 systems To authorize interrupt the interrupt flag must be set to 1 EI and the necessary related interrupt mask registers must be set to 1 enable When an interrupt occurs the interrupt flag is automatically reset to 0 DI and interrupts after that are inhibited The watchdog timer interrupt is an NMI non maskable interrupt therefore the interrupt is generated regardless of the interrupt flag setting Also the interrupt mask register is not provided However it is possible to not generate NMI since software can stop the watchdog timer operation Figure 4 16 1 shows the configuration of the interrupt circuit Note After an initial reset all the interrupts including NMI are masked until both the stack pointers SP1 and SF2 are set with the software Be sure to set the SP1 and SP2 in the initialize routine Further when re setting the stack pointer the SP1 and SP2 must be set as a pair When one of them is set all the interrupts including NMI are masked and interrupts cannot be accepted until the other one is set lt HALT gt 51 63558 has H
290. voltage detection SVD circuit 12 values programmable 2 20 V to 3 30 V It is possible to switch 1 value to the external voltage detection 1 External Input port interrupt 2 systems Internal interrupt Clock timer interrupt 4 systems Stopwatch timer interrupt 2 systems Programmable timer interrupt 2 systems Serial interface interrupt 6 systems Dialer interrupt 1 system FSK interrupt 2 systems Power supply voltage 2 2 V to 5 5 V Operating temperature range 20 C to 70 C Current consumption Typ Low speed operation OSC1 crystal oscillation During HALT 32 kHz 3 0 V LCD power OFF 15 3 0 V LCD power 4uA During operation 32 kHz 3 0 V LCD power 10 pA High speed operation OSC3 ceramic oscillation During operation 3 58 MHz 3 0 V LCD power ON 600 pA During FSK operation 5 5 V LCD power ON 1 800 pA de EUER RERO OFP15 128pin plastic or chip Can be selected with mask option 2 Can be selected with software 1C63558 TECHNICAL MANUAL EPSON 1 CHAPTER 1 OUTLINE 1 2 Block Diagram ROM 8 192 words x 13 bits System Reset Control I 1 RESET Core CPU 51 63000 861 Interrupt osea Eea OSC3 gt OSC4 Lk Stopwatch Timer RAM 5
291. writing FF5AH RXENS 0 Enable Disable Serial I F 2 receive enable TXTRGS 0 Run Stop Serial I F 2 transmit status reading R W Trigger Serial I F 2 transmit trigger writing TXENS 0 Enable Disable Serial I F 2 transmit enable 0 3 2 Unused 0 FERS PERS OERS FERS 0 Error No error Serial I F 2 framing error flag status reading Reset Serial I F 2 framing error flag reset writing FF5BH PERS 0 Error error Serial I F 2 parity error flag status reading Reset Serial I F 2 parity error flag reset writing R RW OERS 0 Error error Serial I F 2 overrun error flag status reading Reset Serial I F 2 overrun error flag reset writing TRXD 2 High L 1 TRXD3S TRXD2S TRXD1S TRXDOS li RXD2S 2 High Low FF5CH i Serial I F 2 transmit receive data low order 4 bits RW RXD1S 2 High Low TRXDOS 2 High Low LSB TRXD7 2 High L MSB TRXD7S TRXD6S TRXD5S TRXD4S be os FF5DH PADSS cs High Bu Serial I F 2 transmit receive data high order 4 bit Bi TRXD5S 2 High Low 2 high order 4 bits TRXD4S 2 High Low J LDUTY1 0 7 LCD drive duty LDUTY1 0 0 1 2 3 LDUTY1 LDUTYO Dummy LDUTYO _ switch Duty UI 1716 1 8 R Dummy 0 General purpose register m LPWR 0 On Off LCD power On Off EXLCDC 0 Enable Disable Expanded LCD driver signal control EXLCDC ALOFF ALON LPAGE ALoFF 1 AllOff Normal L
292. xt is saved in the stack area RAM 3 The interrupt request causes the value of the interrupt vector 0100 010 to be set in the program counter 4 The program at the specified address is executed execution of interrupt processing routine by software Table 4 16 3 1 shows the correspondence of interrupt requests and interrupt vectors Table 4 16 3 1 Interrupt request and interrupt vectors Interrupt vector Interrupt factor Priority 0100H Watchdog timer High 0102H Dialer FSK 0104H Programmable timer 0106H Serial interface 1 2 0108H K00 K03 input 010AH K10 K13 input 010CH Clock timer 010EH Stopwatch timer Low The four low order bits of the program counter are indirectly addressed through the interrupt request 148 EPSON 51 63558 TECHNICAL MANUAL CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Interrupt and HALT 4 16 4 I O memory of interrupt Tables 4 16 4 1 a and b show the I O addresses and the control bits for controlling interrupts Table 4 16 4 1 a Control bits of interrupt 1 Register Address Comment D3 D2 D1 DO Init 1 0 IKO Enable Disable sikoa sikoz sikot sikoo 205 0 Enable Disable SIK02 0 Enable Disable FF20H K00 K03 interrupt selection register BIN
293. y San Jose CA 95134 U S A Phone 1 408 922 0200 Fax 1 408 922 0238 SALES OFFICES West 1960 E Grand Avenue El Segundo CA 90245 U S A Phone 1 310 955 5300 Fax 1 310 955 5400 Central 101 Virginia Street Suite 290 Crystal Lake IL 60014 U S A Phone 1 815 455 7630 Fax 1 815 455 7633 Northeast 301 Edgewater Place Suite 120 Wakefield MA 01880 U S A Phone 1 781 246 3600 Fax 1 781 246 5443 Southeast 3010 Royal Blvd South Suite 170 Alpharetta GA 30005 U S A Phone 1 877 EEA 0020 Fax 1 770 777 2637 EUROPE EPSON EUROPE ELECTRONICS GmbH HEADQUARTERS Riesstrasse 15 80992 Munich GERMANY Phone 49 0 89 14005 0 Fax 49 0 89 14005 110 SALES OFFICE Altstadtstrasse 176 51379 Leverkusen GERMANY Phone 49 0 2171 5045 0 Fax 49 0 2171 5045 10 UK BRANCH OFFICE Unit 2 4 Doncastle House Doncastle Road Bracknell Berkshire RG12 8PE ENGLAND Phone 44 0 1344 381700 Fax 44 0 1344 381701 FRENCH BRANCH OFFICE 1 Avenue de Atlantique LP 915 Les Conquerants 7 de Courtaboeuf 2 F 91976 Les Ulis Cedex FRANCE Phone 33 0 1 64862350 Fax 433 0 1 64862355 BARCELONA BRANCH OFFICE Barcelona Design Center Edificio Testa Avda Alcalde Barrils num 64 68 E 08190 Sant Cugat del Vall s SPAIN Phone 34 93 544 2490 Fax 34 93 544 2491 ChaoYang District Beijing CHINA Phone 64106655 Fax 64107319 SHANGHAI BRANCH 4F Bldg 27 No 69 Gui J
294. y error When 1 is read Error When 0 is read No error When 1 is written Reset to 0 When 0 is written Invalid PER PERS is an error flag that indicates the generation of a parity error and becomes 1 when an error has been generated When a parity check is performed in the asynchronous mode a parity error will be generated if data that does not match the parity is received PER PERS is reset to 0 by writing 1 PER PERS is set to 0 at initial reset or when RXEN RXENS is set to 0 1C63558 TECHNICAL MANUAL EPSON 97 CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Serial Interface FER Serial interface 1 framing error flag FF73H D2 FERS Serial interface 2 framing error flag FF5BH D2 Indicates the generation of a framing error When 1 is read Error When 0 is read No error When 1 is written Reset to 0 When 0 is written Invalid FER FERS is an error flag that indicates the generation of a framing error and becomes 1 when an error has been generated When the stop bit for the receiving in the asynchronous mode has become 0 a framing error is gener ated FER FERS is reset to 0 by writing 1 FER FERS is set to 0 at initial reset or when RKEN RXENS is set to 0 EISRC EISTR EISER Serial interface 1 interrupt mask registers FFE3H DO D1 D2 EISRCS EISTRS EISERS Serial interface 2 interrupt mask registers FFE8H DO D1 D2 Enables or disables the generation of an i
295. y pull up resistors the rise of the waveform is delayed on account of the time constant of the pull up resistor and input gate capacitance Hence when fetching input ports set an appropriate waiting time Particular care needs to be taken of the key scan during key matrix configuration Make this waiting time the amount of time or more calculated by the following expression 10xCxR terminal capacitance 5 pF parasitic capacitance pF R pull up resistance 330 kQ 2 The K13 terminal functions as the clock input terminal for the programmable timer and the input signal is shared with the input port and the programmable timer Therefore when the K13 terminal is set to the clock input terminal for the programmable timer take care of the interrupt setting 3 After an interrupt occurs the same interrupt will occur again if the interrupt enabled state I flag 1 is set or the RETI instruction is executed unless the interrupt factor flag is reset Therefore be sure to reset write 1 to the interrupt factor flag in the interrupt service routine before shifting to the interrupt enabled state 32 EPSON 1C63558 TECHNICAL MANUAL CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Output Ports 4 5 Output Ports 00 03 10 13 and R20 R23 4 5 1 Configuration of output ports 51 63558 has 12 bits general output ports Output specifications of the output ports can be selected individually with the mask option Two kinds
296. zed when 1 is written to them and masked interrupt inhibited when 0 is written to them At initial reset the interrupt mask register is set to 0 Table 4 16 2 1 shows the correspondence between interrupt mask registers and interrupt factor flags Table 4 16 2 1 Interrupt mask registers and interrupt factor flags Interrupt mask register Interrupt factor flag EID FFE9H D0 ID 9 EIRDET FFEAH D1 IRDET FFFAH D1 EICDET FFEAH D0 ICDET FFFAH D0 EIPT1 FFE2H D1 FFF2H D1 EIPTO FFE2H DO IPTO FFF2H D0 EISER FFE3H D2 ISER 2 EISRC FFE3H D0 ISRC EISTR FFE3H D1 ISTR FFF3H D1 EISERS FFE8H D2 ISERS FFF8H D2 EISRCS FFE8H DO ISRCS FFF8H D0 EISTRS FFE8H D1 ISTRS FFF8H D1 EIKO FFE4H D0 IKO FFFA4H D0 EIK1 FFESH D0 FFF5H D0 EIT3 FFE 6H D3 IT3 FFF6H D3 EIT2 FFE6H D2 IT2 FFF6H D2 EIT1 FFE6H D1 FFF6H D1 EITO FFE6H DO ITO 6 5 FFE7H D1 5 FFF7H D1 EISW10 FFE7H D0 ISW10 FFF7H D0 4 16 3 Interrupt vector When an interrupt request is input to the CPU the CPU begins interrupt processing After the program being executed is terminated the interrupt processing is executed in the following order 1 Thecontent of the flag register is evacuated then the I flag is reset 2 The address data value of program counter of the program to be executed ne

Epson S1C63558 User's Manual

Contents

Download Pdf Manuals

Related Search

Related Contents