Cypress STK12C68-5 User's Manual
Contents
1. 4 Voc reference levels throughout this data sheet refer to VCC if that is where the power supply connection is made or Vcap if VCC is connected to ground 5 CE gt Vj does not produce standby current levels until any nonvolatile cycle in progress has timed out Document Number 001 51026 Rev Page 7 of 18 Feedback Sz CYPRESS STK12C68 5 SMD5962 94599 Data Retention and Endurance Parameter Description Min Unit DATAR Data Retention 100 Years NVo Nonvolatile STORE Operations 1 000 K Capacitance In the following table the capacitance parameters are listed 6 Parameter Description Test Conditions Max Unit Cin Input Capacitance Ta 25 C f 1 MHz 8 pF Court Output Capacitance Vcc 0 to 3 0 V 7 pF Thermal Resistance In the following table the thermal resistance parameters are listed 6 Parameter Description Test Conditions 28 CDIP 28 LCC Unit OJA Thermal Resistance Test conditions follow standard test methods and TBD TBD C W Junction to Ambient procedures for measuring thermal impedance per Ojc Thermal Resistance EIA JESD51 TBD TBD C W Junction to Case Figure 7 AC Test Loads R1 963Q R1 9632 For Tri state Specs 5 0V 5 0V Output Output R2 5 pF R2 30 pF 5120 5120 AC Test Conditions Input Pulse Levels ce eeseeeeeeeeseeeeeeneeeeeeeeeeneeeees OV to 3V Input Rise and Fall Tim2. _ G aan CYPRESS PERFORM E Features m 35 ns and 55 ns access times m Hands off automatic STORE on power down with external 68 uF capacitor m STORE to QuantumTrap nonvolatile elements is initiated by software hardware or AutoStore on power down m RECALL to SRAM initiated by software or power up m Unlimited Read Write and Recall cycles m 1 000 000 STORE cycles to QuantumTrap m 100 year data retention to QuantumTrap m Single 5V 10 operation m Military temperature STK12C68 5 SMD5962 94599 64 Kbit 8K x 8 AutoStore nvSRAM Functional Description The Cypress STK12C68 5 is a fast static RAM with a nonvol atile element in each memory cell The embedded nonvolatile elements incorporate QuantumTrap technology producing the world s most reliable nonvolatile memory The SRAM provides unlimited read and write cycles while independent nonvolatile data resides in the highly reliable QuantumTrap cell Data transfers from the SRAM to the nonvolatile elements the STORE operation takes place automatically at power down On power up data is restored to the SRAM the RECALL operation from the nonvolatile memory Both the STORE and RECALL operations are also available under software control A hardware STORE is initiated with the HSB pin m 28 pin 300mil CDIP and 28 pad LCC packages Logic Block Diagram l ROW DECODER STATIC RAM
3. Feedback CYPRESS 4 Read address 0x1FFF Valid READ 5 Read address 0x10F0 Valid READ 6 Read address OxOFOE Initiate RECALL cycle Internally RECALL is a two step procedure First the SRAM data is cleared then the nonvolatile information is transferred into the SRAM cells After the trecatt cycle time the SRAM is again ready for Read and Write operations The RECALL operation does not alter the data in the nonvolatile elements The nonvol atile data can be recalled an unlimited number of times Data Protection The STK12C68 5 protects data from corruption during low voltage conditions by inhibiting all externally initiated STORE and Write operations The low voltage condition is detected when Vec is less than Vswitcu If the STK12C68 5 is in a Write mode both CE and WE are low at power up after a RECALL or aftera STORE the Write is inhibited until a negative transition onCE or WE is detected This protects against inadvertent writes during power up or brown out conditions Noise Considerations The STK12C68 5 is a high speed memory It must have a high frequency bypass capacitor of approximately 0 1 uF connected between Vcc and Vss using leads and traces that are as short as possible As with all high speed CMOS ICs careful routing of power ground and signals reduce circuit noise Hardware Protect The STK12C68 5 offers hardware protection against inadvertent STORE operation and SRAM Writes during low voltage co
4. LOW it allows a time tpeLay to complete However any SRAM Write cycles requested after HSB goes LOW are inhibited until HSB returns HIGH Document Number 001 51026 Rev STK12C68 5 SMD5962 94599 During any STORE operation regardless of how it is initiated the STK12C68 5 continues to drive the HSB pin LOW releasing it only when the STORE is complete After completing the STORE operation the STK12C68 5 remains disabled until the HSB pin returns HIGH If HSB is not used it is left unconnected Hardware RECALL Power Up During power up or after any low power condition Vcc lt VpeserT an internal RECALL request is latched When Vcc once again exceeds the sense voltage of Vewitcu a RECALL cycle is automatically initiated and takes tyReca to complete If the STK12C68 5 is in a Write state at the end of power up RECALL the SRAM data is corrupted To help avoid this situation a 10 Kohm resistor is connected either between WE and system Vcc or between CE and system Vcc Software STORE Data is transferred from the SRAM to the nonvolatile memory by a software address sequence The STK12C68 5 software STORE cycle is initiated by executing sequential CE controlled Read cycles from six specific address locations in exact order During the STORE cycle an erase of the previous nonvolatile data is first performed followed by a program of the nonvolatile elements When a STORE cycle is initiated input and output are disabled
5. Pin Name Alt IO Type Description Ao A12 Input Address Inputs Used to select one of the 8 192 bytes of the nvSRAM DQo DQ7 Input or Output Bidirectional Data IO Lines Used as input or output lines depending on operation WE W Input Write Enable Input Active LOW When the chip is enabled and WE is LOW data on the IO pins is written to the specific address location CE E Input Chip Enable Input Active LOW When LOW selects the chip When HIGH deselects the chip OE G Input Output Enable Active LOW The active LOW OE input enables the data output buffers during read cycles Deasserting OE HIGH causes the IO pins to tri state Vss Ground Ground for the Device The device is connected to ground of the system Vec Power Supply Power Supply Inputs to the Device HSB Input or Output Hardware Store Busy HSB When LOW this output indicates a Hardware Store is in progress When pulled low external to the chip it initiates a nonvolatile STORE operation A weak internal pull up resistor keeps this pin high if not connected connection optional VcaP Power Supply AutoStore Capacitor Supplies power to nvSRAM during power loss to store data from SRAM to nonvolatile elements Document Number 001 51026 Rev Page 2 of 18 Feedback CYPRESS Device Operation The STK12C68 5 nvSRAM is made up of two functional compo nents paired in the same physical cell These are an SRAM memory cell and a nonvolatile Quan
6. Vreser 13 turecact Starts from the time Vcc rises above VewitcH 14 CE and OE low for output behavior 15 CE and OE low and WE high for output behavior BROWN OUT AutoStore RECALL WHEN Vcc RETURNS ABOVE VSWITCH 16 HSB is asserted low for 1us when Vcap drops through Vewitcn If an SRAM Write has not taken place since the last nonvolatile cycle HSB is released and no store takes place Document Number 001 51026 Rev Page 11 of 18 Feedback CYPRESS Software Controlled STORE RECALL Cycle The software controlled STORE RECALL cycle follows l8 STK12C68 5 SMD5962 94599 Switching Waveform ADDRESS DQ DATA Notes Figure 13 CE Controlled Software STORE RECALL Cycle 8l trc gt ADDRESS 1 x gt 35 ns 55 ns Parameter Alt Description Unit Min Max Min Max trc tavay STORE RECALL Initiation Cycle Time 35 55 ns tsal taveL Address Setup Time 0 0 ns tow TELEH Clock Pulse Width 25 30 ns tHacel tELAX Address Hold Time 20 20 ns tRECALL RECALL Duration 20 20 us lt tre j ADDRESS 6 X DATA VALID DATA VALI D gt A lt lt tstore treca gt 17 The software sequence is clocked on the falling edge of CE without involving OE double clocking aborts the sequence 18 The six consecutive addresses must be read in the order listed in Table 1 o
7. finish C Gold lead DIP finish X Lead finish A or C is acceptable Case Outline X Ceramic 28 pin 300 mil DIP Y Ceramic 28 pin LLC Device Class Indicator Class M Device Type 01 55ns 03 35 ns Document Number 001 51026 Rev Page 14 of 18 Feedback CYPRESS Ordering Information STK12C68 5 SMD5962 94599 Speed ns Ordering Code Package Diagram Package Type Operating Range 35 STK12C68 5C35M 001 51695 28 pin CDIP 300 mil Military STK12C68 5K35M 001 51695 28 pin CDIP 300 mil STK12C68 5L35M 001 51696 28 pin LCC 350 mil 55 STK12C68 5C55M 001 51695 28 pin CDIP 300 mil STK12C68 5K55M 001 51695 28 pin CDIP 300 mil STK12C68 5L55M 001 51696 28 pin LCC 350 mil The above table contains Final information Contact your local Cypress sales representative for availability of these parts Document Number 001 51026 Rev Page 15 of 18 Feedback PERFORM Package Diagrams Figure 15 28 Pin 300 Mil Side Braze DIL 001 51695 ____ 1389 3843 INDEX a be 0 060 1 52 N l 24 3 md be E ALL DIMENSIONS ARE IN MILLIMETERS AND INCHS MIN MAX ACKAGE WEICHT TI EDEC REFERENCE MO 058 Document Number 001 51026 Rev oS CYPRESS STK12C68 5 SMD5962 94599
8. 001 51695 Page 16 of 18 Feedback CYPRESS ERFORM Package Diagrams continued STK12C68 5 SMD5962 94599 Figure 16 28 Pad 350 Mil LCC 001 51696 1 ALL DIMENSION ARE IN INCHES AND MILLIMETERS MIN MAX 2 JEDEC 95 OUTLINE MO 041 3 PACKAGE WEIGHT TBD Document Number 001 51026 Rev N qt Aaollo 4 aa oy etal 001 51696 Page 17 of 18 Feedback CYPRESS STK12C68 5 SMD5962 94599 PERFORM Document History Page Document Title STK12C68 5 SMD5962 94599 64 Kbit 8K x 8 AutoStore nvSRAM Document Number 001 51026 Orig of Submission Rev ECN No Change Date 2666844 GVCH PYRS 03 02 09 New data sheet Description of Change Sales Solutions and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices solution centers manufacturer s representatives and distributors To find the office closest to you visit us at cypress com sales Products PSoC Solutions PSoC psoc cypress com General psoc cypress com solutions Clocks amp Buffers clocks cypress com Low Power Low Voltage psoc cypress com low power Wireless wireless cypress com Precision Analog psoc cypress com precision analog Memories memory cypress com LCD Drive psoc cypress com cd drive Image Sensors image cypress
9. 5 5V M Parameter Description Test Conditions Min Max Unit loci Average Vcc Current tac 35 ns 75 mA trc 55ns 55 mA Dependent on output loading and cycle rate Values obtained without output loads lout 0mA loce Average Vcc Current All Inputs Do Not Care Voc Max 3 mA during STORE Average current for duration tstorE locg Average Vcc Currentat WE gt Vcc 0 2V All other inputs cycling 10 mA trc 200 ns 5V 25 C Dependent on output loading and cycle rate Values Typical obtained without output loads loca Average Vcap Current All Inputs Do Not Care Veg Max 2 mA during AutoStore Cycle Average current for duration tstorE Isp Vcc Standby Current tac 35 ns CE gt Viy 24 mA Standby Cycling TTL Itre 55 ns CE gt Viy 19 mA Input Levels lope P Voc Standby Current CE gt Voc 0 2V All others Viy lt 0 2V or gt Vcc 0 2V 2 5 mA Standby current level after nonvolatile cycle is complete Inputs are static f 0 MHz lix Input Leakage Current Vcc Max Vss lt Vin lt Vcc 1 1 uA loz Off State Output Vec Max Vss lt Vin lt Voc CE or OE gt Vin or WE lt Vi 5 5 uA Leakage Current Vin Input HIGH Voltage 2 2 Voc 0 5 V Vit Input LOW Voltage Vss 0 5 0 8 V VoH Output HIGH Voltage lour 4 mA 2 4 V VoL Output LOW Voltage lour 8 mA 0 4 V VBL Logic 0 Voltage on lout 3 mA 0 4 V HSB Output Vcap Storage Capacitor Between Vcap pin and Vss 6V rated 68 uF 20 nom 54 260 uF Notes
10. ARRAY 128 X 512 Quantum Trap 128 X 512 STORE 7 RECALL Vcc Veap tt POWER CONTROL lt STORE RECALL lt _ _ CONTROL gt COLUMN I O Da lt gt HSB SOFTWARE DETECT COLUMN DEC DQ Da DQ DQ Ao Ai Az As A4 Ato INPUT BUFFERS Da Wy aabo say wl AK ro Ao A al ae am Cypress Semiconductor Corporation Document Number 001 51026 Rev 198 Champion Court San Jose CA 95134 1709 7 408 943 2600 Revised March 02 2009 Feedback CYPRESS STK12C68 5 SMD5962 94599 Pinouts Figure 1 Pin Diagram 28 Pin DIP Figure 2 Pin Diagram 28 Pin LLC S i 8 E gt gt C SE lt 1 1 gt gt Var C1 O Vec FIV S N a Ce We 3 2 hI 28 27 A Cos TSE As 4 260 HSB A 4 Ay As Js 25 As i As As 6 24C As N ii A3 7 23 Au aL Top View OE i i p Ra A gt Js TOP 200E A s Not To Scale zE Ay D 9 21 A ipa 4 a Ao 10 200 CE chile pos DQo 11 19 DQ pai J12 Das paz 13 pas DQ J12 18C DQs Vss 14 pas 13 14 15 16 1 NS fA TS S8dgs ra gt dA Pin Definitions
11. DQ DATA OUT gt lt DATA VALID lt tpu ACTIVE icc STANDBY 7 Notes _ ae 7 WE and HSB must be High during SRAM Read cycles 8 Device is continuously selected with CE and OE both Low 9 Measured 200 mV from steady state output voltage Document Number 001 51026 Rev Page 9 of 18 Feedback CYPRESS STK12C68 5 SMD5962 94599 SRAM Write Cycle Parameter 35 ns 55 ns EvE Alt Deseupien Min Max Min Max unit twe tavav Write Cycle Time 35 55 ns tpwe twLWH tWLEH Write Pulse Width 25 45 ns tsce TELWH teLEH Chip Enable To End of Write 25 45 ns tsp DVWH DVEH Data Setup to End of Write 12 25 ns tub tWHDx teHpx Data Hold After End of Write 0 0 ns taw tavwu taveH Address Setup to End of Write 25 45 ns tsa tavw_ taveL Address Setup to Start of Write 0 0 ns tua twHax tEHAX Address Hold After End of Write 0 0 ns tHZWE 9 10 twLaz Write Enable to Output Disable 13 15 ns tLZWE twHax Output Active After End of Write 5 5 ns Switching Waveforms Figure 10 SRAM Write Cycle 1 WE Controlled 1 121 lt twe ADDRESS ae I lt tsce gt CE w gt tsa mena lt tewe gt WE lt tsp gt lt tuo DATA IN DATA VALID lt t n p2 tise gt HIGH IMPEDANCE DATA OUT PREVIOUS DATA Figure 11 SRAM Write Cycl
12. STORE function is disabled by holding HSB high with a driver capable of sourcing 30 mA at a Voy of at least 2 2V because it must_overpower the internal pull down device This device drives HSB LOW for 20 us at the onset of a STORE When the STK12C68 5 is connected for AutoStore operation system Vcc connected to Vcc and a 68 uF capacitor on Vcap and Vcc crosses Vswitcy onthe way down the STK12C68 5 attempts to pull HSB LOW If HSB does not actually get below Vi the part stops trying to pull HSB LOW and abort the STORE attempt Page 5 of 18 Feedback CYPRESS Best Practices nvSRAM products have been used effectively for over 15 years While ease of use is one of the product s main system values experience gained working with hundreds of applica tions has resulted in the following suggestions as best practices m The nonvolatile cells in an nvSRAM are programmed on the test floor during final test and quality assurance Incoming inspection routines at customer or contract manufacturer s sites sometimes reprograms these values Final NV patterns are typically repeating patterns of AA 55 00 FF A5 or 5A The end product s firmware must not assume that an NV array is in a set programmed state Routines that check memory content values to determine first time system config uration cold or warm boot status and so on must always program a unique NV pattern for example complex 4 byte pattern of 46 E6 49 53 hex or more r
13. andom bytes as part of the final system manufacturing test to ensure these system routines work consistently Table 1 Hardware Mode Selection STK12C68 5 SMD5962 94599 m Power up boot firmware routines must rewrite the nvSRAM into the desired state While the nvSRAM is shipped in a preset state best practice is to again rewrite the nvSRAM into the desired state as a safeguard against events that might flip the bit inadvertently program bugs incoming inspection routines and so on m The Vcap value specified in this data sheet includes a minimum and a maximum value size The best practice is to meet this requirement and not exceed the maximum Vcap value because the higher inrush currents may reduce the reliability of the internal pass transistor Customers who want to use a larger Vcap value to make sure there is extra store charge must discuss their Vcap size selection with Cypress Notes __ CE WE SB A12 A0 Mode IO Power H X H X Not Selected Output High Z Standby L H H X Read SRAM Output Data Active L L H X Write SRAM Input Data Active X X L x Nonvolatile STORE Output High Z local L H H 0x0000 Read SRAM Output Data Active Icgal 3l 0x1555 Read SRAM Output Data OxOAAA Read SRAM Output Data Ox1FFF Read SRAM Output Data 0x10FO Read SRAM Output Data OxOFOF Nonvolatile STORE Output High Z L H H 0x0000 Read SRAM Output Data Activel2 3l 0x1555 Read SRAM Output Data Ox0AAA Read SRAM Out
14. arks of their respective holders Feedback
15. com CAN 2 0b psoc cypress com can USB psoc cypress com usb Cypress Semiconductor Corporation 2009 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Any Source Code software and or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign United States copyright laws and international treaty provisions Cypress hereby grants to licensee a personal non exclusive non transferable license to copy use modify create derivative works of and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and o
16. cycle The data on the common IO pins DQ o 7 are written into the memory if it has valid tgp before the end of a WE controlled Write or before the end of an CE controlled Write Keep OE HIGH during the entire Write cycle to avoid data bus contention on common IO lines If OE is left LOW internal circuitry turns off the output buffers tuzwe after WE goes LOW AutoStore Operation The STK12C68 5 stores data to nvSRAM using one of three storage operations 1 Hardware store activated by HSB 2 Software store activated by an address sequence 3 AutoStore on device power down AutoStore operation is a unique feature of QuantumTrap technology and is enabled by default on the STK12C68 5 Document Number 001 51026 Rev STK12C68 5 SMD5962 94599 During normal operation the device draws current from Vcc to charge a capacitor connected to the Vcap pin This stored charge is used by the chip to perform a single STORE operation If the voltage on the Vcc pin drops below Vswitcu the part automatically disconnects the Vca p pin from Voc A STORE operation is initiated with power provided by the Vcap capacitor Figure 3 shows the proper connection of the storage capacitor Vcap for automatic store operation A charge storage capacitor between 68 UF and 220 uF 20 rated at 6V must be provided The voltage on the Vcap pin is driven to 5V by a charge pump internal to the chip A pull up is placed on WE to hold it inactive during power
17. e 2 CE Controlled l1 121 lt twe gt ADDRESS X lt tsa gt tsce tha CE lt taw WE N tewe k lt tsp gt tuo DATAIN DATA VALID DATA OUT HIGH IMPEDANCE Notes 10 If WE is Low when CE goes Low the outputs remain in the high impedance state 11 HSB must be high during SRAM Write cycles 12 CE or WE must be greater than Vj during address transitions Document Number 001 51026 Rev Page 10 of 18 Feedback PE aa E 7j CYPRES PERFORM STK12C68 5 SMD5962 94599 AutoStore or Power Up RECALL Parameter Alt Description SUS esl Unit Min Max tHRECALL 13 tRESTORE Power up RECALL Duration 550 us tstore 4 1 gt 161 tHLHz STORE Cycle Duration 10 ms tperay gt 191 thLaz teraz Time Allowed to Complete SRAM Cycle 1 us VswitcH Low Voltage Trigger Level 4 0 4 5 V VRESET Low Voltage Reset Level 3 9 V VCCRISE Voc Rise Time 150 us tsp Low Voltage Trigger Vswitcy to HSB Low 300 ns Switching Waveform Figure 12 AutoStore Power Up RECALL Voc Veeser AutoStore POWER UP RECALL ee TarecaLe tsar tstorz HSB Teis WE DQ DATA OUT gt lt a POWER UP RECALL Notes BROWN OUT NO STORE NO SRAM WRITES BROWN OUT AutoStore NO RECALL Vcc DID NOT GO BELOW Vreser NO RECALL Vcc DID NOT GO BELOW
18. es 10 to 90 essere lt 5 ns Input and Output Timing Reference Levels 008 1 5 Note 6 These parameters are guaranteed by design and are not tested Document Number 001 51026 Rev Page 8 of 18 Feedback CYPRESS AC Switching Characteristics SRAM Read Cycle STK12C68 5 SMD5962 94599 Parameter 35 ns 55 ns Description Unit ey ree Alt j Min Max Min Max tACE teLav Chip Enable Access Time 35 55 ns tRC 7 tavay tELEH Read Cycle Time 35 55 ns taa 8 tavav Address Access Time 35 55 ns tDOE teLav Output Enable to Data Valid 15 35 ns TOHA Bl taxax Output Hold After Address Change 5 5 ns tLzcE D teELQX Chip Enable to Output Active 5 5 ns tuzce 9 teHaz Chip Disable to Output Inactive 10 12 ns tLZ0E 19 teLax Output Enable to Output Active 0 0 ns tuZ0E DI teHaz Output Disable to Output Inactive 10 12 ns tpu 6 tELICCH Chip Enable to Power Active 0 0 ns tpp 6 tEHICCL Chip Disable to Power Standby 35 55 ns Switching Waveforms Figure 8 SRAM Read Cycle 1 Address Controlled 81 lt tre gt ADDRESS lt taa lt tona DQ DATA OUT DATA VALID gt lt gt lt Figure 9 SRAM Read Cycle 2 CE and OE Controlled l LRC ADDRESS o lt tace gt k tpo gt CE lt tizce gt y tuzce gt OE TE N tuzoe gt tizoe
19. n page 6 WE must be HIGH during all six consecutive cycles Document Number 001 51026 Rev HIGH IMPEDANCE Page 12 of 18 Feedback CYPRESS STK12C68 5 SMD5962 94599 Hardware STORE Cycle Parameter Alt Description aristeuees Unit Min Max tstone 141 tuLHz STORE Cycle Duration 10 ms tDHSB 14 19 RECOVER tHHax Hardware STORE High to Inhibit Off 700 ns tpHsB tuLHx Hardware STORE Pulse Width 15 ns tuLBL Hardware STORE Low to STORE Busy 300 ns Switching Waveform HSB IN HSB OUT DQ DATA OUT Note Figure 14 Hardware STORE Cycle buss lt tstore gt lt thue gt HIGH IMPEDANCE lt toerav gt DATA VALID HIGH IMPEDANCE 19 tpysp is only applicable after tstore is complete Document Number 001 51026 Rev gt lt Dama VALID Page 13 of 18 Feedback CYPRESS STK12C68 5 SMD5962 94599 Part Numbering Nomenclature STK12C68 5 C 35 M Temperature Range M Military 55 to 125 C Speed 35 35 ns 55 55 ns Package C Ceramic 28 pin 300 mil DIP gold lead finish K Ceramic 28 pin 300 mil DIP Solder dip finish L Ceramic 28 pin LLC Retention Endurance 5 Military 10 years or 10 cycles SMD5962 94599 01 MX X Lead Finish A Solder DIP lead
20. ndi tions When Vcap lt Vswitcu all externally initiated STORE operations and SRAM Writes are inhibited AutoStore can be completely disabled by tying VCC to ground and applying 5V to Vcap This is the AutoStore Inhibit mode in this mode STOREs are only initiated_by explicit request using either the software sequence or the HSB pin Low Average Active Power CMOS technology provides the STK12C68 5 the benefit of drawing significantly less current when it is cycled at times longer than 50 ns Figure 5 and Figure 6 shows the relationship between Icc and Read or Write cycle time Worst case current consumption is shown for both CMOS and TTL input levels commercial temperature range VCC 5 5V 100 duty cycle on chip enable Only standby current is drawn when the chip is disabled The overall average current drawn by the STK12C68 5 depends on the following items m The duty cycle of chip enable m The overall cycle rate for accesses m The ratio of Reads to Writes m CMOS versus TTL input levels m The operating temperature m The Vcc level Document Number 001 51026 Rev STK12C68 5 SMD5962 94599 Figure 5 Current Versus Cycle Time Read lt S E 5 60 S g g 40 D i o TTL lt 20 CMOS 0 50 100 150 200 Cycle Time ns Figure 6 Current Versus Cycle Time Write 100 80 E 60 3 TTI R l 2 40 S a CMOS Zz 20 0 L 50 100 150 200 Cycle Time ns Preventing Store The
21. ore Inhibit Mode If an automatic STORE on power loss is not required then Voc is tied to ground and 5V is applied to Vcap Figure 4 This is the AutoStore Inhibit mode where the AutoStore function is disabled If the STK12C68 5 is operated in this configuration references to Vcc are changed to Vcap throughout this data sheet In this mode STORE operations are triggered through software control or the HSB pin To enable or disable Autostore using an IO port pin see Preventing Store on page 5 It is not permissible to change between these three options on the fly Hardware STORE HSB Operation The STK12C68 5 provides the HSB pin for_controlling and acknowledging the STORE operations The HSB pin is used to request a hardware STORE cycle When the HSB pin is driven LOW the STK12C68 5 conditionally initiates a STORE operation after tpg ay An actual STORE cycle only begins if a Write to the SRAM _takes place since the last STORE or RECALL cycle The HSB pin also acts as an open drain driver that is internally driven LOW to indicate a busy condition while the STORE initiated by any means is in progress SRAM Read and Write operations that are in progress when HSB is driven LOW by any means are given time to complete before the STORE operation is initiated After HSB goes LOW the STK12C68 5 continues SRAM operations for tpeLay During tpeLay Multiple SRAM Read operations take place If a Write is in progress when HSB is pulled
22. put Data Ox1FFF Read SRAM Output Data 0x10FO Read SRAM Output Data OxOFOE Nonvolatile RECALL Output High Z 1 HSB STORE operation occurs only if an SRAM Write is done since the last nonvolatile cycle After the STORE If any completes the part goes into standby mode inhibiting all operations until HSB rises 2 The six consecutive addresses must be in the order listed WE must be high during all six consecutive CE controlled cycles to enable a nonvolatile cycle 3 1O state assumes OE lt Vq Activation of nonvolatile cycles does not depend on state of OE Document Number 001 51026 Rev Page 6 of 18 Feedback CYPRESS STK12C68 5 SMD5962 94599 Maximum Ratings Exceeding maximum ratings may shorten the useful life of the Voltage on DQo 7 Or HSB eee eee 0 5V to Vcc 0 5V Power DiSSipatiOn cceecceeeseeeeeeneeeeseeeeeeneeeeseneeteees 1 0W device These user guidelines are not tested DC output Current 1 output at a time 1s duration 15 mA Storage Temperature cece 65 C to 150 C Operating Range Temperature under Bias ieee 55 C to 125 C Voltage on Input Relative to GND seee 0 5V to 7 0V Range __ Ambient Temperature Vcc Voltage on Input Relative to Vss 0 6V to Voc 0 5V Military 55 C to 125 C FIV ICSB DC Electrical Characteristics Over the operating range Vcc 4 5V to
23. r firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement Any reproduction modification translation compilation or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Cypress reserves the right to make changes without further notice to the materials described herein Cypress does not assume any liability arising out of the application or use of any product or circuit described herein Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress product in a life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Use may be limited by and subject to the applicable Cypress software license agreement Document Number 001 51026 Rev Revised March 02 2009 Page 18 of 18 AutoStore and QuantumTrap are registered trademarks of Cypress Semiconductor Corporation All products and company names mentioned in this document may be the tradem
24. tumTrap cell The SRAM memory cell operates as a standard fast static RAM Data in the SRAM is transferred to the nonvolatile cell the STORE operation or from the nonvolatile cell to SRAM the RECALL operation This unique architecture enables the storage and recall of all cells in parallel During the STORE and RECALL operations SRAM Read and Write operations are inhibited The STK12C68 5 supports unlimited reads and writes similar to a typical SRAM In addition it provides unlimited RECALL opera tions from the nonvolatile cells and up to one million STORE operations SRAM Read The STK12C68 5 performs a Read cycle whenever CE and OE are LOW while WE and HSB are HIGH The address specified on pins Ap_42 determines the 8 192 data bytes accessed When the Read is initiated by an address transition the outputs are valid_after_a delay of tan Read cycle 1 If the Read is initiated by CE or OE the outputs are valid at tace or at tpog whichever is later Read cycle 2 The data outputs repeatedly respond to address changes within the ta access time without the need for transitions on any control input_pins and remains valid until another address change or until CE or OE is brought HIGH or WE or HSB is brought LOW SRAM Write A Write cycle is performed whenever CE and WE are LOW and HSB is HIGH The address inputs must be stable prior to entering the Write cycle and must remain stable until either CE or WE goes HIGH at the end of the
25. until the cycle is completed Because a sequence of Reads from specific addresses is used for STORE initiation it is important that no other Read or Write accesses intervene in the sequence If they intervene the sequence is aborted and no STORE or RECALL takes place To initiate the software STORE cycle the following Read sequence is performed 1 Read address 0x0000 Valid READ 2 Read address 0x1555 Valid READ 3 Read address Ox0AAA Valid READ 4 Read address 0x1FFF Valid READ 5 Read address 0x10F0 Valid READ 6 Read address OxOFOF Initiate STORE cycle The software sequence is clocked with CE controlled Reads or OE controlled Reads When the sixth address in the sequence is entered the STORE cycle commences and the chip is disabled It is important that Read cycles and not Write cycles are used in the sequence It is not necessary that OE is LOW for a valid sequence After the tstore cycle time is fulfilled the SRAM is again activated for Read and Write operation Software RECALL Data is transferred from the nonvolatile memory to the SRAM by a software address sequence A software RECALL cycle is initiated with a sequence of Read operations in a manner similar to the software STORE initiation To initiate the RECALL cycle the following sequence of CE controlled Read operations is performed 1 Read address 0x0000 Valid READ 2 Read address 0x1555 Valid READ 3 Read address OxOAAA Valid READ Page 4 of 18
26. up Figure 3 AutoStore Mode 10k Ohm NM 10k Ohm Vow we Vcc WE HSB 68 uF 6v 20 DH O0 1u F Bypass 1 Vss In system power mode both Vcc and Vcap are connected to the 5V power supply without the 68 uF capacitor In this mode the AutoStore function of the STK12C68 5 operates on the stored system charge as power goes down The user must however guarantee that Vcc does not drop below 3 6V during the 10 ms STORE cycle To reduce unnecessary nonvolatile stores AutoStore and Hardware Store operations are ignored unless at least one Write operation has taken place since the most recent STORE or RECALL cycle Software initiated STORE cycles are performed regardless of whether a Write operation has taken place An optional pull up resistor is shown connected to HSB The HSB signal is monitored by the system to detect if an AutoStore cycle is in progress Page 3 of 18 Feedback CYPRESS Figure 4 AutoStore Inhibit Mode T n set TaT E oR O z 17h Vor Vec E s x WE HSB Vss V If the power supply drops faster than 20 us volt before Vcc reaches Vswitcu then a 2 2 ohm resistor must be connected between Vcc and the system supply to avoid momentary excess of current between Vcc and Vear AutoSt
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