Cypress Perform CY62147EV30 User's Manual
Contents
1. 45 ns Ind l Auto A 55 ns Auto E Parameter Description Unit Min Max Min Max Read Cycle Read Cycle Time 45 55 ns Address to Data Valid 45 55 ns Data Hold from Address Change 10 10 ns tace CE LOW to Data Valid 45 55 ns ipo OE LOW to Data Valid 22 25 ns lizoE OE LOW to LOW 214 5 5 ns tuzoE OE HIGH to High 704 15 18 20 ns lizcE CE LOW to Low 214 10 10 ns tuzcE CE HIGH to High 211 15 18 20 ns tpy CE LOW to Power Up 0 0 ns tpp CE HIGH to Power Down 45 55 ns BLE BHE LOW to Data Valid 45 55 ns LZBE BLE BHE LOW to Low 2114 10 10 ns tuzBE BLE BHE HIGH to HIGH 204 15 18 20 ns Write Cyclel 6 twc Write Cycle Time 45 55 ns tsce CE LOW to Write End 35 40 ns taw Address Setup to Write End 35 40 ns tHa Address Hold from Write End 0 0 ns tsa Address Setup to Write Start 0 0 ns tpwe WE Pulse Width 35 40 ns tew BLE BHE LOW to Write End 35 40 ns tsp Data Setup to Write End 25 25 ns tup Data Hold from Write End 0 0 ns tuzwe WE LOW High z 4 15 18 20 ns tizwE WE HIGH to Low z 41 10 10 ns Notes 12 Test conditions for all parameters other than tri state parameters assume signal transition time of 3 ns 1V ns or less timing reference levels of 2 input pulse levels of 0 to Vecityp and output loading of the specified as shown in the AC Test Load and Waveforms on page 4 13 AC timing parameters are subject to byte enable signa2. OE BHE BLE lOs Mode Power H X X X X HighZ Deselect Power Down Standby lag L X X H H Deselect Power Down Standby lag L H L L L Out IO l015 Read Active Icc L H L H L Data Out 10 107 Read Active loc IOg 1O45 in High 2 L H L L H Out lOg 1O 5 Read Active loc 100 105 in High 2 L H H L L High Z Output Disabled Active loc L H H H L High Z Output Disabled Active loc L H H L H High Z Output Disabled Active loc L L x L L Data In IOg 1O 5 Write Active Icc L L X H L Data In IOg 1O Write Active loc IOg 1O s in High Z L L X L H Data In lOg lO 5 Write Active loc 105 105 in High Z Ordering Information ye Ordering Code Dr Package Type 45 CY62147EV30LL 45BVI 51 85150 48 Ball Very Fine Pitch Ball Grid Array 23 Industrial CY62147EV30LL 45BVXI 51 85150 48 Ball Very Fine Pitch Ball Grid Array Pb Free 23 CY62147EV30LL 45B2XI 51 85150 48 Ball Very Fine Pitch Ball Grid Array Pb Free 241 CY62147EV30LL 45ZSXI 51 85087 44 Pin Thin Small Outline Package II Pb Free CY62147EV30LL 45BVXA 51 85150 48 Ball Very Fine Pitch Ball Grid Array Pb Free 1231 Automotive A CY62147EV30LL 45ZSXA 51 85087 44 Pin Thin Small Outline Package Pb Free 55 CY62147EV30LL 55ZSXE 51 85087 44 Pin Thin Small Outline Package II Pb Free Automotive E Contact your local Cypress sales representative for availability o
3. 9 He rs o Os Oe o a x 898209 5 0906906909 Figure 3 44 Pin TSOP 44 5 12 43 2 3 42 Az 04 41 O OE Ao 5 40 BHE CE O 6 39 BLE IOo O 7 38 lO45 IO 8 37 LJ lO44 102 19 36 O 1043 110 35 1040 Vcc 11 34 Vss Vss 112 33 Voc 1O4 113 32 1 IO 105 114 31 0 lOs 115 30 109 107 116 29 WE 117 28 NC A17 118 27 Ag Ais 19 26 O Ag 15 120 25 O Ajo 14 121 24 Aq A13 22 23 Notes 2 Typical values are included for reference only and are not guaranteed or tested Typical values are measured at Voc Ta 25 3 NC pins are not connected on the die 4 Pins H1 G2 and H6 in the BGA package are address expansion pins for 8 Mb 16 Mb and 32 Mb respectively Document 38 05440 Rev G Page 2 of 13 Feedback Cypress PERFORM Maximum Ratings Exceeding the maximum ratings may impair the useful life of the device User guidelines are not Storage Temperature Ambient Temperature with Power Applied Supply Voltage to Ground tested 65 C to 150 C 55 C to 125 C CY62147EV30 MoBL DC Input Voltage 8 0 3V to 3 9V 0 3V Output Current i
4. m Both Byte High Enable and Byte Low Enable are disabled BHE BLE HIGH m Write operation is active CE LOW and WE LOW To write to the device take Chip Enable CE and Write Enable WE inputs LOW If Byte Low Enable BLE is LOW then data from IO pins lOg through 107 is written into the location specified the address pins Ag through A47 If Byte High Enable is LOW then data from IO pins through IO 5 is written into the location specified on the address pins Ao through A47 To read from the device take Chip Enable CE and Output Enable OE LOW while forcing the Write Enable WE HIGH If Byte Low Enable BLE is LOW then data from the memory location specified by the address pins appear on to IO If Byte High Enable BHE is LOW then data from memory appears lOg to 015 See the Truth Table on page 9 for a complete description of read and write modes For best practice recommendations refer to the Cypress application note AN1064 SRAM System Guidelines Logic Block Diagram DATA IN DRIVERS 4 lt ROW DECODER 256K x 16 RAM Array 45 10 10 SENSE AMPS 45 10 1015 COLUMN DECODER CH POWER DOWN gt gt BHE CIRCUIT rY Ose en H EE Note 1 BGA packaged device is offered in si
5. M NJ CYPRESS Features m Very high speed 45 ns m Temperature ranges Industrial 40 C to 85 C Automotive A 40 to 85 C Automotive E 40 to 125 C m Wide voltage range 2 20V to 3 60V m Pin compatible with CY62147DV30 m Ultra low standby power Typical standby current 1 pA Maximum standby current 7 uA Industrial m Ultra low active power Typical active current 2 mA at f 1 MHz m Easy memory expansion with CE l and OE features m Automatic power down when deselected m CMOS for optimum speed and power m Available in Pb free 48 ball VFBGA single dual CE option and 44 pin TSOPII packages m Byte power down feature Functional Description The CY62147EV30 is a high performance CMOS static RAM organized as 256K words by 16 bits This device features advanced circuit design to provide ultra low active current It is CY62147EV30 MoBL 4 Mbit 256K x 16 Static RAM ideal for providing More Battery Life MoBL in portable appli cations such as cellular telephones The device also has an automatic power down feature that significantly reduces power consumption when addresses are not toggling Placing the device into standby mode reduces power consumption by more than 99 when deselected CE HIGH or both BLE and BHE are HIGH The input and output pins IOg through IO45 are placed in a high impedance state when m Deselected CE HIGH m Outputs are disabled OE HIGH
6. G HIGH IMPEDANCE 50 Page 6 of 13 Feedback CY62147EV30 MoBL EN a 76 CYPRESS gt 4 Switching Waveforms continued Figure 8 Write Cycle No 1 WE Controlled 16 20 21 twe ADDRESS CD 224 22 pataio XX NOTE OO lt 2 gt Figure 9 Write Cycle No 2 CE Controlled 16 20 21 gt YETI Document 38 05440 Rev G EN a yc CYPRESS PERFORM CY62147EV30 MoBL Switching Waveforms continued Figure 10 Write Cycle No 3 WE Controlled OE LOW 21 two OK c DW T 17222 tw lt gt twe lt lt lt lt lt m tsa RS NE JR gt Figure 11 Write Cycle No 4 BHE BLE Controlled OE LOW 21 twc ADDRESS TE lt MEE tup m tHzwe tsp DATAIO XX NOTE 22 OOD tL2We 20 Data I O is high impedance if OE _ 21 If CE goes HIGH simultaneously with WE the output remains in a high impedance state 22 During this period the IOs are in output state Do not apply input signals Document 38 05440 Rev G Page 8 of 13 Feedback gt 3 Truth Table T S 2 CYPRESS PERFORM CY62147EV30 MoBL
7. Added 45B2XI part Dual CE option Added CY62147EV30LL 45ZSXA in the ordering information table See ECN C 925501 VKN 10 03 08 D 04 01 09 VKN PYRS 1045701 VKN PYRS Page 12 of 13 Feedback 2577505 2681901 G Document 38 05440 Rev G ES CYPRESS CY62147EV30 MoBL PERFORM Sales Solutions and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices solution centers manufacturer s representatives and distributors To find the office closest to you visit us at cypress com sales Products PSoC Solutions PSoC psoc cypress com General psoc cypress com solutions Clocks amp Buffers clocks cypress com Low Power Low Voltage psoc cypress com low power Wireless wireless cypress com Precision Analog psoc cypress com precision analog Memories memory cypress com LCD Drive psoc cypress com Icd drive Image Sensors image cypress com CAN 2 0b psoc cypress com can USB psoc cypress com usb Cypress Semiconductor Corporation 2007 2009 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving crit
8. 262 0 404 gt 10 058 0 3965 BASE PLANE 40060 0 800 F 0 300 COTES 0 0315 Q 5 0210 00085 0 10 004 18 517 0 7295 0 597 0 02355 18313 0725 0406 0 01605 ATI ANE 51 85087 A 0 150 0 0059 1194 0 0475 Document 38 05440 Rev G Page 11 of 13 Feedback CY62147EV30 MoBL 45 ns Speed Bin lt a FP W CYPRESS PERFORM Document History Page Document Title CY62147EV30 MoBL 4 Mbit 256K x 16 Static RAM Document Number 38 05440 Rev ECN No Cena Description of Change di 201861 AJU 01 13 04 New Data Sheet A 247009 SYT See ECN Changed from Advanced Information to Preliminary Moved Product Portfolio to Page 2 Changed Vcc stabilization time in footnote 8 from 100 us to 200 us Removed Footnote 15 t from Previous Revision Changed lccpn from 2 0 uA to 2 5 uA Changed typo in Data Retention Characteristics ta from 100 us to tac ns Changed topa from 6 ns to 10 ns for both 35 ns and 45 ns Speed Bin Changed tyzoe tyzwe from 12 to 15 ns for 35 ns Speed Bin and 15 to 18 ns for 45 ns Speed Bin Changed and tgw from 25 to 30 ns for 35 ns Speed Bin and 40 to 35 ns for 45 ns Speed Bin Changed tpzce from 12 to 18 ns for 35 ns Speed Bin and 15 to 22 ns for 45 ns Speed Bin Changed tsp from 15 to 18 ns for 35 ns Speed Bin and 20 to 22 ns for Changed from 15 to 18 ns for 35 ns Speed Bin Changed Ordering Info
9. ES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Cypress reserves the right to make changes without further notice to the materials described herein Cypress does not assume any liability arising out of the application or use of any product or circuit described herein Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress product in a life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Use may be limited by and subject to the applicable Cypress software license agreement Document 38 05440 Rev G Revised March 31 2009 Page 13 of 13 MoBL is a registered trademark and More Battery Life is a trademark of Cypress Semiconductor All product and company names mentioned in this document are the trademarks of their respective holders Feedback
10. f these parts Notes 23 This BGA package is offered with single chip enable 24 This BGA package is offered with dual chip enable Document 38 05440 Rev G Page 9 of 13 Feedback Cypress PERFORM Package Diagrams TOP VIEW CY62147EV30 MoBL Figure 12 48 Ball VFBGA 6 x 8 x 1 mm 51 85150 A1 CORNER 12 3 4 5 6 gt gt 8 00 0 10 B m 6 00 0 10 0 55 MAX 0 25 M iu 2 gt 2 p 2005MC EW Al V go25 MCA 0 30 0 05 48X N CORNER ES 075 y A 525 2 625 OOOOCOOOO OOOOJOOOO OOOOIOOOO gt lt 8 00 0 10 m4 0 10 SEATING PLANE 0 26 MAX Document 38 05440 Rev G 0 21 0 05 gt 1 00 MAX 1 875 0 75 3 75 B m 6 00 0 10 0 15 4 lt gt 51 85150 D Page 10 of 13 Feedback SZ Cypress CY62147EV30 MoBL Package Diagrams continued Figure 13 44 Pin TSOP II 51 85087 DIMENSION IN CINCH MAX MIN 10 262 0 404 EJECTDR PIN BOTTOM VIEW TOP VIEW 10
11. ical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Any Source Code software and or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign United States copyright laws and international treaty provisions Cypress hereby grants to licensee a personal non exclusive non transferable license to copy use modify create derivative works of and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement Any reproduction modification translation compilation or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTI
12. ls BHE or BLE not switching when chip is disabled See application note AN13842 for further clarification 14 At any temperature and voltage condition tuzcg is less than tj tyzpe is less than tj tuzog is less than tj zog and tyzwe is less than t zwg for any device 15 tuzog tuzce and tyzwe transitions are measured when the outputs enter a high impedance state 16 The internal write time of the memory is defined by the overlap of WE Vi BLE or both All signals must be active to initiate a write and any of these signals can terminate a write by going inactive The data input setup and hold timing must be referenced to the edge of the signal that terminates the write Document 38 05440 Rev G Page 5 of 13 Feedback CY62147EV30 MoBL 17 18 CYPRESS Switching Waveforms Figure 6 Read Cycle No 1 Address Transition Controlled DATA VALID thc Figure 7 Read Cycle No 2 OE Controlled 18 19 ADDRESS PREVIOUS DATA VALID gt DATA OUT ADDRESS CE tace lt 7 gt seme x CC DATA VALID HIGHMPEDANCE lizcE tpu 5096 DATA OUT Voc SUPPLY CURRENT Notes 17 The device is continuously selected OE CE Vi BLE or both Vi 18 WE is HIGH for read cycle me 19 Address valid before or similar to CE and BHE BLE transition LOW Document 38 05440 Rev
13. ngle CE and dual_CE options In this data sheet for a dual CE device CE refers to the internal logical combination of CE and such that when CE is LOW and is HIGH CE is LOW For all other cases CE is HIGH Cypress Semiconductor Corporation Document 38 05440 Rev G 198 Champion Court San Jose CA 95134 1709 408 943 2600 Revised March 31 2009 Feedback Product Portfolio CY62147EV30 MoBL Power Dissipation Speed Product Range Vcc Range V n Operating Icc mA 9 Standby I A fz1MHz yep HA Typ Max Typ Max Typ Max Typ CY62147EV30LL Ind l Auto A 2 2 3 0 3 6 45 ns 2 2 5 15 20 1 7 Auto E 2 2 3 0 3 6 55 ns 2 3 15 25 1 20 Pin Configuration Figure 1 48 Ball VFBGA Single Chip Enable 3 4 Figure 2 48 Ball VFBGA Dual Chip Enable lt 1 2 3 4 5 6 iS S 8 86 DOMOS te FE C io CAGE e 592 455 o9 8 C ce n Css On Qe o
14. nto Outputs LOW 20 mA Static Discharge Voltage gt 2001V MIL STD 883 Method 3015 Latch Up Currents iiie enc eere gt 200 mA Operating Range Ambient Potential 0 3V to 3 9V 0 3 Range Temperature Vcc u fice CY62147EV30LL Ind VAuto A 40 C to 85 2 2V to debes max 0 Auto E 40 Cto 125 0 36V Electrical Characteristics Over the Operating Range ae 45 ns Ind l Auto A 55 ns Auto E Parameter Description Test Conditions 2 2 Unit Min Typ Max Min Typl Max Vou Output HIGH lou 0 1 mA 2 0 2 0 V Voltage lou 1 0 mA Voc gt 2 70V 24 24 V VoL Output LOW 0 1 mA 0 4 0 4 V Voltage loL 2 1 mA 2 70V 0 4 0 4 V Vin Input HIGH Voc 2 2V to 2 7V 1 8 03 1 8 03 V Vcc 2 7V to 3 6V 2 2 0 3 22 03 V Vit Input LOW Voc 2 2V to 2 7V 0 3 0 6 0 3 0 6 V Voltage Vcc 2 7V to 3 6V 503 08 03 0 8 V lix Input Leakage GND x Vi x 1 1 4 4 Current loz Output Leakage GND lt Vo lt Output Disabled 1 1 4 4 Current lec Voc Operating f fmax 1 Voc Voc max 15 20 15 25 mA Supply Current our mA f 1 MHz GMOS le
15. rmation to include Pb Free Packages 414807 Changed from Preliminary information to Final Changed the address of Cypress Semiconductor Corporation on Page 1 from 8901 North First Street to 198 Champion Court See ECN Removed 35ns Speed Bin Changed ball E3 from DNU to NC Removed L version of CY62147EV30 Removed redundant foot note on DNU Changed Max value from 2 mA to 2 5 mA and Typ value from ZSD 1 5 mA to 2 mA at f 1 MHz Changed Typ value from 12 mA to 15 mA at f fmax B 2 5 uAt Chang Adde Ch C 464503 NXR See E VKN Se 7 pA Changed Isp and lago Typ values from 0 7 uA to 1 uA and Max values from d lccpg typical value A ed lccpn from 2 5 uA to 7 pA Changed AC test load capacitance from 50 pF to 30 pF on Page 4 anged tj zoe from 3 ns to 5 ns hanged t tj 7 and tj zug from 6 ns to 10 ns Changed tpwe_ from 30 ns to 35 ns Changed tyzce from 22 ns to 18 ns Changed tap from 22 ns to 25 ns Updated the package diagram 48 pin VFBGA from B to D Updated the ordering information table and replaced the Package Name column with Package Diagram CN Included Automotive Range in product offering Updated the Ordering Information Added Preliminary Automotive A information Added footnote 9 related to lago and Added footnote 14 related AC timing parameters Converted Automotive A and Automotive E specs from preliminary to final e ECN
16. tion to Case Figure 4 AC Test Load and Waveforms ALL INPUT PULSES R1 Voc V OUTPUT 90 GND 1096 30 q Rise Time 1 V ns Fall Time 1 V ns INCLUDING JIG AND E SCOPE Equivalent to THEVENIN EQUIVALENT RTH OUTPUT oc wo V Parameters 2 50V 3 0V Unit R1 16667 1103 Q R2 15385 1554 Q 8000 645 Q 1 20 1 75 V Data Retention Characteristics Over the Operating Range Parameter Description Conditions Min Typ Max Unit VDR Vcc for Data Retention 1 5 V 8 Data Retention Current 1 5V gt Vec 02V Ind l Auto A 0 8 7 uA Vin gt Voc 0 2 or Vin lt 0 2V Auto E 12 9 Chip Deselect to Data Retention Time 0 ns ig Operation Recovery Time tac ns Figure 5 Data Retention Waveform 11 DATA RETENTION MODE VGC min gt 1 5V uM lt tg CE or BHE BLE Notes 10 Full device operation requires linear ramp from Vpg to VCC min gt 100 us or stable at Vcc min gt 100 us 11 BHE BLE is the AND of both BHE and BLE Deselect the chip by either disabling the chip enable signals or by disabling both BHE and BLE Page 4 of 13 Document 38 05440 Rev G Feedback CYPRESS PERFORM CY62147EV30 MoBL Switching Characteristics Over the Operating Range 12 13
17. vels 2 2 5 2 3 581 Automatic CE gt Vec 0 2V 1 7 1 20 Power Down Vin gt Voc 0 2V Vin lt 0 2V Current f fmax Address and Data Only CMOS Inputs f 2 0 OE BHE BLE and WE Voc 3 60V 582 Automatic CE gt Voc 0 2V 1 7 1 20 uA Power Down Vin gt Voc 0 2V or Vin lt 0 2V Current f 0 3 60V CMOS Inputs Capacitance For all packages Parameter Description Test Conditions Max Unit CN Input Capacitance 25 f 1 MHz 10 pF Cour Output Capacitance Voc 10 pF Notes 5 Vir min 2 0V for pulse durations less than 20 ns ViH max 0 75V for pulse durations less than 20 ns 7 Full device AC operation assumes a minimum of 100 us ramp time from 0 to Vcc min and 200 us wait time after Voc stabilization 8 Only chip enable CE and byte enables and BLE need to be tied to CMOS levels to meet the lag lccpg spec Other inputs can be left floating 9 Tested initially and after any design or process changes that may affect these parameters Document 38 05440 Rev G Page 3 of 13 C E SSS CYPRESS CY62147EV30 MoBL PERFORM Thermal Resistance Parameter Description Test Conditions RE Unit OJA Thermal Resistance Still Air soldered on a 3 x 4 5 inch two layer 75 77 C W Junction to Ambient printed circuit board Thermal Resistance 10 13 C W Junc
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