Cypress NoBL CY7C1470BV25 User's Manual
Contents
1. F CYPRESS PERFORM Boundary Scan Exit Order 4M x 18 Bit 165 Ball ID Bit 165 Ball ID Bit 165 Ball ID Bit 165 Ball ID D2 14 R4 27 L10 40 B10 E2 15 P6 28 K10 41 A8 3 F2 16 R6 29 J10 42 B8 4 G2 17 R8 30 H11 43 A7 5 J1 18 P3 31 G11 44 B7 6 K1 19 P4 32 F11 45 B6 7 L1 20 P8 33 E11 46 A6 8 M1 21 P9 34 D11 47 B5 N1 22 P10 35 C11 48 A4 10 R1 23 R9 36 A11 49 B3 11 R2 24 R10 37 A9 50 A3 12 R3 25 R11 38 B9 51 A2 13 P2 26 M10 39 A10 52 B2 Boundary Scan Exit Order 1M x 72 Bit 209 Ball ID Bit 209 Ball ID Bit 209 Ball ID Bit 209 Ball ID 1 Al 29 T1 57 U10 85 B1 2 A2 30 T2 58 T11 86 B10 3 B1 31 U1 59 T10 87 A11 4 B2 32 U2 60 R11 88 A10 5 C1 33 V1 61 R10 89 A7 6 C2 34 v2 62 P11 90 A5 7 D1 35 W1 63 P10 91 A9 8 D2 36 w2 64 N11 92 U8 E1 37 T6 65 N10 93 A6 10 E2 38 V3 66 M11 94 D6 11 F1 39 V4 67 M10 95 K6 12 F2 40 U4 68 L11 96 B6 13 G1 41 W5 69 L10 97 K3 14 G2 42 V6 70 P6 98 A8 15 H1 43 W6 71 J11 99 B4 16 H2 44 V5 72 J10 100 B3 17 J1 45 U5 73 H11 101 C3 18 J2 46 U6 74 H10 102 C4 19 L1 47 W7 75 G11 103 C8 20 L2 48 V7 76 G10 104 c9 21 M1 49 U7 77 F11 105 B9 22 M2 50 V8 78 F10 106 B8 23 N1 51 V9 79 E10 107 A4 24 N2 52 W11 80 E11 108 C6 25 P1 53 w10 81 D11 109 B7 26 P2 54 vii 82 D10 110 A3 27 R2 55 V10 83 en 28 R1 56 U11 84 C10 Page 18 of 29 Document 001 15032 Rev D Feedback CY7C142. wass R SP CYPRESS PERFORM 2 5V TAP AC Test Conditions CY7C1470BV25 CY7C1472BV25 CY7C1474BV25 Figure 5 2 5V TAP AC Output Load Equivalent Input pulse levelS ooooooooooooooo Vss to 2 5V 1 25V Input rise and fall time oooooWoooomoo 1ns Input timing reference levelS oooo oo 1 25V 500 Output reference levels 1 25V TDO Test load termination supply voltage 1 25V Zo 500 20pF TAP DC Electrical Characteristics And Operating Conditions 0 C lt TA lt 470 C Vpp 2 5V 0 125V unless otherwise noted Parameter Description Test Conditions Min Max Unit VoH1 Output HIGH Voltage lop 1 0 mA Vppa 2 5V 1 7 V VoH2 Output HIGH Voltage loy 100 uA Vppa 2 5V 2 1 V Vout Output LOW Voltage lor 1 0 MA Vppo 2 5V 0 4 V VoL2 Output LOW Voltage lor 100 HA Vppa 2 5V 0 2 V ViH Input HIGH Voltage Vppo 2 5V 1 7 Vpp 0 3 V Vi Input LOW Voltage Vppo 2 5V 0 3 0 7 V lx Input Load Current GND lt V lt Vppo 5 5 HA Table 6 Identification Register Definitions Instruction Field OOM 20 us 48 SM 72 25 Description Revision Number 31 29 000 000 000 Describes the version number Device Depth 28 24 01011 01011 01011 Reserved for internal use Architecture Memory Type 23 18 00100
3. 0 3V or Current CMOS Inputs Vin gt Vppo 0 3V 0 s cycle 200 Mhz 209 mA fmax 1 tcyc 6 0 ns cycle 167 MHz 200 mA Ispa Automatic CE Max Vpp Device Deselected All speed grades 135 mA Power Down Vin 2 Vin or Vin lt Vi f 0 Current TTL Inputs Capacitance Tested initially and after any design or process changes that may affect these parameters Parr YA 100 TQFP 165 FBGA 209 FBGA Parameter Description Test Conditions Max Max Max Unit CADDRESS Address Input Capacitance Ta 25 C f 1 MHz 6 6 6 pF CDATA Data Input Capacitance t DD 5 5 5 pF CcTRL Control Input Capacitance iS 8 8 8 pF Cerk Clock Input Capacitance 6 6 6 pF Cio Input Output Capacitance 5 5 5 pF Thermal Resistance Tested initially and after any design or process changes that may affect these parameters P Ag 100 TQFP 165 FBGA 209 FBGA Parameter Description Test Conditions Package Package Package Unit O JA Thermal Resistance Test conditions follow standard test 24 63 16 3 15 2 C W Junction to Ambient methods and procedures for ing thermal impedance per Ojo Thermal Resistance Measuring 2 28 21 1 7 C W Junction to Case EIA JESD51 AC Test Loads and Waveforms 2 5V IO Test Load R 16670 OUTPUT 2 5V u ALL INPUT PULSES OUTPUT ang RL 500 5pF L R 15380 V 1 25V INCLUDING a JIG AND c score b Document 001 15032 Rev D Page 20 of 29 Feedback YPRESS PERFORM Switching Characteristics Over
4. 0 5 ns taLH ADV LD Hold after CLK Rise 0 4 0 4 0 5 ns tcEH Chip Select Hold After CLK Rise 0 4 0 4 0 5 ns Notes 15 This part has a voltage regulator internally tpower is the time power is supplied above Vpp minimum initially before a read or write operation can be initiated 16 tonz tctz teoLz and teguz are specified with AC test conditions shown in b of AC Test Loads and Waveforms on page 20 Transition is measured 200 mV from steady state voltage 17 At any supplied voltage and temperature t orz is less than teg z and tc bus These specifications do not imply a bus contention condition but re High Z before Low Z under the same system conditions 18 This parameter is sampled and not 100 tested Document 001 15032 Rev D fe is less than tc z to eliminate bus contention between SRAMs when sharing the same data ct parameters guaranteed over worst case user conditions Device is designed to achieve Page 21 of 29 Feedback PERFORM Switching Waveforms Figure 6 shows read write timing waveform 1 20 21 Figure 6 Read Write Timing CY7C1470BV25 f Z CYPRESS CY7C1472BV25 CY7C1474BV25 A 1 2 4a 3 4 5 6 7 8 9 10 a ae ee s NA ADA Mn X Mp LD DA LD Mm E x m ADV LD LLL Eh E w Kn MD mmm IZA ADA ADDRESS AAT MZA na as YAA Z77777 As Was TA ZL Z CD
5. 13 68 DQa 14 67 H Vss J 15 CY7C1472BV25 66 H NC 16 65 H Vpop 17 4M x 18 64 122 18 63 DQa D 19 62 DQa q 20 61 Al Vona 21 60 H Vss 22 59 H DQa 23 58 DQa 24 57 NC 25 56 H NC 26 55 H Vss eL 54 H Vppo 28 53 NC O 29 52 NC O 30 51 NC TN C F LO CO O O gt OO2 QN CO F LO ON OO O O CO C CO CO CO C C CO ANAT F lt Et SS lt F O See 0 Sas s S S gt gt gt zz Page 4 of 29 Feedback LA 05 va gt CYPRESS PERFORM Pin Configurations continued 165 Ball FBGA 15 x 17 x 1 4 mm Pinout CY7C1470BV25 CY7C1472BV25 CY7C1474BV25 CY7C1470BV25 2M x 36 1 2 3 4 5 6 7 8 9 10 11 A NC 576M A CE BW BW CE CEN ADV LD A A NC B NC 1G A CE2 BW BW CLK WE OE A A NC C DQPc NC Vppo Vss Vss Vss Vss Vss Vppo NC DQPb D DQ DOG Vppo Vpp Vss Vss Vss Vpp Vppo DO DQ E DQ DQ Vppa Vpp Vss Vss Vss Vpp Vppa DQ DO F DQ DO Vppa Vpp Vss Vss Vss Vpp Vppo PQ DO G DQ DQ VDDQ VDD Vss Vss Vss VDD VDDQ DQ DO H NC NC NC Vou Ves Ves Vss Von NC NC ZZ J DAg Dag VppQ Vpp Vss Vss Vss Vpp Vppo DQ DQ K DQy DQy Vppa Vpp Vss Vss Vss Vpp Vppo DQ DQ L Dag DGg VppQ Vpp Vss Vss Vss Vpp Vppa DQ DQ M Dag Dag Vppa Vpp Vss Vss Vss Vpp Vppa DQ DQ N DQPa NC VDDQ Vss NC NC
6. 51 85167 Page 28 of 29 Feedback Document 001 15032 Rev D E CY7C1470BV25 SP CYPRESS CY7C1472BV25 CY7C1474BV25 PERFORM Document History Page Document Title CY7C1470BV25 CY7C1472BV25 CY7C1474BV25 72 Mbit 2M x 36 4M x 18 1M x 72 Pipelined SRAM with NoBL Architecture Document Number 001 15032 REV ECN No Issue Date Orig of Change Description of Change 1032642 See ECN VKN KKVTMP New data sheet A 1562503 See ECN VKN AESA Removed 1 8V IO offering from the data sheet B 1897447 See ECN VKN AESA Added footnote 14 related to IDD C 2082487 See ECN VKN Converted from preliminary to final D 2159486 See ECN VKN PYRS Minor Change Moved to the external web O Cypress Semiconductor Corporation 2007 2008 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in
7. DQ and DQP Write All Bytes w Siri E l All B L Note 8 Table lists only a partial listing of the Byte Write combinations Any combination of BWia d is valid Appropriate write is based on which Byte Write is active Document 001 15032 Rev D Page 11 of 29 Feedback CYPRESS PERFORM IEEE 1149 1 Serial Boundary Scan JTAG The CY7C1470BV25 CY7C1472BV25 and CY7C1474BV25 incorporates a serial boundary scan test access port TAP This port operates in accordance with IEEE Standard 1149 1 1990 but does not have the set of functions required for full 1149 1 compliance These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM Note that the TAP controller functions in a manner that does not conflict with the operation of other devices using 1149 1 fully compliant TAPs The TAP operates using JEDEC standard 2 5V IO logic levels The CY7C1470BV25 CY7C1472BV25 and CY7C1474BV25 contains a TAP controller instruction register boundary scan register bypass register and ID register Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature To disable the TAP controller TCK must be tied LOW Vss to prevent clocking of the device TDI and TMS are inter nally pulled up and may be unconnected They may alternately be connected to Vpp through a pull u
8. MODE Input Vss 30 HA Input Vpp 5 uA Input Current of ZZ Input Vss _5 uA Input Vpp 30 uA loz Output Leakage Current GND lt Vj lt Vpno Output Disabled 5 5 pA lobo 14 Vop Operating Supply Vpp Max lour 0 mA 4 0 ns cycle 250 MHz 450 mA f fmax Vtoyc 5 0 ns cycle 200 MHz 450 mA 6 0 ns cycle 167 MHz 400 mA Ispi Automatic CE Max Vpp Device Deselected 4 0 ns cycle 250MHz 200 mA 6 0 ns cycle 167 MHz 200 mA lsgo Automatic CE Max Vpp Device Deselected All speed grades 120 mA Power Down Vin lt 0 3V or Current CMOS Inputs Vin gt Vppo 0 3V f 0 Notes 12 Overshoot V y AC lt Vpp 1 5V pulse width less than tcyc 2 Undershoot Vj AC gt 2V pulse width less than tcyc 2 13 Tpower up assumes a linear ramp from OV to Vpp min within 200 ms During this time Vi lt Vpp and Vppo lt Vpp 14 The operation current is calculated with 50 read cycle and 50 write cycle Document 001 15032 Rev D Page 19 of 29 Feedback C r 4 CYPRESS PERFORM eA Electrical Characteristics Over the Operating Rangel 2 13 continued CY7C1470BV25 CY7C1472BV25 CY7C1474BV25 Min Max Unit Parameter Description Test Conditions 1923 Automatic CE Max Vpn Device Deselected 4 0 ns cycle 250 MHz 200 mA Power Down Vin lt
9. NC Vss VDDQ NC DQP P NC 144M A A TDI Al TDO A A A NC 288M R MODE A A A TMS AO TCK A A A A CY7C1472BV25 4M x 18 1 2 3 4 5 6 7 8 9 10 11 A NC 576M A CE BW NC CE CEN ADViLD A A A B NC 1G A CE2 NC BWa CLK WE OE A A NC c NC NC Vooo Vss Vss Vss Vss Vss Vppo NC DQPa D NC DQ Vppo Voo Vss Vss Vss Vpp VDDQ NC DQa E NC DQ VppQ Vpp Vss Vss Vss Vpp Vppo NC DQ F NC DO VppQ Vpp Vss Vss Vss Vpp Vppo NC DQ G NC DO VppQ Vpp Vss Vss Vss Vpp Vppo NC DQ H NC NC NC Vou Ves Ves Vss Von NC NC ZZ J DQp NC Vopa Vop Vss Vss Vss VDD Vppa DQ NC K DQ NC Vppa Vo Vss Vss Vss Vpp Vppo DQ NC L DQ NC Vppa Vo Vss Vss Vss Vpp Vppo DQ NC M DQ NC Vppa Vpp Vss Vss Vss Vpp Vopa DQ NC N Dar NC Vba Vss NC NC NC Ves Vppa NC NC P NC 144M A A A TDI A1 TDO A A A NC 288M R MODE A A TMS A0 TCK A A A A Document 001 15032 Rev D Page 5 of 29 Feedback a CYPRESS PERFORM CY7C1470BV25 CY7C1472BV25 CY7C1474BV25 Pin Configurations continued 209 Ball FBGA 14 x 22 x 1 76 mm Pinout CY7C1474BV25 1M x 72 1 2 3 4 5 6 7 8 9 10 11 A DQg DQg A CE A ADV LD A CEs A DQb DQb B DQg Dag BWS BWS NC WE A BWS BWS Dab bab C DQg Dag BWS BWS NC 576M CE NC BWS BWS Dab DQb D Dag Dag Vss NC NC IG OE NC NC Vss DQb DQb E DQPg DQPc Vipo Vopa Vpp Vp
10. Z state RESERVED 011 Do Not Use This instruction is reserved for future use SAMPLE PRELOAD 100 Captures lO ring contents Places the boundary scan register between TDI and TDO Does not affect SRAM operation This instruction does not implement 1149 1 preload function and is therefore not 1149 1 compliant RESERVED 101 Do Not Use This instruction is reserved for future use RESERVED 110 Do Not Use This instruction is reserved for future use BYPASS 111 Places the bypass register between TDI and TDO This operation does not affect SRAM operations Table 9 Boundary Scan Exit Order 2M x 36 Bit 165 BalID Bit 165 Ball ID Bit 165 Ball ID Bit 165 Ball ID 1 C1 21 R3 41 J11 61 B7 2 D1 22 P2 42 K10 62 B6 3 E1 23 R4 43 J10 63 A6 4 D2 24 P6 44 H11 64 B5 5 E2 25 R6 45 G11 65 A5 6 F1 26 R8 46 F11 66 A4 7 G1 27 P3 47 E11 67 B4 8 F2 28 P4 48 D10 68 B3 9 G2 29 P8 49 D11 69 A3 10 J1 30 P9 50 C11 70 A2 11 K1 31 P10 51 G10 71 B2 12 L1 Po 32 Ro 5 Fl 13 J2 33 R10 53 E10 14 M1 34 R11 54 A9 15 N1 35 N11 55 B9 16 K2 36 M11 56 A10 17 L2 37 L11 57 B10 18 M2 38 M10 58 A8 19 R1 39 L10 59 B8 20 R2 40 K11 60 A7 Document 001 15032 Rev D Page 17 of 29 Feedback CY7C1472BV25 CY7C1474BV25 CY7C1470BV25 1
11. can be connected to the input of any of the registers The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register For information about loading the instruction register see the TAP Controller State Diagram TDI is internally pulled up and can be unconnected if the TAP is unused in an application TDI is connected to the most significant bit MSB of any register See TAP Controller Block Diagram Test Data Out TDO The TDO output ball is used to serially clock data out from the registers The output is active depending upon the current state ofthe TAP state machine The output changes on the falling edge of TCK TDO is connected to the least significant bit LSB of any register See TAP Controller State Diagram Figure 3 TAP Controller Block Diagram gt 0 gt Bypass Register 12 1 0 gt Selection Circuitry Selection Instruction Register Circuitry TDI gt gt TDO gt Bajo 1 T2 1 0 Identification Register x 1 1 1 1 1 121110 82 Boundary Scan Register ELIT MARA TAP CONTROLLER TCK TMS Performing a TAP Reset A RESET is performed by forcing TMS HIGH V pp for five rising edges of TCK This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating During power up the TAP is reset internally to
12. ensure that TDO comes up in a High Z state TAP Registers Registers are connected between the TDI and TDO balls to scan the data in and out of the SRAM test circuitry Only one register can be selected at a time through the instruction register Data is serially loaded into the TDI ball on the rising edge of TCK Data is output on the TDO ball on the falling edge of TCK Page 12 of 29 Feedback YPRESS PERFORM Instruction Register Three bit instructions can be serially loaded into the instruction register This register is loaded when it is placed between the TDI and TDO balls as shown in the TAP Controller Block Diagram on page 12 During power up the instruction register is loaded with the IDCODE instruction It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section When the TAP controller is in the Capture IR state the two least significant bits are loaded with a binary 01 pattern to enable fault isolation of the board level serial test data path Bypass Register To save time when serially shifting data through registers it is sometimes advantageous to skip certain chips The bypass register is a single bit register that can be placed between the TDI and TDO balls This shifts the data through the SRAM with minimal delay The bypass register is set LOW Vss when the BYPASS instruction is executed Boundary Scan Register Th
13. l VA W mt ZZ s ZA ZZ eza NONA mors ZAR XZ 772 s XZ x 7770 as Z TDT cz m A Jaa s QC s ona In Out DQ h h WRITE READ STALL READ WRITE STALL NOP READ DESELECT CONTINUE D A1 Q A2 Q A3 D A4 Q A5 DESELECT D DONT CARE TI UNDEFINED Figure 8 shows ZZ Mode timing waveform 28 24 Figure 8 ZZ Mode Timing ak PALAS J AJ A AA M tzzREC ZZ g zz p sUPPLY Y ppzz nz except ZZ DON T CARE IGNORE CLOCK EDGE or STALL cycle Clock 3 illustrated CEN being used to create a pause A write is not performed during this cycle 23 Device must be deselected when entering ZZ mode See Truth Table on page 10 for all possible signal conditions to deselect the device 24 lOs are in High Z when exiting ZZ sleep mode Document 001 15032 Rev D Page 23 of 29 Feedback Ordering Information Not all of the speed package and temperature ranges are available Please contact your local sales representative or visit www cypress com for actual products offered CY7C1470BV25 CY7C1472BV25 CY7C1474BV25 CY7C1472BV25 200AXI CY7C1470BV25 200BZI CY7C1472BV25 200BZI 51 85165 165 ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm CY7C1470BV25 200BZXI CY7C1472BV25 200BZXI 51 85165 165 ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Pb Free Tore Ord
14. significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Any Source Code software and or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign United States copyright laws and international treaty provisions Cypress hereby grants to licensee a personal non exclusive non transferable license to copy use modify create derivative works of and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement Any reproduction modification translation compilation or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Cypress reserves the right to make changes without further notice to the materials described herein Cypress does not assume any liability arising out of the application or use of any product or circuit described h
15. the Operating Range Timing reference is 1 25V when Vppa 2 5V Test conditions shown in a of AC Test Loads and Waveforms on page 20 unless otherwise noted CY7C1470BV25 CY7C1472BV25 CY7C1474BV25 Parameter Description Seow Unit Min Max Min Max Min Max Power O Vcc typical to the First Access Read or Write 1 1 1 ms Clock teyc Clock Cycle Time 4 0 5 0 6 0 ns FMAX Maximum Operating Frequency 250 200 167 MHz tcH Clock HIGH 2 0 2 0 2 2 ns teL Clock LOW 2 0 2 0 2 2 ns Output Times tco Data Output Valid After CLK Rise 3 0 3 0 3 4 ns toev OE LOW to Output Valid 3 0 3 0 3 4 ns tpoH Data Output Hold After CLK Rise 1 3 1 3 1 5 ns tcHz Clock to High Z 6 17 18 3 0 3 0 3 4 ns telz Clock to Low Z 16 17 18 1 3 1 3 1 5 ns teouz OE HIGH to Output High Z118 17 18 3 0 3 0 3 4 ns teoLz OE LOW to Output Low Z 5 17 18 0 0 0 ns Setup Times tas Address Setup Before CLK Rise 1 4 1 4 1 5 ns tos Data Input Setup Before CLK Rise 1 4 1 4 1 5 ns teens CEN Setup Before CLK Rise 1 4 1 4 1 5 ns twes WE BW Setup Before CLK Rise 1 4 1 4 1 5 ns tats ADV LD Setup Before CLK Rise 1 4 1 4 1 5 ns tces Chip Select Setup 1 4 1 4 1 5 ns Hold Times tan Address Hold After CLK Rise 0 4 0 4 0 5 ns toH Data Input Hold After CLK Rise 0 4 0 4 0 5 ns tcENH CEN Hold After CLK Rise 0 4 0 4 0 5 ns tweH WE BW Hold After CLK Rise 0 4 0 4
16. 0 B Page 26 of 29 Document 001 15032 Rev D Feedback CY7C1470BV25 CYPRESS CY7C1472BV25 CY7C1474BV25 PERFORM fa Package Diagrams continued Figure 10 165 Ball FBGA 15 x 17 x 1 4 mm 51 85165 BOTTOM VIEW PIN1CORNER TOP VIEW 1 2005MC PIN 1 CORNER P l o2sm B 0 45 0 05 165X 1 9 3 a 7 SS 9 f NP TV S 7 H H A A t 0000000000 A B TA 60000 00000 8 c z 00000b 000o0O c 8 p 00000 00000 B E Q OQ O O 0 S O O O Q E F QO O Q Q O 00000 F 6 60 O O 00000 G H 3 O C H J 8 00000000000 K 000006000090 K k 00000 00000 L 8 M 6 0 O BOSO M N OQ O O O 00 O O 0 0 0 N F JOGOD O 00000 P R 0000 000 i R A 5 00 10 00 3 M U ase q 2 T B T 15002010 Z s yA 2 N A 0 15 4x q SEATING PLANE k 2 51 85165 A Document 001 15032 Rev D Page 27 of 29 Feedback CY7C1470BV25 CY7C1472BV25 CY7C1474BV25 B cypress Figure 11 209 Ball FBGA 14 x 22 x 1 76 mm 51 85167 Package Diagrams continued TOP VIEW j RNE 5 TO YA R 2 4 am BH 14 002 ol o a 0 15 4x JT SEATING PL PA e 29 2
17. 0 001000 001000 Defines memory type and archi tecture Bus Width Density 17 12 100100 010100 110100 Defines width and density Cypress JEDEC ID Code 11 1 00000110100 00000110100 00000110100 Allows unique identification of SRAM vendor ID Register Presence Indicator 0 1 1 1 Indicates the presence of an ID register Table 7 Scan Register Sizes Register Name Bit Size x36 Bit Size x18 Bit Size x72 Instruction 3 3 3 Bypass 1 1 1 ID 32 32 32 Boundary Scan Order 165FBGA 71 52 Boundary Scan Order 209BGA 110 Note 11 All voltages refer to Vss GND Document 001 15032 Rev D Page 16 of 29 Feedback LA 05 va gt CYPRESS PERFORM Table 8 Identification Codes CY7C1470BV25 CY7C1472BV25 CY7C1474BV25 Instruction Code Description EXTEST 000 Captures IO ring contents Places the boundary scan register between TDI and TDO Forces all SRAM outputs to High Z state This instruction is not 1149 1 compliant IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO This operation does not affect SRAM operations SAMPLE Z 010 Captures IO ring contents Places the boundary scan register between TDI and TDO Forces all SRAM output drivers to a High
18. 65 ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm CY7C1472BV25 250BZC CY7C1470BV25 250BZXC 51 85165 165 ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Pb Free CY7C1472BV25 250BZXC CY7C1474BV25 250BGC 51 85167 209 ball Fine Pitch Ball Grid Array 14 x 22 x 1 76 mm CY7C1474BV25 250BGXC 209 ball Fine Pitch Ball Grid Array 14 x 22 x 1 76 mm Pb Free CY7C1470BV25 250AXI 51 85050 100 Pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Pb Free Industrial Document 001 15032 Rev D Page 25 of 29 Feedback CY7C1470BV25 CYPRESS CY7C1472BV25 CY7C1474BV25 PERFORM y Package Diagrams Figure 9 100 Pin Thin Plastic Quad Flatpack 14 x 20 x 1 4 mm 51 85050 16 00 0 20 14 00 0 10 1 400 05 100 81 1 O 80 F 0 30 0 08 0 65 TYP 22 00 0 20 20 00 0 10 SEE DETAIL A 50 0 20 MAX 31 1 60 MAX R0 08 MIN 0 MIN SEATING PLANE 0 20 MAX po N STAND OFF 0 05 MIN NOTE 0 10 023 A 0 15 MAX GAUGE PLANE 1 Y 1 JEDEC STD REF MS 026 2 BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION END FLASH 1 R 0 08 MIN l MOLD PROTRUSION END FLASH SHALL NOT EXCEED 0 0098 in 0 25 mm PER SIDE 0 7 0 20 MAX BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 3 DIMENSIONS IN MILLIMETERS 0 60 0 15 0 20 MIN 1 00 REF al DETAIL A 51 8505
19. 70BV25 a CYPRESS CY7C1472BV25 CY7C1474BV25 Maximum Ratings Current into Outputs LOW 20 mA I Static Discharge Voltage gt 2001V Exceeding maximum ratings may impair the useful life of the MIL STD 883 Method 3015 device These user guidelines are not tested A A 65 C to 150 Latch up Current Woo WWW gt 200 mA u z A with ia Operating Range ower CE to 125 9 Supply vn on Vpp Relative to GND 0 5V to 3 6V Range Fs Vpp Vppa Supply Voltage on Vppc Relative to GND 0 5V to Vpp Commercial 0 C to 70 C 2 5V 5 5 2 5V 5 to DC to Outputs in Tri State 0 5V to Vppa 0 5V Industrial 40 C to 85 C Vpp DC Input Voltage 0 5V to Vpp 0 5V Electrical Characteristics Over the Operating Rangel 2 13 Parameter Description Test Conditions Min Max Unit Vop Power Supply Voltage 2 375 2 625 V Vppo IO Supply Voltage For 2 5V IO 2 375 Vpp V Vou Output HIGH Voltage For 2 5V IO loH 1 0 mA 2 0 V VoL Output LOW Voltage For 2 5V IO ly 1 0 mA 0 4 V Vin Input HIGH Voltage 9 For 2 5V IO 1 7 Vpp 0 3V V Vi Input LOW Voltage For 2 5V IO 0 3 0 7 V lx Input Leakage Current GND lt Vj lt Vppo 5 5 uA except ZZ and MODE Input Current of
20. OGIC Do Qo MODE CLK ADV LD c CEN WRITE ADDRESS REGISTER 1 WRITE ADDRESS REGISTER 2 ADV LD BWa WRITE REGISTRY BWb AND DATA COHERENCY WRITE MEMORY DOs CONTROL LOGIC vamancw ACVACO UE muzmun BW DRIVERS DOP BWa DOPb BWe DQPe m vuwmin Oma A4CVA4CO OZ Wmmin gt PO BW DQPa BW DQPe BW E DOPr DQPs DOPh WE INPUT REGISTER 1 El READ LOGIC CE1 CE2 CE3 zz Sleep Control Document 001 15032 Rev D Page 3 of 29 Feedback Pin Configurations CY7C1470BV25 CY7C1472BV25 CY7C1474BV25 Figure 1 100 Pin TQFP Pinout je l 1D S SO S 00 wr wW W wW w Ju ju O lt lt 8 Elala aa S EBS lt lt lt 8 D CO CO uu uu ua aua uu ON O O5 O5 O5 O DJ O O DJ O OO OO O DDD O MM DQPco 1 80 DQcO 2 79 DQcq 3 78 Vppor 4 77 Vss D 5 76 DQc 6 75 DQc 7 74 DQcU 8 73 DQc 9 72 Vs
21. PERFORM CY7C1470BV25 CY7C1472BV25 CY7C1474BV25 72 Mbit 2M x 36 4M x 18 1M x 72 Pipelined SRAM with NoBL Architecture Features m Pin compatible and functionally equivalent to ZBT m Supports 250 MHz bus operations with zero wait states n Available speed grades are 250 200 and 167 MHz m Internally self timed output buffer control to eliminate the need to use asynchronous OE m Fully registered inputs and outputs for pipelined operation m Byte Write capability m Single 2 5V power supply m 2 5V IO supply Vppq m Fast clock to output times n 3 0 ns for 250 MHz device m Clock Enable CEN pin to suspend operation m Synchronous self timed writes m CY7C1470BV25 CY7C1472BV25 available in JEDEC standard Pb free 100 pin TQFP Pb free and non Pb free 165 ball FBGA package CY7C1474BV25 available in Pb free and non Pb free 209 ball FBGA package m IEEE 1149 1 JTAG Boundary Scan compatible m Burst capability linear or interleaved burst order m ZZ Sleep Mode option and Stop Clock option Selection Guide Functional Description The CY7C1470BV25 CY7C1472BV25 and CY7C1474BV25 are 2 5V 2M x 36 4M x 18 1M x 72 synchronous pipelined burst SRAMs with No Bus Latency NoBL logic respectively They are designed to support unlimited true back to back read or write operations with no wait states The CY7C1470BV25 CY7C1472BV25 and CY7C1474BV25 are equipped with the advanced NoBL logic required to en
22. PRESS PERFORM access read write or deselect is latched into the Address Register provided the appropriate control signals are asserted On the next clock rise the data presented to DQ and DQP DQ4 b c d DQP 4 b c d for CY7C1470BV25 DQ p DQPap for CY7C1472BV25 DQ4 b c de tg h POPabedetgh for CY7C1474BV25 or a subset for Byte Write operations see Partial Write Cycle Description on page 11 for details inputs is latched into the device and the Write is complete The data written during the Write operation is controlled by BW BW b ca for CY7C1470BV25 BW p for CY7C1472BV25 and abedefa h for CY7C1474BV25 signals The CY7C1470BV25 CY7C1472BV25 and CY7C1474BV25 provides Byte Write capability that is described in Partial Write Cycle Description on page 11 Asserting the WE input with the selected BW input selectively writes to only the desired bytes Bytes not selected during a Byte Write operation remain unaltered A synchronous self timed write mechanism has been provided to simplify the write operations Byte Write capability has been included to greatly simplify read modify or write CY7C1470BV25 CY7C1472BV25 CY7C1474BV25 on page 8 When ADV LD is driven HIGH on the subsequent clock rise the Chip Enables CE4 CEs and CE3 and WE inputs are ignored and the burst counter is incremented The correct BW BWa p cq for CY7C1470BV25 BW p for CY7C1472BV25 and BWa bedefah for CY7C1474BV25 inputs must be driv
23. able consecutive read or write operations with data being transferred on every clock cycle This feature dramatically improves the throughput of data in systems that require frequent read or write transitions The CY7C1470BV25 CY7C1472BV25 and CY7C1474BV25 are pin compatible and functionally equivalent to ZBT devices All synchronous inputs pass through input registers controlled by the rising edge of the clock All data outputs pass through output registers controlled by the rising edge_of the clock The clock input is qualified by the Clock Enable CEN signal which when deasserted suspends operation and extends the previous clock cycle Write operations are controlled by the Byte Write Selects BW BW g for CY7C1470BV25 BW BW for CY7C1472BV25 and BW BW for CY7C1474BV25 and a Write Enable WE input All writes are conducted with on chip synchronous self timed write circuitry Three synchronous Chip Enables CE CE gt CE3 and an asynchronous Output Enable OE provide for easy bank selection and output tri state control To avoid bus contention the output drivers are synchronously tri stated during the data portion of a write sequence Description 250 MHz 200 MHz 167 MHz Unit Maximum Access Time 3 0 3 0 3 4 ns Maximum Operating Current 450 450 400 mA Maximum CMOS Standby Current 120 120 120 mA Cypress Semiconductor Corporation Document 001 15032 Rev D 198 Champion Court San J
24. and conduct up to four reads without reasserting the address inputs ADV LD must be driven LOW to load a new address into the SRAM as described in the Single Read Accesses section The sequence of the burst counter is deter mined by the MODE input signal A LOW input on MODE selects a linear burst mode a HIGH selects an interleaved burst sequence Both burst counters use AO and A1 in the burst sequence and wraps around when incremented sufficiently A HIGH input on ADV LD increments the internal burst counter regardless of the state of chip enables inputs or WE WE is latched at the beginning of a burst cycle Therefore the type of access read or write is maintained throughout the burst sequence Single Write Accesses Write accesses are initiated when the following conditions are satisfied at clock rise 1 CEN is asserted LOW 2 CE4 CE9 and CE are ALL asserted active and 3 the signal WE is asserted LOW The address presented to the address inputs is loaded into the Address Register The write signals are latched into the Control Logic block On the subsequent clock rise the data lines are automatically tri stated regardless of the state of the OE input signal This allows the external logic to present the data on DQ and DQP DQ b c d DQP 4 b c a for CY7C1470BV25 DQ p DQPa p for CY7C1472BV25 and DQabcdergnHDOGPabcdefah for CY7C1474BV25 In addition the address for the subsequent Page 8 of 29 Feedback AI CY
25. ble 3 Interleaved Burst Address Table DQa b c d e 19 HDQPa b c de f g h for CY7C1474BV25 are MODE Floating or Vpp automatically tri stated during the data portion of a write cycle DD regardless of the state of OE First Second Third Fourth Address Address Address Address Burst Write Accesses ATAO ATAO ALAO ALAO The CY7C1470BV25 CY7C1472BV25 and CY7C1474BV25 00 01 10 11 has an on chip burst counter that enables the user to supply a 01 00 Ti To single address and conduct up to four write operations without reasserting the address inputs ADV LD must be driven LOW to 10 11 00 01 load the initial address as described in Single Write Accesses 11 10 01 00 ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min Max Unit Ippzz Sleep mode standby current ZZ gt Vpp 0 2V 120 mA tzzs Device operation to ZZ ZZ gt Vpp 0 2V 2tcyc ns tz7REC ZZ recovery time ZZ lt 0 2V 2tcyc ns tzz1 ZZ active to sleep current This parameter is sampled 2tcyc ns RZZI ZZ Inactive to exit sleep current This parameter is sampled 0 ns Document 001 15032 Rev D Page 9 of 29 Feedback 2P CYPRESS PERFORM Table 4 Truth Table The truth table for CY7C1470BV25 CY7C1472BV25 and CY7C1474BV25 follows l 2 3 4 5 6 7 CY7C1470BV25 CY7C1472BV25 CY7C1474BV25 Operation Address CE ZZ ADV LD WE BW OE CEN CLK DQ Deselect Cycle Non
26. bles CE CE CE3 active at the rising edge of the clock If CEN is active LOW and ADV LD is asserted LOW the address presented to the device is latched The access can either be a read or write operation depending on the status of the Write Enable WE BW y can be used to conduct Byte Write opera tions Write operations are qualified by the Write Enable WE All writes are simplified with on chip synchronous self timed write circuitry Three synchronous Chip Enables CE CE CE3 and an asynchronous Output Enable OE simplify depth expansion All operations reads writes and deselects are pipelined ADV LD must be driven LOW after the device is deselected to load a new address for the next operation Single Read Accesses A read access is initiated when the following conditions are satisfied at clock rise 1 CEN is asserted LOW 2 CE CE and CE3 are ALL asserted active 3 the input signal WE is deasserted HIGH and 4 ADV LD is asserted LOW The address presented to the address inputs is latched into the Address Register and presented to the memory core and control logic The control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register At the rising edge of the next clock the requested data is allowed to propagate through the output Document 001 15032 Rev D Pin Name IO Type Pin Description TMS Test Mode Select TMS Pin Controls th
27. controlled by BW MODE Input Strap Pin Mode Input Selects the burst order of the device Tied HIGH selects the interleaved burst order Pulled LOW selects the linear burst order MODE must not change states during operation When left floating MODE defaults HIGH to an interleaved burst order TDO JTAG Serial Serial Data Out to the JTAG Circuit Delivers data on the negative edge of TCK Output Synchronous JTAG Serial Input Serial Data In to the JTAG Circuit Sampled on the rising edge of TCK Synchronous Page 7 of 29 Feedback TDI Document 001 15032 Rev D 2P CYPRESS PERFORM Table 1 Pin Definitions continued CY7C1470BV25 CY7C1472BV25 CY7C1474BV25 Functional Overview The CY7C1470BV25 CY7C1472BV25 and CY7C1474BV25 are synchronous pipelined Burst NoBL SRAMs designed specif ically to eliminate wait states during read or write transitions All synchronous inputs pass through input registers controlled by the rising edge of the clock The clock signal is qualified with the Clock Enable input signal CEN If CEN is HIGH the clock signal is not recognized and all internal states are maintained All synchronous operations are qualified with CEN All data outputs pass through output registers controlled by the rising edge of the clock Maximum access delay from the clock rise tco is 3 0 ns 250 MHz device Accesses can be initiated by asserting all three Chip Ena
28. e 1149 1 convention because some of the mandatory 1149 1 instructions are not fully implemented The TAP controller cannot be used to load address data or control signals into the SRAM and cannot preload the IO buffers The SRAM does not implement the 1149 1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE PRELOAD rather it performs a capture of the IO ring when these instruc tions are executed Document 001 15032 Rev D CY7C1470BV25 CY7C1472BV25 CY7C1474BV25 Instructions are loaded into the TAP controller during the Shift IR state when the instruction register is placed between TDI and TDO During this state instructions are shifted through the instruction register through the TDI and TDO balls To execute the instruction after it is shifted in the TAP controller must be moved into the Update IR state EXTEST EXTEST is a mandatory 1149 1 instruction which is executed whenever the instruction register is loaded with all Os EXTEST is not implemented in this SRAM TAP controller and therefore this device is not compliant to 1149 1 The TAP controller does recognize an all 0 instruction When an EXTEST instruction is loaded into the instruction register the SRAM responds as if a SAMPLE PRELOAD instruction has been loaded There is one difference between the two instructions Unlike the SAMPLE PRELOAD instruction EXTEST places the SRAM outputs in a High Z state IDCODE The IDCODE instruction loads a vendor
29. e H L X X X L H Tri State Continue Deselect Cycle None X X X X L H Tri State Read Cycle External L L L H X L L H Data Out Q Begin Burst Read Cycle Next X L H X X L L L H Data Out Q Continue Burst NOP Dummy Read External L L L H X H L L H Tri State Begin Burst Dummy Read Next X L H X X H L L H Tri State Continue Burst Write Cycle External L L L L L X L L H Data In D Begin Burst Write Cycle Next X L H X L X L L H Data In D Continue Burst NOP Write Abort None L L L L H X L L H Tri State Begin Burst Write Abort Next X L H X H X L L H Tri State Continue Burst Ignore Clock Edge Stall Current X L X X X X H L H Sleep Mode None X X X X X X X Tri State Notes 1 X Don t Care H Logic HIGH L Logic LOW CE stands for ALL Chip Enables active BW L signifies at least one Byte Write Select is active BW Valid signifies that the desired Byte Write Selects are asserted see Partial Write Cycle Description on page 11 for details Write is defined by WE and BW ra q See Partial Write Cycle Description on page 11 for details When a write cycle is detected all IOs are tri stated even during Byte Writes The DQ and DQP pins are controlled by the current cycle and the OE signal CEN H inserts wait states NOORON Document 001 15032 Rev D Device powers up deselected with the IOs in a tri state condition regardless of OE OE is asynchronous and is not sampled with the clock rise It
30. e Test Access Port State Machine Sampled on the rising edge of TCK Synchronous TCK JTAG Clock Clock Input to the JTAG Circuitry Vop Power Supply Power Supply Inputs to the Core of the Device Vppo IO Power Supply Power Supply for the IO Circuitry Vss Ground Ground for the Device Must be connected to ground of the system NC _ No Connects This pin is not connected to the die NC 144M _ These Pins are Not Connected They are used for expansion to the 144M 288M 576M and 1G 288M densities 576M 1G ZZ Input ZZ Sleep Input This active HIGH input places the device in a non time critical sleep condition Asynchronous with data integrity preserved For normal operation this pin has must be LOW or left floating ZZ pin has an internal pull down register and onto the data bus within 2 6 ns 250 MHz device provided OE is active LOW After the first_clock of the read access the output buffers are controlled by OE and the internal control logic OE must be driven LOW to drive out the requested data During the second clock a subsequent operation read write or deselect can be initiated Deselecting the device is also pipelined Therefore when the SRAM is deselected at clock rise by one of the chip enable signals its output tri states following the next clock rise Burst Read Accesses The CY7C1470BV25 CY7C1472BV25 and CY7C1474BV25 have an on chip burst counter that enables the user to supply a single address
31. e boundary scan register is connected to all the input and bidirectional balls on the SRAM The boundary scan register is loaded with the contents of the RAM IO ring when the TAP controller is in the Capture DR state and is then placed between the TDI and TDO balls when the controller is moved to the Shift DR state The EXTEST SAMPLE PRELOAD and SAMPLE Z instructions can be used to capture the contents of the IO ring The Boundary Scan Order tables on page 17 show the order in which the bits are connected Each bit corresponds to one of the bumps on the SRAM package The MSB of the register is connected to TDI and the LSB is connected to TDO Identification ID Register The ID register is loaded with a vendor specific 32 bit code during the Capture DR state when the IDCODE command is loaded in the instruction register The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift DR state The ID register has a vendor code and other information described in Identification Register Definitions on page 16 TAP Instruction Set Overview Eight different instructions are possible with the three bit instruction register All combinations are listed in Identification Codes on page 17 Three of these instructions are listed as RESERVED and must not be used The other five instructions are described in this section in detail The TAP controller used in this SRAM is not fully compliant to th
32. en in each cycle of the burst write to write the correct bytes of data Sleep Mode The ZZ input pin is an asynchronous input Asserting ZZ places the SRAM in a power conservation sleep mode Two clock cycles are required to enter into or exit from this sleep mode While in this mode data integrity is guaranteed Accesses pending when entering the sleep mode are not considered valid nor is the completion of the operation guaranteed The device must be deselected before entering the sleep mode CE4 CE9 and CE3 must remain inactive for the duration of tzzrec after the ZZ input returns LOW Table 2 Linear Burst Address Table MODE GND sequences which can be reduced to simple Byte Write opera First Second Third Fourth tions Address Address Address Address Because the CY7C1470BV25 CY7C1472BV25 and A1 A0 A1 A0 A1 A0 A1 A0 CY7C1474BV25 are common IO devices data must not be 00 01 10 11 driven into the device while the outputs are active OE can be deasserted HIGH before presenting data to the DQ and DQP 01 10 11 00 DQ 4 b c d DQP 4 b c a for CY7C1470BV25 DQ p DQPap for 10 11 00 01 CY7C1472BV25 and DQabcdetanDQPapbcdetgn for u 50 1 i CY7C1474BV25 inputs Doing so tri states the output drivers As a safety precaution DQ and DQP DQ4 pc DQPAa b ca for CY7C1470BV25 DQ DQP for CY7C1472BV25 and Ta
33. erein Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress product in a life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Use may be limited by and subject to the applicable Cypress software license agreement Document 001 15032 Rev D Revised February 29 2008 Page 29 of 29 NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation ZBT is a trademark of Integrated Device Technology Inc All products and company names mentioned in this document may be the trademarks of their respective holders Feedback
34. ering Code Dean Part and Package Type ad 167 CY7C1470BV25 167AXC 51 85050 100 pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Pb Free Commercial CY7C1472BV25 167AXC CY7C1470BV25 167BZC 51 85165 165 ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm CY7C1472BV25 167BZC CY7C1470BV25 167BZXC 51 85165 165 ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Pb Free CY7C1472BV25 167BZXC CY7C1474BV25 167BGC 51 85167 209 ball Fine Pitch Ball Grid Array 14 x 22 x 1 76 mm CY7C1474BV25 167BGXC 209 ball Fine Pitch Ball Grid Array 14 x 22 x 1 76 mm Pb Free CY7C1470BV25 167AXI 51 85050 100 pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Pb Free Industrial CY7C1472BV25 167AXI CY7C1470BV25 167BZI 51 85165 165 ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm CY7C1472BV25 167BZI CY7C1470BV25 167BZXI 51 85165 165 ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Pb Free CY7C1472BV25 167BZXI CY7C1474BV25 167BGl 51 85167 209 ball Fine Pitch Ball Grid Array 14 x 22 x 1 76 mm CY7C1474BV25 167BGXI 209 ball Fine Pitch Ball Grid Array 14 x 22 x 1 76 mm Pb Free 200 CY7C1470BV25 200AXC 51 85050 100 pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Pb Free Commercial CY7C1472BV25 200AXC CY7C1470BV25 200BZC 51 85165 165 ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm CY7C1472BV25 200BZC CY7C1470BV25 200BZXC 51 85165 165 ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Pb Free CY7C1472BV25 200BZXC CY7C1474BV25 200BGC 51 85167 209 ball Fine Pitch Ball Grid Array 14
35. is masked internally during write cycles During a Read cycle DQ and DQPra d tri state when OE is inactive or when the device is deselected and DQ data when OE is active Page 10 of 29 Feedback L 3 CY7C1470BV25 F CYPRESS CY7C1472BV25 CY7C1474BV25 PERFORM i Table 5 Partial Write Cycle Description The partial write cycle description for CY7C1470BV25 CY7C1472BV25 and CY7C1474BV25 follows 2 3 8 o v BW BW X Function CY7C1470BV25 Read Write No bytes written Write Byte a DQ and DAOP Write Byte b DQ and DOP Write Bytes b a Write Byte c DQ and DQP Write Bytes c a Write Bytes c b FVF T F F Write Bytes c b a Write Byte d DA and DAP4 Write Bytes d a Write Bytes d b Write Bytes d b a Write Bytes d c Write Bytes d c a Write Bytes d c b Write All Bytes inn rr rr r r rr rr r r r_I I Ww CT aa ua Oe ir X T C I T C I I x Z Ww r r r III FIF an dl pl T lt FIFIFIFIFIFIFIFI TI TI IT T T III Pri Pi maq oy ZZ oy ri Function CY7C1472BV25 Read Write No Bytes Written Write Byte a DQ and DQP Write Byte b DA and DQP Write Both Bytes w rr IC IC IT R Siria El MI ir T gt Function CY7C1474BV25 Read Write No Bytes Written Write Byte X
36. ls DQ and BW DQP BW controls DA and DQP BW controls DQ and DQPh BW BW BW BW WE Input Write Enable Input Active LOW Sampled on the rising edge of CLK if CEN is active LOW This Synchronous signal must be asserted LOW to initiate a write sequence ADV LD Input Advance Load Input Used to Advance the On Chip Address Counter or Load a New Address Synchronous When HIGH and CEN is asserted LOW the internal burst counter is advanced When LOW a new address can be loaded into the device for an access After being deselected ADV LD must be driven LOW to load a new address CLK Input Clock Input Used to capture all synchronous inputs to the device CLK is qualified with CEN CLK Clock is only recognized if CEN is active LOW CE Input Chip Enable 1 Input Active LOW Sampled on the rising edge of CLK Used in conjunction with Synchronous CE and CE to select deselect the device CE Input Chip Enable 2 Input Active HIGH Sampled on the rising edge of CLK Used in conjunction with Synchronous CE and CE to select deselect the device CE Input Chip Enable 3 Input Active LOW Sampled on the rising edge of CLK Used in conjunction with Synchronous CE and CE to select deselect the device OE Input Output Enable Active LOW Combined with the synchronous logic block inside the device to control Asynchronous the direction of the IO pins When LOW the IO pins can behave as outputs When deasserted HIGH IO pins are tri stated and ac
37. lt gt o i x x tas tau DS DH az DOH tOEV tcHz e Data DIA DIAZ Wo ham Q A3 Q A4 A441 D as HW ana In Out DQ tOEHZ tDOH pl OE OELZ WRITE WRITE BURST READ READ BURST WRITE READ WRITE DESELECT D A1 D A2 WRITE Q A3 Q A4 READ D A5 Q A6 D A7 D A2 1 Q A4 1 DON T CARE Rx UNDEFINED Notes 19 For this waveform ZZ is tied LOW 20 When CE is LOW CE is LOW CE is HIGH and CE is LOW When CE is HIGH CE is HIGH CE is LOW or CE is HIGH 21 Order of the Burst sequence is determined by the status of the MODE 0 Linear 1 Interleaved Burst operations are optional Document 001 15032 Rev D Page 22 of 29 Feedback Mo CY7C1470BV25 E CYPRESS CY7C1472BV25 CY7C1474BV25 PERFORM Switching Waveforms continued Figure 7 shows NOP STALL and DESELECT Cycles waveform Figure 7 NOP STALL and DESELECT Cycles 19 20 22 1 2 3 4 5 6 7 8 9 10 I I l I I I l I I I CLK N i N I I ab MM Vo Ho UO vi T En J IZDA NA m Z Z lt I L I mid A LA Z Z 2 MZA 7 I l l l l l l 2
38. ose CA 95134 1709 408 943 2600 Revised February 29 2008 Feedback CY7C1470BV25 CYPRESS CY7C1472BV25 CY7C1474BV25 PERFORM Logic Block Diagram CY7C1470BV25 2M x 36 ADDRESS A0 A1 A REGISTER 0 Al AO ait Do BURST 00 A0 LOGIC MODE CLK CEN ADV LD WRITE ADDRESS REGISTER 1 WRITE ADDRESS REGISTER 2 ADV LD WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC MEMORY ARRAY DQs DQPa DQPb DQPc DQPa BW BW BW BWa WE WRITE DRIVERS Toazmin Omw A4CVACO AMANTE ACSDACO m INPUT REGISTER 1 INPUT REGISTER 0 Ej E OE CET CE2 CEB READ LOGIC zz CONTROL Logic Block Diagram CY7C1472BV25 4M x 18 ADDRESS REGISTER 0 AO A1 A MODE CLK ADVAN CEN WRITE ADDRESS REGISTER 1 WRITE ADDRESS REGISTER 2 WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC DQs DQPa DQPb WRITE DRIVERS KOES muzmun vamnnce ACTVACO m onamin Oma Cu co OZ 23mmin PPU m OE CEI CE2 CE3 READ LOGIC Sleep Control zz Document 001 15032 Rev D Page 2 of 29 Feedback 2 CY7C1470BV25 CYPRESS CY7C1472BV25 CY7C1474BV25 PERFORM Logic Block Diagram CY7C1474BV25 1M x 72 ADDRESS AO Al A REGISTER 0 Al AO Al AO BURST L
39. p Von Vopa Vopa DQPf DQPb F Doc Dac Vss Vss Vss NC Vss Vss Vss DQf Daf G DQc DQc Vppa Vppa Voo NC Voo Vppa Vppa Dar Daf H Doc Dac Vss Vss Vss NC Vss Vss Vss DQf par J Dac DQc Vppa Vppa Voo NC Voo Vopo Vpba Daf Daf K NC NC CLK NC Vss CEN Vss NC NC NC NC L DQh Dah Vpba Vppa Vpp NC Vo Vppba Vppa DQa DQa M DQh pQh Vss Vss Vss NC Vss Vss Vss DQa DQa N DQh Dah Vppa Vppo Voo NC Von Vopa Voba Daa DQa P DQh DQh Vss Vss Vss ZZ Vss Vss Vss DQa DQa R DQPd DQPh Vppa Vppa Vpp Vpp Vpp Vppo Vppo DQPa DQPe T DQd DQd Vss NC NC MODE NC NC Vss DQe DQe U Dad DQd INcri4aM A A A A A NC 288M page DQe V DQd DQd A A Al A A DQe DQe W Dad DQd TMS TDI AO TDO TCK bae bae Document 001 15032 Rev D Page 6 of 29 Feedback CY7C1470BV25 CY7C1472BV25 CY7C1474BV25 gt Sn FF CYPRESS PERFORM Table 1 Pin Definitions Pin Name IO Type Pin Description A0 Input Address Inputs Used to Select One of the Address Locations Sampled at the rising edge of the A1 Synchronous CLK A BW Input Byte Write Select Inputs Active LOW Qualified with WE to conduct writes to the SRAM Sampled BW Synchronous on the rising edge of CLK BW controls DQ and DQP BW controls DQ and DAP BW controls BW DQ and DQP BW controls DQ and DQPy BW controls DQ and DAP BW contro
40. p resistor TDO must be left unconnected During power up the device comes up in a reset state which does not interfere with the operation of the device Figure 2 TAP Controller State Diagram al TEST LOGIC RESET 0 Y G RUN TEST 1 SELECT 1 SELECT 1 IDLE n DR SCAN IR SCAN 4 0 0 Y 1 1 1 CAPTURE DR CAPTURE IR 0 0 Y Y SHIFTDR 0 SHIFTAR OD L AA 1 1 Y Y 1 1 Le EXITI DR Le EXITI IR 0 0 Y Y PAUSE DR O gt PAUSE IR O gt 1 1 Y E 0 0 EXIT2 DR EXIT2 1R 1 1 Y Y UPDATE DR 1 UPDATE IR lt 1 0 0 Y The 0 1 next to each state represents the value of TMS at the rising edge of TCK Test Access Port TAP Test Clock TCK The test clock is used only with the TAP controller All inputs are captured on the rising edge of TCK All outputs are driven from the falling edge of TCK Document 001 15032 Rev D CY7C1470BV25 CY7C1472BV25 CY7C1474BV25 Test MODE SELECT TMS The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK Itis allowable to leave this ball unconnected if the TAP is not used The ball is pulled up internally resulting in a logic HIGH level Test Data In TDI The TDI ball is used to serially input information into the registers and
41. s o 10 71 Vppor 44 70 DQc 12 69 DQc 13 68 NC O 14 67 V Aa E CY7C1470BV25 66 65 Vss r 17 2M x 36 64 DQdr 18 63 DQdq 19 62 Vppad 20 61 Vss 21 60 DQdq 22 59 DQd 23 58 DQdr 24 57 DQdq 25 56 Vss r 26 55 Vppor 27 54 DQd 28 53 DQdq 29 52 DQPdg 30 51 GN C r LO CO OO O5 O QN C r LO CO OO O O CO QC C C CO C CO NN AAA TT lt TL LLI lt lt lt lt Z G lt 9 S lt lt lt lt lt lt lt lt lt Tam oo z z Document 001 15032 Rev D DQPb NC DQb NC DQb NC Vppq Yopa Vss Vss DQb NC DQb NC DQb DQb Dab DQb Ves Vss Vppq ope DQb DQb DQb DQb Vss NC NC Vpp Vpp NC ZZ Vss DQa DQb DQa DQb Vppq VDDQ Vss Vss DQa DQb DQa DQb DQa DQPb DQa NC Vss Vss Vppa VDDQ DQa NC DQa NC DQPa NC je N 2S WA ne w W O O W w j ju O lt lt 8829 EB Soe Dex 8 D Or Om TOA O O F LO Q F 000000000000 OO CO OO OO CO OO WM 1 80 A 2 79 GNC gq 3 78 NC 4 77 Vona 5 76 H Vss go 6 75 NC 7 74 DQPa q 8 73 DQa 9 72 H DQa 10 71 H Vss 11 70 H Vppa 12 69 DQa
42. specific 32 bit code into the instruction register It also places the instruction register between the TDI and TDO balls and shifts the IDCODE out of the device when the TAP controller enters the Shift DR state The IDCODE instruction is loaded into the instruction register during power up or whenever the TAP controller is in a test logic reset state SAMPLE Z The SAMPLE Z instruction connects the boundary scan register between the TDI and TDO pins when the TAP controller is in a Shift DR state It also places all SRAM outputs into a High Z state SAMPLE PRELOAD SAMPLE PRELOAD is a 1149 1 mandatory instruction The PRELOAD portion of this instruction is not implemented so the device TAP controller is not fully 1149 1 compliant When the SAMPLE PRELOAD instruction is loaded into the instruction register and the TAP controller is in the Capture DR state a snapshot of data on the inputs and bidirectional balls is captured in the boundary scan register The user must be aware that the TAP controller clock can only operate at a freguency up to 20 MHz while the SRAM clock operates more than an order of magnitude faster Because there is a large difference in the clock frequencies it is possible that during the Capture DR state an input or output may undergo a transition The TAP may then try to capture a signal while in transition metastable state This does not harm the device but there is no guarantee as to the value that is capt
43. t as input data pins OE is masked during the data portion of a write sequence during the first clock when emerging from a deselected state and when the device has been deselected CEN Input Clock Enable Input Active LOW When asserted LOW the clock signal is recognized by the SRAM Synchronous When deasserted HIGH the clock signal is masked Since deasserting CEN does not deselect the device CEN can be used to extend the previous cycle when required DA IO Bidirectional Data IO Lines As inputs they feed into an on chip data register that is triggered by Synchronous the rising edge of CLK As outputs they deliver the data contained in the memory location specified by Aj18 0 during the previous clock rise of the read cycle The direction of the pins is controlled by OE and the internal control logic When OE is asserted LOW the pins can behave as outputs When HIGH DQ DQ are placed in a tri state condition The outputs are automatically tri stated during the data portion of a write sequence during the first clock when emerging from a deselected state and when the device is deselected regardless of the state of OE DQPx IO Bidirectional Data Parity IO Lines Functionally these signals are identical to DOj71 01 During write Synchronous sequences DAP is controlled by BW DAP is controlled by BWp DQP is controlled by BWe and DAPgis controlled by BW DQP is controlled by BW DAP is controlled by BW DQP is controlled by BWg DQP is
44. ured Repeatable results may not be possible To guarantee that the boundary scan register captures the correct value of a signal the SRAM signal must be stabilized long enough to meet the TAP controller s capture setup plus hold time tcs plus toy The SRAM clock input might not be captured correctly if there is no way in a design to stop or slow the clock during a SAMPLE PRELOAD instruction If this is an issue it is still Page 13 of 29 Feedback NV b x 4 CYPRESS j PERFORM possible to capture all other signals and simply ignore the value of the CLK captured in the boundary scan register After the data is captured it is possible to shift out the data by putting the TAP into the Shift DR state This places the boundary scan register between the TDI and TDO balls Note that since the PRELOAD part of the command is not imple mented putting the TAP to the Update DR state while performing a SAMPLE PRELOAD instruction has the same effect as the Pause DR command Figure 4 TAP Timing CY7C1470BV25 CY7C1472BV25 CY7C1474BV25 BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift DR state the bypass register is placed between the TDI and TDO balls The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board Reserved These instructions are not implemented but are reser
45. ved for future use Do not use these instructions KA WA 1 2 Test Clock F TCK tTH SL tere aa w tTmss TMSH Test Mode Select 1 4 TMS trois tTDIH SS Test Data In yak ly YA TDI trpov lt trpox Test Data Out Q OO 7 W TDO DON T CARE RY UNDEFINED Document 001 15032 Rev D Page 14 of 29 Feedback CYPRESS PERFORM TAP AC Switching Characteristics CY7C1470BV25 CY7C1472BV25 CY7C1474BV25 Over the Operating Range 10 Parameter Description Min Max Unit Clock trcvc TCK Clock Cycle Time 50 ns trF TCK Clock Frequency 20 MHz tty TCK Clock HIGH time 20 ns tre TCK Clock LOW time 20 ns Output Times trpov TCK Clock LOW to TDO Valid 10 ns trpox TCK Clock LOW to TDO Invalid 0 ns Setup Times trMss TMS Setup to TCK Clock Rise 5 ns trpis TDI Setup to TCK Clock Rise 5 ns tos Capture Setup to TCK Rise 5 ns Hold Times trMSH TMS Hold after TCK Clock Rise 5 ns trpiH TDI Hold after Clock Rise 5 ns tcH Capture Hold after Clock Rise 5 ns Notes 9 tcs and toy refer to the setup and hold time requirements of latching data from the boundary scan register 10 Test conditions are specified using the load in TAP AC Test Conditions tp tp 1 ns Document 001 15032 Rev D Page 15 of 29 Feedback
46. x 22 x 1 76 mm CY7C1474BV25 200BGXC 209 ball Fine Pitch Ball Grid Array 14 x 22 x 1 76 mm Pb Free CY7C1470BV25 200AXI 51 85050 100 pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Pb Free Industrial CY7C1474BV25 200BGI CY7C1474BV25 200BGXI 51 85167 209 ball Fine Pitch Ball Grid Array 14 x 22 x 1 76 mm 209 ball Fine Pitch Ball Grid Array 14 x 22 x 1 76 mm Pb Free Document 001 15032 Rev D Page 24 of 29 Feedback FZ CYPRESS PERFORM Ordering Information continued Not all of the speed package and temperature ranges are available Please contact your local sales representative or visit www cypress com for actual products offered CY7C1470BV25 CY7C1472BV25 CY7C1474BV25 CY7C1472BV25 250AXI CY7C1470BV25 250BZI CY7C1472BV25 250BZI 51 85165 165 ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm CY7C1470BV25 250BZXI CY7C1472BV25 250BZXI 51 85165 165 ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Pb Free CY7C1474BV25 250BGI CY7C1474BV25 250BGXI 51 85167 209 ball Fine Pitch Ball Grid Array 14 x 22 x 1 76 mm 209 ball Fine Pitch Ball Grid Array 14 x 22 x 1 76 mm Pb Free Tore Ordering Code Dean Part and Package Type ad 250 CY7C1470BV25 250AXC 51 85050 100 pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Pb Free Commercial CY7C1472BV25 250AXC CY7C1470BV25 250BZC 51 85165 1
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