Cypress NoBL CY7C1352G User's Manual
Contents
1. kk A 224362 288431 See ECN See ECN RKF VBL New data sheet Deleted 100 MHz and 225 MHz Changed TQFP package in Ordering Information section to lead free TQFP B C 332895 419256 See ECN See ECN SYT RXU Modified Address Expansion balls in the pinouts for 100 TQFP Package as per JEDEC standards and updated the Pin Definitions accordingly Modified VoL Von test conditions Replaced TBD s for O a and O q to their respective values on the Thermal Resis tance table Added lead free product information for 119 BGA Updated the Ordering Information by shading and unshading MPNs as per avail ability Converted from Preliminary to Final Changed address of Cypress Semiconductor Corporation on Page 1 from 3901 North First Street to 198 Champion Court Modified test condition from V y lt Vpp to Vin lt Vpp Modified test condition from VDDQ lt Vop to VDDQ lt Vop Modified Input Load to Input Leakage Current except ZZ and MODE in the Electrical Characteristics Table Replaced Package Name column with Package Diagram in the Ordering Information table Replaced Package Diagram of 51 85050 from A to B Updated the Ordering Information D 480124 See ECN VKN Added the Maximum Rating for Supply Voltage on Vppq Relative to GND Updated the Ordering Information table Document 38 05514 Rev D Page 12 of 12 Feedback2. 38 05514 Rev D 198 Champion Court San Jose CA 95134 1709 e 408 943 2600 Revised July 4 2006 Feedback Eae PERFORM Selection Guide 250 MHz 200 MHz 166 MHz 133 MHz Unit Maximum Access Time 2 6 2 8 3 5 4 0 ns Maximum Operating Current 325 265 240 225 mA Maximum CMOS Standby Current 40 40 40 40 mA Pin Configuration 100 Pin TQFP Pinout o 2 Es a o OQ wn lt M iw xc Wu wi J Wm jw lt lo 0o22 E E so lbl022S lt sc lt o 0O O O O a Na rT OO OR O LO tT YO NN e O O0 O0 DD DD DM O O O O 0 0 0 O O OHO NC E 1 80 A NG 2 79 NC NC E 3 78 NC Vooo EE 4 77 Vopa Vss 5 76 Vss NC 6 75 NC Me 7 74 DOPA gt DQs 8 73 DQ DQg 9 72 7 DQ Vss 10 710 Vss Vppa 11 70 Vppa DQ 12 a CY7C1352G 9 ee DQg 13 68 DQ NC 14 67 Vss BYTE A BYTE B VE 15 66 NC NC 16 65 Vpop Vss 17 64 ZZ DG E 18 63 DQA DOs 19 62 DQ VDDQ 20 6
3. A1 AO A1 AO A1 AO 00 01 10 11 00 01 10 11 01 10 11 00 01 00 11 10 10 11 00 01 10 11 00 01 11 00 01 10 11 10 01 00 ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min Max Unit Ippzz Snooze mode standby current ZZ gt Vpp 0 2V 40 mA tzzs Device operation to ZZ ZZ gt Vpp 0 2V 2icyc ns tz7REC ZZ recovery time ZZ lt 0 2V 2tcyc ns tzz1 ZZ active to snooze current This parameter is sampled 2tcyc ns trzzI ZZ inactive to exit snooze current This parameter is sampled 0 ns Truth Table 9 4 5 6 7 8l Address Operation Used CE ZZ ADV LD WE BW OE CEN CLK DQ Deselect Cycle None HIL L X X X L L H Tri State Continue Deselect Cycle None XIIL H X X X L L H Tri State Read Cycle Begin Burst External L L L H X L L L H Data Out Q Read Cycle Continue Burst Next XIL H X X L L L H Data Out Q NOP Dummy Read Begin Burst External L L L H X H L L H Tri State Dummy Read Continue Burst Next XIL H X X H L L H Tri State Write Cycle Begin Burst External L L L L L X L L H Data In D Write Cycle Continue Burst Next XIL H X L X L L H Data In D NOP WRITE ABORT Begin Burst None L L L L H X L L H Tri State WRITE ABORT Continue Burst Next XIIL H X H X L L H Tri State IGNORE CLOCK EDGE Stall Current X L X X X X H L H SNOOZE MODE None xX H X X X X X X Tri State Truth Table for Read Write 3l Function WE BWB BWa Read H X X Write No bytes written L H H Write Byte A DQ a
4. appropriate control signals are asserted On the next clock rise the data presented to DQs and DQPJ A B or a subset for byte write operations see Write Cycle Description table for details inputs is latched into the device and the write is complete The data written during the Write operation is controlled by BWia s Signals The CY7C1352G provides byte write capability that is described in the Write Cycle Description table Asserting the Write Enable input WE with the selected Byte Write Select BW a B input will selectively write to only the desired bytes Bytes not selected during a byte write operation will remain unaltered A synchronous self timed write mechanism has been provided to simplify the write operations Byte write capability has been included in order to greatly simplify Read Modify Write sequences which can be reduced to simple byte write operations Because the CY7C1352G is a common I O device data should not be driven into the_device while the outputs are active The Output Enable OE can be deasserted HIGH before presenting data to the DQs and DOP ag inputs Doing so will tri state the output drivers As a safety precaution DQs and DQPra p are automatically tri stated during the data portion of a write cycle regardless of the state of OE Burst Write Accesses The CY7C1352G has an on chip burst counter that allows the user the ability to supply a single address and conduct up to four Write operations with
5. left floating ZZ pin has an internal pull down DQs 1 O Bidirectional Data I O Lines As inputs they feed into an on chip data register that is triggered Synchronous by the rising edge of CLK As outputs they deliver the data contained in the memory location specified by the address during the clock rise of the read cycle The direction of the pins is controlled by OE and the internal control logic When OE is asserted LOW the pins can behave as outputs When HIGH DQ and DQP a y are placed in a tri state condition The outputs are automatically tri stated during the data portion of a write sequence during the first clock when emerging from a deselected state and when the device is deselected regardless of the state of OE DOPja B 1 O Bidirectional Data Parity I O Lines Functionally these signals are identical to DQ During Synchronous write sequences DQPrA g is controlled by BW g correspondingly MODE Input Strap Pin Mode Input Selects the burst order of the device When tied to Gnd selects linear burst sequence When tied to Vpp or left floating selects interleaved burst sequence Vop Power Supply Power supply inputs to the core of the device VDDQ 1 0 Power Supply Power supply for the I O circuitry Vss Ground Ground for the device NC No Connects Not internally connected to the die NC 36M No Connects Not internally connected to the die NC 36M NC 72M NC 144M NC 288M are NC 72M address expansion pins are not i
6. 1 1 Vppa Vss 21 60 Vss DQg 22 59 DQA DQ E 23 58 DQ DQPg 24 57 NC NC 25 56 NC Vss 26 55 Vss Vppa 27 54 Vppa NG 28 53 NC NC 29 52 NC NC 30 51 3 NC NO Y DD O 0 Dd O AN Y 0O O N O Q O op E r E 9 OE 9 E gt O OP E OP i SY LO U ae oa ae SS OBS Ss ee tet we Q af res z o 9 22 ZZ Document 38 05514 Rev D Page 2 of 12 Feedback e gt ae YPRESS E PERFORM Pin Definitions CY7C1352G Name I O Description AO A1 A Input Address Inputs used to select one of the 256K address locations Sampled at the rising Synchronous edge of the CLK Aro are fed to the two bit burst counter BWia B Input Byte Write Inputs active LOW Qualified with WE to conduct writes to the SRAM Sampled Synchronous on the rising edge of CLK WE Input Write Enable Input active LOW Sampled on the rising edge of CLK if CEN is active LOW Synchronous This signal must be asserted LOW to initiate a write sequence ADV LD Input Advance Load Input Used to advance the on chip address counter or load a new address Synchronous When HIGH and CEN is asserted LOW the internal burst counter is advanced When LOW a new address can be loaded into the device for an access After being deselected ADV LD should be driven LOW in order to load a new address CLK Input Clock Clock Input Used to capture all synchronous inputs to the device CLK is qualified with
7. 25 mA Current f fmax 1cyc 5 ns cycle 200 MHz 265 mA 6 ns cycle 166 MHz 240 mA 7 5 ns cycle 133 MHz 225 mA Isa Automatic CE Vpp Max Device Deselected 4 ns cycle 250 MHz 120 mA 6 ns cycle 166 MHz 100 mA 7 5 ns cycle 133 MHz 90 mA Ispo Automatic CE Vpp Max Device Deselected All speeds 40 mA Power down Vin lt 0 3V or Current CMOS Inputs Vin gt Vopa 0 3V f 0 Isp3 Automatic CE Vpp Max Device Deselected 4 ns cycle 250 MHz 105 mA nr EMOS Inputs Ma eed 0 3V SS ICE re One Ee ale f fmax 1 teyc 6 ns cycle 166 MHz 85 mA 7 5 ns cycle 133 MHz 75 mA Notes 9 Overshoot V y AC lt Vpp 1 5V Pulse width less than tcyc 2 undershoot Vi AC gt 2V Pulse width less than tcvc 2 10 Tpower up Assumes a linear ramp from OV to Vpp min within 200 ms During this time Vi lt Vpp and Vopa lt Vpp Document 38 05514 Rev D Page 6 of 12 Feedback CY7C1352G Electrical Characteristics Over the Operating Rangel 1 continued Parameter Description Test Conditions Min Max Unit Isa Automatic CE Vpp Max Device Deselected All speeds 45 mA Power down Vin gt VH Or Vin lt Vi f 0 Current TTL Inputs Capacitance 100 TQFP Parameter Description Test Conditions Max Unit Cin Input Capacitance Ta 25 f 1 MHz 5 pF Cerk Clock Input Capacitance K DD mee 5 pF Cio Input Output Capacitance
8. 85050 100 pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Commercial CY7C1352G 133AXI Industrial 166 CY7C1352G 166AXC 51 85050 100 pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Commercial CY7C1352G 166AXI Industrial 200 CY7C1352G 200AXC 51 85050 100 pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Commercial CY7C1352G 200AXI Industrial 250 CY7C1352G 250AXC 51 85050 100 pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Commercial CY7C1352G 250AXI Industrial Package Diagram 22 00 0 20 R 0 08 MIN 0 20 MAX 0 MIN 0 25 y E H NH GAUGE PLANE I VIN 100 Pin TQFP 14 x 20 x 1 4 mm 51 85050 16 00 0 20 EAS o S 2 o a Y 30 31 14 00 0 10 100 81 oo 0 30 0 08 A L 0 65 TYP 51 50 STAND OFF 0 05 MIN 0 15 MAX vo 02 7 0 60 0 15 R 0 08 MIN 0 20 MAX 0 20 MIN 1 00 REF Le DETAIL SEATING PLANE Pd 0 10 O NOTE 1 JEDEC STD REF MS 026 7 T 1 40 0 05 SEE DETAIL A m 0 20 MAX p 1 60 MAX 2 BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION END FLASH MOLD PROTRUSION END FLASH SHALL NOT EXCEED 0 0098 in 0 25 mm PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 3 DIMENSIONS IN MILLIMETERS 51 85050 B ZBT is a trademar
9. CEN CLK is only recognized if CEN is active LOW CE Input Chip Enable 1 Input active LOW Sampled on the rising edge of CLK Used in conjunction Synchronous with CE and CE to select deselect the device CE Input Chip Enable 2 Input active HIGH Sampled on the rising edge of CLK Used in conjunction Synchronous with CE and CE3 to select deselect the device CE Input Chip Enable 3 Input active LOW Sampled on the rising edge of CLK Used in conjunction Synchronous with CE and CE to select deselect the device OE Input Output Enable asynchronous input active LOW Combined with the synchronous logic Asynchronous block inside the device to control the direction of the I O pins When LOW the DQ pins are allowed to behave as outputs When deasserted HIGH DQ pins are tri stated and act as input data pins OE is masked during the data portion of a write sequence during the first clock when emerging from a deselected state when the device has been deselected CEN Input Clock Enable Input active LOW When asserted LOW the Clock signal is recognized by the Synchronous SRAM When deasserted HIGH the Clock signal is masked Since deasserting CEN does not deselect the device CEN can be used to extend the previous cycle when required ZZ Input ZZ sleep Input This active HIGH input places the device in a non time critical sleep Asynchronous condition with data integrity preserved During normal operation this pin has to be low or
10. CYPRESS CY7C1352G o PERFORA Switching Waveforms continued NOP STALL and DESELECT Cycles 8 19 21 aovin Wh WMD I VD ID ID i WED WT WT OTT EL Bwa A WL A Le ADDRESS 7 AZ WZ AZ ZO A O WLLL AS LLL tcHZ Data ESN OCC CE DAM CIE In Out DQ CONTINUE DESELECT READ DESELECT Q AS WRITE STALL NOP D A4 READ Q A3 DONT CARE BA UNDEFINED READ STALL Q A2 WRITE D A1 0 qa qa a ga LNA Ri E SUPPLY l t l DDZZ RZA pt except ZZ Notes 21 The IGNORE CLOCK EDGE or STALL cycle Clock 3 illustrated CEN being used to create a pause A write is not performed during this cycle 22 Device must be deselected when entering ZZ mode See cycle description table for all possible signal conditions to deselect the device 23 DQs are in high Z when exiting ZZ sleep mode Document 38 05514 Rev D Page 10 of 12 Feedback E gas TS J CYPRESS PERFORM Ordering Information CY7C1352G Not all of the speed package and temperature ranges are available Please contact your local sales representative or visit www cypress com for actual products offered Speed Package Operating MHz Ordering Code Diagram Package Type Range 133 CY7C1352G 133AXC 51
11. dade E S 5 pF Thermal Resistance 100 TQFP Parameter Description Test Conditions Package Unit OJA Thermal Resistance Test conditions follow standard test 30 32 C W Junction to Ambient methods and procedures for measuring 80 Thermal Resistance thermal impedance per EIA JESD51 6 85 CW Junction to Case AC Test Loads and Waveforms 3 3V I O Test Load R 3170 ins OUTPUT 3 3V ALL INPUT PULSES OUTPUT RL 500 5pF L R 3510 Vr 1 5V INCLUDING JIG AND scope 0 25V R 16670 OUTPUT Ri 509 5pF INCLUDING R 15380 Vra LN JIG AND a SCOPE b c Note 11 Tested initially and after any design or process changes that may affect these parameters Document 38 05514 Rev D Page 7 of 12 Feedback e E CYPRESS CY7C1352G PERFORM Switching Characteristics Over the Operating Range 17 250 200 166 133 Parameter Description Min Max Min Max Min Max Min Max Unit tPoWER Vpp typical to the first Access 1 1 1 1 ms Clock tovc Clock Cycle Time 4 0 5 0 6 0 7 5 ns tcH Clock HIGH 1 7 2 0 2 5 3 0 ns teL Clock LOW 1 7 2 0 2 5 3 0 ns Output Times tco Data Output Valid After CLK Rise 2 6 2 8 3 5 4 0 ns tboH Data Output Hold After CLK Rise 1 0 1 0 1 5 1 5 ns telz Clock to Low Z119 14 15 0 0 0 0 ns tcHz Clock to H
12. igh Z119 14 15 2 6 2 8 3 5 4 0 ns toev OE LOW to Output Valid 2 6 2 8 3 5 4 0 ns toELz OE LOW to Output Low z 3 14 15 0 0 0 0 ns toEHz OE HIGH to Output High z 3 14 15 2 6 2 8 3 5 4 0 ns Set up Times tas Address Set up Before CLK Rise 1 2 1 2 1 5 1 5 ns tals ADV LD Set up Before CLK Rise 1 2 1 2 1 5 1 5 ns twes GW BWja g Set Up Before CLK Rise 1 2 1 2 1 5 1 5 ns tcENS CEN Set up Before CLK Rise 1 2 1 2 1 5 1 5 ns tos Data Input Set up Before CLK Rise 1 2 1 2 15 15 ns tces Chip Enable Set up Before CLK Rise 1 2 1 2 1 5 1 5 ns Hold Times taH Address Hold After CLK Rise 0 3 0 5 0 5 0 5 ns tana ADV LD Hold after CLK Rise 0 3 0 5 0 5 0 5 ns tweH GW BWA 8 Hold After CLK Rise 0 3 0 5 0 5 0 5 ns tcENH CEN Hold After CLK Rise 0 3 0 5 0 5 0 5 ns toH Data Input Hold After CLK Rise 0 3 0 5 0 5 0 5 ns tceH Chip Enable Hold After CLK Rise 0 3 0 5 0 5 0 5 ns Notes 12 This part has a voltage regulator internally tpower is the time that the power needs to be supplied above Vpp minimum initially before a read or write operation can be initiated 13 toyz tcLz togLz and tognz are specified with AC test conditions shown in part b of AC Test Loads Transition is measured 200 mV from steady state voltage 14 At any given voltage and temperature togpz is less than togLz and toyz is less than tc z to eliminate bus contention between SRAMs when sharing the same data bus These specifications do not imply a bus contention condition but ref
13. isters controlled by the rising edge of the clock The clock input is qualified by the Clock Enable CEN signal which when deasserted suspends operation and extends the previous clock cycle Maximum access delay from the clock rise is 2 6 ns 250 MHz device Write operations are controlled by the two Byte Write Select BWa p and a Write Enable WE input All writes are conducted with on chip synchronous self timed write circuitry Three synchronous Chip Enables CE CE gt CE3 and an asynchronous Output Enable OE provide for easy bank selection and output tri state control In order to avoid bus contention the output drivers are synchronously tri stated during the data portion of a write sequence Logic Block Diagram ADDRESS REGISTER O AO A1 A Al MODE CLK ADV I D CEN WRITE ADDRESS REGISTER 1 WRITE ADDRESS REGISTER 2 ADV LD WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC BWa BWe WE OE CEL cE2 CE3 READ LOGIC Slee control AO D1 po BURST LOGIC Al qu AL Qo AO MEMORY ARRAY WRITE DRIVERS DQs DQPa DQPs NTE MmZzmn wamancw 4Cv4CO m naman a amx ACvjICO O02 2MmmN PAPO m INPUT REGISTER 1 Note 1 For best practices recommendations please refer to the Cypress application note System Design Guidelines on www cypress com Cypress Semiconductor Corporation Document
14. k of Integrated Device Technology Inc NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation All product and company names mentioned in this document are trademarks of their respective holders Document 38 05514 Rev D Cypress Semiconductor Corporation 2006 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Page 11 of 12 Feedback i e a CYPRESS PERFORM Document History Page CY7C1352G Document Title CY7C1352G 4 Mbit 256K x 18 Pipelined SRAM with NoBL Architecture Document Number 38 05514 REV ECN NO Issue Date Orig of Change Description of Change
15. lect parameters guaranteed over worst case user conditions Device is designed to achieve tri state prior to Low Z under the same system conditions 15 This parameter is sampled and not 100 tested 16 Timing reference level is 1 5V when Vppq 3 3V and is 1 25V when Vppq 2 5V 17 Test conditions shown in a of AC Test Loads unless otherwise noted Document 38 05514 Rev D Page 8 of 12 Feedback E zom ooo A CYPRESS CYPRESS CY7C1352G PERFORM Switching Waveforms 1 ss 4 5 6 7 8 9 10 an aca a ala wA D D h 0000000877 ek Uh M D MA alk TA Mi OA Bi BA Who Wh WEA UA YY Ws CD MA O BWas A WA MD eh AI TI ADDRESS A Al W X A2 ES BA NUI AS WIN A6 WIX AT XI t t tas taH DS DH telz DOH tor tCHZ Data In Out DQ OE l l l l l l l l l WRITE WRITE BURST READ READ BURST WRITE READ WRITE DESELECT D A1 D A2 WRITE Q A3 Q A4 READ D A5 Q A6 D A7 D A2 1 Q A4 1 VJ DON T CARE B UNDEFINED Notes 18 For this waveform ZZ is tied low 19 When CE is LOW CE is LOW CE is HIGH and CE is LOW When CE is HIGH CE is HIGH or CE is LOW or CEg is HIGH 20 Order of the Burst sequence is determined by the status of the MODE 0 Linear 1 Interleaved Burst operations are optional Document 38 05514 Rev D Page 9 of 12 Feedback y
16. ll operations Reads Writes and Deselects are pipelined ADV LD should be driven LOW once the device has been deselected in order to load a new address for the next operation Single Read Accesses A read access is initiated when the following conditions are satisfied at clock rise 1 CEN is asserted LOW 2 CE4 CE9 and CE are ALL asserted active 3 the Write Enable input signal WE is deasserted HIGH and 4 ADV LD is asserted LOW The address presented to the address inputs is latched into the Address Register and presented to the memory core and control logic The control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register At the rising edge of the next clock the requested data is allowed to propagate through the output register and onto the data bus provided OE is active LOW After the first clock of the read access the output buffers are controlled by OE and the internal control logic OE must be driven LOW in order for the device to drive out the requested data During the second clock a subsequent operation Read Write Deselect can be initiated Deselecting the device is also pipelined Therefore when the SRAM is deselected at clock rise by one of the chip enable signals its output will tri state following the next clock rise Burst Read Accesses The CY7C1352G has an on chip burst counter that allows the user the ability to supply a single add
17. nd DQPa L H L Write Byte B DQp and DQPp L L H Write All Bytes L L L Notes 2 X Don t Care H Logic HIGH L Logic LOW CE stands for ALL Chip Enables active BWy L signifies at least one Byte Write Select is active BWy Valid signifies that the desired byte write selects are asserted see Write Cycle Description table for details Write is defined by BW and WE See Write Cycle Descriptions table CEN H inserts wait states DADA When a write cycle is detected all I Os are tri stated even during byte writes __ The DQ and DQP pins are controlled by the current cycle and the OE signal OE is asynchronous and is not sampled with the clock Device will power up deselected and the I Os in a tri state condition regardless of OE OE is asynchronous and is not sampled with the clock rise It is masked internally during write cycles During a read cycle DQs and DQPy g tri state when OE is inactive or when the device is deselected and DQs and DQP A g data when OE is active Document 38 05514 Rev D Page 5 of 12 Feedback e 2 CYPRESS i P E RE ORM Maximum Ratings Above which the useful life may be impaired For user guide CY7C1352G DC Input Voltage 0 5V to Vpp 0 5V Current into Outputs LOW 20 mA lines not tested Sta
18. nternally connected to the die NC 144M NC 288M Document 38 05514 Rev D Page 3 of 12 Feedback 7 _ zom See e 389 SS CYPRESS j PERFORM Functional Overview The CY7C1352G is a synchronous pipelined Burst SRAM designed specifically to eliminate wait states during Write Read transitions All synchronous inputs pass through input registers controlled by the rising edge of the clock The clock signal is qualified with the Clock Enable input signal CEN If CEN is HIGH the clock signal is not recognized and all internal states are maintained All synchronous operations are qualified with CEN All data outputs pass through output registers controlled by the rising edge of the clock Maximum access delay from the clock rise tco is 2 6 ns 250 MHz device Accesses can be initiated by asserting all three Chip Enables CE CE2 CE3 active at the rising edge of the clock If Clock Enable CEN is active LOW and ADV LD is asserted LOW the address presented to the device will be latched The access can either be a read or write operation depending on the status of the Write Enable WE BW p can be used to conduct byte write operations Write operations are qualified by the Write Enable WE All writes are simplified with on chip synchronous self timed write circuitry Three synchronous Chip Enables CE CEs CE3 and an asynchronous Output Enable OE simplify depth expansion A
19. o o r E SSS Ra SM ET A A A PE ae T aa YPRESS CY7C1352G PERFORM Features Pin compatible and functionally equivalent to ZBT devices Internally self timed output buffer control to eliminate the need to use OE Byte Write capability 256K x 18 common I O architecture 3 3V core power supply Vpp 2 5V 3 3V I O power supply Vppq Fast clock to output times 2 6 ns for 250 MHz device Clock Enable CEN pin to suspend operation Synchronous self timed writes Asynchronous output enable OE Available in lead free 100 Pin TQFP package Burst Capability linear or interleaved burst order ZZ Sleep Mode Option and Stop Clock option 4 Mbit 256K x 18 Pipelined SRAM with NoBL Architecture Functional Description The CY7C1352G is a 3 3V 256K x 18 synchronous pipelined Burst SRAM designed specifically to support unlimited true back to back Read Write operations without the insertion of wait states The CY7C1352G is equipped with the advanced No Bus Latency NoBL logic required to enable consec utive Read Write operations with data being transferred on every clock cycle This feature dramatically improves the throughput of the SRAM especially in systems that require frequent Write Read transitions All synchronous inputs pass through input registers controlled by the rising edge of the clock All data outputs pass through output reg
20. out reasserting the address inputs ADV LD must be driven LOW in order to load the initial address as described in the Single Write Access section above When ADV LD is driven HIGH on the subsequent clock rise the chip enables CE4 CEs and CE3 and WE inputs are ignored and the burst counter is incremented The correct BWia 8 inputs must be driven in each cycle of the burst write in order to write the correct bytes of data Sleep Mode The ZZ input pin is an asynchronous input Asserting ZZ places the SRAM in a power conservation sleep mode Two clock cycles are required to enter into or exit from this sleep mode While in this mode data integrity is guaranteed Accesses pending when entering the sleep mode are not considered valid nor is the completion of the operation guaranteed The device must be deselected prior to entering the sleep mode CE1 CE2 and CE3 must remain inactive for the duration of tZzrEc after the ZZ input returns LOW Page 4 of 12 Feedback e ea 2 CYPRESS i PERFORM Interleaved Burst Address Table CY7C1352G Linear Burst Address Table MODE GND MODE Floating or Vpp E a FET ais Pete ae i ress ress ress ress Address Address address Address A1 AO ATAO ALAO At AO A1 AO
21. ress and conduct up to four Reads without reasserting the address inputs ADV LD must be driven LOW in order to load a new address into the SRAM as described in the Single Read Access section above The sequence of the burst counter is determined by the MODE input signal A LOW input on MODE selects a linear burst mode a HIGH selects an interleaved burst sequence Both burst counters use AO and A1 in the burst sequence and will wrap around when incremented sufficiently A HIGH input on ADV LD will increment the internal burst counter regardless of Document 38 05514 Rev D CY7C1352G the state of chip enables inputs or WE WE is latched at the beginning of a burst cycle Therefore the type of access Read or Write is maintained throughout the burst sequence Single Write Accesses Write accesses are initiated when the following conditions are satisfied at clock rise 1 CEN is asserted LOW 2 CE4 CE and CE3 are ALL asserted active and 3 the write signal WE is asserted LOW The address presented to the address inputs is loaded into the Address Register The write signals are latched into the Control Logic block On the subsequent clock rise the data lines are automatically tri stated regardless of the state of the OE input signal This allows the external logic to present the data on DQs and DQP 4 g In addition the address for the subsequent access Read Write Deselect is latched into the Address Register provided the
22. tic Discharge Voltage ss eee gt 2001V Storage Temperature ccc ceeeceteeeeeeees 65 C to 150 C per MIL STD 883 Method 3015 Ambient Temperature with Latch up Current gt 200 mA Power Applied 55 C to 125 C Operating Range Supply Voltage on Vpp Relative to GND 0 5V to 4 6V Ambient Supply Voltage on Vppq Relative to GND 0 5V to Vpp Range __ Temperature Ta Vop Vppa DC Voltage Applied to Outputs Commercial 0 C to 70 C 3 3V 5 2 5V 5 AAA ATT 0 5V to Vppq 0 5V Industrial 40 C to 485 C 10 to Vop Electrical Characteristics Over the Operating Rangel 1 Parameter Description Test Conditions Min Max Unit Vop Power Supply Voltage 3 135 3 6 V VDDQ I O Supply Voltage 2 375 Vpp V VoH Output HIGH Voltage for 3 3V I O lop 4 0 mA 2 4 V for 2 5V I O lop 1 0 mA 2 0 V VoL Output LOW Voltage for 3 3V I O ly 8 0 mA 0 4 V tor 2 5V 1 0 lyg 10mA o T 04 Tv Vin Input HIGH Voltage for 3 3V 1 0 2 0 Vpp 0 3V V for 2 5V I O 1 7 Vop 0 3V V Vi Input LOW Voltage for 3 3V I O 0 3 0 8 V for 2 5V I O 0 3 0 7 V Ix Input Leakage Current GND lt V lt Vppq 5 5 pA except ZZ and MODE Input Current of MODE Input Vss 30 pA Input Vpp 5 HA Input Current of ZZ Input Vss 5 uA Input Vpp 30 HA loz Output Leakage Current GND lt V lt Vppq Output Disabled 5 5 pA loo Vpp Operating Supply Vpp Max lour 0 mA 4 ns cycle 250 MHz 3
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