Cypress MoBL CY62157E User's Manual
Contents
1. Document 38 05695 Rev C Page 8 of 12 Feedback CYPRESS PERFORM CY62157E MoBL Truth Table CE CE WE OE BHE BLE Inputs Outputs Mode Power H X X X X X HighZ Deselect Power Down Standby lag X L X X X X 2 Deselect Power Down Standby lag X X X X H H High Z Deselect Power Down Standby lag L H H L L L Data Out 105 1035 Read Active loc L H H L H L Data Out 10 107 Read Active loc High Z IOg 1O L H H L L H High Z 05 105 Read Active loc Data Out lOg 1O45 L H H H L H High Z Output Disabled Active loc L H H H H L High Z Output Disabled Active loc L H H H L L High Z Output Disabled Active loc L H L X L L Data In 100 105 Write Active Icc L H L X H L Data In 10 1075 Write Active loc High Z lOg 1O 4 L H L X L H High Z lOg 1O Write Active Icc Data In IOg 1O 5 Ordering Information Speed Package Operating ns Ordering Code Diagram Package Type Range 45 CY62157ELL 45ZSXI 51 85087 44 pin Thin Small Outline Package Type II Pb free Industrial 55 CY62157ELL 55ZSXE 51 85087 44 pin Thin Small Outline Package Type II Pb free Automotive CY62157ELL 55BVXE 51 85150 48 ball Very Fine Pitch Ball Grid Array Pb free Document 38 05695 Rev C Page 9 of 12 Feedback eM H CYPRESS PERFORM Package Diagrams CY62157E MoBL 44 pin TSOP II2. be P 0 r R M M MEE M Ls c CY62157E MoBL YPRESS PERFORM Features Very high speed 45 ns Wide voltage range 4 5V 5 5V Ultra low standby power Typical Standby current 2 pA Maximum Standby current 8 A Industrial Ultra low active power Typical active current 1 8 mA f 1 MHz Ultra low standby power Easy memory expansion with CE and OE features Automatic power down when deselected CMOS for optimum speed power Available in Pb free 44 pin TSOP and 48 ball VFBGA package Functional Description The CY62157E is a high performance CMOS static RAM organized as 512K words by 16 bits This device features advanced circuit design to provide ultra low active current This is ideal for providing More Battery Life MoBL in portable applications such as cellular telephones The device 8 Mbit 512K x 16 Static RAM also has an automatic power down feature that significantly reduces power consumption when addresses are not toggling The device can also be put into standby mode when deselected HIGH or LOW or both and BLE are HIGH The input output pins IOg through IO z are placed in a high impedance state when deselected CE4HIGH or LOW outputs are disabled OE HIGH both Byte High Enable and Byte Low Enable are disabled BHE BLE HIGH or during a write operation CE LOW HIGH and WE LOW
3. 51 85087 VIEW BASE PLANE 400 0 016 gt 0 800 BSC 1400006 0 0315 0 300 0 012 c004 18 517 0 709 18 313 0 7210 1194 0 047 0 991 0 0395 0 150 0 0059 Document 38 05695 Rev C DIMENSIDN IN MM CINCH MAX MIN 2 10 262 0 4042 9 EJECTOR PIN BOTTOM VIEW 10 262 0 404 gt 0 597 0 02355 0406 0 0160 0 210 0 0083 0120 0 0047 51 85087 Page 10 of 12 Feedback Cd F CYPRESS PERFORM Package Diagrams continued TOP VIEW A1 CORNER 12 3 4 CY62157E MoBL 48 ball VFBGA 6 x 8 x 1 mm 51 85150 BOTTOM VIEW 1 CORNER 2005M C 0 25 MEAB 20 30 0 05 48 o w N Dje 8 00 0 10 rm Q 0 10C 5 6 A B c D 3 H 8 G H A B 6005010 19 2 s 5 S e ws H X 3 1 C C C T SEATING PLANE od 2 S 2 1 oooodo fa T 1 6 000000 18 p S t OOOOOO r N eoooe9oO 1 875 0 75 3 75 B 600010 47 C 0 15 4 51 85150 D MoBL is a registered tradem
4. BHE f 1 disc BLE Note 1 For best practice recommendations please refer to the Cypress application note System Design Guidelines on http www cypress com Cypress Semiconductor Corporation Document 38 05695 Rev 198 Champion Court San Jose CA 95134 1709 408 943 2600 Revised November 21 2006 CYPRESS Pin Configuration 31 CY62157E MoBL TSOP II VFBGA Top View Top View 1 2 3 4 5 6 A4 1 44 As N A302 43 O Ae aga oc Ay 4 41 OE F A AEs 6 39 BLE SBR Ce 9 CC 89 lO O 8 37 1 1044 1 1 C9 360 1043 SU RUE Voc 111 34 Vss 22 ae Hoo 09 6 As e es IO4 713 32 1 IO lOs 114 31 lO4o lOs 715 30 105 116 29 O lOg e 9 0 Aig L118 27 A17 O19 26 DOANE A45 121 24 Ayo A44 122 23 O A43 Product Portfolio Power Dissipation Speed Operating fcc mA Standby leg Vcc Range V ns f 1MHz f fmax uA Product Range Min Typ Max Typ Max Typ Max Typ Max CY62157E 45 Ind l 4 5 5 0 5
5. tup Data Hold from Write End 0 0 ns tuzwE WE LOW to High ZI 14 18 20 ns tLzwe WE HIGH to Low z 3 10 10 ns Notes 12 Test conditions for all parameters other than Tri state parameters assume signal transition time of 3 ns or less timing reference levels of 0 to and output loading of the specified as shown in the AC Test Loads and Waveforms section evels of Vccqypy2 input pulse 13 At any given temperature and voltage condition tuzcg is less than tj tyzpe is less than tj zgg is less than tj zog and tyzwe is less than tj zwg for any given device 14 tuzoe tuzcE and tyzwe transitions are measured when the outputs enter a high impedance state 15 The internal Write time of the memory is defined by the overlap of WE Vi and or BLE Vj and All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE The data input set up and hold timing should be referenced to the edge of the signal that terminates the Write Document 38 05695 Rev C Page 5 of 12 Feedback VCYPRESS CY 62157 MoBL Switching Waveforms Read Cycle 1 Address Transition Controlled 171 tac ADDRESS DATA OUT PREVIOUS DATA VALID DATA VALID Read Cycle 2 OE Controlled 18 ADDRESS CE BHE BLE HIGH DATA OUT HIGH IMPEDANCE CK ONAVAD SATA VALID
6. 45 ns Industrial 55 ns Automotive Parameter Description Test Conditions Min Typ Max Min Typ Unit Output HIGH 1 4 5 2 4 2 4 V Voltage VoL Output LOW 2 2 1 Vcc 4 5V 0 4 0 4 V Voltage Vin Input HIGH Voc 4 5V to 5 5V 2 2 Voc 0 5 NE Voc 0 5 V Voltage Vi Input LOW Vcc 4 5V to 5 5V 0 5 08 05 0 8 V Voltage lix Input Leakage GND lt Vi lt Vcc 1 1 1 Current loz Output Leakage GND lt Vo lt Vcc Output Disabled 1 1 1 1 pA Current loc Voc Operating f Triax 1 Voc 18 25 18 35 Supply 7 lout 0 mA mA Current CMOS levels 18 3 Ve d legi Automatic CE gt Voc 0 2V CE lt 0 2V 2 8 2 30 uA Power Down ViN gt Voc 0 2V Vin lt 0 2 Current f fmax Address and Data Only CMOS Inputs f 0 OE BHE BLE and WE Vec 3 60V Ispe Automatic CE CE gt 0 2V or lt 0 2V 2 8 2 30 Power Down Vin gt Voc 0 2V or Vin lt 0 2V Current f 0 Voc 3 60V CMOS Inputs Capacitance Parameter Description Test Conditions Max Unit Cin Input Capacitance TA 25 f 2 1 MHz Vcc Vcc typ 10 pF Cour Output Capacitance 10 pF Notes 6 Vit min 2 0 for pulse durations less than 20 ns for lt 30 mA 7 Vcc 0 75V for pulse durations less than 20 ns 8 Full device AC operation assumes a 100 us ramp time from 0 to Vcc min and 200 u
7. Writing to the device is accomplished by taking Chip Enable CE LOW and HIGH and Write Enable WE input LOW If Byte Low Enable BLE is LOW then data from IO pins through 1 is written into the location specified on the address pins Ag through A48 If Byte High Enable is LOW then data from IO pins IO through IO is written into the location specified on the address pins Ag through A48 Reading from the device is accomplished by taking Chip Enable LOW and HIGH and Output Enable OE LOW while forcing the Write Enable WE HIGH If Byte Low Enable BLE is LOW then data from the memory location specified by the address pins will appear on to IO If Byte High Enable BHE is LOW then data from memory will appear on lOg to See the truth table at the back of this data sheet for a complete description of read and write modes Logic Block Diagram DATA IN DRIVERS A10 gt Ag Ag p A Ag p A5 ___ A2 gt 512K x 16 RAM Array ROW DECODER 45 10 10 SENSE AMPS 45 10 1035 COLUMN DECODER A 5 gt 6 A17 gt e lt BHE L CE 2 1 oE _p CE BLE POWER DOWN CIRCUIT
8. zh 291273 See ECN PCI New data sheet A 457689 See ECN NXR Added Automotive Product Removed Industrial Product Removed 35 ns and 45 ns speed bins Removed L bin Updated AC Test Loads table Corrected tp in Data Retention Characteristics from 100 us to tac ns Updated the Ordering Information and replaced the Package Name column with Package Diagram B 467033 See ECN NXR Added Industrial Product Final Information Removed 48 ball VFBGA package and its relevant information Changed the Ic c typ value of Automotive from 2 mA to 1 8 mA for f 1MHz Changed the value of Automotive from 5 pA to 1 8 uA Modified footnote 4 to include current limit Updated the Ordering Information table 569114 See VKN Added 48 ball VFBGA package Updated Logic Block Diagram Added footnote 3 Updated the Ordering Information table Page 12 of 12 Feedback
9. 5 45 1 8 3 18 25 2 8 62157 55151 Auto 4 5 5 0 5 5 55 1 8 4 18 35 2 30 Notes 2 NC pins are not connected on the die 3 The 44 pin TSOP II package has only one chip enable CE pin 4 Typical values are included for reference only and are not guaranteed or tested Typical values are measured at Vcc Ta 25 C 5 Automotive product information is Preliminary Document 38 05695 Rev C Page 2 of 12 Feedback oM LLL ILL lt a CYPRESS CY62157E MoBL PERFOR ee Maximum Ratings DC Input Voltagel 1 0 5V to 6 0V LAbavawhich fie aeui fe For aser audes Oupa uneni into Outputs LOW 20 mA lines not tested Static Discharge Voltage nct gt 2001V Storage Temperature 65 C to 150 C 4 Meine sets ee Temperatura with atch Up Current 2 gt m Power Applied 55 C to 125 Operating Range Supply Voltage to Ground Ambient Potential 0 5V to 6 0V Device Range Temperature Vec DC Voltage Applied to Outputs in High 7 State 1 Se ee Automotive 40 to 125 C Electrical Characteristics Over the Operating Range
10. IMPEDANCE Vec Icc SUPPLY 50 50 CURRENT Isg Notes 16 The device is continuously selected OE CE BHE and or BLE Vj and Vi 17 WE is HIGH for read cycle 18 Address valid prior to or coincident with CE4 BLE transition LOW and CE transition HIGH Document 38 05695 Rev C Page 6 of 12 Feedback CY62157E MoBL F CYPRESS Switching Waveforms continued Write Cycle 1 WE Controlled 5 19 20 21 two ADDRESS 7 SS AR tua SA we PWE aw DATA 2 WWE VEEL MEME tsa taw ipwE lizoE 18 De ata IO is high impedance if OE 20 If ge s HIGH a rd goe Lov simultaneous ly with WE Vip the output rema a high impedance state 21 Duri rin bs por iod the are in output state and in ui signale should rate Document 38 05695 Rev Page 7 of 12 Feedback y CYPRESS PERFORM Switching Waveforms continued Write Cycle 3 WE Controlled OE 1 0 20 21 CY62157E MoBL two SSS 2222 ae SLM BHE BLE MASSE SN ton owe S T SSN e omo EET CXTRA D XX t LAWE Write Cycle 4 BHE BLE Controlled OE Low 2 211 c WY M taw t SA WE SS SS SS Y gt 2 1 tsp omo KET OO COS
11. ark and More Battery Life is a trademark of Cypress Semiconductor Corporation All product and company names mentioned in this document are the trademarks of their respective holders Document 38 05695 Rev C Cypress Semiconductor Corporation 2006 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Page 11 of 12 Feedback CYPRESS PERFORM Document History Page CY62157E MoBL Document 38 05695 Rev C Document Title CY62157E MoBL 8 Mbit 512K x 16 Static RAM Document Number 38 05695 Orig of REV NO Issue Date Change Description of Change
12. s wait time after Voc stabilization 9 Tested initially and after any design or process changes that may affect these parameters Document 38 05695 Rev C Page 3 of 12 Feedback 4 iE V CYPRESS CYGZIS7E PERFORM Thermal Resistance Parameter Description Test Conditions TSOP II VFBGA Unit OJA Thermal Resistance Still Air soldered on a 3 x 4 5 inch 77 72 C W Junction to Ambient two layer printed circuit board Ojc Thermal Resistance 13 8 86 C W Junction to Case AC Test Loads and Waveforms R1 Veo ALL INPUT PULSES OUTPUT oe 90 GND 10 30 pF Rise Time 1 V ns gt Fall Time 1 V ns INCLUDING JIG AND 7 E SCOPE Equivalent to THEVENIN EQUIVALENT RTH OUTPUT o w o V Parameters Values Unit R1 1800 R2 990 Q 639 Q VIH 1 77 V Data Retention Characteristics Over the Operating Range Parameter Description Conditions Min Typ Max Unit VDR Vcc for Data Retention 2 V locpr Data Retention Current Vcc 2V CE Voc 0 2V Industrial 8 pA lt 0 2V Vin gt Voc 0 2V or VIN lt 0 2V Automotive 30 Chip Deselect Data 0 ns Retention Time 91 Operation Recovery Time tac ns Data Retention Waveform DATA RETENTION MODE Vice Vec min Von 2V CE or BHE BLE Notes 10 Full de
13. vice operation requires linear Vac ramp from Vpg to gt 100 us or stable at Vcc min gt 100 us 11 BHE BLE is the AND of both BHE and BLE Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE Document 38 05695 Rev C Page 4 of 12 Feedback Switching Characteristics Over the Operating Range 2 CY62157E MoBL 45 ns 55 ns Parameter Description Min Max Min Max Unit Read Cycle tnc Read Cycle Time 45 55 ns TAA Address to Data Valid 45 55 ns Data Hold from Address Change 10 10 ns tACE CE LOW and HIGH to Data Valid 45 55 ns tpoE OE LOW to Data Valid 22 25 ns lizoE OE LOW to LOW 71131 5 5 ns tuzoE OE HIGH to High 2113 14 18 20 ns lizcE CE LOW and CE HIGH to Low 21131 10 10 ns tuzcE CE HIGH and CE LOW to High 2113 14 18 20 ns tpy CE LOW and HIGH to Power Up 0 0 ns tpp CE HIGH and CE LOW to Power Down 45 55 ns tpBE BLE BHE LOW to Data Valid 45 55 ns LZBE BLE BHE LOW to Low 21131 10 10 ns luzpE BLE BHE HIGH to HIGH 2113 141 18 20 ns Write Cyclel twc Write Cycle Time 45 55 ns tecE CE LOW and CE HIGH to Write End 35 40 ns taw Address Set Up to Write End 35 40 ns tua Address Hold from Write End 0 0 ns tsa Address Set Up to Write Start 0 0 ns tpwe WE Pulse Width 35 40 ns tew BLE BHE LOW to Write End 35 40 ns tsp Data Set Up to Write End 25 25 ns
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