Cypress ISR 37000 CPLD User's Manual
Contents
1. o n D a i n 990099 7048690 aauboa g o n n g D D Q 9 o 5 00 0 20 eouooco lt 4 lt o a D a D o a 50 0589595589 D 5 4 2 5 2 15 875 210 25 2 1 17 0 D5 2350 15 210 15 c ITTYIITITITTTIITITITITYTITITITYTITITITYTITITITITIIKI o 51 85103 C SEATNG PLANE 0 56 0 60 0 10 Document 38 03007 61 of 64 Feedback CYPRESS Ultra37000 CPLD Famil Package Diagrams continued 400 Ball FBGA 21 x 21 x 1 4 mm BB400 20 25 QA BIC gans 20 10 WIC Al CORNER 20 45 0 05 400X 1234567 8 9 1011 121314151617 1819 20 201918 1715 15141312 10 9 7654321 amp B B C D O O O O O2. 2 e e OoooooococlooooooonDo gt e 0000000000000 8 5 e 8 6 g 5 w OOOOO000 gt 9 ocoooocoococooo a m ow u gt gs2 m x leal 23 88 AS 001 S SIS lt 2 054 3 Sa n 00 lt 4 01 0 0071 2 4 500 SEO 256 Ball FBGA 17 x 17 mm BB256 Feedback Page 59 of 64 51 85108 10 11 12 13 14 15 16 9 8 VIEW 7 0 56 36 PLANE 140 MAX 1 70 MAX CYPRESS Package Diagrams continued lt m O uu r x lt gt 500 0 0 lt 25201 4 1 CORNER Document 38 03007 Rev Document 38 03007 Rev Ultra37000 CPLD Famil 51 85097 B Page 60 of 64 Feedback Ultra37000 CPLD Famil PIN 1 CORNER 41 00 REF eoconoooaoooonooon0ooonooooQ oagbpoaapnooanmnboeaaooaanooaaag
3. 33 of 64 Feedback Pin Configurations continued 100 ball Fine Pitch BGA BB100 for CY37064V Ultra37000 CPLD Famil Top View 1 2 3 4 5 6 7 8 9 10 A Nc vo vO Oso Ogg 105 Ose B Og vog WO 10 Voc Oss NC Vo NC NC 1041 Voc TDI Os D Oy NC WO VO VO NC CLKy 105 la E 10 vog Nc GND GND 104 10 105 lo F Nc Nc GND GND NC lj G o 109 VOqg 10 NC 104 1 053 TMS Voc O32 1 042 Vec 9 NC VO NC 1 104 105 10 VOj NC NC 100 ball Fine Pitch BB100 for CY37128V Top View 1 2 3 4 5 6 7 8 9 10 A Nc vog vOs vog 10 10 WO WO B VO vo vos VOS VOz Voc O73 Oss l Ogg WO VO Voc 10 WO WO 1055 Voc 1 l Ogg TCK TDI D NC l O VO VOo VO 1 CLKy 11065 la wo 04 GND GND 106 Og CLK 10 lo ls F Oj vO VO GND GND 1 Oss 12 EN G
4. Top View GND GND 10 104 GND GND 2 1 0233 1 0232 GND GND GND GND GND NC 104 1043 VO o GND GND 056 Voc 1 0231 VOz25 GND GND GND GND GND GND 105 10 109 GND GND Voc O228 GND GND GND NC NC GND 1048 1 Og GND GND 1 O236 O44 l Og45 GND 1027 104 1 043 10 NC 1 05 WO UO234 VO2so 248 WO242 225 226 1O47 104 vo Oso NC Og Os VO3 WO2 2 UO249 1 0247 1 0220 1 0221 1 0222 l O223 224 VOss Ogg O5 05 VO2 1 0217 VO248 VOo1g VOz42 1014 215 Voc Voc 1 1 TCK 1 59 2 TDI O246 Vcc l Ogg 1 Osg VOgz Ose VO s VOsa WOs2 WOo WO2ss UO2o2 CLK3 VO2o4 5 l Ozoz 1 O208 209 GND GND GND GND 1 06 GND GND 199 01 GN
5. gt gt lt gt gt 110 594 045 1210 2 S OGIC s LOGI LOGI 6 OG i 36 12 I Os LOGI LOGI 12 VO 2 59 LOGIC 5 lt gt lt 16 16 BLOCK K BF tae 12 I Os 12 105 Yosio 4 roseo t ib 12 12 LOGIC l Ogg l O407 lt lt BLock fe lt gt 1 17 36 12 I Os LOGIC LOGIC 12 5 I O40g l O119 BLOCK 46 F lt 104 106 36 12 I Os LOGIC LOGIC 12 I Os l O429 1 O434 lt stock gt lt gt 444 1 155 BLOCK 16 16 BLOCK gt lt gt 1 0439 l 0 132 132 TDI JTAG Tap TCK TDO TMS Controller Document 38 03007 Rev E Ultra37000 CPLD Famil Page 13 of 64 Feedback e y CYPRESS 5 0V Device Characteristics DC Voltage Applied to Outputs Ultra37000 CPLD Famil Maximum Ratings in High Z 2222122 0 5V to 7 0V DG Input Voltage nenne 0 5V to 7 0V i DC Program 4 5 to 5 5V Storage Temperature 65 C to 150 Current into Outputs 16 mA i Static Discharge gt 2001V 2
6. NC NC 109 l O4g NC Ong 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Document 38 03007 Rev E Page 38 of 64 Feedback Ultra37000 CPLD Famil 256 Ball Fine Pitch BGA BB256 Top View 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A GND GND 10 VO Vec GND GND 1046 VO O14172 O45 GND GND B GND 10 1 104 104 GND GND VO s VOr76 GND VO Oz NC WO VO VO Og WO VO 4g 1075 D NC WO 10 O3 10490 O183 VO za 10469 10460 1 1046 E Os O24 1 l Ogzg O173 O168 457 5 Odo Vec 1 10 TCK Vec 006 WO Oiss VOrg2 TDI VO s4 Oiss 10456 o vo 10 1 Oo VOqgz 104 CLKs 10450 l4 GND GND 1046 CLKo 10 GND GND 1 0444 1045 CLK 10446 O447 GND GND J GND GND 05 10 105 GND GND 100 12 VO142 GND GND K WOs7 Ose WO
7. Warp Professional TM Warp Professional contains several additional features It provides an extra method of design entry with its graphical block diagram editor It allows up to 5 ms timing simulation instead of only 2 ms It allows comparison of waveforms before and after design changes Warp Enterprise Warp Enterprise provides even more features It provides unlimited timing simulation and source level behavioral simulation as well as a debugger It has the ability to generate graphical HDL blocks from HDL text It can even generate testbenches Warp is available for PC and UNIX platforms Some features are not available in the UNIX version For further information see the Warp for PC Warp for UNIX Warp Professional and Warp Enterprise data sheets on Cypress s web site www cypress com Third Party Software Although Warp is a complete CPLD development tool on its own it interfaces with nearly every third party EDA tool All major third party software vendors provide support for the Ultra37000 family of devices Refer to the third party software data sheet or contact your local sales office for a list of currently supported third party vendors Programming There are four programming options available for Ultra37000 devices The first method is to use a PC with the 37000 UltralSR programming cable and software With this method the ISR pins of the Ultra37000 devices are routed to a connector at the edge of the printe
8. Fine Pitch Ball Grid Array 100 CY37032VP44 100AC 44 44 Lead Thin Quad Flat Pack Commercial CY37032VP44 100AXC A44 44 1 Lead Free Thin Quad Flat Pack CY37032VP48 100BAC BA50 48 Fine Pitch Ball Grid Array CY37032VP44 100AI A44 44 Lead Thin Quad Flat Pack Industrial CY37032VP44 100AXI 44 44 1 Lead Free Thin Quad Flat Pack CY37032VP48 100BAI 50 48 Fine Pitch Ball Grid Array CY37032VP44 100JI J67 44 Lead Plastic Leaded Chip Carrier CY37032VP44 100JXI J67 44 Lead Lead Free Plastic Leaded Chip Carrier Document 38 03007 Rev E Page 46 of 64 Feedback Ultra37000 CPLD Famil CYPRESS 3 3V Ordering Information continued Speed Package Operating Macrocells MHz Ordering Code Name Package Type Range 64 143 CY37064VP44 143AC A44 44 Lead Thin Quad Flatpack Commercial CY37064VP44 143AXC A44 44 1 Lead Free Thin Quad Flatpack CY37064VP48 143BAC 50 48 Fine Pitch Ball Grid Array CY37064VP100 143AC A100 100 Lead Thin Quad Flatpack CY37064VP100 143AXC A100 100 Lead Lead Free Thin Quad Flatpack CY37064VP100 143BBC BB100 100 Ball Fine Pitch Ball Grid Array 100 CY37064VP44 100AC A44 44 Lead Thin Quad Flatpack Commercial CY37064VP44 100AXC 44 44 1 Lead Free Thin Quad Flatpack CY37064VP48 100BAC 50 48 Fine Pitch Ba
9. CLK 10 VOg VO VO H WOs Voc VO 5 TDO J WO O35 1045 WO WOso K VOg VO37 VO VO Document 38 03007 Rev E Page 34 of 64 Feedback Ultra37000 CPLD Famil 160 Lead TQFP A160 CQFP U162 for CY37128 V and CY37256 V Top View 1042 O44 O4o 10127 10126 10125 10124 10123 10122 121 119 118 O447 O416 10445 10444 10413 10412 GND E o gt 135 PD i 134 7 124 ES 123 122 O GND 41 42 VO4g 43 44 J 45 lOg TMS Hl 46 I Os 47 I Os X 48 49 72 O3 0 73 74 D 75 l Oz TDO 76 77 78 79 Veco 80 l Os4 Document 38 03007 Rev Vcco O411 O410 O109 O4og TDI O107 O106 O105 O104 GND O103 O102 O101 O100 9 Oo7 96 CLK3 I4 GND Vcco CLKo l3 Oos 4 92 1 89 88 GND Ogz 5 2 1 Ogo GND Page 35 of 64 Feedback Ultra37000 CPLD Famil Q o Qezeosre 800
10. Feedback or d Ultra37000 CPLD Famil CYPRESS Inductance 44 Lead 44 Lead 44 Lead 84 Lead 84 Lead 100 Lead 160 Lead 208 Lead Parameter Description Test Conditions TQFP PLCC CLCC PLCC CLCC TQFP TQFP PQFP Unit L Maximum Pin Vi 5 0V 2 5 2 8 5 8 11 nH Inductance 1 MHz Parameter Description Test Conditions Max Unit Input Output Vin 5 0V atf 1 MHz at T4 25 C 10 pF Signal Vin 5 0V atf 1 MHz at TA 25 12 pF Cpp Dual Function Pins Vin 5 0V atf 1 MHz at TA 25 16 pF Endurance Characteristics Parameter Description Test Conditions Min Typ Unit IN Minimum Reprogramming Cycles Normal Programming Conditions 1 000 10 000 Cycles 3 3V Device Characteristics DC Voltage Applied to Outputs Maximum Ratings in High Z State as saus saus 0 5V to 7 0V DC Input 0 5V to 7 0V DC Program 3 0 to 3 6V Storage Temperature 65 C to 150 C Current into Outputs irent entire 8 mA Static Discharge
11. L LL 04 LL 70118 CJ 1 0117 CJ L O44 LH 1 0115 O45 EJ L3 1 0444 O4 LJ 1 1 0443 1 0412 L 1 0444 GND Lo 1 1 0440 Oso L GND 051 1 O109 O5 LJ 7 LJ 1 0106 NCC Ll 1005 Oss 0104 CJ m 0103 lOs CJ 1 0102 Os3 C 1 0 CJ 1 0100 Veco GND Document 38 03007 Rev E Page 37 of 64 Feedback 292 Ball PBGA BG292 Ultra37000 CPLD Famil Top View 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 A GND Ox NC l Og 10 2 Oo WO VOo NC l Oqzg NC NC B O19 105 Og WO WO 1 0191 NC NC 1 0474 10471 NC NC NC WO 105 NC VOrg4 179 1 473 1 0172 10465 1 0462 D NC GND NC Veco GND NC Vec GND 1 0477 NC GND TDI E
12. Ogg NC l O4e 10464 1 0456 F TCK WOjs Veco 5 NC 1 0454 G O33 WO VO 45 1 0455 1 0452 H lOss NC GND GND GND GND GND GND GND GND 1 0451 1 0449 J GND GND GND GND GND GND O49 l O4g Voc GND GND GND GND GND GND l Oq44 NC NC L 1043 O44 GND GND GND GND GND GND CLK s 1 0443 NC M O47 CLKo lo CLK4 I 1 048 GND GND GND GND GND GND O441 1 0442 N GND GND GND GND GND GND GND GND 10436 0437 138 VOs3 WOss VOsg 1 0434 1 0433 1 0134 R l Og4 VOss WOso Veco Veco 1 0432 T Og VOgo 1 06 l Ogs 1 0427 VO428 1 0429 U 10 1 06 GND Veco GND Vcc l Ogg l Oqp GND GND O43 1 04 1 0426 V WO l Ogg Og VOss 1 l Oqog Oqua 1 0125 W Os 10 VOss Ogg 1053 l Ogs l Ogg l O494 l O49z NC NC 1046 l Oqg 1 04120 Y VOz TMS Ogo l Ogz l Ogo
13. PIN 1 CORNER 12 35 4 5 6 7 9 14 109 87 6 5 4 3 2 1 N gt 11 00 0 10 e ooooiloooo oococooloooo Iro mim G Q 8 a 5 8 11 00 D 1D E E 9 cs 0 156430 SEATING PLANE m u 5 51 85107 B 5 Document 38 03007 Rev E Page 54 of 64 Feedback Ultra37000 CPLD Famil NS 4 lt bbb 51 85049 Document 38 03007 Rev E Page 55 of 64 Feedback Ultra37000 CPLD Famil 160 Lead Ceramic Quad Flatpack Cavity Up U162 25 35 0 10 998 004 DIMENSION IN MM INCH TYP REFERENCE JEDEC N A PKG WEIGHT 6 7gms PIN 1 N 0 650 0256 r 0 300 012 TYP eS R 0 13 005 MIN n 28 00 0 10 1 102 004 0 20 MIN teed 50 008 31 20 0 25 46477 0 1 228 010 50 DETAIL A SEE DETAIL SEATING PLANE V 0 15 0 02 006 001 0 51 0 20 020 008 51 80106 Document 38 03007 56 of 64 Feedback Ultra37000 CPLD Famil TEETH EH TEE 1 Em 156 DIMENSIONS ARE
14. CY37128P100 100AXC CY37128P160 100AXC CY37128P100 100AXI CY37192P160 154AXC CY37192P160 125AXC CY37192P160 125AXI CY37192P160 83AXC CY37192P160 83AXI CY37256P160 154AXC CY37256P160 125AXC CY37256P160 125AXI CY37256P160 83AXC CY37256P160 83AXI CY37032VP44 143AXC CY37032VP44 100AXC CY37032VP44 100AXI CY37032VP44 100JXI CY37064VP44 143AXC CY37064VP100 143AXC CY37064VP44 100AXC CY37064VP100 100AXC CY37064VP44 100AXI CY37064VP100 100AXI CY37128VP100 125AXC CY37128VP160 125AXC CY37128VP160 125AXI CY37128VP100 83AXC CY37128VP160 83AXC CY37128VP100 83AXI CY37128VP160 83AXI CY37192VP160 100AXC CY37192VP160 66AXC CY37256VP160 100AXC CY37256VP160 100AXI CY37256VP160 66AXC E 321635 See ECN PCX Added Package Diagram BG292 Updated all PBGA package type information BG292 amp BG388 Document 38 03007 Rev E Page 64 of 64 Feedback
15. Cy YPRESS Features In System Reprogrammable ISR CMOS CPLDs JTAG interface for reconfigurability Design changes do not cause pinout changes Design changes do not cause timing changes High density 32 to 512 macrocells 32 to 264 I O pins Five dedicated inputs including four clock pins Simple timing model No fanout delays No expander delays No dedicated vs pin delays No additional delay through PIM No penalty for using full 16 product terms No delay for steering or sharing product terms 3 3V and 5V versions PCI compatiblel Programmable bus hold capabilities on all I Os Intelligent product term allocator provides 0 to 16 product terms to any macrocell Product term steering on an individual basis Product term sharing among local macrocells Flexible clocking Four synchronous clocks per device Product term clocking Clock polarity control per logic block Consistent package pinout offering across all densities Simplifies design migration Same pinout for 3 3V and 5 0V devices Packages 44 to 400 leads in PLCC CLCC PQFP TQFP CQFP BGA and Fine Pitch BGA packages Lead Pb free packages available Note Ultra37000 CPLD Family 5V 3 3V ISR High Performance CPLDs General Description The Ultra37000 family of CMOS CPLDs provides a range of high density programmable logic solutions with un
16. Each input macrocell has access to all four synchronous clocks Dedicated Inputs Clocks Five pins on each member of the Ultra37000 family are desig nated as input only There are two types of dedicated inputs on Ultra37000 devices input pins and input clock pins Figure 3 illustrates the architecture for input pins Four input options are available for the user combinatorial registered double registered or latched If a registered or latched option is selected any one of the input clocks can be selected for control Figure 4 illustrates the architecture for the input clock pins Like the input pins input clock pins can be combinatorial registered double registered or latched In addition these pins feed the clocking structures throughout the device The clock path at the input has user configurable polarity Product Term Clocking In addition to the four synchronous clocks the Ultra37000 family also has a product term clock for asynchronous clocking Each logic block has an independent product term clock which is available to all 16 macrocells Each product term clock also supports user configurable polarity selection Document 38 03007 Rev Timing Model One of the most important features of the Ultra37000 family is the simplicity of its timing All delays are worst case and System performance is unaffected by the features used Figure 5 illustrates the true timing model for the 167 MHz devices in high speed m
17. GND GND GND GND GND NC Ogg 10400 l O491 VOr07 1 GND GND VO 43 1 0161 10446 NC GND GND Document 38 03007 Rev E Page 41 of 64 Feedback Ordering Information Ultra37000 CPLD Famil 37512 400 83 BB XC Cypress Semiconductor ID Conditions Family Type Commercial 0 C to 70 C 37 Ultra37000 Family Industrial 40 to 85 Military 55 C to 125 C Macrocell Density Lead Free 32 32 Macrocells 256 256 Macrocells Lead Free 64 64 Macrocells 384 384 Macrocells Package Type 128 128 Macrocells 512 512 Thin Quad Flat Macrocells U Ceramic Quad Flat Pack CQFP 492 5102 Plastic Quad Flat PQFP perating Reference Voltage NT Thermally Enhanced Plastic Quad Flat Pack Supply Voltage EQFP 5 0V if not specified J Plastic Leaded Chip Carrier PLCC Pin Count Y Ceramic Leaded Chip Carrier CLCC P44 44 Leads BG Plastic Ball Grid Array PBGA P48 48 Leads BA Fine Pitch Ball Grid Array FBGA P84 84 Leads 0 8mm Lead Pitch P100 100 Leads BB Fine Pitch Ball Grid Array FBGA P160 160 Leads 1 0mm Lead Pitch P208 208 Leads P256 256 Leads Speed P352 352 Lea
18. 5 0V Power Consumption CY37032 60 High Speed 50 40 Low Power lt 20 10 4 0 r 0 50 100 150 200 250 Frequency MHz The typical pattern is a 16 bit up counter per logic block with outputs disabled 5 0V TA Room Temperature CY37064 90 80 High Speed 70 60 50 t Low Power o 2 40 30 20 10 0 r r 0 20 40 60 80 100 120 140 160 180 Frequency MHz The typical pattern is a 16 bit up counter per logic block with outputs disabled 5 0V TA Room Temperature Document 38 03007 Rev E Page 24 of 64 Feedback Ultra37000 CPLD Famil CY37128 160 140 4 High Speed 120 4 100 4 Low Power lt s 8 60 4 40 4 20 4 0 0 20 40 60 80 100 120 140 160 180 Frequency MHz The typical pattern is a 16 bit up counter per logic block with outputs disabled 5 0V TA Room Temperature CY37192 300 2504 High Speed 2004 lt 150 8 100 4 50 4 0 0 20 40 60 80 100 120 140 160 180 Frequency MHz The typical pattern is a 16 bit up counter per logic block with outputs disabled 5 0V Ta Room Temperature Document 38 03007 Rev E Page 25 of 64 Feedback Ultra37000 CPLD Famil CY37256 300 High Speed 250 4 200 4 Low Power lt 150 5 100 4 50 4 0 0 20 40 60 80 100 120 140 160 180 Frequency
19. have been incorporated in the timing specifications for the Ultra37000 devices Ultra37000 Macrocell Within each logic block there are 16 macrocells Macrocells can either be I O Macrocells which include an Cell which is associated with an I O pin or buried Macrocells which do not connect to an The combination of Macrocells and buried Macrocells varies from device to device Buried Macrocell Figure 2 displays the architecture of buried macrocells The buried macrocell features a register that can be configured as combinatorial a D flip flop a T flip flop or a level triggered latch The register can be asynchronously set or asynchronously reset at the logic block level with the separate set and reset product terms Each of these product terms features program mable polarity This allows the registers to be set or reset based on an AND expression or an OR expression Clocking of the register is very flexible Four global synchronous clocks and a product term clock are available to clock the register Furthermore each clock features program mable polarity so that registers can be triggered on falling as well as rising edges see the Clocking section Clock polarity is chosen at the logic block level Page 4 of 64 Feedback buried macrocell also supports input register capability The buried macrocell can be configured to act as an input register D type or latch whose input comes fro
20. inputs travel through the PIM As a result there are no route dependent timing param eters on the Ultra37000 devices The worst case PIM delays are incorporated in all appropriate Ultra37000 specifications Routing signals through the PIM is completely invisible to the user All routing is accomplished by software no hand routing is necessary Warp and third party development packages automatically route designs for the Ultra37000 family in a matter of minutes Finally the rich routing resources of the Ultra37000 family accommodate last minute logic changes while maintaining fixed pin assignments Document 38 03007 Rev E Logic Block The logic block is the basic building block of the Ultra37000 architecture It consists of a product term array an intelligent product term allocator 16 macrocells and a number of cells The number of I O cells varies depending on the device used Refer to Figure 1 for the block diagram Product Term Array Each logic block features a 72 x 87 programmable product term array This array accepts 36 inputs from the PIM which originate from macrocell feedbacks and device pins Active LOW and active HIGH versions of each of these inputs are generated to create the full 72 input field The 87 product terms in the array can be created from any of the 72 inputs Of the 87 product terms 80 are for general purpose use for the 16 macrocells in the logic block Four of the remaining seven product te
21. the Array PRODUCT TERM CLOCK REGISTERED OUTPUT Registered Output with Product Term Clocking Input Coming From Adjacent Buried Register INPUT PRODUCT TERM CLOCK REGISTERED OUTPUT Latched Output INPUT LATCH ENABLE LATCHED OUTPUT Document 38 03007 Rev E Page 21 of 64 Feedback Ultra37000 CPLD Famil CYPRESS Switching Waveforms continued Registered Input REGISTERED INPUT INPUT REGISTER CLOCK COMBINATORIAL OUTPUT CLOCK Clock to Clock INPUT REGISTER CLOCK gt tscs tics OUTPUT REGISTER CLOCK Latched Input LATCHED INPUT LATCH ENABLE COMBINATORIAL OUTPUT a Document 38 03007 22 64 Feedback Ultra37000 CPLD Famil CYPRESS Switching Waveforms continued Latched Input and Output tico ts INPUT LATCH ENABLE tics gt OUTPUT LATCH ENABLE twH d tw LATCH ENABLE Asynchronous Reset taw INPUT tro REGISTERED OUTPUT CLOCK Asynchronous Preset tpo REGISTERED OUTPUT CLOCK Output Enable Disable INPUT tea OUTPUTS Page 23 of 64 Document 38 03007 Rev E Feedback CYPRESS Power Consumption Ultra37000 CPLD Famil Typical
22. ticg tig MHz or 1 Reset Preset Parameters trw Asynchronous Reset Width ns I Asynchronous Reset Recovery ns incl 14 15 Asynchronous Reset to Output ns tpw Asynchronous Preset Width ns tpp Asynchronous Preset Recovery ns tpo 14 Asynchronous Preset to Output ns User Option Parameters tip Low Power Adder ns tsLEW Slow Output Slew Rate Adder ns 3 3V Mode Timing ns JTAG Timing Parameters ts JTAG Set up Time from TDI and TMS to 5 lume Hold Time on TDI TMS ns tco JTAG Falling Edge of TCK to ns Maximum JTAG Tap Controller Frequency ns Document 38 03007 Rev E Page 18 of 64 Feedback CYPRESS Switching Characteristics Over the Operating Range 12 Ultra37000 CPLD Famil 200 MHz 167 MHz 154 MHz 143 MHz 125 MHz 100 MHz 83MHz 66 MHz Parameter 8 u Unit Combinatorial Mode Parameters 75 14 T9 6 6 5 7 5 8 5 10 15 ns 14 19 11 12 5 14 5 16 16 5 19 ns 173 14 15 12 13 5 15 5 17 17 5 20 ns teal 14 19 8 8 5 11 13 14 19 ns 8 8 5 11 13 14 19 ns Input Register Parameters twi 2 5 2 5 2 5 2 5 3 3 4 5 ns 2 5 2 5 2 5 2 5 3 3 4 5 ns
23. 00000 gt gt 21 This pin is but Cypress recommends that you connect it to Vcc to ensure future compatibility Document 38 03007 Rev E 44 45 46 47 48 49 50 51 a E e VO 39 L GND 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 GND 55 53 52 51 50 49 48 GND Vcco VO 47 1O 46 4 VO 44 45 45 UO 4 Page 32 of 64 Feedback Ultra37000 CPLD Famil 100 lead TQFP A100 Top View TR M 22588 8 5 o 85 9900009000089 100 99 98 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 _ C Os 106 99 Os 9 1052 C os 03 C 04 05 L 104 Veco Veco CLK ally 1 O47 VO s O19 C 1 li p O Veco ENP N nc 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 20 949 85 88 gt 9 Yr gt Document 38 03007
24. 160 Lead Lead Free Thin Quad Flat Pack 125 7192 160 125 A160 160 Lead Thin Quad Flat Pack Commercial CY37192P160 125AXC A160 160 Lead Lead Free Thin Quad Flat Pack CY37192P160 125Al A160 160 Lead Thin Quad Flat Pack Industrial CY37192P160 125AXI A160 160 Lead Lead Free Thin Quad Flat Pack 83 CY37192P160 83AC A160 160 Lead Thin Quad Flat Pack Commercial CY37192P160 83AXC A160 160 Lead Lead Free Thin Quad Flat Pack CY37192P160 83Al A160 160 Lead Thin Quad Flat Pack Industrial CY37192P160 83AXI A160 160 Lead Lead Free Thin Quad Flat Pack Document 38 03007 Rev E Page 44 of 64 Ultra37000 CPLD Famil CYPRESS 5 0V Ordering Information continued Speed Package Operating Macrocells MHz Ordering Code Name Package Type Range 256 154 CY37256P160 154AC A160 160 Lead Thin Quad Flat Pack Commercial 7256 160 154 A160 160 Lead Lead Free Thin Quad Flat Pack CY37256P208 154NC N208 208 Lead Plastic Quad Flat CY37256P256 154BGC BG292 292 Ball Plastic Ball Grid Array 125 7256 160 125 A160 160 Lead Thin Quad Flat Pack Commercial CY37256P160 125AXC A160 160 Lead Lead Free Thin Quad Flat Pack CY37256P208 125NC N208 208 Lead Plastic Quad Flat Pack CY37256P256 125BGC BG292 292 Plastic Ball Grid Array CY37256P160 125Al A160 160 Lead Thin Quad
25. 2 I Os lt gt l O18 1 O494 l O42 l O55 12 5 12 I Os lt gt l O456 1 O479 l O24 l Oss 12 I Os lt gt l Oq44 1 0167 12 1 O36 1 047 12 I Os lt gt 1 2 155 LOGIC ux pE 4 BLOCK B3 8 BLOCK 16 BLOCK gt robe c 16 BLOCK gt 53 BLOCK 18 BLOCK gt 12 12 I Os 12 I Os lt gt 1 0120 l1 0143 12 I Os 12 I Os lt gt l O408 1 O434 l Oz l Oga 12 gt lO5 lOqna LOGIC LOGIC DH 48 36 18 gt TDI Controller TMS 12 4 0 lt gt 12 I Os lt gt l Ogg l O Document 38 03007 Rev E Page 12 of 64 Feedback CYPRESS Logic Block Diagrams continued lis CY37512 CY37512V Input Input 4 4 LOGIC s 12 5 0 lt lt BLOCK 16 12 LOGIC 98 12 0 lt lt lt BLOCK 16 lt gt I O2s2 I O263 12 I Os 36 12 gt BLOCK 16 lt gt 1 0240 l 0251 LOGIC 39 12 BLOCK 16 lt gt 228 228 239 12105 LOGIC jx 1 O36 1 047 lt lt BLOCK 16 LOGIC 36 12 I Os BLOCK 76 lt gt 0516 0227 36 12 I Os LOGIC VO4g VO5g 2 9 BLOCK 16 Y 6 LOGIC LOGIC 12 1105 BLOCK do 16
26. 3V ISR High Performance CPLDs Document Number 38 03007 REV ECN NO Issue Date Orig of Change Description of Change 106272 124942 04 18 01 03 21 03 SZV OOR Change from Spec number 38 00475 to 38 03007 Updated 3 3V requirements for 144 speeds Added an Addendum 126262 05 09 03 TEH Changed pinout for CY37128V BB100 package 128125 07 16 03 HOM Obsoleted following 3 3V PLCC packaged devices CY37032VP44 143JC CY37032VP44 100JC 7032 44 100 CY37064VP44 143JC CY37064VP84 143JC CY37064VP44 100JC CY37064VP84 100JC CY37064VP44 100JI 7064 84 100 CY37128VP84 125JC CY37128VP84 83JC CY37128VP84 83Jl D 282709 See ECN YDT Changed package diagrams and labels for consistency Added Lead Pb free logo on first page as well as a note in Features Added Lead Pb free package diagram labels Added Lead free Parts to Ordering Information CY37032P44 200AXC CY37032P44 200JXC CY37032P44 154AXI CY37032P44 154JXI CY37032P44 125AXC CY37032P44 125JXC CY37064P44 200AXC CY37064P44 200JXC CY37064P100 200AXC CY37064P44 154AXI CY37064P44 154JXI CY37064P44 125AXC CY37064P44 125JXC CY37064P100 125AXC CY37064P44 125AXI CY37064P100 125AXI CY37128P84 167JXC CY37128P100 167AXC CY37128P160 167AXC CY37128P84 125JXC CY37128P100 125AXC CY37128P160 125AXC CY37128P84 125JXI CY37128P100 125AXI CY37128P160 125AXI CY37128P84 100JXC
27. 4 60 4 Low Power 50 4 lt 40 8 304 20 4 10 0 0 20 40 60 80 100 120 140 Document 38 03007 Rev E Frequency MHz The typical pattern is a 16 bit up counter per logic block with outputs disabled 3 3V TA Room Temperature Page 28 of 64 Feedback Ultra37000 CPLD Famil CY37192V 120 High Speed 100 4 80 4 Low Power lt 604 8 40 204 0 0 20 40 60 80 100 120 Frequency MHz The typical pattern is a 16 bit up counter per logic block with outputs disabled Vcc 3 3 TA Room Temperature CY37256V 140 120 High Speed 100 4 Low Power 80 4 lt 8 604 404 20 4 0 60 80 100 Frequency MHz The typical pattern is a 16 bit up counter per logic block with outputs disabled 3 3V TA Room Temperature Document 38 03007 Rev E Page 29 of 64 Feedback Ultra37000 CPLD Famil CY37384V 200 180 High Speed 160 140 4 Low Power 120 4 lt 100 E 80 4 60 4 40 4 20 4 0 0 10 20 30 40 50 60 70 80 90 Frequency MHz The typical pattern is a 16 bit up counter per logic block with outputs disabled Voc 3 3V Room Temperature CY37512V 250 200 High Speed 180 Low Power 2 8 100 50 4 0 50 60 70 80 90 Frequency MHz The typical pattern is a 16 bit up counter per logic block with outputs disabled Vcc 3 3V Room Temperatur
28. 43 14 15 16 17 18 19 20 21 22 23 24 25 26 GND GND 1 04 VO s 10 104 O VO4 vo 0631060 267 237 1 0250 1 0244 GND GND GND NC 10 VO 1 044 UOss O32 10 O44 Os VOg vo 0 5 0581055 1 0234 1 0228 l Og4g 10246 245 240 GND O37 1046 VO O33 l Ogg WO VO O 1 06 103 vo 0 5 5 056 253 5 1 0235 l O233 230 1 0251 1 0227 lOs 104 O gt 10 Vcco GND GND Veco Veco GND GND Vcco Veco NC 1 0223 O45 NC NC TDI 1 022 1 0229 l O43 1 022 1 0242 2021 1 0218 VO217 l O4g 1 0241 216 215 VO214 O49 VOsg 1 051 Veco 242 2 54 Veco O2o8 O2o9 210 Oss l Ogg l Og NC NC 10205 l Ozog 1 0207 105 GND GND GND GND GND GND GND GND V Oo94 l Oqgz Og Oso GND GND GND GND GND GND GND GND 1 WO2os MO2o2 Voc 10 Veco GND GND GND GND GND GND 1 0499 l Ogs Veco GND GND GND GND GND GND lOgg l Ogg GND GND
29. 55 C to 125 Per MIL STD 883 Method 3015 Supply Voltage to Ground 0 5V to 7 0V Latch up Currenit sassa gt 200 mA Operating Range Range Ambient Temperature Junction Temperature Output Condition Commercial 0 C to 70 C 0 to 90 C 5V 5V 0 25 5V 0 25V 3 3V 5V 0 25 3 3V 0 3V Industrial 40 C to 85 C 40 C to 105 C 5V 5V 0 5V 5V 0 5V 3 3V 5V 0 5V 3 3V 0 3V Military 55 10 125 C 55 C to 130 C 5V 5V 0 5V 5V 0 5V 3 3V 5V 0 5V 3 3V 0 3V 5 0V Device Electrical Characteristics Over the Operating Range Parameter Description Test Conditions Min Max Unit Vou Output HIGH Voltage Vec Min lop 3 2mA Com l Ing PT 24 V lop 2 0 mA 24 V Vouz Output HIGH Voltage with Max lou 0 pA 4 2 V Output Disabled lou 0 BA 45 V 100 pA 1 3 6 V 150 pA Ind Mil I 3 6 V VoL Output LOW Voltage Vcc Min 16 mA Com Ind 0 5 V lo 12 mA 05 V Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for all Inputs 2 0 Vccmax V Input LOW Voltage Guaranteed Input Logical LOW Voltage for all Inputs 0 5 0 8 V lix Input Load Current Vi GND OR Bus Hold Disabled 10 10 uA loz Output Leakage Current Vo GND Output Disabled Bus Hold Disabled 50 50 uA los Output Short CircuitCurren
30. 64P44 200JXC J67 44 Lead Lead Free Plastic Leaded Chip Carrier CY37064P84 200JC J83 84 Lead Plastic Leaded Chip Carrier CY37064P100 200AC A100 1 100 Thin Quad Flat Pack 7064 100 200 A100 100 Lead Lead Free Thin Quad Flat Pack Document 38 03007 Rev E Page 42 of 64 Feedback Ultra37000 CPLD Famil CYPRESS 5 0V Ordering Information continued Speed Package Operating Macrocells MHz Ordering Code Name Package Type Range 64 154 7064 44 154 A44 44 Lead Thin Quad Flat Pack Commercial CY37064P44 154JC J67 44 Lead Plastic Leaded Chip Carrier CY37064P84 154JC J83 84 Lead Plastic Leaded Chip Carrier CY37064P100 154AC A100 100 Lead Thin Quad Flat Pack 7064 44 154 44 44 Lead Thin Quad Flat Industrial CY37064P44 154AXI A44 44 Lead Lead Free Thin Quad Flat Pack 7064 44 154 J67 44 Lead Plastic Leaded Chip Carrier CY37064P44 154JXI J67 44 Lead Lead Free Plastic Leaded Chip Carrier CY37064P84 154Jl J83 84 Lead Plastic Leaded Chip Carrier CY37064P100 154Al A100 100 Lead Thin Quad Flat Pack 5962 9951902QYA Y67 44 Lead Ceramic Leadless Chip Carrier Military 125 CY37064P44 125AC A44 44 Lead Thin Quad Flat Pack Commercial CY37064P44 125AXC A44 44 Lead Lead Free Thin Quad Flat Pack CY37064P44 125JC J67 44 Lead Plastic Leaded Chip Carrier CY37064P44 125JXC J67 44 Lead Lead Free Plas
31. 7 Rev E Ultra37000 CPLD Famil The fourth method for programming Ultra37000 devices is to use the same programmer that is currently being used to program FLASH370i devices For all pinout electrical and timing requirements refer to device data sheets For ISR cable and software specifications refer to the UltralSR kit data sheet CY3700i Third Party Programmers As with development software Cypress support is available on a wide variety of third party programmers All major third party programmers including BP Micro Data I O and SMS support the Ultra37000 family Page 8 of 64 Feedback Ultra37000 CPLD Famil Logic Block Diagrams CY37032 CY37032V ock Input Input TBI JTAG Tap 4 Tus Controller TDO 4 JTAGEN 16 16 1 0 15 BLOCK PIM BLOCK 06 00 16 16 CY37064 CY37064V Input nput 16 I Os lt gt 16 I Os lt gt 103 004 16 I Os l Og l O45 cH 16 I Os I O4g l O34 32 TDI JTAG Tap TCK Controller TDO TMS Document 38 03007 Rev E Page 9 of 64 Feedback Ultra37000 CPLD Famil TDI CY37128 CY37128V CLOCK ick JTAG Tap INPUTS INPUTS Controller TMS 4 INPUT CLOCK MACROCELLS 16 I Os 16 I Os l Og l O45 lt gt l O442 1 O427 16 I Os 16 I Os I O16 l O34 l Ogg 1
32. 8 CY37512 512 5 160 192 264 10 118 Speed Bins Device 200 167 154 143 125 100 83 66 CY37032 x x x CY37064 x x x CY37128 x x x CY37192 x x x CY37256 x x x CY37384 x x CY37512 x x x Device Package Offering and Count 44 44 44 84 84 100 160 160 208 208 292 388 Device Lead Lead Lead Lead Lead Lead Lead Lead Lead Lead Lead Lead TQFP PLCC CLCC PLCC CLCC TQFP TQFP CQFP PQFP CQFP PBGA PBGA CY37032 37 37 CY37064 37 37 37 69 69 CY37128 69 69 69 133 CY37192 125 CY37256 133 133 165 197 CY37384 165 197 CY37512 165 165 197 269 3 3V Selection Guide General Information Device Macrocells Dedicated Inputs Pins Speed tpp Speed fmax CY37032V 32 5 32 8 5 143 CY37064V 64 5 32 64 8 5 143 CY37128V 128 5 64 80 128 10 125 CY37192V 192 5 120 12 100 CY37256V 256 5 128 160 192 12 100 CY37384V 384 5 160 192 15 83 CY37512V 512 5 160 192 264 15 83 Document 38 03007 Rev E Page 2 of 64 Feedback II Speed Bins 7 CYPRESS Ultra37000 CPLD Famil Device 200 167 154 125 83 66 CY37032V CY37064V CY37128V CY37192V gt CY37256V CY37384V CY37512V gt x x x x Device Package Offering and I O Count Device 44 Lead n LL Lead CLCC 48 lt Lead CLCC Lea FBG 100 Lead TQFP 100 Lead FBGA 160 Le
33. 966698 0 z 5 GND 41 NC 42 1046 I 43 44 45 Oso 7 48 Document 38 03007 Rev 160 Lead TQFP A160 for CY37192 V Top View O119 O418 O447 O416 10415 10414 10413 10412 GND 135 C 134 7 10440 O109 10108 107 10106 10105 124 EES 123 122 NC a 77 lOi 78 X 79 Veco 80 GND Vcco O104 O103 O102 TDI O401 O100 9 Oog GND Ogz 96 95 4 Oo2 1 CLK3 I4 GND Vcco CLKo l3 5 Oga O82 GND 1 Oz7 Oz5 NC GND Page 36 of 64 Feedback Ultra37000 CPLD Famil 208 Lead PQFP N208 CQFP U208 Top View enD C 1 156 4 Veco 2 110 0 gt 3 1 0138 22 DJ 4 1 043 O54 5 1 0136 O4 6 1 0135 TCK E 7 TDI 0 8 1 0134 1 0433 1 0132 1O25 0131 70130 GND GND 1 0129 O4 70 28 2 CJ 1 0127 O4 Ll 1 0126 1 0125 C 1 1035 1 0123 LL 1 0422 O4 70121 1 0120 CLKylo EJ L Voc Veco GND GND _ 1 Veco NC EJ 1 GND LJ Ll CLK3 13
34. D GND GND GND GND GND GND GND Og GND GND 12 VO4g GND GND GND GND l Ogg VOss VOs Oge VOss CLK 1O74 1O70 1 42 1 01432 VO492 VO494 l Oqza 0155 VOqzg VOqzz 1 17 1 0479 Voc Voc WOoo 1 072 TMS 12 1 0127 462 TDO 1 O168 Voc l Ogs VOgs 10 VO s 1O74 VO73 1 429 1 0434 1 01437 1 1 VOqzo 1 0471 1 0472 1 0473 l Ogo 1 079 1O77 VOzg 5 1 0417 10420 VO4g4 65 VOqga 1 O485 1040 1 0102 1 0421 1 01431 1 1046 1 4 1 0487 0 GND 1 0404 l O422 GND GND 1 0440 1 01457 VOr59 VOqgi GND O s GND GND GND 10 5 GND GND 0452 GND GND GND NC GND GND GND NC 07 GND GND 1 0442 Voc VO445 VO44
35. Document 38 03007 Rev E Page 62 of 64 Cypress Semiconductor Corporation 2005 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Feedback Addendum 3 3V Operating Range Ultra37000 CPLD Famil CY37064VP100 143AC CY37064VP100 143BBC CY37064VP44 143AC CY37064VP48 143BAC Range Ambient Temperature Junction Temperature Vcc Commercial 0 C to 70 C 0 C to 90 C 3 3V 0 16V Document 38 03007 Rev E Page 63 of 64 Feedback CYPRESS Document History Page Ultra37000 CPLD Famil Document Title Ultra37000 CPLD Family 5V 3
36. Flat Pack Industrial CY37256P160 125AXI A160 160 Lead Lead Free Thin Quad Flat Pack CY37256P208 125NI N208 208 Lead Plastic Quad Flat Pack CY37256P256 125BGI BG292 292 Plastic Ball Grid Array 5962 9952302QZC 0162 160 Lead Ceramic Quad Flat Pack Military 83 CY37256P160 83AC A160 160 Lead Thin Quad Flat Pack Commercial CY37256P160 83AXC A160 160 Lead Lead Free Thin Quad Flat Pack CY37256P208 83NC N208 208 Lead Plastic Quad Flat Pack CY37256P256 83BGC BG292 292 Plastic Ball Grid Array CY37256P160 83AI A160 160 Lead Thin Quad Flat Pack Industrial CY37256P160 83AXI A160 160 Lead Lead Free Thin Quad Flat Pack CY37256P208 83NI N208 208 Lead Plastic Quad Flat Pack CY37256P256 83BGI BG292 292 Plastic Ball Grid Array 5962 9952301QZC 0162 160 Lead Ceramic Quad Flat Pack Military 384 125 7384 208 125 208 208 Lead Plastic Quad Flat Commercial CY37384P256 125BGC BG292 292 Ball Plastic Ball Grid Array 83 7384 208 83 N208 208 Lead Plastic Quad Flat Pack Commercial CY37384P256 83BGC BG292 292 Ball Plastic Ball Grid Array CY37384P208 83NI N208 208 Lead Plastic Quad Flat Pack Industrial CY37384P256 83BGI BG292 292 Ball Plastic Ball Grid Array Document 38 03007 Rev E Page 45 of 64 Feedback Ultra37000 CPLD Famil CYPRESS 5 0V Ordering In
37. GND GND GND GND GND GND 1 0493 l O494 105 107 l Og l Ogg GND GND GND GND GND GND GND GND l O4zg 039 Ogg l Ogz NC NC 10177 1 0175 O91 Veco 1 0173 1 0172 O94 Veco 1 0170 Ogs 1 072 O73 1 0453 1 0190 1 0191 1 0168 Oz4 VOzg 1 0152 1 0187 1 0189 1077 VO l Ozg NC l O4g4 1 0185 186 l Ogo l O4og N C GND GND Veco Vcco GND GND NC Veco Veco NC NC 10 55 l Oqga 1 0182 1 0409 l Ogg l Ogz 10400 1 0402 1 0420 1 0426 12 l O433 1 0136 1 04391 1 0442 1 0457 1 0459 1 0461 10463 1 0466 1 0446 1 0154 GND 0 15 6 l Ogg 10404 1 01406 11 0424 10424 l O427 Vec 1 0434 1 0437 1 0440 1 0443 62 1 0444 1 O448 NC GND GND GND l Ogg TMS 1 0107 l O422 1 01425 10428 1 04314 1 0432 1 0435 1 0141 1 0456 TDO 1 0464 1 0467 10446 l O449 GND GND Document 38 03007 Rev E Page 40 of 64 Feedback J 400 Ball Fine Pitch BGA BB400 Ultra37000 CPLD Famil
38. IN MILLIMETERS 1047 027 0 50 BSC s 105 28 00 0 10 SQ 0 60 0 15 30 60 5 50 130 SEATING PLANE 4 t HHHRHHRHRHHHHRHHHHHHHHHHHRRRRRRRRRRRRHRHHRITTHRRRRRHR 34020 i III ab m 017 2040 N P4 51 85069 B Document 38 03007 Rev E Page 57 of 64 Feedback Ultra37000 CPLD Famil Package Diagrams continued 208 Lead Ceramic Quad Flatpack Cavity Up U208 DIMENSIONS IN MM INCH REFERENCE JEDEC N A PKG WEIGHT 6 7gms PIN 1 N j 0 50 0197 __ 0 20 008 TYP R0 13 005 MIN ri m 28 00 0 10 1 102 2 008 SQ 0 20 MIN 31 22 0 25 008 MIN 1 229 010 DETAILA SEE DETAIL A 3 43 135 0 15 0 02 006 001 3 94 3 94 155 X 0 050 0 70 500 020 SEATING PLANE Lt 0 51 0 20 020 2 008 51 80105 B Document 38 03007 Rev E Page 58 of 64 Feedback 1 Q lt m U D u u 9 r x lt 3 e 5 4 l 9 OococoO0oo0oo0oO ooo oo Oo O lt 00000000 00000000 1 O 2
39. MHz The typical pattern is a 16 bit up counter per logic block with outputs disabled 5 0V Room Temperature CY37384 500 450 High 400 350 300 Low Power 250 200 4 150 4 100 4 50 4 0 0 20 40 60 80 100 120 140 160 Frequency MHz The typical pattern is a 16 bit up counter per logic block with outputs disabled Voc 5 0 Ta Room Temperature Document 38 03007 Rev E Page 26 of 64 Feedback Ultra37000 CPLD Famil CY37512 600 High Speed 5004 4004 lt 300 Low Power 8 200 4 100 0 r 0 20 40 60 80 100 120 140 160 Frequency MHz The typical pattern is a 16 bit up counter per logic block with outputs disabled Vcc 5 0V TA Room Temperature Typical 3 3V Power Consumption CY37032V 30 High Speed 254 Low Power 204 lt 151 8 10 4 5 4 0 0 20 40 60 80 100 120 140 160 Frequency MHz The typical pattern is a 16 bit up counter per logic block with outputs disabled Voc 3 3V Ta Room Temperature Page 27 of 64 Document 38 03007 Rev E Feedback Ultra37000 CPLD Famil CY37064V 45 High Speed 40 4 354 Low Power 304 25 p 2 204 15 10 5 0 r r r r r r 0 20 40 60 80 100 120 140 Frequency MHz The typical pattern is a 16 bit up counter per logic block with outputs disabled Vcc 3 3V TA Room Temperature CY37128V 80 High Speed 70
40. O O G O G O O O Q O O O O O D G G H H asd J 4 K B L ODOooo0oO00o0000000000000 M oS e ad N g Hi R 4 U OOOOOOOOOOOOOOOOOOOO U V v Y 0 20 F 4X zs a 1 00 2100 010 1 00 12 00 0410 m VIEW BOTTOM VIEW N eH m N c 51 85111 A SEATING PLANE N 045 ax e gt H C SIDE VIEW Y ViewDraw and SpeedWave are trademarks of ViewLogic Windows is a registered trademark of Microsoft Corporation Warp is a registered trademark and In System Reprogrammable ISR Warp Professional Warp Enterprise and Ultra37000 are trade marks of Cypress Semiconductor Corporation All product and company names mentioned in this document are the trademarks of their respective holders
41. O444 16 I Os 16 I Os l Oa2 1 O47 l Ogo l Ogs 16 I Os 16 I Os 2 l Og4 l Ozg 64 64 Clock CY37192 CY37192V input Input 10 LOGIC 101 05 l Og I Og 16 BLOCK ot 0459 04 10 LOGIC 10 I Os l O49 l O49 16 BLOCK lt 36 10 OGC 10 I Os l O9 l O9 16 BLOCK gt lt gt oso Ooo l3 10 5 L 10 l Os 16 16 BLOCK gt lt gt 36 6 10 2 _ 36 10 I Os 1 0O40 l 049 16 16 BLOCK gt 36 b n LOGIC 10 I Os l Oso l Osg 16 BLOCK gt gt lt gt gt 10 0 T JTAG Tap On 60 60 TMS Controller Document 38 03007 Rev E Page 10 of 64 Feedback Logic Block Diagrams continued CY37256 CY37256V 1205 l Og I O4 lt 12 45 V Oo3 12 l O54 l Oss 12 l Os5 l O47 12 l O48 l Osg 12 12 I Os l Oz2 l Ogs Ultra37000 CPLD Famil 12 I Os L 79 12 I Os L gt 104 1046 12 I Os 1 444 1 155 12 I Os LOMA 104 043 12 I Os 12 l Og4 l Ogg lt TDI Controller TCK TMS Document 38 03007 Rev E 96 Page 11 of 64 Feedback a Ultra37000 CPLD Famil H CYPRESS Block Diagrams continued CY37384 CY37384V Input Input 12 108 12 I Os 1
42. SCOPE a SCOPE b Equivalent to TH VENIN EQUIVALENT 990 COM L 1360 MIL 2 08V COM L OUTPUT 929 2 13V MIL I OR 35 pF 3 3V AC Test Loads and Waveforms 2950 COM L 2950 3930 MIL 3930 MIL ALL INPUT PULSES 3 3V 3 3V 3 0V OUTPUT OUTPUT 3400 COM L 3400 COM L 35 pF 4530 MIL 5 pF 4530 MIL GND INCLUDING INCLUDING 2 ns JIG AND JIG AND SCOPE a SCOPE b Equivalent to TH VENIN EQUIVALENT 1580 COM L 2700 MIL 1 77V COM L OUTPUT di DN 1 77V MIL 1 508 35 pF Document 38 03007 Rev E Page 16 of 64 Feedback 4 Wns 55 Ultra37000 CPLD Famil Parameter Vx Output Waveform Measurement Level 0 5V Vx tER 2 6V s V L tea 1 5V ui tEAC Vihe Test Waveforms Switching Characteristics Over the Operating Range 12 Parameter Description Unit Combinatorial Mode Parameters ton 14 15 Input to Combinatorial Output ns 4 17 Output Through Transparent Input or OutputLatch gt fns 14 TS Input to Output Through Transparent Input and Output Latches ns 14 15 Input to Output Enable ns T inputto Output Disabe Input Register Parameters twL Clock or Latch Enable Input LOW Timel l ns tw Clock or Latch Enable Input HIGH Ti
43. Voltage gt 2001 Poe ADD s perMIL STD 383 Method 3018 Supply Voltage to Ground Potential 0 5V to 4 6V Latch up Curr ent l uu uuu uu uuu usss gt 200 Operating Range Range Ambient Temperature Junction Temperature T Commercial 0 C to 70 C 0 C to 90 C 3 3V 0 3V Industrial 40 C to 85 C 40 C to 105 C 3 3V 0 3V Military 55 C to 125 C 55 C to 130 C 3 3V 0 3V 3 3V Device Electrical Characteristics Over the Operating Range Parameter Description Test Conditions Min Max Unit Vou Output HIGH Voltage Vcc Min 4 mA 2 4 V 3 mA VoL Output LOW Voltage Min 8 0 5 V lo 6 mA Mil ViH Input HIGH Voltage Guaranteed Input Logical HIGH Voltage for 2 0 5 5 V all Inputs VIL Input LOW Voltage Guaranteed Input Logical LOW Voltage for 0 5 0 8 V all Inputs lix Input Load Current GND OR Bus Hold Disabled 10 10 loz Output Leakage Current Vo GND or Vcc Output Disabled 50 50 Bus Hold Disabled los Output Short Circuit Current 81 Vcc Max Vour 0 5V 30 160 mA Input Bus Hold LOW Sustaining Current Vcc Min 0 8V 75 IBHH Input Bus Hold HIGH Sustaining Current Vcc Min 2 0V 75 Input Bus Hold LOW Overdrive Current Vcc Max 500 IBHHO Input Bus Hold HIGH Overd
44. ad TQFP 160 Lead CQFP 208 Lead PQFP 208 Lead CQFP 292 Lead PBGA 256 Lead FBGA 388 Lead PBGA 400 Lead FBGA CY37032V 37 CY37064V CY37128V 37 37 69 133 CY37192V 125 CY37256V CY37384V 133 133 165 165 197 197 197 CY37512V 165 165 197 269 269 Architecture Overview of Ultra37000 Family Programmable Interconnect Matrix The PIM consists of a completely global routing matrix for signals from I O pins and feedbacks from the logic blocks The PIM provides extremely robust interconnection to avoid fitting and density limitations The inputs to the PIM consist of all and dedicated input pins and all macrocell feedbacks from within the logic blocks The number of PIM inputs increases with pin count and the number of logic blocks The outputs from the PIM are signals routed to the appropriate logic blocks Each logic block receives 36 inputs from the PIM and their complements allowing for 32 bit operations to be implemented in a single pass through the device The wide number of inputs to the logic block also improves the routing capacity of the Ultra37000 family An important feature of the PIM is its simple timing The propa gation delay through the PIM is accounted for in the timing specifications for each device There is no additional delay for traveling through the PIM In fact all
45. d circuit board The 37000 UltralSR programming cable is then connected between the parallel port of the PC and this connector A simple configu ration file instructs the ISR software of the programming operations to be performed on each of the Ultra37000 devices in the system The ISR software then automatically completes all of the necessary data manipulations required to accomplish the programming reading verifying and other ISR functions For more information on the Cypress ISR Interface see the ISR Programming Kit data sheet CY3700i The second method for programming Ultra37000 devices is on automatic test equipment ATE This is accomplished through a file created by the ISR software Check the Cypress website for the latest ISR software download information Page 7 of 64 Feedback CYPRESS third programming option for Ultra37000 devices is to utilize the embedded controller or processor that already exists in the system The Ultra37000 ISR software assists in this method by converting the device JEDEC maps into the ISR serial stream that contains the ISR instruction information and the addresses and data of locations to be programmed The embedded controller then simply directs this ISR stream to the chain of Ultra37000 devices to complete the desired reconfiguring or diagnostic operations Contact your local sales office for information on availability of this option Ny Document 38 0300
46. ds 125 125 MHz P400 400 Leads 200 200 MHz 100 100 MHz 167 167 MHz 83 83 MHz 154 154 MHz 66 66 MHz 143 143 MHz 5 0V Ordering Information Speed Package Operating Macrocells MHz Ordering Code Name Package Type Range 32 200 7032 44 200 44 44 Lead Thin Quad Flat Pack Commercial CY37032P44 200AXC 44 44 Lead Lead Free Thin Quad Flat CY37032P44 200JC J67 44 Lead Plastic Leaded Chip Carrier CY37032P44 200JXC J67 44 Lead Lead Free Plastic Leaded Chip Carrier 154 CY37032P44 154AC A44 44 Lead Thin Quad Flat Pack Commercial CY37032P44 154JC J67 44 Lead Plastic Leaded Chip Carrier 7032 44 154 44 44 Lead Thin Quad Flat Pack Industrial CY37032P44 154AXI A44 44 Lead Lead Free Thin Quad Flat Pack 7032 44 154 J67 44 Lead Plastic Leaded Chip Carrier CY37032P44 154JXI J67 44 Lead Lead Free Plastic Leaded Chip Carrier 125 CY37032P44 125AC A44 44 Lead Thin Quad Flat Pack Commercial CY37032P44 125AXC 44 44 Lead Lead Free Thin Quad Flat CY37032P44 125JC J67 44 Lead Plastic Leaded Chip Carrier CY37032P44 125JXC J67 44 Lead Lead Free Plastic Leaded Chip Carrier 7032 44 125 44 44 Lead Thin Quad Flat Industrial CY37032P44 125Jl J67 44 Lead Plastic Leaded Chip Carrier 64 200 7064 44 200 44 44 Lead Thin Quad Flat Pack Commercial 7064 44 200 44 44 Lead Lead Free Thin Quad Flat CY37064P44 200JC J67 44 Lead Plastic Leaded Chip Carrier CY370
47. dustrial CY37128VP100 83AXI A100 100 Lead Lead Free Thin Quad Flat Pack CY37128VP100 83BBI BB100 100 Ball Fine Pitch Ball Grid Array CY37128VP160 83Al A160 160 Lead Thin Quad Flat Pack CY37128VP160 83AXI A160 160 Lead Lead Free Thin Quad Flat Pack 5962 9952201QYA Y84 84 Lead Ceramic Leaded Chip Carrier Military 192 100 7192 160 100 A160 160 Lead Thin Quad Flat Commercial CY37192VP160 100AXC A160 160 Lead Lead Free Thin Quad Flat Pack 66 CY37192VP160 66AC A160 160 Lead Thin Quad Flat Pack Commercial CY37192VP160 66AXC A160 160 Lead Lead Free Thin Quad Flat Pack CY37192VP160 66AI A160 160 Lead Thin Quad Flat Pack Industrial Document 38 03007 Rev E Page 47 of 64 Feedback Ultra37000 CPLD Famil CYPRESS 3 3V Ordering Information continued Speed Package Operating Macrocells MHz Ordering Code Name Package Type Range 256 100 7256 160 100 A160 160 Lead Thin Quad Flat Commercial CY37256VP160 100AXC A160 160 Lead Lead Free Thin Quad Flat Pack CY37256VP208 100NC 08 208 1 Plastic Quad Flat Pack CY37256VP256 100BGC BG292 292 Ball Plastic Ball Grid Array CY37256VP256 100BBC BB256 256 Fine Pitch Ball Grid Array CY37256VP160 100AI A160 160 Lead Thin Quad Flat Industrial CY37256VP160 100AXI A160 160 Lead Lead Fre
48. e Document 38 03007 Rev E Page 30 of 64 Feedback 79 Mi CYPRESS in Configurations Document 38 03007 Rev E Ultra37000 CPLD Famil 44 pin TQFP A44 Top View 1 2 O26 3 1 025 CLK lo 4 1 024 JTAGEN 5 CLK l4 GND 6 GND CLKo l4 7 la l Og 8 CLK3 l l Og 9 1 023 1 010 10 1 022 044 11 1 024 1 OU LI Li Li LI Li LI Li LI Li S 98 2599986 a 6 44 pin PLCC J67 CLCC Y67 Top View lOg TCK 26 1 025 1 07 1 024 CLK lo CLK JTAGEN GND p IO 1 023 9 1 022 1 011 Page 31 of 64 Feedback Ultra37000 CPLD Famil 48 ball Fine Pitch BGA BA50 Top View 1 2 3 4 5 6 7 8 A 105 Voc VO VOg TCK TDI B Voc 1 04 02 VOo WOj WO VOs GND GND 10 10 D JTAGe GND GND 10 10 VOo 106 VO Vcc F uo V 14 15 17 18 58 Note 20 For 3 3V versions Ultra37000V Veco z 9 36 37 38 39 40 41 42 43 1 024 1 025 Note 84 lead PLCC 983 CLCC Y84 Top View Q 2 8 gt LIII Bs mx MS S915 7 86 50
49. e Thin Quad Flat Pack 66 CY37256VP160 66AC A160 160 Lead Thin Quad Flat Commercial CY37256VP160 66AXC A160 160 Lead Lead Free Thin Quad Flat Pack CY37256VP208 66NC 08 208 1 Plastic Quad Flat Pack CY37256VP256 66BGC BG292 292 Ball Plastic Ball Grid Array CY37256VP256 66BBC BB256 256 Fine Pitch Ball Grid Array CY37256VP160 66AI A160 160 Lead Thin Quad Flat Pack Industrial CY37256VP256 66BGI BG292 292 Ball Plastic Ball Grid Array CY37256VP256 66BBI BB256 256 Fine Pitch Ball Grid Array 5962 9952401QZC 0162 160 Lead Ceramic Quad Flat Pack Military 384 83 CY37384VP208 83NC N208 208 1 Plastic Quad Flat Pack Commercial CY37384VP256 83BGC BG292 292 Ball Plastic Ball Grid Array 66 CY37384VP208 66NC N208 208 Lead Plastic Quad Flat Pack Commercial CY37384VP256 66BGC BG292 292 Ball Plastic Ball Grid Array CY37384VP208 66NI N208 208 Lead Plastic Quad Flat Pack Industrial CY37384VP256 66BGI BG292 292 Ball Plastic Ball Grid Array 512 83 CY37512VP208 83NC N208 208 Lead Plastic Quad Flat Pack Commercial CY37512VP256 83BGC BG292 292 Ball Plastic Ball Grid Array CY37512VP352 83BGC BG388 388 Plastic Ball Grid Array CY37512VP400 83BBC BB400 400 Ball Fine Pitch Ball Grid Array 66 CY37512VP208 66NC 208 208 Lead Plastic Quad Flat Commercial CY37512VP256 66BGC BG292 292 Ball Plastic Ball Grid Array CY37512VP352 66BGC BG388 388 Ball Plastic Ball Grid Array CY37512VP400 66BBC BB400 400 Ball Fine Pitch Ba
50. f 80 productterms are available from the local product term array The product term allocator provides two important capabilities without affecting perfor mance product term steering and product term sharing Product Term Steering Product term steering is the process of assigning product terms to macrocells as needed For example if one macrocell requires ten product terms while another needs just three the product term allocator will steer ten product terms to one macrocell and three to the other On Ultra37000 devices product terms are steered on an individual basis Any number between 0 and 16 product terms can be steered to any macrocell Note that 0 product terms is useful in cases where a particular macrocell is unused or used as an input register Product Term Sharing Product term sharing is the process of using the same product term among multiple macrocells For example if more than one output has one or more product terms in its equation that are common to other outputs those product terms are only programmed once The Ultra37000 product term allocator allows sharing across groups of four output macrocells in a Document 38 03007 Rev E variable fashion The software automatically takes advantage of this capability the user does not have to intervene Note that neither product term sharing nor product term steering have any effect on the speed of the product All worst case steering and sharing configurations
51. formation continued Speed Package Operating Macrocells MHz Ordering Code Name Package Type Range 512 125 7512 208 125 N208 208 Lead Plastic Quad Flat Pack Commercial CY37512P256 125BGC BG292 292 Plastic Ball Grid Array CY37512P352 125BGC BG388 388 Plastic Ball Grid Array 100 7512 208 100 N208 208 Lead Plastic Quad Flat Pack Commercial CY37512P256 100BGC BG292 292 Plastic Ball Grid Array CY37512P352 100BGC BG388 388 Plastic Ball Grid Array CY37512P208 100NI N208 208 Lead Plastic Quad Flat Pack Industrial CY37512P256 100BGI BG292 292 Plastic Ball Grid Array CY37512P352 100BGI BG388 388 Plastic Ball Grid Array 5962 9952502QZC 0208 208 Lead Ceramic Quad Flat Pack Military 83 CY37512P208 83NC N208 208 Lead Plastic Quad Flat Pack Commercial CY37512P256 83BGC BG292 292 Plastic Ball Grid Array CY37512P352 83BGC BG388 388 Plastic Ball Grid Array CY37512P208 83NI 08 208 Lead Plastic Quad Flat Pack Industrial CY37512P256 83BGI BG292 292 Plastic Ball Grid Array CY37512P352 83BGI BG388 388 Plastic Ball Grid Array 5962 9952501QZC 0208 208 Lead Ceramic Quad Flat Pack Military 3 3V Ordering Information Speed Package Operating Macrocells MHz Ordering Code Name Package Type Range 32 143 CY37032VP44 143AC A44 44 Lead Thin Quad Flat Commercial CY37032VP44 143AXC A44 44 1 Lead Free Thin Quad Flat Pack CY37032VP48 143BAC 50 48
52. ll Grid Array CY37064VP100 100AC A100 100 Lead Thin Quad Flatpack CY37064VP100 100AXC A100 100 Lead Lead Free Thin Quad Flatpack CY37064VP100 100BBC BB100 100 Ball Fine Pitch Ball Grid Array CY37064VP44 100AI A44 44 Lead Thin Quad Flatpack Industrial CY37064VP44 100AXI A44 44 1 Lead Free Thin Quad Flatpack CY37064VP48 100BAI 50 48 Ball Fine Pitch Ball Grid Array CY37064VP100 100BBI BB100 100 Ball Fine Pitch Ball Grid Array CY37064VP100 100AI A100 100 Lead Thin Quad Flatpack CY37064VP100 100AXI A100 100 Lead Lead Free Thin Quad Flatpack 5962 9952001QYA Y67 44 Lead Ceramic Leaded Chip Carrier Military 128 125 CY37128VP100 125AC A100 100 Lead Thin Quad Flat Pack Commercial CY37128VP100 125AXC A100 100 Lead Lead Free Thin Quad Flat Pack CY37128VP100 125BBC BB100 100 Ball Fine Pitch Ball Grid Array CY37128VP160 125AC A160 160 Lead Thin Quad Flat Pack CY37128VP160 125AXC A160 160 Lead Lead Free Thin Quad Flat Pack CY37128VP160 125AI A160 160 Lead Thin Quad Flat Industrial CY37128VP160 125AXI A160 160 Lead Lead Free Thin Quad Flat Pack 83 CY37128VP100 83AC A100 100 Lead Thin Quad Flat Commercial CY37128VP100 83AXC A100 100 Lead Lead Free Thin Quad Flat Pack CY37128VP100 83BBC BB100 100 Fine Pitch Ball Grid Array CY37128VP160 83AC A160 160 Lead Thin Quad Flat CY37128VP160 83AXC A160 160 Lead Lead Free Thin Quad Flat Pack CY37128VP100 83Al A100 100 Lead Thin Quad Flat Pack In
53. ll Grid Array CY37512VP208 66NI N208 208 1 Plastic Quad Flat Pack Industrial CY37512VP256 66BGI BG292 292 Ball Plastic Ball Grid Array CY37512VP352 66BGI BG388 388 Plastic Ball Grid Array CY37512VP400 66BBI BB400 400 Fine Pitch Ball Grid Array 5962 9952601QZC 0208 208 1 Ceramic Quad Flat Pack Military Document 38 03007 Rev E Page 48 of 64 Feedback Ultra37000 CPLD Famil Package Diagrams 44 Lead Lead Pb Free Thin Plastic Quad Flat Pack A44 DIMENSIONS ARE IN MILLIMETERS 12 00 0 25 SQ 10 00 0 10 SQ 55 0 37 0 05 STAND OFF 0 05 MIN 0 15 MAX 0 08 MIN 0 20 S C 0 20 MIN al 0 60 0 15 1 00 51 85064 B DETAL 12 8X 1 40 0 05 DETAIL DIMENSIONS IN INCHES MIN MAX 0 20 MAX 44 Lead Lead Pb Free Plastic Leaded Chip Carrier J67 SEATING PLANE 0590 0 630 51 85003 A Page 49 of 64 Document 38 03007 Rev E Feedback Ultra37000 CPLD Famil N MZ 11111111 LILILILILILILILILILILI CETT TUTUP EU WWW S UU 51 80014 Document 38 03007 Rev E Page 50 of 64 Feedback Ultra37000 CPLD Famil 48 Ball 7 0 mm x 7 0 mm x 1 2 mm 0 80 pitch Thin BGA BA48D 51 85109 C 84 Lead Lead Pb Free Pla
54. ly and can support 5V or 3 3V I O levels Veco connections provide the capability of interfacing to either a 5V or 3 3V bus By connecting the Vcco pins to 5V the user insures 5V TTL levels on the outputs If Vcco is connected to 3 3V the output levels meet 3 3V standard CMOS levels and are 5V tolerant These devices require 5V ISR programming Ultra37000V 3 3V Devices Devices operating with a 3 3V supply require 3 3V on all Vcco pins reducing the device s power consumption These devices support 3 3V JEDEC standard CMOS output levels and are 5V tolerant These devices allow 3 3V ISR programming 1 Due to the 5V tolerant nature of 3 3V device I Os the I Os are not clamped to Vcc PCI 2V Cypress Semiconductor Corporation Document 38 03007 Rev E 3901 North First Street San Jose CA 95134 408 943 2600 Revised March 7 2004 Feedback IA 2 CYPRESS Selection Guide 5 0V Selection Guide General Information Ultra37000 CPLD Famil Device Macrocells Dedicated Inputs Pins Speed tpp Speed fmax CY37032 32 5 32 6 200 CY37064 64 5 32 64 6 200 CY37128 128 5 64 128 6 5 167 CY37192 192 5 120 7 5 154 CY37256 256 5 128 160 192 7 5 154 CY37384 384 5 160 192 10 11
55. m the associated with the neighboring macrocell The output of all buried macrocells is sent directly to the PIM regardless of its configuration Macrocell Figure 2 illustrates the architecture of the macrocell The macrocell supports the same functions as the buried macrocell with the addition of I O capability At the output of the macrocell a polarity control mux is available to select active LOW or active HIGH signals This has the added advantage of allowing significant logic reduction to occur in many appli cations The Ultra37000 macrocell features a feedback path to the PIM separate from the pin input path This means that if the macrocell is buried fed back internally only the associated pin can still be used as an input Ultra37000 CPLD Famil Bus Hold Capabilities on all I Os Bus hold which is an improved version of the popular internal pull up resistor is a weak latch connected to the pin that does not degrade the device s performance As a latch bus hold maintains the last state of a pin when the pin is placed in a high impedance state thus reducing system noise in bus interface applications Bus hold additionally allows unused device pins to remain unconnected on the board which is particularly useful during prototyping as designers can route new signals to the device without cutting trace connec tions to Vcc or GND For more information see the application note Unders
56. me ns tis Input Register or Latch Set up Time ns tiu Input Register or Latch Hold Time ns 14 Input Register Latch Enable to Combinatorial Output ns tico gt 14 5 Input Register Clock or Latch Enable to Output Through Transparent Output Latch ns Synchronous Clocking Parameters 15113 Set Up Time from Input Sync CLKo CLK4 Latch Enable ns Register Latch Data Hold Time ns tco2 gt 14 15 Output Synchronous Clock CLKo CLK4 CLK3 or Latch Enable to Combinatorial Output ns Delay Through Logic Array tses Output Synchronous Clock CLK4 or Latch Enable to Output Synchronous ns Clock CLKo CLK4 CLK3 or CLK3 or Latch Enable Through Logic Array tg Set Up Time from Input Through Transparent Latch to Output Register Synchronous Clock CLKg ns CLK4 CLK3 or Latch Enable tu Hold Time for Input Through Transparent Latch from Output Register Synchronous Clock ns CLK4 CLK3 or Latch Enable Notes 11 tgg measured with 5 pF AC Test Load and te measured with 35 pF AC Test Load 12 All AC parameters are measured with two outputs switching and 35 pF AC Test Load 13 Logic Blocks operating in Low Power Mode add ti p to this spec 14 Outputs using Slow Output Slew Rate add tg gw to this spec 15 When 3 3V add to this spec Documen
57. ode For combinatorial paths any inputto any output incurs a 6 5 ns worst case delay regardless of the amount of logic used For synchronous systems the input set up time to the output macrocells for any input is 3 5 ns and the clock to output time is also 4 0 ns These measure ments are for any output and synchronous clock regardless of the logic used The Ultra37000 features No fanout delays No expander delays No dedicated vs I O pin delays No additional delay through PIM No penalty for using 0 16 product terms No added delay for steering product terms No added delay for sharing product terms Norouting delays No output bypass delays The simple timing model of the Ultra37000 family eliminates unexpected performance penalties Page 6 of 64 Feedback COMBINATORIAL SIGNAL 6 5 ns OUTPUT INPUT REGISTERED SIGNAL ts 3 5 ns tco 4 5 ns INPUT OUTPUT CLOCK Figure 5 Timing Model for CY37128 JTAG and PCI Standards PCI Compliance 5V operation of the Ultra37000 is fully compliant with the PCI Local Bus Specification published by the PCI Special Interest Group The 3 3V products meet all PCI requirements except for the output 3 3V clamp which is in direct conflict with 5V tolerance The Ultra37000 family s simple and predictable timing model ensures compliance with the PCI AC specifica tions independent of the design IEEE 1149 1 compliant JTAG The Ultra37000 family ha
58. paralleled system performance The Ultra37000 family is designed to bring the flexibility ease of use and performance of the 22V10 to high density CPLDs The architecture is based on a number of logic blocks that are connected by a Programmable Inter connect Matrix PIM Each logic block features its own product term array product term allocator and 16 macrocells The PIM distributes signals from the logic block outputs and all input pins to the logic block inputs All of the Ultra37000 devices are electrically erasable and In System Reprogrammable ISR which simplifies both design and manufacturing flows thereby reducing costs The ISR feature provides the ability to reconfigure the devices without having design changes cause pinout or timing changes The Cypress ISR function is implemented through a JTAG compliant serial interface Data is shifted in and out through the TDI and TDO pins respectively Because of the superior routability and simple timing model of the Ultra37000 devices ISR allows users to change existing logic designs while simultaneously fixing pinout assignments maintaining system performance The entire family features JTAG for ISR and boundary scan and is compatible with the PCI Local Bus specification meeting the electrical and timing requirements The Ultra37000 family features user programmable bus hold capabilities on all I Os Ultra37000 5 0V Devices The Ultra37000 devices operate with a 5V supp
59. rier CY37128P100 125AC A100 100 Lead Thin Quad Flat Pack CY37128P100 125AXC A100 100 Lead Lead Free Thin Quad Flat Pack CY37128P160 125AC A160 160 Lead Thin Quad Flat Pack CY37128P160 125AXC A160 160 Lead Lead Free Thin Quad Flat Pack 7128 84 125 J83 84 Lead Plastic Leaded Chip Carrier Industrial CY37128P84 125JXI J83 84 Lead Lead Free Plastic Leaded Chip Carrier CY37128P100 125Al A100 100 Lead Thin Quad Flat Pack CY37128P100 125AXI A100 100 Lead Lead Free Thin Quad Flat Pack CY37128P160 125Al A160 160 Lead Thin Quad Flat Pack CY37128P160 125AXI A160 160 Lead Lead Free Thin Quad Flat Pack 5962 9952102QYA Y84 84 Lead Ceramic Leaded Chip Carrier Military 100 CY37128P84 100JC J83 84 Lead Plastic Leaded Chip Carrier Commercial CY37128P84 100JXC J83 84 Lead Lead Free Plastic Leaded Chip Carrier CY37128P100 100AC A100 100 Lead Thin Quad Flat Pack CY37128P100 100AXC A100 100 Lead Lead Free Thin Quad Flat Pack CY37128P160 100AC A160 160 Lead Thin Quad Flat Pack CY37128P160 100AXC A160 160 Lead Lead Free Thin Quad Flat Pack 7128 84 100 J83 84 Lead Plastic Leaded Chip Carrier Industrial CY37128P100 100AI A100 100 Lead Thin Quad Flat Pack CY37128P100 100AXI A100 100 Lead Lead Free Thin Quad Flat Pack CY37128P160 100AI A160 160 Lead Thin Quad Flat Pack 5962 9952101QYA Y84 84 Lead Ceramic Leaded Chip Carrier Military 192 154 7192 160 154 A160 160 Lead Thin Quad Flat Pack Commercial CY37192P160 154AXC A160
60. rive Current Vcc Max 500 9 Dual pins are with JTAG pins 10 For CY37064VP100 143AC CY37064VP100 143BBC CY37064VP44 143AC CY37064VP48 143BAC Operating Range Vcc is 3 3V 0 16V Document 38 03007 Rev E Page 15 of 64 Feedback Ultra37000 CPLD Famil 7 CYPRESS Inductance 44 44 44 84 84 100 160 208 Lead Lead Lead Lead Lead Lead Lead Lead Parameter Description Test Conditions PLCC PLCC CLCC TQFP TQFP PQFP Unit L Maximum Pin 3 3V 2 5 2 8 5 8 9 11 nH Inductance atf 1 MHz Capacitance Parameter Description Test Conditions Max Unit Input Output Vin 3 3V at f 1 MHz at TA 25 8 pF Signal Vin 3 3V at 1 MHz at Ta 25 12 pF Cpp Dual Functional Pins Vin 3 3V atf 1 MHz at TA 25 C 16 pF Endurance Characteristics Parameter Description Test Conditions Min Typ Unit N Minimum Reprogramming Cycles Normal Programming Conditions 1 000 10 000 Cycles AC Characteristics ALL INPUT PULSES 5 0V AC Test Loads and Waveforms 238Q COM L 2380 3190 MIL 3190 MIL 5V 5V 3 0V OUTPUT OUTPUT 170Q COM L 1700 35 2360 MIL 5 ET 2360 MIL GND INCLUDING INCLUDING 52 ns gt JIG AND JIG AND
61. rms in the logic block are output enable OE product terms Each of the OE product terms controls up to eight of the 16 macrocells and is selectable on an individual macrocell basis In other words each cell can select between one of two OE product terms to control the output buffer The first two of these four OE product terms are available to the upper half of the macrocells in a logic block The other two OE product terms are available to the lower half of the macrocells a logic block The next two product terms in each logic block are dedicated asynchronous set and asynchronous reset product terms The final product term is the product term clock The set reset OE and product term clock have polarity control to realize OR functions in a single pass through the array Page 3 of 64 Feedback 72 87 PRODUCT TERM ARRAY TERM PRODUCT ALLOCATOR Ultra37000 CPLD Famil PRODUCT TERMS 0 16 PRODUCT TERMS PRODUCT TERMS 0 16 PRODUCT TERMS Figure 1 Logic Block with 50 Buried Macrocells Low Power Option Each logic block can operate in high speed mode for critical path performance or in low power mode for power conser vation The logic block mode is set by the user on a logic block by logic block basis Product Term Allocator Through the product term allocator software automatically distributes product terms among the 16 macrocells in the logic block as needed A total o
62. s an IEEE 1149 1 JTAG interface for both Boundary Scan and ISR Boundary Scan The Ultra37000 family supports Bypass Sample Preload Extest Idcode and Usercode boundary scan instructions The JTAG interface is shown in Figure 6 TDI Data Registers Figure 6 JTAG Interface In System Reprogramming ISR In System Reprogramming is the combination of the capability to program or reprogram a device on board and the ability to support design changes without changing the system timing or device pinout This combination means design changes during debug or field upgrades do not cause board respins The Ultra37000 family implements ISR by providing a JTAG compliant interface for on board programming robust routing Document 38 03007 Rev E Ultra37000 CPLD Famil resources for pinout flexibility and a simple timing model for consistent system performance Development Software Support Warp Warp is a state of the art compiler and complete CPLD design tool For design entry Warp provides an IEEE STD 1076 1164 VHDL text editor an IEEE STD 1364 Verilog text editor and a graphical finite state machine editor It provides optimized synthesis and fitting by replacing basic circuits with ones pre optimized for the target device by implementing logic in unused memory and by perfect communication between fitting and synthesis To facilitate design and debugging Warp provides graphical timing simulation and analysis
63. ss WOs4a WOss WOg1 1 1 0401 1 5 1 0137 1 0139 n L VOsg l Ogg TMS Vcc Oss l Og l Og 2 TDO 1 04 l Oqg4 M WOg2 l Ogs l Ogg MO4o3 1 04112 1 0417 1 0129 1 04314 N 106 10 VO73 Ogg Og Og 104 VOS 104 10428 P 10 Og NC 1079 Ogg 10 1040 VOug 10425 R GND 106 1 Ogo Oss GND GND 1045 GND GND GND Voc GND GND VO o One GND GND Document 38 03007 Rev Page 39 of 64 Feedback gt AD AE AF Ultra37000 CPLD Famil 388 Lead PBGA BG388 Top View 1 2 3 4 5 6 7 8 9 10 11 12
64. stic Leaded Chip Carrier J83 DIMENSIONS IN INCHES MIN SEATING PLANE 1150 1158 0026 0 032 0020 MIN um e 0165 0 200 51 85006 A Page 51 of 64 Document 38 03007 Rev E Feedback Ultra37000 CPLD Famil 84 Lead Ceramic Leaded Chip Carrier Y84 Y DIMENSIONS IN INCH SEE VIEW A PIN 1 N lt lt 85 95 42 58 __ 2090 1142 1158 Tor 420 p nena pnd LTLTLTILTLILTLTLILILTIHLTILILTLTLILILILILILI 1185 SEATING PLANE 1195 006 010 035 X 45 035 045 F y 017 023 032 008 040 X 45 51 80095 A Document 38 03007 Rev E Page 52 of 64 Feedback Document 38 03007 Rev Ultra37000 CPLD Famil 51 85048 B Page 53 of 64 Feedback CYPRESS Package Diagrams continued 4 Ultra37000 CPLD Famil 100 Ball Thin Ball Grid Array 11 x 11 x 1 4 mm BB100 TOP MEW e sur 180 25 PIN 1 CORNER 0 454 0 05 10DX
65. t 38 03007 Rev E Page 17 of 64 Feedback p gt CYPRESS Switching Characteristics Over the Operating Range continued 12 Ultra37000 CPLD Famil Parameter Description Unit Product Term Clocking Parameters A Product Term Clock or Latch Enable PTCLK to Output ns tspT Set Up Time from Input to Product Term Clock or Latch Enable PTCLK ns tup Register or Latch Data Hold Time ns tiger Set Up Time for Buried Register used as an Input Register from Input to Product Term Clock or ns Latch Enable PTCLK Buried Register Used Input Register or Latch Data Hold Time ns 14 To Product Term Clock or Latch Enable PTCLK to Output Delay Through Logic Array ns Pipelined Mode Parameters tics Input Register Synchronous Clock CLKo CLK4 CLK3 to Output Register Synchronous ns Clock CLKo CLK4 or Operating Frequency Parameters fMAX1 Maximum Frequency with Internal Feedback Lesser of 1 tscs 1 ts ty or 1 tco MHz fMAX2 Maximum Data Path in Output Registered Latched Mode Lesser of 1 tuy twp MHz 1 ts ty Maximum Frequency with External Feedback Lesser of 1 ts 1 ty 2 Maximum Frequency Pipelined Mode Lesser of 1 tco tis I
66. t 81 Max Vour 0 5V 30 160 mA IBHL Input Bus Hold LOW Vcc Min 0 8V 75 Sustaining Current IBHH Input Bus Hold HIGH Min 2 0V 75 Sustaining Current IBHLO Input Bus Hold LOW Vcc Max 500 pA Overdrive Current IBHHO Input Bus Hold HIGH Vcc Max 500 uA Overdrive Current Notes 2 Normal Programming Conditions apply across Ambient Temperature Range for specified programming methods For more information on programming the Ultra37000 Family devices please refer to the Application Note titled An Introduction to In System Reprogramming with the Ultra37000 TA is the Instant On case temperature 2 2 mA lot 2 mA for ON problems caused by tester ground degradation Document 38 03007 Rev E Tested initially and after any design or process changes that may affect these parameters When the I O is output disabled the bus hold circuit can weakly pull the I O to above 3 6V if no leakage current is allowed Note that all I Os are output disabled during ISR programming Refer to the application note Understanding Bus Hold for additional information These are absolute values with respect to device ground All overshoots due to system or tester noise are included Not more than one output should be tested at a time Duration of the short circuit should not exceed 1 second Vour 0 5V has been chosen to avoid test Page 14 of 64
67. tanding Bus Hold A Feature of Cypress CPLDs Programmable Slew Rate Control Each output has a programmable configuration bit which sets the output slew rate to fast or slow For designs concerned with meeting FCC emissions standards the slow edge provides for lower system noise For designs requiring very high perfor mance the fast edge rate provides maximum system perfor mance MACROCELL FROM PTM 0 16 PRODUCT TERMS CELL lt ae BURIED MACROCELL FROM PTM 0 16 PRODUCT 5 L FEEDBACK TO PIM FEEDBACK TO PIM FEEDBACK TO PIM ASYNCHRONOUS BLOCKRESE 4 SYNCHRONOUS CLOCKS CLK0 CLK1 CLK2 CLK3 Be ON ER 1 ASYNCHRONOUS CLOCK PTCLK OE1 Figure 2 and Buried Macrocells Document 38 03007 Rev E Page 5 of 64 Feedback POLARITY MUXES INPUT CLOCK POLARITY INPUT 5 Ultra37000 CPLD Famil 12 TO CLOCK MUX ON ALL INPUT MACROCELLS SS SS 1 To cLock EACH LOGIC BLOCK 14 15 ORC46 j TORIM CLOCK POLARITY MUX ONE PER LOGIC BLOCK FOR EACH CLOCK INPUT Figure 4 Input Clock Macrocell Clocking Each and buried macrocell has access to four synchronous clocks CLK0 CLK1 CLK2 as well as an asynchronous product term clock PTCLK
68. tco 6 5 ns tg 9 5 ns and fuax2 105 MHz Document 38 03007 Rev E Page 19 of 64 E d CYPRESS Switching Characteristics Over the Operating Range continued 2 Ultra37000 CPLD Famil 200 MHz 167 MHz 154 MHz 143 MHz 125 MHz 100 2 83 2 66 2 Parameter Unit foli 14 115 12 13 13 14 15 18 21 26 ns tpw 8 8 8 8 10 12 15 20 ns T 10 10 10 10 12 14 17 22 ns 14 151 12 13 13 14 15 18 21 26 ns User Option Parameters tip 2 5 2 5 2 5 2 5 2 5 2 5 2 5 2 5 ns tsLEW 3 3 3 3 3 3 3 3 ns 0 3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 ns JTAG Timing Parameters 0 0 0 0 0 0 0 0 ns ty 20 20 20 20 20 20 20 20 ns les 20 20 20 20 20 20 20 20 ns 20 20 20 20 20 20 20 20 2 Switching Waveforms Combinatorial Output INPUT tpp COMBINATORIAL OUTPUT Registered Output with Synchronous Clocking INPUT SYNCHRONOUS CLOCK tco REGISTERED OUTPUT tco2 u REGISTERED OUTPUT SYNCHRONOUS CLOCK Note 19 Only applicable to the 5V devices Document 38 03007 Rev E Page 20 of 64 Feedback Ultra37000 CPLD Famil CYPRESS Switching Waveforms continued Registered Output with Product Term Clocking Input Going Through
69. tic Leaded Chip Carrier CY37064P84 125JC J83 84 Lead Plastic Leaded Chip Carrier CY37064P100 125AC A100 100 Lead Thin Quad Flat Pack CY37064P100 125AXC A100 100 Lead Lead Free Thin Quad Flat Pack CY37064P44 125Al A44 44 Lead Thin Quad Flat Pack Industrial CY37064P44 125AXI A44 44 Lead Lead Free Thin Quad Flat Pack 7064 44 125 J67 44 Lead Plastic Leaded Chip Carrier CY37064P84 125Jl J83 84 Lead Plastic Leaded Chip Carrier CY37064P100 125Al A100 100 Lead Thin Quad Flat Pack CY37064P100 125AXI A100 100 Lead Lead Free Thin Quad Flat Pack 5962 9951901QYA Y67 44 Lead Ceramic Leadless Chip Carrier Military Document 38 03007 Rev E Page 43 of 64 Feedback Ultra37000 CPLD Famil 5 0V Ordering Information continued Speed Package Operating Macrocells MHz Ordering Code Name Package Type Range 128 167 CY37128P84 167JC J83 84 Lead Plastic Leaded Chip Carrier Commercial CY37128P84 167JXC J83 84 Lead Lead Free Plastic Leaded Chip Carrier 7128 100 167 A100 100 Lead Thin Quad Flat Pack CY37128P100 167AXC A100 100 Lead Lead Free Thin Quad Flat Pack CY37128P160 167AC A160 160 Lead Thin Quad Flat Pack CY37128P160 167AXC A160 160 Lead Lead Free Thin Quad Flat Pack 125 CY37128P84 125JC J83 84 Lead Plastic Leaded Chip Carrier Commercial CY37128P84 125JXC J83 84 Lead Lead Free Plastic Leaded Chip Car
70. tis 2 2 2 2 2 2 5 3 4 ns 2 2 2 2 2 2 5 3 4 ns 11 11 11 12 5 12 5 19 ns Itico TTT 42 12 1121 14 116 13488 21 26 Synchronous Clocking Parameters 4 4 45 6 6 5176 81781 ns 3 4 4 5 5 ss e famil Tns 0 0 0 0 0 0 0 ns 9 5 10 11 12 14 19 ns 51 1651 8484 50 12 45 tg 191 7 5 7 5 8 5 9 12 15 15 ns iur 0 0 0 0 0 0 0 ns Product Term Clocking Parameters teop 14 191 7 10 10 13 13 15 ns tsPT 2 5 2 5 2 5 3 5 5 5 6 7 ns tupr 2 5 2 5 2 5 3 5 5 5 6 7 ns tiger I 0 0 0 0 0 0 0 0 ns tiupr 6 6 5 6 5 7 5 9 11 14 19 ns gom 12 14 psi pef 019 faf 141 130 Pipelined Mode Parameters teal 5 6 6 7 10 12 15 ns Operating Frequency Parameters fMAX1 200 167 154 143 100 83 66 MHz Tr 200 200 200 167 153177 125178 100 MHz 125 125 105 91 801771 62 5 50 MHz Tm 167 167 154 125 100 83 66 MHz Reset Preset Parameters trw 8 8 8 8 12 15 20 ns tari 10 10 10 10 14 17 22 ns Notes 16 The following values correspond to the CY37512 and CY37384 devices tco 5 ns ts 6 5 ns 8 5 ns 8 5 ns fmax1 118 MHz 17 The following values correspond to the CY37192V and CY37256V devices tco 6 ns ts 7 ns fmax2 143 MHZ 77 MHz and 100 MHz and for the CY37512 devices ts 7 ns 18 The following values correspond to the CY37512V CY37384V devices
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