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Cypress enCoRe CY7C604XX User's Manual

1. PORLEWV 1 0 00b HPOR 0 1 61 1 66 1 71 V 1 PORLEWV 1 0 00b HPOR 1 2 36 2 41 V 2 PORLEWV 1 0 01b HPOR 1 2 60 2 66 V VPPOR3 PORLEWV 1 0 10b HPOR 1 2 82 2 95 V Vdd Value for LVD Trip VM 2 0 000b 10 2 40 2 45 2 51 V VIvD1 VM 2 0 001517 2 64 2 71 2 78 V Vivp2 VM 2 0 010612 2 85 2 92 2 99 V VI vp3 VM 2 0 011b 2 95 3 02 3 09 V VM 2 0 100b 3 06 3 13 3 20 Vivps VM 2 0 101b 1 84 1 9 2 32 VM 2 0 110b 9 1 75 1 8 1 84 DC Programming Specifications Table 14 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges Table 14 DC Programming Specifications Symbol Description Min Typ Max Units Vddiwrite Supply Voltage for Flash Write Operations 1 71 V Ippp Supply Current During Programming or Verify 5 25 Input Low Voltage During Programming or Verify Vit V ViHP Input High Voltage During Programming or Verify Vin _ _ V li p Input Current when Applying Vilp to P1 0 or P1 1 During 0 2 mA Programming or Verify 4 lip Input Current when Applying Ms to P1 0 or P1 1 1 5 mA During Programming or Verify Output Low Voltage During Programming or Verify B Vss 4 0 75 V Output High Voltage During Programming or Verify mu Vdd V Flasheypp Flash Write Endurance 9 50 000 Cycles Flashpr Flash Data Retention 10 20 Years Notes 9 Vdd must be greater than or equal to 1 71V
2. z 2 CYPRESS PERFORM CY7C604XX Figure 6 GPIO Timing Diagram 90 GPIO Pin Output Voltage 10 TRise23 TRise01 AC External Clock Specifications Table 17 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges Table 17 AC External Clock Specifications kq D cd A A ee Symbol Description Min Typ Max Units FoscExT Frequency 0 750 25 2 2 High Period 20 6 5300 ns Low Period 20 6 5 Power Up IMO to Switch 150 us AC Programming Specifications Table 18 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges Table 18 AC Programming Specifications Symbol Description Min Typ Max Units Trsc_k Rise Time of SCLK 1 20 ns TrEsciK Fall Time of SCLK 1 20 ns Tsscik Data Set up Time to Falling Edge of SCLK 40 ns Data Hold Time from Falling Edge of SCLK 40 ns Frequency of SCLK 0 E 8 MHz TERASEB Flash Erase Time Block _ _ 18 ms TwRITE Flash Block Write Time _ 25 ms Data Out Delay from Falling Edge of SCLK 85 ns 3 0V Vdd 3 6V Data Out Delay from Falling Edge of SCLK 130 ns 1 71V Vdd 3 0V Document Number 001 12395 Rev H Page 22 of 30 Feedback CY7C604XX Figure 7 Timing Diagram AC Programming Cycl
3. Document Title CY7C604XX enCoRe V Low Voltage Microcontroller Document Number 001 12395 H 2653717 DVJA PYRS 02 04 09 Changed master page from CY7C60445 CY7C6045X to CY7C604XX Updated Features Functional Overview Development Tools and Designing with PSoC Designer sections Removed GUI graphical user interface from Document Conventions acronym table Added Figure 1 and Table 1 16 pin part information to Pin Configurations section Removed O Only a read write register or bits in Table 4 Edited Table 8 removed 10 bit resolution information and corrected units column Added Figure 9 16 pin part information to Package Dimensions section Added Package Handling section Added 8K part CY7C60413 16LKXC to Ordering Information Sales Solutions and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices solution centers manufacturer s representatives and distributors To find the office closest to you visit us at cypress com sales Products PSoC Solutions PSoC psoc cypress com General psoc cypress com solutions Clocks amp Buffers clocks cypress com Low Power Low Voltage psoc cypress com low power Wireless wireless cypress com Precision Analog psoc cypress com precision analog Memories memory cypress com LCD Drive Image Sensors image cypress com 2 05 psoc cypress com can USB
4. M gt CYPRESS CY7C604XX PERFORM enCoRe V Low Voltage Microcontroller Features m Powerful Harvard Architecture Processor m Programmable Pin Configurations a M8C processor speeds running up to 24 MHz a 25 mA sink current on all GPIO Low power at high processing speeds a Pull Up High Z Open Drain CMOS drive modes on all GPIO Interrupt controller Configurable inputs on all GPIO 1 71V to 3 6V operating voltage Low dropout voltage regulator for Port 1 pins Programmable Temperature range 0 to 70 to output 3 0 2 5 or 1 8V at the pins Flexible On Chip Memory Selectable regulated digital I O on Port 1 Configurable input threshold for Port 1 3 0V 20 mA total Port 1 source current Hot swappable a 5 mA strong drive mode on Ports 0 and 1 Up to 32K Flash program storage 50 000 Erase and write cycles Flexible protection modes Up to 2048 bytes SRAM data storage n In System Serial Programming ISSP m Additional System Resources Complete Development Tools Configurable communication speeds P p n C Slave Free development tool PSoC Designer Selectable to 50 kHz 100 kHz 400 kHz Full featured in circuit emulator and programmer Full speed emulation a Complex breakpoint structure 128K trace memory Implementation requires no clock stretching Implementation during sleep modes with less than 100 mA Hardware address detection Precision Progra
5. P2 0 P2 1 P4 2 P4 S QFN P4 0 FADE Top View 6 P3 7 P3 4 P3 5 P3 2 P3 3 P3 0 P3 1 XRES P1 7 P1 6 _ Table 3 48 Pin Part Pinout QFN Pin No Type Name Description 1 NC NC No connection 2 2 7 Digital I O 3 y o P2 5 Digital I O Crystal Out 4 P2 3 Digital I O Crystal In Xin 5 P2 1 Digital I O 6 P4 3 Digital I O 7 4 1 Digital I O 8 P3 7 Digital I O 9 P3 5 Digital I O 10 P3 3 Digital I O 11 P3 1 Digital I O 12 IOHR P1 7 Digital I O 2 SCL SPI SS 13 IOHR P1 5 Digital I O 2 SDA SPI MISO 14 NC NC No connection 15 NC NC No connection 16 IOHR P1 3 Digital SPI CLK 12 IOHR P1 1 8 4 Digital I O ISSP CLK 2 SCL SPI MOSI Document Number 001 12395 Rev H Page 9 of 30 Feedback CYPRESS CY7C604XX 4 PERFORM Table 3 48 Pin Part Pinout QFN continued Pin No Type Name Description 18 Power Vss Supply ground 19 NC NC No connection 20 NC NC No connection 21 Power Vdd Supply voltage 22 IOHR P1 0 9 Digital I O ISSP DATA 12C SDA SPI CLK 23 IOHR P1 2 Digital I O 24 IOHR P1 4 Digital I O optional external clock input EXTCLK 25 IOHR P1 6 Digital I O 26 XRES Ext Reset Active high external reset with internal pull down 27 y o 0 Digital I O 28 VO P3 2 Di
6. C9 0A 4A 8A CA 0B 4B 8B CB PRT3DMO 0C RW 4C 8C cc PRT3DM1 00 RW 4D 8D CD 4 8E GE OF 4F 8F PRT4DMO 0 RW 50 90 DO PRT4DM1 1 RW 91 D1 B 52 92 D2 E 53 93 D3 4 54 94 D4 5 55 95 D5 6 56 96 D6 m 97 7 8 58 98 D8 9 59 99 D9 1A 5A 9A DA B 5B 9B DB 5C 9C IO CFG DC RW D 5D 9D OUT P1 DD RW E 5E 9E DE 1F 5F 9F DF 20 60 AO OSC_CRO EO RW 21 61 A1 ECO CFG E1 22 62 A2 OSC_CR2 E2 RW 23 63 A3 VLT_CR E3 RW 24 64 A4 VLT_CMP E4 R 25 65 A5 5 26 66 E6 27 67 A7 EZ 28 68 A8 IMO TR E8 w SPI CFG 29 RW 69 A9 ILO TR E9 w 2A 6A AA EA 2B eB AB SLP CFG EB RW TMP DRO 6C RW AC SLP_CFG2 EC RW 2D TMP_DR1 6D RW AD SLP_CFG3 ED RW 2E TMP_DR2 6E RW AE EE 2 _ 6F RW AF EF 30 70 BO FO 31 B1 F1 32 72 B2 F2 Sg 73 B3 F3 34 74 B4 F4 35 75 B5 5 36 76 B6 F6 97 TT B7 CPU_F F7 RL 38 78 B8 F8 39 79 B9 F9 3A 7A BA FA 3B 7B BB FB 3C 7C BC 3D 7D BD FD 3E 7E BE FE FF Gray fields are reserved and should not be accessed Document Number 001 12395 Rev H Access is bit specific Page 13 of 30 Feedback LJ CYPRESS PERFORM CY7C604XX Electrical Specifications This section presents the DC and AC electrical specifications of the enCoRe V LV devices For the most up to date electrical specifications verify that you have the most recent data sheet available by visiting the company web site at http www cypres
7. Output Voltage IOH 0 2 mA maximum of 10 mA source Vdd 0 4 V Port 2 or 3 Pins current in all I Os Vous High Output Voltage lt 10 pA maximum of 10 mA source Vdd 0 2 V Port 0 or 1 Pins with LDO Regulator current in all I Os Disabled for Port 1 High Output Voltage IOH 2 mA maximum of 10 mA source Vdd 0 5 V Port 0 or 1 Pins with LDO Regulator current in all I Os Disabled for Port 1 High Output Voltage lt 10 pA Vdd gt 2 4V maximum of 20 1 50 1 80 2 10 V Port 1 Pins with LDO Enabled for 1 8V mA source current in all I Os Out VoH6A High Output Voltage IOH 1 mA Vdd gt 2 4V maximum of 20 1 20 V Port 1 Pins with LDO Enabled for 1 8V mA source current in all I Os Out VoL Low Output Voltage IOL 10 mA maximum of 30 mA sink 0 75 V current on even port pins for example PO 2 and P1 4 and 30 mA sink current on odd port pins for example PO 3 and P1 S Input Low Voltage 0 72 V Vin Input High Voltage 1 6 V Vu Input Hysteresis Voltage 80 mV li Input Leakage Absolute Value 0 001 1 Capacitive Load on Pins Package and pin dependent 0 5 1 7 5 pF Temp 25 C Document Number 001 12395 Rev H Page 18 of 30 Feedback E gt CYPRESS CY7C604XX I PERFORM Table 12 1 71V to 2 4V DC GPIO Specifications Symbol Description Conditions Min Typ Max Units Pul
8. Sample Rate 23 4375 ksps Data Clock set to 6 MHz Sample Rate 0 001 2 Resolution Data clock DC Accuracy DNL 1 2 LSb For any configuration INL 2 2 LSb For any configuration Offset Error 0 15 90 mV Operating Current 275 350 uA Data Clock 2 25 12 MHz Source is chip s internal main oscillator See AC Chip Level Specifications for accuracy Monotonicity Not guaranteed See DNL Power Supply Rejection Ratio PSRR Vdd 3 0V 24 dB PSRR 2 2 Vdd 3 0 30 dB PSRR 2 0 Vdd 2 2 12 dB PSRR Vdd 2 0 0 dB Gain Error 1 5 FSR For any resolution Input Resistance 1 BOOfF D 1 400fF D 1 300fF D Equivalent switched cap input resis ata Clock ata Clock ata Clock tance for 8 9 or 10 bit resolution Document Number 001 12395 Rev H Page 15 of 30 Feedback CYPRESS CY7C604XX Maximum Ratings Electro Static Discharge Voltage ESD 9 2000V 5 i Latch up Current LU 0 2 2 2 200 mA Storage Temperature 557C to 125 C Typical 25 C Supply Voltage Relative to Vss 0 5V to 4 0V Operating Conditions DC Input Voltage Vio Vss 0 5V to Vdd 0 5V Ambient Temperature 0 C to 70 C DC Voltage Applied to Tri state Vioz Vss 0 5V to Vdd 0 5V Operational Die Temperature T 0 C to 85
9. Table 1 the Typ Max values for on the Document Title CY7C604XX enCoRe V Low Voltage Microcontroller DC chip level specifications and the Min voltage value for Vddiwgirg in the DC Corrected Flash Write Endurance minimum value in the DC Programming Speci Corrected the Flash Erase Time max value and the Flash Block Write Time max value in the AC Programming Specifications table Corrected the description to pin 13 29 on Table 1 and 22 44 on Table 2 Added sections Register Reference Register Conventions and Register Mapping Tables Corrected Max values on the DC Chip Level Specifications table Changed parameter max value to 18ms in Table 18 AC Programming Updated Ordering Code table Ordering code changed for 32 QFN package From 32LKXC to 32LTXC Specification Post to www cypress com Added new package type LTXC for 48 QFN Included Tape and Reel ordering code for 32 QFN and 48 QFN packages Changed active current values at 24 12 and 6MHz in table DC Chip Level Speci IDD24 2 15 to 3 1mA IDD12 1 45 to 2 0mA IDD6 1 1 to 1 5mA Added information on using P1 0 and P1 1 as the 2 interface during POR or reset events Converted from Preliminary to Final ADC resolution changed from 10 bit to 8 bit On Page1 SPI Master and Slave speeds changed Included ADC specifications table Flash data retention condition added to Note 15 R
10. during startup reset from the XRES pin or reset from watchdog 10 Always greater than 50 mV above for falling supply 11 Always greater than 50 mV above Vppogo for falling supply 12 Always greater than 50 mV above for falling supply 13 Always greater than 50 mV above voltage for falling supply 14 Driving internal pull down resistor 15 See appropriate DC General Purpose Specifications table For Vdd gt use in Table 10 on page 17 16 Erase write cycles per block 17 Following maximum Flash write cycles at Tamb 55C and Tj 70C Document Number 001 12395 Rev H Page 20 of 30 Feedback gt _ M sd 7 55 PERFORM AC Electrical Characteristics AC Chip Level Specifications Table 15 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges Table 15 AC Chip Level Specifications CY7C604XX Symbol Description Min Typ Max Units FMAx Maximum Operating Frequency 9 24 MHz Maximum Processing Frequency 9 24 MHz 1 Internal Low Speed Oscillator Frequency 19 32 50 kHz Fimo24 Internal Main Oscillator Stability for 24 MHz 5 20 22 8 24 25 2 MHz Fimo12 Internal Main Oscillator Stability for 12 2 20 11 4 12 12 6 MHz Internal Main Oscillator St
11. 0 2 75 V Port 1 Pins with LDO Enabled for 2 5V mA source current in all I Os Out Vous High Output Voltage IOH 2 mA Vdd gt 2 7V maximum of 20 1 90 V Port 1 Pins with LDO Enabled for 2 5V mA source current in all I Os Out Voug High Output Voltage lt 10 pA Vdd gt 2 7V maximum of 20 1 60 1 80 2 1 V Port 1 Pins with LDO Enabled for 1 8V mA source current in all I Os Out 10 High Output Voltage 1 mA Vdd gt 2 7V maximum of 20 1 20 V Port 1 Pins with LDO Enabled for 1 8V mA source current in all I Os Out VoL Low Output Voltage IOL 25 mA Vdd gt 3 3V maximum of 60 0 75 V mA sink current on even port pins for example PO 2 and P1 4 and 60 mA sink current on odd port pins for example PO 3 and P1 5 Vi Input Low Voltage 0 80 V Vin Input High Voltage 2 00 V Vu Input Hysteresis Voltage 80 mV li Input Leakage Absolute Value 0 001 1 Pin Capacitance Package and pin dependent 0 5 1 7 5 pF Temp 25 C Document Number 001 12395 Rev H Page 17 of 30 Feedback 25 gt CYPRESS CY7C604XX I PERFORM Table 11 2 4V to 3 0V DC GPIO Specifications Symbol Description Conditions Min Typ Max Units Pull Up Resistor 4 5 6 8 Vout High Output Voltage lt 10 pA maximum of 10 mA source Vdd 0 2 V Port 2 or 3 Pins current in all I Os High
12. 25 6 87 36 97976 SPSS 525206550504 525 6959525262 262526262 KX h X gt 5 500 0 100 001 13191 C Some IC packages require baking before they are soldered onto a PCB to remove moisture that may have been absorbed after leaving the factory A label on the package has details about the actual bake temperature and the minimum bake time to remove this moisture The maximum bake time is the aggregate time that the parts exposed to the bake temperature Exceeding this exposure may degrade device reliability Table 21 Package Handling Parameter Description Minimum Typical Maximum Unit TBAKETEMP Bake Temperature 125 See package label Me TBAKETIME Bake Time See package label 72 hours Document Number 001 12395 Rev H Page 27 of 30 Feedback gt SZ ED CYPRESS PERFORM Thermal Impedances Package Typical Oj 29 16 QFN 32 69 C W 32 QFN 4 19 51 C W 48 QFN 4 17 68 C W Solder Reflow Peak Temperature Following is the minimum solder reflow peak temperature to achieve good solderability CY7C604XX Package Minimum Peak Temperature Maximum Peak Temperature 16 QFN 2409C 260 C 32 QFN 240 C 260 C 48 QFN 240 C 260 C Ordering Information Orderi
13. C Maximum Current into any Port Pin 25mA to 50 mA DC Electrical Characteristics DC Chip Level Specifications Table 9 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges Table 9 DC Chip Level Specifications Parameter Description Conditions Min Typ Max Units Vdd Supply Voltage See table titled DC POR and LVD 1 71 3 6 V Specifications on page 20 Ipp24 Supply Current IMO 24 MHz Conditions are Vdd 3 0V T4 25 C 3 1 mA CPU 24 MHz No I2C SPI Ipp12 Supply Current IMO 12 MHz Conditions are Vdd 3 0V 25 C 2 0 mA CPU 12 MHz No I2C SPI Ippe Supply Current IMO 6 MHz Conditions Vdd 3 0V TA 25 C 1 5 mA CPU 6 MHz No I2C SPI IsBo Deep Sleep Current Vdd 3 0V T4 25 C IO regulator 0 1 HA turned off Standby Current with POR LVD and Vdd 3 0V T4 25 C IO regulator 1 5 HA Sleep Timer turned off Notes 5 Higher storage temperatures reduce data retention time Recommended storage temperature is 25 C 25 C Extended duration storage temperatures above 85 C degrade reliability 6 Human Body Model ESD 7 According to JESD78 standard 8 The temperature rise from ambient to junction is package specific See on page 27 The user must limit the power consumption to comply with this requirement Document Number 001 12395 Rev H Page 16 of 30 Feedback gt Z e a Am 2 CYP
14. O space and is broken into two parts Bank 0 user space and Bank 1 config uration space The XIO bit in the Flag register CPU F deter mines which bank the user is currently in When the XIO bit is set the user is said to be in the extended address space or the configuration registers Page 11 of 30 Feedback PERFORM Table 5 Register Map Bank 0 Table User Space CY7C604XX Name Addr 0 Hex Access Name Addr 0 Access Name Addr 0 Hex Access Name Addr 0 Access PRTODR 00 RW 40 80 co PRTOIE 01 RW 41 81 Ci 02 42 82 C2 03 43 83 C3 PRT1DR 04 RW 44 84 C4 PRT1IE 05 RW 45 85 c5 06 46 86 C6 07 47 87 C7 PRT2DR 08 RW 48 88 12 _ C8 RW PRT2IE 09 RW 49 89 2 XSTAT C9 R 0A 4A 8A 2 CA RW 0B 4B 8B 2 BP CB R PRT3DR 0C RW 4C 8C 2 cc R PRT3IE oD RW 4D 8D CPU_BP cD RW 0 4 8E CPU_CP CE R OF 4F 8F 12C_BUF CF RW PRT4DR 10 RW 50 90 CUR_PP DO RW PRT4IE 11 RW 51 91 STK PP D1 RW 12 52 92 D2 13 53 93 IDX_PP D3 RW 14 54 94 MVR_PP D4 RW 15 55 95 MVW_PP D5 RW 16 56 96 12 _ D6 RW 17 57 97 2 SCR D7 18 58 98 12C_DR D8 RW 19 59 99 D9 1A 5A 9A INT_CLRO DA RW 1B 5B 9B INT CLR1 DB RW 1 5C 9C INT CLR2 DC RW 1D 5D 9D INT CLR3 DD RW 1E 5E 9E IN
15. RESS PERFORM DC General Purpose I O Specifications CY7C604XX The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges 1 71V to 3 6V and 0 C lt TA x 70 C Typical parameters apply to 3 3V at 25 C These for design guidance only Table 10 3 0V to 3 6V DC GPIO Specifications Symbol Description Conditions Min Typ Max Units Pull Up Resistor 4 5 6 8 High Output Voltage lt 10 uA maximum of 10 mA source Vdd 0 2 V Port 2 or 3 Pins current in all I Os High Output Voltage 1 mA maximum of 20 mA source Vdd 0 9 V Port 2 or 3 Pins current in all I Os Vous High Output Voltage lt 10 uA maximum of 10 mA source Vdd 0 2 V Port 0 or 1 Pins with LDO Regulator current in all I Os Disabled for Port 1 High Output Voltage 5 mA maximum of 20 mA source Vdd 0 9 V Port 0 or 1 Pins with LDO Regulator current in all I Os Disabled for Port 1 Vous High Output Voltage IOH 10 pA Vdd gt 3 1V maximum of 4 2 85 3 00 3 3 V Port 1 Pins with LDO Regulator I Os all sourcing 5 mA Enabled for 3V Out Vous High Output Voltage IOH 5 mA Vdd gt 3 1V maximum of 20 2 20 V Port 1 Pins with LDO Regulator mA source current all I Os Enabled for 3V Out High Output Voltage lt 10 pA Vdd gt 2 7V maximum of 20 2 35 2 5
16. T MSK2 DE RW 1F 9F INT MSK1 DF RW 20 60 AO INT_MSKO EO RW 21 61 A1 INT SW EN E1 RW 22 62 A2 INT VC E2 RC 23 63 A3 RES WDT E3 w 24 64 A4 INT_MSK3 E4 RW 25 65 A5 ES 26 66 A6 E6 27 67 A7 ET 28 68 A8 E8 SPI TXR 29 w 69 A9 E9 SPI RXR 2A R 6A AA EA SPI CR 2B 6B AB EB 2C 6 EC 2D 6D AD ED 2E 6E AE EE 2F 6F AF EF 30 70 PTO_CFG BO RW FO 31 71 PTO DATA1 B1 RW F1 22 72 PTO DATAO B2 RW F2 33 73 PT1 CFG B3 RW 34 74 PT1 DATA1 B4 RW F4 35 75 PT1 DATAO B5 RW 36 76 PT2 CFG B6 RW F6 37 77 PT2 DATA1 B7 RW CPU F7 RL 38 78 PT2 DATAO B8 RW F8 39 79 B9 F9 3A 7A BA FA 3B 7B BB FB 3C 7C BC FC 3D 7D BD FD 3E WE BE CPU SCR1 FE 7 CPU SCRO FF Gray fields are reserved and shou d not be accessed Access is bit specific Document Number 001 12395 Rev H Page 12 of 30 Feedback X CYPRESS PERFORM Table 6 Register Map Bank 1 Table Configuration Space CY7C604XX Name Addr 1 Hex Access Name Addr 1 Hex Access Name Addr 1 Hex Access Name Addr 1 Hex Access PRTODMO 00 RW 40 80 co PRTODM1 01 RW 41 81 Ci 02 42 82 C2 03 43 83 C3 PRT1DMO 04 RW 44 84 C4 PRT1DM1 05 RW 45 85 C5 06 46 86 C6 07 47 87 C7 PRT2DMO 08 RW 48 88 C8 PRT2DM1 09 RW 49 89
17. ability for 6 MHz 5 7 6 0 6 3 MHz DCimo Duty Cycle of IMO 40 50 60 Supply Ramp Time 0 us AC General Purpose IO Specifications Table 16 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges Table 16 AC GPIO Specifications Symbol Description Conditions Min Typ Max Units Fepio GPIO Operating Frequency Normal Strong Mode Port 0 1 0 6 MHz for MHz 1 71V Vdd 2 4V 0 12 MHz for 2 4V lt Vdd lt 3 6V Normal Strong Mode Port 2 3 0 3 MHz for MHz 1 71V lt Vdd lt 2 4V 6 MHz for 3 0V lt Vdd lt 3 6V TRise23 Rise Time Strong Mode Cload Vdd 3 0 to 3 6V 10 90 15 80 5 50 pF Ports 2 or 3 Vdd 2 4 to 3 0V 10 90 15 100 TRise23L Rise Time Strong Mode Low Vdd 1 71 to 3 0V 1096 90 15 100 ns Supply Cload 50 pF Ports 2 or 3 TRise01 Rise Time Strong Mode Cload Vdd 3 0 to 3 6V 10 90 10 50 ns 50 pF LDO enabled or disabled Ports 0 or 1 Vdd 2 4 to 3 0V 10 90 10 70 LDO enabled or disabled TRiseO1L Rise Time Strong Mode Low Vdd 1 71 to 3 0V 1096 90 15 100 ns Supply Cload 50 pF LDO enabled or disabled Ports 0 or 1 TFall Fall Time Strong Mode Cload Vdd 3 0 to 3 6V 1096 90 10 _ 80 ns 50 pF All Ports Vdd 1 71 to 3 0V 10 90 10 _ 80 Notes 18 Digital clocking functions 19 CPU speed 20 Trimmed using factory trim values Document Number 001 12395 Rev H Page 21 of 30 mU x
18. arget board and performs full speed 24 MHz operation Page 3 of 30 Feedback CYPRESS PERFORM Designing with PSoC Designer The development process for the enCoRe V device differs from that of a traditional fixed function microprocessor Powerful PSoC Designer tools get the core of your design up and running in minutes instead of hours The development process can be summarized in the following four steps 1 Select Components 2 Configure Components 3 Organize and Connect 4 Generate Verify and Debug Select Components The chip level views provide a library of pre built pre tested hardware peripheral components These components are called user modules User modules make selecting and implementing peripheral devices simple and come in analog digital and mixed signal varieties Configure Components Each of the components you select establishes the basic register settings that implement the selected function They also provide parameters and properties that allow you to tailor their precise configuration to your particular application The chip level user modules are documented in data sheets that are viewed directly in PSoC Designer These data sheets explain the internal operation of the component and provide perfor mance specifications Each data sheet describes the use of each user module parameter and contains other information you may need to successfully implement your design Orga
19. ces Numeric Naming Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase h for example 14h or 8Ah Hexadecimal numbers may also be represented by a Ox prefix the C coding convention Binary numbers have an appended lowercase b for example 01010100b or 01000011b Numbers not indicated by an h b Ox are decimal Page 5 of 30 Feedback Pin Configuration 16 Pin Part Pinout CY7C604XX Figure 1 CY7C60413 16 Pin enCoRe V LV Device ON 5 A n n gt os P2 5 12E P2 3 QFN COL 11 xnES 1 7 Top View 10 P1 4 P1 S 9 B 1 2 gt gt oa A Table 1 16 Pin Part Pinout QFN Pin No Type Name Description 1 y o P2 5 Digital I O Crystal Out 2 P2 3 Digital I O Crystal In Xin 3 IOHR 1 7 Digital I O 12C SCL SPI SS 4 IOHR P1 5 Digital I O 2 SDA SPI MISO 5 IOHR P1 3 Digital I O SPI CLK 6 IOHR P1 1 Digital I O ISSP 2 SCL SPI MOSI 7 Power Vss Ground Pin 8 IOHR P1 0 Digital I O ISSP DATA 2 SDA SPI CLK 9 IOHR P1 2 Digital I O 10 IOHR P1 4 Digital I O optional external clock input EXTCLK 11 Input XRES Active high external reset with internal pull down 12 IOHR PO 4 Digital I O 13 Power Vdd Power Pin 14 IOHR PO 7 Digital I O 15 IOHR PO 3 Digital I O 16 IOHR PO 1 Dig
20. e SES Cypress 5 AAA SCLK P1 1 RSCLK FS L p Tsscux Toscik AC SPI Specifications Table 19 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges Table 19 AC SPI Specifications Symbol Description Min Typ Max Units Fopim Maximum Input Clock Frequency Selection Master 12 2 4V Vdd 3 6V 21 2 Maximum Input Clock Frequency Selection Master 6 1 71V Vdd 2 4V Maximum Input Clock Frequency Selection Slave 12 2 4V lt Vdd lt 3 6V MHz Maximum Input Clock Frequency Selection Slave 6 1 71V Vdd 2 4V Tss Width of SS_ Negated Between Transmissions 50 ns Page 23 of 30 Feedback 21 Output clock frequency is half of input clock rate Notes Document Number 001 12395 Rev H I lt CYPRESS CY7C604XX PERFORM AC 2 Specifications Table 20 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges Table 20 AC Characteristics of the IC SDA and SCL Pins Standard Mode Fast Mode Symbol Description Min Max Min Max Units Fsciiec SCL Clock Frequency 0 100 0 400 kHz Hold Time repeated START Condition After this period 4 0 0 6 us the first clock pulse is generated TLowlec LOW Period of the SCL Clock 4 7 1 3 B us THIGHI2C HIGH Period of the SCL Clock 4 0 0 6 us Tsu
21. ents specific pin register and electrical specifications For in depth information along with detailed programming information reference the PSoC Programmable System on Chip Technical Reference Manual for CY8C28xxx PSoC devices For up to date Ordering Packaging and Electrical Specification information reference the latest enCoRe V device data sheets on the web at http www cypress com Development Kits Development Kits are available online from Cypress at www cypress com shop and through a growing number of regional and global distributors which include Arrow Avnet Digi Key Farnell Future Electronics and Newark Training Free technical training on demand webinars and workshops is available online at www cypress com training The training covers a wide variety of topics and skill levels to assist you in your designs CyPros Consultants Certified PSoC Consultants offer everything from technical assistance to completed PSoC designs To contact or become a PSoC Consultant go to www cypress com cypros Solutions Library Visit our growing library of solution focused designs at www cypress com solutions Here you can find various appli cation designs that include firmware and hardware design files that enable you to complete your designs quickly Technical Support For assistance with technical issues search KnowledgeBase articles and forums at www cypress com support If you cannot find an answer to your questi
22. ephrased battery monitoring clause in page 1 to include with external compo Document History Page Document Number 001 12395 Orig of Submission Rev ECN No Change Date 57 626516 TYJ See ECN New data sheet A 735721 TYJ ARI See ECN B 1120504 ARI See ECN Programming Specifications table fications table Implemented new latest template C 1225864 AESA ARI See ECN D 1446763 AESA See ECN E 1639963 AESA See ECN F 2138889 TYJ PYRS See ECN fications G 2583853 TYJ PYRS 10 10 08 HMT nents Voh5 Voh7 Voh9 specs changed Input leakage spec changed to 25 nA max Under AC Char Frequency accuracy of ILO corrected GPIO rise time for ports 0 1 and ports 2 3 made common AC Programming specifications updated Included AC Programming cycle timing diagram Input Leakage Current maximum value changed to 1 uA Table 18 Updated parameter in Table 13 Specifications Document Number 001 12395 Rev H AC SPI specification updated Spec change for 32 QFN package Maximum specification for Vopsa parameter changed from 2 0 to 2 1V Minimum voltages for and Fspis specifications changed from 1 8V to 1 71V Updated Thermal impedance values for the packages Table 20 Update Development Tools add Designing with PSoC Designer Edit fix links and table format Update TMs Update maximum data in Table 12 DC POR and LVD Page 29 of 30 Feedback CYPRESS CY7C604XX PERFORM
23. ete with embedded libraries providing port and bus operations standard keypad and display support and extended math functionality Debugger PSoC Designer has a debug environment that provides hardware in circuit emulation allowing you to test the program in a physical system while providing an internal view of the PSoC device Debugger commands allow the designer to read and program flash read and write data memory read and write I O registers read and write CPU registers set and clear break points and provide program run halt and step control The debugger also allows the designer to create a trace buffer of registers and memory locations of interest Online Help System The online help system displays online context sensitive help for the user Designed for procedural help and quick reference each functional subsystem has its own context sensitive help This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer in getting started In Circuit Emulator A low cost high functionality ICE In Circuit Emulator is available for development support This hardware has the capability to program single devices The emulator consists of a base unit that connects to the PC by way of a USB port The base unit is universal and operates with all enCoRe and PSoC devices Emulation pods for each device family are available separately The emulation pod takes the place of the PSoC device in the t
24. ferenced herein are property of the respective corporations Purchase of 12C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips 12C Patent Rights to use these components in an I2C system provided that the system conforms to the 2 Standard Specification as defined by Philips All products and company names mentioned in this document may be the trademarks of their respective holders Feedback
25. gital I O 29 P3 4 Digital I O 30 P3 6 Digital I O 31 4 0 Digital I O 32 y o P4 2 Digital I O 33 y o 2 0 Digital I O 34 2 2 Digital I O 35 P2 4 Digital I O 36 y o 2 6 Digital I O 37 PO 0 Digital I O 38 PO 2 Digital I O 39 PO 4 Digital I O 40 PO 6 Digital I O 41 Power Vdd Supply voltage 42 NC NC No connection 43 NC NC No connection 44 PO 7 Digital I O 45 IOH PO 5 Digital I O 46 PO 3 Digital I O 47 Power Vss Supply ground 48 1 Digital I O CP Power Vss Center pad must be connected to ground LEGEND Input O Output OH 5 mA High Output Drive R Regulated Output Document Number 001 12395 Rev H Page 10 of 30 Feedback n gt L Ed Register Reference CY7C604XX The section discusses the registers of the enCoRe V LV device It lists all the registers in mapping tables in address order Register Conventions The register conventions specific to this section are listed in the following table Table 4 Register Conventions Convention Description R Read register or bits W Write register or bits L Logical register or bits C Clearable register or bits Access is bit specific Document Number 001 12395 Rev H Register Mapping Tables The enCoRe V LV device has a total register address space of 512 bytes The register space is also referred to as I
26. herals 2 a fast CPU Flash program memory SRAM data memory and configurable I O are included in a range of convenient pinouts The architecture for this device family as illustrated in enCoRe V LV Block Diagram is comprised of two main areas the CPU core and the system resources Depending on the enCoRe V LV package up to 36 general purpose IO GPIO are also included Enhancements over the Cypress s legacy low voltage microcon trollers include faster CPU at lower voltage operation lower current consumption twice the RAM and Flash hot swapable l Os 2 hardware address recognition new very low current sleep mode and new package options The enCoRe V LV Core The enCoRe V LV Core is a powerful engine that supports a rich instruction set It encompasses SRAM for data storage an interrupt controller sleep and watchdog timers and IMO internal main oscillator and ILO internal low speed oscillator The CPU core called the M8C is a powerful processor with speeds up to 24 MHz The is a four MIPS 8 bit Harvard architecture microprocessor System Resources provide additional capability such as a configurable 2 slave and SPI master slave communication interface and various system resets supported by the M8C Additional System Resources System Resources some of which have been previously listed provide additional capability useful to complete systems Additional resources include low voltage detec
27. ital I O LEGEND Input O Output OH 5 mA High Output Drive R Regulated Output Document Number 001 12395 Rev H Page 6 of 30 Feedback 32 Pin Part Pinout Figure 2 CY7C60445 32 Pin enCoRe V LV Device 2 9 gt a n 7 Vdd PO 6 PO 4 PO 2 CY7C604XX PO 1 1 PO 0 P2 7 2 P2 6 P2 5 3 P2 4 P2 3 4 QFN P2 2 P2 1 5 Top View P2 0 P3 3 m 6 P3 2 P3 1 7 P3 0 1 7 m 8 XRES morgen e amp KR aaad Table 2 32 Pin Part Pinout QFN Pin No Type Name Description 1 IOH P0 1 Digital I O 2 2 7 Digital I O 3 y o P2 5 Digital I O Crystal Out 4 P2 3 Digital I O Crystal In Xin 5 P2 1 Digital 6 P3 3 Digital I O 7 P3 1 Digital 8 IOHR P1 7 Digital I O 2 SCL SPI SS 9 IOHR P1 5 Digital I O 2 SDA SPI MISO 10 IOHR P1 3 Digital I O SPI CLK 11 IOHR P1 1 7 Digital 1 0 ISSP CLK 12C SCL SPI MOSI 12 Power Vss Ground connection 13 IOHR 1 0 9 Digital O ISSP DATA I2C SDA SPI CLK 14 IOHR P1 2 Digital I O 15 IOHR P1 4 Digital I O optional external clock input EXTCLK 16 IOHR P1 6 Digital Notes 1 Document Number 001 12395 Rev H During power up or reset event device P1 0 and P1 1 may disturb the 2 bus Use alternate pins if issues are encountered 2 These are the in system serial programmi
28. l Up Resistor 4 5 6 8 High Output Voltage 10 pA maximum of 10 mA Vdd 0 2 V Port 2 or 3 Pins source current in all I Os High Output Voltage IOH 0 5 mA maximum of 10 mA Vdd 0 5 V Port 2 or 3 Pins source current in all I Os Vous High Output Voltage 100 pA maximum of 10 mA Vdd 0 2 V Port 0 or 1 Pins with LDO Regulator source current in all I Os Disabled for Port 1 High Output Voltage IOH 2 mA maximum of 10 mA Vdd 0 5 V Port 0 or 1 Pins with LDO Regulator source current in all I Os Disabled for Port 1 VoL Low Output Voltage IOL 5 mA maximum of 20 mA sink 0 4 V current on even port pins for example PO 2 and P1 4 and 30 mA sink current on odd port pins for example PO 3 and P1 5 Input Low Voltage O 3xVdd V Vin Input High Voltage 0 65 x Vdd V Vu Input Hysteresis Voltage 80 liL Input Leakage Absolute Value 0 001 1 HA CpiN Capacitive Load on Pins Package and pin dependent 0 5 1 7 5 pF Temp 25 C Document Number 001 12395 Rev H Page 19 of 30 Feedback DC POR and LVD Specifications Table 13 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges Table 13 DC POR and LVD Specifications CY7C604XX Symbol Description Min Typ Max Units Vdd Value for PPOR Trip
29. lso supports easy development of multiple configura tions and dynamic reconfiguration Dynamic reconfiguration enables changing configurations at run time System Level View The system level view is a drag and drop visual embedded system design environment based on PSoC Designer Hybrid Designs You can begin in the system level view allow it to choose and configure your user modules routing and generate code then switch to the chip level view to gain complete control over on chip resources All views of the project share common code editor builder and common debug emulation and programming tools Code Generation Tools PSoC Designer supports multiple third party C compilers and assemblers The code generation tools work seamlessly within the PSoC Designer interface and have been tested with a full range of debugging tools The choice is yours Document Number 001 12395 Rev H CY7C604XX Assemblers The assemblers allow assembly code to be merged seamlessly with C code Link libraries automatically use absolute addressing or are compiled in relative mode and linked with other software modules to get absolute addressing C Language Compilers C language compilers are available that support the enCoRe and PSoC families of devices The products allow you to create complete C programs for the PSoC family devices The optimizing C compilers provide all the features of C tailored to the PSoC architecture They come compl
30. mmable Clocking Erst master and SP Slave Configurable between 93 75 kHz and 12 MHz Crystal less oscillator with support for an external crystal a Three 16 bit timers resonator i a 8 bit ADC used to monitor battery voltage or other signals Internal 5 0 6 12 or 24 MHz main oscillator with external components Internal low speed oscillator at 32 kHz for watchdog and 3 Watchdog and sleep timers sleep The frequency range is 19 to 50 kHz with a 32 kHz 4 typical value Integrated supervisory circuit enCoRe V LV Block Diagram Port 4 Port 3 Prog LDO enCoRe V Low Voltage CORE System Bus Sleep and Watchdog 6 12 24 MHz Internal Main Oscillator 2048 Bytes SROM Flash 32K CPU Core Interrupt M8C Controller 3 16 Bit 12C Slave SPI POR and LVD Timers Master Slave System Resets SYSTEM RESOURCES Cypress Semiconductor Corporation 198 Champion Court San Jose CA 95134 1709 408 943 2600 Document Number 001 12395 Rev H Revised January 30 2009 Feedback CYPRESS PERFORM Functional Overview The enCoRe V LV family of devices are designed to replace multiple traditional low voltage microcontroller system compo nents with one low cost single chip programmable component Communication perip
31. ng ISSP pins that are not High Z at power on reset POR Page 7 of 30 Feedback ES CYPRESS CY7C604XX Table 2 32 Pin Part Pinout QFN continued Pin No Type Name Description 17 Reset Input XRES Active high external reset with internal pull down 18 yo P3 0 Digital I O 19 y o 2 Digital I O 20 2 0 Digital I O 21 2 2 Digital I O 22 2 4 Digital I O 23 2 6 Digital I O 24 0 Digital I O 25 PO 2 Digital I O 26 PO 4 Digital I O 27 PO 6 Digital I O 28 Power Vdd Supply voltage 29 PO 7 Digital I O 30 PO 5 Digital I O 31 PO 3 Digital I O 32 Power Vss Ground connection CP Power Vss Center pad must be connected to ground LEGEND Input O Output OH 5 mA High Output Drive R Regulated Output Notes 3 During power up or reset event device P1 0 and P1 1 may disturb the I2C bus Use alternate pins if issues are encountered 4 These are the in system serial programming ISSP pins that are not High Z at power on reset POR Document Number 001 12395 Rev H Page 8 of 30 Feedback S CYPRESS CY7C604XX PERFORM 48 Pin Part Pinout Figure 3 CY7C60455 CY7C60456 48 Pin enCoRe V LV Device mif 22 NC P2 6 P2 7 P2 4 P2 5 2 2 P2 3
32. ng Code Package Information Flash SRAM No of GPIOs Target Applications CY7C60413 16LKXC 16 Pin QFN 8x3 mm 8K 1K 13 Feature rich Wireless Mouse CY7C64013 16LKXCT 16 Pin QFN 3X3 mm 8K 1K 13 Feature rich Wireless Mouse CY7C60445 32LQXC 32 QFN 16K 1K 28 Feature Rich Wireless Mouse 5x5x0 55 mm CY7C60445 32LQXCT 32 Pin QFN and Reel 16K 1K 28 Feature Rich Wireless Mouse 5x5x0 55 mm CY7C60455 48LTXC 48 QFN 16K 1K 36 Mid Tier Wireless Keyboard 7x7x0 9 mm CY7C60455 48LTXCT 48 Pin QFN Tape and Reel 16K 1K 36 Mid Tier Wireless Keyboard 7x7x0 9 mm CY7C60456 48LTXC 48 Pin QFN 32K 2K 36 Feature Rich Wireless 7x7x0 9 mm Keyboard CY7C60456 48LTXCT 48 Pin QFN Tape and Reel 32K 2K 36 Feature Rich Wireless 7x7x0 9 mm Keyboard Notes 23 TA Power x OJA 24 To achieve the thermal impedance specified for the package solder the center thermal pad to the PCB ground plane 25 Higher temperatures may be required based on the solder melting point Typical temperatures for solder are 220 5 C with Sn Pb or 245 5 C with Sn Ag Cu paste Refer to the solder manufacturer specifications Document Number 001 12395 Rev H Page 28 of 30 Feedback CY7C604XX Description of Change Added new block diagram replaced TBDs corrected values updated pinout infor mation changed part number to reflect new specifications Corrected the description to pin 29 on
33. nize and Connect You build signal chains at the chip level by interconnecting user modules to each other and the I O pins or connect system level inputs outputs and communication interfaces to each other with Document Number 001 12395 Rev H CY7C604XX valuator functions In the chip level view you perform the selection configuration and routing so that you have complete control over the use of all on chip resources Generate Verify and Debug When you are ready to test the hardware configuration or move on to developing code for the project you perform the Generate Configuration Files step This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the software for the system Both system level and chip level designs generate software based on your design The chip level design provides application programming interfaces APIs with high level functions to control and respond to hardware events at run time and interrupt service routines that you can adapt as needed The system level design also generates a C main program that completely controls the chosen application and contains placeholders for custom code at strategic positions allowing you to further refine the software without disrupting the generated code A complete code development environment allows you to develop and customize your applications in C assembly language or both The las
34. on call technical support at 1 800 541 4736 Application Notes Application notes are an excellent introduction to the wide variety of possible PSoC designs They located here www cypress com psoc Select Application Notes under the Documentation tab Page 2 of 30 Feedback Development Tools PSoC Designer is a Microsoft Windows based integrated development environment for the Programmable System on Chip PSoC devices The PSoC Designer IDE runs on Windows XP or Windows Vista This system provides design database management by project an integrated debugger with In Circuit Emulator in system programming support and built in support for third party assem blers and C compilers PSoC Designer also supports C language compilers developed specifically for the devices in the enCoRe and PSoC families PSoC Designer Software Subsystems Chip Level View The chip level view is a traditional integrated development environment IDE based on PSoC Designer 4 4 Choose a base device to work with and then select different onboard analog and digital components called user modules that use the PSoC blocks Examples of user modules are ADCs DACs Amplifiers and Filters Configure the user modules for the chosen appli cation and connect them to each other and to the proper pins Then generate your project This prepopulates your project with APIs and libraries that you can use to program your application The tool a
35. product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement Any reproduction modification translation compilation or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Cypress reserves the right to make changes without further notice to the materials described herein Cypress does not assume any liability arising out of the application or use of any product or circuit described herein Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress product in a life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Use may be limited by and subject to the applicable Cypress software license agreement Document Number 001 12395 Rev H Revised January 30 2009 Page 30 of 30 enCoRe PSoC Designer and Programmable System on Chip are trademarks and PSoC is a registered trademark of Cypress Semiconductor Corporation All other trademarks or registered trademarks re
36. psoc cypress com usb Cypress Semiconductor Corporation 2006 2009 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Any Source Code software and or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign United States copyright laws and international treaty provisions Cypress hereby grants to licensee a personal non exclusive non transferable license to copy use modify create derivative works of and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee
37. s com Figure 5 IMO Frequency Trim Options Figure 4 Voltage versus CPU Frequency A 3 6V 8 gt 3 gt 171 4 4 I gt 3 MHz 24 MHz 750 kHz 3 MHz 6 MHz 12 MHz 24 MHz CPU Frequency IMO Frequency The following table lists the units of measure that are used in this chapter Table 7 Units of Measure Symbol Unit of Measure Symbol Unit of Measure C degree Celsius uW microwatts dB decibels mA milli ampere fF femto farad ms milli second Hz hertz mV milli volts KB 1024 bytes nA nanoampere Kbit 1024 bits ns nanosecond kHz kilohertz nV nanovolts kilohm Q ohm MHz megahertz pA picoampere MO megaohm pF picofarad uF microfarad ppm parts per million uH microhenry ps picosecond us microsecond sps samples per second uV microvolts S sigma one standard deviation pu Vrms microvolts root mean square V volts Document Number 001 12395 Rev H Page 14 of 30 Feedback S CYPRESS CY7C604XX PERFORM ADC Electrical Specifications Table 8 ADC Electrical Specifications Symbol Description Min Typ Max Units Conditions Input Input Voltage Range Vss 1 3 V This gives 72 of maximum code Input Capacitance 5 pF Resolution 8 Bits 8 Bit
38. scription of the enCoRe V LV emulation tools and their dimensions refer to the development kit Packaging Dimensions Figure 9 16 Pin 3 x 3 mm QFN 001 09116 PIN ID 0 20 DIA TYP SEATING PLANE TOP VIEW SIDE VIEW BOTTOM VIEW NOTES 1 JEDEC MO 220 PART NO 2 Package Welght 0 0140 3 DIMENSIONS IN MM MIN LD16A 001 09116 0 Page 25 of 30 Document Number 001 12395 Rev H Feedback CY7C604XX PERFORM Figure 10 32 Pin 5 x 5 x 0 55 mm QFN 001 42168 0025 0 02 726 0 15 0 550 0 05 PIN CORNER OOOO 555 3 500 5 0 0 10 XD XO gt 505050506 xy TOP VIEW BOTTOM VIEW SIDE VIEW NOTES 1 E HATCH AREA IS SOLDERABLE EXPOSED PAD 2 BASED ON REF JEDEC 8 MO 248 3 PACKAGE WEIGHT 0 0388g 4 DIMENSIONS ARE IN MILLIMETERS 001 42168 C Document Number 001 12395 Rev H Page 26 of 30 Feedback ES CYPRESS CY7C604XX PERFORM Figure 11 48 Pin 7 x 7 x 0 9 mm QFN 001 13191 SIDE VIEW TOP VIEW BOTTOM VIEW 7 000 100 5 100 REF 7 00 0 100 48 37 PIN 1 DOT LASER MARK 12 25 13 24 NOTES 1 224 HATCH AREA IS SOLDERABLE EXPOSED METAL 2 REFERENCE JEDEC MO 220 3 PACKAGE WEIGHT 0 13g 4 ALL DIMENSIONS ARE IN MILLIMETERS Package Handling 0 900 0 100 0 200 TH 0207 9 025 0 020 9 66 SEATING PLANE P 0 40 0 10 0 025 0 05 0 0
39. srapc Setup Time for a Repeated START Condition 4 7 0 6 us Tu pparec Data Hold Time 0 0 us TsupArec Data Setup Time 250 10022 ns Tsustoic Setup Time for STOP Condition 4 0 0 6 us TBUFI2C Bus Free Time Between a STOP and START Condition 4 7 _ 1 3 us Pulse Width of Spikes Suppressed by the Input Filter 0 50 ns SDA SCL Notes 22 A fast mode I2C bus device can be used in a standard mode I2C bus system but the requirement tsy pat 250 ns must then be met This is automatically the case if the device does not stretch the LOW period of the SCL signal If such device does stretch the LO Figure 8 Definition of Timing for Fast Standard Mode on the Bus Tsu DATI2C T HDDAT2C SUSTAI2C HDSTAI2C Tsusroizc period of the SCL signal it must output the next data bit to the Teurizc SDA line tma tsu pAr 1000 250 1250 ns according to the standard mode 2 bus specification before the SCL line is released Document Number 001 12395 Rev H Page 24 of 30 Feedback GE CYPRESS CY7C604XX PERFORM Package Diagram This section illustrates the packaging specifications for the enCoRe V LV device along with the thermal impedances for each package Important Note Emulation tools may require a larger area on the target PCB than the chip s footprint For a detailed de
40. t step in the development process takes place inside PSoC Designer s Debugger access by clicking the Connect icon PSoC Designer downloads the HEX image to the In Circuit Emulator ICE where it runs at full speed PSoC Designer debugging capabilities rival those of systems costing many times more In addition to traditional single step run to breakpoint and watch variable features the debug interface provides a large trace buffer and allows you to define complex breakpoint events that include monitoring address and data bus values memory locations and external signals Page 4 of 30 Feedback CYPRESS PERFORM Document Conventions Acronyms Used The following table lists the acronyms that are used in this document Acronym Description API application programming interface CPU central processing unit GPIO general purpose IO ICE in circuit emulator ILO internal low speed oscillator IMO internal main oscillator IO input output LSb least significant bit LVD low voltage detect MSb most significant bit POR power on reset PPOR precision power on reset PSoC Programmable System on Chip SLIMO slow IMO SRAM static random access memory Document Number 001 12395 Rev H CY7C604XX Units of Measure A units of measure table is located in the Electrical Specifications section Table 7 on page 14 lists all the abbreviations used to measure the enCoRe V LV devi
41. tion and power on reset The following statements describe the merits of each system resource m 8 bit on chip ADC shared between System Performance manager used to calculate parameters based on temperature for flash write operations and the user m The 2 slave and SPI master slave module provides 50 100 or 400 kHz communication over two wires SPI communication over three or four wires runs at speeds of 46 9 kHz to 3 MHz lower for a slower system clock m In 2 slave mode the hardware address recognition feature reduces the already low power consumption by eliminating the need for CPU intervention until a packet addressed to the target device has been received m Low Voltage Detection LVD interrupts can signal the appli cation of falling voltage levels while the advanced POR Power On Reset circuit eliminates the need for a system supervisor m The 5V maximum input 1 8 2 5 or 3V selectable output low dropout regulator LDO provides regulation for I Os A register controlled bypass mode enables the user to disable the LDO m Standard Cypress PSoC IDE tools are available for debugging the enCoRe V LV family of parts Document Number 001 12395 Rev H CY7C604XX Getting Started The quickest way to understanding the enCoRe V silicon is by reading this data sheet and using the PSoC Designer Integrated Development Environment IDE This data sheet is an overview of the enCoRe V integrated circuit and pres

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