Cypress CYV15G0100EQ User's Manual
Contents
1. Cable Length Analog Adjustor and Mute gt gt Threshold Block DC Restore 1 55 SDI SDI Equalizer Differential Output SDO SDO Pinouts Figure 1 Pin Diagram 16 Pin SOIC Top View 16 PIN SOIC Top View cu 16 1 CD MUTE VCC 2 15 VCC GND 3 14 GND SDI 4 13 SDO NEN CYV15G0100EQ 501 5 12 5 GND 6 11 GND AGC 7 10 MCLADJ AGC 8 9 BYPASS Document Number 001 12520 Rev Page 2 of 10 Feedback Signal Description IO Characteristics Carrier Detect or Mute Indicator Output CYV15G0100EQ Cable Length Indicator CLI provides an analog voltage proportional to the equalized 2 PERFORM Table 1 Pin Descriptions CYV15G0100EQ Single Channel Cable Equalizer cable length CLI works at both SD SDI and HD SDI data rates Analog Output When the incoming data stream is present and the cable length does not exceed the length Name Control Signals that is set by MCLADJ the CD MUTE outputs a voltage less than 0 8V LI O When the incoming data stream is not present or the cable length exceeds the length that is set by MCLADJ the CD MUTE outputs a voltage greater than 2 8V CD MUTE When the CD MUTE pin is set LOW the equalizer s differential serial outputs are not When the CD MUTE pin is set HIGH t2. Input Common Mode Voltage 1 1 4 V Bypass High Input Common Mode Voltage 0 2 9 V Bypass Low CLI DC Voltage 22 2 65 2 95 V CLI DC Voltage No Signai l 1 5 1 9 2 3 V Floating MCLADJ DC Voltage 1 3 V MCLADJ Rangel 0 4 0 72 1 02 V VepmuTE OH CD MUTE Output Voltagel Carrier Not Present 2 8 V VCD MUTE OL Carrier Present 0 8 V VGD MUTE CD MUTE Input Voltage Required to to Mute 2 5 V Force Outputs to VGD MUTE CD MUTE Input Voltage Required to Max to Activate 1 V Force Activel l Notes 1 Production test 2 Calculated results from production test 3 Not tested Based on characterization Document Number 001 12520 Rev Page 5 of 10 Feedback eS P 2 CYPRESS CYV15G0100EQ PERFORM AC Electrical Characteristics Parameter Description Test Conditions Min Typ Max Unit E Serial Input Data Rate 143 1485 Mbps Vspi Input Voltage Swing Single ended at the transmitter 500151 1200 HD data rate Vspi Input Voltage Swing Single ended at the transmitter 500161 1200 SD data rate AVspo Output Voltage Swing Differential 500 load 450 700 950 mV Output Jitter for Various Cable 270 Mbps E 0 211 Ul Lengths and Data Rates Belden 1694A 0 175m Canare L 5CFB 0 175m 800 mV transmit amplitude Equalizer pathological pattern 1 485 Gbps 0 25111 E UI Beld
3. PERFORM Features m Multi rate adaptive equalization m Operates from 143 to 1485 Mbps serial data rate m SMPTE 292M SMPTE 344M and SMPTE 259M compliant m Supports DVB ASI at 270 Mbps m Cable length indicator for HD SDI and SD SDI data rates m Maximum cable length adjustment for HD SDI and SD SDI data rates m Carrier detect and mute functionality for HD SDI and SD SDI data rates m Equalizer bypass mode m Seamless connection with HOTLink II family m Equalizes up to 175m of Canare L 5CFB and Belden 1694A coaxial cable at 270 Mbps m Equalizes up to 70m of Canare L 5CFB and Belden 1694A coaxial cable at 1 485 Gbps m Low power 160 mW at 3 3V m Single 3 3V supply m 16 pin SOIC m 0 18 um CMOS technology CYV15G0100EQ Prosumer Video Cable Equalizer m Pb free and RoHS compliant m Uses Cypress CLEANLink technology m Pin compatible to existing equalizer devices Functional Description The CYV15G0100EQ is a multi rate adaptive equalizer designed to equalize and restore signals received over 75Q coaxial cable The equalizer meets SMPTE 292M SMPTE 344M and SMPTE 259M data rates The CYV15G0100EQ is optimized to equalize up to 175m of Belden 1694A coaxial cable at 270 Mbps and up to 70m of Belden 1694A coaxial cable at 1 485 Gbps This device is mainly targeted for Prosumer Video applications where the cable length requirements are not as stringent as professional broadcast video applications The CYV15G0100EQ co
4. CD MUTE is not functional AGC Place a capacitor of 1 uF between the AGC pins of the CYV15G0100EQ equalizer Page 4 of 10 Feedback 7 CYPRESS PERFORM Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device These user guidelines are not tested CYV15G0100EQ Power Up Requirements The CYV15G0100EQ contains one power supply The voltage on any input or IO pin must not exceed the power pin during power up Storage Temperature 65 C to 150 C Ambient Temperature with Operating Range Power 55 C to 125 C Ambient Supply Voltage to Ground Potential 0 5V to 3 8V Range Temperature Vec DC Voltage Applied to Outputs 7 V 45 in High Z State 0 5V to Voc 0 5V cee DC Input Voltage 0 5V to Voc 40 5V Electro Static Discharge ESD HBM gt 2000 V JEDEC EIA JESD A114A Latch Up gt 200 mA DC Electrical Characteristics Parameter Description Test Conditions Min Typ Max Unit Voc Supply Voltage 3 135 3 3 3 465 V Pp Power Consumption 125 160 190 mW ls Supply Current 38 48 60 mA VCMOUT Output Common Mode Voltage Load 500 Vcc AVspo 2 V 2 9
5. 2520 Rev Page 3 of 10 Feedback Equalizer Operation The CYV15G0100EQ is a high speed adaptive cable equalizer designed to equalize standard definition SD and high definition HD serial digital interface SDI video data streams The CYV15G0100EQ equalizer is optimized to equalize up to 175m of Canare L 5CFB and Belden 1694A cable at 270 Mbps and up to 70m of Canare L 5CFB and Belden 1694A cable at 1 485 Gbps The CYV15G0100EQ equalizer contains one power supply and typically consumes 160 mW power at 3 3V The multi rate equalizer meets the SMPTE 259M SMPTE 292M SMPTE 344M and DVB ASI video standards It meets all pathological requirements for SMPTE 292M as defined by RP198 and for SMPTE 259M as defined by RP178 The CYV15G0100EQ Prosumer video cable equalizer is auto adaptive from 143 Mbps to 1 485 Gbps The CYV15G0100EQ equalizer has variable gain and multiple equalization stages that reverse the effects of the cable This equalization is achieved by separate regulation of the lower and higher frequency components in the signal to give a clean output eye diagram The CYV15G0100EQ has DC restoration for compensating the DC content of the SMPTE pathological patterns SDI SDI The CYV15G0100EQ accepts single ended or differential serial video data streams over 750 coaxial cable It is recommended to AC couple the SDI and SDI inputs as they are internally biased to 1 2V SDO SDO The CYV15G0100EQ has differential
6. E CD MUTE is a bidirectional pin that provides an indication of the signal present at the equalizer s input or it controls the muting of the equalizer s output The CD MUTE operates for both HD and SD data rates If CD MUTE is used as an output and the incoming data stream is not present or the cable length exceeds the length that is set by MCLADy the voltage at the CD MUTE output is greater than 2 8V If CD MUTE is used as an output the incoming data stream is present and the cable length does not exceed the length that is set by MCLADJ then the voltage at the CD MUTE output is less than 0 8V If CD MUTE is used as an input and is set LOW the equalizer serial outputs are not muted If the CD MUTE is used as an input and is set HIGH then the equalizer serial outputs are muted When an invalid signal or a signal transmitted with a launch amplitude of less than 500 mV at HD data rates is received the equalizer s serial outputs are muted BYPASS The CYV15G0100EQ has a bypass mode that enables the user to bypass the equalizer s equalization and DC restoration functions When the bypass mode is set HIGH the signal presented at the equalizer s differential serial inputs SDI SDI is routed to the equalizer s differential serial outputs SDO SDO without equalizing When BYPASS is set LOW the incoming video data stream is equalized and presented at the equalizer s differential serial outputs SDO SDO In equalizer bypass mode
7. ING PLANE 51 85068 0 050 1 270 0 0138 0 350 BSC 0 0192 0 487 Document Number 001 12520 Rev 0 004 0 102 0 0098 0 249 Page 9 of 10 Feedback Cypress CYV15G0100EQ PERFORM Document History Page Document Title CYV15G0100EQ Prosumer Video Cable Equalizer Document Number 001 12520 ISSUE ORIG OF REV ECN NO DATE CHANGE DESCRIPTION OF CHANGE Wwe 1396423 SEE ECN UKK AESA New datasheet Cypress Semiconductor Corporation 2007 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Any Source Code software and or firmware is owned by Cypress Semiconductor Co
8. ata Rates VOLTAGE V 75 100 CABLE LENGTH m 125 150 175 Document Number 001 12520 Rev Page 7 of 10 Feedback F CYPRESS CYV15G0100EQ PERFORM Typical Application Circuit Figure 4 Interfacing CYV15G0100EQ to the HOTLink II SerDes CD MUTE CLI FI RXLE RX07 SDASEL RXD6 LPEN RXD5 INSEL VC RE VE RXD3 SD RXD ai VE 1RXD0 M FRAMCHAR BY RXST2 RFEN st RXCLK RXCKSEL CYV15G0100EQ RXCLK RXMODE RXCLKC RXRATE CYV15G0101DXB Document Number 001 12520 Rev Page 8 of 10 Feedback CYV15G0100EQ Ux a Sa CYPRESS PERFORM Ordering Information i Operating Ordering Code Package Name Package Type Range CYV15G0100EQ SXC 5716 15 Pb free 16 150 Mil SOIC 0 to 70 C Package Dimension Figure 5 16 Pin 150 Mil SOIC 516 15 PIN 1 ID 8 1 DIMENSIONS IN INCHES MM MIN MAX REFERENCE JEDEC 5 012 0 150310 PACKAGE WEIGHT 0 15gms 0 157 3 987 0 386 9 804 0 393 9 982 E J i 0 068 1 727 0 004 0 102 0 8 0 230 5 842 0 244 6 197 PART STANDARD PKG 516 15 5216 15 LEAD FREE PKG 0 010 0 254 7 B X45 0 016 0 406 0 016 0 406 0 0075 0 190 03510 0 0098 0 249 0 035 0 889 SEAT
9. en 1694A 0 70m Canare L 5CFB 0 70m 800 mV transmit amplitude Equalizer pathological pattern Output Rise Fall Timel 41 20 80 HD data rate 80 120 220 ps Output Rise Fall Timel 4 20 80 SD data rate 80 120 350 ps Mismatch Rise Fall Timel 41 30 Duty Cycle Distortionl 4 HD color bar pattern 20 ps Overshootl 41 10 96 Input Return 1055131 15 dB ES Input Resistancel 4 Single ended 2 5 kQ E Input Capacitancel 4 Single ended 1 pF Output Resistancel 4 Single ended 50 Q Notes 4 Not tested Guaranteed by design simulations 5 Based on characterization across temperature and voltage with 70m of Belden 1694A cable transmitting SMPTE Equalizer Pathological Test Pattern 6 Based on characterization across temperature and voltage with 175m of Belden 1694A cable transmitting SMPTE Equalizer Pathological Test Pattern Document Number 001 12520 Rev Page 6 of 10 Feedback a 7 CYPRESS PERFORM Typical Performance Graphs Unless otherwise stated Vcc 3 3V T4 25 C Figure 2 MCLADJ Input Voltage vs Belden 1694A Cable Length at SD SDI and HD SDI Data Rates CYV15G0100EQ G VOLTAGE V Po Po Po a 8 o 8 m amp N lt 25 75 100 CABLE LENGTH m 125 175 Figure 3 CLI Output Voltage Vs Belden 1694A Cable Length at SD SDI and HD SDI D
10. he equalizer s differential serial outputs are muted Maximum Cable Length Adjust The maximum equalized cable length is set by the voltage applied to the MCLADJ input When the maximum cable length set by MCLADJ is reached CD is driven high and the differential output is muted If MCLADJ functionality is not needed then this pin should be left floating or tied to ground to allow maximum equalized cable length MCLADJ works at both SD and HD data rates Equalizer Bypass When BYPASS is set HIGH the signal presented at the equalizer s differential serial inputs SDI SDI is routed to the equalizer s differential serial outputs SDO SDO without equalizing When BYPASS is set LOW the incoming video data stream is equalized and presented at the equalizer s serial differential outputs SDO SDO In equalizer bypass mode CD MUTE is not functional Automatic Gain Control Place a capacitor of 1 uF between the pins Differential Serial Outputs The equalized serial video data stream is presented at the SDO SDO differential serial CML output Differential Serial Inputs SDI SDI accepts either a single ended or differential serial video data stream over 750 coaxial cable 3 3V Power Connect to Ground LVTTL IO Input muted MCLADJ Analog Input BYPASS LVTTL Input AGC Analog SDO SDO Differential Output SDI SDI Differential Input Power VCC Power GND Gnd Document Number 001 1
11. nnects seamlessly to the HOTLink II family of transceivers The CYV15G0100EQ has DC restoration to compensate for the DC content of the SMPTE pathological patterns A cable length indicator CLI provides an indication of the cable length equalized at HD SDI and SD SDI data rates The maximum cable length adjust MCLADJ sets the approximate maximum cable length to equalize at SD and HD data rates The CYV15G0100EQ s differential serial outputs SDO SDO mute when the approximate cable length set by MCLADJ is reached CD MUTE is a bidirectional pin that provides an indication of the signal present at the equalizer inputs It also controls muting the outputs of the equalizer at HD and SD data rates Power consumption is typically 160 mW at 3 3V Equalizer System Connection Diagram HOTLink II Cable Serial Links 2 HOTLink II Seriali Dri Prosumer Video in Copper Cable Cable Deserializer Connections Equalizer Cypress Semiconductor Corporation Document Number 001 12520 Rev 198 Champion Court San Jose CA 95134 1709 408 943 2600 Revised October 25 2007 Feedback ES CYPRESS ind CYV15G0100EQ MUTE Mute Control Block CYV15G0100EQ Prosumer Video Cable Equalizer Block Diagram Carrier Detect and MCLADJ Equalizer Block Diagram
12. rer assumes all risk of such use and in doing so indemnifies Cypress against all charges Use may be limited by and subject to the applicable Cypress software license agreement Document Number 001 12520 Rev Revised October 25 2007 Page 10 of 10 PSoC Designer Programmable System on Chip and PSoC Express are trademarks and PSoC is a registered trademark of Cypress Semiconductor Corp All other trademarks or registered trademarks referenced herein are property of the respective corporations Purchase of C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips 2 Patent Rights to use these components an IC system provided that the system conforms to the Standard Specification as defined by Philips HOTLink II is a trademark of Cypress Semiconductor Corp All other trademarks or registered trademarks referenced herein are property of the respective corporations All products and company names mentioned in this document may be the trademarks of their respective holders Feedback
13. rporation Cypress and is protected by and subject to worldwide patent protection United States and foreign United States copyright laws and international treaty provisions Cypress hereby grants to licensee a personal non exclusive non transferable license to copy use modify create derivative works of and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement Any reproduction modification translation compilation or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Cypress reserves the right to make changes without further notice to the materials described herein Cypress does not assume any liability arising out of the application or use of any product or circuit described herein Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress product in a life support systems application implies that the manufactu
14. serial output interface drivers that use current mode logic CML drivers to provide source matching for the transmission line These outputs are either AC coupled or DC coupled to the HOTLink Il SerDes device CLI Cable Length Indicator CLI is an analog output that gives an output voltage proportional to the equalized cable length CLI gives an approximation of the length of cable at the differential serial inputs SDI SDI CLI works at high definition HD data rates and standard definition SD data rates The graph in Figure 3 on page 7 illustrates the CLI output voltage at various Belden 1694A cable lengths With an increase in cable length CLI output voltage decreases Document Number 001 12520 Rev CYV15G0100EQ MCLADJ Maximum Cable Length Adjust MCLADJ sets the approximate maximum amount of cable to be equalized MCLADJ works at SD and HD data rates If the MCLADJ voltage is greater than the CLI output voltage the CD pin is driven HIGH and the outputs are muted If the MCLADJ voltage is less than CLI voltage then the equalizer s CD pin is driven LOW and the incoming data stream is equalized The graph in Figure 2 on page 7 illustrates the voltage required at MCLAD J input to equalize various Belden 1694A cable lengths for SD and HD data rates If MCLADJ functionality is not needed then this pin should be left floating or tied to ground to allow maximum equalized cable length CD MUTE Carrier Detect MUT
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