Home

Cypress CYDC064B16 User's Manual

1. Feedback CYDC256B16 CYDC128B16 CYDC064B16 CYDC128B08 CYDC064B08 S CYPRESS PERFORM I n Configurations 4 5 6 71 100 Pin TQFP Top View x 2 ls gt Y e a Qa s lt lt 86 85 84 83 82 81 80 79 78 77 76 ODR4 a y z l oa al ETETA a N 8 lt lt gt 91 100 99 98 97 96 95 94 93 92 ina 5 lt oc E E a a Oo O 90 89 gt amp O OMNOAO A WH A a CYDC064B16 no Lo CYDC128B16 n CYDC256B16 26 27 28 29 30 31 32 o gt 4 VOg L__ On 1 07 VppioL 1 Og 1 09 Notes 3 A12L and A12R are NC pins for CYDC064B16 4 IRR functionality is not supported for the CYDC256B16 device 5 This pin is A13L for CYDC256B16 device 6 This pin is A13R for CYDC256B16 device 7 Leave this pin unconnected No trace or power component can be connected to this pin Document 001 01638 Rev E IRR4 8 ncl VDDIOR VO15R VOrar VO43R Vss VOr1oR VOuRr VOxor Page 3 of 26 Feedback CYDC256B16 CYDC128B16 CYDC064B16 CYDC128B08 CYDC064B08 CYPRESS PERFORM Pin Configurations continued 9 10 100 pin TQFP Top View Z amp x ge amp ey eg od EH gyo aoaoo BIbw ke amp amp ae 3228 aizis ggs gS sFueae ss 100 99 98 97 96 95 94 93 92 91 86 85 84 83 82 81 80 79 78 77 76 OMWOAN DA A WN CYDC064B08 CYDC128B08 Aur A12R IRR110 Nc VDDIOR lt Q io 7 28 29 30
2. CYDC064B16 CYDC064B16 CYDC128B08 CYDC128B08 CYDC064B08 CYDC064B08 40 55 Pil O P21 0 Parameter Description Voltage Voltage Min Typ Max Min Typ Max Unit lix Input Leakage Current 1 8V 1 8V 1 1 1 1 uA 2 5V 2 5V 1 1 1 1 uA 3 0V 3 0V 1 1 1 1 uA lec Operating Current Vcc Max Ind 1 8V 1 8V 25 40 15 25 mA lour 0 mA Outputs Disabled Isp4 Standby Current Both Ports TTL Ind 1 8V 1 8V 2 6 2 6 uA Level CE and CER Vcc 0 2 SEM SEM R Vcc 0 2 f fMAX Ispo Standby Current One Port TTL Ind 1 8V 1 8V 8 5 18 8 5 14 mA Level CE CER gt Vin f fax Isp3 Standby Current Both Ports Ind 1 8V 1 8V 2 6 2 6 pA CMOS Level CE amp CER Vcc 0 2V SEM and SEMp gt Vcc 0 2V f 0 Ispa Standby Current One Port CMOS Ind 1 8V 1 8V 8 5 18 8 5 14 mA Level CE CER gt Vin f fmax Notes 25 fmax 1 tac All inputs cycling at f 1 tac except output enable f 0 means no address or control lines change This applies only to inputs at CMOS level standby Isp3 Document 001 01638 Rev E Page 10 of 26 Feedback CYDC256B16 CYDC128B16 CYDC064B16 CYDC128B08 CYPRESS CYDC064B08 PERFORM Electrical Characteristics for Vec 2 5V Over the Operating Range CYDC256B16 CYDC256B16 CYDC128B16 CYDC128B16 CYDC064B16 CYDC0
3. 100 uA 1 8V any port VppiIo VDpio V 0 2 0 2 Output HIGH Voltage lop 2 mA 2 5V any port 2 0 2 0 V Output HIGH Voltage lop 2 mA 3 0V any port 2 1 2 1 V VoL Output LOW Voltage Io 100 uA 1 8V any port 0 2 0 2 V Output HIGH Voltage lo 2 mA 2 5V any port 0 4 0 4 V Output HIGH Voltage lo 2 mA 3 0V any port 0 4 0 4 V Vo ODR ODR Output LOW Voltage Io 8 mA 1 8V any port 0 2 0 2 V 2 5V any port 0 2 0 2 V 3 0V any port 0 2 0 2 V Vin Input HIGH Voltage 1 8V any port 1 2 Vppio 1 2 Vppio V 0 2 0 2 2 5V any port 1 7 VDpio 1 7 VDpio V 0 3 0 3 3 0V any port 2 0 VDpio 2 0 VDpio V 0 2 0 2 ViL Input LOW Voltage 1 8V any port 0 2 0 4 0 2 0 4 V 2 5V any port 0 3 0 6 0 3 0 6 V 3 0V any port 0 2 0 7 0 2 0 7 loz Output Leakage Current 1 8V 1 8V 1 1 1 1 uA 2 5V 2 5V 1 1 1 1 pA 3 0V 3 0V 1 1 1 1 pA Ic Ex ODR ODR Output Leakage Current 1 8V 1 8V 1 1 1 1 uA Vout Vopio 25v 25v 1 1 1 1 uA 3 0V 3 0V 1 1 1 1 pA Notes 23 The voltage on any input or I O pin can not exceed the power pin during power up 24 Pulse width lt 20 ns Document 001 01638 Rev E Page 9 of 26 Feedback CYDC256B16 CYDC128B16 CYDC064B16 CYDC128B08 CYPRESS CYDC064B08 PERFORM Electrical Characteristics for Vec 1 8V continued Over the Operating Range CYDC256B16 CYDC256B16 CYDC128B16 CYDC128B16
4. 3 0V 3 0V 28 40 25 35 mA Level CEL CER gt Vins f fax lsB3 Standby Current Both Ports Ind 3 0V 3 0V 6 8 6 8 uA CMOS Level CE amp CEp Vcc 0 2V SEM and SEMp gt Voc 0 2V f 0 Ispa4 Standby Current One Port CMOS Ind 3 0V 3 0V 28 40 25 35 mA Level CE CER 2 Vin f fax Capacitance Parameter Description Test Conditions Max Unit Cin Input Capacitance Ta 25 C f 1 MHz 9 pF Cout Output Capacitance Voc 3 0V 10 pF Note 26 Tested initially and after any design or process changes that may affect these parameters Document 001 01638 Rev E Page 12 of 26 Feedback CYPRESS PERFORM AC Test Loads and Waveforms OUTPUT C 30 pF IHA 3 0V 2 5V 1 8V R1 R2 a Normal Load Load 1 3 0V 2 5V 1 8V R1 10220 135000 R2 7920 108000 R 6kQ OUTPUT C 30 pF L CYDC256B16 CYDC128B16 CYDC064B16 CYDC128B08 o VTH 0 8V b Th venin Equivalent Load 1 ALL INPUT PULSES 1 8V GND lt 3ns gt me Switching Characteristics for Vec 1 8V Over the Operating Rangel lt 3ns CYDC064B08 3 0V 2 5V 1 8V R1 OUTPUT C 5 pF T Be c Three State Delay Load 2 Used for tz thz tuzwe gt and tLzwe including scope and jig CYDC256B16 CYDC256B16 CYDC128B16 CYDC128B16 CYDC064B16
5. CE Vi UB Vit SEM Vip To access lower byte CE Vi LB Vi SEM Vip 47 Transition is measured 0 mV from steady state with a 5 pF load including scope and jig This parameter is sampled and not 100 tested 48 During this period the I O pins are in the output state and input signals must not be applied Document 001 01638 Rev E Page 19 of 26 Feedback CYDC256B16 CYDC128B16 CYDC064B16 CYDC128B08 CYPRESS CYDC064B08 PERFORM Switching Waveforms continued Semaphore Read After Write Timing Either Side 501 CE Le tote XXX SEM f as DATA n VALID XX DATAour VALID oi E LLLA LLL LL LLL AL WRITE CYCLE READ CYCLE Timing Diagram of Semaphore Contention 521 AoL A2L MATCH RWL SEM tsps AoRT 2R MATCH R WR SEMR Notes 49 If the CE or SEM LOW transition occurs simultaneously with or after the R W LOW transition the outputs remain in the high impedance state 50 CE HIGH for the duration of the above timing both write and read cycle 51 1 Oor Oo LOW request semaphore CER CE HIGH 52 If tsps is violated the semaphore will definitely be obtained by one side or the other but which side will get the semaphore is unpredictable Document 001 01638 Rev E Page 20 of 26 Feedback CYDC256B16 CYDC128B16 CYDC064B16 CYDC128B08 CYPRESS CYDC064B08 PERFORM Switching Waveforms continued Timin
6. CYDC064B16 CYDC128B08 CYDC128B08 CYDC064B08 CYDC064B08 40 55 Parameter Description Min Max Min Max Unit Read Cycle tre Read Cycle Time 40 55 ns taa Address to Data Valid 40 55 ns toHa Output Hold From Address Change 5 5 ns tace CE LOW to Data Valid 40 55 ns tDoE OE LOW to Data Valid 25 30 ns tizog a 90 11 OE Low to Low Z 5 5 ns thzog 30 31 OE HIGH to High Z 15 25 ns tLzcg 90 1 CE LOW to LowZ 5 5 ns tuzcelZ 30 311 CE HIGH to High Z 15 25 ns tpu CE LOW to Power Up 0 0 ns tpp CE HIGH to Power Down 40 55 ns tage Byte Enable Access Time 40 55 ns Write Cycle twe Write Cycle Time 40 55 ns tsce l CE LOW to Write End 30 45 ns taw Address Valid to Write End 30 45 ns Notes 27 Test conditions assume signal transition time of 3 ns or less timing reference levels of Vcc 2 input pulse levels of 0 to Vcc and output loading of the specified lo lon and 30 pF load capacitance _ a See 28 To access RAM CE L UB L SEM H To access semaphore CE H and SEM L Either condition must be valid for the entire tgcg time 29 At any given temperature and voltage condition for any given device tyzcg is less than t zce and tyzo is less than t zog 30 Test conditions used are Load 3 31 This parameter is guaranteed but not tested For information on port to port delay through RAM cells from writing port to reading port refer to Read Timing with Busy waveform Document 001 01638 Rev E Page 13 of 26 F
7. Description The CYDC256B16 CYDC128B16 CYDC064B16 CYDC128B08 CYDCO64B08 are low power CMOS 4k 8k 16k x 16 and 8 16k x 8 dual port static RAMs Arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data Two ports are provided permitting independent asynchronous access for reads and writes to any location in memory The devices can be utilized as standalone 16 bit dual port static RAMs or multiple devices can be combined in order to function as a 32 bit or wider master slave dual port static RAM An M S pin is provided for implementing 32 bit or wider memory appli cations without the need for separate master and slave devices or additional discrete logic Application areas include interprocessor multiprocessor designs communications status buffering and dual port video graphics memory Each port has independent control pins Chip Enable CE Read or Write Enable R W and Output Enable OE Two flags are provided on each port BUSY and INT BUSY signals that the port is trying to access the same location currently being accessed by the other port The Interrupt flag INT permits communication between ports or systems by means of a mail box The semaphores are used to pass a flag or token from one port to the other to indicate that a shared resource is in use The semaphore logic is comprised of eight shared latches Only one side can control the latch semaphore at
8. Device is continuously selected CE V _ and UB or LB V This waveform cannot be used for semaphore reads 38 OE ViL 39 Address valid prior to or coincident with CE transition LOW a 40 To access RAM CE V UB or LB Vj_ SEM Vj To access semaphore CE Vip SEM Vi 41 R W must be HIGH during all address transitions 2 Bel ees 42 A write occurs during the overlap tsce or tpye of a LOW CE or SEM and a LOW UB or LB Document 001 01638 Rev E Page 18 of 26 Feedback CYDC256B16 CYDC128B16 CYDC064B16 CYDC128B08 CYPRESS CYDC064B08 PERFORM Switching Waveforms continued Write Cycle No 1 R W Controlled Timing 4 42 43 44 45 46 ADDRESS ss 72 TIZZA taw 45 46 CE 46 R W lt thzwel LZWE DATA OUT NOTE 48 NOTE 48 tsp tHD SP Write Cycle No 2 CE Controlled Timing 1 42 43 48 twe ADDRESS 45 46 cE R W tsp tup Notes 43 ta is measured from the earlier of CE or R W or SEM or R W going HIGH at the end of write cycle 44 If OE is LOW during a R W controlled write cycle the write pulse width must be the larger of tpwe or tyzwe tsp to allow the I O drivers to turn off and data to be placed on the bus for the required tgp If OE is HIGH during an R W controlled write cycle this requirement does not apply and the write pulse can be as short as the specified tpywe 45 To access RAM CE V SEM Vin 46 To access upper byte
9. Side Sets INT two ADDRESS OK WRITE TFFE OR FFE XXX CER INTL ti T Left Side Clears INT POQQOOOOOOOODODOO ADDRESSR tac READ 1FFE OR 1 3FFE CEL Rm SSL K AXAOS INT tinRIoS Notes 55 ty depends on which enable pin CE or RW is deasserted first 56 ting OF tiyr depends on which enable pin CE or R W_ is asserted last Document 001 01638 Rev E Page 23 of 26 Feedback CYDC256B16 CYDC128B16 CYDC064B16 CYDC128B08 CYPRESS CYDC064B08 PERFORM Ordering Information 16k x16 1 8V Asynchronous Dual Port SRAM Speed Package Operating ns Ordering Code Name Package Type Range 40 CYDC256B16 40AXC AZOAB 100 pin Lead free TQFP Commercial 55 CYDC256B16 55AXC AZOAB 100 pin Lead free TQFP Commercial 55 CYDC256B16 55AXI AZOAB 100 pin Lead free TQFP Industrial 8k x16 1 8V Asynchronous Dual Port SRAM Speed Package Operating ns Ordering Code Name Package Type Range 40 CYDC128B16 40AXC AZOAB 100 pin Lead free TQFP Commercial 55 CYDC128B16 55AXC AZOAB 100 pin Lead free TQFP Commercial 55 CYDC128B16 55AXI AZOAB 100 pin Lead free TQFP Industrial 4k x16 1 8V Asynchronous Dual Port SRAM Speed Package Operating ns Ordering Code Name Package Type Range 40 CYDC064B16 40AXC AZOAB 100 pin Lead free TQFP Commercial 55 CYDC064B16 55AXC AZOAB 100 pin Lead free TQFP Commercial 55 CYDC064B16 55AXI AZOAB
10. any time Control of a semaphore indicates that a shared resource is in use An automatic power down feature is controlled independently on each port by a Chip Enable CE pin Document 001 01638 Rev E The CYDC256B 16 CYDC128B16 CYDC064B16 CYDC128B08 CYDC064B08 are available in 100 pin TQFP packages Power Supply The core voltage Vcc can be 1 8V 2 5V or 3 0V as long as it is lower than or equal to the I O voltage Each port can operate on independent I O voltages This is determined by what is connected to the VppioL and Vppior pins The supported I O standards are 1 8V 2 5V LVCMOS and 3 0V LVTTL Write Operation Data must be set up for a duration of tsp before the rising edge of R W in order to guarantee a valid write A write operation is controlled by either the R W pin see Write Cycle No 1 waveform or the CE pin see Write Cycle No 2 waveform Required inputs for non contention operations are summa rized in Table 1 If a location is being written to by one port and the opposite port attempts to read that location a port to port flowthrough delay must occur before the data is read on the output otherwise the data read is not deterministic Data will be valid on the port tppp after the data is presented on the other port Read Operation When reading the device the user must assert both the OE and CE pins Data will be available tace after CE or tpoe after OE is asserted If the user wishes to access a
11. 08 and Table 1 Non Contending Read Write CYDC256B16 CYDC128B16 CYDC064B16 CYDC128B08 CYDC064B08 CYDC128B08 consist of an array of 8k and 16k words of 8 each of dual port RAM cells I O and address lines and control signals CE OE R W These control pins permit independent access for reads or writes to any location in memory To handle simultaneous writes reads to the same location a BUSY pin is provided on each port Two Interrupt INT pins can be utilized for port to port communication Two Semaphore SEM control pins are used for allocating shared resources With the M S pin the devices can function as a master BUSY pins are outputs or as a slave BUSY pins are inputs The devices also have an automatic power down feature controlled by CE Each port is provided with its own output enable control OE which allows data to be read from the device Inputs Outputs CE R W OE UB LB SEM 1 0s VO45 1O 07 Operation H X X X X H High Z High Z Deselected Power down X X X H H H High Z High Z Deselected Power down L L X L H H Data In High Z Write to Upper Byte Only L L X H L H High Z Data In Write to Lower Byte Only L L X L L H Data In Data In Write to Both Bytes L H L L H H Data Out High Z Read Upper Byte Only L H L H L H High Z Data Out Read Lower Byte Only L H L L L H Data Out Data Out Read Bot
12. 100 pin Lead free TQFP Industrial 16k x8 1 8V Asynchronous Dual Port SRAM Speed Package Operating ns Ordering Code Name Package Type Range 40 CYDC128B08 40AXC AZOAB 100 pin Lead free TQFP Commercial 55 CYDC128B08 55AXC AZOAB 100 pin Lead free TQFP Commercial 55 CYDC128B08 55AXI AZOAB 100 pin Lead free TQFP Industrial 8k x8 1 8V Asynchronous Dual Port SRAM Speed Package Operating ns Ordering Code Name Package Type Range 40 CYDC064B08 40AXC AZOAB 100 pin Lead free TQFP Commercial 55 CYDC064B08 55AXC AZOAB 100 pin Lead free TQFP Commercial 55 CYDC064B08 55AXI AZOAB 100 pin Lead free TQFP Industrial Document 001 01638 Rev E Page 24 of 26 Feedback CYDC256B16 CYDC128B16 CYDC064B16 CYDC128B08 s CYPRESS CYDC064B08 PERFORM Package Diagram 100 Pin Thin Plastic Quad Flat Pack TQFP A100 AMHR 2 L Z oS ES EEFRRREHUPMUUTTTAT CUR 51 85048 C All products and company names mentioned in this document may be the trademarks of their respective holders Document 001 01638 Rev E Page 25 of 26 Cypress Semiconductor Corporation 2006 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life su
13. 31 32 33 34 35 36 37 48 49 50 aA a oF E S g EE b 9 fo N 8 g 8 8 8 pA N N gt v on a a gt ao gt a a gt gt Notes 8 IRR functionality is not supported for the CYDC128B08 device 9 This pin is A13L for CYDC128B08 devices 10 This pin is A13R for CYDC128B08 devices Document 001 01638 Rev E Page 4 of 26 Feedback CYPRESS PERFORM Pin Definitions CYDC256B16 CYDC128B16 CYDC064B16 CYDC128B08 CYDC064B08 Left Port Right Port Description CEL CER Chip Enable RW R Wrp Read Write Enable OEL OER Output Enable Aot A13L Aor A13R Address Ag A for 4k devices Ag A42 for 8k devices Ag A 3 for 16k devices 1 OoL l O15L 1 Oor l O15R Data Bus Input Output for x16 devices 1 Og l O7 for x8 devices SEM SEMR Semaphore Enable UBL UBR Upper Byte Select I Og I O 5 for x16 devices Not applicable for x8 devices LB LBR Lower Byte Select I O I O7 for x16 devices Not applicable for x8 devices INTL INTR Interrupt Flag BUSY BUSYp Busy Flag IRRO IRR1 Input Read Register for CYDC064B16 CYDC064B08 CYDC128B16 A13L A13R for CYDC256B16 and CYDC128B08 devices ODRO ODR4 Output Drive Register These outputs are Open Drain SFEN Special Function Enable M S Master or Slave Select Vec Core Power GND Ground VppDIOL Left Port I O Voltage VppIOR Right Port I O Voltage NC No Connect Leave this pin Unconnected Functional
14. 64B16 CYDC128B08 CYDC128B08 CYDC064B08 CYDC064B08 40 55 Pil O P21 0 Parameter Description Voltage Voltage Min Typ Max Min Typ Max Unit VoH Output HIGH Voltage lop 2 mA 2 5V any port 2 0 2 0 V Output HIGH Voltage lop 2 mA 3 0V any port 2 1 2 1 V VoL Output LOW Voltage Io 2 mA 2 5V any port 0 4 0 4 V Output LOW Voltage Io 2 mA 3 0V any port 0 4 0 4 V Vo ODR ODR Output LOW Voltage Io 8 mA 2 5V any port 0 2 0 2 V 3 0V any port 0 2 0 2 V Vin Input HIGH Voltage 2 5V any port 1 7 Vppio 1 7 Vopio V 0 3 0 3 3 0V any port 2 0 VppIo 2 0 VppIo V 0 2 0 2 VIL Input LOW Voltage 2 5V any port 0 3 0 6 0 3 0 6 V 3 0V any port 0 2 0 7 0 2 0 7 V loz Output Leakage Current 2 5V 2 5V 1 1 1 1 uA 3 0V 3 0V 1 1 1 1 pA lcexODR ODR Output Leakage Current 2 5V 2 5V 1 1 1 1 uA Vout Vcc 3 0v 3 0V 1 1 1 pA lix Input Leakage Current 2 5V 2 5V 1 1 1 1 uA 3 0V 3 0V 1 1 1 1 pA lcc Operating Current Vcc Max ind 2 5V 2 5V 39 55 28 40 mA lout 0 mA Outputs Disabled Isp4 Standby Current Both Ports TTL Ind 2 5V 2 5V 6 8 6 8 uA Level CE and CEr Vcc 0 2 SEM L SEMr Vcc 0 2 f fMAX Ispo Standby Current One Port TTL iInd 2 5V 2 5V 21 30 18 25 mA Level CEL CER 2 Vin f fax Isp3 Standby Current Both Ports Ind 2 5V 2 5V 4 6 4 6 uA CMOS Level CE amp CEp Vcc 0 2V SEM and SEMp gt Vcc 0 2V f 0 Ispa Stan
15. 8B16 CYDC064B16 CYDC128B08 CYDC064B08 provide on chip arbitration to resolve simultaneous memory location access contention If both ports CEs are asserted and an address match occurs within tps of each other the busy logic will determine which port has access If tps is violated one port will definitely gain permission to the location but it is not predictable which port will get that permission BUSY will be asserted tp after an address match or tg c after CE is taken LOW Master Slave A M S pin is provided in order to expand the word width by configuring the device as either a master or a slave The BUSY output of the master is connected to the BUSY input of the slave This will allow the device to interface to a master device with no external components Writing to slave devices must be delayed until after the BUSY input has settled tgLc or tga otherwise the slave chip may begin a write_cycle during a contention situation When tied HIGH the M S pin allows the device to be used as a master and therefore the BUSY line is an output BUSY can then be used to send the arbitration outcome to a slave Input Read Register The Input Read Register IRR captures the status of two external input devices that are connected to the Input Read pins The contents of the IRR read from address x0000 from either port During reads from the IRR DQO and DQ1 are valid bits and DQ lt 15 2 gt are don t care Writes to addres
16. 8B16 CYDC256B16 CYDC128B16 CYDC064B16 CYDC128B08 CYDC064B16 CYDC128B08 CYDC064B08 CYDC064B08 40 55 Port I O Voltages P1 P2 2 5V 2 5V 2 5V 2 5V Unit Maximum Access Time 40 55 ns Typical Operating Current 39 28 mA Typical Standby Current for Isp 6 6 uA Typical Standby Current for Isp3 4 4 uA Selection Guide for Vec 3 0V CYDC256B16 CYDC128B16 CYDC256B16 CYDC128B16 CYDC064B16 CYDC128B08 CYDC064B16 CYDC128B08 CYDC064B08 CYDC064B08 40 55 Port I O Voltages P1 P2 3 0V 3 0V 3 0V 3 0V Unit Maximum Access Time 40 55 ns Typical Operating Current 49 42 mA Typical Standby Current for Isp 7 7 uA Typical Standby Current for Isg3 uA 198 Champion Court San Jose CA 95134 1709 408 943 2600 Cypress Semiconductor Corporation Revised January 25 2007 Document 001 01638 Rev E Feedback CYDC256B16 CYDC128B16 CYDC064B16 CYDC128B08 CYPRESS CYDC064B08 PERFORM VO 15 0 NOt as UB UBR LB io 10 LB Control Control 16K X 16 Dual Ported Array Address Decode Address Decode A 13 0 A 13 0 CE Interrupt Mi 2 Arbitration Semaphore Input Read Register and Output Drive Register Figure 1 Top Level Block Diagram 2 Notes 1 Ag Ay for 4k devices Ag A42 for 8k devices Ag A43 for 16k devices 2 BUSY is an output in master mode and an input in slave mode Document 001 01638 Rev E Page 2 of 26
17. Description Min Max Min Max trawl 3 R W LOW to High Z 15 25 ns tizwel 31 R W HIGH to Low Z 0 0 ns twop 2 Write Pulse to Data Delay 55 80 ns topp Write Data Valid to Read Data Valid 55 80 ns Busy Timing tBLa BUSY LOW from Address Match 30 45 ns tBHA BUSY HIGH from Address Mismatch 30 45 ns tac BUSY LOW from CE LOW 30 45 ns tBHC BUSY HIGH from CE HIGH 30 45 ns tpg Port Set up for Priority 5 ns twe R W HIGH after BUSY Slave 0 ns twH R W HIGH after BUSY HIGH Slave 20 35 ns tepp BUSY HIGH to Data Valid 30 40 ns Interrupt Timing tins INT Set Time 35 45 ns tine INT Reset Time 35 45 ns Semaphore Timing tsop SEM Flag Update Pulse OE or SEM 10 15 ns tswRD SEM Flag Write to Read Time 10 10 ns tsps SEM Flag Contention Window 10 10 ns tsaa SEM Address Access Time 40 55 ns Document 001 01638 Rev E Page 17 of 26 Feedback CYDC256B16 CYDC128B16 ie CYDC064B16 CYDC128B08 i CYPRESS CYDC064B08 PERFORM Uns Switching Waveforms Read Cycle No 1 Either Port Address Access 37 38 ADDRESS DATA OUT PREVIOUS DATAVALID Kx xX gt Read Cycle No 2 Either Port CE OE Access 6 39 40 DATA VALID _CE and LB or UB AF ese LLLLLLLLY DATA OUT RMN A DATA VALID loc CURRENT SB Read Cycle No 3 Either Port 3 38 41 42 tac ADDRESS UB or LB DATA OUT Looe Notes _ 36 R W is HIGH for read cycles __ oa as 37
18. Ps p6 CYDC256B16 CYDC128B16 CYDC064B16 CYDC128B08 CYDC064B08 1 8V 4k 8k 16k x 16 and 8k 16k x 8 ConsuMoBL Dual Port Static RAM Features Lead Pb free 14 x 14 x 1 4 mm 100 pin TQFP Package PERFORM e Full h ti True dual ported memory cells which allow simulta Te oem rag ad pee a neous access of the same memory location e 4 8 16k x 16 and 8 16k x 8 organization e Pin select for Master or Slave Expandable data bus to 32 bits with Master Slave chip select when using more than one device e High speed access 40 ns e On chip arbitration logic e Ultra Low operating power On chip semaphore logic Active Icc 15 mA typical at 55 ns Active lcc 25 mA typical at 40 ns Standby Isp3 2 pA typical e Port independent 1 8V 2 5V and 3 0V I Os INT flag for port to port communication Separate upper byte and lower byte control Input Read Registers and Output Drive Registers e Commercial and industrial temperature ranges Selection Guide for Vcc 1 8V CYDC256B16 CYDC128B16 CYDC256B16 CYDC128B16 CYDC064B16 CYDC128B08 CYDC064B16 CYDC128B08 CYDC064B08 CYDC064B08 40 55 Port I O Voltages P1 P2 1 8V 1 8V 1 8V 1 8V Unit Maximum Access Time 40 55 ns Typical Operating Current 25 15 mA Typical Standby Current for Isp 2 2 uA Typical Standby Current for Isp3 2 2 uA Selection Guide for Vcc 2 5V CYDC256B16 CYDC12
19. a 8l Address Set up to Write Start ns tpwe Write Pulse Width 25 40 ns tsp Data Set up to Write End 20 30 ns tub Data Hold From Write End 0 0 ns tyzwel 31 R W LOW to High Z 15 25 ns trzwel 311 R W HIGH to Low Z 0 0 ns twop Write Pulse to Data Delay 55 80 ns topp Write Data Valid to Read Data Valid 55 80 ns Busy Timing tBLa BUSY LOW from Address Match 30 45 ns iBHA BUSY HIGH from Address Mismatch 30 45 ns tac BUSY LOW from CE LOW 30 45 ns tBHC BUSY HIGH from CE HIGH 30 45 ns tpg Port Set up for Priority 5 ns twe R W HIGH after BUSY Slave ns twH R W HIGH after BUSY HIGH Slave 20 35 ns tepp BUSY HIGH to Data Valid 30 40 ns Document 001 01638 Rev E Page 15 of 26 CYDC256B16 CYDC128B16 CYDC064B16 CYDC128B08 CYPRESS CYDC064B08 PERFORM Switching Characteristics for Voc 2 5V Over the Operating Range continued CYDC256B16 CYDC256B16 CYDC128B16 CYDC128B16 CYDC064B16 CYDC064B16 CYDC128B08 CYDC128B08 CYDC064B08 CYDC064B08 40 55 Parameter Description Min Max Min Max Unit Interrupt Timing tins INT Set Time 35 45 ns tinR INT Reset Time 35 45 ns Semaphore Timing tsop SEM Flag Update Pulse OE or SEM 10 15 ns tswRD SEM Flag Write to Read Time 10 10 ns tsps SEM Flag Contention Window 10 10 ns tsaa SEM Address Access Time 40 55 ns Switching Character
20. ble 4 Output Drive Register 20 SFEN CE R W OE UB LB ADDR 1 0 04 VO5V045 Mode L H x21 Lt7 L17 x0000 Max VALID 7 VALID 7 Standard Memory Access L L x x L x0001 VALID 8 X ODR Writel 0 221 L H L X L x0001 VALIDIS X ODR Read Table 5 Semaphore Operation Example Function I Og O45 Left 1 0 0145 Right Status No action 1 1 Semaphore free Left port writes 0 to semaphore 0 1 Left Port has semaphore token Right port writes 0 to semaphore 0 1 No change Right side has no write access to semaphore Left port writes 1 to semaphore 1 0 Right port obtains semaphore token Left port writes 0 to semaphore 1 0 No change Left port has no write access to semaphore Right port writes 1 to semaphore 0 1 Left port obtains semaphore token Left port writes 1 to semaphore 1 1 Semaphore free Right port writes 0 to semaphore 1 0 Right port has semaphore token Right port writes 1 to semaphore 1 1 Semaphore free Left port writes 0 to semaphore 0 1 Left port has semaphore token Left port writes 1 to semaphore 1 1 Semaphore free Notes 16 SFEN Vi for IRR reads 17 UB or LB V If LB Vi then DQ lt 7 0 gt are valid If UB Vi then DQ lt 15 8 gt are valid 18 LB must be active LB V for these bits to be valid a 19 SFEN active when either CE V _ or CER Via It is inactive when CE CER Vip 20 SFEN V for ODR reads and writes 21 Output enable must be low OE VL during reads for valid data to b
21. dby Current One Port CMOS Ind 2 5V 2 5V 21 30 18 25 mA Level CE CER gt Vin f faa Document 001 01638 Rev E Page 11 of 26 Feedback CYDC256B16 CYDC128B16 CYDC064B16 CYDC128B08 CYPRESS CYDC064B08 PERFORM Electrical Characteristics for 3 0V Over the Operating Range CYDC256B16 CYDC256B16 CYDC128B16 CYDC128B16 CYDC064B16 CYDC064B16 CYDC128B08 CYDC128B08 CYDC064B08 CYDC064B08 40 55 P11 0 P21 O Parameter Description Voltage Voltage Min Typ Max Min Typ Max Unit VoH Output HIGH Voltage lop 2 mA 3 0V any port 2 1 2 1 V VoL Output LOW Voltage Io 2 mA 3 0V any port 0 4 0 4 V Vo ODR ODR Output LOW Voltage Io 8 mA 3 0V any port 0 2 0 2 V Vin Input HIGH Voltage 3 0V any port 2 0 Vppio 2 0 Vppio V 0 2 0 2 VIL Input LOW Voltage 3 0V any port 0 2 0 7 0 2 0 7 V loz Output Leakage Current 3 0V 3 0V 1 1 1 1 LA Icex ODR ODR Output Leakage Current 3 0V 3 0V 1 1 1 1 pA Vout Vcc lix Input Leakage Current 3 0V 3 0V 1 1 1 1 uA lcc Operating Current Vcc Max _ Ind 3 0V 3 0V 49 70 42 60 mA lout 0 mA Outputs Disabled Ispi Standby Current Both Ports TTL Ind 3 0V 3 0V 7 10 7 10 uA Level CE and CER Vcc 0 2 SEM SEMpr Vcc 0 2 f fMAX Ispo Standby Current One Port TTL Ind
22. e output 22 During ODR writes data will also be written to the memory Document 001 01638 Rev E Page 8 of 26 Feedback CYPRESS PERFORM Maximum Ratings Above which the useful life may be impaired For user guide lines not tested REAA 65 C to 150 C Ambient Temperature with Storage Temperature CYDC256B16 CYDC128B16 CYDC064B16 CYDC128B08 CYDC064B08 Output Current into Outputs LOW eee 90 mA Static Discharge Voltage cceeeeeeeeeteeeeeetees gt 2000V Latch up Current c ccccccceeceeeeeeeeeeeeeeeeeeeeeeeees gt 200 mA Operating Range Power Appli d eccccccccccsscsesessssssssssssssesssseeeee 55 C to 125 C Tange AMn ENPA Vcc Supply Voltage to Ground Potential 0 5V to 3 3V Commercial OAOE Lan ne m DC Voltage Applied to 3 0V 300 mV Outputs in High Z State 0 5V to Vcc 0 5V Industrial 40 C to 85 C 1 8V 100 mV DC Input Voltage oo cecceseeeeeeeaee 0 5V to Vec 0 5V 2 5V 100 mV 3 0V 300 mV Electrical Characteristics for Voc 1 8V Over the Operating Range CYDC256B16 CYDC256B16 CYDC128B16 CYDC128B16 CYDC064B16 CYDC064B16 CYDC128B08 CYDC128B08 CYDC064B08 CYDC064B08 40 55 Pil 0 P21 0 Parameter Description Voltage Voltage Min Typ Max Min Typ Max Unit VoH Output HIGH Voltage lo
23. eedback CYDC256B16 CYDC128B16 CYDC064B16 CYDC128B08 CYPRESS CYDC064B08 PERFORM Switching Characteristics for Voc 1 8V Over the Operating Range continued CYDC256B16 CYDC256B16 CYDC128B16 CYDC128B16 CYDC064B16 CYDC064B16 CYDC128B08 CYDC128B08 CYDC064B08 CYDC064B08 40 55 Parameter Description Min Max Min Max Unit tha Address Hold From Write End 0 0 ns tgpl26l Address Set up to Write Start 0 0 ns tpwe Write Pulse Width 25 40 ns tsp Data Set up to Write End 20 30 ns tub Data Hold From Write End 0 0 ns tuzwe_el 31 R W LOW to High Z 15 25 ns trzwel 31 R W HIGH to Low Z 0 0 ns twop 2 Write Pulse to Data Delay 55 80 ns tppp 2 Write Data Valid to Read Data Valid 55 80 ns Busy Timing tBLa BUSY LOW from Address Match 30 45 ns BHA BUSY HIGH from Address Mismatch 30 45 ns tic BUSY LOW from CE LOW 30 45 ns tsHc BUSY HIGH from CE HIGH 30 45 ns tpg Port Set up for Priority 5 ns twe R W HIGH after BUSY Slave ns twa R W HIGH after BUSY HIGH Slave 20 35 ns tepp BUSY HIGH to Data Valid 30 40 ns Interrupt Timing tins INT Set Time 35 45 ns tinR INT Reset Time 35 45 ns Semaphore Timing tsop SEM Flag Update Pulse OE or SEM 10 15 ns tswRD SEM Flag Write to Read Time 10 10 ns tsps SEM Flag Contention Window 10 10 ns tsaa SEM Address Access Time 40 55 ns Notes 32 For information on po
24. g Diagram of Read with BUSY M S HIGH 2 twc ADDRESSR MATCH R iWrp tHD VALID gt ADDRESS DATA INR OD tBHA BUSY teb tppp DATAgutL VALID twop Write Timing with Busy Input M S LOW tpwe _ lt lt twB twH BUSY Note __ 53 CE CER LOW Document 001 01638 Rev E Page 21 of 26 Feedback CYDC256B16 CYDC128B16 gt CYDC064B16 CYDC128B08 CYPRESS CYDC064B08 PERFORM Switching Waveforms continued Busy Timing Diagram No 1 CE Arbitration CE Valid First ADDRESS R ADDRESS MATCH BUSYp CEp Valid First ADDRESS _R ADDRESS MATCH BUSY Busy Timing Diagram No 2 Address Arbitration Left Address Valid First trc or twe ADDRESS ADDRESS MATCH ADDRESS MISMATCH ADDRESSpR BUSYR Right Address Valid First ADDRESSp ADDRESS BUSY Note 54 If tpg is violated the busy signal will be asserted on one side or the other but there is no guarantee to which side BUSY will be asserted Document 001 01638 Rev E Page 22 of 26 Feedback CYDC256B16 CYDC128B16 z CYDC064B16 CYDC128B08 s CYPRESS CYDC064B08 Switching Waveforms continued Interrupt Timing Diagrams Left Side Sets INTp two gt ADDRESS OR 1 3FFF C merom KOK CE INTR Right Side Clears INTR tac ADDRESS XX XQ OOO DQ XXK wiser A CER tinr l wie ZZ LDR Oe AASS INTR Right
25. h Bytes X X H X X X High Z High Z Outputs Disabled H H L X X L Data Out Data Out Read Data in Semaphore Flag X H L H H L Data Out Data Out Read Data in Semaphore Flag H i X X X L Data In Data In Write Diyo into Semaphore Flag X i X H H L Data In Data In Write Diyo into Semaphore Flag L X X L X L Not Allowed L X X X L L Not Allowed Table 2 Interrupt Operation Example Assumes BUSY BUSYp HIGH 21 Left Port Right Port Function RW CE OEL AoL 13L INT RR CER OER Aor 13R INTR Set Right INTp Flag L L x 3FFFIS x xX x X x Lt 4 Reset Right INT Flag x x x x x x L L 3FFFI 5 HI13 Set Left INT Flag x x x x Lee L L x 3FFE SI x Reset Left INT Flag x L L 3FFE 5l HIA x x xX x xX Notes 11 This column applies to x16 devices only 12 See Interrupts Functional Description for specific highest memory locations by device 13 If BUSYR L then no change 14 If BUSY L then no change 15 See Functional Description for specific addresses by device Document 001 01638 Rev E Page 7 of 26 CYPRESS PERFORM Table 3 Input Read Register Operation 19 CYDC256B16 CYDC128B16 CYDC064B16 CYDC128B08 CYDC064B08 SFEN CE R W OE UB LB ADDR 0 0 OVO45 Mode H L H L L L x0000 Max VALID 71 VALIDI Standard Memory Access L L H L x0000 VALIDI xX IRR Read Ta
26. istics for Voc 3 0V Over the Operating Range CYDC256B16 CYDC256B16 CYDC128B16 CYDC128B16 CYDC064B16 CYDC064B16 CYDC128B08 CYDC128B08 CYDC064B08 CYDC064B08 Unit 40 55 Parameter Description Min Max Min Max Read Cycle tro Read Cycle Time 40 55 ns taa Address to Data Valid 40 55 ns toHA Output Hold From Address Change 5 5 ns tace CE LOW to Data Valid 40 55 ns tDoE OE LOW to Data Valid 25 30 ns tLzog 22 30 31 OE Low to Low Z 1 1 ns ee 30 31 OE HIGH to High Z 15 15 ns tLzcg 30 31 CE LOW to Low Z 1 1 ns tise 9 311 CE HIGH to High Z 15 15 ns tpu CE LOW to Power Up 0 0 ns tpp CE HIGH to Power Down 40 55 ns tage Byte Enable Access Time 40 55 ns Write Cycle twe Write Cycle Time 40 55 ns tsce l CE LOW to Write End 30 45 ns taw Address Valid to Write End 30 45 ns tua Address Hold From Write End ns tsa l Address Set up to Write Start ns tpwe Write Pulse Width 25 40 ns tsp Data Set up to Write End 20 30 ns tub Data Hold From Write End 0 0 ns Document 001 01638 Rev E Page 16 of 26 Feedback CYDC256B16 CYDC128B16 CYDC064B16 CYDC128B08 CYPRESS CYDC064B08 PERFORM Switching Characteristics for Voc 3 0V Over the Operating Range continued CYDC256B16 CYDC256B16 CYDC128B16 CYDC128B16 CYDC064B16 CYDC064B16 CYDC128B08 CYDC128B08 CYDC064B08 CYDC064B08 Unit 40 55 Parameter
27. pport life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Feedback CYPRESS PERFORM Document History Page CYDC256B16 CYDC128B16 CYDC064B16 CYDC128B08 CYDC064B08 Document Title CYDC256B16 CYDC128B16 CYDC064B16 CYDC128B08 CYDC064B08 1 8V 4k 8k 16k x 16 and 8k 16k x 8 ConsuMoBL Dual Port Static RAM Document Number 001 01638 Orig of REV ECN NO Issue Date Change Description of Change i 385185 SEE ECN YDT New data sheet A 396697 SEE ECN KGH Updated ISB2 and ISB4 typo to mA Updated tINS and tINR for 55 to 31ns B 404777 SEE ECN KGH Updated lop and lo values for the 1 8V 2 5V and 3 0V parameters Vop and VoL Replaced 35 speed bin with 40 Updated Switching Characteristics for Voc 2 5V and Vec 3 0V Included note 34 C 463014 SEE ECN HKH Changed spec title to from Consumer Dual Port to ConsuMoBL Dual Port Cypress Internet Release D 505803 SEE ECN HKH Corrected typo in Features and Ordering Info sections Cy
28. press external web release E 735537 SEE ECN HKH Corrected typo in Pg5 power supply section Updated tDDD timing value to be consistent with tWDD Document 001 01638 Rev E Page 26 of 26 Feedback
29. r reading a semaphore the other address pins have no effect When writing to the semaphore only I Og is used If a zero is written to the left port of an available semaphore a one will appear at the same semaphore address on the right port That semaphore can now only be modified by the side showing zero the left port in this case If the left port now relinquishes control by writing a one to the semaphore the semaphore will be set to one for both sides However if the right port had requested the semaphore written a zero while the left port had control the right port would immediately own the semaphore as soon as the left port released it Table 5 shows sample semaphore operations Page 6 of 26 Feedback CYPRESS PERFORM When reading a semaphore all sixteen eight data lines output the semaphore value The read value is latched in an output register to prevent the semaphore from changing state during a write from the other port If both ports attempt to access the semaphore within tsps of each other the semaphore will definitely be obtained by one side or the other but there is no guarantee which side will control the semaphore On power up both ports should write 1 to all eight semaphores Architecture The CYDC256B 16 CYDC128B16 CYDC064B 16 CYDC128B08 CYDC064B08 consist of an array of 4k 8k or 16k words of 16 dual port RAM cells I O and address lines and control signals CE OE R W The CYDC064B
30. rt to port delay through RAM cells from writing port 33 Test conditions used are Load 2 34 Add 2ns to this value when the I O ports are operating at different voltages 35 tgpp is a calculated parameter and is the greater of twpp tpwe actual or tppp tsp actual Document 001 01638 Rev E to reading port refer to Read Timing with Busy waveform Page 14 of 26 Feedback CYDC256B16 CYDC128B16 CYDC064B16 CYDC128B08 CYPRESS CYDC064B08 PERFORM Switching Characteristics for Voc 2 5V Over the Operating Range CYDC256B16 CYDC256B16 CYDC128B16 CYDC128B16 CYDC064B16 CYDC064B16 CYDC128B08 CYDC128B08 CYDC064B08 CYDC064B08 40 55 Parameter Description Min Max Min Max Unit Read Cycle tre Read Cycle Time 40 55 ns taa Address to Data Valid 40 55 ns toHa Output Hold From Address Change 5 5 ns tace CE LOW to Data Valid 40 55 ns DOE OE LOW to Data Valid 25 30 ns tLzoef 30 31 OE Low to Low Z 2 2 ns tuzog 30 311 OE HIGH to High Z 15 15 ns tLzcg 30 311 CE LOW to Low Z 2 2 ns tuzc 22 30 31 CE HIGH to High Z 15 15 ns tpu CE LOW to Power Up 0 0 ns tep CE HIGH to Power Down 40 55 ns tage Byte Enable Access Time 40 55 ns Write Cycle twe Write Cycle Time 40 55 ns tsce l CE LOW to Write End 30 45 ns taw Address Valid to Write End 30 45 ns tha Address Hold From Write End ns ts
31. s x0000 are not allowed from either port Address x0000 is not available for standard memory accesses when SFEN Vi When SFEN Vip address x0000 is available for memory accesses Document 001 01638 Rev E CYDC256B16 CYDC128B16 CYDC064B16 CYDC128B08 CYDC064B08 The inputs will be 1 8V 2 5V LVCMOS or 3 0V LVTTL depending on the core voltage supply Vcc Refer to Table 3 for Input Read Register operation IRR is not available in the CYDC256B16 and CYDC128B08 as the IRR pins are used as extra address pins Aj3 and Ay3p Output Drive Register The Output Drive Register ODR determines the state of up to five external binary state devices by providing a path to Vss for the external circuit These outputs are Open Drain The five external devices can operate at different voltages 1 5V lt Vppio lt 3 5V but the combined current cannot exceed 40 mA 8 mA max for each external device The status of the ODR bits are set using standard write accesses from either port to address x0001 with a 1 corresponding to on and 0 corresponding to off The status of the ODR bits can be read with a standard read access to address x0001 When SFEN V the ODR is active and address x0001 is not available for memory accesses When SFEN Vip the ODR is inactive and address x0001 can be used for standard accesses During reads and writes to ODR DQ lt 4 0 gt are valid and DQ lt 15 5 gt are don t care Refer
32. semaphore flag Page 5 of 26 Feedback CYPRESS PERFORM then the SEM pin must be asserted instead of the CE pin and OE must also be asserted Interrupts The upper two memory locations may be used for message passing The highest memory location FFF for the CYDC064B16 1FFF for the CYDC128B16 and CYDC064B08 3FFF for the CYDC256B16 and CYDC128B08 is the mailbox for the right port and the second highest memory location FFE for the CYDC064B16 1FFE for the CYDC128B16 and CYDC064B08 3FFE for the CYDC256B16 and CYDC128B08 is the mailbox for the left port When one port writes to the other port s mailbox an interrupt is generated to the owner The interrupt is reset when the owner reads the contents of the mailbox The message is user defined Each port can read the other port s mailbox without resetting the interrupt The active state of the busy signal to a port prevents the port from setting the interrupt to the winning port Also an active busy to a port prevents that port from reading its own mailbox and thus resetting the interrupt to it If an application does not require message passing do not connect the interrupt pin to the processor s interrupt request input pin On power up an initialization program should be run and the interrupts for both ports must be read to reset them The operation of the interrupts and their interaction with Busy are summarized in Table 2 Busy The CYDC256B16 CYDC12
33. to Table 4 for Output Drive Register operation Semaphore Operation The CYDC256B16 CYDC128B16 CYDC064B16 CYDC128B08 CYDC064B08 provide eight semaphore latches which are separate from the dual port memory locations Semaphores are used to reserve resources that are shared between the two ports The state of the semaphore indicates that a resource is in use For example if the left port wants to request a given resource it sets a latch by writing a zero to a semaphore location The left port then verifies its success in setting the latch by reading it After writing to the semaphore SEM or OE must be deasserted for tsop before attempting to read the semaphore The semaphore value will be available tswrp tpoe after the rising edge of the semaphore write If the left port was successful reads a zero it assumes control of the shared resource otherwise reads a one it assumes the right port has control and continues to poll the semaphore When the right side has relinquished control of the semaphore by writing a one the left side will succeed in gaining control of the semaphore If the left side no longer requires the semaphore a one is written to cancel its request Semaphores are accessed by asserting SEM LOW The SEM pin functions as a chip select for the semaphore latches CE must remain HIGH during SEM LOW Ap_ represents the semaphore address OE and R W are used in the same manner as a normal memory access When writing o

Cypress CYDC064B16 User's Manual

Contents

Download Pdf Manuals

Related Search

Related Contents