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Cypress CY8CNP102B User's Manual

1. Symbol Description Min Typ Max Units Notes Vcc Supply Voltage 3 00 3 6 V Ipp Supply Current 36 40 mA Ta 25 C CPU 3 MHz SYSCLK doubler disabled VC1 1 5 MHz VC2 93 75 kHz VC3 0 366 kHz continuous nvSRAM access Ippp Supply current when IMO 6 MHz a 27 28 mA Ta 25 C CPU 0 75 MHz using SLIMO mode SYSCLK doubler disabled VC1 0 375 MHz VC2 23 44 kHz VC3 0 09 kHz continuous nvSRAM access Isp Sleep Mode Current with POR LVD 5 mA nvSRAM in standby Sleep Timer WDT and internal slow oscillator active VREF Reference Voltage Bandgap 1 28 1 3 1 32 V Trimmed for appropriate Vcc Veap Storage Capacitor between Vcap and 61 68 82 uF 5V rated minimum Vss DC General Purpose IO Specifications Table 6 3 3V DC GPIO Specifications CY8CNP102B Symbol Description Min Typ Max Units Notes Rpy Pull up Resistor 4 5 6 8 KQ Rpp Pull down Resistor 4 5 6 8 KQ VoH High Output Level Vcc 1 0 V IOH 10 mA Vcc 3 0 to 3 6V 8 total loads 4 on even port pins for example PO 2 P1 4 4 on odd port pins for example PO 3 P1 5 80 mA maximum combined IOH budget VoL Low Output Level 7 0 75 V IOL 25 mA Vcc 3 0 to 3 6V 8 total loads 4 on even port pins for example PO 2 P1 4 4 on odd port pins for example PO 3 P1 5 150 mA maximum combined IOL budget ViL Input Low Level 0 8 V Vcc 3 0 to 3 6 Vin Input High Level 1 6 V Vcc 3 0 to 3 6 Vu Inp
2. Page 8 of 38 Feedback 7 CYPRESS PRELIMINARY CY8CNP102B CY8CNP102E PERFORM The last step in the development process takes place inside the PSoC Designers Debugger subsystem The Debugger downloads the HEX image to the In Circuit Emulator ICE where it runs at full speed The Debugger capabilities rival those of systems costing much more In addition to traditional single step run to breakpoint and watch variable features the Debugger provides a large trace buffer enabling you to define complex breakpoint events that include monitoring address and data bus values memory locations and external signals Electrical Specifications Cypress nvSRAM user Module The nvSRAM user module is integrated with the PSoC Designer tool and contains APIs that facilitate nvSRAM access and control The user module provides high level access to the nvSRAM without user developed code The user module API also provides the ability to read and write arbitrary data struc tures to or from the nvSRAM and initiate nvSRAM Store or Recall operations This section lists the PSoC NV device DC and AC electrical specifications Specifications are valid for 40 C lt T lt 85 C and Tj lt 100 C except where noted Refer Table 14 on page 17 for electrical specifications on the Internal Main Oscillator IMO using SLIMO mode Figure 4 Voltage versus CPU Frequency A 5 25 Operating Region CY8CNP
3. are nvSRAM 7 Parameter Description Unit Min Max tuRECALL Power Up RECALL Duration 20 ms tsTORE STORE Cycle Duration 12 5 ms VswitcH Low Voltage Trigger Level 4 4 V tVccRISE VCC Rise Time 150 us AC General Purpose IO Specifications Table 35 5V AC GPIO Specifications CY8CNP102E Symbol Description Min Typ Max Units Notes Fepio GPIO Operating Frequency 0 12 3 MHz Normal Strong Mode TRiseF Rise Time Normal Strong Mode Cload 50 pF 3 18 ns Vcc 4 75V to 5 25V 10 90 TFallF Fall Time Normal Strong Mode Cload 50 pF 2 18 ns Vcc 4 75V to 5 25V 10 90 Figure 7 GPIO Timing Diagram 90 GPIO Pin Output Voltage 10 TFallF TRiseS TFallS ER sa tps att reel pea t Document 001 43991 Rev D Page 29 of 38 Feedback PERFORM AC Operational Amplifier Specifications Settling times slew rates and gain bandwidth are based on the Analog Continuous Time PSoC block Table 36 5V AC Operational Amplifier Specifications CY8CNP102E PRELIMINARY CY8CNP102B CY8CNP102E Symbol Description Min Typ Max Units TROA Rising Settling Time to 0 1 for a 1V Step 10 pF load Unity Gain Power Low Opamp Bias Low 3 9 us Power Medium Opamp Bias High 0 72 us Power High Opamp Bias High 0 62 us Tson Falling Settling Time to 0 1 for a 1V Step 10 pF load Unity Gain
4. MHz BW og Large Signal Bandwidth 1Vpp 3dB BW 100pF Load Power Low 200 kHz Power High 200 kHz Document 001 43991 Rev D Page 20 of 38 Feedback 7 CYPRESS PRELIMINARY CY8CNP102B CY8CNP102E PERFORM AC Programming Specifications Table 20 3 3V AC Programming Specifications CY8CNP102B Symbol Description Min Typ Max Units Notes TRSCLK Rise Time of SCLK 1 20 ns TFscLK Fall Time of SCLK 1 20 ns TsscLK Data Set up Time to Falling Edge of SCLK 40 ns THSCLK Data Hold Time from Falling Edge of SCLK 40 ns FscLK Frequency of SCLK 0 8 MHz TERASEB Flash Erase Time Block 10 ms TwrITE Flash Block Write Time 10 ms Tpsc_k3 Data Out Delay from Falling Edge of SCLK 50 ns 3 0V lt Vcc lt 3 6V AC IC Specifications Table 21 3 3V AC Characteristics of the I7C SDA and SCL Pins CY8CNP102B ae Standard Mode Fast Mode Symbol Description Units Min Max Min Max Fscii2c SCL Clock Frequency 0 100 0 400 kHz THDSTAI2C Hold Time repeated START Condition After this period the 4 0 0 6 us first clock pulse is generated TLowizc LOW Period of the SCL Clock 4 7 1 3 us THIGHI2C HIGH Period of the SCL Clock 4 0 0 6 us TSUSTAI2C Setup Time for a Repeated START Condition 4 7 0 6 us Tuppatizc Data Hold Time 0 0 us Tsupatzc Data Setup Time 25
5. Power Low Opamp Bias Low 5 9 us Power Medium Opamp Bias High 0 92 us Power High Opamp Bias High 0 72 us SRroa Rising Slew Rate 20 to 80 of a 1V Step 10 pF load Unity Gain Power Low Opamp Bias Low 0 15 V us Power Medium Opamp Bias High 1 7 V us Power High Opamp Bias High 6 5 V s SRFoa Falling Slew Rate 20 to 80 of a 1V Step 10 pF load Unity Gain Power Low Opamp Bias Low 0 01 V us Power Medium Opamp Bias High 0 5 V us Power High Opamp Bias High 4 0 V s BWoa Gain Bandwidth Product Power Low Opamp Bias Low 0 75 MHz Power Medium Opamp Bias High 3 1 MHz Power High Opamp Bias High 5 4 MHz ENoA Noise at 1 kHz Power Medium Opamp Bias High 100 nV rt Hz AC Digital Block Specifications Table 37 5V AC Digital Block Specifications CY8CNP102E Function Description Min Typ Max Units Notes All Maximum Block Clocking Frequency 49 2 MHz 4 75V lt Vcc lt 5 25V Functions Timer Capture Pulse Width 50 8 ns Maximum Frequency No Capture 49 2 MHz 4 75V lt Vcc lt 5 25V Maximum Frequency With Capture 24 6 MHz 4 75V lt Vcc lt 5 25V Counter Enable Pulse Width 50 8 ns Maximum Frequency No Enable Input 49 2 MHz 4 75V lt Vcc lt 5 25V Maximum Frequency Enable Input 24 6 MHz 4 75V lt Vcc lt 5 25V Dead Band Kill Pulse Width Asynchronous Restart Mode 20 ns Synchronous R
6. Slow Strong Mode Cload 50 pF 10 27 ns Vcc 3V to 3 6V 10 90 TFallS Fall Time Slow Strong Mode Cload 50 pF 10 22 ns Vcc 3V to 3 6V 10 90 90 Figure 6 GPIO Timing Diagram GPIO Pin Output Voltage 10 Document 001 43991 Rev D de oe ae t TFallF TFalls Page 18 of 38 Feedback PERFORM AC Operational Amplifier Specifications Settling times slew rates and gain bandwidth are based on the Analog Continuous Time PSoC block Table 17 3 3V AC Operational Amplifier Specifications CY8CNP102B PRELIMINARY CY8CNP102B CY8CNP102E Symbol Description Min Typ Max Units Notes TROA Rising Settling Time to 0 1 of a 1V Step Power High and 10 pF load Unity Gain Opamp Bias High is Power Low Opamp Bias Low 3 92 us oo at Power Medium Opamp Bias High 0 72 us Tsoa Falling Settling Time to 0 1 of a 1V Step 10 pF load Unity Gain Power Low Opamp Bias Low 5 41 us Power Medium Opamp Bias High 0 72 us SRroa Rising Slew Rate 20 to 80 of a 1V Step 10 pF load Unity Gain Power Low Opamp Bias Low 0 31 V us Power Medium Opamp Bias High 2 7 V s SReoa Falling Slew Rate 20 to 80 of a 1V Step 10 pF load Unity Gain Power Low Opamp Bias Low 0 24 V s Power Medium Opamp Bias High 1 8
7. V us BWoa Gain Bandwidth Product Power Low Opamp Bias Low 0 67 MHz Power Medium Opamp Bias High 2 8 MHz Enoa Noise at 1 kHz 100 nV rt Hz Power Medium Opamp Bias High AC Digital Block Specifications Table 18 3 3V AC Digital Block Specifications CY8CNP102B Function Description Min Typ Max Units Notes All Functions Maximum Block Clocking Frequency 24 6 MHz 3 0V lt Vcc lt 3 6V Timer Capture Pulse Width 5018 ns Maximum Frequency No Capture 24 6 MHz 3 0V lt Vcc lt 3 6V Maximum Frequency With Capture 24 6 MHz 3 0V lt Vcc lt 3 6V Counter Enable Pulse Width 508 ns Maximum Frequency No Enable Input 24 6 MHz 3 0V lt Vcc lt 3 6V Maximum Frequency Enable Input 24 6 MHz 3 0V lt Vcc lt 3 6V Dead Band Kill Pulse Width Asynchronous Restart Mode 20 ns Synchronous Restart Mode 50 8 ns Disable Mode 508 ns Maximum Frequency 24 6 MHz 3 0V lt Vcc lt 3 6V Note 8 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz 42 ns nominal period Document 001 43991 Rev D Page 19 of 38 Feedback PERFORM Table 18 3 3V AC Digital Block Specifications CY8CNP102B continued PRELIMINARY CY8CNP102B CY8CNP102E Function Description Min Typ Max Units Notes CRCPRS Maximum Input Clock Frequency
8. 24 6 MHz 3 0V lt Vcc lt 3 6V PRS Mode CRCPRS Maximum Input Clock Frequency 24 6 MHz 3 0V lt Vcc lt 3 6V CRC Mode SPIM Maximum Input Clock Frequency 8 2 MHz Maximum data rate at 4 1 MHz due to 2 x over clocking SPIS Maximum Input Clock Frequency 4 1 ns Width of SS_ Negated Between Transmissions 50 8 ns Transmitter Maximum Input Clock Frequency 24 6 MHz Maximum data rate at Vcc 3 0V 2 Stop Bits 3 08 MHz due to 8 x over clocking 49 2 MHz Maximum data rate at 6 15 MHz due to 8 x over clocking Receiver Maximum Input Clock Frequency 24 6 MHz Maximum data rate at 3 08 MHz due to 8 x over clocking Vcc gt 3 0V 2 Stop Bits 49 2 MHz Maximum data rate at 6 15 MHz due to 8 x over clocking AC Analog Output Buffer Specifications Table 19 3 3V AC Analog Output Buffer Specifications CY8CNP102B Symbol Description Min Typ Max Units TROB Rising Settling Time to 0 1 1V Step 100pF Load Power Low 4 7 us Power High 4 7 us TsoB Falling Settling Time to 0 1 1V Step 100pF Load Power Low 4 us Power High 4 us SRRoB Rising Slew Rate 20 to 80 1V Step 100pF Load Power Low 0 36 V us Power High 0 36 V us SRfog Falling Slew Rate 80 to 20 1V Step 100pF Load Power Low 0 4 V us Power High 0 4 V us BW og Small Signal Bandwidth 20MV pp 3dB BW 100pF Load Power Low 0 7 MHz Power High 0 7
9. 5 x Vcc 1 0 V VoLowog Low Output Voltage Swing Load 1KQ to Vcc 2 Power Low 0 5 x Vcc 1 0 V Power High 0 5 x Vcc 1 0 V lsop Supply Current Including Bias Cell No Load Power Low 0 8 1 mA Power High 2 0 5 mA PSRRog_ Supply Voltage Rejection Ratio 60 64 dB Document 001 43991 Rev D Page 13 of 38 Feedback PERFORM DC Analog Reference Specifications The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks The power levels for AGND refer to the power of the Analog Continuous Time PSoC block The power levels for RefHi and RefLo refer to the Analog Reference Control register The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block Reference control power is high Table 10 3 3V DC Analog Reference Specifications CY8CNP102B PRELIMINARY CY8CNP102B CY8CNP102E Symbol Description Min Typ Max Units VBG33 Bandgap Voltage Reference 3 3V 1 28 1 30 1 32 V AGND Vec 2l7 Vec 2 0 02 Vec 2 Vec 2 0 02 V l AGND 2xBandGap J NotAllowed S S AGND P2 4 P2 4 Vcc 2 P2 4 0 009 P2 4 P2 4 0 009 V AGND BandGap 7 1 27 1 30 1 34 V AGND 1 6 x BandGap 2 03 2 08 2 13 V AGND Block to Block Variation AGND Vec 2 I 0 034 0 000 0 034 mV RefHi Vcc
10. Oo Importable Design Database Device PSoC Database O Configuration PSoC Sheet Application Designer Database Core Engine Manufacturing Project O Information Database File User Modules C Library sm Device Programmer In Circuit Emulator Emulation Pod Document 001 43991 Rev D PSoC Designer Software Subsystems Device Editor The Device Editor subsystem enables the user to select different onboard analog and digital components called user modules using the PSoC blocks Examples of user modules are ADCs DACs nvSRAM Amplifiers and Filters The device editor also supports easy development of multiple configurations and dynamic reconfiguration Dynamic configuration enables changing configurations at run time PSoC Designer sets up power on initialization tables for selected PSoC block configurations and creates source code for an application framework The framework contains software to operate the selected components Also if the project uses more than one operating configuration the framework contains routines to switch between different sets of PSoC block configurations at run time PSoC Designer can print out a configuration sheet for a given project configuration for use during application programming in conjunction with the Device Data Sheet After the framework is generated the user can add application specific code to flesh out the fra
11. while providing an internal view of the PSoC device Debugger commands enable the designer to read and program read and write data memory read and write IO registers read and write CPU registers set and clear breakpoints and provide program run halt and step control The debugger also enables the designer to create a trace buffer of registers and memory locations of interest Page 7 of 38 Feedback CYPRESS PRELIMINARY CY8CNP102B CY8CNP102E PERFORM Online Help System The online help system displays online context sensitive help for the user Designed for procedural and quick reference each functional subsystem has its own context sensitive help This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer in getting started Hardware Tools In Circuit Emulator A low cost high functionality ICE In Circuit Emulator is available for development support This hardware has the capability to program single devices The emulator consists of a base unit that connects to the PC through the USB port The base unit is universal and operates with all PSoC devices Emulation pods for each device family are available separately The emulation pod takes the place of the PSoC device in the target board and performs full speed 24 MHz operation Designing with User Modules The development process for the PSoC device differs from that of a traditional fixed function microprocesso
12. 0 10001 ns Tsustoizc Setup Time for STOP Condition 4 0 0 6 us TBuUFI2C Bus Free Time Between a STOP and START Condition 4 7 1 3 us Tspi2c Pulse Width of spikes are suppressed by the input filter 0 50 ns Note 9 A Fast Mode I2C bus device may be used in a Standard Mode I2C bus system but the requirement tSUDAT 250 ns must then be met This is automatically the case if the device does not stretch the LOW period of the SCL signal If such device does stretch the LOW period of the SCL signal it must output the next data bit to the SDA line trmax tSU DAT 1000 250 1250 ns according to the Standard Mode 12C bus specification before the SCL line is released Document 001 43991 Rev D Page 21 of 38 Feedback PERFORM 5V Operation Absolute Maximum Ratings Table 22 5V Absolute Maximum Ratings CY8CNP102E PRELIMINARY CY8CNP102B CY8CNP102E Symbol Description Min Typ Max Units Notes TsTG Storage Temperature 55 25 100 C Higher storage temperatures reduce data retention time Recommended storage temperature is 25 C Extended duration storage temperatures above 65 C degrade reliability Ta Ambient Temperature with 40 85 C Power Applied Vcc Supply Voltage on Vcc 0 5 6 0 V Relative to Vss Vio DC Input Voltage Vss 0 5 Vcc 0 5 V Vioz DC Voltage Applied to Vss 0 5 Vcc 0 5 V Tri sta
13. 1 43991 Rev D Feedback PRELIMINARY CY8CNP102B CY8CNP102E PERFORM Switching Waveforms continued Figure 11 External Crystal Oscillator Startup Timing Diagram 32K Select 32 kHz a Tos Figure 12 24 MHz Period Jitter IMO Timing Diagram Jitter24M1 _ lt F 24M mi Figure 13 32 kHz Period Jitter ECO Timing Diagram Jitter32k a ee LT F 32K2 Figure 14 Definition of Timing for Fast Standard Mode on the I C Bus gt lt taurizci gt 4 tspi2c tuDsTAl2c i ie i t oF i 1 tsustoi2c tsusTal2c i i iSro i tHDDATI2C tuiHi2c Page 34 of 38 Document 001 43991 Rev D Feedback PERFORM Part Numbering Nomenclature PRELIMINARY CY8CNP102B CY8CNP102E CiY 8s8 Cj N P 1 0 2 B A X Cypress Temp C Commercial Industrial Microcontroller X Pb free C CMOS A 100TQFP B 3 3V NP PSoC NV Family E 5V Density 01 1Mb Processor Type 02 2Mb 1 M8C PSoC1 Based 12 512Kb Ordering Information Ordering Code Package Diagram Package Type Operating Range CY8CNP102B AXI 51 85048 100 pin TQFP Industrial CY8CNP102E A
14. 102E 4 75 4 l l l 5 33 60 i Q Operating Region i CY8CNP102B 3 00 i i l l l l l l I TP 93 kHz 12 MHz 24 MHz CPU Frequency Figure 5 IMO Frequency Trim Options A 5 25 ry Ad a a a LA PPA t t 1 1 1 1 1 1 l l l l l l 1 gt T T T T 93 kHz 6 MHz 12 MHz 24 MHz IMO Frequency The following table lists the units of measure that are used in this data sheet Table 2 Units of Measure Symbol Unit of Measure Symbol Unit of Measure ga degree Celsius uW microwatts dB decibels mA milli ampere fF femto farad ms milli second Hz hertz mV milli volts KB 1024 bytes nA nanoampere Kbit 1024 bits ns nanosecond kHz kilohertz nV nanovolts kQ kilohm Q ohm MHz megahertz pA picoampere MQ megaohm pF picofarad uA microampere pp peak to peak uF microfarad ppm parts per million uH microhenry ps picosecond us microsecond sps samples per second uV microvolts o sigma one standard deviation uVrms microvolts root mean square V volts Document 001 43991 Rev D Page 9 of 38 Feedback PERFORM 3 3V Operation Absolute Maximum Ratings Table 3 3 3V Absolute Maximum Ratings CY8CNP102B PRELIMINARY CY8CNP102B CY8CNP102E Symbol Description Min Typ M
15. 2 BandGap Not Allowed RefHi 3 x BandGap Not Allowed RefHi 2 x BandGap P2 6 P2 6 0 5V Not Allowed RefHi P2 4 BandGap P2 4 Vcc 2 Not Allowed RefHi P2 4 P2 6 P2 4 Vcc 2 P2 6 0 5V P2 4 P2 6 0 042 P2 4 P2 6 P2 4 P2 6 0 042 V RefHi 2 x BandGap 2 50 2 60 2 70 V RefHi 3 2 x BandGap Not Allowed RefLo Vcc 2 BandGap Not Allowed RefLo BandGap Not Allowed RefLo 2 x BandGap P2 6 P2 6 0 5V Not Allowed RefLo P2 4 BandGap P2 4 Vcc 2 Not Allowed RefLo P2 4 P2 6 P2 4 Vcc 2 P2 6 0 5V P2 4 P2 6 0 036 P2 4 P2 6 P2 4 P2 6 0 036 V DC Analog PSoC NV Block Specifications Table 11 3 3V DC Analog PSoC NV Block Specifications CY8CNP102B Symbol Description Min Typ Max Units Ret Resistor Unit Value Continuous Time 12 2 kQ Csc Capacitor Unit Value Switch Cap 80 fF Note 1 AGND tolerance includes the offsets of the local buffer in the PSoC block Bandgap voltage is 1 3V 0 02V Document 001 43991 Rev D Page 14 of 38 Feedback PERFORM DC POR SMP and LVD Specifications PRELIMINARY CY8CNP102B CY8CNP102E Table 12 3 3V DC POR SMP and LVD Specifications CY8CNP102B Symbol Description Min Typ Max Units Vdd Value for PPOR Trip positive ramp Vpporor PORLEV 1 0 00b 2 91 V Vdd Value for PPOR Tr
16. 231 V RefLo BandGap 1 20 1 30 1 40 V RefLo 2 x BandGap P2 6 P2 6 1 3V 2 489 P2 6 2 6 P2 6 2 711 P2 6 V RefLo P2 4 BandGap P2 4 Vcc 2 P2 4 1 368 P2 4 1 30 P2 4 1 232 V RefLo P2 4 P2 6 P2 4 Vcc 2 P2 6 1 3V P2 4 P2 6 0 042 P2 4 P2 6 P2 4 P2 6 0 042 V Document 001 43991 Rev D Page 25 of 38 Feedback CYPRESS PRELIMINARY CY8CNP102B CY8CNP102E PERFORM DC Analog PSoC NV Block Specifications Table 30 5V DC Analog PSoC NV Block Specifications CY8CNP102E Symbol Description Min Typ Max Units Ret Resistor Unit Value Continuous Time 12 2 kQ Csc Capacitor Unit Value Switch Cap 80 fF DC POR SMP and LVD Specifications Table 31 5V DC POR SMP and LVD Specifications CY8CNP102E Symbol Description Min Typ Max Units Vdd Value for PPOR Trip positive ramp Vpporor PORLEV 1 0 00b 2 91 V Vppor r PORLEV 1 0 01b 4 39 V Vppor2R PORLEV 1 0 10b 4 55 V Vdd Value for PPOR Trip negative ramp Vpporo PORLEV 1 0 00b 2 82 V Vppor1 PORLEV 1 0 01b 4 39 V Vppor2 PORLEV 1 0 10b 4 55 V PPOR Hysteresis VpHo PORLEV 1 0 00b 92 mV VPH1 PORLEV 1 0 01b 0 mV VpPH2 PORLEV 1 0 10b 0 mV Vdd Value for LVD Trip Vivoo VM 2 0 000b 2 86 2 92 2 98 41 V VLvp1 VM 2 0 001b 2 96 3 02 3 08 V VLvp2 VM 2 0 010b 3 07 3 13 3 20 V VLyD3 VM 2 0 011b
17. 3 92 4 00 4 08 V Vivp4a VM 2 0 100b 4 39 4 48 4 57 V VLvp5 VM 2 0 101b 4 55 4 64 4 74 V VLyD6 VM 2 0 110b 4 63 4 73 4 82 V Vivp7 VM 2 0 111b 4 72 4 81 4 91 V Vdd Value for SMP Trip Vpumpo VM 2 0 000b 2 96 3 02 3 08 V Vpump1 VM 2 0 001b 3 03 3 10 3 16 V Vpump2 VM 2 0 010b 3 18 3 25 3 32 V Vpump3 VM 2 0 011b 4 11 4 19 4 28 V Vpump4 VM 2 0 100b 4 55 4 64 4 74 V Vpumps VM 2 0 101b 4 63 4 73 4 82 V Vpumpe VM 2 0 110b 4 72 4 82 4 91 V Vpump7 VM 2 0 111b 4 90 5 00 5 10 V Document 001 43991 Rev D Page 26 of 38 Feedback PERFORM DC Programming Specifications Table 32 5V DC Programming Specifications CY8CNP102E PRELIMINARY CY8CNP102B CY8CNP102E Symbol Description Min Typ Max Units Notes Ipppv Supply Current During Programming or Verify 10 30 mA ViLp Input Low Voltage During Programming or Verify 0 8 V ViHP Input High Voltage During Programming or Verify 2 2 V liLpP Input Current when Applying Vilp to P1 0 or 0 2 mA _ Driving internal pull P1 1 During Programming or Verify down resistor liHP Input Current when Applying Vihp to P1 0 or 1 5 mA Driving internal pull P1 1 During Programming or Verify down resistor Vov Output Low Voltage During Programming or Vss 0 75 V Verify VoHv Output High Voltage During Programming or Vcc 1 0 Vcc V Verify Flashgypsg Flash Endurance per block 50 000 Erase w
18. 5 mA resp Table 23 Changed Typ and max value of Ippp from 15 mA and 16 mA to 27 mA and 28 mA resp Table 23 Changed Min and Max value of Vcap from 56 uF and 100 uF to 61 uF and 82 uF resp Added Table 30 DC POR SMP and LVD specifications Table 31 Changed Ippp naming convention to Ipppy table 32 Updated note references Updated Figure 14 Definition for Timing for Fast Standard Mode on the I2C bus Updated part Numbering Nomenclature Updated Thermal Impedance table Updated data sheet template C 2571208 GVCH PYRS 09 23 08 Changed Title from nvPSoC to PSoC NV Updated Features D 2594976 GVCH PYRS 10 22 08 Added M8C processor speeds for 3 3V and 5V operation in Features Updated Logic block diagram Changed total GPIOs from 27 to 33 Changed pin number 53 name from P1_4 to P1_6 Changed pin definition of pin 79 and 99 Table 5 Changed Isp from 3 mA to 5 mA Updated Table 12 Table 24 Changed Isp from 3 mA to 5 mA Document 001 43991 Rev D Page 37 of 38 Feedback formes PRELIMINARY CY8CNP102B CY8CNP102E S SS SS SSS 1 PERFORM Sales Solutions and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices solution centers manufacturer s representatives and distributors To find the office closest to you visit us at cypress com sales Products PSoC Solutions PSoC psoc cypress com General psoc cypre
19. 67 80 dB Vss lt VIN lt Vcc 2 25 or Vcc 1 25V lt VIN lt Vcc DC Low Power Comparator Specifications Table 27 5V DC Low Power Comparator Specifications CY8CNP102E Symbol Description Min Typ Max Units VRefLpc Low power comparator LPC reference voltage range 0 2 Vcc 1 0 V IsLPC LPC supply current 7 10 40 LA Vostpc LPC voltage offset 2 5 30 mV Document 001 43991 Rev D Page 24 of 38 Feedback PERFORM DC Analog Output Buffer Specifications Table 28 5V DC Analog Output Buffer Specifications CY8CNP102E PRELIMINARY CY8CNP102B CY8CNP102E Symbol Description Min Typ Max Units Vosos Input Offset Voltage Absolute Value 3 12 mV TCVosop Average Input Offset Voltage Drift 7 6 uV C VCMOB Common Mode Input Voltage Range 0 5 Vcc 1 0 V Rourog Output Resistance Power Low 1 Q Power High 1 Q VonicHos High Output Voltage Swing Load 32 ohms to Vcc 2 Power Low 0 5 x Vcc 1 3 V Power High 0 5 x Vcc 1 3 V VoLowos Low Output Voltage Swing Load 32 ohms to Vcc 2 Power Low 0 5 x Vcc 1 3 V Power High 0 5 x Vcc 1 3 V lsoB Supply Current Including Bias Cell No Load Power Low 1 1 2 mA Power High 2 6 5 mA PSRRog_ Supply Voltage Rejection Ratio 40 64 dB DC Analog Reference Specifications The guaranteed specifications a
20. API functions User Module and Source Code Development Flows The next step is to write the main program and any subroutine using PSoC Designer s Application Editor subsystem The Application Editor includes a Project Manager that enables you to open the project source code files including all generated code files from a hierarchal view The source code editor provides syntax coloring and advanced edit features for C and assembly language File search capabilities include simple string searches and recursive grep style patterns A single mouse click invokes the Build Manager It employs a professional strength makefile system to automatically analyze all file dependencies and run the compiler and assembler as necessary Project level options control optimization strategies used by the compiler and linker Syntax errors are displayed in a console window Double clicking the error message takes you directly to the offending line of source code After correction the linker builds a HEX file image suitable for programming Figure 3 User Module and Source Code Development Flows Device Editor User oe Source Module Code i Parameter Selection E aii Generator ization Generate Application Application Editor Project Source Build Manager Code Manager g Editor j Build All Debugger Event amp Interface Storage Breakpoint to ICE Inspector Manager
21. AX f L SEE DETAIL A 51 85048 C Thermal Impedance Table 41 Thermal Impedance Package Typical Oja Typical jc 100 TQFP 26 14 C W 5 81 C W Note 10 Ty Ta POWER x Oja Document 001 43991 Rev D Page 36 of 38 Feedback PERFORM Document History Page PRELIMINARY CY8CNP102B CY8CNP102E Document Title CY8CNP102B CY8CNP102E Nonvolatile Programmable System on Chip PSoC NV Document Number 001 43991 REV ECN Orig of Change sagt on Description of Change sii 1941108 vsutmp8 AESA See ECN New Data Sheet A 2378513 PYRS See ECN Move to external web B 2512803 GVCH PYRS 06 05 2008 Features Added total no of GPIO information in Programmable Pin configurations Changed Pin no 14 from P3_7 to NC in the Pin diagram Table 1 Updated Pin definitions Table 5 Changed Typ and max value of Ipp from 25 mA and 29mA to 36 mA and 40 mA resp Table 5 Changed Typ and max value of Ippp from 15 mA and 16 mA to 27 mA and 28 mA respectively Table 5 Changed Min and Max value of Vcap from 56 uF and 100 uF to 61 uF and 82 uF resp Table 6 Changed Vjy min value from 2 1 mV to 1 6 mV Added Table 12 DC POR SMP and LVD specifications Table 13 Changed Ippp naming convention to Ipppy Table 14 Updated note references Table 17 Updated Timer Counter deadband and CRCPS PRS mode values Table 23 Changed Typ and max value of Ipp from 28 mA and 34 mA to 39 mA and 4
22. PRELIMINARY CY8CNP102B CY8CNP102E Nonvolatile Programmable System on Chip PERFORM PSoC NV m Precision Programmable Clocking a Internal 2 5 24 and 48 MHz Oscillator a 24 and 48 MHz with optional 32 768 kHz Crystal a Optional External Oscillator up to 24 MHz a Internal Oscillator for Watchdog and Sleep Overview The Cypress nonvolatile Programmable System on Chip PSoc NV processor combines a versatile Programmable System on Chip PSoC core with an infinite endurance nvSRAM in a single package The PSoC NV combines an 8 bit MCU core M8C configurable analog and digital functions a uniquely flexible IO interface and a high density nvSRAM This creates versatile data logging solutions that provide value through component integration and programmability The flexible core and a powerful development environment work to reduce Flexible On Chip Memory a 32K Bytes Flash Program Storage a 2K Bytes SRAM Data Storage a 256K Bytes secure store nvSRAM with data throughput be design complexity component count and development time Features m Powerful Harvard Architecture Processor a M8C processor speeds Up to 12 MHz for 3 3V operation e Up to 24 MHz for 5V operation a Two 8x8 multiply 32 bit accumulate a Low power at high speed Operating Voltage a 3 3V CY8CNP102B a 5V CY8CNP102E Advanced Peripherals a 12 Rail to Rail Analog PSoC blocks provide e Up to 14 bit ADCs Up to 9 bit DACs e Prog
23. Symbol Description Units Min Max Min Max Fsczc SCL Clock Frequency 0 100 0 400 kHz THDSTAI2C Hold Time repeated START Condition After this 4 0 0 6 us period the first clock pulse is generated TLowlzc LOW Period of the SCL Clock 4 7 1 3 us THIGHI2c HIGH Period of the SCL Clock 4 0 7 0 6 us TsusTAl2c Setup Time for a Repeated START Condition 4 7 7 0 6 us Tuppati2c Data Hold Time 0 0 us Tsupatizc Data Setup Time 250 z 10001 ns Tsustol2c Setup Time for STOP Condition 4 0 0 6 us TBuUFI2C Bus Free Time Between a STOP and START Condition 4 7 1 3 us Tspi2c Pulse Width of spikes are suppressed by the input filter E 7 0 50 ns Document 001 43991 Rev D Page 32 of 38 Feedback PRELIMINARY CY8CNP102B CY8CNP102E PERFORM Switching Waveforms Figure 8 AutoStore Power Up RECALL No STORE occurs without atleast one STORE occurs only if a SRAM write Vec has happened A SRAM write Waa gt c lt tvccrise AutoStore lt tstore gt lt tstore gt POWER UP RECALL e lt areca LurecaLt Read amp Write Inhibited Figure 9 PLL Lock Timing Diagram PLL Gain 0 Figure 10 PLL Lock for Low Gain Setting Timing Diagram PLL Enable lt a Tpitstewtow 24 MHz PLL 1 Gain Page 33 of 38 Document 00
24. XI 51 85048 100 pin TQFP All the above mentioned parts are of Pb free type and contain preliminary information Please contact your local Cypress sales representative for availability of these parts Document 001 43991 Rev D Page 35 of 38 Feedback CYPRESS PRELIMINARY CY8CNP102B CY8CNP102E PERFORM Packaging Information This section describes the packaging specifications for the PSoC NV device and the thermal impedances for TQFP package Note Emulation tools may require a larger area on the target PCB than the chip s footprint For a detailed description of the emulation tool dimensions refer to the document PSoC Emulator Pod Dimensions at http www cypress com design MR10161 Package Diagrams Figure 15 100 Pin TQFP 14x 14 x 1 4mm NOTE 1 JEDEC STD REF MS 026 2 BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION END FLASH MOLD PROTRUSION END FLASH SHALL NOT EXCEED 0 0098 In 0 25 mm PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 3 DIMENSIONS IN MILLIMETERS 16 00 0 25 SQ 14 00 0 05 SQ N u ite 2 S R 0 08 MIN Fi 0 MIN 4 020 MAX a gt STAND OFF 0 05 MIN 0 25 0 15 MAX GAUGE PLANE S 0 20 MAX 0t 7 0 50 TYP DETAIL 1 00 REF NOTE PKG CAN HAVE r SEATING PLANE 12 41 L60 MAX C B i TOP LEFT CORNER CHAMFER 4 CORNERS CHAMFER 0 20 M
25. _5 IO GPIO 16 EN_W Connect to Pin 26 EN_W to NV_W 17 P3_1 IO GPIO Document 001 43991 Rev D Page 3 of 38 Feedback CYPRESS PRELIMINARY CY8CNP102B CY8CNP102E PERFORM Table 1 Pin Definitions 100 Pin TQFP continued Pin Number Pin Name Type Pin Definition Digital Analog 18 P5_7 IO GPIO 19 P5_5 IO GPIO 20 P5_3 IO GPIO 21 P5_1 IO GPIO 22 P1_7 IO 12C Serial Clock SCL GPIO 23 P1_5 IO I2C Serial Data SDA GPIO 24 P1_3 IO GPIO 25 P1_1 IO Serial Clock SCL Crystal XTALin GPIO 26 NV_W Connect to pin 16 NV_W to EN_W 27 34 NC Not connected on the die 35 39 Vss Power Ground 40 47 NC Not connected on the die 48 DNU Reserved for test modes Do Not Use 49 NV_A1 Connect to pin 58 NV_A1 to EN_A1 50 NV_A2 Connect to pin 59 NV_A2 to EN_A2 51 P1_0 IO Serial Data SDA Crystal XTALout GPIO 52 P1_2 IO GPIO 53 P1_6 IO GPIO 54 P5_0 IO GPIO 55 P5_2 IO GPIO 56 P5_4 IO GPIO 57 P5_6 IO GPIO 58 EN_A1 Connect to Pin 49 EN_A1 to NV_A1 59 EN_A2 Connect to Pin 50 EN_A2 to NV_A2 60 EN_O Connect to Pin 76 EN_O to NV_O 61 EN_C Connect to Pin 99 EN_C to NV_C 62 XRES Input Active high external reset Internal Pull down 63 VCAP Power External Capacitor connection for nvSRAM 64 Vcc Power Supply Voltage 65 P2_0 IO l Direct Switched Capacitor Block Inpu
26. ack F CYPRESS PRELIMINARY CY8CNP102B CY8CNP102E PERFORM Logic Block Diagram I e Programmable Interconnect x and Logic Watchdog Sleep Time LYD Supervisor Interrupt Controller syuod OL aKeunbipio gt Clocking Gererator t Analog Input 24 MHz Internal Oscillator Document 001 43991 Rev D Page 2 of 38 Feedback PRELIMINARY CY8CNP102B CY8CNP102E Figure 1 Pin Diagram 100 Pin TQFP Package 14 x 14 x 1 4 mm 1 2 o o gt Q gt oo0ocovcovvns Zz2z2z2z2222222 100 TQFP Vss jar on 0 w n o CER ER n a gt gt gt gt NC NC NC NC NC 100 CMONADHRWN AO z eeegseeessssseeeeeeer22 2 22 Table 1 Pin Definitions 100 Pin TQFP 7 Type Ree Pin Number Pin Name Pin Definition Digital Analog 1 P0_5 IO IO Analog Column Mux Input and Column Output 2 P0_3 IO IO Analog Column Mux Input and Column Output 3 PO_1 IO l Analog Column Mux Input GPIO 4 P2_7 IO GPIO 5 P2_5 10 GPIO 6 P2_3 IO l Direct Switched Capacitor Block Input 7 P2_1 IO l Direct Switched Capacitor Block Input 8 Vcc Power Supply Voltage 9 DNU Reserved for test modes Do Not Use 10 DNU Reserved for test modes Do Not Use 11 DNU Reserved for test modes Do Not Use 12 DNU Reserved for test modes Do Not Use 13 DNU Reserved for test modes Do Not Use 14 NC Not connected on the die 15 P3
27. applicable Cypress software license agreement Document 001 43991 Rev D Revised October 20 2008 Page 38 of 38 PSoC Designer Programmable System on Chip and PSoC Express are trademarks and PSoC is a registered trademark of Cypress Semiconductor Corp All other trademarks or registered trademarks referenced herein are property of the respective corporations AutoStore and QuantumTrap are registered trademarks of Simtek Corporation All products and company names mentioned in this document are the trademarks of their respective holders Feedback
28. ax Units Notes TsTG Storage Temperature 55 25 100 C Higherstorage temperatures reduce data retention time Recommended storage temperature is 25 C Extended duration storage temperatures above 65 C degrade reliability Ta Ambient Temperature with Power Applied 40 85 C Vcc Supply Voltage on Vcc Relative to Vss 0 5 4 1 V Vio DC Input Voltage Vss 0 5 Vcc 0 5 V Vioz DC Voltage Applied to Tri state Vss 0 5 Vcc 0 5 V Imio Maximum Current into any Port Pin 25 50 mA IMAIO Maximum Current into any Port Pin 50 50 mA Configured as Analog Driver ESD Electro Static Discharge Voltage 2000 V Human Body Model ESD LU Latch up Current 200 mA Operating Temperature Table 4 3 3V Operating Temperature CY8CNP102B Symbol Description Min Typ Max Units Notes Ta Ambient Temperature 40 85 C Ty Junction Temperature 40 100 C Document 001 43991 Rev D Page 10 of 38 Feedback CYPRESS PRELIMINARY CY8CNP102B CY8CNP102E PERFORM DC Electrical Characteristics The following DC electrical specifications list the guaranteed maximum and minimum specifications for the voltage and temperature range 3 0V to 3 6V over the Temperature range of 40 C lt T lt 85 C Typical parameters apply to 3 3V at 25 C and are for design guidance only DC Chip Level Specifications Table 5 3 3V DC Chip Level Specifications CY8CNP102B
29. dependent 50 duty cycle Foie PLL Frequency 23 986 MHz A multiple x732 of crystal frequency Jitter24M2 24 MHz Period Jitter PLL 600 ps TPLLSLEW PLL Lock Time 0 5 10 ms TpLLSLEWLow PLL Lock Time for Low Gain Setting 0 5 50 ms Tos External Crystal Oscillator Startup to 1 250 500 ms Tosacc External Crystal Oscillator Startup to 100 ppm E 300 600 ms The crystal oscillator frequency is within 100 ppm of its final value by the end of the Tosacc period Correct operation assumes a properly loaded 1 uW maximum drive level 32 768 kHz crystal Jitter32k 32 kHz Period Jitter 100 ns Txrst External Reset Pulse Width 10 us DC24M 24 MHz Duty Cycle 40 50 60 Step24M 24 MHz Trim Step Size 50 kHz Fout48M 48 MHz Output Frequency 46 8 48 0 49 2140 MHz Trimmed Using factory trim values Jitter24M1 24 MHz Period Jitter IMO 600 ps FMAX Maximum frequency of signal on row input or 12 3 MHz row output TRAMP Supply Ramp Time 0 us Document 001 43991 Rev D Page 28 of 38 Feedback Ss PRELIMINARY CY8CNP102B CY8CNP102E PERFORM In the following table tyrecatt Starts from the time Vcc rises above Vswitcu If an SRAM WRITE has not taken place since the last nonvolatile cycle no STORE takes place Industrial grade devices require 15 ms maximum Table 34 5V nvSRAM AutoStore Power Up RECALL CY8CNP102E
30. ency 46 8 48 0 49 2481 MHz Trimmed Using factory trim values Jitter24M1 24 MHz Period Jitter IMO 600 ps FMAX Maximum frequency of signal on row input 12 3 MHz or row output TRAMP Supply Ramp Time 0 us Notes 4 4 75V lt Vcc lt 5 25V 5 Accuracy derived from Internal Main Oscillator with appropriate trim for Vcc range 6 3 0V lt Vcc lt 3 6V See Application Note AN2012 Adjusting PSoC Micro controller Trims for Dual Voltage Range Operation for information on trimming for operation at 3 3V 7 See individual user module data sheets for information on maximum frequencies for user modules Document 001 43991 Rev D Page 17 of 38 Feedback In the following table tyrecatt Starts from the time Vcc rises above Vswitcu If an SRAM WRITE has not taken place since the last PRELIMINARY CY8CNP102B CY8CNP102E nonvolatile cycle no STORE occurs Industrial grade devices require 15 ms maximum Table 15 3 3V nvSRAM AutoStore Power Up RECALL CY8CNP102B poe nvSRAM p Parameter Description Unit Min Max tuRECALL Power Up RECALL Duration 20 ms tsTORE STORE Cycle Duration 12 5 ms VswitcH Low Voltage Trigger Level 2 65 V tVccRISE VCC Rise Time 150 us AC General Purpose IO Specifications Table 16 3 3V AC GPIO Specifications CY8CNP102B Symbol Description Min Typ Max Units Notes Fepio GPIO Operating Frequency 0 12 3 MHz Normal Strong Mode TRiseS Rise Time
31. er for digital signal and processing applications including the creation of Delta Sigma ADCs m The 12C module provides 100 and 400 kHz communication over two wires Slave master and multi master modes are all supported m Low Voltage Detection LVD interrupts can signal the application of falling voltage levels while the advanced POR Power On Reset circuit eliminates the need for a system supervisor Page 6 of 38 Feedback CYPRESS PRELIMINARY CY8CNP102B CY8CNP102E PERFORM Development Tools PSoC Designer is a Microsoft Windows based integrated development environment for Programmable System on Chip PSoC devices The PSoC Designer IDE and application run on Windows NT 4 0 Windows 2000 Windows Millennium Me Microsoft Vista and Windows XP PSoC Designer helps the customer to select an operating configuration for the PSoC write application code that uses the PSoC and debug the application This system provides design database management by project an integrated debugger with In Circuit Emulator in system programming support and the CYASM macro assembler for the CPUs PSoC Designer also supports a high level C language compiler developed specifically for the devices in this family Figure 2 PSoC Designer Subsystem i i Context Graphical Designer PSoC Mia race I Sensitive Designer Help N g D e J c 5 J
32. estart Mode 50 8 ns Disable Mode 50 8 ns Maximum Frequency 49 2 MHz 4 75V lt Vcc lt 5 25V CRCPRS Maximum Input Clock Frequency 49 2 MHz 4 75V lt Vcc lt 5 25V PRS Mode Document 001 43991 Rev D Page 30 of 38 Feedback Table 37 5V AC Digital Block Specifications CY8CNP102E continued PERFORM PRELIMINARY CY8CNP102B CY8CNP102E Function Description Min Typ Max Units Notes CRCPRS Maximum Input Clock Frequency 24 6 MHz 4 75V lt Vcc lt 5 25V CRC Mode SPIM Maximum Input Clock Frequency 8 2 MHz _ Maximum data rate at 4 1 MHz due to 2 x over clocking SPIS Maximum Input Clock Frequency 4 1 ns Width of SS_ Negated Between Transmis 508 ns sions Transmitter Maximum Input Clock Frequency 24 6 MHz _ Maximum data rate at Vcc gt 4 75V 2 Stop Bits 3 08 MHz due to 8 x over clocking 49 2 MHz _ Maximum data rate at 6 15 MHz due to 8 x over clocking Receiver Maximum Input Clock Frequency 24 6 MHz Maximum data rate at Vcc gt 4 75V 2 Stop Bits 3 08 MHz due to 8 x over clocking 49 2 MHz _ Maximum data rate at 6 15 MHz due to 8 x over clocking AC Analog Output Buffer Specifications Table 38 5V AC Analog Output Buffer Specifications CY8CNP102E Symbol Description Min Typ Max Units Trop Rising Settling Time to 0 1 1V Step 100 pF Load Power L
33. gurable analog and digital blocks interconnect circuitry around an MCU subsystem and an infinite endurance nvSRAM This enables high level integration in consumer industrial and automotive applications where preventing data loss under all conditions is vital PSoC NV Core The PSoC NV core is a powerful PSoC engine that supports a rich feature set The core includes a M8C CPU memory clocks and configurable GPIO General Purpose IO The M8C CPU core is a powerful processor with speeds up to 24 MHz providing a four MIPS 8 bit Harvard architecture microprocessor The CPU uses an interrupt controller with 25 vectors to simplify programming of real time embedded events Program execution is timed and protected using the included Sleep and Watch Dog Timers WDT On chip memory encompasses 32 KB Flash for program storage 2 KB SRAM for data storage 256 KB nvSRAM for data logging and up to 2 KB EEPROM emulated using Flash Program Flash uses four protection levels on blocks of 64 bytes allowing customized software IP protection The nvSRAM combines a static RAM cell and a SONOS cell to provide an infinite endurance nonvolatile memory block The memory is random access and is accessed using a user module provided with the device The device incorporates flexible internal clock generators including a 24 MHz Internal Main Oscillator IMO accurate to 2 5 percent over temperature and voltage The 24 MHz IMO can also be doubled to 48 MHz f
34. ip negative ramp Vpporo PORLEV 1 0 00b 2 82 V PPOR Hysteresis VpHo PORLEV 1 0 00b 92 mV VPH1 PORLEV 1 0 01b 0 mV VpH2 PORLEV 1 0 10b 0 mV Vdd Value for LVD Trip Vivpo VM 2 0 000b 2 86 2 92 2 98 71 V Vivo1 VM 2 0 001b 2 96 3 02 3 08 V Vivp2 VM 2 0 010b 3 07 3 13 3 20 V Vdd Value for SMP Trip Vpumpo VM 2 0 000b 2 96 3 02 3 08 V Vpump VM 2 0 001b 3 03 3 10 3 16 V Vpump2 VM 2 0 010b 3 18 3 25 3 32 V Note 2 Always greater than 50 mV above PPOR PORLEV 00 for falling supply Document 001 43991 Rev D Page 15 of 38 Feedback PRELIMINARY CY8CNP102B CY8CNP102E PERFORM DC Programming Specifications Table 13 3 3V DC Programming Specifications CY8CNP102B Symbol Description Min Typ Max Units Notes Ipppv Supply Current During Programming or Verify 10 30 mA ViLp Input Low Voltage During Programming or Verify 0 8 V ViHP Input High Voltage During Programming or Verify 2 2 V liLpP Input Current when Applying Vilp to P1 0 or P1 1 0 2 mA Driving internal pull During Programming or Verify down resistor liHP Input Current when Applying Vihp to P1 0 or P1 1 1 5 mA Driving internal pull During Programming or Verify down resistor Vov Output Low Voltage During Programming or Verify Vss 0 75 V VoHv Output High Voltage During Programming or Verify Vcc 1 0 Vcc V Flashenpg Flash Endurance
35. mework It is also possible to change the selected components and regenerate the framework Design Browser The Design Browser enables users to select and import preconfigured designs into their project Users can easily browse a catalog of preconfigured designs to facilitate time to design Examples provided in the tools include a 300 baud modem LIN Bus master and slave fan controller and magnetic card reader Application Editor In the Application Editor you can edit C language and Assembly language source code You can also assemble compile link and build Assembler The macro assembler seamlessly merges the assembly code with C code The link libraries automatically use absolute addressing or are compiled in relative mode and linked with other software modules to get absolute addressing C Language Compiler A C language compiler that supports Cypress PSoC family devices is available Even if you have never worked in the C language before the product quickly enables you to create complete C programs for the PSoC family devices The embedded optimizing C compiler provides all the features of C tailored to the PSoC architecture It is complete with embedded libraries providing port and bus operations standard keypad and display support and extended math functionality Debugger The PSoC Designer Debugger subsystem provides hardware in circuit emulation which enables the designer to test the program in a physical system
36. nitiate software STORE and RECALL function from the user program nvSRAM Operation The nvSRAM is made up of an SRAM memory cell and a nonvolatile QuantumTrap cell paired in the same physical cell The SRAM memory cell operates as a standard fast static and all READ and WRITE takes place from the SRAM during normal operation During the STORE and RECALL operations SRAM READ and WRITE operations are inhibited and internal operations transfer data between the SRAM and nonvolatile cells The nvSRAM provides infinite RECALL operations from the nonvolatile cells and up to 200 000 STORE operations To reduce unnecessary nonvolatile stores AutoStore is ignored unless at least one WRITE operation is complete after the most recent STORE or RECALL cycle Software initiated STORE cycles are performed regardless of whether a WRITE operation has taken place Embedded APIs provide a seamless interface to the nvSRAM During normal operation the embedded nvSRAM draws current from Vcc to charge a capacitor connected to the Vcap pin This stored charge is used by the chip to perform a STORE operation If the voltage on the Vcc pin drops below Vsgwitcu the part automatically disconnects the Vcap pin from Vcc and STORE operation is initiated Page 5 of 38 Feedback CYPRESS PRELIMINARY CY8CNP102B CY8CNP102E PERFORM Programmable Digital System The digital system contains 16 digital PSoC blocks Each block is an 8 bit resource tha
37. nternal 0 01 V signals Isoa Supply Current including associated AGND buffer Power Low Opamp Bias Low 150 200 uA Power Low Opamp Bias High 300 400 uA Power Medium Opamp Bias Low 600 800 uA Power Medium Opamp Bias High 1200 1600 HA Power High Opamp Bias Low 2400 3200 uA Power High Opamp Bias High uA Not Allowed for 3 3V operation PSRR oa Supply Voltage Rejection Ratio 54 80 dB Vss lt VIN lt Vcc 2 25 or Vcc 1 25V lt VIN lt Vcc DC Low Power Comparator Specifications Table 8 3 3V DC Low Power Comparator Specifications CY8CNP102B Symbol Description Min Typ Max Units VREFLPC Low power comparator LPC reference voltage range 0 2 Vcc 1 0 V IsLPC LPC supply current 10 40 LA Vos pc LPC voltage offset 2 5 30 mV Document 001 43991 Rev D Page 12 of 38 Feedback Ss PRELIMINARY CY8CNP102B CY8CNP102E PERFORM DC Analog Output Buffer Specifications Table 9 3 3V DC Analog Output Buffer Specifications CY8CNP102B Symbol Description Min Typ Max Units Vosos Input Offset Voltage Absolute Value 3 12 mV TCVosog Average Input Offset Voltage Drift 6 V C Vcmos Common Mode Input Voltage Range 0 5 Vcc 1 0 V Routos Output Resistance Power Low 10 Q Power High 10 Q VonicHos High Output Voltage Swing Load 1KQ to Vcc 2 Power Low 0 5 x Vec 1 0 V Power High 0
38. nternal Main Oscillator Frequency for 23 4 24 24 6l4 5 6l MHz Trimmed for 3 3V operation using 24 MHz factory trim values See the figure on page 10 SLIMO Mode 0 Fimoe Internal Main Oscillator Frequency for 5 75 6 6 35455 MHz Trimmed for 3 3V operation using 6 MHz factory trim values See the figure on page 10 SLIMO Mode 1 Fopy2 CPU Frequency 3 3V Nominal 0 93 12 12 3581 MHz Fas Digital PSoC Block Frequency 0 48 49 2145 7I MHz Refer to section AC Digital Block Specifications on page 19 Foam Digital PSoC Block Frequency 0 24 24 67 MHz F32K1 Internal Low Speed Oscillator Frequency 15 32 64 kHz F32K2 External Crystal Oscillator 32 768 kHz Accuracy is capacitor and crystal dependent 50 duty cycle Foie PLL Frequency 23 986 MHz A multiple x732 of crystal frequency Jitter24M2 24 MHz Period Jitter PLL 600 ps TPLLSLEW PLL Lock Time 0 5 10 ms TpPLLsLewLow PLL Lock Time for Low Gain Setting 0 5 50 ms Tos External Crystal Oscillator Startup to 1 250 500 ms Tosacc External Crystal Oscillator Startup to 7 300 600 ms The crystal oscillator frequency is 100 ppm within 100 ppm of its final value by the end of the Tosacc period Correct operation assumes a properly loaded 1 uW maximum drive level 32 768 kHz crystal Jitter32k 32 kHz Period Jitter 100 ns Txrst External Reset Pulse Width 10 7 us DC24M 24 MHz Duty Cycle 40 50 60 Step24M 24 MHz Trim Step Size 50 kHz Fout48M 48 MHz Output Frequ
39. or use by the digital system A low power 32 kHz Internal Low speed Oscillator ILO is provided for the Sleep timer and WDT The clocks together with programmable clock dividers as a System Resource provide the flexibility to integrate almost any timing requirement into the PSoC NV device GPIOs provide connection to the CPU and digital and analog resources of the device Each pin s drive mode may be selected from eight options allowing great flexibility in external Document 001 43991 Rev D interfacing Every pin also has the capability to generate a system interrupt on high level low level and change from last read nvSRAM Data Memory The nvSRAM memory block is byte addressable fast static RAM with a nonvolatile element in each memory cell The embedded nonvolatile elements incorporate QuantumTrap technology producing the world s most reliable nonvolatile memory The SRAM provides infinite read and write cycles when independent nonvolatile data resides in the highly reliable QuantumTrap cell Data transfers from the SRAM to the nonvolatile elements the STORE operation takes place automatically at power down and data is restored to the SRAM the RECALL operation from the nonvolatile memory on power up All cells store and recall data in parallel Both the STORE and RECALL operations may be initiated under software control The PSoC NV user module embedded in the PSoC Designer Tool provides all necessary APIs to i
40. ow 4 us Power High 4 us TsoB Falling Settling Time to 0 1 1V Step 100 pF Load Power Low 3 4 us Power High 3 4 us SRrosp Rising Slew Rate 20 to 80 1V Step 100 pF Load Power Low 0 5 V us Power High 0 5 V s SRfog Falling Slew Rate 80 to 20 1V Step 100 pF Load Power Low 0 55 V s Power High 0 55 V us BWos Small Signal Bandwidth 20mV pp 3dB BW 100 pF Load Power Low 0 8 MHz Power High 0 8 MHz BW og Large Signal Bandwidth 1Vpp 3dB BW 100 pF Load Power Low 300 kHz Power High 300 kHz Document 001 43991 Rev D Page 31 of 38 Feedback PERFORM AC Programming Specifications Table 39 5V AC Programming Specifications CY8CNP102E PRELIMINARY CY8CNP102B CY8CNP102E Symbol Description Min Typ Max Units Notes TRSCLK Rise Time of SCLK 1 20 ns TEScLK Fall Time of SCLK 1 20 ns Tssc_k Data Set up Time to Falling Edge of SCLK 40 7 ns THsc_k Data Hold Time from Falling Edge of SCLK 40 ns Fscik Frequency of SCLK 0 8 MHz TERASEB Flash Erase Time Block 10 ms TwrITE Flash Block Write Time 10 ms Tpsc_k Data Out Delay from Falling Edge of SCLK 45 ns 4 75V lt Vcc lt 5 25V ACC Specifications Table 40 5V AC Characteristics of the I2C SDA and SCL Pins CY8CNP102E ee Standard Mode Fast Mode
41. p Timer WDT and internal slow oscillator active VREF Reference Voltage Bandgap 1 28 1 3 1 32 V Trimmed for appropriate Vcc Veap Storage Capacitor between Vcap 61 68 82 uF 5V rated minimum and Vss DC General Purpose IO Specifications Table 25 5V DC GPIO Specifications CY8CNP102E Symbol Description Min Typ Max Units Notes Rpy Pull up Resistor 4 5 6 8 kQ Rpp Pull down Resistor 4 5 6 8 kQ VoH High Output Level Vcc 1 0 V IOH 10 mA Vcc 4 75 to 5 25V 8 total loads 4 on even port pins for example PO 2 P1 4 4 on odd port pins for example PO 3 P1 5 80 mA maximum combined IOH budget VoL Low Output Level 0 75 V IOL 25 mA Vcc 4 75 to 5 25V 8 total loads 4 on even port pins for example PO 2 P1 4 4 on odd port pins for example PO 3 P1 5 150 mA maximum combined IOL budget Vit Input Low Level 0 8 V 4 75 to 5 25 Vin Input High Level 2 1 V 4 75 to 5 25 Vu Input Hysterisis 60 mV liL Input Leakage Absolute Value 1 nA Gross tested to 1 uA Cin Capacitive Load on Pins as Input 3 5 10 pF Pin dependent Temp 25 C Cout Capacitive Load on Pins as Output 3 5 10 pF Pin dependent Temp 25 C Document 001 43991 Rev D Page 23 of 38 Feedback Ss PRELIMINARY CY8CNP102B CY8CNP102E PERFORM DC Operational Amplifier Specifications The Operational Amplifie
42. per block 50 000 Erase write cycles per block Flashent Flash Endurance total I 1 800 000 Erase write cycles Flashpr Flash Data Retention 10 Years Note 3 A maximum of 36 x 50 000 block endurance cycles is allowed This may be balanced between operations 36x1 blocks of 50 000 maximum cycles each 36x2 blocks of 25 000 maximum cycles each or 36x4 blocks of 12 500 maximum cycles each to limit the total number of cycles to 36x50 000 and that no single lock ever sees more than 50 000 cycles For the full industrial range the user must employ a temperature sensor user module Flash Temp and feed the result to the temperature argument before timing Refer to the Flash APIs Application Note AN2015 at http www cypress com under Application Notes for more information Document 001 43991 Rev D Page 16 of 38 Feedback CYPRESS PRELIMINARY CY8CNP102B CY8CNP102E PERFORM AC Electrical Characteristics The following AC electrical specifications list the guaranteed maximum and minimum specifications for the voltage and temperature range 3 0V to 3 6V over the temperature range of 40 C lt T4 lt 85 C Typical parameters apply to 3 3V at 25 C and are for design guidance only AC Chip Level Specifications Table 14 3 3V AC Chip Level Specifications CY8CNP102B Symbol Description Min Typ Max Units Notes Fimo24 I
43. r The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that manages specification change during development and lowers inventory costs These configurable resources called PSoC Blocks implement a wide variety of user selectable functions Each block has several registers that determine its function and connectivity to other blocks multiplexers buses and to the IO pins Iterative development cycles permit you to adapt the hardware and the software This substantially lowers the risk of selecting a different part to meet the final design requirements To speed the development process the PSoC Designer IDE provides a library of prebuilt pretested hardware peripheral functions called User Modules User modules simplify selecting and implementing peripheral devices and come in analog digital and mixed signal varieties The standard User Module library contains over 50 peripherals such as ADCs DACs Timers Counters UARTs nvSRAM DTMF Generators and Bi Quad analog filter sections Each user module establishes the basic register settings that implement the selected function It also provides parameters that enable you to tailor its precise configuration to your particular application For example a Pulse Width Modulator User Module configures one or more digital PSoC blocks one for each 8 bits of resolution The user module parameters permit you to establish the pulse width and duty c
44. r is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Capacitor PSoC blocks The guaranteed specifications are measured in the Analog Continuous Time PSoC block Table 26 5V DC Operational Amplifier Specifications CY8CNP102E Symbol Description Min Typ Max Units Notes Vosoa Input Offset Voltage absolute value Power Low Opamp Bias High 1 6 10 mV Power Medium Opamp Bias High 1 3 8 mV Power High Opamp Bias High 1 2 7 5 mV TCVosoa Average Input Offset Voltage Drift 7 0 35 0 uV C IEBOA Input Leakage Current Port 0 Analog Pins 200 pA Gross tested to 1 uA Cinoa Input Capacitance Port 0 Analog Pins 4 5 9 5 pF Pin dependent Temp 25 C Vomoa Common Mode Voltage Range All Cases except highest 0 0 Vec V Power High Opamp Bias High 0 5 Vec 0 5 V CMRR oa Common Mode Rejection Ratio 60 dB GoLoa Open Loop Gain 80 dB VonicHoa High Output Voltage Swing internal signals Vcc 0 01 V Votowoa_ Low Output Voltage Swing internal signals 0 1 V Isoa Supply Current including associated AGND buffer Power Low Opamp Bias Low 150 200 uA Power Low Opamp Bias High 300 400 uA Power Medium Opamp Bias Low 600 800 uA Power Medium Opamp Bias High 1200 1600 uA Power High Opamp Bias Low 2400 3200 uA Power High Opamp Bias High 4600 6400 uA PSRRo _ Supply Voltage Rejection Ratio
45. rammable Gain Amplifiers Programmable Filters and Comparators e 8 Analog channels for simultaneous sampling Up to 820 SPS for each channel with 8 channel sampling and logging a 16 Digital PSoC Blocks provide 8 to 32 bit timers counters and PWMs e CRC and PRS Modules Up to 4 Full Duplex UARTs e Multiple SPI Masters and Slaves o Complex Peripherals by Combining Blocks Cypress Semiconductor Corporation Document 001 43991 Rev D 198 Champion Court tween 100 KBPS and 1 MBPS a In System Serial Programming ISSP a Partial Flash Updates a Flexible Protection Modes a EEPROM Emulation in Flash Programmable Pin Configurations a 33 GPIOs a25 mA Sink on all GPIO a Pull up Pull down High Z Strong or Open Drain Drive Modes on all GPIO o Up to 12 Analog Inputs on GPIOs a Analog Outputs with 40 mA on 4 GPIOs a Configurable Interrupt on all GPIOs Additional System Resources a IC Slave Master and MultiMaster to 100 Kbps and 400 Kbps a Watchdog and Sleep Timers a Integrated Supervisory Circuit a On Chip Precision Voltage Reference Complete Development Tools a Free Development Software PSoC Designer a Full Featured In Circuit Emulator and Programmer a Full Speed Emulation aC Compilers Assembler and Linker Temperature and Packaging a Industrial Temperature Range 40 C to 85 C oa Packaging 100 pin TQFP San Jose CA 95134 1709 408 943 2600 Revised October 20 2008 Feedb
46. re measured through the Analog Continuous Time PSoC blocks The power levels for AGND refer to the power of the Analog Continuous Time PSoC block The power levels for RefHi and RefLo refer to the Analog Reference Control register The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block Reference control power is high Table 29 5V DC Analog Reference Specifications CY8CNP102E Symbol Description Min Typ Max Units VBG5 Bandgap Voltage Reference 5V 1 28 1 30 1 32 V JAGND Veal T Ve2 0 02 Veo2 Vec2 0 02 v AGND 2 x BandGapl 2 52 2 60 2 72 V AGND P2 4 P2 4 Vec 2 I7 P2 4 0 013 P2 4 P2 4 0 013 V JAGND BandG amp al era 184 AGND 1 6 x BandGapll 2 03 2 08 2 13 V AGND Block to Block Variation AGND Vcc 2 I7 0 034 0 000 0 034 V RefHi Vcc 2 BandGap Vcc 2 1 21 Vcc 2 1 3 Vcc 2 1 382 V RefHi 3 x BandGap 3 75 3 9 4 05 V RefHi 2 x BandGap P2 6 P2 6 1 3V P2 6 2 478 P2 6 2 6 P2 6 2 722 V RefHi P2 4 BandGap P2 4 Vcc 2 P2 4 1 218 P2 4 1 3 P2 4 1 382 V RefHi P2 4 P2 6 P2 4 Vcc 2 P2 6 1 3V P2 4 P2 6 0 058 P2 4 P2 6 P2 4 P2 6 0 058 V RefHi 2 x BandGap 2 50 2 60 2 70 V RefHi 3 2 x BandGap 4 02 4 16 4 29 V RefLo Vcc 2 BandGap Vcc 2 1 369 Vee 2 1 30 Vee 2 1
47. rite cycles per block Flashent Flash Endurance total 1 800 000 Erase write cycles Flashpr Flash Data Retention 10 Years Document 001 43991 Rev D Page 27 of 38 Feedback CYPRESS PRELIMINARY CY8CNP102B CY8CNP102E PERFORM AC Electrical Characteristics The following AC electrical specifications lists the guaranteed maximum and minimum specifications for the voltage and temperature range 4 75V to 5 25V over the Temperature range of 40 C lt T lt 85 C Typical parameters apply to 5V at 25 C and are for design guidance only AC Chip Level Specifications Table 33 5V AC Chip Level Specifications CY8CNP102E Symbol Description Min Typ Max Units Notes Fimo24 Internal Main Oscillator Frequency for 24 MHz 23 4 24 24 645 6I MHz Trimmed for 5V operation using factory trim values See Figure 5 on page 9 SLIMO Mode 0 Fimoe Internal Main Oscillator Frequency for 6 MHz 5 75 6 6 3559 MHz Trimmed for 5V operation using factory trim values See Figure 5 on page 9 SLIMO Mode 1 Foput CPU Frequency 5V Nominal 0 93 24 24 6451 MHz F48M Digital PSoC Block Frequency 0 48 49 245 7I MHz Refer to AC Digital Block Specifications on page 30 Foam Digital PSoC Block Frequency 0 24 24 657 MHz F32K1 Internal Low Speed Oscillator Frequency 15 32 64 kHz F32K2 External Crystal Oscillator 32 768 7 kHz Accuracy is capacitor and crystal
48. ss com solutions Clocks amp Buffers clocks cypress com Low Power Low Voltage psoc cypress com low power Wireless wireless cypress com Precision Analog psoc cypress com precision analog Memories memory cypress com LCD Drive psoc cypress com Icd drive Image Sensors image cypress com CAN 2 00 psoc cypress com can USB psoc cypress com usb Cypress Semiconductor Corporation 2008 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Any Source Code software and or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign United States copyright la
49. t GPIO 66 P2_2 IO l Direct Switched Capacitor Block Input GPIO 67 P2 4 10 External Analog GND GPIO 68 P2_6 IO External Voltage Ref GPIO 69 PO_O IO l Analog Column Mux Input GPIO 70 PO_2 IO 10 Analog Column Mux Input and Column Output 71 PO_4 IO IO Analog Column Mux Input and Column Output 72 73 NC Not connected on the die 74 PO_6 IO l Analog Column Mux Input GPIO 75 Vcc Power Supply Voltage 76 NV_O Connect to Pin 60 NV_O to EN_O 77 DNU Reserved for test modes Do Not Use 78 NC Not connected on the die Document 001 43991 Rev D Page 4 of 38 Feedback CYPRESS PRELIMINARY CY8CNP102B CY8CNP102E PERFORM Table 1 Pin Definitions 100 Pin TQFP continued Pin Number Pin Name Type Pin Definition Digital Analog 79 HSB Weak Pull up Connect 10kQ to Vcc 80 Vcc Power Supply Voltage 81 85 NC Not connected on the die 86 90 Vss Power Ground 91 98 NC Not connected on the die 99 NV_C Connect to Pin 61 NV_C to EN_C Weak Pull up Connect 10kQ to Vcc 100 PO_7 IO l Analog Column Mux Input GPIO PSoC NV Functional Overview The PSoC NV provides a versatile microcontroller core M8C Flash program memory nvSRAM data memory and configurable analog and digital peripheral blocks in a single package The flexible digital and analog lOs and routing matrix create a powerful embedded and flexible mixed signal System on Chip SoC The device incorporates confi
50. t is used alone or combined with other blocks to form 8 16 24 and 32 bit peripherals which are called user module references The digital peripheral configurations re m PWMs 8 to 32 bit m PWMs with dead band 8 to 32 bit m Counters 8 to 32 bit m Timers 8 to 32 bit m UART 8 bit with selectable parity up to 4 m SPI master and slave up to 4 each a C slave and multimaster 1 available as a System Resource m Cyclical Redundancy Checker and Generator 8 to 32 bit m IrDA up to 4 m Pseudo Random Sequence Generators 8 to 32 bit The digital blocks connect to any GPIO through a series of global buses that route any signal to any pin The buses also enable signal multiplexing and performing logic operations This configurability frees your designs from the constraints of a fixed peripheral controller Digital blocks are provided in rows of four where the number of blocks varies with PSoC device family This gives you the optimum choice of system resources for your application Programmable Analog System The analog system consists 12 configurable blocks each having an opamp circuit enabling the creation of complex analog signal flows Analog peripherals are very flexible and may be customized to support specific application requirements Some of the more common analog functions most available as user modules are m Analog to digital converters up to 4 with 6 to 14 bit resolution selectable as Incremen
51. tal Delta Sigma and SAR m Filters 2 4 6 or 8 pole band pass low pass and notch m Amplifiers up to 4 with selectable gain to 48x m Instrumentation amplifiers up to 2 with selectable gain to 93x m Comparators up to 4 with 16 selectable thresholds m DACs up to 4 with 6 to 9 bit resolution m Multiplying DACs up to 4 with 6 to 9 bit resolution m High current output drivers four with 40 mA drive as a Core Resource m 1 3V reference as a System Resource m DTMF Dialer m Modulators m Correlators Document 001 43991 Rev D m Peak Detectors m Other possible topologies m Analog blocks are provided in columns of three which includes one CT Continuous Time and two SC Switched Capacitor blocks Additional System Resources System Resources some of which are listed in the previous sections provide additional capability useful to complete systems Resources include a multiplier decimator switch mode pump low voltage detection and power on reset The merits of each system resource are m Digital clock dividers provide three customizable clock frequencies for use in applications The clocks may be routed to both the digital and analog systems Additional clocks are generated using digital PSoC blocks as clock dividers m Multiply Accumulate MAC provides fast 8 bit multiplier with 32 bit accumulate to assist in general math and digital filters m The decimator provides a custom hardware filt
52. te Imio Maximum Current into any 25 50 mA Port Pin IMAIo Maximum Current into any 50 50 mA Port Pin Configured as Analog Driver ESD Electro Static Discharge 2000 V Human Body Model ESD Voltage LU Latch up Current 200 mA Operating Temperature Table 23 5V Operating Temperature CY8CNP102E Symbol Description Min Typ Max Units Notes Ta Ambient Temperature 40 85 C Ty Junction Temperature 40 100 C Document 001 43991 Rev D Page 22 of 38 Feedback CYPRESS PRELIMINARY CY8CNP102B CY8CNP102E PERFORM DC Electrical Characteristics The following DC electrical specifications lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges 4 75V to 5 25V over the Temperature range of 40 C lt Ty lt 85 C Typical parameters apply to 5V at 25 C and are for design guidance only DC Chip Level Specifications Table 24 5V DC Chip Level Specifications CY8CNP102E Symbol Description Min Typ Max Units Notes Vcc Supply Voltage 4 75 5 25 V IDD Supply Current 39 45 mA Ta 25 C CPU 3 MHz SYSCLK doubler disabled VC1 1 5 MHz VC2 93 75 kHz VC3 0 366 kHz continuous nvSRAM access Ippp Supply current when IMO 6 MHz 27 28 mA Ta 25 C CPU 0 75 MHz using SLIMO mode SYSCLK doubler disabled VC1 0 375 MHz VC2 23 44 kHz VC3 0 09 kHz continuous nvSRAM access Isp Sleep Mode Current with POR 5 mA nvSRAM in standby LVD Slee
53. ut Hysterisis 60 mV liL Input Leakage Absolute Value 1 nA Gross tested to 1 uA CiN Capacitive Load on Pins as Input 3 5 10 pF Pin dependent Temp 25 C Court Capacitive Load on Pins as Output 3 5 10 pF Pin dependent Temp 25 C Document 001 43991 Rev D Page 11 of 38 Feedback PERFORM DC Operational Amplifier Specifications The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Capacitor PSoC blocks The guaranteed specifications are measured in the Analog Continuous Time PSoC block Table 7 3 3V DC Operational Amplifier Specifications CY8CNP102B PRELIMINARY CY8CNP102B CY8CNP102E Symbol Description Min Typ Max Units Notes Vosoa Input Offset Voltage absolute value High Power is 5 Volts Only Power Low Opamp Bias High 1 65 10 mV Power Medium Opamp Bias High 1 32 8 mV TCVosoa_ Average Input Offset Voltage Drift 7 0 35 0 uV C lEBOA Input Leakage Current Port 0 Analog 200 pA Gross tested to 1 uA Pins Cinoa Input Capacitance Port 0 Analog Pins 4 5 9 5 pF Pin dependent Temp 25 C Vemoa Common Mode Voltage Range 0 Vcc V CMRR oa Common Mode Rejection Ratio 60 7 dB GoLoa Open Loop Gain 80 dB VonicHoa High Output Voltage Swing internal Vcc 0 01 V signals VoLowoa Low Output Voltage Swing i
54. ws and international treaty provisions Cypress hereby grants to licensee a personal non exclusive non transferable license to copy use modify create derivative works of and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement Any reproduction modification translation compilation or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Cypress reserves the right to make changes without further notice to the materials described herein Cypress does not assume any liability arising out of the application or use of any product or circuit described herein Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress product in a life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Use may be limited by and subject to the
55. ycle User modules also provide tested software to cut your development time The user module Application Programming Interface API provides high level functions to control and respond to hardware events at run time The API also provides optional interrupt service routines that you can adapt as needed The API functions are documented in user module data sheets that are viewed directly in the PSoC Designer IDE These data sheets explain the internal operation of the user module and provide performance specifications Each data sheet describes the use of each user module parameter and documents the setting of each register controlled by the user module Document 001 43991 Rev D The development process starts when you open a new project and bring up the Device Editor which is a graphical user interface GUI for configuring the hardware Pick the user modules required for your project and map them onto the PSoC blocks with point and click simplicity Next build signal chains by interconnecting user modules to each other and to the IO pins At this stage configure the clock source connections and enter parameter values directly or by selecting values from drop down menus When you are ready to test the hardware configuration or develop code for the project perform the Generate Application step PSoC Designer generates source code that automatically configures the device to your specification and provides high level user module

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