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Cypress CY8C24094 User's Manual

1. o o Pin 9 y menn Pin S 2 DESCHDIT No 9 8 escription 9 escription a lt a lt A1 Vss Ground connection F1 NC No connection A2 Vss Ground connection F2 M P5 7 A3 NC No connection M P3 5 A4 NC No connection F4 M P5 1 A5 NC No connection F5 Power Vss Ground connection Vdd Supply voltage F6 Power Vss Ground connection AT NC No connection F7 M P5 0 A8 NC No connection F8 M P3 0 A9 Vss Ground connection F9 XRES Active high pin reset with internal pull down A10 Power Vss Ground connection F10 P7 1 B1 Power Vss Ground connection G1 NC No connection B2 Power Vss Ground connection G2 P5 5 P2 1 Direct switched capacitor block input G3 O M P3 3 B4 LM 1 Analog column input G4 O P1 7 I2C Serial Clock SCL B5 LM 7 Analog column input G5 M P1 1 I2C Serial Clock SCL ISSP SCLKTI Power Vdd Supply voltage G6 O P1 0 I2C Serial Data SDA ISSP SDATATT B7 LM 2 Analog column input G7 O P1 6 B8 ILM P2 2 Direct switched capacitor block input G8 P3 4 B9 Power Vss Ground connection G9 M P5 6 B10 Power Vss Ground connection G10 I O P7 2 C1 NC No connection H1
2. 00H 03506060 ZazazZzaz2Z2z22222222 gt 25 gt 02020A2 o NC 1 p NC NC 2 74 PO 0 M AI ALM PO 1 amp 73 NC M P2 7 4 72 P2 6 M External VREF M P2 5 5 71 NC Al M P2 3 6 70 P2 4 M External AGND ALM P2 1 7 69 P2 2 M AI 4 7 8 P2 0 M AI 4 5 m 9 67 B 4 6 M P4 3 m 10 65 P4 4 M M P4 1 65 Vss OCDE amp B 4 2 OCDO 63 P4 0 M NC 62 XRES Vss 61 CCLK M P3 7 60 HCLK M P3 5 59 P3 6 M M P3 3 58 a P3 4 M M P3 1 57 P3 2 M M P5 7 56 ja P3 0 M M P5 5 55 P5 6 M M P5 3 54 P5 4 M M P5 1 53 P5 2 M I2C SCL P1 7 52 P5 0 M NC 51 P1 6 M 3 6 996 Rap AAA aan 5 d X o o 70 o k e e Document Number 38 12018 Rev Page 16 of 47 Feedback PERFORM 9 Register Reference This section lists the registers of the CY8C24x94 PSoC device family For detailed register information reference the PSoC Programmable System on Chip Technical Reference Manual 9 1 Register Conventions The register conventions specific to this section are listed in the following table Convention Description Read register or bit s Write register or bit s Logical register or bit s Clearable register or bit s Access is bit specific Document Number 38 12018 Rev M CY8C24094 CY8C24794 CY8C24894 CY8C24994
3. F SS SSS 1 CY8C24094 CY8C24794 PERFORM Sales Solutions and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices solution centers manufacturer s representatives and distributors To find the office closest to you visit us at cypress com sales Products PSoC Solutions PSoC psoc cypress com General psoc cypress com solutions Clocks amp Buffers clocks cypress com Low Power Low Voltage psoc cypress com low power Wireless wireless cypress com Precision Analog psoc cypress com precision analog Memories memory cypress com LCD Drive psoc cypress com Icd drive Image Sensors image cypress com CAN 2 0b psoc cypress com can USB psoc cypress com usb Cypress Semiconductor Corporation 2004 2009 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury t
4. sess sez 4 5 OCDE OCD even data I O RANN 6 OCD odd data output 2 Power Vss Ground connection M 4 7 1 2 0 M 8 P3I7 M 4 5 2 P4 6 M p fra zm 10 o P3 3 OCDE 5 M 11 I O M P3 1 XRES 12 M P5 7 Ba 7 CCLK 13 O P5 5 M Pas QFN dale Psem 14 M P5 3 M P3I3 10 Top View 42 P3 4 M 15 M P5 1 M P3 1 11 41 P3 2 16 M P1 7 12 Serial Clock SCL dad T 2 P3 0 M 17 M P1 5 I2C Serial Data SDA M Paal E als S 18 M P1 3 M P5 1 e 15 P5I21 M 19 M P1 1 I2C Serial Clock SCL ISSP 12 SCL M 1 7 e 16 5 0 f M 20 Vss Ground connection I2C SDA M P1 5 We P1 6 M 21 USB D 22 USB D 3JKESNT ENES SR 23 Power Vdd Supply voltage a a Eee LAA a a a 24 P7 7 _ Pinbe 25 uo P7 6 3 2 7 E 26 P7 5 Q 27 P7 4 28 P7 3 29 P7 2 Pin Type ene 30 No Digital Analog 1275 Description 31 P7 0 50 M 4 6 32 M 1 0 12 Serial Data SDA ISSP SDATAU 51 10 Ll M P2 0 Direct switched capacitor block input 33 M P1 2 52 LM P2 2 Direct switched capacitor block input 34 M P1 4 Optional External Clock Input EXTCLK 53 M P2 4 External Analog Ground AGND input 35 M P1 6 54 I 0 M P2 6 External Voltage Re
5. 9 2 Register Mapping Tables The PSoC device has a total register address space of 512 bytes The register space is referred to as I O space and is divided into two banks The XOI bit in the Flag register CPU F determines which bank the user is currently in When the XOI bit is set the user is in Bank 1 Note In the following register mapping tables blank fields are Reserved and should not be accessed Page 17 of 47 Feedback CY8C24094 CY8C24794 CYPRESS CY8C24894 CY8C24994 PERFORM 9 3 Register Map Bank 0 Table User Space Name Addr 0 Hex Access Name Addr 0 Hex Access Name Addr 0 Hex Access Name Addr 0 Hex Access PRTODR 00 RW PMAO DR 40 RW ASC10CRO 80 RW CO PRTOIE 01 RW PMA1 DR 41 RW 5 81 RW C1 PRTOGS 02 RW PMA2 DR 42 RW 5 2 82 RW C2 PRTODM2 03 RW PMA3 DR 43 RW 83 RW C3 PRTIDR RW 05 RW PMA5 DR 45 RW ASD11CR1 85 RW 5 PRT1GS 06 RW PMA6_DR 46 RW ASD11CR2 86 RW C6 PRT1DM2 07 RW DR 47 RW 7 PRT2DR 08 RW N 88 8 PRT2IE 09 RW USB SOF1 89 C9 PRT2GS 0A RW USB CRO 8A CA PRT2DM2 RW USBI O CRO 8B CB PRT3DR OC RW USBI O CR1 8C CC PRISE 00 RW 19 1 D RW E H 8E E PRT3DM2 OF RW EP1 CNT 8F CF PRT4DR 10 RW EP2 CNT1 ASD20CRO 90 RW CUR PP DO RW
6. Value for PPOR Trip negative ramp Vppogo PORLEV 1 0 00b 2 82 V PPOR1 PORLEV 1 0 016 4 39 V PPOR2 PORLEV 1 0 10b 4 55 V PPOR Hysteresis PORLEV 1 0 00b 92 mV PORLEV 1 0 01b 0 PH2 PORLEV 1 0 10b 0 Vdd Value for LVD Trip VM 2 0 000b 286 292 298 v VM 2 0 001b 2 96 3 02 3 08 V LVD2 VM 2 0 010b 3 07 13 13 3 20 V LVD3 VM 2 0 011b 3 92 14 00 4 08 V LVD4 VM 2 0 100b 4 39 14 48 4 57 V wwps VM 2 0 101b 4 55 4 64 47411 v LVD6 VM 2 0 110b 4 63 14 73 4 82 V LVD7 VM 2 0 111b 4 72 14 81 4 91 V V Notes 6 Always greater than 50 mV above PPOR PORLEV 00 for falling supply 7 Always greater than 50 mV above PPOR PORLEV 10 for falling supply Document Number 38 12018 Rev M Page 28 of 47 Feedback EF CY8C24094 CY8C24794 SES Cypress CY8C24894 CY8C24994 PERFORM 10 3 10 DC Programming Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges 4 75V to 5 25V and 40 C x Ta x 85 or 3 0V to 3 6V and 40 C lt Ta lt 85 respectively Typical parameters apply to 5V and 3 3V at 25 and are for design guidance only Table 10 15 DC Programming Specifications Symbol Description Min Typ Max Units Notes Ippp Supply Current During Programming or Verify 15 30 mA
7. Input Low Voltage During Programming or 0 8 V Verify Viup Input High Voltage During Programming or 2 1 V Verify lu p Input Current when Applying Vilp to P1 0 or 0 2 mA Driving internal pull down P1 1 During Programming or Verify resistor Input Current when Applying Vihp to P1 0 1 5 mA Driving internal pull down P1 1 During Programming or Verify resistor Output Low Voltage During Programming Vss V Verify 0 75 Output High Voltage During Programming 1 0 Vdd V Verify Flashenp Flash Endurance per block 50 000 Erase write cycles block B Flashent Flash Endurance total 1 800 0 Erase write cycles 00 Flashpg Flash Data Retention 10 Years Note 8 Amaximum of 36 x 50 000 block endurance cycles is allowed This may be balanced between operations on 36x1 blocks of 50 000 maximum cycles each 36x2 blocks of 25 000 maximum cycles each or 36x4 blocks of 12 500 maximum cycles each to limit the total number of cycles to 36x50 000 and that no single block ever sees more than 50 000 cycles For the full industrial range the user must employ a temperature sensor user module FlashTemp and feed the result to the temperature argument before writing Refer to the Flash APIs Application Note AN2015 at http www cypress com under Application Notes for more information Document Number 38 12018 Rev M Page 29 of 47 Feedback PERFORM 10 4
8. TF BF CPU SCRO FF Blank fields are Reserved and should not be accessed Access is bit specific Document Number 38 12018 Rev M Page 18 of 47 Feedback CYPRESS PERFORM 9 4 Register Map Bank 1 Table Configuration Space CY8C24094 CY8C24794 CY8C24894 CY8C24994 Name Addr 1 Hex Access Name Addr 1 Hex Access Name Addr 1 Hex Access Name Addr 1 Access PRTODMO 00 RW PMAO WA 40 RW ASC10CRO 80 RW USBI O_CR2 CO RW PRTODM1 01 RW PMA1_WA 41 RW ASC10CR1 81 RW USB_CR1 C1 PRTOICO 02 RW PMA2_WA 42 RW ASC10CR2 82 RW PRTOIC1 03 RW PMA3_WA 43 RW ASC10CR3 83 RW PRT1DMO 04 RW PMA4_WA 44 RW ASD11CRO 84 RW EP1 CRO C4 PRT1DM1 05 RW PMA5 WA 45 RW ASD11CR1 85 RW EP2 CRO C5 PRT1ICO 06 RW PMA6 WA 46 RW ASD11CR2 86 RW EP3 CRO C6 PRT1IC1 07 RW PMA7 WA 47 RW ASD11CR3 87 RW EP4 CRO C7 PRT2DMO 08 RW 48 88 C8 PRT2DM1 09 RW 49 89 C9 PRT2ICO 0A RW 4A 8A CA PRT2IC1 0B RW 4B 8B CB PRT3DMO OC RW 4C 8C cc PRT3DM1 00 RW 4D 8D CD PRT3ICO OE RW 4E PRT3IC1 OF RW 4F 8F CF PRT4DM0 10 RW PMAO RA 50 RW 90 GDI O IN DO RW PRT4DM1 11 RW PMA1 RA 51 RW ASD20CR1 91 RW GDI E IN D1 RW PRTAICO 12 RW PMA2 RA 52 RW ASD20CR2 92 RW GDI O OU D2 RW PRTAIC1 13 RW PMA3 RA 53 RW ASD20CR3 93 RW GDI E OU D3 RW PRT5DMO 14 RW PMA4 RA 54 RW AS
9. o P 5 8 amp S 3 54 39 55 E 59 85 5 5 3 S 20 sd 9 9 o o9 g s x hs lt lt g 56 Pin 8x8 mm QFN CY8C24794 24LFXI 16K 1K 40 C to 85 C 4 6 50 48 2 56 Pin 8x8 mm QFN CY8C24794 24LFXIT 16K 1K 40 to 85 4 6 50 48 2 No Tape and Reel 56 Pin 8x8 mm QFN CY8C24894 24LFXI 16K 1K 40 to 85 C 4 6 49 47 2 Yes 56 Pin 8x8 mm QFN CY8C24894 24LFXIT 16K 1K 40 C to 85 C 4 6 49 47 2 Yes Tape and Reel 68 Pin OCD 8x8 mm 21 Cy8C24094 24LFXI 16K 1K 40 C to 85 4 6 56 48 2 Yes 68 Pin 8x8 mm QFN CY8C24994 24LFXI 16K 1K 40 C to 85 4 6 56 48 2 Yes 68 Pin 8x8 mm QFN CY8C24994 24LFXIT 16K 1K 40 C to 85 4 6 56 48 2 Yes Tape and Reel 68 Pin QFN Sawn CY8C24994 24LT XI 16K 1K 40 C to 85 C 4 6 56 48 2 Yes 68 Pin QFN Sawn CY8C24994 24LTXIT 16K 1K 40 C to 85 C 4 6 56 48 2 Yes 100 Ball OCD 6x6 mm CY8C24094 24BVXI 16K 1K 40 C to 85 C 4 6 56 48 2 Yes VFBGAP I 100 Ball 6x6 mm VFBGA CY8C24994 24BVXI 16K 1K 40 to 85 4 6 56 48 2 Yes 100 Pin OCD CY8C24094 24AXI 16K 1K 40 to 85 4 6 56 48 2 Yes 68 Pin QFN Sawn CY8C24094 24LT XI 16K 1K 40 C to 85 4 6 56 48 2 Yes 68 Pin QFN Sawn CY8C24094 24LTXIT 16K 1K 40 C to 85 C 4 6 56 48 2 Yes Note For Die sales information contact a local Cypress sale
10. 3 EgZETS KRSr re 20 USB D aaia 21 USB D gt 22 Power Supply voltage o 2 3 23 WO P7 7 SN OS k 24 WO P7 0 22 z 25 I O M P1 0 12C Serial Data SDA ISSP SDATAIT 26 I O M P1 2 27 I O M P1 4 Optional External Clock Input EXTCLK 28 I O M P1 6 29 I O M P5 0 Pin Type Name Description 30 I O M P5 2 No Digital Analog 31 I O M P5 4 44 I O M P2 6 External Voltage Reference VREF input 32 I O M P5 6 45 I O M PO 0 Analog column mux input 33 I O M P3 0 46 I O I M PO 2 Analog column mux input 34 I O M P3 2 47 I O M PO 4 Analog column mux input VREF 35 I O M P3 4 48 I O I M PO 6 Analog column mux input 36 I O M P3 6 49 Power Vdd _ Supply voltage 37 I O M 4 0 50 Vss Ground 38 I O M P4 2 51 I O I M PO 7 Analog column mux input 39 I O M P4 4 52 VO PO 5 Analog column mux input and column output 40 I O M 4 6 53 I O PO 3 Analog column input and column output 41 I O I M P2 0 Direct switched capacitor block input 54 VO M PO 1 Analog column input 42 I O l M P2 2 Direct switched capacitor block input 55 VO M P2 7 43 I O M P2 4 External Analog Ground AGND input 56 I O M P2 5 Document Number 38 12018 Rev M Page 8 of 47 Feedback a CY8C24094 CY8C24794 F CYPRESS CY8C24894 CY8C24994 PERFORM 8 1 56 Pin Part Pinout with XRES Table 8 2 56 Part
11. Feedback PERFORM 10 3 7 DC Analog Reference Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges 4 75V to 5 25V and 40 C x Ta x 85 or 3 0V to 3 6V and 40 C lt Ta lt 85 respectively Typical parameters apply to 5V and 3 3V at 25 and are for design guidance only The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks The power levels for AGND refer to the power of the Analog Continuous Time PSoC block The power levels for RefHi and RefLo refer to the Analog Reference Control register The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block Reference control power is high Table 10 11 5V DC Analog Reference Specifications CY8C24094 CY8C24794 CY8C24894 CY8C24994 Symbol Description Min Typ Max Units BG Bandgap Voltage Reference 1 28 1 30 1 32 V AGND Vdd 214 5 Vdd 2 0 04 Vdd 2 0 01 Vdd 2 0 007 V AGND 2 x BandGapl 5 2 x BG 0 048 2 x BG 0 030 2 x BG 0 024 V AGND P2 4 P2 4 Vdd 2 4 5 2 4 0 011 P2 4 P2 4 0 011 V AGND BandGapl 51 BG 0 009 BG 0 008 BG 0 016 V AGND 1 6 x SI 1 6 x BG 0 022 1 6xBG 0 010 1 6xBG 0 018 V AGND Block to Block Variat
12. Symbol Description Min Typ Max Units Notes TRoB Rising Settling Time to 0 196 1V Step 100pF Load 2 5 us Power Low 2 5 us Power High Falling Settling Time to 0 1 1V Step 100pF Load 2 2 us Power Low 2 2 us Power High 5 Rising Slew Rate 20 to 80 1V Step 100 pF Load 0 65 V us Power Low 0 65 V us Power High SRfog Falling Slew Rate 80 to 20 1V Step 100 pF Load 0 65 V us Power Low 0 65 V us Power High BWogss Small Signal Bandwidth 20mV BW 100 pF Load 0 8 MHz Power Low 0 8 2 Power High BWog s Large Signal Bandwidth 1V BW 100 pF Load 300 kHz Power Low 300 kHz Power High Document Number 38 12018 Rev M Page 35 of 47 Feedback 8 24094 CY8C24794 CYPRESS CY8C24894 CY8C24994 PERFORM Table 10 25 3 3V AC Analog Output Buffer Specifications Symbol Description Min Typ Max Units Notes TRoB Rising Settling Time to 0 1 1V Step 100 pF Load 3 8 us Power Low 3 8 us Power High Falling Settling Time to 0 1 1V Step 100 pF Load 2 6 us Power Low 2 6 us Power High Rising Slew Rate 20 to 80 1V Step 100 pF Load 0 5 V us Power Low 0 5 V us Power High SReog Slew Rate 80 to 20 1V Step 100 pF Load 0 5 V us Power Low 0 5 V us Power High BWogs
13. M 2 CYPRESS 53 1 Features m XRES Pin to Support In System Serial Programming ISSP and External Reset Control in CY8C24894 m Powerful Harvard Architecture Processor M8C Processor Speeds to 24 MHz Two 8x8 Multiply 32 Bit Accumulate Low Power at High Speed 3V to 5 25V Operating Voltage Industrial Temperature Range 40 C to 85 C USB Temperature Range 10 to 85 m Advanced Peripherals PSoc Blocks 6 Rail to Rail Analog PSoC Blocks Provide Up to 14 Bit ADCs Up to 9 Bit DACs Programmable Gain Amplifiers Programmable Filters and Comparators a 4 Digital PSoC Blocks Provide 8 to 32 Bit Timers Counters and PWMs CRC and PRS Modules Full Duplex UART Multiple SPI Masters or Slaves Connectable to all GPI O Pins Complex Peripherals by Combining Blocks Capacitive Sensing Application Capability CY8C24094 CY8C24794 CY8C24894 CY8C24994 PERFORM Programmable System on Chip T m Full Speed USB 12 Mbps Four Uni Directional Endpoints One Bi Directional Control Endpoint USB 2 0 Compliant Dedicated 256 Byte Buffer No External Crystal Required Flexible On Chip Memory 16K Flash Program Storage 50 000 Erase and Write Cycles 1K SRAM Data Storage In System Serial Programming ISSP Partial Flash Updates Flexible Protection Modes EEPROM Emulation in Flash Programmable Pin Configurations 25 mA Si
14. PERFORM Table 8 6 100 Ball Part Pinout VFBGA continued CY8C24094 CY8C24794 CY8C24894 CY8C24994 C8 LM P2 0 Direct switched capacitor block input H8 M P3 2 C9 P4 2 H9 10 5 4 C10 NC No connection H10 I O P7 3 D1 NC No connection J1 Vss Ground connection 02 M P3 7 J2 Power Vss Ground connection P4 5 J3 USB D D4 M P2 5 44 USB D 05 VO PO 3 Analog column mux input and column output J5 Power Vdd Supply voltage 06 1 0 LM Analog column mux input J6 P7 7 D7 M P2 6 External Voltage Reference VREF input J7 P7 0 08 M P4 6 J8 M P5 2 D9 M P4 0 49 Vss Ground connection D10 CCLK OCD CPU clock output J10 Power Vss Ground connection E1 NC No connection K1 Power Vss Ground connection E2 NC No connection K2 Power Vss Ground connection M 4 3 K3 NC No connection E4 LM P2 3 Direct switched capacitor block input 4 No connection E5 Vss Ground connection K5 Power Vdd Supply voltage Power Vss Ground connection K6 P7 6 E7 M P2 4 External Analog Ground AGND input WO P7 5 E8 l O P4 4 K8 P7 4 E9 10 M P3 6 K9 Power Vss Ground connection E10 HCLK OCD high speed clock output K10
15. 31 NC No connection 81 O 1 6 Analog column mux input 32 Power Vss Ground connection 82 Power Vdd Supply voltage 33 USB D 83 NC No connection 34 USB D 84 Vss Ground connection 35 Power Vdd Supply voltage 85 NC No connection 36 P7 7 86 NC No connection 37 P7 6 87 NC No connection 38 P7 5 88 NC No connection 39 P7 4 89 NC No connection 40 l O P7 3 90 NC No connection 41 10 P7 2 91 NC No connection 42 10 P7 1 92 NC No connection 43 10 P7 0 93 NC No connection 44 NC No connection 94 NC No connection 45 NC No connection 95 L M PO 7 Analog column mux input 46 NC No connection 96 NC No connection 47 NC No connection 97 PO 5 Analog column input and column output 48 P1 0 Crystal XTAL gut I2C Serial Data SDA 98 NC No connection ISSP SDATAM 49 10 P1 2 99 i PO 3 Analog column mux input and column output 50 P1 4 Optional External Clock Input EXTCLK 100 NC No connection Document Number 38 12018 Rev M Page 15 of 47 Feedback a CY8C24094 CY8C24794 7 Cypress CY8C24894 CY8C24994 PERFORM Table 8 7 100 Pin Part Pinout TQFP continued LEGENDA Analog Input Output NC No Connection M Analog Input OCD On Chip Debugger Figure 8 7 CY8C24094 OCD Not for Production lt lt lt lt lt lt gt gt 5 KR c
16. Update copyright and trademarks 561158 HMT Add Low Power Comparator LPC AC DC electrical spec tables Add CY8C20x34 to PSoC Device Characteristics table Add detailed dimensions to 56 pin QFN package diagram and update revision Secure one package diagram manufacturing per QFN Update emulation pod feet kit part numbers Fix pinout type o per TestTrack J 728238 See ECN HMT Add CapSense SNR requirement reference Update figure standards Update Technical Training paragraphs Add QFN package clarifications and dimensions Update ECN ed Amkor dimensioned QFN package diagram revisions Reword SNR reference Add new 56 pin QFN spec K 2552459 08 14 08 AZIE PYRS Add footnote on AGND descriptions to avoid using P2 4 for digital signaling as it may add noise to AGND Remove reference to CMP GO EN1 in Map Bank 1 Table on Address 65 this register has no functionality on 24xxx Add footnote on die sales Add description Optional External Clock Input on P1 4 to match description of P1 4 L 2616550 12 05 08 OGNE PYRS Updated Programmable Pin Configuration detail Changed title from PSoC Mixed Signal Array to PSoC amp Programmable System on Chip M 2657956 02 11 09 DPT PYRS Added package diagram 001 09618 and updated Ordering Information table Document Number 38 12018 Rev M Page 46 of 47 Feedback CYPRESS CY8C24894 CY8C24994 ET
17. gt Design Resources gt Application Notes In general and unless otherwise noted in the relevant Application Notes the minimum signal to noise ratio SNR for CapSense applications is 5 1 Document Number 38 12018 Rev M Page 3 of 47 Feedback PERFORM 3 1 Additional System Resources System Resources provide additional capability useful to complete systems Additional resources include a multiplier decimator low voltage detection and power on reset Brief state ments describing the merits of each resource follow m Full Speed USB 12 Mbps with 5 configurable endpoints and 256 bytes of RAM No external components required except two series resistors Wider than commercial temperature USB operation 10 to 85 m Digital clock dividers provide three customizable clock frequencies for use in applications The clocks can be routed to both the digital and analog systems Additional clocks are generated using digital PSoC blocks as clock dividers m Two multiply accumulates MACs provide fast 8 bit multipliers with 32 bit accumulate to assist in both general math and digital filters m Decimator provides a custom hardware filter for digital signal processing applications including creation of Delta Sigma ADCs m Thel2C module provides 100 and 400 kHz communication over two wires Slave master multi master are supported m Low Voltage Detection LVD interrupts signal the application of falling voltage l
18. 0 5 Vdd 1 0 V Rourop Output Resistance Power Low 0 6 W Power High 0 6 W High Output Voltage Swing Load 32 ohms B to Vdd 2 0 5 x Vdd V Power Low 1 1 V Power High 0 5 x Vdd 1 1 VoLowoB Low Output Voltage Swing Load 32 ohms to Vdd 2 0 5 x Vdd V Power Low 1 3 V Power High 0 5 x Vdd 1 3 Supply Current Including Bias Cell No Load Power Low 1 1 5 1 mA Power High 2 6 8 8 mA PSRRog Supply Voltage Rejection Ratio 53 64 dB 0 5 x Vdd 1 3 lt Vout lt Vdd 2 3 Table 10 10 3 3V DC Analog Output Buffer Specifications Symbol Description Min Typ Max Units Notes VosoB Input Offset Voltage Absolute Value 3 12 mV TCVoso Average Input Offset Voltage Drift 6 uV P c Common Mode Input Voltage Range 0 5 Vdd 1 0 V Rourop Output Resistance Power Low 1 W Power High 1 W High Output Voltage Swing Load 1K ohms B to Vdd 2 0 5 x Vdd V Power Low 1 0 V Power High 0 5 x Vdd 1 0 Vorowop Low Output Voltage Swing Load 1K ohms to Vdd 2 0 5 x Vdd V Power Low 1 0 V Power High 0 5 x Vdd 1 0 Isop Supply Current Including Bias Cell No Load Power Low 0 8 2 0 mA Power High 2 0 4 3 mA PSRRog Supply Voltage Rejection Ratio 34 64 0 5 x Vdd 1 0 lt Vgyr lt 0 5 x Vdd 0 9 Document Number 38 12018 Rev M Page 25 of 47
19. 11 RW EP2 CNT 51 RW TK PP D1 RW 4 12 RW EP3 CNT1 52 ASD20CR2 92 RW D2 PRT4DM2 13 RW EP3 CNT 53 RW IDX PP D3 RW PREDR 14 RW MYR PP 54 RW PRISE 75 RW MWPP DS RW 5 16 RW EPO CR 56 ASC21CR2 96 RW CF D6 RW 78 1 RW 75 pop 18 m ees vs EPO DR2 5A RW 9A INT CLRO DA RW 1 mv eom oc NER RW 10 mv epe jun RW RW NT MSKS DE RW PRTIDWI TF RW TNT SKZ DF RW DEBUUDRU 20 NT SKU EO RW DEBUDDRT 7 W RT SK ET RW DEBUDDRI 27 RW TV E2 R DBBOOCRO 23 CR 63 RW A3 RES WDT W DBBO1DRO 24 CMP CRO 64 DEC DH E4 RC DEBUIDRT 25 W DECDL t5 R DBBO1DR2 26 RW MP CR1 66 RW A6 DEC CRO E6 RW DCBO2DRO 28 68 MUL1 X A8 MULO X E8 W DCBO2DR1 29 W 69 MUL1 Y A9 MULO Y E9 W DCBO2DR2 2A RW 6A MUL1 DH AA MULO DH EA R DCBO2CRO 2B GJ MUL1 DL AB R MULO DL EB R DCBO3DRO 2 TMP DRO 6 RW ACC1 DR1 ACCO DR1 E RW DCBO3DR1 2D W TMP RW ACC1 DRO ACCO DRO ED RW DCBO3DR2 2E RW TMP DR2 RW ACC1 DR3 ACCO DR3 EE RW DCBO3CRO 2F TMP_DR3 RW DR2 ACCO DR2 EF RW 30 ACBOOCR3 RW RDIORI FO 31 ACBOOCRO RW RDIOSYN F1 32 ACBOOCR1 RW RDIOIS F2 33 ACBOOCR2 RW RDIOLTO F3 34 ACBOTCR3 RW RDIOLT1 F4 35 ACBOTCRO RW RDIOROO F5 36 ACBOTCR1 RW RDIORO1 F6 37 ACBOTCR2 RW CPU_F F7 RL 38 F8 39 79 B9 F9 3A 3B 7B BB FB 7C BC FC 3D 7D BD DAC D FD RW 3E CPU SCR1 FE
20. AC Electrical Characteristics 10 4 1 AC Chip Level Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges 4 75V to 5 25V and 40 x Ta x 85 or 3 0V to 3 6V and 40 C lt Ta x 85 respectively Typical parameters apply to 5V and 3 3V at 25 and are for design guidance only CY8C24094 CY8C24794 CY8C24894 CY8C24994 Table 10 16 AC Chip Level Specifications Symbol Description Min Typ Max Units Notes 245 Internal Main Oscillator Frequency for 24 MHz 23 04 24 24 960 10 MHz Trimmed for 5V operation 5V using factory trim values Fimoz43v_ Internal Main Oscillator Frequency for 24 MHz 22 08 24 25 920011 MHz Trimmed for 3 3V operation 3 3V using factory trim values Fimousss Internal Main Oscillator Frequency with USB 23 94 24 24 0612 2 10 lt Ta lt 85 v SV 4 35 lt Vdd lt 5 15 Frequency locking enabled and USB traffic present Fimousss Internal Main Oscillator Frequency with USB 23 94 24 24 0612 2 0 x TA x 70 V 3 3V 3 15 lt Vdd lt 3 45 Frequency locking enabled and USB traffic present Fceu1 CPU Frequency 5V Nominal 0 93 24 24 96 1071 MHz Fopy2 _ CPU Frequency 3 3V Nominal 0 93 12 12 9610 MHz 5 Digital PSoC Block Frequency 5V Nominal 0 48 49 929 102 MHz Refer to the AC Digital Block Speci
21. CY8C24994 YPRESS PERFORM When bypassed by a capacitor on P2 4 the noise of the analog ground signal distributed to each block is reduced by a factor of up to 5 14 dB This is at frequencies above the corner frequency defined by the on chip 8 1k resistance and the external capacitor Figure 10 4 Typical AGND Noise with P2 4 Bypass dBV rtHz 10000 1000 100 i 0 1 Freq kHz 1 0 001 0 01 by device geometry At high At low frequencies the opamp noise is proportional to 1 f power independent and determined frequencies increased power level reduces the noise spectrum level Figure 10 5 Typical Opamp Noise nV rtHz 10000 1000 100 10 0 001 mew 4 Page 33 of 47 Document Number 38 12018 Rev M Feedback a CY8C24094 CY8C24794 cypress CY8C24894 CY8C24994 PERFORM 10 0 1 AC Low Power Comparator Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges 4 75V to 5 25V and 40 lt Ta x 85 C 3 0V to 3 6V and 40 C lt Ty lt 85 C or 2 4V to 3 0V and 40 C lt Ta x 85 C respectively Typical parameters apply to 5V at 25 C and are for design guidance only Table 10 21 AC Low Power Comparator Specifications Symbol Description Min Typ Max Units Notes TRLPC LPC response time 50 US gt 50 mV overdrive comparator reference set within Vref pc
22. IN MILLIMETERS 16 000 25 50 R 0 08 MIN 0 MIN 0 20 T el el S STAND OFF a 0 05 MIN m 015 GAUGE PLANE 0 20 MAX DETAIL A 0 50 0 15 25 1 100 REF 25 50 NOTE PKG CAN HAVE m SEATING PLANE OR 160 MAX mo L 140405 LEFT CORNER CHAMFER 4 CORNERS CHAMFER 020 MAX 51 85048 C SEE DETAIL A Document Number 38 12018 Rev M Page 40 of 47 Feedback PERFORM 11 1 Thermal Impedance Table 11 1 Thermal Impedance for the Package Package Typical 15 56 6 12 93 C W 68 QFNIS 13 05 C W 100 VFBGA 65 C W 100 51 C W 11 2 Solder Reflow Peak Temperature Following is the minimum solder reflow peak temperature to achieve good solderability CY8C24094 CY8C24794 CY8C24894 CY8C24994 Table 11 2 Solder Reflow Peak Temperature Package Minimum Peak Temperature Maximum Peak Temperature 56 QFN 2409C 2609C 68 QFN 2409C 2609C 100 VFBGA 2409C 2609C Notes Refer to the solder manufacturer specifications Document Number 38 12018 Rev M 15 Tj TA POWER x 16 To achieve the thermal impedance specified for the QFN package the center thermal pad should be soldered to the PCB ground plane 17 Higher temperatures may be required based on the solder melting point Typical temperatures for
23. Output 3 5 10 pF Package and pin dependent Temp 25 C Note 3 Standby current includes all functions POR LVD WDT Sleep Time needed for reliable system operation This should be compared with devices that have similar functions enabled Document Number 38 12018 Rev M Page 22 of 47 Feedback Fm CY8C24094 CY8C24794 cypress CY8C24894 CY8C24994 PERFORM 10 3 3 DC Full Speed USB Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges 4 75V to 5 25V and 10 C lt Ta x 85 or 3 0V to 3 6V and 10 C lt Ta lt 85 respectively Typical parameters apply to 5V and 3 3V at 25 and are for design guidance only Table 10 6 DC Full Speed 12 Mbps USB Specifications Symbol Description Min Typ Max Units Notes USB Interface Differential Input Sensitivity 0 2 V D D Vem Differential Input Common Mode Range 0 8 2 5 V Vse Single Ended Receiver Threshold 0 8 2 0 V CiN Transceiver Capacitance 20 pF High Z State Data Line Leakage 10 10 OV lt Vin lt 3 3V Rext External USB Series Resistor 23 25 W In series with each USB pin Static Output High Driven 2 8 3 6 V 15 5 to Ground Internal pull up enabled Static Output High Idle 2 7 3 6 V 15 596 to Ground Internal pull up enabled VuoL Static Output Low 0 3 V 1
24. Pinout QFN 2 Pin Type Name Description Figure 8 2 CY8C24894 56 Pin PSoC Device No Digital Analog 1 I O M P2 3 Direct switched capacitor block input 2 IM P2 1 Direct switched capacitor block input 26g 2222 3 I O M P4 7 lt lt lt lt CLEE 4 I O M P4 5 GEZEEE ESErZEBEDtE OD OO DUOCOCGOCOSO o Q 5 4 3 0 E OBL QE BOR Q D Bo 6 vo 12128155559045 7 VO M P37 ALM P23 9 EDNT 8 VO M P3 5 A M 21 m2 41m P2 0 A I M 9 o M Pai Wed ER uM 10 vo M P3 i pap EE pac m 11 I O M P5 7 M P4 1 6 37d P4 0 M 12 I O M P5 5 M P3 7 QFN 36g XRES 13 vo M P5I3 up Top View 2 14 I O M P5 1 M P UM 15 I O M P1 7 I2C Serial Clock SCL M PS 7 GL M 16 I O M P1 5 12 Serial Data SDA M P5 5 4j M 17 I O M P1 3 M 5 3 2 18 M P1 1 12 Serial Clock SCL ISSP 5 M PS 1 0 M 19 Power Vss Ground connection 20 USB D 5 21 USB D 22 Power Supply voltage 3 3 5 23 10 P7 7 MEA 24 VO P7 0 gt 2 25 I O M 1 0 I2C Serial Data SDA ISSP SDATAT E B 26 I O M P1 2 27 I O M P1 4 Optional Exter
25. Timer WDT at high temperature I oscillator Vdd 3 3V 55 lt Ta lt 85 analog power off 10 3 2 DC General Purpose Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges 4 75V to 5 25V and 40 x Ta x 85 or 3 0V to 3 6V and 40 lt Ta lt 85 respectively Typical parameters apply to 5V and 3 3V at 25 and are for design guidance only Table 10 5 DC GPI O Specifications Symbol Description Min Typ Max Units Notes Rpy Pull Up Resistor 4 5 6 8 Rpp Pull Down Resistor 4 5 6 8 kQ VoH High Output Level Vdd V 10 mA Vdd 4 75 to 5 25 8 1 0 total loads 4 on even pins for example PO 2 P1 4 4 on odd port pins for example PO 3 P1 5 80 mA maximum combined budget VoL Low Output Level 0 75 V 25 mA Vdd 4 75 to 5 25V 8 total loads 4 on even port pins for example PO 2 P1 4 4 on odd port pins for example PO 3 P1 5 200 mA maximum combined I OL budget Vi Input Low Level 0 8 V Vdd 3 0 to 5 25 Input High Level 2 1 V Vdd 3 0 to 5 25 Vu Input Hysterisis 60 mV lu Input Leakage Absolute Value 1 nA Gross tested to 1 uA Cin Capacitive Load on Pins as Input 3 5 10 pF Package and pin dependent Temp 25 Cour Capacitive Load on Pins as
26. components are called drivers and correspond to inputs a thermistor for example outputs a brushless DC fan for example communication interfaces 12 for example and the logic to control how they interact with one another called valuators In the chip level view the components are called user modules User modules make selecting and implementing peripheral devices simple and come in analog digital and mixed signal varieties 6 2 Configure Components Each of the components you select establishes the basic register settings that implement the selected function They also provide parameters and properties that allow you to tailor their precise configuration to your particular application For example a Pulse Width Modulator PWM User Module configures one or more digital PSoC blocks one for each 8 bits of resolution The user module parameters permit you to establish the pulse width and duty cycle Configure the parameters and properties to correspond to your chosen application Enter values directly or by selecting values from drop down menus Both the system level drivers and chip level user modules are documented in data sheets that are viewed directly in the PSoC Designer These data sheets explain the internal operation of the component and provide performance specifications Each data sheet describes the use of each user module parameter or driver property and other information you may need to successfully
27. includes an LCD module potentiometer LEDs an enunciator and plenty of bread boarding space to meet all of your evaluation needs The kit includes m PSoCEvalUSB Board m LCD Module m MiniProg Programming Unit m Mini USB Cable m PSoC Designer and Example Projects CD m Getting Started Guide m Wire Pack 12 5 Accessories Emulation and Programming Table 12 1 Emulation and Programming Accessories CY8C24094 CY8C24794 CY8C24894 CY8C24994 12 4 Device Programmers All device programmers can be purchased from the Cypress Online Store 12 4 1 CY3216 Modular Programmer The CY3216 Modular Programmer kit features a modular programmer and the MiniProg1 programming unit The modular programmer includes three programming module cards and supports multiple Cypress products The kit includes m Modular Programmer Base m 3 Programming Module Cards m MiniProg Programming Unit m PSoC Designer Software CD m Getting Started Guide m USB 2 0 Cable 12 4 2 CY3207ISSP In System Serial Programmer ISSP The CY3207ISSP is a production programmer It includes protection circuitry and an industrial case that is more robust than the MiniProg in a production programming environment Note CY3207ISSP needs special software and compatible with PSoC Programmer The kit includes is not m CY3207 Programmer Unit m PSoC ISSP Software CD m 110 240V Power Supply Euro Plug Adapter m USB 2 0 Cable Part Pin Package Flex Pod Kit Foo
28. of system resources for your application Family resources are shown in Table 3 1 on page 4 Page 2 of 47 Feedback PERFORM 3 1 The Analog System The Analog System is composed of 6 configurable blocks each comprised of an opamp circuit allowing the creation of complex CY8C24094 CY8C24794 CY8C24894 CY8C24994 Figure 3 2 Analog System Block Diagram IO Exce pt Port 7 NS analog signal flows Analog peripherals are very flexible and can dat e be customized to support specific application requirements Some of the more common PSoC analog functions most 1 e available as user modules are listed below PO 3 gr PO m Analog to digital converters up to 2 with 6 to 14 bit resolution iis selectable as Incremental Delta Sigma and SAR 2 P2 3 gt Sx E m Filters 2 and 4 pole band pass low pass and notch lt m Amplifiers up to 2 with selectable gain to 48x P2 3 P2 m Instrumentation amplifiers 1 with selectable gain to 93x m Comparators up to 2 with 16 selectable thresholds m DACs up to 2 with 6 to 9 bit resolution m Multiplying DACs up to 2 with 6 to 9 bit resolution anm poros i H H m High current output drivers two with 30 mA drive as a PSoC i ACIO 1 0 ACH 1 0 Core Resource GER REO
29. programming file for a specific PSoC device 5 1 2 Chip Level View The chip level view is a more traditional integrated development environment IDE based on PSoC Designer 4 4 Choose a base device to work with and then select different onboard analog and digital components called user modules that use the PSoC blocks Examples of user modules are ADCs DACs Amplifiers and Filters Configure the user modules for your chosen application and connect them to each other and to the proper pins Then generate your project This prepopulates your project with APIs and libraries that you can use to program your application The device editor also supports easy development of multiple configurations and dynamic reconfiguration Dynamic configuration allows for changing configurations at run time 5 1 3 Hybrid Designs You can begin in the system level view allow it to choose and configure your user modules routing and generate code then switch to the chip level view to gain complete control over on chip resources All views of the project share a common code editor builder and common debug emulation and programming tools Document Number 38 12018 Rev M CY8C24094 CY8C24794 CY8C24894 CY8C24994 5 1 4 Code Generation Tools PSoC Designer supports multiple third party C compilers and assemblers The code generation tools work seamlessly within the PSoC Designer interface and have been tested with a full range of debugging too
30. 0 25 0 25 Document Number 38 12018 Rev M Page 31 of 47 Feedback a CY8C24094 CY8C24794 SES cypress CY8C24894 CY8C24994 PERFORM 10 0 2 AC Operational Amplifier Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges 4 75V to 5 25V and 40 C x Ta x 85 or 3 0V to 3 6V and 40 C lt Ta lt 85 respectively Typical parameters apply to 5V and 3 3V at 25 and are for design guidance only Settling times slew rates and gain bandwidth are based on the Analog Continuous Time PSoC block Power High and Opamp Bias High is not supported at 3 3V Table 10 19 5V AC Operational Amplifier Specifications Symbol Description Min Typ Max Units Rising Settling Time from 80 of AV to 0 1 of AV 10 pF load Unity Gain Power Low Opamp Bias Low 3 9 us Power Medium Opamp Bias High 0 72 us Power High Opamp Bias High 0 62 us TsoA Falling Settling Time from 20 of AV to 0 1 of AV 10 pF load Unity Gain Power Low Opamp Bias Low 5 9 us Power Medium Opamp Bias High 0 92 us Power High Opamp Bias High 0 72 us SRroa Rising Slew Rate 20 to 80 10 pF load Unity Gain 0 15 V us Power Low Opamp Bias Low 1 7 V us Power Medium Opamp Bias High 6 5 V us Power High Opamp Bias High SRroA Falling Rate 20 to 80 10 pF load Unit
31. 10 0 2 AC Digital Block Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges 4 75V to 5 25V and 40 C x Ta x 85 C or 3 0V to 3 6V and 40 C lt Ta x 85 C respectively Typical parameters apply to 5V and 3 3V at 25 are for design guidance only Table 10 22 AC Digital Block Specifications Function Description Min Typ Max Units Notes Timer Capture Pulse Width 50131 ns Maximum Frequency No Capture 49 92 2 4 75V Vdd lt 5 25V Maximum Frequency With Capture 25 92 2 Counter Enable Pulse Width 501131 ns Maximum Frequency No Enable Input 49 92 2 4 75V Vdd lt 5 25V Maximum Frequency Enable Input 25 92 2 Dead Kill Pulse Width Band Asynchronous Restart Mode 20 ns Synchronous Restart Mode 501131 ns Disable Mode 501181 ns Maximum Frequency 49 92 2 4 75V Vdd lt 5 25V CRCPRS Maximum Input Clock Frequency 49 92 2 4 75V lt Vdd lt 5 25V PRS Mode CRCPRS Maximum Input Clock Frequency 24 6 2 Mode SPIM Maximum Input Clock Frequency 8 2 2 Maximum data rate at 4 1 MHz due to 2 x over clocking SPIS Maximum Input Clock Frequency 4 1 2 Width of SS_ Negated Between Transmissions 5011381 ns Trans Maximum Input Clock Frequency 24 6 MHz Maximum data
32. 11 8 100 319 S ee Ny 2 24 0 009 977 EN 0 300 012 Lasoo 0 600 024 SEATING PLANE 0 50 0 020 6 45 0 254 6 55 0 258 NOTES 1 AREA IS SOLDERABLE EXPOSED METAL 2 REFERENCE JEDEC MO 220 3 PACKAGE WEIGHT 0 162g 4 ALL DIMENSIONS ARE IN MM MIN MAX 5 PACKAGE CODE DESCRIPTION LF56A STANDARD LY56A PB FREE 001 12921 Page 38 of 47 Document Number 38 12018 Rev M Feedback CY8C24094 CY8C24794 2 Cypress CY8C24894 CY8C24994 Figure 11 2 68 Pin 8x8 mm x 0 89 mm QFN TOP VIEW SIDE VIEW BOTTOM VIEW 7 90 0 311 8 10 0 319 gt o oa c 0 05 0 002 MAX 1 REF 5 69 7 70 0 303 0 9 0 035 MAX 7 80 0 307 PIN1 ID 0 70 0 028 MAX 0 20 R XD MA RRS 5 69 7 70 0 303 7 80 0 307 7 90 0 311 6 50 0 255 REF 8 10 0 319 FOO AAR J 0 24 0 009 0 40 0 015 0 60 0 0235 0 50 0 020 0 4 B S C 6 50 0 255 REF NOTES 1 HATCH IS SOLDERABLE EXPOSED PAD 2 REFERENCE JEDEC MO 220 3 PACKAGE WEIGHT 0 17g NOTE EXPOSED PAD DIMENSION VARIES BY LEADFRAME CAVITY PADDLE SIZE 4 ALL DIMENSIONS ARE IN MM MIN MAX 5 PACKAGE CODE PART DESCRIPTION LF68 STANDARD 51 85214 C LY68 PB FREE Important Note m For information on the preferred dimensions for mounting QFN packages see the foll
33. 3 39 5 6 M 18 M P1 3 M 5 3 14 38 P5 4 M 5 1 15 372 5 2 19 2 Serial Clock SCL ISSP I2C SCL M P 7 e 16 360m 50 M 20 Vss Ground connection 12 SDA M 1 5 17 35E 1 6 M CO O O WN Oo r QN Oc x E 21 USB 0 ON CN ON QNI CON OI QN ON 0 22 USB D SoSA As 23 Power Vdd Supply voltage gt EERE ran 24 P7 7 25 0 P7 6 3 o N 26 10 P7 5 d e ul 27 MO P7 4 28 P7 3 29 P7 2 Pin Type US N D t 30 7 1 No Digital Analog 27 SUD 31 P7 0 50 M P4 6 32 M 1 0 I2C Serial Data SDA ISSP 51 LM P2 0 Direct switched capacitor block input 33 M P1 2 52 LM P2 2 Direct switched capacitor block input 34 M P1 4 Optional External Clock Input EXTCLK 53 M P2 4 External Analog Ground AGND input 35 M P1 6 54 M P2 6 External Voltage Reference VREF input 36 M P5 0 55 LM PO 0 Analog column input 37 M P5 2 56 LM PO 2 Analog column mux input and column output 38 M P5 4 57 LM PO 4 Analog column mux input and column output 39 M P5 6 58 LM PO 6 Analog column mux input 40 U O M P3 0 59 Power Vdd Supply voltage 41 M P3 2 60 Power Vss Ground connecti
34. 5 5 to Ground Internal pull up enabled Zo USB Driver Output Impedance 28 44 W Including Resistor Vers D D Crossover Voltage 1 3 2 0 V 10 3 4 DC Operational Amplifier Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges 4 75V to 5 25V and 40 C x Ta x 85 C or 3 0V to 3 6V and 40 C lt Ta x 85 C respectively Typical parameters apply to 5V and 3 3V at 25 and are for design guidance only The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Capacitor PSoC blocks The guaranteed specifications are measured in the Analog Continuous Time PSoC block Table 10 7 5V DC Operational Amplifier Specifications Symbol Description Min Typ Max Units Notes Vosoa Input Offset Voltage absolute value Power Low Opamp Bias High 1 6 10 mV Power Medium Opamp Bias High 1 3 8 mV Power High Opamp Bias High 1 2 7 5 mV TCVosoa Average Input Offset Voltage Drift x 7 0 35 0 uV c Input Leakage Current Port 0 Analog Pins 20 Gross tested to 1 uA Input Capacitance Port 0 Analog Pins 4 5 9 5 pF Package and pin dependent Temp 259C Common Mode Voltage Range 0 0 Vdd V The common mode input voltage Common Mode Voltage Range high power 9 5 _ Vdd range is measu
35. 8 bit resource used alone or combined with other blocks to form 8 16 24 and 32 bit peripherals which are called user module references Figure 3 1 Digital System Block Diagram a a E Port 0 To System Bus Digital Clocks From Core To Analog System DIGITAL SYSTEM Digital PSoC Block Array Row 0 4 DBBOO DCBO2 DCBO3 Y Y Y Y 4 gt Global Digital Interconnect Row Input Configuration indino GIE 7 0 GIO 7 0 GOE 7 0 GOO 7 0 Digital peripheral configurations include those listed below m Full Speed USB 12 Mbps m PWMs 8 to 32 bit m PWMs with Dead band 8 to 24 bit m Counters 8 to 32 bit m Timers 8 to 32 bit m UART 8 bit with selectable parity m SPI master and slave m 12 slave and multi master m Cyclical Redundancy Checker Generator 8 to 32 bit m IrDA m Pseudo Random Sequence Generators 8 to 32 bit The digital blocks are connected to any GPI O through a series of global buses that can route any signal to any pin The buses also allow signal multiplexing and performing logic operations This configurability frees the designs from the constraints of a fixed peripheral controller Digital blocks are provided in rows of four where the number of blocks varies by PSoC device family This allows you the optimum choice
36. C21CRO 94 RW D4 PRT5DM1 15 RW 5 RA 55 RW ASC21CR1 95 RW D5 PRTSICO 16 RW PMA6 RA 56 RW ASC21CR2 96 RW D6 PRTSIC1 17 RW PMA7 RA 57 RW ASC21CR3 97 RW D7 18 58 98 MUX CRO D8 RW 19 59 99 MUX CR1 D9 RW 1A 5A 9A MUX CR2 DA RW 1B 5B 9B MUX CR3 DB RW PRT7DMO 1C RW 5 9C DC PRT7DM1 1D RW 5D 9D OSC GO EN DD RW PRT7ICO 1E RW 5E 9E OSC CR4 DE RW PRT7IC1 1F RW 5F 9F OSC CR3 DF RW DBBOOFN 20 RW CLK CRO 60 RW A0 OSC CRO EO RW DBBOOIN 21 RW CLK CR1 61 RW A1 OSC CR1 E1 RW DBBOOOU 22 RW ABF_CRO 62 RW A2 OSC_CR2 E2 RW 23 AMD_CRO 63 RW A3 VLT_CR E3 RW DBBO1FN 24 RW CMP_GO_EN 64 RW A4 VLT CMP 4 R DBBO1IN 25 RW 65 A5 E5 DBB010U 26 RW AMD CR1 66 RW A6 E6 27 ALT CRO 67 RW A7 E7 DCBO2FN 28 RW 68 A8 IMO TR E8 w DCBO2IN 29 RW 69 A9 ILO TR E9 Ww DCB020U 2A RW 6A AA BDG TR EA RW 2B 6B AB ECO TR EB DCBO3FN 2C RW TMP DRO 6c RW AC MUX CR4 EC RW DCBO3IN 2D RW TMP DR1 6D RW AD MUX CR5 ED RW DCB030U 2E RW TMP DR2 6E RW AE 2F TMP DR3 6F RW AF EF 30 ACBOOCR3 70 RW RDIORI BO RW FO 31 ACBOOCRO 71 RW RDIOSYN B1 RW F1 32 ACBOOCR1 72 RW RDIOIS B2 RW F2 33 ACBOOCR2 73 RW RDIOLTO B3 RW 34 ACBO1CR3 74 RW RDIOLT1 B4 RW F4 35 ACBO1CRO 75 RW RDIOROO B5 RW F5 36 ACBO1CR1 76 RW RDIORO1 B6 RW F6 37 ACBO1CR2 77 RW B7 CPU F F7 RL 38 78 B8 F8 39 79 B9 F9 3A 7A BA FA 3B 7B BB FB 3C 7C BC FC 3D 7D BD DAC_CR FD RW 3E 7E BE CPU_SCR1 FE 3F 7F BF CPU SCRO FF Blank fields are Reserved and should not be acces
37. G 0 015 V AGND 1 6 x 5 1 6 x BG 0 027 1 6xBG 0 010 1 6xBG 0 018 V AGND Column to Column Variation AGND 0 034 0 000 0 034 V 2 5 RefHi Vdd 2 BandGap Not Allowed RefHi 3 x BandGap Not Allowed RefHi 2 x BandGap P2 6 P2 6 0 5V Not Allowed RefHi P2 4 BandGap P2 4 Vdd 2 Not Allowed RefHi P2 4 P2 6 P2 4 Vdd 2 P2 6 0 5V P2 4 P2 6 2 4 P2 6 P2 4 P2 6 V 0 075 0 009 0 057 Document Number 38 12018 Rev M Page 26 of 47 Feedback ER CY8C24094 CY8C24794 CY8C24894 CY8C24994 PERFORM Table 10 12 3 3V DC Analog Reference Specifications continued Symbol Description Min Typ Max Units RefHi 3 2 x BandGap Not Allowed RefLo Vdd 2 BandGap Not Allowed RefLo BandGap Not Allowed RefLo 2 x BandGap P2 6 P2 6 0 5V Not Allowed RefLo P2 4 BandGap P2 4 Vdd 2 Not Allowed RefLo P2 4 P2 6 P2 4 Vdd 2 2 6 0 5V P2 4 P2 6 P2 4 P2 6 P2 4 P2 6 V 0 048 0 022 0 092 10 3 8 DC Analog PSoC Block Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges 4 75V to 5 25V and 40 C x Ta lt 85 C or 3 0V to 3 6V and 40 C lt Ta x 85 C respectively Typical parameters apply to 5V and 3 3V at 25 and are for design guidance only T
38. NC No connection C2 M P4 1 H2 O IM 5 3 C3 M P4 7 H3 O IM 1 M P2 7 H4 O IM P1 5 I2C Serial Data SDA C5 I O M PO 5 Analog column input and column output H5 P1 3 C6 LM 6 Analog column mux input H6 M P1 2 C7 LM 0 Analog column input H7 WO M P1 4 Optional External Clock Input EXTCLK C8 LM 2 0 Direct switched capacitor block input H8 M P3 2 C9 M P4 2 H9 O IM P5 4 C10 NC No connection H10 1 0 P7 3 D1 NC No connection J1 Power Vss Ground connection D2 1 0 M P3 7 J2 Power Vss Ground connection P4 5 J3 USB D D4 W O M 2 5 J4 USB D D5 l O M PO S Analog column mux input and column output J5 Power Vdd Supply voltage D6 LM Analog column input J6 l O P7 7 D7 M P2 6 External Voltage Reference VREF input J7 10 P7 0 D8 M 4 6 J8 P5 2 D9 I O M 4 0 J9 Power Vss Ground connection D10 NC No connection J10 Vss Ground connection E1 NC No connection K1 Power Vss Ground connection E2 NC No connection K2 Power Vss Ground connection P4 3 K3 NC No connection E4 LM 2 3 Direct switched capacitor block input K4 NC No connection E5 Power Vss Ground connection K5 Power Vdd Supply voltage Vss Ground connection K6 P7 6 E7 P2 4 External A
39. Power Vss Ground connection LEGENDA Analog Input Output Analog Input NC No Connection OCD On Chip Debugger Figure 8 6 CY8C24094 OCD Not for Production Document Number 38 12018 Rev M m gt N o GJ 9 9 COGO OD OD DD OD DOOOGOGODOME oo Q 90999999 OOOQOOOOO CODD ODD DD CO QD OOOOOOOOO DA DOOOAAOME Page 14 of 47 Feedback PERFORM 8 1 100 Pin Part Pinout On Chip Debug The 100 pin TQFP part is for the CY8C24094 On Chip Debug OCD PSoC device Note This part is only used for in circuit debugging It is NOT available for production Table 8 7 100 Pin Part Pinout TQFP CY8C24094 CY8C24794 CY8C24894 CY8C24994 o o Pin 2 Descriptio Pin 2 lt Description gt ption amp 8 puo lt lt 1 51 IM 1 6 2 No connection 52 M P5 0 3 lO M PO 1 Analog column mux input 53 11 0 IM P5 2 4 VO 2 7 54 WO M P5 4 5 I O 2 5 55 WO M P5 6 6 M P2 3 switched capac
40. R m 1 3V reference as a System Resource m DTMF Dialer T _ c ERN m Modulators ason B m Correlators i m Peak Detectors LI LI m Many other topologies possible Analog blocks are arranged in a column of three which includes L 22000 Reri anon AGNDIn one CT Continuous Time and two SC Switched Capacitor PP ID 2 WR blocks as shown in Figure 3 2 pp M8C Interface Address Bus Data Bus Etc 3 0 1 The Analog Multiplexer System The Analog Mux Bus can connect to every GPI O pin in ports 0 5 Pins are connected to the bus individually or in any combination The bus also connects to the analog system for analysis with comparators and analog to digital converters It is split into two sections for simultaneous dual channel processing An additional 8 1 analog input multiplexer provides a second path to bring Port 0 pins to the analog array Switch control logic enables selected pins to precharge continu ously under hardware control This enables capacitive measurement for applications such as touch sensing Other multiplexer applications include m Track pad finger sensing m Chip wide mux that allows analog input from up to 48 I O pins m Crosspoint connection between any I O pin combinations When designing capacitive sensing applications refer to the latest signal to noise signal level requirements Application Notes which are found under http www cypress com
41. Vrms microvolts root mean square V volts Document Number 38 12018 Rev M Page 20 of 47 Feedback 8 24094 CY8C24794 7 Cypress CY8C24894 CY8C24994 PERFORM 10 1 Absolute Maximum Ratings Table 10 2 Absolute Maximum Ratings Symbol Description Min Typ Max Units Notes TsrG Storage Temperature 55 25 100 Higher storage temperatures reduces data retention time Recom mended storage temperature is 25 25 Extended duration storage temperatures above 65 degrades reliability TA Ambient Temperature with Power Applied 40 85 C Vdd Supply Voltage on Vdd Relative to Vss 0 5 6 0 V Vio DC Input Voltage Vss Vdd V 0 5 0 5 Vio2 DC Voltage Applied to Tri state Vss Vdd V 0 5 0 5 Maximum Current into any Port Pin 25 50 mA Maximum Current into any Port Pin 50 50 Configured as Analog Driver ESD Electro Static Discharge Voltage 2000 V Human Body Model ESD LU Latch up Current 200 mA 10 2 Operating Temperature Table 10 3 Operating Temperature Symbol Description Min Typ Max Units Notes TA Ambient Temperature 40 85 C Tausp Ambient Temperature using USB 10 85 C Ty Junction Temperature 40 100 The temperature rise from ambient to junction is package specific See Thermal Impedance on page 41 The user must limit the power consumption to co
42. able 10 13 DC Analog PSoC Block Specifications Symbol Description Min Typ Max Units Notes Resistor Unit Value Continuous Time 12 2 Csc Capacitor Unit Value Switched Capacitor 80 Note 4 AGND tolerance includes the offsets of the local buffer in the PSoC block Bandgap voltage is 1 3V 0 02V 5 Avoid using P2 4 for digital signaling when using an analog resource that depends on the Analog Reference Some coupling of the digital signal may appear on the Page 27 of 47 Document Number 38 12018 Rev M Feedback PERFORM 10 3 9 DC POR and LVD Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges 4 75V to 5 25V and 40 lt Ty lt 85 C or 3 0V to 3 6V and 40 C lt Ty x 85 C respectively Typical parameters apply to 5V or 3 3V at 25 and are for design guidance only Note The bits PORLEV and VM in the table below refer to bits in the VLT CR register See the PSoC Programmable System on Chip Technical Reference Manual for more information on the VLT CR register Table 10 14 DC POR and LVD Specifications CY8C24094 CY8C24794 CY8C24894 CY8C24994 Symbol Description Min Typ Max Units Notes Vdd Value for PPOR Trip positive ramp Vpporor PORLEV 1 0 00b 2 91 V PPOR1R PORLEV 1 0 01b 4 39 V PPOR2R PORLEV 1 0 10b 4 55 V
43. ates the CY8C24x94 PSoC device family pins and pinout configuration The CY8C24x94 PSoC devices are available in the following packages all of which are shown on the following pages Every port pin labeled with a is capable of Digital However Vss Vdd and XRES are not capable of Digital I O 8 1 56 Pin Part Pinout Table 8 1 56 Pin Part Pinout QFN See LEGEND details and footnotes in Table 8 2 on page 9 Pini Type Name cesis Figure 8 1 CY8C24794 56 Pin PSoC Device No Digital Analog 1 Vo I M P2 3 Direct switched capacitor block input 2 2 LM P2 1 Direct switched capacitor block input lt lt lt lt lt lt lt lt 4 nannna gt gt aanannnane 5 I O M P4 3 6 I O M 1 2 2 A I M 7 vo M P3 7 2 4 OLA I M 8 lo M P3 5 40 6 M 4 39 4 M 9 I O M P3 3 5 28 21 M 10 I O M P3 1 6 37 01 11 I O M P5 7 y QFN 36 61 M 12 1 0 M P5 5 8 Top View 35 4 M 13 VO M P5 3 es A p 14 WO M P5 a SUM 15 I O M P1 7 2 Serial Clock SCL 31 4 M 16 I O M P1 5 12 Serial Data SDA 30 2 17 I O M P1 3 29 0 M 18 I O M P1 1 12 Serial Clock SCL ISSP 19 Power Vss Ground connection 5 8
44. d links to FAQs and an Online Support Forum to aid the designer in getting started 5 2 In Circuit Emulator A low cost high functionality ICE In Circuit Emulator is available for development support This hardware has the capability to program single devices The emulator consists of a base unit that connects to the PC by way of a USB port The base unit is universal and operates with all PSoC devices Emulation pods for each device family are available separately The emulation pod takes the place of the PSoC device in the target board and performs full speed 24 MHZ operation Page 5 of 47 Feedback PERFORM 6 Designing with PSoC Designer The development process for the PSoC device differs from that of a traditional fixed function microprocessor The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification change during development and by lowering inventory costs These configurable resources called PSoC Blocks have the ability to implement a wide variety of user selectable functions The PSoC development process can be summarized in the following four steps 1 Select components 2 Configure components 3 Organize and Connect 4 Generate Verify and Debug 6 1 Select Components Both the system level and chip level views provide a library of prebuilt pretested hardware peripheral components In the system level view these
45. er Comparator Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges 4 75V to 5 25V and 40 x Ta x 85 C 3 0V to 3 6V and 40 lt Ty x 85 C or 2 4V to 3 0V and 40 C lt Ta x 85 C respectively Typical parameters apply to 5V at 25 and are for design guidance only Table 10 8 DC Low Power Comparator Specifications Symbol Description Min Typ Max Units Notes Low power comparator LPC reference 0 2 Vdd 1 V voltage range lai pc LPC supply current 10 40 Vosipc LPC voltage offset 2 5 30 mV Document Number 38 12018 Rev M Page 24 of 47 Feedback E CY8C24094 CY8C24794 CYPRESS CY8C24894 CY8C24994 PERFORM 10 3 6 DC Analog Output Buffer Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges 4 75V to 5 25V and 40 C x Ta x 85 or 3 0V to 3 6V and 40 C lt Ta lt 85 respectively Typical parameters apply to 5V and 3 3V at 25 and are for design guidance only Table 10 9 5V DC Analog Output Buffer Specifications Symbol Description Min Typ Max Units Notes VosoB Input Offset Voltage Absolute Value 3 12 mV TCVoso Average Input Offset Voltage Drift 6 uV C B Common Mode Input Voltage Range
46. evelopment kits can be purchased from the Cypress Online Store 12 2 1 CY3215 DK Basic Development Kit The CY3215 DK is for prototyping and development with PSoC Designer This kit supports in circuit emulation and the software interface allows users to run halt and single step the processor and view the content of specific memory locations Advance emulation features also supported through PSoC Designer The kit includes m PSoC Designer Software CD m ICE Cube In Circuit Emulator m ICE Flex Pod for CY8C29x66 Family m Cat 5 Adapter m Mini Eval Programming Board m 110 240V Power Supply Euro Plug Adapter Document Number 38 12018 Rev M CY8C24094 CY8C24794 CY8C24894 CY8C24994 m iMAGEcraft C Compiler Registration Required m ISSP Cable m USB 2 0 Cable and Blue Cat 5 Cable m 2 CY8C29466 24PXI 28 PDIP Chip Samples 12 2 2 CY3210 ExpressDK PSoC Express Development Kit The CY3210 ExpressDK is for advanced prototyping and devel opment with PSoC Express may be used with ICE Cube In Circuit Emulator It provides access to 2 buses voltage reference switches upgradeable modules and more The kit includes m PSoC Express Software CD m Express Development Board m 4 Fan Modules m 2 Proto Modules m MiniProg In System Serial Programmer m MiniEval PCB Evaluation Board m Jumper Wire Kit m USB 2 0 Cable m Serial Cable DB9 m 110 240V Power Supply Euro Plug Adapter m 2 CY8C24423A 24PXI 28 PDIP Chip Samp
47. evels while the advanced POR Power On Reset circuit eliminates the need for a system supervisor m An internal 1 3V reference provides an absolute reference for the analog system including ADCs and DACs m Versatile analog multiplexer system 3 2 PSoC Device Characteristics Depending on your PSoC device characteristics the digital and analog systems can have 16 8 or 4 digital blocks and 12 6 or 4 analog blocks The following table lists the resources available for specific PSoC device groups The device covered by this data sheet is shown in the highlighted row of the table Table 3 1 PSoC Device Characteristics PSoCPart BS 89 52 38 88 3 Se se 50 52 155 2 55 lt SN Number ES 80 DES ES ex ue es o a Of Om lt lt 0 lt lt u CY8C29x66 upto 4 16 12 4 4 12 2K 32K 64 CY8C27x43 upto 2 8 12 4 4 12 256 16K 44 Bytes CY8C24x94 56 1 4 48 2 2 6 1K 16K CY8C24x23A upto 1 4 12 2 2 6 256 4K 24 Bytes CY8C21x34 upto 1 4 28 0 2 411 512 8K 28 Bytes CY8C21x23 16 1 4 8 0 2 41 256 4 Bytes CY8C20x34 upto 0 28 0 o 1382 1512 8 28 Bytes Document Number 38 12018 Rev M CY8C24094 CY8C24794 CY8C24894 CY8C24994 4 Getting Started The quickest way to understand PSoC silicon is to read this data sheet and then use the PSoC Designer Integrated Development Environment IDE This data sheet is an
48. ference VREF input 36 M 5 0 55 Ll M PO 0 Analog column mux input 37 M P5 2 56 l O LM PO 2 Analog column input and column output 38 M P5 4 57 O Ll M PO 4 Analog column mux input and column output 39 M P5 6 58 l O Ll M PO 6 Analog column input 40 l O M P3 0 59 Power Vdd Supply voltage 41 M P3 2 60 Power Vss Ground connection 42 10 M P3 4 61 l O Ll M PO 7 Analog column input integration input 1 43 10 M P3 6 62 I O M 5 Analog column input and column output integration input 2 44 HCLK OCD high speed clock output 63 I O M 0 3 Analog column input and column output 45 CCLK OCD CPU clock output 64 Ll M PO 1 column mux input 46 Input XRES Active high pin reset with internal pull 65 M P2 7 down 47 M O M P4 0 66 M P2 5 48 10 M P4 2 67 l O Ll M P2 3 Direct switched capacitor block input 49 10 M 4 4 68 Ll M P2 1 Direct switched capacitor block input LEGENDA Analog Input Output M Analog Input OCD On Chip Debugger Document Number 38 12018 Rev M Page 11 of 47 Feedback a CY8C24094 CY8C24794 F CYPRESS CY8C24894 CY8C24994 PERFORM 8 1 100 Ball VFBGA Part Pinout The 100 ball VFBGA part is for the CY8C24994 PSoC device Table 8 5 100 Ball Part Pinout VFBGA
49. fications Digital PSoC Block Frequency 3 3V Nominal 0 24 25 92110 72 MHz F32k1 Internal Low Speed Oscillator Frequency 15 32 64 kHz Jitter32k 32 kHz Period Jitter 100 ns Step24M 24 MHz Trim Step Size 50 kHz Fout48M 48 MHz Output Frequency 46 08 48 0 49 92911 MHz Trimmed Utilizing factory trim values Jitter24M 24 MHz Period Jitter IMO Peak to Peak 300 ps 1 FMAX Maximum frequency of signal on row input or 12 96 MHz row output TRAMP Supply Ramp Time 0 us Figure 10 2 24 MHz Period Jitter IMO Timing Diagram Jitter24M1 Notes 9 4 75V lt Vdd lt 5 25V 10 Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range 11 3 0V Vdd 3 6V See Application Note AN2012 Adjusting PSoC Microcontroller Trims for Dual Voltage Range Operation for information on trimming for operation at 3 3V 12 See the individual user module data sheets for information on maximum frequencies for user modules Document Number 38 12018 Rev M Page 30 of 47 Feedback Fm CY8C24094 CY8C24794 DWP Cypress CY8C24894 CY8C24994 PERFORM 10 0 1 AC General Purpose I O Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges 4 75V to 5 25V and 40 C lt Ta lt 85 or 3 0V to 3 6V and 40 C lt Ta lt 85 C respectively Typical parameters apply to 5V and 3 3V at 25 and are for design
50. gns that include firmware and hardware design files that enable you to complete your designs quickly 4 6 Technical Support For assistance with technical issues search KnowledgeBase articles and forums at www cypress com support If you cannot find an answer to your question call technical support at 1 800 541 4736 Page 4 of 47 Feedback PERFORM 5 Development Tools PSoC Designer is a Microsoft Windows based integrated development environment for the Programmable System on Chip PSoC devices The PSoC Designer IDE runs on Windows XP or Windows Vista This system provides design database management by project an integrated debugger with In Circuit Emulator in system programming support and built in support for third party assemblers and C compilers PSoC Designer also supports C language compilers developed specifically for the devices in the PSoC family 5 1 PSoC Designer Software Subsystems 5 1 1 System Level View A drag and drop visual embedded system design environment based on PSoC Express In the system level view you create a model of your system inputs outputs and communication inter faces You define when and how an output device changes state based upon any or all other system devices Based upon the design PSoC Designer automatically selects one or more PSoC Mixed Signal Controllers that match your system requirements PSoC Designer generates all embedded code then compiles and links it into a
51. guidance only Table 10 17 AC GPI O Specifications Symbol Description Min Typ Max Units Notes GPI O Operating Frequency 0 12 MHz Normal Strong Mode TRiseF Rise Time Normal Strong Mode Cload 50 pF 3 18 ns 4 5 to 5 25V 10 90 TFallF Fall Time Normal Strong Mode Cload 50 pF 2 18 ns Vdd 4 5 to 5 25V 10 90 1 1 TRiseS Rise Time Slow Strong Mode Cload 50 pF 27 ns 3 to 5 25V 10 90 TFallS Fall Time Slow Strong Mode Cload 50 pF 22 ns 3 to 5 25V 10 90 Figure 10 3 Timing Diagram 90 GPIO Pin Output Voltage 10 TRiseF TFallF TRiseS TFallS 10 0 1 AC Full Speed USB Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges 4 75V to 5 25V and 10 C x Ta x 85 or 3 0V to 3 6V and 10 lt Ta lt 85 respectively Typical parameters apply to 5V and 3 3V at 25 and are for design guidance only Table 10 18 AC Full Speed 12 Mbps USB Specifications Symbol Description Min Typ Max Units Notes Tres Transition Rise Time 4 20 ns For 50 pF load Tess Transition Fall Time 4 20 ns For 50 pF load Tremes Rise Fall Time Matching 90 111 For 50 pF load Tpraters Full Speed Data Rate 12 12 12 Mbps
52. hardware events at run time and interrupt service routines that you can adapt as needed The system level design also generates a C main program that completely controls the chosen application and contains placeholders for custom code at strategic positions allowing you to further refine the software without disrupting the generated code A complete code development environment allows you to develop and customize your applications in C assembly language or both The last step in the development process takes place inside the PSoC Designers Debugger subsystem The Debugger downloads the HEX image to the In Circuit Emulator ICE where it runs at full speed Debugger capabilities rival those of systems costing many times more In addition to traditional single step run to breakpoint and watch variable features the Debugger provides a large trace buffer and allows you define complex breakpoint events that include monitoring address and data bus values memory locations and external signals Page 6 of 47 Feedback PERFORM 7T Document Conventions 7 1 Acronyms Used The following table lists the acronyms that are used in this document Acronym Description AC alternating current ADC analog to digital converter API application programming interface CPU central processing unit CT continuous time DAC digital to analog converter DC direct current ECO exte
53. implement your design Document Number 38 12018 Rev M CY8C24094 CY8C24794 CY8C24894 CY8C24994 6 3 Organize and Connect You can build signal chains at the chip level by interconnecting user modules to each other and the I O pins or connect system level inputs outputs and communication interfaces to each other with valuator functions In the system level view selecting a potentiometer driver to control a variable speed fan driver and setting up the valuators to control the fan speed based on input from the pot selects places routes and configures a programmable gain amplifier PGA to buffer the input from the potentiometer an analog to digital converter ADC to convert the potentiometer s output to a digital signal and a PWM to control the fan In the chip level view perform the selection configuration and routing so that you have complete control over the use of all on chip resources 6 4 Generate Verify and Debug When you are ready to test the hardware configuration or move on to developing code for the project perform the Generate Application step This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the software for the system Both system level and chip level designs generate software based on your design The chip level design provides application programming interfaces APIs with high level functions to control and respond to
54. inouts 2 MACs Change 512 bytes of SRAM to 1K Add dimension key to package Remove HAPI Update diagrams registers and specs C 335236 HMT Add CY logo Update CY copyright Update new CY com URLs Re add ISSP programming pinout notation Add Reflow Temp table Update features MAC Oscillator and voltage range registers INT CLR2 MSK2 second MAC and specs Rext IMO analog output buffer D 344318 See HMT Add new color and logo Expand analog arch diagram Fix I O Update Electrical Specifications E 346774 HMT Add USB temperature specifications Make data sheet Final 349566 HMT Remove USB logo Add URL to preferred dimensions for mounting MLF packages G 393164 See HMT Add new device CY8C24894 56 pin MLF with XRES pin Add Fimousb3v char to specs Upgrade to CY Perform logo and update corporate address and copyright H 469243 HMT Add ISSP note to pinout tables Update typical and recommended Storage Temperature per industrial specs Update Low Output Level maximum I OL budget Add FLS PR1 to Register Map Bank 1 for users to specify which Flash bank should be used for SROM operations Add two new devices for a 68 pin QFN and 100 ball VFBGA under RPNs CY8C24094 and CY8C24994 Add two packages for 68 pin QFN Add OCD non production pinouts and package diagrams Update CY branding and QFN convention Add new Dev Tool section
55. ion AGND Vdd 2 1 5I 0 034 0 000 0 034 V RefHi Vdd 2 BandGap Vdd 2 BG 0 10 Vdd 2 BG Vdd 2 0 10 V RefHi 3 x BandGap 3 x BG 0 06 3x BG 3 x BG 0 06 V RefHi 2 x BandGap P2 6 P2 6 1 3V 2 2 6 2 x BG P2 6 2 2 6 V 0 113 0 018 0 077 RefHi P2 4 BandGap P2 4 Vdd 2 P2 4 BG 0 130 P2 4 BG 0 016 P2 4 BG 0 098 V RefHi P2 4 P2 6 P2 4 Vdd 2 P2 6 1 3V P2 4 P2 6 P2 4 P2 6 P2 4 P2 6 V 0 133 0 016 0 100 RefHi 3 2 x BandGap 3 2 x 0 112 3 2 3 2 x BG 0 076 V RefLo Vdd 2 BandGap Vdd 2 BG 0 04 Vdd 2 0 024 Vdd 2 0 04 V RefLo BandGap BG 0 06 BG 0 06 V RefLo 2 x BandGap P2 6 P2 6 1 3V 2 x BG P2 6 2 x BG P2 6 2 2 6 V 0 084 0 025 0 134 RefLo P2 4 BandGap P2 4 Vdd 2 P2 4 BG 0 056 P2 4 BG 0 026 P2 4 BG 0 107 V RefLo P2 4 P2 6 P2 4 Vdd 2 P2 6 1 3V P2 4 2 6 P2 4 P2 6 2 4 P2 6 V 0 057 0 026 0 110 Table 10 12 3 3V DC Analog Reference Specifications Symbol Description Min Typ Max Units BG Bandgap Voltage Reference 1 28 1 30 1 32 V AGND 21 51 Vdd 2 0 03 Vdd 2 0 01 Vdd 2 0 005 V AGND 2 x BandGapl 51 Not Allowed AGND P2 4 P2 4 Vdd 2 P2 4 0 008 P2 4 0 001 P2 4 0 009 V AGND SI BG 0 009 BG 0 005 B
56. itor block input 56 M P3 0 7 lO M P2 1 Direct switched capacitor block input 57 M P3 2 8 I O 4 7 58 P3 4 9 VO P4 5 59 WO P3 6 10 O P4 3 60 HCLK OCD high speed clock output 11 P4 1 61 CCLK OCD CPU clock output 12 OCDE OCD even data I O 62 Input XRES Active high pin reset with internal pull down 13 OCDO OCD odd data output 63 P4 0 14 NC No connection 64 l O P4 2 15 Vss Ground connection 65 Vss Ground connection 16 P3 7 66 P4 4 17 P3 5 67 4 6 18 P3 3 68 LM P2 0 Direct switched capacitor block input 19 O P3 1 69 I O 1 P2 2 Direct switched capacitor block input 20 O 5 7 70 P2 4 Analog Ground AGND input 21 11 0 P5 5 71 NC No connection 22 P5 3 72 P2 6 External Voltage Reference VREF input 23 M P5 1 73 24 P1 7 12 Serial Clock SCL 74 PO 0 Analog column mux input 25 NC No connection 75 NC No connection 26 NC No connection 76 NC No connection 27 NC No connection 77 LM PO 2 Analog column mux input and column output 28 P1 5 12 Serial Data SDA 78 NC No connection 29 P1 3 79 LM 4 Analog column mux input and column output 30 P1 1 Crystal in I2C Serial Clock SCL 80 NC No connection ISSP SCLK
57. les m 2 CY8C27443 24PXI 28 PDIP Chip Samples m 2 CY8C29466 24PXI 28 PDIP Chip Samples 12 3 Evaluation Tools All evaluation tools can be purchased from the Cypress Online Store 12 3 1 CY3210 MiniProg1 The CY3210 MiniProg1 kit allows a user to program PSoC devices via the MiniProg1 programming unit The MiniProg is a small compact prototyping programmer that connects to the PC via a provided USB 2 0 cable The kit includes m MiniProg Programming Unit m MiniEval Socket Programming and Evaluation Board m 28 Pin CY8C29466 24PXI PDIP PSoC Device Sample m 28 Pin CY8C27443 24PXI PDIP PSoC Device Sample m PSoC Designer Software CD m Getting Started Guide m USB 2 0 Cable Page 42 of 47 Feedback PERFORM 12 3 2 CY3210 PSoCEval1 The CY3210 PSoCEval1 kit features an evaluation board and the MiniProg1 programming unit The evaluation board includes an LCD module potentiometer LEDs and plenty of bread boarding space to meet all of your evaluation needs The kit includes m Evaluation Board with LCD Module m MiniProg Programming Unit m 28 Pin CY8C29466 24PXI PDIP PSoC Device Sample 2 m PSoC Designer Software CD m Getting Started Guide m USB 2 0 Cable 12 3 3 CY3214 PSoCEvalUSB The CY3214 PSoCEvalUSB evaluation kit features a devel opment board for the CY8C24794 24LFXI PSoC device Special features of the board include both USB and capacitive sensing development and debugging support This evaluation board also
58. ls The choice is yours Assemblers The assemblers allow assembly code to merge seamlessly with C code Link libraries automatically use absolute addressing or are compiled in relative mode and linked with other software modules to get absolute addressing C Language Compilers C language compilers are available that support the PSoC family of devices The products allow you to create complete C programs for the PSoC family devices The optimizing C compilers provide all the features of C tailored to the PSoC architecture They come complete with embedded libraries providing port and bus operations standard keypad and display support and extended math functionality 5 1 5 Debugger The PSoC Designer Debugger subsystem provides hardware in circuit emulation allowing you to test the program in a physical system while providing an internal view of the PSoC device Debugger commands allow the designer to read and program and read and write data memory read and write I O registers read and write CPU registers set and clear breakpoints and provide program run halt and step control The debugger also allows the designer to create a trace buffer of registers and memory locations of interest 5 1 6 Online Help System The online help system displays online context sensitive help for the user Designed for procedural and quick reference each functional subsystem has its own context sensitive help This System also provides tutorials an
59. mply with this requirement Document Number 38 12018 Rev M Page 21 of 47 Feedback a CY8C24094 CY8C24794 SES cypress CY8C24894 CY8C24994 PERFORM 10 3 DC Electrical Characteristics 10 3 1 DC Chip Level Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges 4 75V to 5 25V and 40 C x Ta x 85 C or 3 0V to 3 6V and 40 C lt Ta x 85 C respectively Typical parameters apply to 5V and 3 3V at 25 are for design guidance only Table 10 4 DC Chip Level Specifications Symbol Description Min Typ Max Units Notes Vdd Supply Voltage 3 0 5 25 V See DC POR and LVD specifications Table 10 14 on page 28 1505 Supply Current 1 24 MHz 5V 14 27 Conditions Vdd 5 0V T4 25 CPU 3 MHz SYSCLK doubler disabled VC1 1 5 MHz VC2 93 75 kHz VC3 93 75 kHz analog power off 1503 Supply Current IMO 24 MHz 3 3V 8 14 mA Conditions are Vdd 3 3V T4 25 CPU 3 MHz SYSCLK doubler disabled VC1 1 5 MHz VC2 93 75 kHz VC3 0 367 kHz analog power off Isp Sleep Mode Current with POR LVD Sleep 3 6 5 Conditions are with internal slow speed Timer WDT 3 oscillator Vdd 3 3V 40 lt TA lt 55 analog power off lagu Sleep Mode Current with POR LVD Sleep 4 25 Conditions are with internal slow speed
60. nal Clock Input EXTCLK 28 I O M P1 6 29 I O M P5 0 Pin Type Name Description 30 I O M 5 2 No Digital Analog p 31 I O M P5 4 44 I O M P2 6 External Voltage Reference VREF input 32 I O M P5 6 45 I M PO 0 Analog column input 33 I O M P3 0 46 I O I M PO 2 Analog column mux input 34 I O M P3 2 47 I O I M PO 4 Analog column mux input VREF 35 I O M P3 4 48 I O I M PO 6 Analog column mux input 36 Input XRES Active high external reset with internal 49 Power Vdd Supply voltage pull down 37 I O M 4 0 50 Vss Ground connection 38 I O M P4 2 51 I O M PO 7 Analog column mux input 39 I O M 4 4 52 I O PO 5 Analog column mux input and column output 40 I O M 4 6 53 I O M PO 3 Analog column mux input and column output 41 I O I M P2 0 Direct switched capacitor block input 54 I O LM PO 1 Analog column mux input 42 I O M P2 2 Direct switched capacitor block input 55 I O M P2 7 43 I O M P2 4 External Analog Ground AGND input 56 I O M P2 5 LEGEND A Analog Input O Output and M Analog Mux Input Notes 1 These are the ISSP pins which are not High Z at POR See the PSoC Programmable System on Chip Technical Reference Manual for details 2 The center pad on the QFN package should be connected to ground Vss for best mechanical thermal and electrical performance If not connected to ground it should be electrically floated and not connected
61. nalog Ground AGND input P7 5 E8 P4 4 K8 l O P7 4 E9 M P3 6 K9 Vss Ground connection E10 NC No connection K10 Power Vss Ground connection LEGENDA Analog Input Output M Analog Input NC No Connection Document Number 38 12018 Rev M Page 12 of 47 Feedback CYPRESS PERFORM CY8C24094 CY8C24794 CY8C24894 CY8C24994 Figure 8 5 CY8C24094 OCD Not for Production o 400 doo JOD doo doo JOD QOOOOQOHOSO QOOOOOS 900C COGO CQ O OOOOOO 000002 02000000 OOOOOOOOO QOOOOOOOOO BGA Top View 8 1 100 Ball VFBGA Part Pinout On Chip Debug The 100 pin VFBGA part table and drawing below is for the CY8C24094 On Chip Debug OCD PSoC device Note This part is only used for in circuit debugging It is NOT available for production Table 8 6 100 Ball Part Pinout VFBGA o o Pin S 2 ly Pin 2 2 Descnp No 9 T ame escription No 9 8 ame escription a lt A lt A1 Power Vss Ground connection F1 OCDE OCD even data I O A2 Power Vss Ground connection F2 M P5 7 A3 NC No connection M P3 5 A4 NC No connection FA M P5 1 A5 NC No connection F5 Power Vss Ground connection A6 Power Vdd Supply voltage F6 V
62. nd the numerous discrete components that surround them The PSoC CY8C24x94 devices are unique members of the PSoC family because it includes a full featured full speed 12 Mbps USB port Configurable analog digital and interconnect circuitry enable a high level of integration in a host of industrial consumer and communication applications This architecture allows the user to create customized peripheral configurations that match the requirements of each individual application Additionally a fast CPU Flash program memory SRAM data memory and configurable I O are included in a range of convenient pinouts and packages The PSOC architecture as illustrated on the left is comprised of four main areas PSoC Core Digital System Analog System and System Resources including a full speed USB port Config urable global busing allows all the device resources to be combined into a complete custom system The PSoC CY8C24x94 devices can have up to seven I O ports that connect to the global digital and analog interconnects providing access to 4 digital blocks and 6 analog blocks 3 4 The PSoC Core The PSoC Core is a powerful engine that supports a rich feature set The core includes a CPU memory clocks and configurable GPI O General Purpose I O The M8C CPU core is a powerful processor with speeds up to 24 MHz providing a four MIPS 8 bit Harvard architecture micropro cessor The CPU uses an interrupt controller with up to 20 vect
63. nk 10 mA Drive on all GPI O Pull Up Pull Down High Z Strong or Open Drain Drive Modes on all Up to 48 Analog Inputs on GPI O Two 33 mA Analog Outputs on GPI O Configurable Interrupt on all GPI O Precision Programmable Clocking Internal 4 24 and 48 MHz Oscillator Internal Oscillator for Watchdog and Sleep 0 25 Accuracy for USB with no External Components m Additional System Resources alc Slave Master and Multi Master to 400 kHz Watchdog and Sleep Timers User Configurable Low Voltage Detection 2 Logic Block Diagram Port 3 HPort 2 l sues NT Global Digital Interconnect Global Analog Interconnect PSoC CORE SRAM SROM Flash 16K 1K Interrupt CPU Core M8C Controller Clock Sources Sleep and Watchdog Includes IMO and ILO Internal Voltage Ref D igital 2 Decimator Clocks 2 SYSTEM RESOURCES POR and LVD 12G System Resets San Jose CA 95134 1709 408 943 2600 Revised February 10 2009 Cypress Semiconductor Corporation Document Number 38 12018 Rev M 198 Champion Court Feedback PERFORM 3 PSoC Functional Overview The PSoC family consists of many Mixed Signal Array with On Chip Controller devices All PSoC family devices are designed to replace traditional MCUs system ICs a
64. o the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Any Source Code software and or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign United States copyright laws and international treaty provisions Cypress hereby grants to licensee a personal non exclusive non transferable license to copy use modify create derivative works of and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement Any reproduction modification translation compilation or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Cypress reserves the right to make changes without further notice to the materials described herein Cypress does not assume any liability arising out of the application or use of any product or circuit described herein Cypress does n
65. oltage and temperature ranges 4 75V to 5 25V and 40 C x Ta x 85 or 3 0V to 3 6V and 40 C lt Ta lt 85 respectively Typical parameters apply to 5V and 3 3V at 25 and are for design guidance only Table 10 27 AC Characteristics of the 2 SDA and SCL Pins for Vdd or Standard Mode Fast Mode y Symbol Description Min Max Min Max Units Notes Fscu2c SCL Clock Frequency 0 100 0 400 kHz TupsrAi Hold Time repeated START Condition After 4 0 0 6 us C this period the first clock pulse is generated LOW Period of the SCL Clock 4 7 1 3 US HIGH Period of the SCL Clock 4 0 0 6 us Set up Time for a Repeated START Condition 4 7 0 6 E us THDDATI2 Data Hold Time 0 0 US Data Set up Time 250 1001747 ns TsusTor Set up Time for STOP Condition 4 0 0 6 US Tpuri2c Bus Free Time Between STOP and START 4 7 m 1 3 US Condition TsPi2c Pulse Width of spikes are suppressed by the x 0 50 ns input filter Figure 10 6 Definition for Timing for Fast Standard Mode on the 2 Bus SDA THDSTAI2C TLowizc T MC 4 gt 4 I SUDATI2C Tpuri2c SCL na T Tupsragc THDDATI2C me Por TANTEN 1 2 aud 200000 ke Note 14 A Fast Mode I2C bus device can be used in a Standa
66. on 42 10 M P3 4 61 LM PO 7 Analog column input integration input 1 43 10 M P3 6 62 PO 5 Analog column mux input and column output integration input 2 44 NC No connection 63 PO 3 Analog column mux input and column output 45 NC No connection 64 LM PO 1 Analog column mux input 46 Input XRES Active high pin reset with internal pull 65 M P2 7 down 47 M O M P4 0 66 M P2 5 48 10 M P4 2 67 LM P2 3 Direct switched capacitor block input 49 10 M P4 4 68 LM P2 1 Direct switched capacitor block input LEGENDA Analog Input Output NC No Connection M Analog Input Document Number 38 12018 Rev M Page 10 of 47 Feedback a CY8C24094 CY8C24794 F CYPRESS CY8C24894 CY8C24994 PERFORM 8 1 68 Pin Part Pinout On Chip Debug The 68 pin QFN part table and drawing below is for the CY8C24094 On Chip Debug OCD PSoC device Note This part is only used for in circuit debugging It is NOT available for production Table 8 4 68 Pin Part Pinout QFN Fin Pe EUNT Figure 8 4 CY8C24094 68 Pin OCD PSoC Device gital Analog m 9 1 I O M P4 7 g 2 M ES lt lt 2922 aaa 3 e uM
67. ors to simplify programming of real time embedded events Program execution is timed and protected using the included Sleep and Watch Dog Timers WDT Memory encompasses 16K of Flash for program storage 1K of SRAM for data storage and up to 2K of EEPROM emulated using the Flash Program Flash uses four protection levels on blocks of 64 bytes allowing customized software IP protection The PSoC device incorporates flexible internal clock generators including 24 MHz IMO internal main oscillator accurate to 8 over temperature and voltage The 24 MHz IMO can also be doubled to 48 MHz for use by the digital system A low power 32 kHz ILO internal low speed oscillator is provided for the Sleep timer and WDT The clocks together with programmable clock dividers as a System Resource provide the flexibility to integrate almost any timing requirement into the PSoC device In USB systems the IMO self tunes to 0 2596 accuracy for USB communication PSoC GPI Os provide connection to the CPU digital and analog resources of the device Each pin s drive mode may be selected from eight options allowing great flexibility in external inter facing Every pin is also capable of generating a system interrupt on high level low level and change from last read Document Number 38 12018 Rev M CY8C24094 CY8C24794 CY8C24894 CY8C24994 3 2 The Digital System The Digital System is composed of four digital PSoC blocks Each block is an
68. ot authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress product in a life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Use may be limited by and subject to the applicable Cypress software license agreement Document Number 38 12018 Rev M Revised February 10 2009 Page 47 of 47 PSoC Designer and Programmable System on Chip are trademarks and PSoC6 is a registered trademark of Cypress Semiconductor Corp All other trademarks or registered trademarks referenced herein are property of the respective corporations Feedback
69. overview of the PSoC integrated circuit and presents specific pin register and electrical specifications For in depth information along with detailed programming details see the PSoC Programmable System on Chip Technical Reference Manual for CY8C28xxx PSoC devices For up to date ordering packaging and electrical specification information see the latest PSoC device data sheets on the web at www cypress com psoc 4 1 Application Notes Application notes are an excellent introduction to the wide variety of possible PSoC designs They are located here www cypress com psoc Select Application Notes under the Documentation tab 4 2 Development Kits PSoC Development Kits are available online from Cypress at www cypress com shop and through a growing number of regional and global distributors which include Arrow Avnet Digi Key Farnell Future Electronics and Newark 4 3 Training Free PSoC technical training on demand webinars and workshops is available online at www cypress com training The training covers a wide variety of topics and skill levels to assist you in your designs 4 4 CyPros Consultants Certified PSoC Consultants offer everything from technical assistance to completed PSoC designs To contact or become a PSoC Consultant go to www cypress com cypros 4 5 Solutions Library Visit our growing library of solution focused designs at www cypress com solutions Here you can find various appli cation desi
70. owing Application Note at http www amkor com products notes_papers MLFAppNote pdf m Pinned vias for thermal conduction are not required for the low power PSoC device Figure 11 3 68 Pin SAWN QFN 8X8 mm X 0 90 mm MEN SIDE VIEW BOTTOM VIEW 90040 100 200 REF 0 025 8 86 BH 5 motes Ida 1 MATCH AREA I SOLDERABLE EXPOSED METAL 2 REFERENCE JEDECO MO 220 3 PACKAGE WEIGHT 0 178 001 09618 A 4 ALL DIMENSIONS ARE N MILLIMETERS Document Number 38 12018 Rev M Page 39 of 47 Feedback CY8C24094 CY8C24794 Cypress CY8C24894 CY8C24994 PERFORM Figure 11 4 100 Ball 6x6 mm VFBGA VIEW BOTTOM VIEW A1 CDRNER 1 CORNER Y 0 30 0 05 100X 12345678810 10 6 00 0 16 A IQ Qmmr udqcoue T 6 00 0 10 4 50 9 50 2 25 B000000098 0000000000 6000060000 0000000000 2000000000 0000000000 0000000000 0000000000 B000000000 X I TIMOOU gt 6 00 0 10 i B DO 0 10 e gt x 5 0 45 REF REFERENCE JEDEC 0 195 PKG WEIGHT TBD NEW PKG SEATING PLANE 5 5 51 85209 B NOTE 1 JEDEC STD REF MS 026 2 BODY LENGTH DIMENSION DOES INCLUDE MOLD PROTRUSION END FLASH MOLD PROTRUSION END FLASH SHALL NOT EXCEED 0 0098 in 0 25 mm PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 75 3 DIMENSIONS
71. rate at 3 08 MHz mitter due to 8 x over clocking Receiver Maximum Input Clock Frequency 24 6 MHz Maximum data rate at 3 08 MHz due to 8 x over clocking Note 13 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz 42 ns nominal period Document Number 38 12018 Rev M Page 34 of 47 Feedback Fm CY8C24094 CY8C24794 SES Cypress CY8C24894 CY8C24994 PERFORM 10 0 3 AC External Clock Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges 4 75V to 5 25V and 40 C lt Ta lt 85 or 3 0V to 3 6V and 40 C lt Ta lt 85 C respectively Typical parameters apply to 5V and 3 3V at 25 and are for design guidance only Table 10 23 AC External Clock Specifications Symbol Description Min Typ Max Units Notes Foscext Frequency for USB Applications 23 94 24 24 06 MHz Duty Cycle 47 50 53 Power up to IMO Switch 150 us 10 0 4 AC Analog Output Buffer Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges 4 75V to 5 25V and 40 C x Ta x 85 or 3 0V to 3 6V and 40 C lt Ta lt 85 respectively Typical parameters apply to 5V and 3 3V at 25 and are for design guidance only Table 10 24 5V AC Analog Output Buffer Specifications
72. rd Mode I2C bus system but the requirement tsy pat 250 ns must then be met This automatically is the case if the device does not stretch the LOW period of the SCL signal If such device does stretch the LOW period of the SCL signal it must output the next data bit to the SDA line tra tsu pAr 1000 250 1250 ns according to the Standard Mode I2C bus specification before the SCL line is released Document Number 38 12018 Rev M Page 37 of 47 Feedback CY8C24094 CY8C24794 mE CYPRESS CY8C24894 CY8C24994 PERFORM 11 Packaging Dimensions This section illustrates the package specification for the CY8C24x94 PSoC devices along with the thermal impedance for the package and solder reflow peak temperatures Important Note Emulation tools may require a larger area on the target PCB than the chip s footprint For a detailed description of the emulation tools dimensions refer to the document titled PSoC Emulator Pod Dimensions at http www cypress com design MR10161 Q Figure 11 1 56 Pin 8x8 mm QFN VIEW SIDE VIEW BOTTOM VIEW 56 08 0 003 1 00 0 039 4 T 0 05 0 002 MAX 0 80 0 031 MAX 0 20 0 008 REF 7 30 0 311 8 10 0 319 2 70 0 303 7 800 307 PIN ID 0 200 008 vw X XX X X 0 45 0 018 0 80 0 031 DIA UUUUUUUUU 5 21 AAA PX 7 80 0 307 2 90 0 3
73. red through an analog or high opamp bias 0 5 output buffer The specification includes the limitations imposed by the characteristics of the analog output buffer Gor oA Open Loop Gain Power Low Opamp Bias High 60 Power Medium Opamp Bias High 60 Power High Opamp Bias High 80 Document Number 38 12018 Rev M Page 23 of 47 Feedback PERFORM Table 10 7 5V DC Operational Amplifier Specifications continued CY8C24094 CY8C24794 CY8C24894 CY8C24994 Symbol Description Min Typ Max Units Notes High Output Voltage Swing internal signals A Power Low Opamp Bias High Vdd V Power Medium Opamp Bias High 0 2 V Power High Opamp Bias High Vdd V 0 2 Vdd 0 5 Low Output Voltage Swing internal signals Power Low Opamp Bias High 0 2 V Power Medium Opamp Bias High 0 2 V Power High Opamp Bias High 0 5 V Ison Supply Current including associated AGND buffer 400 800 Power Low Opamp Bias Low 500 900 Power Low Opamp Bias High 800 1000 Power Medium Opamp Bias Low 1200 1600 Power Medium Opamp Bias High 2400 3200 Power High Opamp Bias Low 4600 6400 Power High Opamp Bias High PSRRoA Supply Voltage Rejection Ratio 65 80 Vss lt VIN lt Vdd 2 25 or Vdd 1 25V lt VIN lt Vdd 10 3 5 DC Low Pow
74. rnal crystal oscillator EEPROM electrically erasable programmable read only memory FSR full scale range GPI O general purpose I O GUI graphical user interface HBM human body model ICE in circuit emulator ILO internal low speed oscillator IMO internal main oscillator I O input output IPOR imprecise power on reset LSb least significant bit LVD low voltage detect MSb most significant bit PC program counter PLL phase locked loop POR power on reset PPOR precision power on reset PSoC Programmable System on Chip PWM pulse width modulator SC Switched capacitor SRAM static random access memory Document Number 38 12018 Rev M CY8C24094 CY8C24794 CY8C24894 CY8C24994 7 2 Units of Measure units of measure table is located in the Electrical Specifications section Table 10 1 on page 20 lists all the abbreviations used to measure the PSoC devices 7 3 Numeric Naming Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase h for example 14h or 3Ah Hexadecimal numbers may also be represented by 0 prefix the C coding convention Binary numbers have an appended lowercase b e g 010101006 or 01000011b Numbers not indicated by an h or b are decimal Page 7 of 47 Feedback a CY8C24094 CY8C24794 CYPRESS CY8C24894 CY8C24994 PERFORM 8 Pin Information This section describes lists and illustr
75. s Small Signal Bandwidth 20mV p BW 100 pF Load 0 7 MHz Power Low 0 7 MHz Power High BWog s Large Signal Bandwidth 1V55 BW 100 pF Load 200 kHz Power Low 200 kHz Power High 10 0 5 AC Programming Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges 4 75V to 5 25V and 40 C x Ta x 85 C or 3 0V to 3 6V and 40 C lt Ta x 85 C respectively Typical parameters apply to 5V and 3 3V at 25 and are for design guidance only Table 10 26 AC Programming Specifications Symbol Description Min Typ Max Units Notes Trscuk Rise Time of SCLK 1 20 ns Time of SCLK 1 20 ns Data Set up Time to Falling Edge of SCLK 40 ns Data Hold Time from Falling Edge of SCLK 40 ns Frequency of SCLK 0 8 MHz Flash Erase Time Block m 10 me Twrite Flash Block Write Time 30 ms Data Out Delay from Falling Edge of SCLK 45 ns Vdd 3 6 Data Out Delay from Falling Edge of SCLK 50 ns 3 0 x Vdd x 3 6 Document Number 38 12018 Rev M Page 36 of 47 Feedback EF CY8C24094 CY8C24794 SES Cypress CY8C24894 CY8C24994 PERFORM 10 0 6 AC Specifications The following table lists guaranteed maximum and minimum specifications for the v
76. s office or Field Applications Engineer FAE Document Number 38 12018 Rev M Page 44 of 47 Feedback CY8C24094 CY8C24794 3 CYPRESS CY8C24894 CY8C24994 PERFORM 13 1 Ordering Code Definitions CY 8 24 XXX SP Thermal Rating PX PDIP Pb Free _ SX SOIC Pb Free C Commercial PVX SSOP Pb Free LFX LKX LTX QFN Pb Free Industrial TQFP Pb Free E Extended BVX VFBGA Pb Free Speed 24 MHz Part Number Family Code Technology Code C CMOS Marketing Code 8 Cypress PSoC Company ID CY Cypress Note 21 This part may be used for in circuit debugging It is NOT available for production Page 45 of 47 Document Number 38 12018 Rev M Feedback a CY8C24094 CY8C24794 cypress CY8C24894 CY8C24994 PERFORM 14 Document History Page Document Title CY8C24094 CY8C24794 CY8C24894 and CY8C24994 PSoC Programmable System on Chip Document Number 38 12018 Submission Orig of Description of Change Rev ECN No Date Change B 133189 01 27 2004 NWJ New silicon and new document Advance Data Sheet A 251672 See SFV First Preliminary Data Sheet Changed title to encompass only the CY8C24794 because the CY8C24494 and CY8C24694 are not being offered by Cypress B 289742 See HMT Add standard DS items from SFV memo Add Analog Input Mux on p
77. sed Document Number 38 12018 Rev M Access is bit specific Page 19 of 47 Feedback PERFORM 10 Electrical Specifications CY8C24094 CY8C24794 CY8C24894 CY8C24994 This section presents the DC and AC electrical specifications of the CY8C24x94 PSoC device family For the most up to date electrical specifications confirm that you have the most recent data sheet by going to the web at http www cypress com psoc Specifications are valid for 40 C lt TAS 85 and T lt 100 C except where noted Specifications for devices running at greater than 12 MHz are valid for 40 C lt Ta lt 70 and T lt 82 Figure 10 1 Voltage versus CPU Frequency 5 25 Vdd Voltage 3 00 93 kHz CPU Frequency The following table lists the units of measure that are used in this chapter gt 12 MHz 24 MHz Table 10 1 Units of Measure Symbol Unit of Measure Unit of Measure C degree Celsius microwatts dB decibels milli ampere fF femto farad milli second Hz hertz milli volts KB 1024 bytes nanoampere Kbit 1024 bits ns nanosecond kHz kilohertz nV nanovolts kilohm W ohm MHz megahertz pA picoampere MO megaohm pF picofarad microampere pp peak to peak uF microfarad ppm parts per million uH microhenry ps picosecond us microsecond sps samples per second uV microvolts S sigma one standard deviation u
78. solder are 220 5 C with Sn Pb or 245 5 with Sn Ag Cu paste Page 41 of 47 Feedback PERFORM 12 Development Tool Selection 12 1 Software 12 1 1 PSoC Designer At the core of the PSoC development software suite is PSoC Designer Used by thousands of PSoC developers this robust software has been facilitating PSoC designs for half a decade PSoC Designer is available free of charge http www cypress com under DESIGN RESOURCES gt gt Software and Drivers 12 1 2 PSoC Programmer Flexible enough to be used on the bench in development yet suitable for factory programming PSoC Programmer works either as a standalone programming application or it can operate directly from PSoC Designer or PSoC Express PSoC Programmer software is compatible with both PSoC ICE Cube In Circuit Emulator and PSoC MiniProg PSoC programmer is available free of charge at http www cypress com psocpro grammer 12 1 3 C Compilers PSoC Designer comes with a free HI TECH C Lite C compiler The HI TECH C Lite compiler is free supports all PSoC devices integrates fully with PSoC Designer and PSoC Express and runs on Windows versions up to 32 bit Vista Compilers with additional features are available at additional cost from their manufactures m HI TECH C PRO for the PSOC is available from http www htsoft com m ImageCraft Cypress Edition Compiler is available from http www imagecraft com 12 2 Development Kits All d
79. ss Ground connection AT NC No connection F7 M 5 0 8 NC No connection F8 M P3 0 A9 Power Vss Ground connection F9 XRES Active high pin reset with internal pull down A10 Power Vss Ground connection F10 P7 1 B1 Power Vss Ground connection G1 OCDO OCD odd data output B2 Power Vss Ground connection G2 M P5 5 2 1 Direct switched capacitor block input G3 M P3 3 B4 PO 1 Analog column input G4 M P1 7 I2C Serial Clock SCL B5 PO 7 Analog column mux input G5 M P1 1 I2C Serial Clock SCL ISSP SCLKIT B6 Power Vdd Supply voltage G6 M P1 0 12 Serial Data SDA ISSP SDATA PO 2 Analog column input G7 M P1 6 B8 2 2 Direct switched capacitor block input G8 M P3 4 B9 Power Vss Ground connection G9 M P5 6 B10 Power Vss Ground connection G10 I O P7 2 C1 NC No connection H1 NC No connection C2 H2 IM 5 3 C3 M 4 7 H3 O M P3 1 M P2 7 H4 WO IM 1 5 2 Serial Data SDA C5 VO PO 5 Analog column mux input and column output H5 I O M P1 3 C6 PO 6 Analog column input H6 M P1 2 C7 O PO 0 Analog column input H7 O M P1 4 Optional External Clock Input EXTCLK Document Number 38 12018 Rev M Page 13 of 47 Feedback CYPRESS
80. t Adapter CY8C24794 24LFXI 56 QFN CY3250 24X94QFN CY3250 56QFN FK AS 56 28 CY8C24894 24LFXI 56 QFN CY3250 24X94QFN CY3250 56QFN FK AS 28 28 02SS 6ENG GANG 12 5 2 Build a PSoC Emulator into Your Board For details on how to emulate your circuit before going to volume production using an on chip debug OCD non production PSoC device see Application Note Debugging Build a PSoC Emulator into Your Board AN2323 at http www cypress com an2323 12 5 1 3rd Party Tools Several tools have been specially designed by the following 3rd party vendors to accompany PSoC devices during devel opment and production Specific details for each of these tools are found at http www cypress com under Design Resources gt Evaluation Boards Notes 18 Flex Pod kit includes a practice flex pod and a practice PCB in addition to two flex pods 19 Foot kit includes surface mount feet that are soldered to the target PCB 20 Programming adapter converts non DIP package to DIP footprint Specific details and ordering information for each of the adapters are found at http www emulation com Document Number 38 12018 Rev M Page 43 of 47 Feedback CYPRESS PERFORM 13 Ordering Information CY8C24094 CY8C24794 CY8C24894 CY8C24994 Table 13 1 CY8C24x94 PSoC Device s Key Features and Ordering Information 7 2
81. to any other signal Document Number 38 12018 Rev M Page 9 of 47 Feedback CYPRESS PERFORM 8 1 68 Pin Part Pinout The 68 pin QFN part table and drawing below is for the CY8C24994 PSoC device Table 8 3 68 Pin Part Pinout CY8C24094 CY8C24794 CY8C24894 CY8C24994 i T i p Name Description Figure 8 3 CY8C24994 68 Pin PSoC Device o Digital Analog 2 LL 1 o M PA 7 2 M PA 5 56 211 xx 3 10 M P4 3 1a LETT EE SE 4 M PA 1 22222222 2222222 aE OS x 09 wos 0 S CN 5 NC No connection POP 6 NC No connection _ 7 Vss Ground connection 89 5 080590105 EHR BEBE s M P4 7 1 51 2 0 AI 8 I O M P3 7 M P4 5 2 502 P4 6 M 9 I O M P3 5 P4 3 3 P4 4 M 10 P3I3 M P4 1 4 48 P4 2 NC 5 472 P4 0 11 P3 1 NC d 6 46 XRES 12 M P5 7 Vss 7 45E NC 13 M P5 5 3 7 8 44 NC 14 WO P5 3 P3 5 9 QFN 432 236 M M P3 3 10 Top View 42 P3 4 M 15 5 M 11 41 P3 2 16 M P1 7 12 Serial Clock SCL M 5 7 42 P3 0 M 17 P1 5 12 Serial Data SDA M 5 5 sj 1
82. y Gain 0 01 V us Power Low Opamp Bias Low 0 5 V us Power Medium Opamp Bias High 4 0 V us Power High Opamp Bias High BWoa Gain Bandwidth Product Power Low Opamp Bias Low 0 75 2 Power Medium Opamp Bias High 3 1 MHz Power High Opamp Bias High 5 4 MHz ENOA Noise at 1 kHz Power Medium Opamp Bias High 100 nV rt Hz Table 10 20 3 3V AC Operational Amplifier Specifications Symbol Description Min Typ Max Units TROA Rising Settling Time from 8096 of AV to 0 196 of AV 10 pF load Unity Gain Power Low Opamp Bias Low 3 92 us Power Medium Opamp Bias High 0 72 us TsoA Falling Settling Time from 20 of AV to 0 1 of AV 10 pF load Unity Gain Power Low Opamp Bias Low 5 41 us Power Medium Opamp Bias High 0 72 us SRroa Rising Slew Rate 20 to 80 10 pF load Unity Gain Power Low Opamp Bias Low 0 31 V us Power Medium Opamp Bias High 2 7 V us SRroA Falling Rate 20 to 80 10 pF load Unity Gain 0 24 V us Power Low Opamp Bias Low 1 8 V us Power Medium Opamp Bias High BWoa Gain Bandwidth Product Power Low Opamp Bias Low 0 67 2 Power Medium Opamp Bias High 2 8 MHz ENOA Noise at 1 kHz Power Medium Opamp Bias High 100 nV rt Hz Document Number 38 12018 Rev M Page 32 of 47 Feedback CY8C24094 CY8C24794 CY8C24894

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