Cypress CY8C22213 User's Manual
Contents
1. Symbol Description Min Typ Max Units Notes Heu Pull up Resistor 4 5 6 8 kQ Rpp Pull down Resistor 4 5 6 8 kQ VoH High Output Level Vdd 1 0 V IOH 10 mA Vdd 4 75 to 5 25V 80 mA max imum combined IOH budget VoL Low Output Level 0 75 V IOL 25 mA Vdd 4 75 to 5 25V 150 mA maximum combined IOL budget Vit Input Low Level 0 8 V Vdd 3 0 to 5 25 Vin Input High Level 2 1 V Vdd 3 0 to 5 25 Vu Input Hysterisis 60 mV lit Input Leakage Absolute Value 1 nA Gross tested to 1 uA Cin Capacitive Load on Pins as Input z 3 5 10 pF Package and pin dependent Temp 25 C Cout Capacitive Load on Pins as Output 3 5 10 pF Package and pin dependent Temp 25 C June 3 2004 Document No 38 12009 Rev E 15 Feedback CY8C22x13 Final Data Sheet 3 Electrical Specifications 3 3 3 DC Operational Amplifier Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges 4 75V to 5 25V and 40 C lt Ta lt 85 C or 3 0V to 3 6V and 40 C lt Ta lt 85 C respectively Typical parameters apply to 5V and 3 3V at 25 C and are for design guidance only or unless otherwise specified The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Cap PSoC blocks The guaranteed specifications are measured in the Analog Continuous Time PSoC block Typica2. User Modules and Development Process Flow Chart The next step is to write your main program and any sub rou tines using PSoC Designers Application Editor subsystem The Application Editor includes a Project Manager that allows you to open the project source code files including all gener ated code files from a hierarchal view The source code editor provides syntax coloring and advanced edit features for both C and assembly language File search capabilities include simple string searches and recursive grep style patterns A single mouse click invokes the Build Manager It employs a profes sional strength makefile system to automatically analyze all file dependencies and run the compiler and assembler as nec essary Project level options control optimization strategies used by the compiler and linker Syntax errors are displayed in a console window Double clicking the error message takes you directly to the offending line of source code When all is correct the linker builds a ROM file image suitable for programming The last step in the development process takes place inside the PSoC Designer s Debugger subsystem The Debugger down loads the ROM image to the In Circuit Emulator ICE where it runs at full soeed Debugger capabilities rival those of systems costing many times more In addition to traditional single step run to breakpoint and watch variable features the Debugger provides a large trace buffer and
3. Blank fields are Reserved and should not be accessed Access is bit specific June 3 2004 Document No 38 12009 Rev E 11 Feedback CY8C22x13 Final Data Sheet 2 Register Reference Register Map Bank 1 Table Configuration Space z Zaia z Spl z z Zol z Sal 18 I2 9 m IQ o m IQ o m IQ bi 8 ge g 8 Ss 8 Ss 8 ge lt D lt o Kid o _ o PRTODMO 00 RW 40 80 CO PRTODM1 01 RW 41 81 C1 PRTOICO 02 RW 42 82 C2 PRTOIC1 03 RW 43 83 C3 PRT1DMO 04 RW 44 ASD11CRO 84 RW C4 PRT1DM1 05 RW 45 ASD11CR1 85 RW C5 PRT11CO 06 RW 46 ASD11CR2 86 RW C6 PRT1IC1 07 RW 47 ASD11CR3 87 RW C7 08 48 88 C8 09 49 89 C9 0A 4A 8A CA 0B 4B 8B CB OG 4C 8C CC oD 4D 8D CD 0E 4E 8E CE OF 4F 8F CF 10 50 90 GDI_O_IN DO RW 11 51 91 GDI_E_IN D1 RW 12 52 92 GDI_O_OU D2 RW 13 53 93 GDI_E_OU D3 RW 14 54 ASC21CRO 94 RW D4 15 55 ASC21CR1 95 RW D5 16 56 ASC21CR2 96 RW D6 17 57 ASC21CR3 97 RW D7 18 58 98 D8 19 59 99 D9 1A 5A 9A DA 1B 5B 9B DB 1C 5C 9C DC 1D 5D 9D OSC_GO_EN DD RW 1E 5E 9E OSC_CR4 DE RW 1F 5F OF OSC_CR3 DF RW DBBOOFN 20 RW CLK CRO 60 RW AO OSC_CRO EO RW DBBOOIN 21 RW CLK CRI 61 RW A1 OSC CR1 E1 RW DBBO00U 22 RW ABF CRO 62 RW A2 OSC_CR2 E2 RW 23 63 A3 VLT CR E3 RW DBB01FN 24 RW 64 A4 VLT_CMP E4 R
4. ns Transmitter Maximum Input Clock Frequency 16 4 MHz Receiver Maximum Input Clock Frequency 16 49 2 MHz 4 75V lt Vdd 5 25V a b ns minimum input pulse width is based on the input synchronizers running at 24 MHz 42 ns nominal period June 3 2004 Document No 38 12009 Rev E 27 Feedback CY8C22x13 Final Data Sheet 3 Electrical Specifications 3 4 5 AC Analog Output Buffer Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges 4 75V to 5 25V and 40 C lt Ta lt 85 C or 3 0V to 3 6V and 40 C lt Ta lt 85 C respectively Typical parameters apply to 5V and 3 3V at 25 C and are for design guidance only or unless otherwise specified Table 3 20 5V AC Analog Output Buffer Specifications Symbol Description Min Typ Max Units Notes Tros Rising Settling Time to 0 1 1V Step 100pF Load Power Low 2 5 us Power High 2 5 us TsoB Falling Settling Time to 0 1 1V Step 100pF Load Power Low 2 2 us Power High 2 2 us SRros Rising Slew Rate 20 to 80 1V Step 100pF Load Power Low 0 65 V us Power High 0 65 Vius SRroB Falling Slew Rate 80 to 20 1V Step 100pF Load Power Low 0 65 V us Power High 0 65 V us BWog Small Signal Bandwidth 20mVpp 3dB BW 100pF Load Power Low 0 8 MHz Power High 0 8 MHz
5. 1 1 1 8 Pin Part Pinout Table 1 1 8 Pin Part Pinout PDIP SOIC En m Type Pin Description CY8C22113 8 Pin PSoC Device 0 Digital Analog Name 1 IO IO PO 5 Analog column mux input and column output 2 IO I PO 3 Analog column mux input AIO PO 5 Vdd 3 IO P1 1 Crystal Input XTALin I2C Serial Clock SCL Al POR POL Al 4 Power Vss Ground connection I2 SCL XTALin P 1 PO 2 Al 5 IO Pilo Crystal Output XTALout 12C Serial Data vss PAO XTALout 12C SDA SDA 6 IO PO 2 Analog column mux input 7 IO PO 4 Analog column mux input 8 Power Vdd Supply voltage LEGEND A Analog Input and O Output 1 1 2 20 Pin Part Pinout Table 1 2 20 Pin Part Pinout PDIP SSOP SOIC Ha Type Pin Description CY8C22213 20 Pin PSoC Device o Digital Analog Name 1 IO I PO 7 Analog column mux input AL PO 7 Wi 2 IO IO PO 5 Analog column mux input and column output AIO PO S 2 AI 3 IO I PO 3 Analog column mux input Al POB 3 Al 4 IO PO 1 Analog column mux input Al PO L 4 LAI 5 Power Vss Ground connection Vss 5 LAI 6 IO P1 7 12C Serial Clock SCL 12C SCL P1 7 6 S 7 IO P1 5 I2C Serial Data SDA I2C SDA P1 5 7 8 IO P1 3 P13 8 EXTCLK 9 IO P1 1 Crystal Input XTALin I2C Serial Clock SCL 12C SCL XTALIn P1 1 9 10 Power Vss Ground connection
6. 600 ps TPLLSLEW PLL Lock Time 0 5 10 ms TpLLsLews PLL Lock Time for Low Gain Setting 0 5 50 ms LOW Tos External Crystal Oscillator Startup to 1 1700 2620 ms Tosacc External Crystal Oscillator Startup to 100 ppm 2800 3800 ms Jitter32k 32 kHz Period Jitter Si 100 ns TxrsT External Reset Pulse Width 10 us DC24M 24 MHz Duty Cycle 40 50 60 96 Step24M 24 MHz Trim Step Size 50 kHz Fout48M 48 MHz Output Frequency 46 8 48 0 49 236 MHz Trimmed Utilizing factory trim values Jitter24M1 24 MHz Period Jitter IMO 600 ps FMax Maximum frequency of signal on row input or row output 12 3 MHz TRAMP Supply Ramp Time 0 us a 45V Vdd lt 5 25V b Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range c 3 0V Vdd 3 6V See Application Note AN2012 Adjusting PSoC Microcontroller Trims for Dual Voltage Range Operation for information on trimming for operation at 3 3V d Seethe individual user module data sheets for information on maximum frequencies for user modules e 3 0V lt 5 25V f The crystal oscillator frequency is within 100 ppm of its final value by the end of the Tosacc period Correct operation assumes a properly loaded 1 uW maximum drive level June 3 2004 Document No 38 12009 Rev E 22 Feedback CY8C22x13 Final Data Sheet 3 Electrical Specifications PLL Enable 4 pustewmow 24 MHz PLL Gain Figure 3 3 PLL Lock for Low
7. Document No 38 12009 Rev E 34 Feedback 5 Ordering Information i H d 1 ESS MICROSYSTI EMS The following table lists the CY8C22x13 PSoC Device family s key package features and ordering codes Table 5 1 CY8C22x13 PSoC Device Family Key Features and Ordering Information E o o o o o a g 2 2 2 3 v s amp 2 5 o E o 2 ES zo 2 9 ol oe c 2 a S i Y fr E EC m m2 o 3 Oo x o0 E 5 o Slol D G S ZO e 24 S Ee EN EE gl r Ss S ise El lal z ra E qe lai a lt lt G lt S 8 Pin 300 Mil DIP CY8C22113 24PI 2 256 No 40C to 85C 4 3 6 4 1 No 8 Pin 150 Mil SOIC CY8C22113 24SI 2 256 No 40C to 85C 6 4 1 No Sia MII SOIC CY8C22113 24SIT 2 256 No 400t0 850 4 3 6 4 1 No Tape and Reel 20 Pin 300 Mil DIP CY8C22213 24PI 256 No 40C to 85C 16 1 Yes 20 Pin 210 Mil SSOP CY8C22213 24PVI 256 No 40C to 85C 16 1 Yes ZU Pin 210 Mi SSOP CY8C22213 24PVIT 2 256 No 400t0 850 4 3 16 8 1 ves Tape and Reel 20 Pin 300 Mil SOIC CY8C22213 24SI 2 256 No 40C to 85C 4 3 16 8 1 Yes 20 Pi 300 MII SOIG CY8C22213 24SIT 2 256 No 400t0 850 4 3 16 8 1 ves Tape and Reel 32 Pin 5x5 mm MLF CY8C22213 24LFI 2 256 No 40C to 85C 4 3 16 8 1 Yes 5 1 Ordering Code Definitions CY 8 C 22 xxx SPxx de Package Type T
8. Bop Large Signal Bandwidth 1Vop 3dB BW 100pF Load Power Low 300 kHz Power High 300 kHz Table 3 21 3 3V AC Analog Output Buffer Specifications Symbol Description Min Typ Max Units Notes Tros Rising Settling Time to 0 1 1V Step 100pF Load Power Low 3 8 us Power High 3 8 us TsoB Falling Settling Time to 0 1 1V Step 100pF Load Power Low 2 6 us Power High 26 us SRroB Rising Slew Rate 20 to 80 1V Step 100pF Load Power Low 0 5 V us Power High 0 5 V us SRroB Falling Slew Rate 80 to 20 1V Step 100pF Load Power Low 0 5 V us Power High 0 5 V us BWog Small Signal Bandwidth 20mV p 3dB BW 100pF Load Power Low 0 7 MHz Power High 0 7 MHz BWos Large Signal Bandwidth 1V 3dB BW 100pF Load Power Low 200 kHz Power High 200 kHz June 3 2004 Document No 38 12009 Rev E 28 Feedback CY8C22x13 Final Data Sheet 3 Electrical Specifications 3 4 6 AC External Clock Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges 4 75V to 5 25V and 40 C lt Ta lt 85 C or 3 0V to 3 6V and 40 C lt Ta lt 85 C respectively Typical parameters apply to 5V and 3 3V at 25 C and are for design guidance only or unless otherwise specified Table 3 22 5V AC External Clock Specifications Symbol Description Min Typ Max Units Notes
9. TRiseS Figure 3 7 GPIO Timing Diagram i eebe AES TFallF TFallS a June 3 2004 Document No 38 12009 Rev E 24 Feedback CY8C22x13 Final Data Sheet 3 Electrical Specifications 3 4 3 AC Operational Amplifier Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges 4 75V to 5 25V and 40 C lt Ta lt 85 C or 3 0V to 3 6V and 40 C lt Ta lt 85 C respectively Typical parameters apply to 5V and 3 3V at 25 C and are for design guidance only or unless otherwise specified Note Seitling times slew rates and gain bandwidth are based on the Analog Continuous Time PSoC block Table 3 17 5V AC Operational Amplifier Specifications Symbol Description Min Typ Max Units Notes TROA Rising Settling Time from 80 of AV to 0 1 of AV 10 pF Specification maximums for low power and load Unity Gain high opamp bias medium power and Power Low DI ES 3 9 us medium power and high opamp bias levels i d are between low and high power levels Power Low Opamp Bias High us Power Medium us Power Medium Opamp Bias High 0 72 us Power High us Power High Opamp Bias High 0 62 us TsoA Falling Settling Time from 2096 of AV to 0 196 of AV 10 pF Specification maximums for low power and load Unity Gain high opamp bias medium power and Power Low JE E 59 us
10. devices The PSoC Designer IDE and application runs on Windows 98 Windows NT 4 0 Windows 2000 Windows Millennium Me or Windows XP Reference the PSoC Designer Functional Flow diagram below PSoC Designer helps the customer to select an operating con figuration for the PSoC write application code that uses the PSoC and debug the application This system provides design database management by project an integrated debugger with In Circuit Emulator in system programming support and the CYASM macro assembler for the CPUs PSoC Designer also supports a high level C language compiler developed specifically for the devices in the family i i Context TM Graphical Designer e ani n Designer Help Importable Design CH Database Device PSoC Database Configuration PSoC Sheet Application Designer Database Core Engine Manufacturing Project Information Database File User Modules e Library Emulation In Circuit Device Pod Emulator Programmer PSoC Designer Subsystems June 3 2004 Document No 38 12009 Rev E 4 Feedback CY8C22x13 Final Data Sheet PSoC Overview PSoC Designer Software Subsystems Device Editor The Device Editor subsystem allows the user to select different onboard analog and digital components called user modules using the PSoC blocks Examples of user modules are ADCs DACs Amplifiers and Filters The device editor
11. ware as well as the software This substantially lowers the risk of having to select a different part to meet the final design requirements To speed the development process the PSoC Designer Inte grated Development Environment IDE provides a library of pre built pre tested hardware peripheral functions called User Modules User modules make selecting and implementing peripheral devices simple and come in analog digital and mixed signal varieties The standard User Module library con tains over 50 common peripherals such as ADCs DACs Tim ers Counters UARTs and other not so common peripherals such as DTMF Generators and Bi Quad analog filter sections Each user module establishes the basic register settings that implement the selected function It also provides parameters that allow you to tailor its precise configuration to your particular application For example a Pulse Width Modulator User Mod ule configures one or more digital PSoC blocks one for each 8 bits of resolution The user module parameters permit you to establish the pulse width and duty cycle User modules also provide tested software to cut your development time The user module application programming interface API provides high level functions to control and respond to hardware events at run time The API also provides optional interrupt service rou tines that you can adapt as needed The API functions are documented in user module data sheets that
12. 1 ID mm DIMENSIONS IN INCHESCMM MIN DE 7 6201 MAX naana REFERENCE JEDEC MO 119 04191105421 PACKAGE WEIGHT 0 55gms ween 20 3 STANDARD PKG 7 Steen LEAD FREE PKG E 0497026231 SEATING PLANE 0313013 0301 IEEE x sese samen 51 85024 B Figure 4 5 20 Lead 300 Mil Molded SOIC June 3 2004 Document No 38 12009 Rev E 33 Feedback CY8C22x13 Final Data Sheet 4 Packaging Information 0 05 C el bt MAX 0 20 REF 4 2 TOP VIEW SEATING PLANE SIDE VIEW DIMENSIONS IN mm MIN MAX X 138 MIL Y 138 MIL X 4 0 23 0 05 4 SIN 32 0 20 R ZU s t 20 45 P E PAS d Y S 4 3 50 c DI CH D Cj 040 080 lt a AO UD AN 07 poe 0 50 4X 3 50 BOTTOM VIEW 51 85188 Figure 4 6 32 Lead 5x5 mm MLF Thermal Impedances Table 4 1 Thermal Impedances per Package Package Typical 04 8 PDIP 123 C W 8 SOIC 185 C W 20 PDIP 109 C W 20 SSOP 117 C W 20 SOIC 81 C W 32 MLF 22 C W Ty Ta POWER x Bus 4 3 Capacitance on Crystal Pins Table 4 2 Typical Package Capacitance on Crystal Pins Package Package Capacitance 8 PDIP 2 8 pF 8 SOIC 2 0 pF 20 PDIP 3 0 pF 20 SSOP 2 6 pF 20 SOIC 2 5 pF 32 MLF 2 0 pF June 3 2004
13. 19 NC No connection Do not use 20 NC No connection Do not use 21 NC No connection Do not use 22 NC No connection Do not use 23 IO I PO O Analog column mux input 24 IO I Po 2 Analog column mux input 25 NC No connection Do not use 26 IO I PO 4 Analog column mux input 27 IO I PO 6 Analog column mux input 28 Power Vdd Supply voltage 29 IO I PO 7 Analog column mux input 30 IO IO PO 5 Analog column mux input and column output 31 IO PO S Analog column mux input 32 IO I PO 1 Analog column mux input LEGEND A Analog Input and O Output The MLF package has a center pad that must be connected to the same ground as the Vss pin CY8C22213 PSoC Device NC NC NC NC Vss Vss 12C SCL P1 7 GC SDA P1 5 e 32 PO 1 Al 0 4 OO P G ND A On z a amp x x d o a Oo e 316 PO 3 Al 80 PO 5 AIO 29e PO 7 Al 28e Vdd MLF Top View o o gt A 5 o zal lt x FE x Ed a D O e 27e P0 6 AI 266 PO 4 Al a a D x a o E X LI Po 2 Al PO O Al NC NC NC NC XRES P1 6 June 3 2004 Document No 38 12009 Rev E Feedback 2 Register Reference ESS MICROSYSTEMS This chapter lists the registers of the CY8C22x13 PSoC device by way of mapping tables in offset order For detailed register infor mation reference the PSoC Mixed Signal Array Technical Reference Manual 2
14. 85 C or 3 0V to 3 6V and 40 C lt Ta lt 85 C respectively Typical parameters apply to 5V and 3 3V at 25 C and are for design guidance only or unless otherwise specified Table 3 12 DC Analog PSoC Block Specifications Symbol Description Min Typ Max Units Notes Ret Resistor Unit Value Continuous Time 12 24 kQ Cgc Capacitor Unit Value Switch Cap 80 fF June 3 2004 Document No 38 12009 Rev E 19 Feedback CY8C22x13 Final Data Sheet 3 Electrical Specifications 3 3 7 DC POR and LVD Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges 4 75V to 5 25V and 40 C lt Ta lt 85 C or 3 0V to 3 6V and 40 C lt Ta lt 85 C respectively Typical parameters apply to 5V and 3 3V at 25 C and are for design guidance only or unless otherwise specified Note The bits PORLEV and VM in the table below refer to bits in the VLT_CR register See the PSoC Mixed Signal Array Technical Reference Manual for more information on the VLT_CR register Table 3 13 DC POR and LVD Specifications Symbol Description Min Typ Max Units Notes Vdd Value for PPOR Trip positive ramp VPPOROR PORLEV 1 0 00b 2 908 V VPPORIR PORLEV 1 0 01b 4 394 V VPPOR2R PORLEV 1 0 10b 4 548 V Vdd Value for PPOR Trip negative ramp VPPORO PORLEV 1 0 00b 2 816 V VPPORI PORLEV 1
15. DBBO1IN 25 RW 65 A5 E5 DBB010U 26 RW JAMD_CRI 66 RW A6 E6 27 ALT_CRO 67 RW A7 E7 DCBO2FN 28 RW 68 A8 IMO TR E8 Ww DCBO2IN 29 RW 69 A9 ILO TR E9 Ww DCB020U 2A RW 6A AA BDG_TR EA RW 2B 6B AB ECO_TR EB W DCBO3FN 2C RW 6C AG EC DCBOSIN 2D RW 6D AD ED DCB030U 2E RW 6E AE EE 2F 6F AF EF 30 70 RDIORI BO RW FO 31 71 RDIOSYN BI RW FI 32 72 RDIOIS B2 RW F2 33 73 RDIOLTO B3 RW F3 34 ACB01CR3 74 RW RDIOLT1 B4 RW F4 35 ACBO1CRO 75 RW RDIOROO B5 RW F5 36 ACBO1CR1 76 RW RDIORO1 B6 RW F6 37 ACB01CR2 77 RW B7 CPU_F F7 RL 38 78 B8 F8 39 79 B9 F9 3A 7A BA FA 3B 7B BB FB 3C 7C BC FC 3D 7D BD FD 3E 7E BE CPU SCR1 FE 3F 7F BF CPU_SCRO FF Blank fields are Reserved and should not be accessed Access is bit specific June 3 2004 Document No 38 12009 Rev E 12 Feedback 3 Electrical Specifications This chapter presents the DC and AC electrical specifications of the CY8C22x13 PSoC device For the most up to date electrical specifications confirm that you have the most recent data sheet by referencing the web at http www cypress com psoc Specifications are valid for 40 C lt Ta lt 85 C and Ty lt 100 C as specified except where noted Specifications for devices running at greater than 12 MHz are valid for 40 C lt T4 x 70 C and Ty lt 82 C T L_ _ _ ___ Figure 3 1 Voltage versus Operating Frequency 93 kHz CPU Frequency N E The following table lists the uni
16. Gain Setting Timing Diagram 32K Select 32 kHz HK4 Tos l Ge AAAAAAAAAAAAAT LI LT LI LI Figure 3 4 External Crystal Oscillator Startup Timing Diagram Jitter24M1 le Foam Figure 3 5 24 MHz Period Jitter IMO Timing Diagram Jitter32k Ad le Fake Figure 3 6 32 kHz Period Jitter ECO Timing Diagram June 3 2004 Document No 38 12009 Rev E 23 Feedback CY8C22x13 Final Data Sheet 3 Electrical Specifications 3 4 2 AC General Purpose IO Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges 4 75V to 5 25V and 40 C lt Ta lt 85 C or 3 0V to 3 6V and 40 C lt Ta lt 85 C respectively Typical parameters apply to 5V and 3 3V at 25 C and are for design guidance only or unless otherwise specified Table 3 16 AC GPIO Specifications Symbol Description Min Typ Max Units Notes Fepio GPIO Operating Frequency 0 12 MHz TRiseF Rise Time Normal Strong Mode Cload 50 pF 3 18 ns Vdd 4 5 to 5 25V 10 90 TFallF Fall Time Normal Strong Mode Cload 50 pF 2 18 ns Vdd 4 5 to 5 25V 10 90 TRiseS Rise Time Slow Strong Mode Cload 50 pF 10 27 ns Vdd 3 to 5 25V 10 90 TFallS Fall Time Slow Strong Mode Cload 50 pF 10 22 ns Vdd 3 to 5 25V 10 90 90 GPIO Pin 2 gt gt TRiseF
17. Specifica tions section Table 3 1 on page 13 lists all the abbreviations 4 Packaging Information 1 iiio o a secari ron nin enun 31 used to measure the PSoC devices 4 1 Packaging Dimensions 31 4 2 Thermal Impedances _ eee 34 Numeric Naming 4 3 Capacitance on Crystal Pins 34 Hexidecimal numbers are represented with all letters in upper 5 Ordering Information seeeeeseeeee 35 case with an appended lowercase h for example 14h or 5 1 Ordering Code Definitions 35 SAh Hexidecimal numbers may also be represented by a OX amp Sales and Company Information su nssnr1111100111221 36 prefix the C coding convention Binary numbers have an 6 1 Revision History 36 appended lowercase b e g 01010100b or 01000011b i i Numbers not indicated by an h or b are decimal 2 Copyrights sssssssesseeeeeeeenennnnnn June 3 2004 Document No 38 12009 Rev E 7 Feedback 1 Pin Information il RESS MICROSYSTEMS This chapter describes lists and illustrates the CY8C22x13 PSoC device pins and pinout configurations 1 1 Pinouts The CY8C22x13 PSoC device is available in a variety of packages which are listed and illustrated in the following tables Every port pin labeled with a P is capable of Digital IO However Vss Vdd SMP and XRES are not capable of Digital IO
18. Time 250 1002 ns Tsustorzc Set up Time for STOP Condition 4 0 0 6 us TBUFI2C Bus Free Time Between a STOP and START Condition 4 7 1 3 us Tspi2c Pulse Width of spikes are suppressed by the input fil 0 50 ns ter a A Fast Mode I2C bus device can be used in a Standard Mode I2C bus system but the requirement Eu par 250 ns must then be met This will automatically be the case if the device does not stretch the LOW period of the SCL signal If such device does stretch the LOW period of the SCL signal it must output the next data bit to the SDA line t max tsu pat 1000 250 1250 ns according to the Standard Mode I2C bus specification before the SCL line is released SDA T LOWI2C T lt gt gt T SUDATI2C HDSTAI2C BUFI2C r SCL gt x T S Tupstaiec T uppariec Tuichiec Tsustarec k Sr RARO GE IS Figure 3 8 Definition for Timing for Fast Standard Mode on the IC Bus June 3 2004 Document No 38 12009 Rev E 30 Feedback 4 Packaging Information ESS MICROSYSTEMS This chapter illustrates the packaging specifications for the CY8C22x13 PSoC device along with the thermal impedances for each package and the typical package capacitance on crystal pins 4 1 Packaging Dimensions DIMENSIONS IN INCHES MIN MAX 0 300 T3895 0 100 BSC EN SEATING 0 115 PLANE 0 180 MAX 0 145 0 008 0125 0 015 MIN E 0 10 014
19. also supports easy development of multiple configurations and dynamic reconfiguration Dynamic configu ration allows for changing configurations at run time PSoC Designer sets up power on initialization tables for selected PSoC block configurations and creates source code for an application framework The framework contains software to operate the selected components and if the project uses more than one operating configuration contains routines to switch between different sets of PSoC block configurations at run time PSoC Designer can print out a configuration sheet for a given project configuration for use during application pro gramming in conjunction with the Device Data Sheet Once the framework is generated the user can add application specific code to flesh out the framework It s also possible to change the selected components and regenerate the framework Design Browser The Design Browser allows users to select and import precon figured designs into the user s project Users can easily browse a catalog of preconfigured designs to facilitate time to design Examples provided in the tools include a 300 baud modem LIN Bus master and slave fan controller and magnetic card reader Application Editor In the Application Editor you can edit your C language and Assembly language source code You can also assemble com pile link and build Assembler The macro assembler allows the assembly code to be merged seamlessly wi
20. analog signal flows Analog peripherals are very flexible and can be customized to support specific application requirements Some of the more common PSoC analog functions most avail able as user modules are listed below m Analog to digital converters one with 6 to 14 bit resolution selectable as Incremental Delta Sigma and SAR Filters two pole band pass low pass and notch Amplifiers one with selectable gain to 48x Comparators one with 16 selectable thresholds DACs one with 6 to 9 bit resolution Multiplying DACs one with 6 to 9 bit resolution High current output drivers one with 30 mA drive as a Core Resource 1 3V reference as a System Resource m Many other topologies possible June 3 2004 Document No 38 12009 Rev E 2 Feedback CY8C22x13 Final Data Sheet PSoC Overview Analog blocks are provided in columns of three which includes one CT Continuous Time and two SC Switched Capacitor blocks The number of blocks is dependant on the device family which is detailed in the table titled PSoC Device Characteris tics on page 3 PO 7 LI Po 6 PO 5 4 r PO 4 PO 3 lt PO 2 PO 1 PO 0 Additional System Resources System Resources some of which have been previously listed provide additional capability useful to complete systems Addi tional resources include a decimator low voltage detecti
21. are viewed directly in the PSoC Designer IDE These data sheets explain the internal operation of the user module and provide performance specifications Each data sheet describes the use of each user module parameter and documents the set ting of each register controlled by the user module The development process starts when you open a new project and bring up the Device Editor a pictorial environment GUI for configuring the hardware You pick the user modules you need for your project and map them onto the PSoC blocks with point and click simplicity Next you build signal chains by intercon necting user modules to each other and the IO pins At this stage you also configure the clock source connections and enter parameter values directly or by selecting values from drop down menus When you are ready to test the hardware configuration or move on to developing code for the project you perform the Generate Application step This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the high level user module API functions Device Editor Placement and Parameter ization Source Code Generator User Module Selection Generate Application Application Editor Source Project Build Manager Code Manager g Editor 3 Build AII Debugger Event amp Interface Storage Breakpoint to ICE Inspector M anager
22. memory SRAM data memory and configurable IO are included in a range of conve nient pinouts and packages The PSoC architecture as illustrated on the left is comprised of four main areas PSoC Core Digital System Analog System and System Resources Configurable global busing allows all Digital Analog H ae the device resources to be combined into a complete custom Block Array Fa system The PSoC CY8C22x13 family can have up to two IO S ports that connect to the global digital and analog interconnects dod 1 Column Analog providing access to 4 digital blocks and 3 analog blocks 3 Blocks PG Input Muxing The PSoC Core The PSoC Core is a powerful engine that supports a rich fea ture set The core includes a CPU memory clocks and config Digital pecimator us FOR and Ev Vee urable GPIO General Purpose IO Clocks System Resets Ref i i The M8C CPU core is a powerful processor with speeds up to SYSTEM RESOURCES 24 MHz providing a four MIPS 8 bit Harvard architecture micro June 2004 Cypress MicroSystems Inc 2004 Document No 38 12009 Rev E 1 Feedback CY8C22x13 Final Data Sheet PSoC Overview processor The CPU utilizes an interrupt controller with 10 vec tors to simplify programming of real time embedded events Program execution is timed and protected using the included Sleep and Watch Dog Timers WDT Memory encompasses 2 KB of Flash for program storage 256 bytes of SRAM for data storage an
23. or Verify 0 8 V Vue Input High Voltage During Programming or Verify 2 2 V li p Input Current when Applying Vilp to P1 0 or P1 1 During 0 2 mA Driving internal pull down resistor Programming or Verify lip Input Current when Applying Vihp to P1 0 or P1 1 During B 1 5 mA Driving internal pull down resistor Programming or Verify Mou Output Low Voltage During Programming or Verify Vss 0 75 V VoHv Output High Voltage During Programming or Verify Vdd 1 0 Vdd V Flashenpp Flash Endurance per block 50 000 Erase write cycles per block Flashent Flash Endurance total 1 800 000 Erase write cycles Flashpr Flash Data Retention 10 Years a A maximum of 36 x 50 000 block endurance cycles is allowed This may be balanced between operations on 36x1 blocks of 50 000 maximum cycles each 36x2 blocks of 25 000 maximum cycles each or 36x4 blocks of 12 500 maximum cycles each and so forth to limit the total number of cycles to 36x50 000 and that no single block ever sees more than 50 000 cycles For the full industrial range the user must employ a temperature sensor user module FlashTemp and feed the result to the temperature argument before writing Refer to the Flash APIs Application Note AN2015 at http www cypress com under Application Notes for more information June 3 2004 Document No 38 12009 Rev E 21 Feedback CY8C22x13 Final Data Sheet 3 Electrical Spec
24. products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress MicroSystems June 2004 Cypress MicroSystems Inc 2004 Document No 38 12009 Rev E 36 Feedback
25. 0 01b E 4 394 V VPPOR2 PORLEV 1 0 10b 4 548 V PPOR Hysteresis VPHo PORLEV 1 0 00b 92 mV VPHI PORLEV 1 0 01b 0 mV Veus PORLEV 1 0 10b 0 D mV Vdd Value for LVD Trip Vivpo VM 2 0 000b 2 863 2 921 2 9798 V Vivi VM 2 0 001b 2 963 3 023 3 083 V Vivp2 VM 2 0 010b 3 070 3 133 3 196 V Vivps VM 2 0 011b 3 920 4 00 4080 V Vun VM 2 0 100b 4303 4483 14 573 Y Vivps VM 2 0 101b 4 550 4 643 4 736 x Vivpe VM 2 0 110b 4 632 4 727 4 822 V Vivpz VM 2 0 111b 4 718 4 814 4 910 v a Always greater than 50 mV above PPOR PORLEV 00 for falling supply b Always greater than 50 mV above PPOR PORLEV 10 for falling supply June 3 2004 Document No 38 12009 Rev E 20 Feedback CY8C22x13 Final Data Sheet 3 Electrical Specifications 3 3 8 DC Programming Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges 4 75V to 5 25V and 40 C lt Ta lt 85 C or 3 0V to 3 6V and 40 C lt Ta lt 85 C respectively Typical parameters apply to 5V and 3 3V at 25 C and are for design guidance only or unless otherwise specified Table 3 14 DC Programming Specifications Symbol Description Min Typ Max Units Notes Ippp Supply Current During Programming or Verify 5 25 mA Vip Input Low Voltage During Programming
26. 0 Wes EE 0 430 MAX 0 014 DOSS 51 85075 A Figure 4 1 8 Lead 300 Mil PDIP May 2004 O Cypress MicroSystems Inc 2003 Document No 38 12009 Rev E 31 Feedback CY8C22x13 Final Data Sheet 4 Packaging Information PIN 1 ID 1 DIMENSIONS IN INCHESLMMJ MIN 2 PIN 1 ID IS OPTIONAL ROUND ON SINGLE LEADFRAME RECTANGULAR ON MATRIX LEADFRAME 3 REFERENCE JEDEC MS 012 4 PACKAGE WEIGHT 0 07gms PART 08 15 STANDARD PKG 5208 15 LEAD FREE PKG SEATING PLANE BE x a pa ell Ti 0 03310 0057 ge 51 85066 C Figure 4 2 8 Lead 150 Mil SOIC 10 1 EF DIMENSIONS IN INCHES MIN 0 250 0 270 Qr ur ram hg RES Wr tp d 3 88 SEATING PLANE 0 280 cue ns DS 3 MIN wad Ahea Lum 38 51 85011 A Figure 4 3 20 Lead 300 Mil Molded DIP June 3 2004 Document No 38 12009 Rev E 32 Feedback CY8C22x13 Final Data Sheet 4 Packaging Information 0 I PIN ae 114 131 E VLA I 810 DIMENSIONS IN MILLIMETERS MIN MAX UU 20 7 00 m 7 40 i SEATING PLANE 25 umns P 235 MIN uU EE N 1 r d 1 i GAUGE PLANE 200 jos 165 0 25 pt MAX FOR ni 185 i x p LU Tool TT gt f I 0 05 Le 0 2 JL 022 25 REFS la 038 al la DD 0 95 51 85077 C Figure 4 4 20 Lead 210 Mil SSOP PIN
27. 1 2 1 The register conventions specific to this section are listed in the following table Register Conventions 1 Abbreviations Used 2 2 Register Mapping Tables The PSoC device has a total register address space of 512 bytes The register space is also referred to as IO space and is broken into two parts The XOI bit in the Flag register deter mines which bank the user is currently in When the XOI bit is set the user is said to be in the extended address space or the configuration registers Convention Description RW Read and write register or bit s Note In the following register mapping tables blank fields are R Read register or bit s Reserved and should not be accessed WwW Write register or bit s L Logical register or bit s C Clearable register or bit s Access is bit specific May 2004 Cypress MicroSystems Inc 2003 Document No 38 12009 Rev E 10 Feedback CY8C22x13 Final Data Sheet 2 Register Reference Register Map Bank 0 Table User Space z S B z S B z S B z S B m IQ o m I2 o9 m IQ bi m To Ei 8 29 8 ge 8 29 8 29 pen o _ o Kid o lt o PRTODR 00 RW 40 80 CO PRTOIE 01 RW 41 81 C1 PRTOGS 02 RW 42 82 C2 PRT
28. Electrical Specifications section Miscellaneous changes to I2C GDI RDI Registers and Digital Block chapters D 131803 12 22 2003 NWJ Changes to Electrical Specifications and miscellaneous small changes throughout the data sheet E 229421 06 03 2004 SFV New data sheet format and organization Reference the PSoC Mixed Signal Array Tech nical Reference Manual for additional information Title change Distribution External Public Posting None 6 2 Copyrights Cypress MicroSystems Inc 2004 All rights reserved PSoC Programmable System on Chip are trademarks of Cypress MicroSystems Inc All other trademarks or registered trademarks referenced herein are property of the respective corporations The information contained herein is subject to change without notice Cypress MicroSystems assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress MicroSystems product Nor does it convey or imply any license under patent or other rights Cypress MicroSystems does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress MicroSystems products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Micro Systems against all charges Cypress MicroSystems
29. FOSCEXT Frequency 0 24 24 MHz High Period 20 6 ns Low Period 20 6 _ ns Power Up IMO to Switch 150 us Table 3 23 3 3V AC External Clock Specifications Symbol Description Min Typ Max Units Notes FoscExr Frequency with CPU Clock divide by 12 0 12 12 MHz FOSCEXT Frequency with CPU Clock divide by 2 or greater 0 24 24 MHz High Period with CPU Clock divide by 1 41 7 ns Low Period with CPU Clock divide by 1 41 7 ns Power Up IMO to Switch 150 us a Maximum CPU frequency is 12 MHz at 3 3V With the CPU clock divider set to 1 the external clock must adhere to the maximum frequency and duty cycle requirements b If the frequency of the external clock is greater than 12 MHz the CPU clock divider must be set to 2 or greater In this case the CPU clock divider will ensure that the fifty per cent duty cycle requirement is met 3 4 7 AC Programming Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges 4 75V to 5 25V and 40 C lt Ta lt 85 C or 3 0V to 3 6V and 40 C lt Ta lt 85 C respectively Typical parameters apply to 5V and 3 3V at 25 C and are for design guidance only or unless otherwise specified Table 3 24 AC Programming Specifications Symbol Description Min Typ Max Units
30. Final Data Sheet PSoC Mixed Signal Array CY8C22113 and CY8C22213 in o M ESS MICROSYSTEMS Features W Powerful Harvard Architecture Processor E Precision Programmable Clocking W Additional System Resources C1 M8C Processor Speeds to 24 MHz O Internal 2 5 24 48 MHz Oscillator IC Slave Master and Multi Master to O Low Power at High Speed I 3 0to 5 25 V Operating Voltage O Industrial Temperature Range 40 C to 85 C Advanced Peripherals PSoC Blocks O 3 Rail to Rail Analog PSoC Blocks Provide Up to 14 Bit ADCs Up to 9 Bit DACs Programmable Gain Amplifiers Programmable Filters and Comparators O 4 Digital PSoC Blocks Provide 8 to 32 Bit Timers Counters and PWMs CRC and PRS Modules Full Duplex UART SPI Masters or Slaves Connectable to all GPIO Pins Complex Peripherals by Combining Blocks High Accuracy 24 MHz with Optional 32 768 kHz Crystal and PLL O Optional External Oscillator up to 24 MHz O Internal Oscillator for Watchdog and Sleep E Flexible On Chip Memory 2K Bytes Flash Program Storage 50 000 Erase Write Cycles 256 Bytes SRAM Data Storage In System Serial Programming ISSP Partial Flash Updates Flexible Protection Modes EEPROM Emulation in Flash W Programmable Pin Configurations 25 mA Sink on all GPIO Pull up Pull down High Z Strong or Open Drain Drive Modes on all GPIO Up to 8 Analog Inputs on GPIO One 30 mA Analog Outputs on GPIO Configura
31. Notes TRSCLK Rise Time of SCLK 1 20 ns TFSCLK Fall Time of SCLK 1 20 ns TssciK Data Set up Time to Falling Edge of SCLK 40 ns THSCLK Data Hold Time from Falling Edge of SCLK 40 e ns Fock Frequency of SCLK 0 8 MHz Terase Flash Erase Time Block E 15 ms TwRITE Flash Block Write Time 30 ms Tpsci Data Out Delay from Falling Edge of SCLK 45 ns June 3 2004 Document No 38 12009 Rev E 29 Feedback CY8C22x13 Final Data Sheet 3 Electrical Specifications 3 4 8 AC I C Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges 4 75V to 5 25V and 40 C lt Ta lt 85 C or 3 0V to 3 6V and 40 C lt Ta lt 85 C respectively Typical parameters apply to 5V and 3 3V at 25 C and are for design guidance only or unless otherwise specified Table 3 25 AC Characteristics of the I2C SDA and SCL Pins Standard Mode Fast Mode Symbol Description Min Max Min Max Units Notes Facts SCL Clock Frequency 0 100 0 400 kHz Tupstaizc Hold Time repeated START Condition After this 4 0 0 6 us period the first clock pulse is generated TLOWI2C LOW Period of the SCL Clock 4 7 1 3 us Tuiguec HIGH Period of the SCL Clock 4 0 0 6 us Tsystaizc Set up Time for a Repeated START Condition 4 7 7 0 6 us THDDATI2C Data Hold Time 0 0 us Tsupati2c Data Set up
32. ODM2 03 RW 43 83 C3 PRT1DR 04 RW 44 ASD11CRO 84 RW C4 PRTIIE 05 RW 45 ASD11CR1 85 RW C5 PRT1GS 06 RW 46 ASD11CR2 86 RW C6 PRT1DM2 07 RW 47 ASD11CR3 87 RW C7 08 48 88 C8 09 49 89 C9 0A 4A 8A CA 0B 4B 8B CB OG 4C 8C CC DD 4D 8D CD 0E 4E 8E CE OF 4F 8F CF 10 50 90 DO 11 51 91 D1 12 52 92 D2 13 53 93 D3 14 54 ASC21CRO 94 RW D4 15 55 ASC21CR1 95 RW D5 16 56 ASC21CR2 96 RW I2C CFG D6 RW 17 57 ASC21CR3 97 RW I2C SCR D7 18 58 98 12C_DR D8 RW 19 59 99 I2C MSCR D9 1A 5A 9A INT_CLRO DA RW 1B 5B 9B INT CLR1 DB RW 1C 5C 9C DC 1D 5D 9D INT CLR3 DD RW 1E 5E 9E INT MSK3 DE RW 1F 5F 9F DF DBBOODRO 20 AMX_IN 60 RW AO INT_MSKO EO RW DBBOODR1 21 Ww 61 A1 INT MSK1 E1 RW DBBOODR2 22 RW 62 A2 INT VC E2 RC DBBOOCRO 23 ARF_CR 63 RW A3 RES WDT E3 Ww DBBO1DRO 24 CMP_CRO 64 A4 DEC_DH E4 RC DBBO1DR1 25 Ww ASY CR 65 A5 DEC DL E5 RC DBBO1DR2 26 RW CMP CR1 66 RW A6 DEC CRO E6 RW DBB01CRO 27 67 A7 DEC_CRI E7 RW DCBO2DRO 28 68 A8 E8 DCBO2DR1 29 Ww 69 A9 E9 DCB02DR2 2A RW 6A AA EA DCBO2CRO 2B 6B AB EB DCBO3DRO 2C 6C AC EC DCBO3DR1 2D Ww 6D AD ED DCB03DR2 2E RW 6E AE EE DCBO3CRO 2F 6F AF EF 30 70 RDIORI BO RW FO 31 71 RDIOSYN BI RW F1 32 72 RDIOIS B2 RW F2 33 73 RDIOLTO B3 RW F3 34 ACBO1CR3 74 RW RDIOLT1 B4 RW F4 35 ACBO1CRO 75 RW RDIOROO B5 RW F5 36 ACBO1CR1 76 RW RDIORO1 B6 RW F6 37 ACB01CR2 77 RW B7 CPU_F F7 RL 38 78 B8 F8 39 79 B9 F9 3A 7A BA FA 3B 7B BB FB 3C 7C BC FC 3D 7D BD FD 3E 7E BE CPU SCR1 FE 3F 7F BF CPU_SCRO FF
33. Vss e 10 XTALout I2C SDA 11 IO P1 0 Crystal Output XTALout I2C Serial Data SDA 12 IO P1 2 13 IO P1 4 Optional External Clock Input EXTCLK 14 IO P1 6 15 Input XRES Active high external reset with internal pull down 16 IO PO 0 Analog column mux input 17 IO PO 2 Analog column mux input 18 IO I PO 4 Analog column mux input 19 IO PO 6 Analog column mux input 20 Power Vdd Supply voltage LEGEND A Analog Input and O Output June 2004 Document No 38 12009 Rev E 8 Feedback CY8C22x13 Final Data Sheet 1 Pin Information 1 1 3 32 Pin Part Pinout Table 1 3 32 Pin Part Pinout MLF i Type i a No Digital Analog ane E 1 NC No connection Do not use 2 NC No connection Do not use 3 NC No connection Do not use 4 NC No connection Do not use 5 Power Vss Ground connection 6 Power Vss Ground connection T IO P1 7 12C Serial Clock SCL 8 IO P1 5 12C Serial Data SDA 9 NC No connection Do not use 10 IO P1 3 11 IO P1 1 Crystal Input XTALin I2C Serial Clock SCL 12 Power Vss Ground connection 13 IO P1 0 Crystal Output XTALout I2C Serial Data SDA 14 IO P1 2 15 IO P1 4 Optional External Clock Input EXTCLK 16 NC No connection Do not use 17 IO P1 6 18 Input XRES Active high external reset with internal pull down
34. allows you define complex breakpoint events that include monitoring address and data bus values memory locations and external signals June 3 2004 Document No 38 12009 Rev E 6 Feedback CY8C22x13 Final Data Sheet PSoC Overview Document Conventions Acronyms Used The following table lists the acronyms that are used in this doc ument Table of Contents For an in depth discussion and more information on your PSoC device obtain the PSoC Mixed Signal Array Technical Refer ence Manual This document encompasses and is organized into the following chapters and sections Acronym Description 1 Pin Information severnnnnnnnvnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn 8 AC alternating current 1 1 PINOUTS 8 ADC analog to digital converter 1 1 1 8 Pin Part Pinout i 8 API application programming interface 1 1 2 20 Pin Part Pinout n 8 CPU central processing unit 1 1 3 32 Pin Part Pinout 9 CT continuous time 2 Register Reference tnnt 10 DAG digital to analog converter 2 1 Register Conventions 10 DC direct current 2 1 1 Abbreviations Used 10 EEPROM electrically erasable programmable read only memory 2 2 Register Mapping Tables A 10 ease 3 Electrical Specifications 13 GPIO ge
35. and links to FAQs and an Online Support Forum to aid the designer in getting started Hardware Tools In Circuit Emulator A low cost high functionality ICE In Circuit Emulator is avail able for development support This hardware has the capability to program single devices The emulator consists of a base unit that connects to the PC by way of the parallel or USB port The base unit is universal and will operate with all PSoC devices Emulation pods for each device family are available separately The emulation pod takes the place of the PSoC device in the target board and performs full speed 24 MHz operation se PSoC Development Tool Kit June 3 2004 Document No 38 12009 Rev E 5 Feedback CY8C22x13 Final Data Sheet PSoC Overview User Modules and the PSoC Development Process The development process for the PSoC device differs from that of a traditional fixed function microprocessor The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification change during development and by lowering inventory costs These configurable resources called PSoC Blocks have the ability to implement a wide variety of user selectable functions Each block has several registers that determine its function and connectivity to other blocks multiplexers buses and to the IO pins Iterative development cycles permit you to adapt the hard
36. associated AGND buffer Power Low 150 200 uA Power Low Opamp Bias High 300 400 uA Power Medium 600 800 uA Power Medium Opamp Bias High 1200 1600 uA Power High 2400 3200 uA Power High Opamp Bias High 4600 6400 uA PSRRoA Supply Voltage Rejection Ratio 60 dB June 3 2004 Document No 38 12009 Rev E 16 Feedback CY8C22x13 Final Data Sheet 3 Electrical Specifications Table 3 7 3 3V DC Operational Amplifier Specifications Symbol Description Min Typ Max Units Notes Vosoa Input Offset Voltage absolute value Low Power 1 65 10 mV Input Offset Voltage absolute value Mid Power 1 32 8 mV High Power is 5 Volt Only TCVosoa Average Input Offset Voltage Drift 7 0 35 0 uV c legoa Input Leakage Current Port 0 Analog Pins 20 pA Gross tested to 1 uA CiNOA Input Capacitance Port 0 Analog Pins 4 5 9 5 pF Package and pin dependent Temp 25 C Vemoa Common Mode Voltage Range 0 2 Vdd 0 2 V The common mode input voltage range is measured through an analog output buffer The specification includes the limitations imposed by the characteristics of the analog output buffer GoioA Open Loop Gain dB Specification is applicable at high power For Power Low 60 all other bias modes except high power high opamp bias minimum is 60 dB Power Medium 60 Power High 80 VOHIGHOA High Output Voltage Swing worst cas
37. ble Interrupt on all GPIO a aadd aaa ad Port 1 400 kHz Watchdog and Sleep Timers User Configurable Low Voltage Detection Integrated Supervisory Circuit On Chip Precision Voltage Reference aaan a Complete Development Tools Free Development Software PSoC Designer Full Featured In Circuit Emulator and Programmer Full Speed Emulation Complex Breakpoint Structure 128K Bytes Trace Memory aaa OF Port 0 Analog Drivers PSoC CORE SYSTEM BUS Global Digital Interconnect Global Analog Interconnect SRAM 256 Bytes SROM Flash 2K CPU Core M8C Sleep and Interrupt 39 Watchdog Controller I Multiple Clock Sources Includes IMO ILO PLL and ECO DIGITAL SYSTEM ANALOG SYSTEM PSoC Functional Overview The PSoC family consists of many Mixed Signal Array with On Chip Controller devices These devices are designed to replace multiple traditional MCU based system components with one low cost single chip programmable device PSoC devices include configurable blocks of analog and digital logic as well as programmable interconnects This architecture allows the user to create customized peripheral configurations that match the requirements of each individual application Additionally a fast CPU Flash program
38. d up to 2 KB of EEPROM emulated using the Flash Program Flash utilizes four protec tion levels on blocks of 64 bytes allowing customized software IP protection The PSoC device incorporates flexible internal clock genera tors including a 24 MHz IMO internal main oscillator accurate to 2 5 over temperature and voltage The 24 MHz IMO can also be doubled to 48 MHz for use by the digital system A low power 32 kHz ILO internal low speed oscillator is provided for the Sleep timer and WDT If crystal accuracy is desired the ECO 32 768 kHz external crystal oscillator is available for use as a Real Time Clock RTC and can optionally generate a crys tal accurate 24 MHz system clock using a PLL The clocks together with programmable clock dividers as a System Resource provide the flexibility to integrate almost any timing requirement into the PSoC device PSoC GPIOs provide connection to the CPU digital and analog resources of the device Each pin s drive mode may be selected from eight options allowing great flexibility in external interfac ing Every pin also has the capability to generate a system inter rupt on high level low level and change from last read The Digital System The Digital System is composed of 4 digital PSoC blocks Each block is an 8 bit resource that can be used alone or combined with other blocks to form 8 16 24 and 32 bit peripherals which are called user module references Digital Clocks To Sys
39. e internal load Power Low Vdd 0 2 V Power Medium Vdd 0 2 V Power High is 5V only Vdd 0 2 V VoLowoa Low Output Voltage Swing worst case internal load Power Low 0 2 V Power Medium 0 2 V Power High 0 2 V Ison Supply Current including associated AGND buffer Power Low 150 200 uA Power Low Opamp Bias High 300 400 uA Power Medium 600 800 uA Power Medium Opamp Bias High 1200 1600 uA Power High 2400 3200 uA Power High Opamp Bias High 4600 6400 uA PSRRoa Supply Voltage Rejection Ratio 50 dB June 3 2004 Document No 38 12009 Rev E 17 Feedback CY8C22x13 Final Data Sheet 3 Electrical Specifications 3 3 4 DC Analog Output Buffer Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges 4 75V to 5 25V and 40 C lt Ta lt 85 C or 3 0V to 3 6V and 40 C lt Ta lt 85 C respectively Typical parameters apply to 5V and 3 3V at 25 C and are for design guidance only or unless otherwise specified Table 3 8 5V DC Analog Output Buffer Specifications Symbol Description Min Typ Max Units Notes VosoB Input Offset Voltage Absolute Value 3 12 mV TCVosoB Average Input Offset Voltage Drift 6 uV C VcMoB Common Mode Input Voltage Range 0 5 Vdd 1 0 V Ro
40. hermal Rating P PDIP C Commercial S SOIC Industrial PV SSOP E Extended LF MLF A TQFP Speed 24 MHz Part Number Family Code Technology Code C CMOS Marketing Code 8 Cypress MicroSystems Company ID CY Cypress June 3 2004 Document No 38 12009 Rev E 35 Feedback 6 Sales and Company Information J M US l ESS MICROSYSTEMS To obtain information about Cypress MicroSystems or PSoC sales and technical support reference the following information or go to the section titled Getting Started on page 4 in this document Cypress MicroSystems 2700 162nd Street SW Building D Lynnwood WA 98037 Phone 800 669 0557 Facsimile 425 787 4641 Web Sites Company Information http www cypress com Sales http www cypress com aboutus sales locations cfm Technical Support http www cypress com support login cfm 6 1 Revision History Table 6 1 CY8C22x13 Data Sheet Revision History Document Title CY8C22113 and CY8C22213 PSoC Mixed Signal Array Final Data Sheet Document Number 38 12009 Revision ECN Issue Date Origin of Change Description of Change Ke 128180 06 30 2003 New Silicon New document Advanced Data Sheet two page product brief A 129202 09 16 2003 NWJ New document Preliminary Data Sheet 300 page product detail B 130127 10 15 2003 NWJ Revised document for Silicon Revision A C 131679 12 05 2003 NWJ Changes to
41. ias High 200 nV rt Hz June 3 2004 Document No 38 12009 Rev E 25 Feedback CY8C22x13 Final Data Sheet 3 Electrical Specifications Table 3 18 3 3V AC Operational Amplifier Specifications Symbol Description Min Typ Max Units Notes TROA Rising Settling Time from 80 of AV to 0 1 of AV 10 pF Specification maximums for low power and load Unity Gain high opamp bias medium power and Power Low Pa E 3 92 us medium power and high opamp bias levels are between low and high power levels Power Low Opamp Bias High us Power Medium us Power Medium Opamp Bias High 0 72 us Power High 3 3 Volt High Bias Operation not supported us Power High Opamp Bias High 3 3 Volt High Power High Opamp Bias not supported us TsoA Falling Settling Time from 2096 of AV to 0 196 of AV 10 pF Specification maximums for low power and load Unity Gain high opamp bias medium power and Power Low S 5 41 us medium power and high opamp bias levels i are between low and high power levels Power Low Opamp Bias High us Power Medium us Power Medium Opamp Bias High 0 72 US Power High 3 3 Volt High Bias Operation not supported us Power High Opamp Bias High 3 3 Volt High Power High Opamp Bias not supported us SRroa Rising Slew Rate 20 to 80 10 pF load Unity Gain Specification minimums for low power a
42. ic Discharge Voltage 2000 V Latch up Current 200 mA 3 2 Operating Temperature Table 3 3 Operating Temperature Symbol Description Min Typ Max Units Notes Ta Ambient Temperature 40 85 oG Ty Junction Temperature 40 100 oc The temperature rise from ambient to junction is package specific See Thermal Impedances on page 34 The user must limit the power con sumption to comply with this requirement June 3 2004 Document No 38 12009 Rev E 14 Feedback CY8C22x13 Final Data Sheet 3 Electrical Specifications 3 3 DC Electrical Characteristics 3 3 1 DC Chip Level Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges 4 75V to 5 25V and 40 C lt T4 lt 85 C or 3 0V to 3 6V and 40 C lt T4 lt 85 C respectively Typical parameters apply to 5V and 3 3V at 25 C and are for design guidance only or unless otherwise specified Table 3 4 DC Chip Level Specifications Symbol Description Min Typ Max Units Notes Vdd Supply Voltage 3 00 5 25 V Ipp Supply Current T 5 8 mA Conditions are Vdd 5 0V 25 C CPU 3 MHz 48 MHz disabled VC1 1 5 MHz VC2 93 75 kHz VC3 93 75 kHz Jos Supply Current 3 3 6 0 mA Conditions are Vdd 3 3V Ta 25 C CPU 3 MHz 48 MHz Disabled VC1 1 5 MHz VC2 93 75 kHz VC3 93 75 kHz Isp Sleep Mode Current wi
43. ifications 3 4 3 4 1 AC Electrical Characteristics AC Chip Level Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges 4 75V to 5 25V and 40 C lt T4 lt 85 C or 3 0V to 3 6V and 40 C lt T4 lt 85 C respectively Typical parameters apply to 5V and 3 3V at 25 C and are for design guidance only or unless otherwise specified Table 3 15 AC Chip Level Specifications 32 768 kHz crystal 3 0V lt Vdd lt 5 5V 40 C lt T4 lt 85 C PLL Enable D Le Tru stew gt 24 MHz Fu XXXL TT PLL Gain Figure 3 2 PLL Lock Timing Diagram Symbol Description Min Typ Max Units Notes Fimo Internal Main Oscillator Frequency 23 4 24 24 62 MHz Trimmed Utilizing factory trim values Foput CPU Frequency 5V Nominal 0 93 24 24 68 MHz Fon CPU Frequency 3 3V Nominal 0 93 12 42 30 MHz F48M Digital PSoC Block Frequency 0 48 49 23b d MHz Sa to the AC Digital Block Specifications elow Foam Digital PSoC Block Frequency 0 24 24 6bed MHz F30K1 Internal Low Speed Oscillator Frequency 15 32 64 kHz F3ok2 External Crystal Oscillator 32 768 kHz Accuracy is capacitor and crystal dependent 50 duty cycle FPLL PLL Frequency 23 986 MHz Is a multiple x732 of crystal frequency Jitter24M2 24 MHz Period Jitter PLL
44. l parameters apply to 5V at 25 C and are for design guidance only Table 3 6 5V DC Operational Amplifier Specifications Symbol Description Min Typ Max Units Notes Vosoa Input Offset Voltage absolute value Low Power 1 6 10 mV Input Offset Voltage absolute value Mid Power 1 3 8 mV Input Offset Voltage absolute value High Power 1 2 7 5 mV TCVosoa Average Input Offset Voltage Drift 7 0 35 0 uVv C IEBOA Input Leakage Current Port 0 Analog Pins 20 pA Gross tested to 1 LA Cinoa Input Capacitance Port 0 Analog Pins 4 5 9 5 pF Package and pin dependent Temp 25 C Vemoa Common Mode Voltage Range 0 0 Vdd V The common mode input voltage range is mea Common Mode Voltage Range high power or high 0 5 Vdd 0 5 sured through an analog output buffer The opamp bias specification includes the limitations imposed by the characteristics of the analog output buffer GoioA Open Loop Gain dB Specification is applicable at high power For all Power Low 60 other bias modes except high power high opamp bias minimum is 60 dB Power Medium 60 Power High 80 VOHIGHOA High Output Voltage Swing worst case internal load Power Low Vdd 0 2 V Power Medium Vdd 0 2 V Power High Vdd 0 5 V VoL owoA Low Output Voltage Swing worst case internal load Power Low 0 2 V Power Medium 0 2 V Power High 0 5 V Ison Supply Current including
45. medium power and high opamp bias levels j are between low and high power levels Power Low Opamp Bias High us Power Medium us Power Medium Opamp Bias High 0 92 us Power High us Power High Opamp Bias High 0 72 us SRroa Rising Slew Rate 20 to 80 10 pF load Unity Gain Specification minimums for low power and Power Low 0 15 E V us high opamp bias medium power and medium power and high opamp bias levels Power Low Opamp Bias High V us are between low and high power levels Power Medium V us Power Medium Opamp Bias High 1 7 V us Power High V us Power High Opamp Bias High 6 5 V us SRroA Falling Slew Rate 20 to 80 10 pF load Unity Gain Specification minimums for low power and Power Low 0 01 KE V us high opamp bias medium power and medium power and high opamp bias levels Power Low Opamp Bias High Vis are between low and high power levels Power Medium V us Power Medium Opamp Bias High 0 5 V us Power High Vius Power High Opamp Bias High 4 0 V us BWoa Gain Bandwidth Product Specification minimums for low power and Power Low 0 75 M MHz high opamp bias medium power and medium power and high opamp bias levels Power Low Opamp Bias High MHz are between low and high power levels Power Medium MHz Power Medium Opamp Bias High 3 1 MHz Power High MHz Power High Opamp Bias High 5 4 MHz ENOA Noise at 1 kHz Power Medium Opamp B
46. nd Power Low 0 31 T V us high opamp bias medium power and medium power and high opamp bias levels Power Low Opamp Bias High V us are between low and high power levels Power Medium V us Power Medium Opamp Bias High 2 7 Vius Power High 3 3 Volt High Bias Operation not supported V us Power High Opamp Bias High 3 3 Volt High Power High Opamp Bias not supported V us SRroa Falling Slew Rate 20 to 80 10 pF load Unity Gain Specification minimums for low power and Power Low 0 24 _ V us high opamp bias medium power and medium power and high opamp bias levels Power Low Opamp Bias High V us are between low and high power levels Power Medium V us Power Medium Opamp Bias High 1 8 V us Power High 3 3 Volt High Bias Operation not supported V us Power High Opamp Bias High 3 3 Volt High Power High Opamp Bias not supported V us BWoa Gain Bandwidth Product Specification minimums for low power and Power Low 0 67 MHz high opamp bias medium power and medium power and high opamp bias levels Power Low Opamp Bias High MHz are between low and high power levels Power Medium MHz Power Medium Opamp Bias High 2 8 MHz Power High 3 3 Volt High Bias Operation not supported MHz Power High Opamp Bias High 3 3 Volt High Power d z MHz High Opamp Bias not supported ENOA Noise at 1 kHz Power Medium Opamp Bias High 200 nV
47. neral purpose IO A 3 1 Absolute Maximum Ratings 14 IO input output R Dr imprecise poner ONTE 3 2 Operating Temperature _ 14 3 3 DC Electrical Characteristics 15 Eee east significant bit 3 3 1 DC Chip Level Specifications 15 EE low votageidetect 3 3 2 DC General Purpose IO Specifications 15 MSb most significant bit 3 3 3 DC Operational Amplifier Specifications 16 PC program counter 3 3 4 DC Analog Output Buffer Specifications 18 POR power on reset 3 3 5 DC Analog Reference Specifications 19 PPOR precision power on reset 3 3 6 DC Analog PSoC Block Specifications 19 PSoc Programmable System on Chip 3 3 7 DC POR and LVD Specifications 20 PWM pulse width modulator 3 3 8 DC Programming Specifications 21 RAM random access memory 3 4 AC Electrical Characteristics T eene 22 ROM read iiy mamonyi 3 4 1 AC Chip Level Specifications eee 22 SS ii ne 3 4 2 AC General Purpose IO Specifications 24 3 4 3 AC Operational Amplifier Specifications 25 SMP switeh mode pump 3 44 AC Digital Block Specifications 27 3 4 5 AC Analog Output Buffer Specifications 28 3 4 6 AC External Clock Specifications 29 Units of Measure 3 4 7 AC Programming Specifications 29 3 4 8 AC I2C Specifications 30 A units of measure table is located in the Electrical
48. ns for the voltage and temperature ranges 4 75V to 5 25V and 40 C lt Ta lt 85 C or 3 0V to 3 6V and 40 C lt Ta lt 85 C respectively Typical parameters apply to 5V and 3 3V at 25 C and are for design guidance only or unless otherwise specified The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks The power levels for AGND refer to the power of the Analog Continuous Time PSoC block The power levels for RefHi and RefLo refer to the Analog Reference Control register The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block Table 3 10 5V DC Analog Reference Specifications Symbol Description Min Typ Max Units gt AGND Vdd 2 CT Block Power High Vdd 2 0 043 Vdd 2 0 025 Vdd 2 0 003 V a AGND tolerance includes the offsets of the local buffer in the PSoC block Bandgap voltage is 1 3V 2 Table 3 11 3 3V DC Analog Reference Specifications Symbol Description Min Typ Max Units AGND Vdd 2 CT Block Power High Vdd 2 0 037 Vdd 2 0 020 Vdd 2 0 002 V a AGND tolerance includes the offsets of the local buffer in the PSoC block Bandgap voltage is 1 3V 2 3 3 6 DC Analog PSoC Block Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges 4 75V to 5 25V and 40 C lt Ta lt
49. oCPat E z2 zg g ET l Number SH oo Dio Siae Es Lo N ASD11 a act Am 4E a lt 8 lt a l LI up to LI l ASC21 CY8C29x66 64 4 16 12 4 4 12 l V WEE up to LI CY8C27x66 ia 2 8 12 4 4 12 E up to FI Analog Reference CY8C27x43 aA 2 8 12 4 4 12 p e EE 5 ll Interfaceto i Ref up to j dnt RefHi eference La AGNDIn CY8C24x23 S 1 4 12 2 2 6 L p Digital System RefLo t Generators le Refin i AGND lt Band T E 0 cysc22x13 d NPA 4 4 8 1 1 3 M8C Interface Address Bus Data Bus Etc Analog System Block Diagram June 3 2004 Document No 38 12009 Rev E 3 Feedback CY8C22x13 Final Data Sheet PSoC Overview Getting Started The quickest path to understanding the PSoC silicon is by read ing this data sheet and using the PSoC Designer Integrated Development Environment IDE This data sheet is an over view of the PSoC integrated circuit and presents specific pin register and electrical specifications For in depth information along with detailed programming information reference the PSoC Mixed Signal Array Technical Reference Manual For up to date Ordering Packaging and Electrical Specification information reference the latest PSoC device data sheets on the web at http www cypress com psoc Development Kits Development Kits are available from the following distributors Digi Key Avnet Arrow and Future The Cypress Online Store at http
50. on and power on reset Brief statements describing the merits of each system resource are presented below m Digital clock dividers provide three customizable clock fre quencies for use in applications The clocks can be routed to both the digital and analog systems Additional clocks can be generated using digital PSoC blocks as clock dividers m The decimator provides a custom hardware filter for digital signal processing applications including the creation of Delta Sigma ADCs m The 12C module provides 100 and 400 kHz communication over two wires Slave master and multi master modes are all supported m Low Voltage Detection LVD interrupts can signal the appli cation of falling voltage levels while the advanced POR Power On Reset circuit eliminates the need for a system supervisor m An internal 1 3 voltage reference provides an absolute refer ence for the analog system including ADCs and DACs WW Array Input Configuration MER eresse SON CERE E PSoC Device Characteristics Lu d SR D I i Aciort 07 Acr Depending on your PSoC device characteristics the digital and I I analog systems can have 16 8 or 4 digital blocks and 12 6 or I 7 3 analog blocks The following table lists the resources I EE available for specific PSoC device groups I Block Arra z S is I asa Nec EE j PSoC Device Characteristics Ir ACBO1 D o DE o Da N PS
51. rt Hz June 3 2004 Document No 38 12009 Rev E 26 Feedback CY8C22x13 Final Data Sheet 3 Electrical Specifications 3 4 4 AC Digital Block Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges 4 75V to 5 25V and 40 C lt Ta lt 85 C or 3 0V to 3 6V and 40 C lt Ta lt 85 C respectively Typical parameters apply to 5V and 3 3V at 25 C and are for design guidance only or unless otherwise specified Table 3 19 AC Digital Block Specifications Function Description Min Typ Max Units Notes Timer Capture Pulse Width 502 ns Maximum Frequency No Capture 49 2 MHz 4 75V lt Vdd 5 25V Maximum Frequency With Capture 24 6 MHz Counter Enable Pulse Width 502 ns Maximum Frequency No Enable Input 49 2 MHz 4 75V lt Vdd lt 5 25V Maximum Frequency Enable Input 24 6 MHz Dead Band Kill Pulse Width Asynchronous Restart Mode 20 ns Synchronous Restart Mode 502 ns Disable Mode 502 ns Maximum Frequency 49 2 MHz 4 75V lt Vdd lt 5 25V CRCPRS Maximum Input Clock Frequency 49 2 MHz 4 75V lt Vdd 5 25V PRS Mode CRCPRS Maximum Input Clock Frequency 24 6 MHz CRC Mode SPIM Maximum Input Clock Frequency 8 2 MHz SPIS Maximum Input Clock Frequency 4 1 ns Width of SS_ Negated Between Transmissions 508
52. tem Bus From Core To Analog System DIGITAL SYSTEM SYSTEM Digital PSoC Block Array o o E S Row Input Configurati uomneanByu MOH GIE 7 0 Global Digital GOE 7 0 GIO 7 0 Interconnect LL GO07 0 Digital System Block Diagram Digital peripheral configurations include those listed below PWMs 8 to 32 bit PWMs with Dead band 8 to 32 bit Counters 8 to 32 bit Timers 8 to 32 bit UART 8 bit with selectable parity up to 1 SPI master and slave up to 1 I2C slave and master 1 available as a System Resource Cyclical Redundancy Checker Generator 8 to 32 bit IrDA up to 1 Pseudo Random Sequence Generators 8 to 32 bit The digital blocks can be connected to any GPIO through a series of global buses that can route any signal to any pin The buses also allow for signal multiplexing and for performing logic operations This configurability frees your designs from the con straints of a fixed peripheral controller Digital blocks are provided in rows of four where the number of blocks varies by PSoC device family This allows you the opti mum choice of system resources for your application Family resources are shown in the table titled PSoC Device Charac teristics on page 3 The Analog System The Analog System is composed of 3 configurable blocks each comprised of an opamp circuit allowing the creation of complex
53. th C code The link libraries auto matically use absolute addressing or can be compiled in relative mode and linked with other software modules to get absolute addressing C Language Compiler A C language compiler is available that supports Cypress MicroSystems PSoC family devices Even if you have never worked in the C language before the product quickly allows you to create complete C programs for the PSoC family devices The embedded optimizing C compiler provides all the features of C tailored to the PSoC architecture It comes complete with embedded libraries providing port and bus operations standard keypad and display support and extended math functionality Debugger The PSoC Designer Debugger subsystem provides hardware in circuit emulation allowing the designer to test the program in a physical system while providing an internal view of the PSoC device Debugger commands allow the designer to read and program and read and write data memory read and write IO registers read and write CPU registers set and clear break points and provide program run halt and step control The debugger also allows the designer to create a trace buffer of registers and memory locations of interest Online Help System The online help system displays online context sensitive help for the user Designed for procedural and quick reference each functional subsystem has its own context sensitive help This system also provides tutorials
54. th POR LVD Sleep Timer and 3 6 5 uA Conditions are with internal slow speed oscilla WDT2 tor Vdd 3 3V 40 C lt Ty lt 55 C IsBH Sleep Mode Current with POR LVD Sleep Timer and 4 25 uA Conditions are with internal slow speed oscilla WDT at high temperature tor Vdd 3 3V 55 C T4 lt 85 C ISBXTL Sleep Mode Current with POR LVD Sleep Timer WDT 4 7 5 uA Conditions are with properly loaded 1 uW max and external crystal 32 768 kHz crystal Vdd 3 3V 40 C lt T4 lt 55 C ISBXTLH Sleep Mode Current with POR LVD Sleep Timer WDT 5 26 uA Conditions are with properly loaded 1 uW max and external crystal at high temperature 32 768 kHz crystal Vdd 3 3V 55 C lt Ty lt 85 OC VREF Reference Voltage Bandgap 1 275 1 3 1 325 V Trimmed for appropriate Vdd a Standby current includes all functions POR LVD WDT Sleep Time needed for reliable system operation This should be compared with devices that have similar functions enabled 3 3 2 DC General Purpose IO Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges 4 75V to 5 25V and 40 C lt T4 lt 85 C or 3 0V to 3 6V and 40 C lt T4 lt 85 C respectively Typical parameters apply to 5V and 3 3V at 25 C and are for design guidance only or unless otherwise specified Table 3 5 DC GPIO Specifications
55. ts of measure that are used in this chapter Table 3 1 Units of Measure Symbol Unit of Measure Symbol Unit of Measure oC degree Celsius uw micro watts dB decibels mA milli ampere fF femto farad ms milli second Hz hertz mV milli volts KB 1024 bytes nA nano ampere Kbit 1024 bits ns nanosecond kHz kilohertz nv nanovolts kQ kilohm Q ohm MHz megahertz pA pico ampere MQ megaohm pF pico farad uA micro ampere pp peak to peak uF micro farad ppm parts per million uH micro henry ps picosecond us microsecond sps samples per second uV micro volts o sigma one standard deviation uVrms micro volts root mean square V volts June 2004 Document No 38 12009 Rev E d 4 2 ESS MICROSYSTI Y CY8C22x13 Final Data Sheet 3 Electrical Specifications 3 1 Absolute Maximum Ratings Table 3 2 Absolute Maximum Ratings Symbol Description Min Typ Max Units Notes TsrG Storage Temperature 55 100 oc Higher storage temperatures will reduce data retention time TA Ambient Temperature with Power Applied 40 85 oc Vdd Supply Voltage on Vdd Relative to Vss 0 5 6 0 V Vio DC Input Voltage Vss 0 5 Vdd 0 5 V DC Voltage Applied to Tri state Vss 0 5 Vdd 0 5 V luo Maximum Current into any Port Pin 25 450 mA Mao Maximum Current into any Port Pin Configured as Analog 50 50 mA Driver Stat
56. uroB Output Resistance Power Low 1 Q Power High 1 Q VOHIGHOB High Output Voltage Swing Load 32 ohms to Vdd 2 Power Low 0 5 x Vdd 1 1 v Power High a 2 V 0 5 x Vdd 1 1 VoLowo8 Low Output Voltage Swing Load 32 ohms to Vdd 2 Power Low 0 5 x Vdd 1 3 V Power High 0 5 x Vdd 1 3 V Loop Supply Current Including Bias Cell No Load Power Low 1 1 5 1 mA Power High 2 6 8 8 mA PSRRog Supply Voltage Rejection Ratio 60 dB Table 3 9 3 3V DC Analog Output Buffer Specifications Symbol Description Min Typ Max Units Notes Vosos Input Offset Voltage Absolute Value 3 12 mV TCVosoB Average Input Offset Voltage Drift 6 uV C VemoB Common Mode Input Voltage Range 0 5 Vdd 1 0 V RouroB Output Resistance Power Low 1 Q Power High 1 Q VOHIGHOB High Output Voltage Swing Load 1K ohms to Vdd 2 Power Low 0 5 x Vdd 1 0 V Power High 0 5 x Vdd 1 0 p Y Voi owoB Low Output Voltage Swing Load 1K ohms to Vdd 2 Power Low 0 5 x Vdd 1 0 V Power High 0 5x Vdd 1 0 V Iso Supply Current Including Bias Cell No Load Power Low 0 8 2 0 mA Power High 2 0 4 3 mA PSRRog Supply Voltage Rejection Ratio 50 dB June 3 2004 Document No 38 12009 Rev E 18 Feedback CY8C22x13 Final Data Sheet 3 Electrical Specifications 3 3 5 DC Analog Reference Specifications The following tables list guaranteed maximum and minimum specificatio
57. www onfulfillment com cypressstore contains develop ment kits C compilers and all accessories for PSoC develop ment Click on PSoC Programmable System on Chip to view a current list of available items Tele Training Free PSoC Tele training is available for beginners and taught by alive marketing or application engineer over the phone Five training classes are available to accelerate the learning curve including introduction designing debugging advanced design advanced analog as well as application specific classes cover ing topics like PSoC and the LIN bus For days and times of the tele training see http www cypress com support training cfm Consultants Certified PSoC Consultants offer everything from technical assistance to completed PSoC designs To contact or become a PSoC Consultant go to the following Cypress support web site http www cypress com support cypros cfm Technical Support PSoC application engineers take pride in fast and accurate response They can be reached with a 4 hour guaranteed response at http www cypress com support login cfm Application Notes A long list of application notes will assist you in every aspect of your design effort To locate the PSoC application notes go to http www cypress com design results cfm Development Tools The Cypress MicroSystems PSoC Designer is a Microsoft Windows based integrated development environment for the Programmable System on Chip PSoC
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