Home

Cypress CY8C21534 User's Manual

1. PIN 11D 8 1 DIMENSIONS IN INCHESIMM MIN MAX REFERENCE JEDEC MS 012 F 0 150 3 810 PACKAGE WEIGHT 0 15gms 0 157 3 987 0 230 5 842 0 244 6 197 PART 16 15 STANDARD SZ16 15 LEAD FREE PKG 9 16 0 010 0 254 0 38619 8041 SEATING PLANE 00160 40 x 0 393 9 982 0 061 1 549 o 0 068 1 727 0 00410 1021 0 050 1 270 0 0075 0 190 BSC 0 8 0 01810 406 ___ 0 009810 2491 0 0138 0 350 0 004 0 102 0 035 0 889 0 0192 0 487 0 0098 0 249 51 85068 B Figure 21 20 Pin 210 MIL SSOP 0 1 L 114 lt lt 7 50 SP I 8 10 DIMENSIONS IN MILLIMETERS MIN MAX 11 20 7 00 7 40 i SEATING PLANE 235 MIN F 0 65 BSC i ca GAUGE PLANE 200 165 0 25 H J 185 Y 2 J desc 040 m 5 00 LOI 2 50 0 8 02 125 REF 0 38 0 55 0 55 51 85077 Document Number 38 12025 Rev O Page 34 of 45 Feedback PERFORM CY8C21634 CY8C21534 CY8C21434 CY8C21334 CY8C21234 Figure 22 28 Pin 210 Mil SSOP
2. 114 114 DIA 14 1 PIN 1 ID ry 144 7 30 i ai DIMENSIONS IN MILLIMETERS MIN 15 28 10 00 10 40 I SEATING PLANE 233 m 0 65 BSC O 1 r 1 i GAUGE PLANE eon 165 025 _________ 185 ffr h ts Y 0 10 llos j I 4d uns oix 0 38 51 85079 C i 32 Pi Figure 23 32 Pin 5 5 mm 0 93 MAX TOP VIEW SIDE VIEW 40 05 BOTTOM VIEW 4 90 E 5 10 0 93 MAX 4 65 0 05 MAX 4 85 0 20 REF 0 23 0 05 ID 0 50 DIA 0 80 1 0 20 R N Mn Ni i VUUUUUUY 1H H H 1 F2 0 45 2H H H az i 490 i q H NENNEN x 5 10 B H H 485 B 50 el 3 50 L D XXX H H H 559 H lt 000000009000 H H M H ED K lt X lt AKAA SSS 0 30 0 50 i 0 12 i 0 50 0 42 0 18 3 50 4 Cr lt PLANE i NOTES 1 AREA IS SOLDERABLE EXPOSED PAD 2 REFERENCE JEDEC MO 220 3 PACKAGE WEIGHT 0 054g E PAD X Y for this product is 3 53 mm 3 53 mm 0 11 mm 4 ALL DIMENSIONS ARE IN MM MIN MAX
3. o fe o o fe i 8 i 8 i 8 i 8 z 45 2 2 lt 2 2 45 2 2 lt 2 PRTODR 00 RW 40 ASE10CRO 80 RW PRTOIE 01 RW 41 81 C1 PRTOGS 02 RW 42 82 C2 PRTODM2 03 RW 43 83 C3 PRT1DR 04 RW 44 ASE11CRO 84 RW C4 05 RW 45 85 C5 PRT1GS 06 RW 46 86 C6 PRT1DM2 07 RW 47 87 C7 PRT2DR 08 RW 48 88 C8 PRT2IE 09 RW 49 89 C9 PRT2GS 0A RW 4A 8A CA PRT2DM2 0B RW 4B 8B CB PRT3DR 0 RW 4C 8C 00 RW 4D 8D CD PRT3GS 0 RW 4E 8E CE PRT3DM2 OF RW 4F 8F CF 10 50 90 CUR_PP DO RW 11 51 91 STK PP D1 RW 12 52 92 D2 13 53 93 IDX PP D3 RW 14 54 94 MVR PP 04 RW 15 55 95 MVW PP D5 RW 16 56 96 12 _ 06 RW 17 57 97 2 SCR D7 18 58 98 2 DR D8 RW 19 59 99 2 MSCR D9 9A INT CLRO DA RW 1B 5B 9B INT CLR1 DB RW 1D 5D 9D INT CLR3 DD RW 1 5 9F DF Blank fields are Reserved and must not be accessed Access is bit specific Document Number 38 12025 Rev O Page 15 of 45 Feedback Table 9 Register Map 0 Table User Space continued CY8C21634 CY8C21534 CY8C21434 CY8C21334 CY8C21234 2 2 f o 2 5 9
4. Page 43 of 45 Document Number 38 12025 Rev O Feedback Document History Page CY8C21634 CY8C21534 CY8C21434 CY8C21334 CY8C21234 Document Title CY8C21234 CY8C21334 CY8C21434 CY8C21534 CY8C21634 PSoC Programmable System on Chip Document Number 38 12025 Revision ECN No un Description of Change 7 227340 New silicon and document Revision A 235992 SFV See ECN Updated Overview and Electrical Spec chapters along with revisions to the 24 pin pinout part Revised the register mapping tables Added a SSOP 28 pin part B 248572 SFV See ECN Changed title to include all part 5 Changed 28 pin SSOP from CY8C21434 to CY8C21534 Changed pin 9 on the 28 pin SSOP from SMP pin to Vss pin Added SMP block to architecture diagram Update Electrical Specifications Added another 32 pin MLF part CY8C21634 C 277832 HMT See ECN Verify data sheet standards from SFV memo Add Analog Input Mux to appli cable pin outs Update PSoC Characteristics table Update diagrams and specs Final D 285293 HMT See ECN Update 2 7V DC GPIO spec Add Reflow Peak Temp table E 301739 See ECN DC Chip Level Specification changes Update links to new CY com Portal 329104 Re add pinout ISSP notation Fix TMP register names Clarify ADC feature Update Electrical Specifications Update Reflow Peak
5. Wy 55 8 21634 8 21534 CY8C21434 8 21334 CY8C21234 PERFORM PSoC9 Programmable System on Chip V Features m Powerful Harvard Architecture Processor M8C Processor Speeds to 24 MHz Low power at high speed 2 4 to 5 25V Operating Voltage Operating Voltages Down to 1 0V using On Chip Switch Mode Pump SMP Industrial Temperature Range 40 to 85 Advanced Peripherals PSoc Blocks 4 Analog Type E PSoC Blocks provide 2 Comparators with DAC Refs Single or Dual 8 Bit 28 Channel ADC 4 Digital PSoC Blocks provide 8 to 32 Bit Timers Counters and PWMs CRC and PRS Modules Full Duplex UART SPI Master or Slave Connectable to All GPIO Pins Complex Peripherals by Combining Blocks Flexible On Chip Memory 8K Flash Program Storage 50 000 Erase Write Cycles 512 Bytes SRAM Data Storage In System Serial Programming ISSP Partial Flash Updates Flexible Protection Modes EEPROM Emulation in Flash m Complete Development Tools Free Development Software PSoC Designer Full Featured In Circuit Emulator and Programmer Full Speed Emulation Complex Breakpoint Structure 128K Trace Memory m Precision Programmable Clocking Internal 2 5 24 48 MHz Oscillator Internal Oscillator for Watchdog and Sleep m Programmable Pin Configurations 25 mA Sink 10 mA Drive on GPIO Pull Up Pull Dow
6. 85 4 4 28 28 0 Yes SAWN QFNP I Tape and Reel 32 Pin 5 5 mm 0 60 CY8C21434 24LQXI 8K 512 40 85 4 4 28 2827 o Yes THIN SAWN QFN 32 Pin 5 5 mm 0 60 CY8C21434 24LQXIT 8K 512 40 C to 85 C 4 4 28 2827 o Yes THIN SAWN QFN Tape and Reel 32 Pin 5 5 mm 0 93 MAX CY8C21634 24LTXI 8K 512 Yes 40 C to 85 C 4 4 26 2627 0 Yes SAWN 29 32 Pin 5 5 mm 0 93 MAX CY8C21634 24LTXIT 8K 512 Yes 40 C to 85 C 4 4 26 26271 0 Yes SAWN F9 56 OCD SSOP CY8C21001 24PVXI 8K 512 Yes 40 85 4 4 26 2677 Yes Note For Die sales information contact a local Cypress sales office or Field Applications Engineer FAE Notes 27 All Digital IO Pins also connect to the common analog mux 28 Refer to the section 32 Pin Part Pinout on page 11 for pin differences Document Number 38 12025 Rev O Page 42 of 45 Feedback 8 21634 8 21534 CY8C21434 8 21334 CY8C21234 PERFORM Ordering Code Definitions Thermal Rating CY 8 C 21 xxx 24xx s FV sS Package Type PX PDIP Pb Free C Commercial Industrial SX SOIC Pb Free PVX SSOP Pb Free E Extended LFX LKX QFN Pb Free AX TQFP Pb Free Speed 24 MHz Part Number Family Code Technology Code C CMOS Marketing Code 8 Cypress PSoC Company ID CY Cypress
7. o e 7 8 8 8 z Document Number 38 12025 CY8C21634 CY8C21534 CY8C21434 CY8C21334 CY8C21234 Figure 9 CY8C21634 32 Pin PSoC Device Al M PO 1 M P2 7 M P2 5 M P2 3 M P2 1 SMP vss 12C SCL 1 7 Figure 11 M 12C SCL Vss on C Ch t9 M I2C SDA P1 5 PO 3 ax PD 5 cC gt 0 0 QFN Top View Vss 12 SDA P1 0 M P1 2 12 SCL P1 1 M EXTCLK P1 4 0 A 1 M 2216 M 2214 M 2 2 M 220 M P3 2 M P3 0 M XRES CY8C21634 32 Pin Sawn PSoC Device PO 1 P2 7 P2 5 P2 3 P2 1 SMP Vss P1 7 m1 m2 m4 m5 m6 m7 m8 gt gt gt lt lt lt lt lt lt S gt gt Nr cO CN CN NAN 24 23 22 QFN 21 Top View 20 19 18 17 aha AAAA 2245 72 7 S 8 8 d s gt PO O A M P2 6 2 4 2 2 2 0 P3 2 P3 0 XRES Page 11 of 45 Feedback CY8C21634 CY8C21534 CYPRESS CY8C21434 CY8C21334 CY8C21234 PERFORM Table 6 Pin Definitions CY8C21434 CY8C21634 32 Pin QFN Digital Name Description
8. All device programmers can be purchased from the Cypress Online Store 216 Modular Programmer The CY3216 Modular Programmer kit features a modular programmer and the MiniProg1 programming unit The modular programmer includes three programming module cards and supports multiple Cypress products The kit includes m Modular Programmer Base m 3 Programming Module Cards m MiniProg Programming Unit m PSoC Designer Software CD m Getting Started Guide m USB 2 0 Cable CYS3207ISSP In System Serial Programmer ISSP The CY32071SSP is a production programmer It includes protection circuitry and an industrial case that is more robust than the MiniProg in a production programming environment Note CY3207ISSP needs special software and is not compatible with PSoC Programmer The kit includes m CY3207 Programmer Unit m PSoC ISSP Software CD m 110 240V Power Supply Euro Plug Adapter m USB 2 0 Cable Programming adapter converts non DIP package to DIP footprint Specific details and ordering information for each of the adapters can be found at http www emulation com Third Party Tools Several tools have been specially designed by the following 3rd party vendors to accompany PSoC devices during devel opment and production Specific details for each of these tools can be found at http www cypress com under DESIGN RESOURCES gt gt Evaluation Boards Notes 8 21234 245 16 SOIC CY3250
9. PERFORM DC Analog Mux Bus Specifications Table 22 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges 4 75V to 5 25V and 40 lt TA 85 C 3 0V to 3 6V and 40 C lt TA x 85 C or 2 4V to 3 0V and 40 C x Ty x 85 C respectively Typical parameters apply to 5V 3 3V or 2 7V at 25 C and are for design guidance only Table 22 DC Analog Mux Bus Specifications Symbol Description Min Typ Max Units Notes Rsw Switch Resistance to Common Analog Bus 400 W gt 2 7V 800 W 12 4 lt lt 2 7V Rypp Resistance of Initialization Switch to Vdd 800 W DC POR and LVD Specifications Table 23 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges 4 75V to 5 25V and 40 C lt TA 85 C 3 0V to 3 6V and 40 lt TA x 85 or 2 4V to 3 0V and 40 lt TA lt 85 C respectively Typical parameters apply to 5V 3 3V or 2 7V at 25 C and are for design guidance only Table 23 DC POR and LVD Specifications Symbol Description Min Typ Units Notes Vdd Value for PPOR Trip Vdd must be greater than or equal Vpporo PORLEV 1 0 00b 2 36 2 40 V to 2 5V during startup reset from Vppor1 PORLEV 1 0 016 2 82 2 95 V the XRES pin or reset from Vppor2 PORLEV 1 0 10b 4 55 4 70 V Watchdog Vdd Value for LVD Trip Vivpo VM 2 0 000b 2
10. 24 6 MHz Counter Enable Pulse Width 50 ns Maximum Frequency No Enable Input 49 2 MHz 4 75 lt lt 5 25 Maximum Frequency Enable Input 24 6 MHz Dead Band Kill Pulse Width Asynchronous Restart Mode 20 ns Synchronous Restart Mode 50 ns Disable Mode 50 ns Maximum Frequency 49 2 MHz 4 75 lt lt 5 25 CRCPRS Input Clock Frequency 49 2 MHz 4 75 lt lt 5 25V PRS Mode CRCPRS Maximum Input Clock Frequency 24 6 MHz CRC Mode SPIM Maximum Input Clock Frequency 8 2 MHz Maximum data rate at 4 1 MHz due to 2 x over clocking SPIS Maximum Input Clock Frequency 4 1 MHz Width of SS_ Negated Between Transmissions 50 ns Transmitter Maximum Input Clock Frequency 24 6 MHz Maximum data rate at 3 08 MHz due to 8 x over clocking Maximum Input Clock Frequency with Vdd gt 49 2 MHz Maximum data rate at 6 15 MHz 4 75V 2 Stop Bits due to 8 x over clocking Receiver Maximum Input Clock Frequency 24 6 MHz Maximum data rate at 3 08 MHz due to 8 x over clocking Maximum Input Clock Frequency with Vdd gt 49 2 MHz Maximum data rate at 6 15 MHz 4 75V 2 Stop Bits due to 8 x over clocking Note 19 50 ns minimum input pulse width is based on the input synchronizers running at 12 MHz 84 ns nominal period Document Number 38 12025 Rev O Page 29 of 45 Feedback CY8C21634 CY8C21534 F CYPRESS CY8C21434 CY8C21334 CY
11. 1 5 MHz VC2 93 75 kHz VC3 0 366 kHz 1503 Supply Current 1 6 MHz using SLIMO 1 2 2 mA Conditions are Vdd 3 3V mode 25 C CPU 3 MHz clock doubler disabled VC1 lt 375 kHz VC2 23 4 kHz VC3 0 091 kHz Ipp27 Supply Current IMO 6 MHz using SLIMO 1 1 1 5 mA Conditions are Vdd 2 55V mode 25 C CPU 3 MHz clock doubler disabled VC1 375 kHz VC2 23 4 kHz VC3 0 091 kHz Document Number 38 12025 Rev O Page 19 of 45 Feedback m CY8C21634 CY8C21534 CY8C21434 CY8C21334 CY8C21234 PERFORM Table 14 DC Chip Level Specifications continued Symbol Description Min Typ Max Units Notes 5 27 Sleep Mode Current with Sleep 2 6 4 uA Vdd 2 55 0 C lt Ty lt 40 C Timer WDT and internal slow oscillator active Mid temperature range Isp Sleep Mode Current with POR LVD Sleep 2 8 5 3 3V 40 C lt TA lt 85 C Timer WDT and internal slow oscillator active Reference Voltage Bandgap 1 28 1 30 1 32 V Trimmed for appropriate Vdd 3 0V to 5 25V VREF27 Reference Voltage Bandgap 1 16 1 30 1 33 V Trimmed for appropriate Vdd Vdd lt 2 4V to 3 0V AGND Analog Ground VREF V 0 003 0 003 DC General Purpose IO Specifications The following tables list the guaranteed maximum and minimum specifications
12. 5 PACKAGE CODE PART DESCRIPTION LF32 STANDARD LY32 PB FREE 51 85188 B Document Number 38 12025 Rev O Page 35 of 45 Feedback Document Number 38 12025 Rev O We CY8C21634 CY8C21534 CYPRESS CY8C21434 CY8C21334 CY8C21234 PERFORM Figure 24 32 Pin 5x5 mm 0 60 QFN TOP VIEW SIDE VIEW BOTTOM VIEW NOTES HATCH AREA IS EXPOSED METAL JEDEC MO 220 DIMENSIONS IN mm MIN MAX E PAD X Y for this product is 3 53 mm 3 53 mm 0 11 mm UNIT PACKAGE WEIGHT 0 0354 Grams PACKAGE CODE PART DESCRIPTION LJ328 STANDARD 328 PB FREE 001 06392 Figure 25 32 Pin 5 X 5 X 0 4MM SAWN 1 85 X 2 85 EPAD m 5 00040 10 5 000 0 10 0 10 MIN 0 15 MAX YIS i VIEW w 7 BARE COOPER NOTES 4 0 0635 1 HATCH AREA IS SOLDERABLE EXPOSED PAD 2 ALL DIMENSIONS ARE IN MILLIMETERS 3 REFERENCE JEDEC MO 220 4 MAXIMUM ALLOWABLE METAL IS 0 0508 5 PACKAGE WEIGHT 0 029 grams 001 44368 A 0 127 Page 36 of 45 Feedback CY8C21634 CY8C21534 CYPRESS CY8C21434 CY8C21334 CY8C21234 Figure 26 32 Sawn Package 5 000 0 100 57036100 NOTES 1 B HATCH AREA 18 SOLDERABLE 2 ON REF 2 MO
13. PWM pulse width modulator SC Switched capacitor SLIMO slow IMO SMP switch mode pump SRAM static random access memory Document Number 38 12025 Rev O CY8C21634 CY8C21534 CY8C21434 CY8C21334 CY8C21234 Units of Measure A units of measure table is located in the Electrical Specifications section Table 2 on page 7 lists all the abbreviations used to measure the PSoC devices Numeric Naming Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase h for example 14h or 3Ah Hexadecimal numbers may also be represented by 0 prefix the C coding convention Binary numbers have an appended lowercase b for example 010101000 or 01000011b Numbers not indicated by h b or are decimal Page 7 of 45 Feedback 8 21634 8 21534 CYPRESS CY8C21434 CY8C21334 CY8C21234 PERFORM Pin Information The CY8C21x34 PSoC device is available in a variety of packages which are listed in the following tables Every port pin labeled with a P is capable of Digital IO and connection to the common analog bus However Vss Vdd SMP and XRES are not capable of Digital 10 16 Pin Part Pinout Figure 3 CY8C21234 16 Pin PSoC Device A IM PO 4 Vad AIM P05 2 POB A I M 3 ALI M AIM POM mj 4 PO 2 AI M SMP 5 POD A I M Vss 6 MI2CSCL P1
14. SSOP CY8C21334 24PVXIT 8K 512 40 85 4 4 16 1677 o Yes Tape and Reel 28 Pin 210 Mil SSOP CY8C21534 24PVXI 8K 512 40 85 4 4 24 2427 0 Yes 28 Pin 210 Mil SSOP CY8C21534 24PVXIT 8K 512 40 C to 85 C 4 4 24 2427 Yes Tape and Reel 32 Pip 5 5 0 93 CY8C21434 24LFXI 8K 512 40 to 85 4 4 28 2827 0 Yes QFN 32 Pin 5 5 0 93 CY8C21434 24LFXIT 8 512 40 85 4 4 28 2827 o Yes b Tape and Reel CY8C21434 24LKXI 8K 512 40 to 85 C 4 4 28 28771 o Yes 32 Pin 5 5 mm 0 60 MAX CY8C21434 24LKXIT 8K 512 40 to 85 4 4 28 282 0 Yes Ber in 5 5 mm 0 93 MAX QFN CY8C21634 24LFXI 8K 512 Yes 40 to 85 C 4 4 26 26271 0 Yes 32 Pin 5 5 mm 0 93 CY8C21634 24LFXIT 8K 512 Yes 40 to 85 C 4 4 26 26271 0 Yes 28 32 Pin 5 5 mm 1 00 CY8C21434 24LTXI 8K 512 40 C to 85 C 4 4 28 2827 o Yes SAWN QFN 32 Pin 5x5 mm 1 00 MAX CY8C21434 24LTXIT 8K 512 40 C to 85 C 4 4 28 28771 o Yes SAWN I Tape and Reel 32 Pin 5x5 mm 0 40 MAX CY8C21434 24LCXI 8K 512 40 to 85 C 4 4 28 28 0 Yes SAWN QFNP I 32 Pin 5 5 mm 0 40 MAX CY8C21434 24LCXIT 8K 512 40
15. devices The PSoC Designer IDE runs on Windows XP or Windows Vista This system provides design database management by project an integrated debugger with In Circuit Emulator in system programming support and built in support for third party assemblers and C compilers PSoC Designer also supports C language compilers developed specifically for the devices in the PSoC family PSoC Designer Software Subsystems System Level View A drag and drop visual embedded system design environment based on PSoC Express In the system level view you create a model of your system inputs outputs and communication inter faces You define when and how an output device changes state based upon any or all other system devices Based upon the design PSoC Designer automatically selects one or more PSoC Mixed Signal Controllers that match your system requirements PSoC Designer generates all embedded code then compiles and links it into a programming file for a specific PSoC device Chip Level View The chip level view is a more traditional Integrated Development Environment IDE based on PSoC Designer 4 4 Choose a base device to work with and then select different onboard analog and digital components called user modules that use the PSoC blocks Examples of user modules are ADCs DACs Amplifiers and Filters Configure the user modules for your chosen application and connect them to each other and to the proper pins Then generate your project
16. 1 IO M PO 1 Analog column mux input integrating input 2 IO M P2 7 3 IO M 2 5 4 IO M P2 3 5 IO M P2 1 6 IO M P3 3 In CY8C21434 part 6 Power SMP Switch Mode Pump SMP connection to required external components in CY8C21634 part 4 IO M P3 1 In CY8C21434 part 7 Power Vss Ground connection in CY8C21634 part 8 IO M 1 7 I2C Serial Clock SCL 9 1 5 I2C Serial Data SDA 10 P1 3 11 IO M P1 1 12 Serial Clock SCL ISSP scLKEI 12 Power Vss Ground connection 13 P1 0 I2C Serial Data SDA ISSP SDATAPJ 14 IO M P1 2 15 IO M P1 4 Optional External Clock Input EXTCLK 16 IO M P1 6 17 Input XRES Active high external reset with internal pull down 18 IO M P3 0 19 IO M P3 2 20 IO M P2 0 21 IO M P2 2 22 IO M P2 4 23 2 6 24 IO lI M P0 0 Analog column mux input 25 M PO 2 Analog column mux input 26 IO lI M PO 4 Analog column mux input 27 IO I M PO 6 Analog column mux input 28 Power Vdd Supply voltage 29 IO I M PO 7 Analog column mux input 30 IO I M P0 5 Analog column mux input 31 IO I M PO 3 Analog column mux input integrating input 32 Power Vss Ground connection LEGEND Analog Input Output and Analog Mux Input Note 4 The center pad on the QFN package must be connected to ground Vss for best mechanical thermal and electrical performance If not connected to ground it must be electrically floated and
17. 11 5 12 12 706 778 MHz Trimmed for 2 7V operation using factory trim values See Figure 14 on page 18 SLIMO mode 1 Internal Main Oscillator Frequency for 6 MHz 5 75 6 6 35116 7778 MHz Trimmed for 2 7V operation using factory trim values See Figure 14 on page 18 SLIMO mode 1 Fopu1 CPU Frequency 2 7V Nominal 0 093 3 3 15116 MHz 24 MHz only for SLIMO mode 0 27 Digital PSoC Block Frequency 2 7V Nominal 0 12 12 516 17 18 MHz Refertothe AC Digital Block Specifications F32K1 Internal Low Speed Oscillator Frequency 8 32 96 kHz Jitter32k 32 kHz RMS Period Jitter 150 200 ns Jitter32k 32 kHz Peak to Peak Period Jitter 1400 TxRsT External Reset Pulse Width 10 us Maximum frequency of signal on row input or 12 3 MHz row output TRAMP Supply Ramp Time 0 us Figure 16 24 MHz Period Jitter IMO Timing Diagram Jitter24M1 lt Foam Figure 17 32 kHz Period Jitter ILO Timing Diagram Jitter32k gt lt Fa2K4 Notes 16 2 4V lt Vdd lt 3 0V 17 Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range 18 Application Note AN2012 Adjusting PSoC Microcontroller Trims for Dual Operation for information on maximum frequency for user modules Page 27 of 45 Document Number 38 12025 Feedback PERFORM AC General Purpose IO Specifications The following tables list the guara
18. 4 51 IO P2 6 52 IO 0 Analog column mux input 53 PO 2 Analog column mux input and column output 54 IO PO 4 Analog column mux input and column output 55 IO PO 6 Analog column mux input 56 Power Vdd Supply voltage LEGEND A Analog Input Output and OCD Debug Document Number 38 12025 Rev O Page 14 of 45 Feedback Z 8 21634 8 21534 CYPRESS CY8C21434 8 21334 CY8C21234 PERFORM Register Reference This chapter lists the registers of the CY8C21x34 PSoC device For detailed register information refer the PSoC Programmable System on Chip Technical Reference Manual Register Conventions The register conventions specific to this section are listed in Table 8 Table 8 Register Conventions Convention Description Read register or bit s Write register or bit s Logical register or bit s Clearable register or bit s Or Access is specific Register Mapping Tables The PSoC device has a total register address space of 512 bytes The register space is referred to as IO space and is divided into two banks The XOI bit in the Flag register CPU F determines which bank the user is currently in When the XOI bit is set the user is in Bank 1 Note In the following register mapping tables blank fields are Reserved and must not be accessed Table 9 Register Map 0 Table User Space
19. 40 245 25171 v VM 2 0 001b 2 85 2 92 2998 v Vivp2 VM 2 0 010b 2 95 3 02 3 09 V Vivp3 VM 2 0 lt 011b 3 06 3 13 3 20 V Vivp4 VM 2 0 100b 4 37 4 48 4 55 V Vivp5 VM 2 0 101b 4 50 4 64 4 75 V Vivpe VM 2 0 110b 4 62 4 73 4 83 V Vivp7 VM 2 0 111b 4 71 4 81 4 95 V Vdd Value for PUMP Trip Vpympo VM 2 0 000b 2 45 2 55 2629 v Vpeuup4 VM 2 0 001b 2 96 3 02 3 09 V Vpump2_ VM 2 0 010b 3 03 3 10 3 16 V VPUMP3 VMI2 0 011b 3 18 325 3320 v Vpump4 VM 2 0 100b 4 54 4 64 4 74 V Vpumps VM 2 0 101b 4 62 4 73 4 83 V Vpumpe VM 2 0 110b 4 71 4 82 4 92 V Vpump7 VM 2 0 111b 4 89 5 00 5 12 V Notes 7 Always greater than 50 mV above PORLEV 00 for falling supply 8 Always greater than 50 mV above PORLEV lt 01 for falling supply 9 Always greater than 50 mV above 10 Always greater than 50 mV above Document Number 38 12025 Rev O Page 24 of 45 Feedback m CY8C21634 CY8C21534 CY8C21434 CY8C21334 CY8C21234 PERFORM DC Programming Specifications Table 24 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges 4 75V to 5 25V and 40 lt TA lt 85 C 3 0V to 3 6V and 40 C lt TA x 85 C or 2 4V to 3 0V and 40 C x Ty x 85 C respectively Typical parameters apply to 5V 3 3V or 2 7V at 25 C and are for design guidance only Table 24 DC Programming Specificatio
20. 6 8 High Output Level Vdd 2 5 mA 6 25 Typ Vdd 2 4 0 4 to 3 0V 16 mA maximum 50 mA Typ combined budget VoL Low Output Level 0 75 10 mA Vdd 24 to 3 0V 90 mA maximum combined IOL budget Input Low Level 0 75 V 2 4 to 3 0 Document Number 38 12025 Rev O Page 20 of 45 Feedback m CY8C21634 CY8C21534 2 ypnrcs CY8C21434 CY8C21334 CY8C21234 PERFORM Table 16 2 7V DC GPIO Specifications continued Symbol Description Min Typ Max Units Notes Input High Level 2 0 V Vdd 2 4 to 3 0 Vu Input Hysteresis 90 mV liL Input Leakage Absolute Value 1 nA Gross tested to 1 uA Capacitive Load on Pins as Input 3 5 10 pF and dependent Temp 25 C Capacitive Load on Pins as Output 3 5 10 pF and dependent Temp 25 C DC Operational Amplifier Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges 4 75V to 5 25V and 40 lt TA x 85 C 3 0V to 3 6V and 40 lt Ty x 85 C or 2 4V to 3 0V and 40 C lt TA x 85 C respectively Typical parameters apply to 5V 3 3V or 2 7V at 25 C and are for design guidance only Table 17 5V DC Operational Amplifier Specifications Symbol Description Min Typ Max Units Notes
21. A LM PO 7 i 20 PO 5 2 H 6 M A I M 3 8 B A LM PO 1 4 B 2 AI M Vss 5 16 PO 0 AI M MI2C 6 15 XRES MI2C SDA P1 b 7 14 P P1 6 M MP1 3 8 13 P 2 SCL P1 1 9 12 Vss CJ 10 11 P PI 0 I2C SDAM Table 4 Pin Definitions CY8C21334 20 Pin SSOP 3 a Pin No N D in No Digital Analog ame escription 1 M PO 7 Analog column mux input 2 M PO 5 Analog column mux input 3 IO I M PO 3 Analog column mux input integrating input 4 IO I M PO 1 Analog column mux input integrating input 5 Power Vss Ground connection 6 P1 7 I2C Serial Clock SCL 7 IO M P1 5 I2C Serial Data SDA 8 IO M P1 3 9 IO M P1 1 12 Serial Clock SCL ISSP SCLKBT 10 Power Vss Ground connection 11 IO M P1 0 2 Serial Data SDA ISSP SDATABI 12 IO M 1 2 13 IO M P1 4 Optional External Clock Input EXTCLK 14 IO M P1 6 15 Input XRES high external reset with internal pull down 16 IO I M P0 0 Analog column mux input 17 IO lI M PO 2 Analog column mux input 18 IO LM PO 4 Analog column mux input 19 IO M PO 6 Analog column mux input 20 Power Vdd Supply voltage LEGEND Analog Input Output and M Analog Input Document Number 38 12025 Rev O Page 9 of 45 Feedback CY8C21634 CY8C21534 F CYPRESS CY8C21434 CY8C21334 CY8C212
22. C W Document Number 38 12025 Rev O Page 38 of 45 Feedback Solder Reflow Peak Temperature Following is the minimum solder reflow peak temperature to achieve good solderability Table 41 Solder Reflow Peak Temperature CY8C21634 CY8C21534 CY8C21434 CY8C21334 CY8C21234 Minimum Peak Temperature Maximum Peak Temperature Package 16 SOIC 2409C 2609C 20 SSOP 2409C 2609 28 SSOP 2409 2609 32 QFN 240 2609 Notes 22 Tj Power x Oja 23 To achieve the thermal impedance specified for the QFN package the center thermal pad must be soldered to the PCB ground plane 24 Higher temperatures may be required based on the solder melting point Typical temperatures for solder are 220 5 C with Sn Pb or 245 5 with Sn Ag Cu paste Refer to the solder manufacturer specifications Document Number 38 12025 Rev O Page 39 of 45 Feedback PERFORM Development Tool Selection This section presents the development tools available for all current PSoC device families including the CY8C21x34 family Software PSoC Designer At the core of the PSoC development software suite is PSoC Designer Used by thousands of PSoC developers this robust software has been facilitating PSoC designs for half a decade PSoC Designer is available free of charge at http www cypress com under DESIGN RESOURCES gt gt Software and Drivers PSoC Programmer
23. Clock 4 0 0 6 us Tsustaizc Set up Time for a Repeated START 4 7 0 6 us Condition THDDATI2C Data Hold Time 0 0 us Data Set up Time 250 1001211 ns Set up Time for STOP Condition 4 0 0 6 us TBurI2C Bus Free Time Between a STOP and START 4 7 1 3 us Condition TsPi2c Pulse Width of spikes are suppressed by the 0 50 ns input filter Note 21 A Fast Mode I2C bus device may be used in a Standard Mode I2C bus system but the requirement tsu par gt 250 ns must then be met This is automatically the case if the device does not stretch the LOW period of the SCL signal If such device does stretch the LOW period of the SCL signal it must output the next data bit to the SDA tsu par 1000 250 1250 ns according to the Standard Mode I2C bus specification before the SCL line is released Document Number 38 12025 Rev O Page 32 of 45 Feedback 8 21634 8 21534 CY8C21434 8 21334 CY8C21234 Table 39 2 7V AC Characteristics of the SDA and SCL Pins Fast Mode not Supported UE Standard Mode Fast Mode Symbol Description Min Max Min Max Units FscLI2C SCL Clock Frequency 0 100 _ _ kHz Tupstaizc_ Hold Time repeated START Condition 4 0 us After this period the first clock pulse is generated TLowlc LOW Period of the SCL Clock 4 7 us HIGH Period
24. Switched Capacitor blocks The CY8C21x34 devices provide limited functionality Type E analog blocks Each column contains one CT Type E block and one SC Type E block Refer to the PSoC Programmable System on Chip Technical Reference Manual for detailed information on the CY8C21x34 s Type E analog blocks Figure 2 Analog System Block Diagram Document Number 38 12025 Rev O CY8C21634 CY8C21534 CY8C21434 CY8C21334 CY8C21234 The Analog Multiplexer System The Analog Mux Bus can connect to every GPIO pin Pins may be connected to the bus individually or in any combination The bus also connects to the analog system for analysis with comparators and analog to digital converters An additional 8 1 analog input multiplexer provides a second path to bring Port 0 pins to the analog array Switch control logic enables selected pins to precharge continuously under hardware control This enables capacitive measurement for applications such as touch sensing Other multiplexer applications include m Track pad finger sensing m Chip wide mux that allows analog input from any IO pin m Crosspoint connection between any IO pin combinations When designing capacitive sensing applications refer to the signal to noise system level requirement found in Application Note AN2403 the Cypress web site at http www cypress com Additional System Resources System Resources some of which are listed in the previous sections p
25. This prepopulates your project with APIs and libraries that you can use to program your application The device editor also supports easy development of multiple configurations dynamic reconfiguration Dynamic configuration allows for changing configurations at run time Hybrid Designs You can begin in the system level view allow it to choose and configure your user modules routing and generate code then switch to the chip level view to gain complete control over on chip resources All views of the project share a common code editor builder and common debug emulation and programming tools Document Number 38 12025 Rev O CY8C21634 CY8C21534 CY8C21434 CY8C21334 CY8C21234 Code Generation Tools PSoC Designer supports multiple third party C compilers and assemblers The code generation tools work seamlessly within the PSoC Designer interface and have been tested with a full range of debugging tools The choice is yours Assemblers The assemblers allow assembly code to merge seamlessly with C code Link libraries automatically use absolute addressing or are compiled in relative mode and linked with other software modules to get absolute addressing C Language Compilers C language compilers are available that support the PSoC family of devices The products allow you to create complete C programs for the PSoC family devices The optimizing C compilers provide all the features of C tailored to the PSoC archi
26. Trim Options A 5 25 5 25 4 75 i 4 75 5 3 3 60 3 00 3 00 240 240 ewe gt T T T T gt 93kHz 3 12 MHz 24 93 kHz 6 MHz 12MHz 24 CPUFrequency IMOFrequency Table 11 lists the units of measure that are used in this section Table 11 Units of Measure Symbol Unit of Measure Symbol Unit of Measure C degree Celsius uW microwatts dB decibels mA milli ampere fF femto farad ms milli second Hz hertz mV milli volts KB 1024 bytes nA nanoampere Kbit 1024 bits ns nanosecond kHz kilohertz nV nanovolts kQ kilohm W ohm MHz megahertz pA picoampere MO megaohm pF picofarad microampere pp peak to peak uF microfarad ppm parts per million uH microhenry ps picosecond us microsecond sps samples per second uV microvolts S sigma one standard deviation uVrms microvolts root mean square V volts Document Number 38 12025 Rev O Page 18 of 45 Feedback CY8C21634 CY8C21534 CY8C21434 CY8C21334 CY8C21234 PERFORM Absolute Maximum Ratings Table 12 Absolute Maximum Ratings Symbol Description Min Typ Max Units Notes TsrG Storage Temperature 55 25 100 C Higher storage temperatures reduce data retention time Recom mended storage temperature is 25 C 25 C Extended duration storage temperatures above 65 C degrade rel
27. argument before writing Refer to the Flash APIs Application Note AN2015 at http www cypress com under Application Notes for more information Document Number 38 12025 Rev O Page 25 of 45 Feedback CY8C21634 CY8C21534 CY8C21434 CY8C21334 CY8C21234 PERFORM AC Electrical Characteristics AC Chip Level Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges 4 75V to 5 25V and 40 C x T4 lt 85 C 3 0V to 3 6V and 40 C lt T lt 85 or 2 4V to 3 0V and 40 C lt T4 lt 85 C respectively Typical parameters apply to 5V 3 3V or 2 7V at 25 C and are for design guidance only Table 25 5V and 3 3V AC Chip Level Specifications Symbol Description Min Typ Max Units Notes 24 Internal Main Oscillator Frequency for 24 MHz 23 4 24 24 62 75 VI MHz Trimmed for 5V or 3 3V operation using factory trim values See Figure 14 on page 18 SLIMO mode 0 Internal Main Oscillator Frequency for 6 MHz 5 75 6 6 35112 13 14 MHz Trimmed for 5V or 3 3V operation using factory trim values See Figure 14 on 18 SLIMO mode 1 Fopu1 CPU Frequency 5V Nominal 0 93 24 24 6112 73 MHz 24 MHz only for SLIMO mode 0 Fopy2 CPU Frequency 3 3V Nominal 0 93 12 12 313747 MHz 5 Digital PSoC Block Frequency 5V N
28. m Mini Eval Programming Board Document Number 38 12025 Rev O CY8C21634 CY8C21534 CY8C21434 CY8C21334 CY8C21234 m 110 240V Power Supply Euro Plug Adapter m iMAGEcraft C Compiler Registration Required m ISSP Cable m USB 2 0 Cable and Blue Cat 5 Cable m 2 CY8C29466 24PXI 28 PDIP Chip Samples CY3210 ExpressDK PSoC Express Development Kit The CY3210 ExpressDK is for advanced prototyping and development with PSoC Express may be used with ICE Cube In Circuit Emulator It provides access to buses voltage reference switches upgradeable modules and more The kit includes m PSoC Express Software CD m Express Development Board m 4 Fan Modules m 2 Proto Modules m MiniProg In System Serial Programmer m MiniEval PCB Evaluation Board m Jumper Wire Kit m USB 2 0 Cable m Serial Cable DB9 m 110 240V Power Supply Euro Plug Adapter m 2 CY8C24423A 24PXI 28 PDIP Chip Samples m 2 CY8C27443 24PXI 28 PDIP Chip Samples m 2 CY8C29466 24PXI 28 PDIP Chip Samples Evaluation Tools All evaluation tools can be purchased from the Cypress Online Store CY3210 MiniProg1 The CY3210 MiniProg1 kit allows a user to program PSoC devices through the MiniProg1 programming unit The MiniProg is a small compact prototyping programmer that connects to the PC through a provided USB 2 0 cable The kit includes m MiniProg Programming Unit m MiniEval Socket Programming and Evaluation Board m 28 Pin CY8C29466 24PXI PDIP PS
29. not connected to any other signal Document Number 38 12025 Rev O Page 12 of 45 Feedback 8 21634 8 21534 CYPRESS CY8C21434 CY8C21334 CY8C21234 PERFORM 56 Pin Part Pinout The 56 pin SSOP part is for the CY8C21001 On Chip Debug OCD PSoC device Note This part is only used for in circuit debugging It is NOT available for production Figure 12 CY8C21001 56 Pin PSoC Device Vss 1 Al PO 7 2 PO 6 Al PO S 3 PO 4 A Al PO 3 4 PO 2 Al Al PO 1 5 PO 0 Al P2 7 6 2 6 P2 5 7 2 4 P2 3 8 P2 2 P2 1 9 2 0 P3 2 NC P3 O OCDE CCLK OCDO HCLK SMP XRES Vss NC Vss NC P3 3 NC P3 1 NC NC NC NC NC I2C SCL P1 7 1 6 2 SDA 1 5 1 4 EXTCLK NC P1 2 1 3 1 0 12 SDA SDATA SCLK 12 SCL 1 1 Vss NC Table 7 Pin Definitions CY8C21001 56 Pin SSOP Type Pin No Digital D Analog Pin Name Description 1 Power Vss Ground connection 2 IO l PO 7 Analog column mux input 3 IO 5 Analog column input and column output 4 IO 3 Analog column input and column output 5 IO PO 1 Analog column mux input 6 IO P2 7 7 IO P2 5 8 IO P2 3 Direct switched capacitor block input 9 IO 2 1 Direct switched capacitor block input 10 NC No connection 11 NC No connection 12 NC No connection 13 NC No connection 1
30. of the SCL Clock 4 0 us Tsustaizc Setup Time for a Repeated START 4 7 us Condition THDDATI2C Data Hold Time 0 us Tsuparoc Data Set up Time 250 ns Tsustoizc Set up Time for STOP Condition 4 0 us TaBuFI2C Bus Free Time Between a STOP and START 4 7 us Condition TsPi2c Pulse Width of spikes are suppressed by the ns input filter SDA SCL Figure 19 Definition for Timing for Fast Standard Mode on the Bus Tsu DATI2C Tupstaizc HDDAT2C Document Number 38 12025 Rev O TsusrAi2C Ds 1 1 1 I 1 I 1 1 I 1 1 I 1 I 1 I 1 I 1 4 HDSTAI2C Tsusroizc 1 1 1 1 1 1 1 I 1 I 1 4 la Taurizc Page 33 of 45 Feedback 8 21634 8 21534 CY8C21434 8 21334 CY8C21234 PERFORM Packaging Information This section shows the packaging specifications for the CY8C21x34 PSoC device with the thermal impedances for each package Important Note Emulation tools may require a larger area on the target PCB than the chip s footprint For a detailed description of the emulation tools dimensions refer to the document titled PSoC Emulator Pod Dimensions at http Awww cypress com design MR10161 Packaging Dimensions Figure 20 16 Pin 150 Mil SOIC
31. 0 8 MHz Flash Erase Time Block E 15 his Document Number 38 12025 Rev O Page 31 of 45 Feedback m CY8C21634 CY8C21534 2 VpnEsS CY8C21434 CY8C21334 CY8C21234 PERFORM Table 37 AC Programming Specifications continued Symbol Description Min Typ Max Units Notes TwRITE Flash Block Write Time 30 ms Data Out Delay from Falling Edge of SCLK 45 ns 3 6 Vdd Data Out Delay from Falling Edge of SCLK 50 ns 3 0 lt Vdd lt 3 6 TpscLk2 Data Out Delay from Falling Edge of SCLK 70 ns 2 4 x Vdd x 3 0 AC Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges 4 75V to 5 25V and 40 lt TA x 85 C 3 0V to 3 6V and 40 lt Ty x 85 C or 2 4V to 3 0V and 40 C lt TA x 85 C respectively Typical parameters apply to 5V 3 3V or 2 7V at 25 C and are for design guidance only Table 38 AC Characteristics of the IC SDA and SCL Pins for Vdd gt 3 0V Aen Standard Mode Fast Mode Symbol Description Min Max Min Max Units SCL Clock Frequency 0 100 0 400 kHz TupsrAaoc Hold Time repeated START Condition 4 0 0 6 us After this period the first clock pulse is generated LOW Period of the SCL Clock 4 7 1 3 us THIGHI2C HIGH Period of the SCL
32. 1 m 7 P1 2 M Vss 8 1 0 I2CSDA M Table 3 Pin Definitions CY8C21234 16 Pin SOIC Pin No Digital aa Name Description 1 PO 7 Analog column mux input 2 IO I P0 5 Analog column mux input 3 I PO 3 Analog column mux input integrating input 4 IO 1 M P0 1 Analog column mux input integrating input 5 Power SMP Switch Mode Pump SMP connection to required external components 6 Power Vss Ground connection 7 IO M P1 1 I2C Serial Clock SCL 155 5 8 Ground connection 9 IO M P1 0 I2C Serial Data SDA ISSP SDATABI 10 IO M P1 2 11 IO M P1 4 Optional External Clock Input EXTCLK 12 IO M PO 0 Analog column mux input 13 IO 1 P0 2 Analog column mux input 14 PO 4 Analog column mux input 15 IO M PO 6 Analog column mux input 16 Power Supply voltage LEGEND Analog Input Output and M Analog Input Note 3 These are the ISSP pins which are not High Z at POR Power On Reset See the PSoC Programmable System on Chip Technical Reference Manual for details Document Number 38 12025 Rev O Page 8 of 45 Feedback PERFORM 20 Pin Part Pinout CY8C21634 CY8C21534 CY8C21434 CY8C21334 CY8C21234 Figure 4 CY8C21334 20 Pin PSoC Device
33. 1 8 5 91 8 5 91 8 E 8 2 45 2 z 45 2 z 45 2 z 45 2 DBBOODRO 20 AMX_IN 60 RW AO INT_MSKO RW DBBOODR1 21 Ww AMUXCFG 61 RW A1 INT MSK1 E1 RW DBBOODR2 22 RW PWM CR 62 RW A2 INT VC E2 RC DBBOOCRO 23 63 RES WDT E3 Ww DBBO1DRO 24 64 4 4 DBBO1DR1 25 Ww 65 A5 E5 DBBO1DR2 26 RW CMP CR1 66 RW A6 DEC CRO E6 RW DBBO1CRO 27 67 7 1 E7 RW DCBO2DRO 28 ADCO CR 68 E8 DCBO2DR1 29 Ww ADC1 CR 69 A9 E9 DCBO02DR2 2A RW 6A AA EA DCBO2CRO 2B 6B AB EB DCBO3DRO 2C 6c RW AC EC DCBO3DR1 2D Ww TMP DR1 6D RW AD ED DCBO3DR2 2E RW TMP_DR2 6E RW AE EE DCBO3CRO 2F 6F RW AF EF 30 70 RDIORI BO RW FO 31 71 RDIOSYN B1 RW F1 32 ACEOOCR1 72 RW RDIOIS B2 RW F2 33 ACEO0CR2 73 RW RDIOLTO B3 RW F3 34 74 RDIOLT1 B4 RW F4 35 75 RDIOROO B5 RW F5 36 ACEO1CR1 76 RW RDIORO1 B6 RW F6 37 ACEO1CR2 77 RW B7 CPU F F7 RL 38 78 B8 F8 39 79 B9 F9 3A 3B 7B BB FB 3C 7C BC FC 3D 7D BD DAC_D FD RW 3E 7E BE CPU_SCR1 FE 3F 7F BF CPU SCRO FF Blank fields are Reserved and must not be accessed Access is bit specific Table 10 Register Map 1 Table Configuration Space f e f 158 s s S s s 2 lt 2 lt lt z lt lt z lt 00 RW 40 ASE10CRO 80 RW CO PRTODM1 01 RW 41 81 C1 PRTOICO 02 RW 42 82 C2 PRTOIC1 03 RW 43 83 C3 PRT1DMO 04 RW 44 ASE11CRO 84 RW C4 PRT1DM1 05 RW 45 85 C5 PRT1ICO 06 RW 46 86 C6 PRT1I
34. 21X34 CY3250 16SOIC FK CY8C21334 24PVXI 20 SSOP CY3250 21X34 CY3250 20SSOP FK CY8C21434 24LFXI 32 QFN CY3250 21X34QFN CY3250 32QFN FK CY8C21534 24PVXI 28 SSOP CY3250 21X34 CY3250 28SSOP FK CY8C21634 24LFXI 32 QFN CY3250 21X34QFN CY3250 32QFN FK Build a PSoC Emulator into Your Board For details on how to emulate your circuit before going to volume production using an on chip debug OCD non production PSoC device see Application Note AN2323 Debugging Build a PSoC Emulator into Your Board 25 Flex Pod kit includes a practice flex pod and a practice PCB in addition to two flex pods 26 Foot kit includes surface mount feet that can be soldered to the target PCB Document Number 38 12025 Rev O Page 41 of 45 Feedback Ordering Information CY8C21634 CY8C21534 CY8C21434 CY8C21334 CY8C21234 Ber n 5x5 mm 0 60 MAX QFN 28 Tape and Reel o o o o 2 on 9 58 5g 55 55 595 se 92 95 gt 5 8 85 gt 55 LL n m mS c 6 2 x lt lt lt o o 16 Pin 150 Mil SOIC CY8C21234 24SXI 8K 512 Yes 40 C to 85 4 4 12 1227 16 Pin 150 Mil SOIC 8 21234 245 8K 512 Yes 40 C 85 4 4 12 12777 o No Tape and Reel 20 Pin 210 Mil SSOP CY8C21334 24PVXI 8K 512 40 to 85 4 4 16 1627 o Yes 20 Pin 210 Mil
35. 220 PACKAGE WEIGHT 0 068g 4 DIMENSIONS ARE N MILLIMETERS 001 30999 A Figure 27 32 Pin Thin Sawn QFN Package 594919 0 02 239 3 500 015 DIA 0 20 PIN CORNER 0 550 0 05 32 25 1 6 55 609 550 9 52 3 500 Ox e 252 54 6 2 9 16 TOP VIEW BOTTOM VIEW SIDE VIEW NOTES 1 Ed HATCH AREA 15 SOLDERABLE EXPOSED PAD 2 BASED REF MO 245 3 PACKAGE WEIGHT 0 03880 4 DIMENSIONS ARE IN MILLIMETERS 001 42168 C Important Note For information on the preferred dimensions for mounting QFN packages see the following Application Note at http www amkor com products notes papers MLFAppNote pdf Document Number 38 12025 Rev O Page 37 of 45 Feedback CY8C21634 CY8C21534 CYPRESS CY8C21434 CY8C21334 CY8C21234 PERFORM Figure 28 56 Pin 300 Mil SSOP 020 p DIMENSIONS IN INCHES MIN MAX SEATING PLANE a y um 0 010 G um 0024 J 0 008 0 B 0 016 L 51 85062 0008 0 0135 Thermal Impedances Table 40 Thermal Impedances per Package Package Typical Oja ES Typical 16 SOIC 123 C W 55 C W 20 SSOP 117 C W 41 C W 28 SSOP 96 C W 39 C W 32 QFNI25I 5x5 mm 0 60 MAX 27 C W 15 C W 32 5x5 mm 0 93 22 C W 12
36. 3 0V 10 90 Figure 18 GPIO Timing Diagram Output Voltage 10 AC Operational Amplifier Specifications Table 29 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges 4 75V to 5 25V and 40 C lt TA lt 85 C 3 0V to 3 6V and 40 C lt TA lt 85 C or 2 4V to 3 0V and 40 x Ty lt 85 C respectively Typical parameters apply to 5V 3 3V or 2 7V at 25 C and are for design guidance only Table 29 AC Operational Amplifier Specifications ES TFallS TFallF Symbol Description Min Typ Max Units Notes Comparator Mode Response Time 50 mV 100 ns Vdd gt 3 0V Overdrive 200 ns 2 4V lt Vcc lt 3 0V AC Low Power Comparator Specifications Table 30 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges 4 75V to 5 25V and 40 C lt TA lt 85 C 3 0V to 3 6V and 40 C lt TA x 85 C or 2 4V to 3 0V and 40 C x Ty x 85 C respectively Typical parameters apply to 5V at 25 C and are for design guidance only Table 30 AC Low Power Comparator Specifications Symbol Description Min Typ Max Units Notes Ta PC LPC response time Document Number 38 12025 Rev O 50 us gt 50 mV overdrive comparator reference set within Veer pc Page 28 of 45 Feedback PERFORM AC Analog Mux Bus Specifications Table 31 lists
37. 34 28 Pin Part Pinout Figure 5 CY8C21534 28 Pin PSoC Device A M P0 E LM PO S 2 PO 6 A 1 M LM PO 3 3 A M A M 4 POP AI M 2 7 5 PO 0 A 1 M MP2 5 6 2 6 2 3 7 2 41 M P2 1 8 221 Vss P2 0 M MI2C SCL P1 7 XRES SDA P1 5 P1 6 M MP1 3 P1 4 EXTCLKM MI2C SCL P1 1 P1 2 M Vss P1 0 I2C SDA M Table 5 Pin Definitions CY8C21534 28 Pin SSOP Pin No Digital Analog Name Description 1 IO PO 7 Analog column mux input 2 IO LM PO 5 Analog column mux input and column output 3 IO M PO 3 Analog column mux input and column output integrating input 4 IO 1 M PO 1 Analog column mux input integrating input 5 IO M P2 7 6 IO M P2 5 7 IO M P2 3 Direct switched capacitor block input 8 IO 1 P2 1 Direct switched capacitor block input 9 Power Vss Ground connection 10 IO M P1 7 12 Serial Clock SCL 11 IO M P1 5 12 Serial Data SDA 12 IO M P1 3 13 IO M P1 1 I2C Serial Clock SCL 155 5 14 Ground connection 15 IO M P1 0 I2C Serial Data SDA ISSP SDATABI 16 IO M P1 2 17 IO M P1 4 Optional External Clock Input EXTCLK 18 IO M P1 6 19 Input XRES Active high external reset with internal pull down 20 IO I M P2 0 Direct switched capacitor block input 21 IO 1 M P2 2 Direct switche
38. 4 OCD OCDE OCD even data IO 15 OCD OCDO OCD odd data output 16 Power SMP Switch Mode Pump SMP connection to required external components 17 Power Vss Ground connection 18 Power Vss Ground connection Document Number 38 12025 Rev O Page 13 of 45 Feedback CY8C21634 CY8C21534 CYPRESS CY8C21434 CY8C21334 CY8C21234 PERFORM Table 7 Pin Definitions CY8C21001 56 Pin SSOP continued Pin No Analog Pin Name Description 19 IO P3 3 20 IO P3 1 21 NC No connection 22 NC No connection 23 IO 1 7 I2C Serial Clock SCL 24 IO P1 5 12 Serial Data SDA 25 NC No connection 26 IO P1 3 1 27 IO P1 1 Crystal Input XTALin I2C Serial Clock SCL 55 5 28 Vss Ground connection 29 NC No connection 30 NC No connection 31 IO P1 0 Crystal Output XTALout 12 Serial Data SDA ISSP SDATABI 32 IO P1 2 VFMTEST 33 IO P1 4 Optional External Clock Input EXTCLK 34 IO P1 6 35 NC No connection 36 NC No connection 37 NC No connection 38 NC No connection 39 NC No connection 40 NC No connection 41 Input XRES Active high external reset with internal pull down 42 OCD HCLK OCD high speed clock output 43 OCD CCLK OCD CPU clock output 44 IO P3 0 45 IO P3 2 46 NC No connection 47 NC No connection 48 IO l P2 0 49 IO 2 2 50 IO P2
39. 5 and are for design guidance only Table 21 DC Switch Mode Pump SMP Specifications Symbol Description Min Typ Max Units Notes 5V Output Voltage from Pump 4 75 5 0 5 25 V Configuration of footnote l9 Average neglecting ripple SMP trip voltage is set to 5 0V 3 3V Output Voltage from Pump 3 00 3 25 3 60 V Configuration of footnote 6 Average neglecting ripple SMP trip voltage is setto 3 25V Vpumpa2v 2 6V Output Voltage from Pump 2 45 2 55 2 80 V Configuration of footnote 6 Average neglecting ripple SMP trip voltage is setto 2 55V Available Output Current Configuration of footnote 6 VPUMP5V Vear 1 8V 5 0V 5 mA SMP trip voltage is to 5 0V Veat 1 5V Vpump 3 25V 8 mA SMP trip voltage is set to 3 25V Veat 1 3V Vpump 2 55V 8 mA SMP trip voltage is set to 2 55V Veatsv Voltage Range from Battery 1 8 5 0 V Configuration of footnote SMP trip voltage is set to 5 0V Input Voltage Range from Battery 1 0 3 3 V Configuration of footnote 6 SMP trip voltage is setto 3 25V Vpgaroy Input Voltage Range from Battery 1 0 2 8 V Configuration of footnote 6 SMP trip voltage is setto 2 55V VpgarsrA Minimum Input Voltage from Battery to Start 1 2 V Configuration of footnote 6l RT Pump 0 C lt TA lt 100 1 25V at TA 409 Document Number 38 12025 Rev O P
40. 8C21234 PERFORM Table 33 2 7V AC Digital Block Specifications Function Description Min Typ Max Units Notes All Maximum Block Clocking Frequency 12 7 MHz 2 4 lt Vdd lt 3 0V Functions Timer Capture Pulse Width 1001201 ns Maximum Frequency With or Without Capture 12 7 MHz Counter Enable Pulse Width 100 ns Maximum Frequency No Enable Input 12 7 MHz Maximum Frequency Enable Input 12 7 MHz Dead Band Kill Pulse Width Asynchronous Restart Mode 20 ns Synchronous Restart Mode 100 ns Disable Mode 100 ns Maximum Frequency 12 7 MHz CRCPRS Input Clock Frequency 12 7 MHz PRS Mode CRCPRS Input Clock Frequency 12 7 MHz CRC Mode SPIM Maximum Input Clock Frequency 6 35 MHz Maximum data rate at 3 17 MHz due to 2 x over clocking SPIS Maximum Input Clock Frequency 4 1 MHz Width of SS_ Negated Between Transmissions 100 ns Transmitter Maximum Input Clock Frequency 12 7 MHz Maximum data rate at 1 59 MHz due to 8 x over clocking Receiver Maximum Input Clock Frequency 12 7 MHz Maximum data rate at 1 59 MHz due to 8 x over clocking AC External Clock Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges 4 75V to 5 25V and 40 C x TA lt 85 C or 3 0V to 3 6V and 40 C l
41. C External Clock Specifications Symbol Description Min Typ Max Units Notes Foscext Frequency with CPU Clock divide by 1 0 093 3 08 MHz CPU frequency is 3 MHz at 2 7V With the CPU clock divider set to 1 the external clock must adhere to the maximum frequency and duty cycle requirements Foscext Frequency with CPU Clock divide by 2 or 0 186 6 35 MHz Ifthe frequency of the external clock greater is greater than 3 MHz the CPU clock divider must be set to 2 or greater In this case the CPU clock divider ensures that the fifty percent duty cycle requirement is met High Period with CPU Clock divide by 1 160 5300 ns Low Period with CPU Clock divide by 1 160 ns Power Up IMO to Switch 150 us AC Programming Specifications Table 37 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges 4 75V to 5 25V and 40 C lt TA lt 85 C or 3 0V to 3 6V and 40 C lt TA x 85 C respectively Typical parameters apply to 5V 3 3V or 2 7V at 25 C and are for design guidance only Table 37 AC Programming Specifications Symbol Description Min Typ Max Units Notes TRSCLK Rise Time of SCLK 1 20 ns Fall Time of SCLK 1 20 ns lt Data Set up Time to Falling Edge of SCLK 40 ns Data Hold Time from Falling Edge of SCLK 40 E ns Frequency of SCLK
42. C1 07 RW 47 87 C7 PRT2DMO 08 RW 48 88 C8 PRT2DM1 09 RW 49 89 C9 PRT2ICO 0A RW 4A 8A CA PRT2IC1 0B RW 4B 8B CB RW 4C 8c 1 00 RW 4D 8D CD PRT3ICO RW 4E 8E CE OF RW 4F 8F 10 50 90 GDI DO RW 11 51 91 GDI E IN D1 RW 12 52 92 GDI O OU D2 RW 13 53 93 GDI E OU D3 RW 14 54 94 04 Blank fields are Reserved and must not be accessed Document Number 38 12025 Rev O Access is bit specific Page 16 of 45 Feedback Table 10 Register Map 1 Table Configuration Space continued CY8C21634 CY8C21534 CY8C21434 CY8C21334 CY8C21234 o _ 5 2 lt 2 lt 2 5 2 o 3 j eee lt lt lt lt 15 55 95 05 16 56 96 06 17 57 97 07 18 58 98 MUX CRO D8 RW 19 59 99 MUX CR1 D9 RW 1A 5A 9A MUX CR2 DA RW 1B 5B 9B MUX CR3 DB RW 1C 5C 9c DC 1D 5D 9D OSC GO EN DD RW 1E 5E 9E OSC CR4 DE RW 1F 5F 9F OSC CR3 DF RW DBBOOFN 20 RW CLK CRO 60 RW OSC CRO EO RW DBBOOIN 21 RW CLK CR1 61 RW A1 OSC CR1 E1 RW DBBOOOU 22 RW ABF CRO 62 RW A2 OSC CR2 E2 RW 23 AMD CRO 63 RW A3 VLT CR E3 RW DBBO1FN 24 RW CMP_GO_EN 64 RW A4 VLT_CMP E4 R DBBO1IN 25 RW 65 A5 ADCO TR E5 RW DBB010U 26 RW AMD CR1 66 R
43. Flexible enough to be used on the bench in development yet suitable for factory programming PSoC Programmer works either as a standalone programming application or operates directly from PSoC Designer or PSoC Express PSoC Programmer software is compatible with both PSoC ICE Cube In Circuit Emulator and PSoC MiniProg PSoC programmer is available free ofcharge at http www cypress com psocpro grammer C Compilers PSoC Designer comes with a free HI TECH C Lite C compiler The HI TECH C Lite compiler is free supports all PSoC devices integrates fully with PSoC Designer and PSoC Express and runs on Windows versions up to 32 bit Vista Compilers with additional features are available at additional cost from their manufactures m HI TECH C PRO for the PSoC is available from http www htsoft com m ImageCraft Cypress Edition Compiler is available from http www imagecraft com Development Kits All development kits can be purchased from the Cypress Online Store CY3215 DK Basic Development Kit The CY3215 DK is for prototyping and development with PSoC Designer This kit supports in circuit emulation and the software interface allows users to run halt and single step the processor and view the content of specific memory locations Advance emulation features also supported through PSoC Designer The kit includes m PSoC Designer Software CD m ICE Cube In Circuit Emulator m ICE Flex Pod for CY8C29x66 Family m Cat 5 Adapter
44. O THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Cypress reserves the right to make changes without further notice to the materials described herein Cypress does not assume any liability arising out of the application or use of any product or circuit described herein Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress product in a life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Use may be limited by and subject to the applicable Cypress software license agreement Document Number 38 12025 Rev O Revised April 06 2009 Page 45 of 45 PSoC Designer and Programmable System on Chip are trademarks and PSoC6 is a registered trademark of Cypress Semiconductor Corp All other trademarks or registered trademarks referenced herein are property of the respective corporations Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system provided that the system conforms to the I2C Standard Specification as defined by Philips All products and company names mentioned in this document may be the tr
45. SMP that generates normal operating voltages off a single battery cell m Various system resets supported by the M8C The Digital System consists of an array of digital PSoC blocks that may be configured into any number of digital peripherals The digital blocks are connected to the GPIO through a series of global buses that can route any signal to any pin freeing designs from the constraints of a fixed peripheral controller The Analog System consists of four analog PSoC blocks supporting comparators and analog to digital conversion up to 8 bits in precision Document Number 38 12025 Rev O CY8C21634 CY8C21534 CY8C21434 CY8C21334 CY8C21234 The Digital System The Digital System consists of 4 digital PSoC blocks Each block is an 8 bit resource that is used alone or combined with other blocks to form 8 16 24 and 32 bit peripherals which are called user module references Digital peripheral configurations include the following m PWMs 8 to 32 bit m PWMs with Dead band 8 to 32 bit m Counters 8 to 32 bit m Timers 8 to 32 bit m UART 8 bit with selectable parity m SPI master and slave m 2C slave and multi master m Cyclical Redundancy Checker Generator 8 to 32 bit m IrDA m Pseudo Random Sequence Generators 8 to 32 bit The digital blocks are connected to any GPIO through a series of global buses that can route any signal to any pin The buses also allow for signal multiplexing and for performing lo
46. Temp table Add 32 MLF E PAD dimensions Add ThetaJC to Thermal Impedance table Fix 20 pin package order number Add CY logo Update CY copyright G 352736 See ECN Add new color and logo Add URL to preferred dimensions for mounting MLF packages Update Transmitter and Receiver AC Digital Block Electrical Specifications H 390152 See ECN Clarify MLF thermal pad connection info Replace 16 pin 300 MIL SOIC with correct 150 MIL 413404 HMT See ECN Update 32 pin QFN E Pad dimensions and rev A Update CY branding and convention J 430185 HMT See ECN Add new 32 pin 5x5 mm 0 60 thickness QFN package and diagram CY8C21434 24LKXI Update thermal resistance data Add 56 pin SSOP on chip debug non production part CY8C21001 24PVXI Update typical and recommended Storage Temperature per industrial specs Update copyright and trademarks K 677717 HMT See ECN Add CapSense SNR requirement reference Add new Dev Tool section Add CY8C20x34 to PSoC Device Characteristics table Add Low Power Comparator LPC AC DC electrical spec tables Update rev of 32 Lead 5x5 mm 0 60 MAX QFN package diagram L 2147847 UVS PYRS 02 27 08 Added 32 Pin QFN Sawn pin diagram package diagram and ordering infor mation M 2273246 UVS AESA 04 01 08 Added 32 pin thin sawn package diagram N 2618124 OGNE PYRS 112 09 08 Added Note in Ordering Information section Changed title from PSoC Mixed Signal Array to PSoC Programmable Syst
47. VosoA Input Offset Voltage absolute value 2 5 15 mV TCVosoA Average Input Offset Voltage Drift 10 _ uV C legoa Input Leakage Current Port 0 Analog Pins 200 pA Gross tested to 1 pA Input Capacitance Port 0 Analog Pins 4 5 9 5 Package and dependent Temp 25 C VcuoA Common Mode Voltage Range 0 0 x Vdd 1 V Open Loop Gain 80 dB Isoa Amplifier Supply Current 10 30 uA Table 18 3 3V DC Operational Amplifier Specifications Symbol Description Min Typ Max Units Notes VosoA nput Offset Voltage absolute value 2 5 15 mV TCVosoa Average Input Offset Voltage Drift 10 uV PC legoa Input Leakage Current Port 0 Analog Pins 200 Gross tested to 1 uA CINOA Input Capacitance Port 0 Analog Pins 4 5 9 5 Package and dependent Temp 25 C Vcmoa Common Mode Voltage Range 0 Vdd 1 V Loop Gain 80 dB Isoa Amplifier Supply Current 10 30 Note 5 Atypical behavior lego of Port 0 Pin 0 is below 1 nA at 25 C 50 nA over temperature Use Port 0 Pins 1 7 for the lowest leakage of 200 nA Document Number 38 12025 Rev O Page 21 of 45 Feedback m CY8C21634 CY8C21534 2 ypnrcs CY8C21434 CY8C21334 CY8C21234 PERFORM Table 19 2 7V DC Operational Amplifier Specifications Symbol Description Min Typ Max U
48. W A6 ADC1 TR E6 RW 27 ALT CRO 67 RW AT E7 DCBO2FN 28 RW 68 A8 IMO TR E8 DCBO2IN 29 RW 69 AQ ILO_TR E9 DCB020U 2A RW 6A AA BDG TR EA RW 2B CLK CR3 6B RW AB ECO TR EB 2 RW TMP DRO 6C RW AC EC DCBO3IN 2D RW TMP DR1 6D RW AD ED DCB03OU 2b RW TMP DR2 6E RW AE EE 2F TMP DR3 6F RW AF EF 30 70 RDIORI BO RW FO 31 71 RDIOSYN B1 RW F1 32 ACEOOCR1 72 RW RDIOIS B2 RW F2 33 ACEO0CR2 73 RW RDIOLTO B3 RW F3 34 74 RDIOLT1 4 RW F4 35 75 RDIOROO B5 RW F5 36 ACEO1CR1 76 RW RDIORO1 B6 RW F6 37 ACEO1CR2 7T RW B7 CPU F F7 RL 38 78 B8 F8 39 79 B9 F9 3A 7A BA FLS PR1 FA RW 3B 7B BB FB 3C 7C BC FC 3D 7D BD DAC CR FD RW 3E CPU SCR1 FE CPU SCRO FF Blank fields are Reserved and must not be accessed Document Number 38 12025 Rev O Access is bit specific Page 17 of 45 Feedback CY8C21634 CY8C21534 CYPRESS CY8C21434 CY8C21334 CY8C21234 PERFORM Electrical Specifications This section presents the DC and AC electrical specifications of the CY8C21x34 PSoC device For up to date electrical specifications visit the web site http www cypress com psoc Specifications are valid for 40 C lt lt 85 C and lt 100 C as specified except where noted Refer Table 25 on page 26 for the electrical specifications on the internal main oscillator IMO using SLIMO mode Figure 13 Voltage versus CPU Frequency Figure 14 IMO Frequency
49. ademarks of their respective holders Feedback
50. age 22 of 45 Feedback CY8C21634 CY8C21534 CY8C21434 CY8C21334 CY8C21234 PERFORM Table 21 DC Switch Mode Pump SMP Specifications continued Symbol Description Min Typ Max Units Notes Line Regulation over Vi range 5 Configuration of footnote 61 Vo Line i is the Vdd Value for PUMP Trip specified by the VM 2 0 setting inthe DC POR and LVD Specification Table 23 on page 24 AVpump_ Load Regulation 5 Configuration of footnote 1 Vo Load is the Vdd Value for PUMP Trip specified by the VM 2 0 setting inthe DC POR and LVD Specification Table 23 on page 24 Output Voltage Ripple depends on cap load 100 mVpp Configuration of footnote 6l Ripple 7 Load is 5 Efficiency 35 50 Configuration of 61 Load is 5 mA SMP trip voltage is set to 3 25V E gt Efficiency 35 80 load 1mA 2 55V 1 3V 10 uH inductor 1 uF capacitor and Schottky diode Foump Switching Frequency 1 3 MHz DCpymp Switching Duty Cycle 50 Figure 15 Basic Switch Mode Pump Circuit D1 Veuve Veat Battery Note 6 L4 2 mH inductor C4 10 mF capacitor D4 Schottky diode See Figure 15 Document Number 38 12025 Rev O Page 23 of 45 Feedback CY8C21634 CY8C21534 CYPRESS CY8C21434 CY8C21334 CY8C21234
51. d capacitor block input 22 IO M P2 4 23 IO M P2 6 24 IO M PO 0 Analog column mux input 25 IO 1 M PO 2 Analog column mux input 26 IO 1 M PO 4 Analog column mux input 27 IO PO 6 Analog column mux input 28 Power Supply voltage LEGEND Analog Input O lt Output and M lt Analog Mux Input Document Number 38 12025 Rev O Page 10 of 45 Feedback 32 Part Pinout Figure 6 CY8C21434 32 Pin PSoC Device M PO 1 M P2 7 M P2 5 M P2 3 M P2 1 M P3 3 M P3 1 I2C SCL P1 7 Figure 10 CY8C21434 32 Pin Sawn PSoC Device A 1 M PO 1 M 2 7 M 2 5 M 2 3 M P2 1 M P3 3 M P3 1 M 12C SCL P1 7 N 1 m2 m4 m5 m6 m7 m8 Vss 12 SDA P1 5 PO 3 0 5 POP Vdd PO 6 QFN lt P0 4 P0 2 P0 0 A I M 2 6 M P2 4 M P2 2 M Top View P2 0 M YSS M P1 3 12C SDA P1 0 12C SCL P1 1 M P1 2 M EXTCLK 1 4 P3 2 3 0 XRES zzz zzz lt lt lt lt lt lt 0 0 5 222528 Nr 1020 CN CN CN CN U CM 24 0 A M 234 P2 6 224 2 4 M 21 P2 2 View 20 P2 0 19 P3 2 18 P3 0 178 XRES alse as Du cu
52. e Characteristics a o2 PSoC gogl 80 85 8 92 o Zo SN Number 12 S a lt lt lt lt u CY8C29x66 4 16 12 4 4 12 32K 64 CY8C27x43 2 8 12 4 4 12 256 16 44 Bytes 8 24 94 56 1 4 482 2 6 16K CY8C24x23A upto 1 4 12 2 2 6 1256 4 24 Bytes CY8C21x34 1 4 28 0 2 411 512 8 28 Bytes 8 21 23 16 1 4 0 2 1401256 Bytes CY8C20x34 0 0 28 0 371 512 8 28 Bytes Getting Started The quickest way to understand PSoC silicon is to read this data sheet and then use the PSoC Designer Integrated Development Environment IDE This data sheet is an overview of the PSoC integrated circuit and presents specific pin register and electrical specifications For in depth information along with detailed programming details see the PSoC Programmable System on Chip Technical Reference Manual for CY8C28xxx PSoC devices Notes 1 Limited analog functionality 2 Two analog blocks and one CapSense Document Number 38 12025 Rev O CY8C21634 CY8C21534 CY8C21434 CY8C21334 CY8C21234 For up to date ordering packaging and electrical specification information see the latest PSoC device data sheets on the web at www cypress com psoc Application Notes Application notes are an excellent introducti
53. em on Chip 0 2684145 SNV AESA 04 06 2009 Updated 32 Pin Sawn QFN package dimension for CY8C21434 24LTXIT Updated Getting Started Development Tools and Designing with PSoC Designer Sections Document Number 38 12025 Rev O Page 44 of 45 Feedback P CYPRESS CY8C21434 CY8C21334 CY8C21234 M SS SSS 1 m CY8C21634 CY8C21534 PERFORM Sales Solutions and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices solution centers manufacturer s representatives and distributors To find the office closest to you visit us at cypress com sales Products PSoC Solutions PSoC psoc cypress com General psoc cypress com solutions Clocks amp Buffers clocks cypress com Low Power Low Voltage psoc cypress com low power Wireless wireless cypress com Precision Analog psoc cypress com precision analog Memories memory cypress com LCD Drive psoc cypress com Icd drive Image Sensors image cypress com CAN 2 0b psoc cypress com can USB psoc cypress com usb Cypress Semiconductor Corporation 2004 2009 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted n
54. for the voltage and temperature ranges 4 75V to 5 25V and 40 C lt TA lt 85 C 3 0V to 3 6V and 40 C lt Ty lt 85 C or 2 4V to 3 0V and 40 C lt TA lt 85 C respectively Typical parameters apply to 5V 3 3V and 2 7V at 25 C and are for design guidance only Table 15 5V and 3 3V DC GPIO Specifications Symbol Description Min Typ Max Units Notes Pull up Resistor 4 5 6 8 Rpp Pull down Resistor 4 5 6 8 High Output Level Vdd V 10 mA Vdd 4 75 to 5 25V 8 1 0 total loads 4 on even port pins for example PO 2 P1 4 4 on odd port pins for example PO 3 P1 5 VoL Low Output Level 0 75 V 25 mA Vdd 4 75 to 5 25V 8 total loads 4 on even port pins for example PO 2 P1 4 4 on odd port pins for example PO 3 P1 5 Input Low Level 0 8 V Vdd 3 0 to 5 25 Input High Level 2 1 V 3 0 to 5 25 Input Hysteresis 60 mV Input Leakage Absolute Value 1 nA Gross tested to 1 uA Capacitive Load on Pins as Input 3 5 10 pF and dependent Temp 25 C Cout Capacitive Load on Pins as Output _ 3 5 10 pF Package pin dependent Temp 25 C Table 16 2 7V DC GPIO Specifications Symbol Description Min Typ Max Units Notes Rpy Pull up Resistor 4 5 6 8 Rpp Pull down Resistor 4 5
55. gic operations This configurability frees your designs from the constraints of a fixed peripheral controller Digital blocks are provided in rows of four where the number of blocks varies by PSoC device family This allows the optimum choice of system resources for your application Family resources are shown in Table 1 on page 4 Figure 1 Digital System Block Diagram DigitalClocks FromCore ToAnalog System To System Bus DIGITAL SYSTEM Digital PSoC Block Array Row 0 4 5 5 So gs DBBOO DBBO1 DCB02 DCB03 c o 5 28 8 V 3 3 XE GIE7 0 GOE7 0 Global Digital GIO 7 0 Interconnect GOO 7 0 Page 2 of 45 Feedback PERFORM The Analog System The Analog System consists of 4 configurable blocks that allow the creation of complex analog signal flows Analog peripherals are very flexible and may be customized to support specific application requirements Some of the common PSoC analog functions for this device most available as user modules are m Analog to digital converters single or dual with 8 bit or 10 bit resolution m Pin to pin comparator m Single ended comparators up to 2 with absolute 1 3V reference or 8 bit DAC reference m 1 3V reference as a System Resource In most PSoC devices analog blocks are provided in columns of three which includes one CT Continuous Time and two SC
56. iability Ambient Temperature with Power Applied 40 85 Supply Voltage Relative to Vss 0 5 6 0 V Vio DC Input Voltage Vss Vdd V 0 5 0 5 Vioz DC Voltage Applied to Tri state Vss Vdd V 0 5 0 5 Maximum Current into any Port Pin 25 50 mA ESD Electro Static Discharge Voltage 2000 V Human Body Model ESD LU Latch up Current 200 mA Operating Temperature Table 13 Operating Temperature Symbol Description Min Typ Max Units Notes TA Ambient Temperature 40 85 C Ty Junction Temperature 40 _ 100 C The temperature rise from ambient to junction is package specific See Table 40 on page 38 The user must limit the power consumption to comply with this requirement DC Electrical Characteristics DC Chip Level Specifications Table 14 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges 4 75V to 5 25V and 40 lt TA lt 85 C 3 0V to 3 6V and 40 C lt TA x 85 C or 2 4V to 3 0V and 40 C x Ty x 85 C respectively Typical parameters apply to 5V 3 3V or 2 7V at 25 C and are for design guidance only Table 14 DC Chip Level Specifications Symbol Description Min Typ Max Units Notes 2 40 5 25 V See Table 23 on page 24 150 Supply Current 1 24 MHz 3 4 mA Conditions are Vdd lt 5 0V TA 25 C CPU 3 MHz 48 MHz disabled VC1 lt
57. n High 2 Strong or Open Drain Drive Modes on All GPIO Up to 8 Analog Inputs on GPIO Configurable Interrupt on All GPIO Cypress Semiconductor Corporation 198 Champion Court Document Number 38 12025 Rev O m Versatile Analog Mux Common Internal Analog Bus Simultaneous Connection of IO Combinations Capacitive Sensing Application Capability m Additional System Resources a Master Slave and Multi Master to 400 kHz Watchdog and Sleep Timers User Configurable Low Voltage Detection Integrated Supervisory Circuit On Chip Precision Voltage Reference Logic Block Diagram it it i it PSoC CORE Global Digital Interconnect Global Analog Interconnect SROM Flash 8K Sleep and Watchdog CPU Core M8C Digital PSoC Block Digital POR and LvD Switch Internal 2 Mode Voltage System Resets Pump Ref SYSTEM RESOURCES San Jose CA 95134 1709 408 943 2600 Revised April 06 2009 Feedback PSoC Functional Overview The PSoC family consists of many Mixed Signal Array with On Chip Controller devices These devices are designed to replace multiple traditional MCU based system components with one low cost single chip programmable component A PSoC device includes configurable blocks of analog and digital logic and programmable interconnect This architecture enables the user to create cust
58. nits Notes VosoA Input Offset Voltage absolute value 2 5 15 mV TCVosoa Average Input Offset Voltage Drift 10 uV c legoa Input Leakage Current Port 0 Analog Pins 200 Gross tested to 1 uA CINOA Input Capacitance Port 0 Analog Pins 45 9 5 Package and dependent Temp 25 C Vcmoa Common Mode Voltage Range 0 Vdd 1 V Loop Gain 80 dB Ison Amplifier Supply Current 10 30 DC Low Power Comparator Specifications Table 20 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges 4 75V to 5 25V and 40 lt TA lt 85 C 3 0V to 3 6V and 40 C lt TA x 85 C or 2 4V to 3 0V and 40 C x Ty x 85 C respectively Typical parameters apply to 5V at 25 C and are for design guidance only Table 20 DC Low Power Comparator Specifications Symbol Description Min Typ Max Units Notes Low power comparator LPC reference 0 2 Vdd 1 V voltage range LPC supply current 10 40 Vosipc LPC voltage offset 2 5 30 mV DC Switch Mode Pump Specifications Table 21 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges 4 75V to 5 25V and 40 lt TA 85 C 3 0V to 3 6V and 40 C lt Ty lt 85 C or 2 4V to 3 0V and 40 C x T4 x 85 C respectively Typical parameters apply to 5V 3 3V or 2 7V at 2
59. ns Symbol Description Min Typ Max Units Notes Vddiwrite Supply Voltage for Flash Write Operations 2 70 V Ippp Supply Current During Programming or Verify 5 25 mA Input Low Voltage During Programming or 0 8 V Verify ViHP Input High Voltage During Programming or 2 2 V Verify ly p Input Current when Applying Vilp to P1 0 or 0 2 mA Driving internal pull down resistor P1 1 During Programming or Verify Input Current when Applying Vihp to P1 0 or 1 5 mA Driving internal pull down resistor P1 1 During Programming or Verify Output Low Voltage During Programming V Verify 0 75 Output High Voltage During Programming Vdd Vdd V Verify 1 0 Flashgypg Flash Endurance per block 50 000 Erase write cycles per block Flashent Flash Endurance total T 1 800 Erase write cycles 000 Flashpr Flash Data Retention 10 Years Note 11 A maximum of 36 x 50 000 block endurance cycles is allowed This may be balanced between operations on 36x1 blocks of 50 000 maximum cycles each 36x2 blocks of 25 000 maximum cycles each or 36x4 blocks of 12 500 maximum cycles each to limit the total number of cycles to 36x50 000 and that no single block ever sees more than 50 000 cycles For the full industrial range the user must employ a temperature sensor user module FlashTemp and feed the result to the temperature
60. nteed maximum and minimum specifications for the voltage and temperature ranges 4 75V to 5 25V and 40 C lt TA lt 85 3 0V to 3 6V and 40 C lt Ty lt 85 C or 2 4V to 3 0V and 40 C lt TA lt 85 C respectively Typical parameters apply to 5V 3 3V or 2 7V at 25 C and are for design guidance only Table 27 5V and 3 3V AC GPIO Specifications CY8C21634 CY8C21534 CY8C21434 CY8C21334 CY8C21234 Symbol Description Min Typ Max Units Notes GPIO Operating Frequency 0 12 MHz Normal Strong Mode TRiseF Rise Time Normal Strong Mode Cload 50 pF 3 18 ns Vdd 4 5 to 5 25V 10 90 TFallF Fall Time Normal Strong Mode Cload lt 50 pF 2 18 ns 4 5 to 5 25V 10 90 TRiseS Rise Time Slow Strong Mode Cload 50 pF 7 27 ns 9 3 to 5 25V 10 90 TFallS Fall Time Slow Strong Mode Cload lt 50 pF 7 22 ns Vdd 3 to 5 25V 10 90 Table 28 2 7V AC GPIO Specifications Symbol Description Min Typ Max Units Notes Fepio GPIO Operating Frequency 0 3 MHz Normal Strong Mode TRiseF Rise Time Normal Strong Mode Cload lt 50 pF 6 50 ns Vdd 24 to 3 0V 10 90 TFallF Fall Time Normal Strong Mode Cload 50 pF 6 50 ns Vdd lt 2 4 to 3 0V 1096 9096 TRiseS Rise Time Slow Strong Mode Cload lt 50 pF 18 40 120 ns Vdd 2 4 to 3 0V 10 90 TFallS Fall Time Slow Strong Mode Cload 50 pF 18 40 120 ns Vdd 2 4 to
61. oC Device Sample m 28 Pin CY8C27443 24PXI PDIP PSoC Device Sample m PSoC Designer Software CD m Getting Started Guide m USB 2 0 Cable Page 40 of 45 Feedback PERFORM CY3210 PSoCEval1 The CY3210 PSoCEval1 kit features an evaluation board and the MiniProg1 programming unit The evaluation board includes an LCD module potentiometer LEDs and plenty of bread boarding space to meet all of your evaluation needs The kit includes m Evaluation Board with LCD Module m MiniProg Programming Unit m 28 Pin CY8C29466 24PXI PDIP PSoC Device Sample 2 m PSoC Designer Software CD m Getting Started Guide m USB 2 0 Cable CY3214 PSoCEvalUSB The 3214 evaluation kit features development board for the 8 24794 24 PSoC device Special features of the board include both USB and capacitive sensing development and debugging support This evaluation board also includes an LCD module potentiometer LEDs an enunciator and plenty of bread boarding space to meet all of your evaluation needs The kit includes m PSoCEvalUSB Board m LCD Module m MiniProg Programming Unit m Mini USB Cable m PSoC Designer and Example Projects CD m Getting Started Guide m Wire Pack Accessories Emulation and Programming Table 42 Emulation and Programming Accessories Part Pin Package 251 Foot Adapter CY8C21634 CY8C21534 CY8C21434 CY8C21334 CY8C21234 Device Programmers
62. ominal 0 48 49 21213151 MHz RefertotheAC Digital Block Specifications Digital PSoC Block Frequency 3 3V Nominal 0 24 24 613191 MHz F32K1 Internal Low Speed Oscillator Frequency 15 32 64 kHz Jitter32k 32 kHz RMS Period Jitter 100 200 ns Jitter32k 32 kHz Peak to Peak Period Jitter 1400 TxRsT External Reset Pulse Width 10 _ us DC24M 24 MHz Duty Cycle 40 50 60 Step24M 24 MHz Trim Step Size 50 kHz Fout48M 48 MHz Output Frequency 46 8 48 0 49 211214 MHz Trimmed Using factory trim values Jitter24M1 24 MHz Peak to Peak Period Jitter IMO 600 ps FMAX Maximum frequency of signal on row input or 12 3 MHz row output TRAMP Supply Ramp Time 0 us Notes 12 4 75 lt Vdd lt 5 25V 13 Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range 14 3 0 lt Vdd lt 3 6V See Application Note AN2012 Adjusting PSoC Microcontroller Trims for Dual Voltage Range Operation for information on trimming for operation at 3 3V 15 See the individual user module data sheets for information on maximum frequencies for user modules Document Number 38 12025 Rev O Page 26 of 45 Feedback CY8C21634 CY8C21534 CY8C21434 CY8C21334 CY8C21234 PERFORM Table 26 2 7V AC Chip Level Specifications Symbol Description Min Typ Max Units Notes 12 Internal Main Oscillator Frequency for 12 MHz
63. omized peripheral configurations to match the requirements of each individual application Additionally a fast CPU Flash program memory SRAM data memory and configurable IO are included in a range of convenient pinouts The PSoC architecture shown in Figure 1 consists of four main areas the Core the System Resources the Digital System and the Analog System Configurable global bus resources allow combining all the device resources into a complete custom System Each CY8C21x34 PSoC device includes four digital blocks and four analog blocks Depending on the PSoC package up to 28 general purpose IO GPIO are also included The GPIO provide access to the global digital and analog inter connects The PSoC Core The PSoC Core is a powerful engine that supports a rich instruction set It encompasses SRAM for data storage an interrupt controller sleep and watchdog timers and IMO internal main oscillator and ILO internal low speed oscillator The CPU core called the M8C is a powerful processor with speeds up to 24 MHz The 8 is a four MIPS 8 bit Harvard architecture microprocessor System Resources provide the following additional capabilities m Digital clocks to increase the flexibility of the PSoC mixed signal arrays m 2C functionality to implement an I2C master and slave m An internal voltage reference MultiMaster that provides an absolute value of 1 3V to a number of PSoC subsystems m A switch mode pump
64. on to the wide variety of possible PSoC designs They located here www cypress com psoc Select Application Notes under the Documentation tab Development Kits PSoC Development Kits are available online from Cypress at www cypress com shop and through a growing number of regional and global distributors which include Arrow Avnet Digi Key Farnell Future Electronics and Newark Training Free PSoC technical training on demand webinars and workshops is available online at www cypress com training The training covers a wide variety of topics and skill levels to assist you in your designs Cypros Consultants Certified PSoC Consultants offer everything from technical assistance to completed PSoC designs To contact or become a PSoC Consultant go to www cypress com cypros Solutions Library Visit our growing library of solution focused designs at www cypress com solutions Here you can find various appli cation designs that include firmware and hardware design files that enable you to complete your designs quickly Technical Support For assistance with technical issues search KnowledgeBase articles and forums at www cypress com support If you cannot find an answer to your question call technical support at 1 800 541 4736 Page 4 of 45 Feedback Development Tools PSoC Designer is a Microsoft Windows based integrated development environment for the Programmable System on Chip PSoC
65. or intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Any Source Code software and or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign United States copyright laws and international treaty provisions Cypress hereby grants to licensee a personal non exclusive non transferable license to copy use modify create derivative works of and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement Any reproduction modification translation compilation or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD T
66. places routes and configures a programmable gain amplifier PGA to buffer the input from the potentiometer an analog to digital converter ADC to convert the potentiometer s output to a digital signal and a PWM to control the fan In the chip level view perform the selection configuration and routing so that you have complete control over the use of all on chip resources Generate Verify and Debug When you are to test the hardware configuration or move on to developing code for the project perform the Generate Application step This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the software for the system Both system level and chip level designs generate software based on your design The chip level design provides application programming interfaces APIs with high level functions to control and respond to hardware events at run time and interrupt service routines that you can adapt as needed The system level design also generates a C main program that completely controls the chosen application and contains placeholders for custom code at strategic positions allowing you to further refine the software without disrupting the generated code A complete code development environment allows you to develop and customize your applications in C assembly language or both The last step in the development process takes place inside the PSoC De
67. rovide additional capability useful to complete systems Additional resources include a switch mode pump low voltage detection and power on reset Brief statements describing the merits of each system resource follow m Digital clock dividers provide three customizable clock frequencies for use in applications The clocks may be routed to both the digital and analog systems Additional clocks can be generated using digital PSoC blocks as clock dividers m Thel2C module provides 100 and 400 kHz communication over two wires Slave master and multi master modes are all supported m Low Voltage Detection LVD interrupts can signal the application of falling voltage levels while the advanced POR Power On Reset circuit eliminates the need for a system supervisor m An internal 1 3 voltage reference provides an absolute reference for the analog system including ADCs and DACs m An integrated switch mode pump SMP generates normal operating voltages from a single 1 2V battery cell providing a low cost boost converter m Versatile analog multiplexer system Page 3 of 45 Feedback PERFORM PSoC Device Characteristics Depending on your PSoC device characteristics the digital and analog systems can have 16 8 or 4 digital blocks and 12 6 or 4 analog blocks Table 1 lists the resources available for specific PSoC device groups The PSoC device covered by this data sheet is highlighted in this table Table 1 PSoC Devic
68. settings that implement the selected function They also provide parameters and properties that allow you to tailor their precise configuration to your particular application For example a Pulse Width Modulator PWM User Module configures one or more digital PSoC blocks one for each 8 bits of resolution The user module parameters permit you to establish the pulse width and duty cycle Configure the parameters and properties to correspond to your chosen application Enter values directly or by selecting values from drop down menus Both the system level drivers and chip level user modules are documented in data sheets that are viewed directly in the PSoC Designer These data sheets explain the internal operation of the component and provide performance specifications Each data sheet describes the use of each user module parameter or driver Document Number 38 12025 Rev O CY8C21634 CY8C21534 CY8C21434 CY8C21334 CY8C21234 property and other information you may need to successfully implement your design Organize and Connect You can build signal chains at the chip level by interconnecting user modules to each other and the IO pins or connect system level inputs outputs and communication interfaces to each other with valuator functions In the system level view selecting a potentiometer driver to control a variable speed fan driver and setting up the valuators to control the fan speed based on input from the pot selects
69. signers Debugger subsystem The Debugger downloads the HEX image to the ICE where it runs at full speed Debugger capabilities rival those of systems costing many times more In addition to traditional single step run to breakpoint and watch variable features the Debugger provides a large trace buffer and allows you define complex breakpoint events that include monitoring address and data bus values memory locations and external signals Page 6 of 45 Feedback Document Conventions Acronyms Used The following table lists the acronyms that are used in this document Table 2 Acronyms Used Acronym Description AC alternating current ADC analog to digital converter API application programming interface CPU central processing unit CT continuous time DAC digital to analog converter DC direct current ECO external crystal oscillator EEPROM electrically erasable programmable read only memory FSR full scale range GPIO general purpose IO GUI graphical user interface HBM human body model ICE in circuit emulator ILO internal low speed oscillator IMO internal main oscillator IO input output IPOR imprecise power on reset LSb least significant bit LVD low voltage detect MSb most significant bit PC program counter PLL phase locked loop POR power on reset PPOR precision power on reset PSoC Programmable System on Chip
70. t Ty lt 85 C respectively Typical parameters apply to 5V 3 3V or 2 7V at 25 C and are for design guidance only Table 34 5V AC External Clock Specifications Symbol Description Min Typ Max Units Foscext Frequency 0 093 24 6 MHz High Period 20 6 5300 ns Low Period 20 6 ns Power Up IMO to Switch 150 us Note 20 100 ns minimum input pulse width is based on the input synchronizers running at 12 MHz 84 ns nominal period Document Number 38 12025 Rev O Page 30 of 45 Feedback CY8C21634 CY8C21534 CY8C21434 CY8C21334 CY8C21234 PERFORM Table 35 3 3V AC External Clock Specifications Symbol Description Min Typ Max Units Notes Foscext Frequency with CPU Clock divide by 1 0 093 12 3 MHz CPU frequency is 12 MHz at 3 3V With the CPU clock divider set to 1 the external clock must adhere to the maximum frequency and duty cycle requirements Foscext Frequency with CPU Clock divide by 2 or 0 186 E 24 6 MHz Ifthefrequency ofthe external clock greater is greater than 12 MHz the CPU clock divider must be set to 2 or greater In this case the CPU clock divider ensures thatthe fifty percent duty cycle requirement is met High Period with CPU Clock divide by 1 41 7 5300 ns Low Period with CPU Clock divide by 1 41 7 5 Power Up IMO to Switch 150 us Table 36 2 7V A
71. t board and performs full speed 24 MHZ operation Page 5 of 45 Feedback PERFORM Designing with PSoC Designer The development process for the PSoC device differs from that of a traditional fixed function microprocessor The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification change during development and by lowering inventory costs These configurable resources called PSoC Blocks have the ability to implement a wide variety of user selectable functions The PSoC development process can be summarized in the following four steps 1 Select components 2 Configure components 3 Organize and Connect 4 Generate Verify and Debug Select Components Both the system level and chip level views provide a library of prebuilt pretested hardware peripheral components In the system level view these components are called drivers and correspond to inputs a thermistor for example outputs a brushless DC fan for example communication interfaces 12 for example and the logic to control how they interact with one another called valuators In the chip level view the components are called user modules User modules make selecting and implementing peripheral devices simple and come in analog digital and mixed signal varieties Configure Components Each of the components you select establishes the basic register
72. tecture They come complete with embedded libraries providing port and bus operations standard keypad and display support and extended math functionality Debugger The PSoC Designer Debugger subsystem provides hardware in circuit emulation allowing you to test the program in a physical system while providing an internal view of the PSoC device Debugger commands allow the designer to read and program and read and write data memory read and write IO registers read and write CPU registers set and clear breakpoints and provide program run halt and step control The debugger also allows the designer to create a trace buffer of registers and memory locations of interest Online Help System The online help system displays online context sensitive help for the user Designed for procedural and quick reference each functional subsystem has its own context sensitive help This System also provides tutorials and links to FAQs and an Online Support Forum to aid the designer in getting started In Circuit Emulator A low cost high functionality In Circuit Emulator ICE is available for development support This hardware has the capability to program single devices The emulator consists of a base unit that connects to the PC by way of a USB port The base unit is universal and operates with all PSoC devices Emulation pods for each device family are available separately The emulation pod takes the place of the PSoC device in the targe
73. the guaranteed maximum and minimum specifications for the voltage and temperature ranges 4 75V to 5 25V and 40 lt TA 85 C 3 0V to 3 6V and 40 C lt TA x 85 C or 2 4V to 3 0V and 40 C x Ty x 85 C respectively Typical parameters apply to 5V 3 3V or 2 7V at 25 C and are for design guidance only Table 31 AC Analog Mux Bus Specifications CY8C21634 CY8C21534 CY8C21434 CY8C21334 CY8C21234 Symbol Description Min Typ Max Units Notes Fsw Switch Rate 3 17 MHz AC Digital Block Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges 4 75V to 5 25V and 40 lt TA x 85 C 3 0V to 3 6V and 40 lt Ty x 85 C or 2 4V to 3 0V and 40 C lt TA x 85 C respectively Typical parameters apply to 5V 3 3V or 2 7V at 25 C and are for design guidance only Table 32 5V and 3 3V AC Digital Block Specifications Function Description Min Typ Max Units Notes gt 4 75 49 2 MHz 4 75 lt lt 5 25 Functions Maximum Block Clocking Frequency lt 4 75V 24 6 MHz 3 0V Vdd 4 75V Timer Capture Pulse Width 501191 ns Maximum Frequency No Capture 49 2 MHz 4 75 lt lt 5 25V Maximum Frequency With or Without Capture

Cypress CY8C21534 User's Manual

Contents

Download Pdf Manuals

Related Search

Related Contents