Cypress CY7C68023 User's Manual
Contents
1. F CYPRESS 1 0 FER FAL KA Features High 480 Mbps or full 12 Mbps speed USB support Both common NAND page sizes supported 512bytes Up to 1 Gbit Capacity 2K bytes Up to 8 Gbit Capacity 8 chip enable pins Up to 8 NAND Flash single device chips Up to 4 NAND Flash dual device chips Industry standard ECC NAND Flash correction 1 bit per 256 correction 2 bit error detection Industry standard SmartMedia page management for wear leveling algorithm bad block handling and Physical to Logical management Supports 8 bit NAND Flash interfaces Supports 30 ns 50 ns 100 ns NAND Flash timing Complies with USB Mass Storage Class Specification rev 1 0 CY7C68024 complies with USB 2 0 Specification for Bus Powered Devices TID 40460274 CY7C68023 CY7C68024 EZ USB NX2LP USB 2 0 NAND Flash Controller 43 mA Typical Active Current e Space saving and lead free 56 QFN package 8 mm x 8 mm e Support for board level manufacturing test via USB interface e 3 3V NAND Flash operation NAND Flash power management support 2 0 Introduction The EZ USB NX2LP NX2LP implements a USB 2 0 NAND Flash controller This controller adheres to the Mass Storage Class Bulk Only Transport Specification The USB port of the NX2LP is connected to a host computer directly or via the downstream port of a USB hub Host software issues commands and data to the NX2LP and receives status and data from the NX2. respective holders Document 38 08055 Rev B Page 8 of 9 Cypress Semiconductor Corporation 2005 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Feedback CYPRESS PERFORM CY7C68023 CY7C68024 Mu A UU 7 o Se ume o A A h HER Document History Page Description Title CY7C68023 CY7C68024 EZ USB NX2LP USB 2 0 NAND Flash Controller Document Number 38 08055 Issue Orig of ECN NO Date Change Description of Change 286009 SEE ECN New Data Sheet Preliminary Information 334796 SEE ECN Adjusted default VID PID released as final IR IR IR Changed Vcc to 10 in DC Characteristics table Change
3. 2LP using standard USB protocol The NX2LP supports industry leading 8 bit NAND Flash inter faces and both common NAND page sizes of 512 and 2k bytes Eight chip enable pins allow the NX2LP to be connected to up to eight single or four dual device NAND Flash chips Certain NX2LP features are configurable enabling the NX2LP to meet the needs of different designs requirements Write Protect LED2 LED1 NAND Control Signals NAND Flash Chip Reset 24 MHz Xtal EZ USB NX2LP Internal Control Logic VBUS USB 2 0 ou FS USB D Xceiver D Engine Cypress Semiconductor Corporation e Interface Chip Enable Signal Logic 8 bit Data Bus Figure 1 1 NX2LP Block Diagram Document 38 08055 Rev B 198 Champion Court San Jose CA 95134 1709 408 943 2600 Revised October 5 2005 ij 7 CYPRESS CY7C68023 CY7C68024 PERFORM 3 0 Pin Assignments 3 1 Pin Diagram CE2 54 N C 53 GND 52 CE7 51 CEG 50 CE5 49 CE4 48 CE3 46 CE1 45 CEO 44 Reserved 43 vcc O O gt RABIA O 42 RESET R B2 41 GND AVCC 3 40 N C XTALOUT 39 N C XTALIN 5 38 WP_SW WP NFZ AVCC EZ USB NX2LP LED2 DPLUS 56 pin QFN 35 LED1 DMINUS 34 ALE AGND 10 33 CLE vcc 11 32 VCC GND 12 31 RE1 N C 13_ 30 REO 29 WE O N c0 O O N Ag
4. Package Type Note 3 Measured at Max Vcc 25 C Document 38 08055 Rev B Page 7 of 9 Feedback CEmZ CYPRESS CY7C68023 CY7C68024 FER FO ROM 14 0 Package Diagram 56 Lead QFN 8 x 8 MM LF56A TOP VIEW SIDE VIEW BOTTOM VIEW 0 08 0 003 c 1 00 0 039 MAX L jus 7 90 0 311 8 10 0 319 0 05 0 002 MAX 7 70 0 303 0 80 0 031 MAX P 0 18 0 007 7 80 0 307 0 200 008 REF 0 28 0 011 PIN1ID N N 0 20 0 008 R y a CU UUUUUUUUUU 1H 0 80 0 031 21 E et Z 0 45 0 018 DIA 5 uo Li E E ES 2 2 C Od O0 LE TEE 8 eg 22 PAD SIZE VARY i n a S 5 DEVICE TYPE 5 oO 0 30 0 012 E 0 50 0 020 Cc 3 UN hnnnnntliannnnf i i ryt l E 0 24 0 009 4X 0 12 L 0 60 0 024 0 50 0 020 z HN 6 45 0 254 SEATING 6 55 0 258 Dimensions in mm PLANE 51 85144 D E Pad Size 4 3 x 5 0 mm typ Figure 14 1 56 lead Quad Flatpack No Lead 8 x 8 mm LF56 15 0 Disclaimers Trademarks and Copyrights EZ USB NX2LP is a trademark and EZ USB is a registered trademark of Cypress Semiconductor Corporation All product and company names mentioned in this document are the trademarks of their
5. aagaaaAangaaA o Bug aaa DD4 GND 26 Reserved 15 Reserved 16 VCC VCC GND 28 Figure 3 1 56 pin QFN 3 2 Pin Descriptions Pin Name Type Default State at Startup Despion pesem i OO ReadyrBusy 1 22Kt0 pulp resistors required 2 REN z RemBuy2QZktikpukwpresstrieqied 4 pno XH NA Ono S XmUN Xu NA mmu S AGND GND GND gen T ACC ewm PWR Analog 33Vsuppy s pws vo tuus NEED NENNEN vo Ho 885 Lec pw pw Gb eno en orn 3 ge Must be tied HIGH no pull up resistor required No connect 1 A sign after the pin name indicates that it is an active LOW signal Document 38 08055 Rev B Page 2 of 9 Feedback M a oa rp y CYPRESS CY7C68023 CY7C68024 PER FORM 3 2 Pin Descriptions continued Reserved N A N A Must be tied HIGH no pull up resistor required VCC P D 3 3V supply Data 0 DD1 Data 1 EM Us wo fC os io 2 ata a Ue vO A pao wer o MH Wie 3 RE 0 O RedEmbe rar REW 0 A RemEmbei OOO ue 0 2 Commdwhenbe 4 AE 0 2 pss tl enable OOOO ras teow o 2 JeasMMytEDsk s ie o 2 fees or wene o Z JWi epoedNANDFGSh OOOO pa RW z Arras 4 Ow o Z Jbemi 4 cew o 2 JWbemmi par
6. cee 0 2 Dbsmmh2 4 Ow 0 2 ETC reo cee o Z JWbemmib SI Ow 0 2 bemmheb rea cm o A Jbember U A a a e O CO NI O B NO O i E al s NINININI N e 00 ES o E co F Im I Document 38 08055 Rev B Page 3 of 9 Feedback ij 7 CYPRESS PERFORM 3 3 Additional Pin Descriptions 3 3 1 DPLUS DMINUS DPLUS and DMINUS are the USB signaling pins and they should be tied to the D and D pins of the USB connector Because they operate at high frequencies the USB signals require special consideration when designing the layout of the PCB General guidelines are given at the end of this document 3 3 2 XTALIN XTALOUT 24 MHz Xtal 12 pF 12 pF capacitor values assume a trace capacitance of 3 pF per side ona four layer FR4 PCB XTALIN XTALOUT Figure 3 2 XTALIN XTALOUT Diagram The NX2LP requires a 24 MHz 100 ppm signal to derive internal timing Typically a 24 MHz 20 pF 500 uW parallel resonant fundamental mode crystal is used but a 24 MHz square wave from another source can also be used If a crystal is used connect its pins to XTALIN and XTALOUT and also through 12 pF capacitors to GND If an alternate clock source is used apply it to XTALIN and leave XTALOUT open 3 33 Data 7 0 The Data 7 0 I O pins provide an 8 bit interface to a NAND Flash device These pins are used to transfer address comma
7. d leave LED1 floating 3 39 10 LED2 The Chip Active LED output pin is used to indicate proper device operation LED2 is asserted LOW when the NX2LP is powered and initialized It is placed in a high Z state under all other conditions If this functionality is not utilized leave LED25 floating 3 3 11 WP_NF The Write protect NAND Flash output pin is used to control the write protect pins on NAND Flash devices This pin should be tied to the Write Protect pins of the NAND Flash devices If WP SWh56 is asserted LOW during a data transfer or if internal operations are still pending the NX2LP will wait until the operation is complete before asserting WP_NF to ensure that there is no data loss or risk of OS error 3 3 12 WP_SW The Write protect Switch input pin is used to select whether or not NAND Flash write protection is enabled by the NX2LP When the pin is asserted LOW the NX2LP will report to the host that the NAND Flash is write protected the WP_NF will be driven LOW and any attempts to write to the configuration data memory area will be blocked by the NX2LP If this pin is asserted LOW during a data transfer or if internal operations are still pending the NX2LP will wait until the operation is complete before asserting WP_NF to ensure that there is no data loss or risk of OS error 33 13 CE 7 O E The Chip Enable output pins are used to select the NAND Flash that the NX2LP will interface Unused Chip Enable pins s
8. d the supply B 397024 SEE ECN G voltage tolerance to 10 in the Operating Conditions section Added new logo Document 38 08055 Rev B Page 9 of 9 Feedback
9. e bypass flyback caps on VBUS placed near connector Product string in USB descriptors Manufacturer string in USB descriptors Enables write protection capability Enabled A Maintain a solid ground plane under the DPLUS and DMI NUS traces Do not allow the plane to be split under these traces Place no vias on the DPLUS or DMINUS trace routing solate the DPLUS and DMINUS traces from all other signal traces use gt 10 mm spacing for best signal quality Source for recommendations e EZ USB FX2 PCB Design Recommendations www cy press com cfuploads support app notes FX2 PCB pdf High speed USB Platform Design Guidelines www usb org developers data hs usb pdg r1 O pdf 9 0 Absolute Maximum Ratings Storage Temperature 65 C to 150 C Ambient Temperature with Power eji eso seen see 0 C to 70 C Supply Voltage to Ground Potential 0 5V to 4 0V DC Input Voltage to Any Input Pin 5 25V DC Voltage Applied to Outputs in High Z State ssssssuss 0 5V to VCC 0 5V Power DisSipatiON ccooccccooccncoccnccocncocnncnnnncnncnnnnnnnos 300 mW Static Discharge Voltage coccconcconcococcnnccooccnnconnnoos 2000V Max Output Current per lO port 10 mA 10 0 Operating Conditions Ta Ambient Temperature Under Bias 0 C to 70 C Supply Volta
10. ge ooooocccccoocncococoococncononos 3 00V to 3 60V Ground Voltage chron eiie ais OV Fosc Oscillator or Crystal Frequency 24 MHz 100 ppm Parallel Resonant 2 Ifan alternate clock source is input on XTALIN it must be supplied with standard 3 3V signaling characteristics and XTALOUT must be left floating Document 38 08055 Rev B Page 6 of 9 Feedback M a a wat V CYPRESS CY7C68023 CY7C68024 PERFORM DC Characteristics Typ 3 3 lt Vo o Ramp T E 3 T Input Pin Capacitance All but D D Only D D Supply Current USB High Speed Suspend Current CY7C68023 Connected p Disconnected CY7C68024 und Disconnected lUNCONFIG Before current requested in USB descriptors is granted by the host TRESET Reset Time After Valid Power c gt 3 0V Pin Reset After Valid Startup Q O V V E gt E r X O A lt Z C IH IL VoH VoL H C O c A 3 gt 3 gt ii ES e Lo O Z gl e 3 gt e D gt O lc Oo al 3 gt 0 C 02 U O O 2 2 D O r D o o B y on Qo E gt gt lt Q 3 12 0 AC Electrical Characteristics 12 1 USB Transceiver The NX2LP s USB interface complies with the USB 2 0 speci fication for bus powered devices 12 2 NAND Flash Timing The NX2LP supports 30 ns 50 ns and 100 ns NAND Flash devices 13 0 Ordering Information Part Number
11. he NX2LP uses the values stored in NAND Flash to configure the USB descriptors for normal operation as a USB mass storage device If no NAND Flash is detected or if no valid configuration data is found in the configuration data memory area the NX2LP uses the default values from internal ROM space for manufacturing mode operation The two modes of operation are described in sections 6 1 and 6 2 below 6 1 Normal Operation Mode In Normal Operation Mode the NX2LP behaves as a USB 2 0 Mass Storage Class NAND Flash controller This includes all typical USB device states powered configured etc The USB descriptors are returned according to the data stored in the configuration data memory area Normal read and write access to the NAND Flash is available in this mode 6 2 Manufacturing Mode In Manufacturing mode the NX2LP enumerates using the default descriptors and configuration data that are stored in internal ROM This mode allows for first time programming of the configuration data memory area as well as board level manufacturing tests Document 38 08055 Rev B CY7C68023 CY7C68024 A unique USB serial number is required for each device in order to comply with the USB Mass Storage specification Also Cypress requires designers to use their own Vendor ID for final products The Vendor ID is obtained through regis tration with the USB Implementor s Forum USB IF and the Product ID is determined by the designer Cypress pr
12. hould be left floating 3 3 14 RESET Asserting RESET for 10 ms will reset the NX2LP A reset and or watchdog chip is recommended to ensure that startup and brownout conditions are properly handled Page 4 of 9 Feedback ij 7 CYPRESS PERFORM 4 0 Applications The NX2LP is a high speed USB 2 0 peripheral device that connects NAND Flash devices to a USB host using the USB Mass Storage Class protocol 4 1 Additional Resources e CY3685 EZ USB NX2LP Development Kit e CY4618 EZ USB NX2LP Reference Design Kit e USB Specification version 2 0 e USB Mass Storage Class Bulk Only Transport Specification http www usb org developers data devclass usbmassbulk 10 pdf 5 0 Functional Overview 5 1 USB Signaling Speed The NX2LP operates at two of the three rates defined in the USB Specification Revision 2 0 dated April 27 2000 Full speed with a signaling bit rate of 12 Mbits sec High speed with a signaling bit rate of 480 Mbits sec The NX2LP does not support the low speed signaling rate of 1 5 Mbits sec 5 2 NAND Flash Interface During normal operation the NX2LP supports an 8 bit I O interface eight chip enable pins and other control signals compatible with industry standard NAND Flash devices 6 0 Enumeration During the start up sequence internal logic checks for the presence of NAND Flash with valid configuration data in the configuration data memory area If valid configuration data is found t
13. nd and read write data between the NX2LP and NAND Flash 334 R B 2 1 The Ready Busy input pins are used to determine the state of the currently selected NAND Flash device These pins must be pulled HIGH through a 2k 4k resistor These pins are pulled LOW by the NAND Flash when it is busy 3 9 5 WE The Write Enable output pin is used by the NAND Flash to latch commands address and data during the rising edge of the pulse 33 6 RE 1 0 The Read Enable output pins are used to control the data flow from the NAND Flash devices The device presents valid data and will increment its internal column address counter by one Document 38 08055 Rev B CY7C68023 CY7C68024 step on each falling edge of the Read Enable pulse A 10k pull up is an option For RE1 0 3 3 7 CLE The Command Latch Enable output pin is used to indicate that the data on the I O bus is a command The data is latched into the NAND Flash control register on the rising edge of WEZ when CLE is HIGH 3 3 8 ALE The Address Latch Enable output pin is used to indicate that the data on the I O bus is an address The data is latched into the NAND Flash address register on the rising edge of WEZ when ALE is HIGH 3 29 9 LED1 The Data Activity LED output pin is used to indicate data transfer activity LED1 is asserted LOW at the beginning of a data transfer and set to a high Z state when the transfer is complete If this functionality is not utilize
14. ovides all the software tools and drivers necessary for properly programming and testing the NX2LP Please refer to the documentation in the development or reference design kit for more information on these topics C Start up b Yes NAND Flash No Present NAND Flash No Programmed Y Load Default Descriptors and Configuration Data Load Custom Descriptors and Configuration Data Enumerate As Generic NX2LP Storage Device Device Normal Operation Manufacturing Mode Mode Figure 6 1 NX2LP Enumeration Process Enumerate As USB Mass 6 3 Configuration Data Certain features in the NX2LP can be configured by the designer to disable unneeded features and to comply with the USB 2 0 specifications descriptor requirements for mass storage devices Table 6 1 lists the variable configuration data and the default values that are stored in internal ROM space The default ROM values are returned by an unprogrammed NX2LP device Page 5 of 9 Feedback UY CYPRESS Q MG PERFORM CY7C68023 CY7C68024 Table 6 1 Variable Configuration Data And Default ROM Values Configuration Data Vendor ID Product ID Serial Number Manufacturer String Product String Enable Write Protection SCSI Device Name 7 0 Design Notes For The Quad Flat NoLead QFN Package The NX2LP comes in a 56 pin QFN
15. package which utilizes a metal pad on the bottom to aid in heat dissipation The low power operation of the NX2LP makes the thermal pad on the bottom of the QFN package unnecessary Because of this PCB layout may utilize the space under the NX2LP for routing signals as needed provided that any traces or vias under the thermal pad are covered by solder mask or other material to prevent shorting Standard PCB layout recommendations for USB devices still apply For further information on this package design please refer to the application note from AMKOR titled Surface Mount Assembly of AMKOR s MicroLeadFrame MLF Technology This application note provides detailed information on board mounting guidelines soldering flow rework process etc 8 0 The following recommendations should be followed to ensure reliable High speed USB performance operation A four layer impedance controlled board is recommended to ensure best signal quality Specify impedance targets ask your board vendor what they can achieve Maintain trace widths and trace spacing to control imped ance Minimize stubs on DPLUS and DMINUS to avoid reflected signals Place any connections between the USB connector shell and signal ground near the USB connector PCB Layout Recommendations Keep DPLUS and DMINUS trace lengths to within 2 mm of each other in length with preferred length of 20 30 mm Note String shown in the device manager properties Us
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