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Cypress CY7C65113C User's Manual

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1. USB A 3 3V Regulator Vref us IN OUT b S SEHR 2 k 2 2 uF P WW Vref i GND 1 5K V T R USB B Ruup Vbusl 4 Vbus OOT pF in D MN 22x2 Rext N C p V V GND USB A SHELL BG 22x8 Rext ups DO D1 P D DECKER ER D ional 4 nF D1 Rb GND Optional en yac i i XTALO V BE SG D2 10 a duc EE 6 000 IF XTALI D3 ES GND D3 n i GND i Ka USB A D4 TVBUs V A cC D D 15K x8 GND Rupn oeo o o o V V USB A POWER Vbus MANAGEMENT D D 21 0 Absolute Maximum Ratings Storage Temperature EE a A 65 C to 150 C Ambient Temperature with Power Apple 0 C to 70 C Supply voltage op V g relative tO Vegirnir aa Aa aN EAE Ea ASA RNE EE NEEE 0 5V to 7 0V DG Input VONAGE Se rS 0 5V to Voc 0 5V DC Voltage applied to Outputs in High Z State enne nennen 0 5V to Vec 0 5V Be El EE te E 500 mW Static Discharge Voltage e eL gt 2000V L teh Up eli acm gt 200 mA Max Output Sink Current into Port 0 60 mA Max Output Sink Current into DAC 7 2 Pins 10 mA Max Output Source Current from Port 1 2 3 4AB8TI nenne nennen neni nn sinas sessi se essen enne 30 mA Document 38 08002 Rev D Page 45 of 49 Feedback
2. CYPRESS CY7C65113C PERFORM 22 0 Electrical Characteristics fosc 6 MHz Operating Temperature 0 to 70 C Vcc 4 0V to 5 25V Parameter Description Conditions Min Max Unit General VREF Reference Voltage 3 3V 5 3 15 3 45 V Vop Programming Voltage disabled 0 4 0 4 V loc Vcc Operating Current No GPIO source current 50 mA lag Supply Current Suspend Mode 50 uA Let Vrer Operating Current No USB Traffic 10 mA li Input Leakage Current Any pin 1 uA USB Interface V i Differential Input Sensitivity D D 0 2 V Vom Differential Input Common Mode Range 0 8 2 5 V Vse Single Ended Receiver Threshold 0 8 2 0 V Cin Transceiver Capacitance 20 pF lio Hi Z State Data Line Leakage OV lt Vin lt 3 3V 10 10 uA Rex External USB Series Resistor In series with each USB pin 19 21 Q Ryup External Upstream USB Pull up Resistor 1 5 kQ 45 D to VREG 1 425 1 575 kQ RupN External Downstream Pull down Resistors 15 ka 15 downstream USB pins 14 25 15 75 kQ Power on Reset tes VocRampRate fuinearrampovtoVec o 100 ms USB Upstream Downstream Port VuoH Static Output High 15 kQ 5 to Gnd 2 8 3 6 V VuoL Static Output Low 1 5 KO 5 to VREF 0 3 V Zo USB Driver Output Impedance Including Rex Resistor 28 44 Q General Purpose I O GPIO Rup Pull up Resistance typical 14 kQ 8 0 24 0 kQ VITH Input Threshold Voltage All ports low to high edge 20 40 Vec V
3. Mode Bits token count buffer dval DTOG DVAL COUNT Setup in Out ACK Mode Bits Response Intr See Table 18 1 Setup 10 data valid updates 1 updates 1 UC JUC 0 JO O 1 ACK yes See Table 18 1 Setup 10 junk x updates updates updates 1 UC JUC JUC NoChange ignore yes See Table 18 1 Setup x junk invalid updates 0 updates 1 UC UC JUC NoChange ignore yes Properties of Incoming Packet Changes made by SIE to Internal Registers and Mode Bits Mode Bits token count butter dval DTOG DVAL COUNT Setup in Out ACK Mode Bits Response Intr DISABLED 0 10 JO JO x x UC x UC UC UC UC UC JUC JUC NoChange ignore no Nak In Out 0 10 10 1 Out UC UC UC UC UC UC UC NoChange NAK yes 0 10 JO 1 In UC UC UC UC UC 1 UC UC NoChange NAK yes Ignore In Out O 11 10 JO Out UC UC UC UC UC UC UC JUC NoChange ignore no 0 1 O JO Jin UC UC UC UC UC UC UC UC NoChange ignore no Stall In Out 0 10 1 1 Out UC UC UC UC UC UC 1 UC NoChange Stall yes 0 10 1 1 In UC UC UC UC UC 1 UC JUC NoChange Stall yes CONTROL WRITE Properties of Incoming Packet Changes made by SIE to Internal Registers and Mode Bits Mode Bits token count buffer dval DTOG DVAL COUNT Setup in Out ACK Mode Bits Response Intr Normal Out premature status In 110 1 1 Out 210 data valid updates 1 updates UC UC 1 1 1 JO 1 O ACK yes 110 1 1 Out gt 10 junk x updates updates
4. Global Interrupt Enable Bit Int Enable Sense Enable 2 AddrA ENP2 Int CLK Reg 0x21 Controlled by DI El and CLR RETI Instructions Interrupt Acknowledge o o Figure 14 3 Interrupt Controller Function Diagram Document 38 08002 Rev D Page 25 of 49 Feedback CYPRESS CY7C65113C PERFORM Although Reset is not an interrupt the first instruction executed after a reset is at PROM address 0x0000h which corresponds to the first entry in the Interrupt Vector Table Because the JMP instruction is two bytes long the interrupt vectors occupy two bytes Table 14 1 Interrupt Vector Assignments Interrupt Vector Number ROM Address Function Not Applicable 0x0000 Execution after Reset begins here 1 0x0002 USB Bus Reset interrupt 2 0x0004 128 us timer interrupt 3 0x0006 1 024 ms timer interrupt 4 0x0008 USB Address A Endpoint 0 interrupt 5 0x000A USB Address A Endpoint 1 interrupt 6 0x000C USB Address A Endpoint 2 interrupt 7 0x000E USB Address B Endpoint 0 interrupt 8 0x0010 USB Address B Endpoint 1 interrupt 9 0x0012 USB Hub interrupt 10 0x0014 DAC interrupt 11 0x0016 GPIO interrupt 12 0x0018 IC interrupt 14 2 Interrupt Latency Interrupt latency can be calculated from the following equation Interrupt latency Number of clock cycles remaining in the current instruction 10 clock cycles for the CALL
5. ssssssseeeeeee 31 Table 16 2 Control Bit Definition for Upstream Port ronnrnnnrnnrrnnrrnnrrrrnrrnnrrnrrrrnrrrrrnnrrenrrnnsennsennsennesne 34 Table 17 1 Memory Allocation for Endpoints rennnnnrrnnrnnnrrnrrrnnrrnrrrnrrrnrrrnrrrrrrrrrrrnnrensrnnsennsennsennesne 35 Table 18 1 USB Register Mode Encoding rrrrnnnnnnrerrnrnnnnnnnnnvnennrvnnnnnnnannnennnnnenennnnnnnnennnnennnnnnnnnnennenn 39 Table 18 2 Decode table for Table 18 3 Details of Modes for Differing Traffic Condition 40 Table 18 3 Details of Modes for Differing Traffic Conditions rrrarnrrnnnnnrrrrnnnnnnnonnnrrrrnnnnnnnrnnnrnnnnnnnnnn 41 Document 38 08002 Rev D Page 4 of 49 Feedback CYPRESS CY7C65113C PERFORM 1 0 Features Full Speed USB hub with an integrated microcontroller 8 bit USB optimized microcontroller Harvard architecture 6 MHz external clock source 12 MHz internal CPU clock 48 MHz internal hub clock Internal memory 256 bytes of RAM 8 KB of PROM Integrated Master Slave l C compatible Controller 100 kHz enabled through General purpose I O GPIO pins UO ports Two GPIO ports Port 0 to 2 capable of sinking 7 mA per pin typical Higher current drive achievable by connecting multiple GPIO pins together to drive a common output Each GPIO port can be configured as inputs with internal pull ups or open drain outputs or traditional CMOS outputs Maskable i
6. sccccceeeeeeeeseeneeeeeeeeeeseeeceneseeeeeensasssaneneeeseeeeseneeee 32 Figure 16 9 Hub Ports Resume Status Register eeeeeeessseeeceeeeeeene nennt ak nnns ent 33 Figure 16 10 USB Status and Control Register ironic rra n sarete kt nnn a tth an EE EENEG 33 Figure 17 1 USB Device Address Registers eeeseeeeeseseeneeeeee nennen innt nnns nnns 34 Figure 17 2 USB Device Endpoint Zero Mode Registers AAA 35 Figure 17 3 USB Non control Device Endpoint Mode Registers rrnrrnnrrnrrrrrrrrrrrrrrrrnrrnnrrnnrrnnsennnn 36 Figure 174 USB Endpoint Counter Registers 22er erre roba ged Fenkx nen EE S ERI IEEEEV SK UiUNUE 36 Figure 17 5 Token Data Packet Flow Diagram eeeeeeeeeeeeseeeenmeee entren nennt then nnn nnn inns 38 LIST OF TABLES Table 4 1 Pin Assignments ME 8 Table 4 2 I O Register Summary APER Rr 9 Table 4 3 Instruction Set Summary eh eiert ie o clauses iut uada Edi un bh basi pa sedo bi boa Batu 10 Table 9 1 GPIO Port Output Control Truth Table and Interrupt Polarity 19 Table 11 1 I C Port Configuration WEE 20 Table 12 1 I C Status and Control Register Bit Definitions rrrrrrrrnrrnrrrnrrnvrrnrrrnrrnvrrnrrrnrrnnernnrrnennn 21 Table 14 1 Interrupt Vector Assignments mnnrrrnnnnnnnnrnnnvnnnnnnnnnvennnnrnnnnnnnnnnnnnnnnerrnnnnnnnnennnnennnnnnnnnnnenenn 26 Table 16 1 Control Bit Definition for Downstream Ports
7. 28 Lead 300 Mil Molded SOIC NOTE PIN 1 JEDEC STD REF MO 119 2 BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION END FLASH BUT DOES INCLUDE MOLD MISMATCH AND ARE MEASURED AT THE MOLD PARTING LINE MOLD PROTRUSION END FLASH SHALL NOT EXCEED 0 010 in 0 254 mm PER SIDE 1 UBHRDBRODRER E A 3 DIMENSIONS IN INCHES MIN W MAX 0 291 7 39 7599 4 PACKAGE WEIGHT 0 85gms 0 300 7 62 TTITUTUTTESUTUS A i us 28 E 0 026 0 66 528 3 STANDARD PKG 0 032 0 81 Z28 3 LEAD FREE PKG 0 697 17 70 SEATING PLANE 0 713 18 11 t d d j 0 092 2 33 d 0 105 2 67 S I I C 0 004 0 10 8 0 0091 0 23 m 0 013 0 33 0 004 0 10 09131038 0 0125 3 17 La 0 050 1 27 0 019 0 48 0 0118 0 30 0 050 1 27 51 85026 D Purchase of I C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I C Patent Rights to use these components in an 12C system provided that the system conforms to the I C Standard Specification as defined by Philips All product and company names mentioned in this document are the trademarks of their respective holders Document 38 08002 Rev D Page 48 of 49 Cypress Semiconductor Corporation 2006 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes
8. Reset 1 1 1 Figure 9 3 Port1 Data Special care should be taken with any unused GPIO data bits An unused GPIO data bit either a pin on the chip or a port bit that is not bonded on a particular package must not be left floating when the device enters the suspend state If a GPIO data bit is left floating the leakage current caused by the floating bit may violate the suspend current limitation specified by the USB Specifications If a 1 is written to the unused data bit and the port is configured with open drain outputs the unused data bit remains in an indeterminate state Therefore if an unused port bit is programmed in open drain mode it must be written with a 0 A read from a GPIO port always returns the present state of the voltage at the pin independent of the settings in the Port Data Registers During reset all of the GPIO pins are set to a high impedance input state Writing a 0 to a GPIO pin drives the pin LOW In this state a 0 is always read on that GPIO pin unless an external source overdrives the internal pull down device Document 38 08002 Rev D Page 17 of 49 Feedback CYPRESS CY7C65113C PERFORM 9 1 GPIO Configuration Port Every GPIO port can be programmed as inputs with internal pull ups outputs LOW or HIGH or Hi Z floating the pin is not driven internally In addition the interrupt polarity for each port can be programmed The Port Configuration bits Figure
9. The CY7C65113C includes an integrated USB Serial Interface Engine SIE that supports the integrated peripherals and the hub controller function The hardware supports up to two USB device addresses with one device address for the hub two endpoints and a device address for a compound device three endpoints The SIE allows the USB host to communicate with the hub and functions integrated into the microcontroller The CY7C65113C part includes a 1 4 hub repeater with one upstream port and four downstream ports The USB Hub allows power management control of the downstream ports by using GPIO pins assigned by the user firmware The user has the option of ganging the downstream ports together with a single pair of power management pins or providing power management for each port with four pairs of power management pins Document 38 08002 Rev D Page 6 of 49 Feedback CYPRESS PERFORM CY7C65113C 6 MHz crystal i iN PLL Logic Block Diagram Clock Divider p 12 MHz 8 bit CPU 12 MHz PROM 8 KB RAM 256 byte 6 MHz 12 bit Timer Y Watchdog Timer Power on Reset 8 bit Bus 1r 2 Interrupt Controller 48 MHz GPIO PORT 0 lt gt PO O M Po GPIO PORT 1 a P1 0 La P1 2 c comp Interface La
10. 1 JO JO Out x UC x UC UC UC UC UC UC JUC NoChange ignore no 1 1 10 JO Jin x UC x UC UC UC UC 1 UC JUC NoChange NAK yes Isochronous endpoint In O 11 1 1 Out x UC x UC UC UC UC UC JUC JUC NoChange ignore no O 1 1111 Jin x UC x UC UC UC UC 1 UC JUC NoChange TX yes Document 38 08002 Rev D Page 42 of 49 Feedback PERFORM 19 0 Register Summary CY7C65113C Address Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read Write B Default oth 7 Reset E 0x00 Port 0 Data P0 7 P0 6 P0 5 P0 4 P0 3 P0 2 P0 1 P0 0 BBBBBBBB 11111111 9 0x01 Port 1 Data P1 7 P1 6 P1 5 P1 4 P1 3 P1 2 P1 1 P1 0 BBBBBBBB 11111111 lt 0x02 Port 2 Data P2 7 P2 6 P2 5 P2 4 P2 3 P2 2 P2 1 P2 0 BBBBBBBB 11111111 E 0x03 Port 3 Data P3 7 P3 6 P3 5 P3 4 P3 3 P3 2 P3 1 P3 0 BBBBBBBB 11111111 Q 0x04 Port 0 Interrupt Enable PO Intr PO 6 Intr P0 5 Intr PO A Intr P0 3 Intr P0 2 Intr P0 1 Intr PO 0 Intr wwwwwwww 00000000 gt Enable Enable Enable Enable Enable Enable Enable Enable 2 0x05 Port 1 Interrupt Enable P1 7 Intr P1 6 Intr P1 5 Intr P1 4 Intr Reserved P1 2 Intr P1 1 Intr P1 0 Intr wwwwwwww 00000000 E Enable Enable Enable Enable Enable Enable Enable z 0x08 GPIO Configuration Reserved Reserved Reserved Reserved Port 1 Port 1 Port 0 Port 0 BBBBBBBB 00000000 E Config Bit 1 Config Bit 0 Config Bit
11. Reset 0 0 0 0 0 0 0 0 Figure 9 5 Port 0 Interrupt Enable Port 1 Interrupt Enable Address 0x05 Bit 7 6 5 4 3 2 1 0 Bit Name Reserved Reserved Reserved Reserved Reserved P0 2 Intr P1 1 Intr P1 0 Intr Enable Enable Enable Read Write Ww Ww W Reset 0 0 0 Figure 9 6 Port 1 Interrupt Enable 10 0 12 bit Free Running Timer The 12 bit timer operates with a 1 us tick provides two interrupts 128 us and 1 024 ms and allows the firmware to directly time events that are up to 4 ms in duration The lower eight bits of the timer can be read directly by the firmware Reading the lower eight bits latches the upper four bits into a temporary register When the firmware reads the upper four bits of the timer it is actually reading the count stored in the temporary register The effect of this is to ensure a stable 12 bit timer value can be read even when the two reads are separated in time Document 38 08002 Rev D Page 19 of 49 CYPRESS PERFORM Timer LSB CY7C65113C Address 0x24 Bit 7 6 5 4 3 2 1 0 Bit Name Timer Bit 7 TimerBit6 Timer Bit 5 Timer Bit 4 Timer Bit 3 Timer Bit 2 Timer Bit 1 Timer Bit 0 Read Write R R R R R R R R Reset 0 0 0 0 0 0 0 0 Figure 10 1 Timer LSB Register Bit 7 0 Timer lower eight bits Timer MSB Address 0x25 Bit 7 6 5 4 3 2 1 0 Bit Name Reserved Reserved Reserved Reserved Timer
12. gt CYPRESS CY7C65113C mm PERF OR M L USB Hub with Microcontroller n USB Hub with Microcontroller Cypress Semiconductor Corporation 198 Champion Court e Gan Jose CA 95134 1709 408 943 2600 Revised March 6 2006 Document 38 08002 Rev D Feedback CYPRESS CY7C65113C PERFORM TABLE OF CONTENTS UI WqUnicl ene 5 2 0 FUNCTIONAL OVERVIEW geet nao nro ram reto nce eoo nere on Ex e ENKE EEN ano Eua c Ea PEN ERR ERRXR ER YR ENRENRRENER 6 3 0 PINCONFIGURA wuel FETT 8 4 0 PRODUCT SUMMARY TABLES 2uggeeger gedu ee ee NEEN onn NR oL ES aa Ce re ine n lo Ne dern ni 8 21 Pi ASSgnmens tc 8 42 VO Regler SUIMMATY mesmsmstsnmmennetpunsubasrktnsiensamejngdeaedlasdunenenredeninennnnedekee 9 4 3 Instruction Set SUMMATY tetengien ENEE nde Ee EE 10 5 0 PROGRAMMING MODEL 2 2 52227222 1ee eet CECR eru uen eee e Ceo eo eoe aL un ara eau EYE ER deed RR EUER YR Eugen 11 5 1 D leet iE TN Em 11 5 1 1 Program Memory Organization eere rennen the eene eek reae inte der ca EAE e cda 12 52 FM FRC CUI UA sva ti boue ical races M pde eder Ed M end um e a estet 13 5 3 8 bit Temporary Register X uisus Eton p ks eR RU en RUE EDnEREIS KI deg ERRARE CAR EEXEA SUAM KE RA RARE MMRNNRRR nnet 13 5 4 8 bit Program Stack Pointer PSP ere SE EE 13 54 1 Data Memory Org
13. locking allows the hardware to complete certain operations that may require an extended period of time Following an Ic interrupt the I C compatible block does not return to the Busy state until firmware sets the Continue bit This allows the firmware to make one control register write without the need to check the Busy bit Bit 5 Xmit Mode This bit is set by firmware to enter transmit mode and perform a data transmit in master or slave mode Clearing this bit sets the part in receive mode Firmware generally determines the value of this bit from the R W bit associated with the PC address packet The Xmit Mode bit state is ignored when initially writing the MSTR Mode or the Restart bits as these cases always cause transmit mode for the first byte Bit 4 ACK This bit is set or cleared by firmware during receive operation to indicate if the hardware should generate an ACK signal on the I C compatible bus Writing a 1 to this bit generates an ACK SDA LOW on the I2C compatible bus at the ACK bit time During transmits Xmit Mode 1 this bit should be cleared Bit 3 Addr This bit is set by the I C compatible block during the first byte of a slave receive transaction after an IC start or restart The Addr bit is cleared when the firmware sets the Continue bit This bit allows the firmware to recognize when the master has lost arbitration and in slave mode it allows the firmware to recognize that a start or restart has occurred Bit 2 ARB Lost
14. the port is being forced 14 7 GPIO Interrupt Each of the GPIO pins can generate an interrupt if enabled The interrupt polarity can be programmed for each GPIO port as part of the GPIO configuration All of the GPIO pins share a single interrupt vector which means the firmware needs to read the GPIO ports with enabled interrupts to determine which pin or pins caused an interrupt A block diagram of the GPIO interrupt logic is shown in Figure 14 4 Port Configuration GPIO Interrupt Register OR Gate Flip Flop 1 input per Interrupt gt IRQout GPIO pin 4 p o D Priority IN Encoder gt Interrupt Vector ed J CLR 1 Enable Port Interrupt 0 Disable Enable Register IRA Global 1 Enable GPIO Interrupt 0 Disable Enable Bit 5 Register 0x20 Figure 14 4 GPIO Interrupt Structure Refer to Sections 9 1 and 9 2 for more information of setting GPIO interrupt polarity and enabling individual GPIO interrupts If one port pin has triggered an interrupt no other port pins can cause a GPIO interrupt until that port pin has returned to its inactive non trigger state or its corresponding port interrupt enable bit is cleared The USB Controller does not assign interrupt priority to different port pins and the Port Interrupt Enable Registers are not cleared during the interrupt acknowledge process 148 IC Interrupt The IC interrupt occurs af
15. 49 Feedback CYPRESS CY7C65113C PERFORM 9 0 General purpose I O Ports V GPIO BG CFG mode I Ir OE gt d e a2 b Internal pata Ou c Data Bus Latch D gt 8 14 ko GPIO Port Write T DIN 1 ex Data Port Read In Vv Latch Re Bt 1 STRB Latch is Transparent Data Interrupt Latch Control 4 Interrupt Enable Interrupt 4 Controller Port 0 1 Low Link Figure 9 1 Block Diagram of a GPIO Pin There are 11 GPIO pins PO 7 0 and P1 2 0 for the hardware interface Each port can be configured as inputs with internal pull ups open drain outputs or traditional CMOS outputs The data for each GPIO port is accessible through the data registers Port data registers are shown in Figure 9 2 through Figure 9 3 and are set to 1 on reset Port 0 Data Address 0x00 Bit 7 6 5 4 3 2 1 0 Bit Name P0 7 P0 6 P0 5 P0 4 P0 3 P0 2 P0 1 P0 0 Read Write R W R W R W R W R W R W R W R W Reset 1 1 1 1 1 1 1 1 Figure 9 2 Port 0 Data Port 1 Data Address 0x01 Bit 2 1 0 Bit Name P1 2 P1 1 P1 0 ReadWrite 1 RW RW RW
16. 9 4 and the Interrupt Enable bit Figure 9 5 through Figure 9 6 determine the interrupt polarity of the port pins GPIO Configuration Address 0x08 Bit 7 6 5 4 3 2 1 0 Bit Name Reserved Reserved Reserved Reserved Port 1 Port 1 Port 0 Port 0 Config Bit 1 Config Bit 0 Config Bit 1 Config Bit 0 Read Write R W R W R W R W Reset 0 0 0 0 Figure 9 4 GPIO Configuration Register As shown in Table 9 7 below a positive polarity on an input pin represents a rising edge interrupt LOW to HIGH and a negative polarity on an input pin represents a falling edge interrupt HIGH to LOW The GPIO interrupt is generated when all of the following conditions are met the Interrupt Enable bit of the associated Port Interrupt Enable Register is enabled the GPIO Interrupt Enable bit of the Global Interrupt Enable Register Figure 14 1 is enabled the Interrupt Enable Sense bit 2 Figure 13 1 is set and the GPIO pin of the port sees an event matching the interrupt polarity The driving state of each GPIO pin is determined by the value written to the pin s Data Register Figure 9 2 through Figure 9 3 and by its associated Port Configuration bits as shown in the GPIO Configuration Register Figure 9 4 These ports are configured on a per port basis so all pins in a given port are configured together The possible port configurations are detailed in Table 9 1 As shown in this table below
17. Bit 11 Timer Bit 10 Timer Bit 9 Timer Bit 8 Read Write R R R R Reset 0 0 0 0 0 0 0 0 Figure 10 2 Timer MSB Register Bit 3 0 Timer higher nibble Bit 7 4 Reserved 11 0 Figure 10 3 Timer Block Diagram IPC Configuration Register 8 gt 1 024 ms interrupt gt 128 us interrupt 1 MHz clock To Timer Registers Internal hardware supports communication with external devices through an 12C compatible interface I2C compatible function is discussed in detail in Section 12 0 3 The I C Position bit Bit 7 Figure 11 1 and I C Port Width bit Bit 1 Figure 11 1 select the locations of the SCL clock and SDA data pins on Port 1 as shown in Table 11 1 These bits are cleared on reset When the GPIO is configured for I C function the internal pull ups on the pins are disabled Addition of an external weak pull up resistors on SCL and SDA is recommended Re Configuration Address 0x09 Bit 7 6 5 4 3 2 1 0 Bit Name IC Position Reserved Reserved Reserved Reserved Reserved IC Port Reserved Width Read Write R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Figure 11 1 Ic Configuration Register Table 11 1 I C Port Configuration I C Position I C Position Bit7 Figure 11 1 IC Port Width Bit Figure 11 1 0 0 12C on P1 1 0 0 SCL 1 SDA Note 3 I
18. GPIO Port 0 Data 17 Port 1 Data 0x01 R W GPIO Port 1 Data 17 Port 0 Interrupt Enable 0x04 W Interrupt Enable for Pins in Port 0 19 Port 1 Interrupt Enable 0x05 W Interrupt Enable for Pins in Port 1 19 GPIO Configuration 0x08 R W GPIO Port Configurations 18 I C Configuration 0x09 R W I C Position Configuration 20 USB Device Address A 0x10 R W USB Device Address A 34 EP AO Counter Register 0x11 R W USB Address A Endpoint 0 Counter 36 EP AO Mode Register 0x12 R W USB Address A Endpoint 0 Configuration 35 EP A1 Counter Register 0x13 R W USB Address A Endpoint 1 Counter 36 EP A1 Mode Register 0x14 R W USB Address A Endpoint 1 Configuration 36 EP A2 Counter Register 0x15 R W USB Address A Endpoint 2 Counter 36 EP A2 Mode Register 0x16 R W USB Address A Endpoint 2 Configuration 36 USB Status amp Control Ox1F R W USB Upstream Port Traffic Status and Control 33 Global Interrupt Enable 0x20 R W Global Interrupt Enable 24 Endpoint Interrupt Enable 0x21 R W USB Endpoint Interrupt Enables 24 Interrupt Vector 0x23 R Pending Interrupt Vector Read Clear 26 Timer LSB 0x24 R Lower Eight Bits of Free running Timer 1 MHz 20 Timer MSB 0x25 R Upper Four Bits of Free running Timer 20 WDR Clear 0x26 W Watchdog Reset Clear 16 I C Control A Status 0x28 R W CC Status and Control 21 IC Data 0x29 R W IC Data 21 Reserved 0x30 Reserved Reserved 0x31 Reserved Reserved 0x32 Reserved Reserved 0x38 0x3F Reserved USB Device Address B 0x40 R W USB Device Address B no
19. Hub Ports Speed Bit 0 3 Port x Speed where x 1 4 Set to 1 if the device plugged in to Port x is Low Speed Set to 0 if the device plugged in to Port x is Full Speed Bit 4 7 Reserved Set to 0 The Hub Ports Speed register is cleared to zero by reset or bus reset This must be set by the firmware on issuing a port reset The Reserved bits 4 7 should always read as 0 16 2 Enabling Disabling a USB Device After a USB device connection has been detected firmware must update status change bits in the hub status change data structure that is polled periodically by the USB host The host responds by sending a packet that instructs the hub to reset and enable the downstream port Firmware then sets the bit in the Hub Ports Enable register Figure 16 3 for the downstream port The hub repeater hardware responds to an enable bit in the Hub Ports Enable register Figure 16 3 by enabling the downstream port so that USB traffic can flow to and from that port If a port is marked enabled and is not suspended it receives all USB traffic from the upstream port and USB traffic from the downstream port is passed to the upstream port unless babble is detected Low speed ports do not receive full speed traffic from the upstream port When firmware writes to the Hub Ports Enable register Figure 16 3 to enable a port the port is not enabled until the end of any packet currently being transmitted If there is no USB traffic the
20. MOV A expr data 19 4 IOWX X expr index 39 6 MOV A expr direct 1A 5 CPL 3A 4 MOV A X expr index 1B 6 ASL 3B 4 MOV X expr data 1C 4 ASR 3C 4 MOV X expr direct 1D 5 RLC 3D 4 reserved 1E RRC 3E 4 Document 38 08002 Rev D Page 10 of 49 Feedback CYPRESS CY7C65113C PERFORM Table 4 3 Instruction Set Summary continued MNEMONIC operand opcode cycles MNEMONIC operand opcode cycles XPAGE 1F 4 RET 3F 8 MOV A X 40 4 DI 70 4 MOV X A 41 4 EI 72 4 MOV PSP A 60 4 RETI 73 8 CALL addr 50 5F 10 JC addr CO CF 5 or 4 JMP addr 80 8F 5 JNC addr DO DF 5 or 4 CALL addr 90 9F 10 JACC addr EO EF 7 JZ addr AO AF 5 or 4 INDEX addr FO FF 14 JNZ addr BO BF 5 or 4 5 0 Programming Model 5 1 14 bit Program Counter The 14 bit Program Counter PC allows access to up to 8 KB of PROM available with the CY7C65113C architecture The top 32 bytes of the ROM in the 8K part are reserved for testing purposes The program counter is cleared during reset such that the first instruction executed after a reset is at address 0x0000h Typically this is a jump instruction to a reset handler that initializes the application see Interrupt Vectors on page 25 The lower eight bits of the program counter are incremented as instructions are loaded and executed The upper six bits of the program counter are incremented by executing an XPAGE instruction As a
21. Reserved Resume 4 Resume 3 Resume 2 Resume 1 Read Write R R R R Reset 0 0 0 0 0 0 0 0 Figure 16 9 Hub Ports Resume Status Register Bit 0 3 Resume x where x 1 4 When set to 1 Port x requesting to be resumed set by hardware default state is O Bit 4 7 Reserved Set to 0 Resume from a selectively suspended port with the hub not in suspend typically involves the following actions 1 Hardware detects the Resume drives a K to the port and generates the hub interrupt The corresponding bit in the Resume Status Register Ox4E reads 1 in this case 2 Firmware responds to hub interrupt and reads register Ox4E to determine the source of the Resume 3 Firmware begins driving K on the port for 10 ms or more through register Ox4B 4 Firmware clears the Selective Suspend bit for the port 0x4D which clears the Resume bit OxAE This ends the hardware driv en Resume but the firmware driven Resume continues To prevent traffic being fed by the hub repeater to the port during or just after the Resume firmware should disable this port 5 Firmware drives a timed SEO on the port for two low speed bit times as appropriate Firmware must disable interrupts during this SEO so the SEO pulse isn t inadvertently lengthened and appear as a bus reset to the downstream device 6 Firmware drives a J on the port for one low speed bit time then it idles the port 7 Firmware re enables the port Re
22. Restart This bit is valid as a status bit ARB Lost after master mode transactions In master mode set this bit along with the Continue and MSTR Mode bits to perform an 12C restart sequence The Pc target address for the restart must be written to the data register before setting the Continue bit To prevent false ARB Lost signals the Restart bit is cleared by hardware during the restart sequence Bit 1 Receive Stop This bit is set when the slave is in receive mode and detects a stop bit on the bus The Receive Stop bit is not set if the firmware terminates the DC transaction by not acknowledging the previous byte transmitted on the I C compatible bus e g in receive mode if firmware sets the Continue bit and clears the ACK bit Bit 0 12C Enable Setthis bit to override GPIO definition with I C compatible function on the two I C compatible pins When this bit is cleared these pins are free to function as GPIOs In I C compatible mode the two pins operate in open drain mode independent of the GPIO configuration setting Document 38 08002 Rev D Page 22 of 49 Feedback CYPRESS CY7C65113C PERFORM 13 0 Processor Status and Control Register Processor Status and Control Address OxFF Bit 7 6 5 4 3 2 1 0 Bit Name IRQ Watchdog USB Bus Power on Suspend Interrupt Reserved Run Pending Reset Reset Reset Enable Interrupt Sense Read Write R R W R W R W R W R R W R W R
23. Setup in Out ACK Mode Bits Response Intr Normal Out erroneous In 110 JO 1 Out 210 data valid updates 1 updates UC UC 1 1 1 JO JO O ACK yes 110 JO 1 Out gt 10 junk x updates updates updates UC UC 1 UC NoChange ignore yes 110 JO 1 Out x junk invalid updates 0 updates UC UC 1 UC NoChange ignore yes 110 JO 1 Jin x UC x UC UC UC UC UC JUC JUC NoChange ignore no STALL 0 110 O 1 Jin x UC x UC UC UC UC UC UC JUC NoChange Stall no STALLE 1 NAK Out erroneous In 1 10 JO 10 Out lt 10 UC valid UC UC UC UC UC 1 UC NoChange NAK yes 1 10 JO JO Out gt 10 UC x UC UC UC UC UC JUC JUC NoChange ignore no 1 10 JO JO Out x UC invalid UC UC UC UC UC JUC JUC NoChange ignore no 1 10 JO JO Jin x UC x UC UC UC UC UC JUC JUC NoChange ignore no Isochronous endpoint Out 0 1 10 1 Out x updates updates updates updates updates UC UC 1 1 NoChange RX yes 0 1 O 1 Jin x UC x UC UC UC UC UC JUC JUC NoChange ignore no IN ENDPOINT Properties of Incoming Packet Changes made by SIE to Internal Registers and Mode Bits Mode Bits token count butter dval DTOG DVAL COUNT Setup in Out ACK Mode Bits Response Intr Normal In erroneous Out 1 1 JO 1 Out x UC x UC UC UC UC UC JUC JUC NoChange ignore no STALL 0 1 1 JO 1 Out x UC x UC UC UC UC UC JUC JUC NoChange stall no surr vr EE EET EE VEE Luces y lt 1 1 10 1 in x UC x UC UC UC UC 1 UC 1 1 1 0 O ACK back yes NAK In erroneous Out 1
24. Status and Control Register is set to 00010001 which indicates a POR bit 4 set has occurred and no interrupts are pending bit 7 clear During the 96 ms suspend at start up explained in Section 7 1 a Watchdog Reset also occurs unless this suspend is aborted by an upstream SEO before 8 ms If a WDR occurs during the power up suspend interval firmware reads 01010001 from the Status and Control Register after power up Normally the POR bit should be cleared so a subsequent WDR can be clearly identified If an upstream bus reset is received before firmware examines this register the Bus Reset bit may also be set During a Watchdog Reset the Processor Status and Control Register is set to 01XX0001 which indicates a Watchdog Reset bit 6 set has occurred and no interrupts are pending bit 7 clear The Watchdog Reset does not effect the state of the POR and the Bus Reset Interrupt bits Document 38 08002 Rev D Page 23 of 49 Feedback CYPRESS PERFORM Interrupts CY7C65113C 14 0 Interrupts are generated by GPIO pins internal timers I2C compatible operation internal USB hub and USB traffic conditions All interrupts are maskable by the Global Interrupt Enable Register and the USB End Point Interrupt Enable Register Writing a T to a bit position enables the interrupt associated with that bit position Global Interrupt Enable Register Address 0X20 Bit 7 6 5 4 3 2 1 0 Bit Name Reserved JC Interrup
25. an ACK is transferred These registers are only unlocked by a CPU read of the register which should be done by the firmware only after the transaction is complete This represents about a 1 us window in which the CPU is locked from register writes to these USB registers Normally the firmware should perform a register read at the beginning of the Endpoint ISRs to unlock and get the mode register information The interlock on the Mode and Count registers ensures that the firmware recognizes the changes that the SIE might have made during the previous transaction Note that the setup bit of the mode register is NOT locked This means that before writing to the mode register firmware must first read the register to make sure that the setup bit is not set which indicates a setup was received while processing the current USB request This read will of course unlock the register So care must be taken not to overwrite the register elsewhere Document 38 08002 Rev D Page 40 of 49 Feedback E YPRESS PERFORM CY7C65113C Table 18 3 Details of Modes for Differing Traffic Conditions see Table 18 2 for the decode legend SETUP if accepting SETUPs Properties of Inc oming Packet Changes made by SIE to Internal Registers and Mode Bits
26. no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Feedback CYPRESS PERFORM Document History Page CY7C65113C Document Title CY7C65113C USB Hub with Microcontroller Document Number 38 08002 REV ECN NO Issue Date Orig of Change Description of Change 109965 02 22 02 SZV Change from Spec number 38 00590 to 38 08002 A B 120372 124522 12 17 02 03 13 03 MON MON Added register bit definitions Added default bit state of each register Corrected the Schematic location of the pull up on D Corrected the Logical Diagram removed the extra GPIO Port 1 Added register summary Modified Figure 17 5 more labeling Removed information on the availability of the
27. off except the GPIO interrupt logic and the USB receiver The clock oscillator and PLL as well as the free running and Watchdog timers are shut down Only the occurrence of an enabled GPIO interrupt or non idle bus activity at a USB upstream or downstream port wakes the part out of suspend The Run bit in the Processor Status and Control Register must be set to resume a part out of suspend The clock oscillator restarts immediately after exiting suspend mode The microcontroller returns to a fully functional state 1 ms after the oscillator is stable The microcontroller executes the instruction following the I O write that placed the device into suspend mode before servicing any interrupt requests The GPIO interrupt allows the controller to wake up periodically and poll system components while maintaining a very low average power consumption To achieve the lowest possible current during suspend mode all I O should be held at Vcc or Gnd Note This also applies to internal port pins that may not be bonded in a particular package Typical code for entering suspend is shown below All GPIO set to low power state no floating pins Enable GPIO interrupts if desired for wake up mov a 09h Set suspend and run bits iowr FFh Write to Status and Control Register Enter suspend wait for USB activity or GPIO Interrupt nop This executes before any ISR Remaining code for exiting suspend routine Document 38 08002 Rev D Page 16 of
28. otherwise be active and Ke register contents may be changed by the hardware during the transaction until the Ke interrupt occurs 15 0 USB Overview The USB hardware includes a USB Hub repeater with one upstream and up to seven downstream ports The USB Hub repeater interfaces to the microcontroller through a full speed serial interface engine SIE An external series resistor of Re must be placed in series with all upstream and downstream USB outputs in order to meet the USB driver requirements of the USB specification The CY7C65113C microcontroller can provide the functionality of a compound device consisting of a USB hub and permanently attached functions 15 1 USB Serial Interface Engine SIE The SIE allows the CY7C65113C microcontroller to communicate with the USB host through the USB repeater portion of the hub The SIE simplifies the interface between the microcontroller and USB by incorporating hardware that handles the following USB bus activity independently of the microcontroller Bit stuffing unstuffing Checksum generation checking ACK NAK STALL Token type identification Address checking Firmware is required to handle the following USB interface tasks Coordinate enumeration by responding to SETUP packets Fill and empty the FIFOs Suspend Resume coordination Verify and select DATA toggle values 15 2 USB Enumeration The internal hub and any compound device function are enumerated under firmware control T
29. port is enabled immediately When a USB device disconnection has been detected firmware must update status bits in the hub change status data structure that is polled periodically by the USB host In suspended mode a connect or disconnect event generates an interrupt if the hub interrupt is enabled even if the port is disabled Hub Ports Enable Register Address 0x49 Bit 7 6 5 4 3 2 1 0 Bit Name Reserved Reserved Reserved Reserved Port4 Enable Port 3 Enable Port 2 Enable Port 1 Enable Read Write R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Figure 16 3 Hub Ports Enable Register Bit 0 3 Port x Enable where x 1 4 Set to 1 if Port x is enabled Set to 0 if Port x is disabled Bit 4 7 Reserved Set to 0 The Hub Ports Enable register is cleared to zero by reset or bus reset to disable all downstream ports as the default condition A port is also disabled by internal hub hardware enable bit cleared if babble is detected on that downstream port Babble is defined as Any non idle downstream traffic on an enabled downstream port at EOF2 Any downstream port with upstream connectivity established at EOF2 i e no EOP received by EOF2 16 3 Hub Downstream Ports Status and Control Data transfer on hub downstream ports is controlled according to the bit settings of the Hub Downstream Ports Control Register Figure 16 4 Each downstream port is controlled by two b
30. read only if the read operation occurs after the UPDATE The firmware needs to perform a register read as a part of the endpoint ISR processing to unlock the effected registers The locking mechanism on mode and counter registers ensures that the firmware recognizes the changes that the SIE might have made since the previous IO read of that register UPDATE 1 Endpoint Mode Register All the bits are updated except the SETUP bit of the endpoint 0 mode register 2 Counter Registers All bits are updated 3 Interrupt If an interrupt is to be generated as a result of the transaction the interrupt flag for the corresponding endpoint is set at this time For details on what conditions are required to generate an endpoint interrupt refer to Table 18 2 4 The contents of the updated endpoint 0 mode and counter registers are locked except the SETUP bit of the endpoint O mode register which was locked earlier Document 38 08002 Rev D Page 37 of 49 Feedback ps CYPRESS CY7C65113C PERFORM 1 IN Token Host To Device Device To Host Host To Device S A Y C N K C Token Packet Data Packet Hand Shake Packet Host To Device Device To Host UPDATE mm NAK STALL D H Token Packet Data Packet E O UPDATE V S 2 OUT or SETUP Token without CRC error T Host To Device Host To Device Device To Host C Pe E ACK NAK STAL Token Packet Data Packet A Hand Sh
31. result the last instruction executed within a 256 byte page of sequential code should be an XPAGE instruction The assembler directive XPAGEON causes the assembler to insert XPAGE instructions automatically Because instructions can be either one or two bytes long the assembler may occasionally need to insert a NOP followed by an XPAGE to execute correctly The address of the next instruction to be executed the carry flag and the zero flag are saved as two bytes on the program stack during an interrupt acknowledge or a CALL instruction The program counter carry flag and zero flag are restored from the program stack during a RETI instruction Only the program counter is restored during a RET instruction The program counter cannot be accessed directly by the firmware The program stack can be examined by reading SRAM from location 0x00 and up Document 38 08002 Rev D Page 11 of 49 Feedback CYPRESS PERFORM 5 1 1 Program Memory Organization after reset 14 bit PC p Address 0x0000 0x0002 0x0004 0x0006 0x0008 0x000A 0x000C 0x000E 0x0010 0x0012 0x0014 0x0016 0x0018 0x001A Ox1FDF CY7C65113C Program execution begins here after a reset USB Bus Reset interrupt vector 128 us timer interrupt vector 1 024 ms timer interrupt vector USB address A endpoint 0 interrupt vector USB address A endpoint 1 interrupt vector USB address A end
32. semi suspend state During the semi suspend state which is different from the suspend state defined in the USB specification the oscillator and all other blocks of the part are functional except for the CPU This semi suspend time ensures that both a valid Vcc level is reached and that the internal PLL has time to stabilize before full operation begins When the Vcc has risen above approximately 2 5V and the oscillator is stable the POR is deasserted and the on chip timer starts counting The first 1 ms of suspend time is not interruptible and the semi suspend state continues for an additional 95 ms unless the count is bypassed by a USB Bus Reset on the upstream port The 95 ms provides time for Vcc to stabilize at a valid operating voltage before the chip executes code If a USB Bus Reset occurs on the upstream port during the 95 ms semi suspend time the semi suspend state is aborted and program execution begins immediately from address 0x0000 In this case the Bus Reset interrupt is pending but not serviced until firmware sets the USB Bus Reset Interrupt Enable bit Bit 0 Figure 14 1 and enables interrupts with the El command The POR signal is asserted whenever Vcc drops below approximately 2 5V and remains asserted until Vcc rises above this level again Behavior is the same as described above Document 38 08002 Rev D Page 15 of 49 Feedback CYPRESS CY7C65113C PERFORM 7 2 Watchdog Reset The WDR occurs when the in
33. the byte If more bytes are to be sent firmware writes the next byte into the Data Register and then sets the Xmit MODE and Continue Busy bits as required 4 In master transmit mode after the master sends a byte of data Firmware should load the Data Register if necessary and set the Xmit MODE MSTR MODE and Continue Busy bits appropriately Clearing the MSTR MODE bit issues a stop signal to the I C compatible bus and return to the idle state 5 In master receive mode after the master receives a byte of data Firmware should read the data and set the ACK and Continue Busy bits appropriately for the next byte Clearing the MSTR MODE bit at the same time causes the master state machine to issue a stop signal to the I C compatible bus and leave the I2C compatible hardware in the idle state 6 When the master loses arbitration This gondition clears the MSTR MODE bit and sets the ARB Lost Restart bit immediately and then waits for a stop signal on the I c compatible bus to generate the interrupt The Continue Busy bit is cleared by hardware prior to interrupt conditions 1 to 4 Once the Data Register has been read or written firmware should configure the other control bits and set the Continue Busy bit for subsequent transactions Following an interrupt from master mode firmware should perform only one write to the Status and Control Register that sets the Continue Busy bit without checking the value of the Continue Busy bit The Busy bit may
34. this endpoint 0 mode register The bit must be cleared by firmware as part of the USB processing Note 4 n 5 endpoint mode USB Status And Control Register Bits 7 6 are set to 0 1 or 1 1 Register 0x42 serves as non control endpoint 3 and has the format for non control endpoints shown in Figure 17 3 Document 38 08002 Rev D Page 35 of 49 Feedback CYPRESS CY7C65113C PERFORM Bits 6 0 of the endpoint 0 mode register are locked from CPU write operations whenever the SIE has updated one of these bits which the SIE does only at the end of the token phase of a transaction SETUP Data ACK OUT Data ACK or IN Data ACK The CPU can unlock these bits by doing a subsequent read of this register Only endpoint 0 mode registers are locked when updated The locking mechanism does not apply to the mode registers of other endpoints Because of these hardware locking features firmware must perform an IORD after an IOWR to an endpoint 0 register This verifies that the contents have changed as desired and that the SIE has not updated these values While the SETUP bit is set the CPU cannot write to the endpoint zero FIFOs This prevents firmware from overwriting an incoming SETUP transaction before firmware has a chance to read the SETUP data Refer to Table 17 1 for the appropriate endpoint zero memory locations The Mode bits bits 3 0 control how the endpoint responds to USB bus traffic The mode bit enc
35. updates UC UC 1 UC NoChange ignore yes 1 10 1 1 Ou x junk invalid updates 0 updates UC UC 1 UC NoChange ignore yes 110 1 1 Jin x UC x UC UC UC UC 1 UC 1 NoChange TXO yes NAK Out premature status In 1 10 1 10 Ou lt 10 UC valid UC UC UC UC UC 1 UC NoChange NAK yes 1 10 1 O Ou gt 10 UC x UC UC UC UC UC JUC JUC NoChange ignore no 1 10 1 O Ou x UC invalid UC UC UC UC UC JUC JUC NoChange ignore no 110 1 O Jin x UC x UC UC UC UC 1 UC 1 NoChange TXO yes Status In extra Out 0 1 11 JO Ou lt 10 UC valid UC UC UC UC UC 1 UC 0 10 11 1 Stall yes O 1 1 JO Out gt 10 UC x UC UC UC UC UC UC JUC NoChange ignore no O 1 1 JO Out x UC invalid UC UC UC UC UC JUC JUC NoChange ignore no O 1 1 JO Jin x UC x UC UC UC UC 1 UC 1 NoChange TXO yes CONTROL READ Properties of Incoming Packet Changes made by SIE to Internal Registers and Mode Bits Mode Bits token count butter dval DTOG DVAL COUNT Setup in Out ACK Mode Bits Response Intr Normal In premature status Out 1 11 1 1 Out 2 UC valid 1 1 updates UC UC 1 1 NoChange ACK yes 1 11 1 1 Out 2 UC valid 0 1 updates UC UC 1 UC 0 O 1 1 Stall yes 1 11 1 1 Out 1 2 UC valid updates 1 updates UC UC 1 UC O O 1 1 Stall yes 1 11 1 1 Out gt 10 UC x UC UC UC UC UC JUC JUC NoChange ignore no 1 11 1 1 Out x UC invalid UC UC UC UC UC JUC JUC NoChange ignore no 1 1 1 1 jin x UC x UC UC UC UC 1 UC 1 1 1 1 0 ACK back yes Nak In premature status
36. used to measure the duration of an event under firmware control by reading the timer at the start of the event and after the event is complete The difference between the two readings indicates the duration of the event in microseconds The upper four bits of the timer are latched into an internal register when the firmware reads the lower eight bits A read from the upper four bits actually reads data from the internal register instead of the timer This feature eliminates the need for firmware to try to compensate if the upper four bits increment immediately after the lower eight bits are read Interrupts The microcontroller supports ten maskable interrupts in the vectored interrupt controller Interrupt sources include the USB Bus Reset interrupt the 128 us bit 6 and 1 024 ms bit 9 outputs from the free running timer five USB endpoints the USB hub the GPIO ports and the I C compatible master mode interface The timer bits cause an interrupt if enabled when the bit toggles from LOW 0 to HIGH 1 The USB endpoints interrupt after the USB host has written data to the endpoint FIFO or after the USB controller sends a packet to the USB host The GPIO ports also have a level of masking to select which GPIO inputs can cause a GPIO interrupt Input transition polarity can be programmed for each GPIO port as part of the port configuration The interrupt polarity can be rising edge 0 to 1 or falling edge 1 to 0 USB
37. when a GPIO port is configured with CMOS outputs interrupts from that port are disabled During reset all of the bits in the GPIO Configuration Register are written with 0 to select Hi Z mode for all GPIO ports as the default configuration Document 38 08002 Rev D Page 18 of 49 Feedback CYPRESS PERFORM Table 9 1 GPIO Port Output Control Truth Table and Interrupt Polarity CY7C65113C Port Config Bit 1 Port Config Bit0 Data Register Output Drive Strength Interrupt Enable Bit Interrupt Polarity 1 1 0 Output LOW 0 Disabled 1 Resistive 1 Falling Edge 1 0 0 Output LOW 0 Disabled 1 Output HIGH 1 Disabled 0 1 0 Output LOW 0 Disabled 1 Hi Z 1 Falling Edge 0 0 0 Output LOW 0 Disabled 1 Hi Z 1 Rising Edge Q1 Q2 and Q3 discussed below are the transistors referenced in Figure 9 1 The available GPIO drive strength are Output LOW Mode The pin s Data Register is set to 0 Writing 0 to the pin s Data Register puts the pin in output LOW mode regardless of the contents of the Port Configuration Bits 1 0 In this mode Q1 and Q2 are OFF Q3 is ON The GPIO pin is driven LOW through Q3 Output HIGH Mode The pin s Data Register is set to 1 and the Port Configuration Bits 1 0 is set to 10 In this mode Q1 and Q3 are OFF Q2 is ON The GPIO is pulled up through Q2 The GPIO pin is capable of sourcing of current R
38. 1 Config Bit 0 z o o o a o z 0x09 HAPI I7C Configuration I7C Position Reserved Reserved Reserved Reserved Reserved C Port Reserved BBBBBBBB 00000000 ze Width z 0x10 USB Device Address A Device Device Device Device Device Device Device Device BBBBBBBB 00000000 o Address A Address A Address A Address A Address A Address A Address A Address A 3 Enable Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 5 0x11 EP AO Counter Data 0 1 Data Valid Byte Count Byte Count Byte Count Byte Count Byte Count Byte Count BBBBBBBB 00000000 o Register Toggle Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 z 0x12 EP AO Mode Register EndpointO EndpointO EndpointO ACK Mode Bit 3 Mode Bit2 Mode Bit 1 Mode Bit 0 BBBBBBBB 00000000 R SETUP IN OUT Cat Received Received Received e 0x13 EP A1 Counter Data 0 1 Data Valid Byte Count Byte Count Byte Count Byte Count Byte Count Byte Count BBBBBBBB 00000000 z Register Toggle Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 E 0x14 EP A1 Mode Register STALL ACK Mode Bit 3 Mode Bit2 Mode Bit 1 Mode Bit 0 BBBBBBBB 00000000 ei 0x15 EP A2 Counter Data 0 1 Data Valid Byte Count Byte Count Byte Count Byte Count Byte Count Byte Count BBBBBBBB 00000000 Register Toggle Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 5 0x16 EP A2 Mode Register STALL ACK Mode Bit 3 Mode Bit 2 Mode Bit 1 Mode Bit 0 BBBBBBBB 00000000 a a z ui d Ox1F USB Status and Control Endpoint Endpoint D D Bus Activity Control Control Control
39. A typical 25 27 26 XTAL N IN 2 6 MHz crystal or external clock input XTALour OUT 1 6 MHz crystal out Vpp 19 Programming voltage supply tie to ground during normal operation Vece 28 Voltage supply GND 4 20 Ground VREF IN 3 External 3 3V supply voltage for the downstream differential data output buffers and the D pull up Document 38 08002 Rev D Page 8 of 49 Feedback CYPRESS CY7C65113C PERFORM 4 2 I O Register Summary I O registers are accessed via the I O Read IORD and I O Write IOWR IOWX instructions IORD reads data from the selected port into the accumulator IOWR performs the reverse it writes data from the accumulator to the selected port Indexed I O Write IOWX adds the contents of X to the address in the instruction to form the port address and writes data from the accumulator to the specified port Specifying address 0 e g IOWX Oh means the I O register is selected solely by the contents of X All undefined registers are reserved Do not write to reserved registers as this may cause an undefined operation or increased current consumption during operation When writing to registers with reserved bits the reserved bits must be written with 0 Table 4 2 I O Register Summary Register Name I O Address Read Write Function Page Port 0 Data 0x00 R W
40. BBRRBBBB 0xx0000 o 8 Size Mode Upstream Upstream Bit 2 Bit 1 Bit 0 5 0x20 Global Interrupt Enable Reserved c GPIO Reserved USB Hub 1 024 ms 128 us USB Bus BBBBBBB 0000000 E Interrupt Interrupt Interrupt Interrupt Interrupt RESET 5 Enable Enable Enable Enable Enable Interrupt x Enable H 0x21 Endpoint Interrupt Reserved Reserved Reserved EPB1 EPBO EPA2 EPA1 EPAO BBBBB 00000 z Enable Interrupt Interrupt Interrupt Interrupt Interrupt Enable Enable Enable Enable Enable c 0x24 Timer LSB Timer Bit 7 Timer Bit6 Timer Bit 5 Timer Bit4 Timer Bit 3 Timer Bit 2 Timer Bit 1 Timer Bit 0 RRRRRRRR 00000000 ui z 0x25 Timer MSB Reserved Reserved Reserved Reserved Timer Bit 11 Timer Bit 10 Time Bit9 Timer Bit 8 ITIT 0000 E 0x28 DC Control and Status MSTR Continue Xmit ACK Addr ARB Lost Received Pc BBBBBBBB 00000000 9 Mode Busy Mode Restart Stop Enable B 0x29 17C Data PC Data7 C Data6 C Data5 C Data 4 PCData3 lC Data 2 lC Data 1 ICDataO BBBBBBBB XXXXXXXX z 0x40 USB Device Address B Device Device Device Device Device Device Device Device BBBBBBBB 00000000 o Address B Address B Address B Address B Address B Address B Address B Address B s Enable Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 5 0x41 EP BO Counter Register Data 0 1 Data Valid Byte Count Byte Count Byte Count Byte Count Byte Count Byte Count BBBBBBBB 00000000 o Toggle Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 z 0x42 EP BO Mode Regis
41. C compatible function must be separately enabled as described in Section 12 0 Document 38 08002 Rev D Page 20 of 49 Feedback CYPRESS CY7C65113C PERFORM 12 0 12C compatible Controller The I2C compatible block provides a versatile two wire communication with external devices supporting master slave and multi master modes of operation The I2C compatible block functions by handling the low level signaling in hardware and issuing interrupts as needed to allow firmware to take appropriate action during transactions While waiting for firmware response the hardware keeps the I2C compatible bus idle if necessary The I2C compatible block generates an interrupt to the microcontroller at the end of each received or transmitted byte when a stop bit is detected by the slave when in receive mode or when arbitration is lost Details of the interrupt responses are given in Section 14 8 The I2C compatible interface consists of two registers an C Data Register Figure 12 1 and an I C Status and Control Register Figure 12 2 The 1 C Data Register is implemented as separate read and write registers Generally the I C Status and Control Register should only be monitored after the 12C interrupt as all bits are valid at that time Polling this register at other times could read misleading bit status if a transaction is underway The 12C clock SCL is connected to bit 0 of GPIO port 1 and the I C SDA data is connected to bit 1 GP
42. EERE EESE EEEE EEEn 25 14 2 InterruptlLatenoy eerte ere c vec d E OR ER E cash D eR Y E d 26 14 3 USB Bus Reset Interrupt cece cece cece etter nee en annan nn nnne nnne 26 14 4 Timer Interr pt E 26 14 5 USB Endpoint Interrupts ccc eee eect eee eee eee mne nennen nnnm rn en nennen 27 14 6 USB Hub Interr pt iir rem e een edere e do n Rn CER EK ep rd Ri d eta D E E e d ERR RR 27 14 7 GPIO Interrupt ee eee 27 14 8 IC Interrupt EK BE MEN ND EL 27 15 0 USB OVERVIEW dnne 28 15 1 USB Serial Interface Engine SIE EE 28 15 2 USB Enumeratlon 5t ree nex nk ek Rd KR EX ERR X E EE EE X KR e e E Ru RR RR RR 28 Document 38 08002 Rev D Page 2 of 49 Feedback CYPRESS PERFORM 150 USB HUB E 16 1 Connecting Disconnecting a USB Device seeeeeessssss 16 2 Enabling Disabling a USB Device rrmnsrvrnnennnrernsnsnnnnrenvenennnnnnnnvnenerennnn 16 3 Hub Downstream Ports Status and Control mrrrnnnnnnnnnnnrnnrrnnnnn rn rnnnr 16 4 Downstream Port Suspend and Resume rrnnnnnnnnnnnnnnnnnnnnnnnnnnsnnnnnnnnene 16 5 USB Upstream Port Status and Control 17 0 USB SERIAL INTERFACE ENGINE OPERATION eee 17 1 SR e moi 17 2 USB Device Endpoint ssssssse Hem 17 3 USB Control Endpoint Mode Registers A 17 4 USB Non control Endpoint Mode Registers ssesssssss 17 5 USB Endpoint Cou
43. IO port 1 The port selection is determined by settings in the Ic Port Configuration Register Section 11 0 Once the GE compatible functionality is enabled by setting the I C Enable bit of the IC Status and Control Register bit O Figure 12 2 the two LSB 1 0 of the corresponding GPIO port i is placed in Open Drain mode regardless of the settings of the GPIO Configuration Register In Open Drain mode the GPIO pin outputs Low if the pin s Data Register is 0 and the pin is in Hi Z mode if the pin s Data Register is 1 The electrical characteristics of the I C compatible interface is the same as that of GPIO port 1 Note that the lo max is 2 mA Vo 2 0V for port 1 All control of the I C clock SCL and data SDA lines is performed by the I C compatible block 12C Data Address 0x29 Bit 4 7 6 5 4 3 2 1 0 Bit Name IC Data7 IC Data6 C Data 5 IC Data4 17C Data3 IPC Data2 lC Data 1 I2C Data 0 Read Write R W R W R W R W R W R W R W R W Reset X X X X X X X X Figure 12 1 I C Data Register Bits 7 0 IC Data Contains the 8 bit data on the I2C Bus I C Status and Control Address 0x28 Bit 4 7 6 5 4 3 2 1 0 Bit Name MSTR Mode Continue Bu Xmit Mode ACK Addr ARB Received I C Enable Sy Lost Restart Stop Read Write R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Figure 12 2 I C Status and Control Register The IC Sta
44. O OxA8 8 EPA4 OxD8 8 EPA3 0xA8 8 EPBO OxEO 8 EPB1 0xBO 8 EPA3 OxEO 8 EPA4 0xBO 8 EPA2 OxE8 8 EPAO 0xB8 8 EPA2 OxE8 8 EPAO 0xB8 8 EPA1 OxFO 8 EPA1 OxCO 32 EPA1 OxFO 8 EPA1 0xCO 32 EPAO OxF8 8 EPA2 OxEO 32 EPAO OxF8 8 EPA2 OxEO 32 When the SIE writes data to a FIFO the internal data bus is driven by the SIE not the CPU This causes a short delay in the CPU operation The delay is three clock cycles per byte For example an 8 byte data write by the SIE to the FIFO generates a delay of 2 us 3 cycles byte 83 33 ns cycle 8 bytes 17 3 USB Control Endpoint Mode Registers All USB devices are required to have a control endpoint 0 EPAO and EPBO that is used to initialize and control each USB address Endpoint 0 provides access to the device configuration information and allows generic USB status and control accesses Endpoint 0 is bidirectional to both receive and transmit data The other endpoints are unidirectional but selectable by the user as IN or OUT endpoints The endpoint mode registers are cleared during reset When USB Status And Control Register Bits 6 7 are set to 0 0 or 1 0 the endpoint zero EPAO and EPBO mode registers use the format shown in Figure 17 2 USB Device Endpoint Zero Mode A0 B0 Addresses 0x12 A0 and 0x42 B0 Bit 7 6 5 4 3 2 1 0 Bit Name Endpoint 0 Endpoint O Endpoint 0 ACK Mode Bit 3 Mode Bit2 Mode Bit 1 Mode Bit 0 SETUP IN OUT Received Received Received Read Writ
45. OWR attempting to put the part into suspend is ignored if USB bus activity is present See Section 8 0 for more details on suspend mode operation Bit 4 Power on Reset The Power on Reset is set to 1 during a power on reset The firmware can check bits 4 and 6 in the reset handler to determine whether a reset was caused by a power on condition or a Watchdog timeout A POR event may be followed by a Watchdog reset before firmware begins executing as explained below Bit 5 USB Bus Reset Interrupt The USB Bus Reset Interrupt bit is set when the USB Bus Reset is detected on receiving a USB Bus Reset signal on the upstream port The USB Bus Reset signal is a single ended zero SEO that lasts from 12 to 16 us An SEO is defined as the condition in which both the D line and the D line are LOW at the same time Bit 6 Watchdog Reset The Watchdog Reset is set during a reset initiated by the Watchdog Timer This indicates the Watchdog Timer went for more than tyyatck 8 ms minimum between Watchdog clears This can occur with a POR event as noted below Bit 7 IRQ Pending The IRQ pending when set indicates that one or more of the interrupts has been recognized as active An interrupt remains pending until its interrupt enable bit is set Figure 14 1 Figure 14 2 and interrupts are globally enabled At that point the internal interrupt handling sequence clears this bit until another interrupt is detected as pending During power up the Processor
46. Out 1 11 1 JO Out 2 UC valid 1 1 updates UC UC 1 1 NoChange ACK yes 1 1 1 JO Out 2 UC valid 0 1 updates UC UC 1 UC O O 1 1 Stall yes 1 11 1 JO Out 1 2 UC valid updates 1 updates UC UC 1 UC O O 1 1 Stall yes 1 1 1 JO Out gt 10 UC x UC UC UC UC UC JUC JUC NoChange ignore no 1 1 1 JO Out x UC invalid UC UC UC UC UC UC UC NoChange ignore no 1 1 1 JO Jin x UC x UC UC UC UC 1 UC JUC NoChange NAK yes Status Out extra In 0 10 1 JO Out 2 UC valid 1 1 updates UC UC 1 1 NoChange ACK yes 0 10 1 JO Out UC valid 0 1 updates UC UC 1 UC 0 O 1 1 Stall yes Document 38 08002 Rev D Page 41 of 49 Feedback 7 CYPRESS CY7C65113C PERFORM Table 18 3 Details of Modes for Differing Traffic Conditions see Table 18 2 for the decode legend continued 0 10 1 JO Out 1 2 UC valid updates 1 updates UC UC 1 UC O O 1 1 Stall yes 0 10 11 JO Out gt 10 UC x UC UC UC UC UC UC JUC NoChange ignore no 0 10 1 JO Out x UC invalid UC UC UC UC 1 UC JUC NoChange ignore no 0 10 1 O jin x UC x UC UC UC UC 1 UC UC 0 O 1 1 Stall yes OUT ENDPOINT Properties of Incoming Packet Changes made by SIE to Internal Registers and Mode Bits Mode Bits token count buffer dval DTOG DVAL COUNT
47. P p gt user selected Data Stack Growth User variables USB FIFO space for up to two Addresses and five endpoints OxFF Notes 1 Refer to Section 5 5 for a description of DSP 2 Endpoint sizes are fixed by the Endpoint Size Bit I O register Ox1F Bit 7 See Table 17 1 Document 38 08002 Rev D Page 13 of 49 Feedback CYPRESS CY7C65113C 5 5 8 bit Data Stack Pointer DSP The Data Stack Pointer DSP supports PUSH and POP instructions that use the data stack for temporary storage A PUSH instruction pre decrements the DSP then writes data to the memory location addressed by the DSP A POP instruction reads data from the memory location addressed by the DSP then post increments the DSP During a reset the DSP is reset to 0x00 A PUSH instruction when DSP equals 0x00 writes data at the top of the data RAM address OxFF This writes data to the memory area reserved for USB endpoint FIFOs Therefore the DSP should be indexed at an appropriate memory location that does not compromise the Program Stack user defined memory variables or the USB endpoint FIFOs For USB applications the firmware should set the DSP to an appropriate location to avoid a memory conflict with RAM dedicated to USB FIFOs The memory requirements for the USB endpoints are described in Section 17 2 Example assembly instructions to do this with two device addresses FIFOs begin at 0xD8 are shown below MOV A 20h Move 20 hex into Accumula
48. SCLK jt SDATA USB EZ pt gt Transceiver a D 0 Upstream Transceiver gt D 0 USB Port Downstream USB Ports USB USB gt Transceiver Repeater mE d USB gt Transceiver tp lt gt gt USB La e Transceiver 2C compatible interface enabled by firmware through P1 1 0 ra D 1 a D 1 a D 2 lt gt D 2 a D 3 a D 3 te D 4 Lab D 4 Power management under firmware control using GPIO pins Document 38 08002 Rev D Page 7 of 49 Feedback CYPRESS CY7C65113C PERFORM 3 0 Pin Configurations Top View CY7C65113C 28 pin SOIC XTALOUT 1 Voc XTALIN 2 P1 1 VREF 3 P1 0 GND 4 P1 2 D 0 5 DD D 0 6 D 3 D 1 7 D 4 D 1 8 D 4 DAS 9 GND D 2 Vpp PO 7 PO O PO 5 PO 2 PO 3 PO 4 PO 1 POLS 4 0 Product Summary Tables 4 1 Pin Assignments Table 4 1 Pin Assignments Name UO 28 pin Description D 0 D 0 lO 15 6 Upstream port USB differential data D 1 D 1 lO 17 8 Downstream Port 1 USB differential data D 2 D 2 I O 19 10 Downstream Port 2 USB differential data D 3 D 3 lO 23 24 Downstream Port 3 USB differential data D 4 D 4 lO 121 22 Downstream Port 4 USB differential data PO I O P1 7 0 GPIO Port 0 capable of sinking 7 mA typical 11 15 12 16 13 17 14 18 P1 I O P1 2 0 GPIO Port 1 capable of sinking 7 m
49. TUP IN and OUT These columns shows the SIE s response to the host on receiving a SETUP IN and OUT token depending on the mode set in the Endpoint Mode Register A Check on the OUT token column implies that on receiving an OUT token the SIE checks to see whether the OUT packet is of zero length and has a Data Toggle DTOG set to 1 If the DTOG bit is set and the received OUT Packet has zero length the OUT is ACKed to complete the transaction If either of this condition is not met the SIE will respond with a STALLL or just ignore the transaction A TX Count entry in the IN column implies that the SIE transmit the number of bytes specified in the Byte Count bits 3 0 of the Endpoint Count Register to the host in response to the IN token received A TXO Byte entry in the IN column implies that the SIE transmit a zero length byte packet in response to the IN token received from the host An Ignore in any of the columns means that the device will not send any handshake tokens no ACK to the host An Accept in any of the columns means that the device will respond with an ACK to a valid SETUP transaction to the host Note 6 STALL bit is bit 7 of the USB Non control Device Endpoint Mode registers For more information refer to Section 17 4 Document 38 08002 Rev D Page 39 of 49 Feedback CY7C65113C Some Mode Bits are automatically changed by the SIE in response to certain USB transactions For exam
50. ake SETUP UPDATE Packet 3 OUT or SETUP Token with CRC error Host To Device Host To Device Token Packet Data Packet UPDATE only if FIFO is written Figure 17 5 Token Data Packet Flow Diagram Document 38 08002 Rev D Page 38 of 49 Feedback CYPRESS CY7C65113C PERFORM 18 0 USB Mode Tables Table 18 1 USB Register Mode Encoding Mode Moder Bits SETUP IN OUT Comments Disable 0000 ignore ignore ignore Ignore all USB traffic to this endpoint Nak In Out 0001 accept NAK NAK Forced from Setup on Control endpoint from modes other than 0000 Status Out Only 0010 accept stall check For Control endpoints Stall In Out 0011 accept stall stall For Control endpoints Ignore In Out 0100 accept ignore ignore For Control endpoints Isochronous Out 0101 ignore ignore always For Isochronous endpoints Status In Only 0110 accept TXO Byte stall For Control Endpoints Isochronous In 0111 ignore TX Count ignore For Isochronous endpoints Nak Out 1000 ignore ignore NAK Is set by SIE on an ACK from mode 1001 Ack Out Ack Out STALLl 0 1001 ignore ignore ACK On issuance of an ACK this mode is changed by SIE to 1000 NAK Ack Out STALL l 1 1001 ignore ignore stall Out Nak Out Status In 1010 accept TX0 Byte NAK jls set by SIE on an ACK from mode 1011 Ack Out Status In Out Status In Nak In 1100 ignore NAK ignore Is set by SIE
51. anization kaiini rE N AAEE AE aA 13 5 5 8 bit Data Stack Pointer DSP 1 ie tede ertet lena gba dara mee Rl EE ER SE KENEEN eNe 14 5 6 Address Modes ee 14 5 6 1 Data Immediate 0 0 eee eee enn ee eee nee rennet ee end enne enne ee enne nennen nnne nenne enne nnne 14 5 0 2 Diett RC m 14 Sno5aMSC M M 14 6 0 CLOCKING os iscsi 15 L IWE N T 15 7 1 Power on Reset deret er t i Ri ee FE RR een E d Ra Gu Rd ER ERR EA KR RR RR RR a 15 7 2 AN 0 6 0 E 16 8 0 SUSPEND ojo ste aapa KAREN ESA 16 9 0 GENERAL PURPOSE I O PORTS rnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnenene 17 9 1 GPIO Configuration Port seende Mm 18 9 2 GPIO Interrupt Enable Ports AAA 19 10 0 12 BIT FREE RUNNING TIMER rnnnnnnnnnnnnnnnnnnnnnnnvnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnene 19 11 0 PC CONFIGURATION REGISTER rrrnnrrnnvernnvennnvnnnvrnnvennnvennnnsnnvrnnvennnnsnnnnsnnnennnennnvennnesnnnennnnnnnen 20 12 0 12C COMPATIBLE CONTROLLER nennen einen nura nnn narra nna ra a nora a n rhon Sn Ua voe Rao akon NENNEN 21 13 0 PROCESSOR STATUS AND CONTROL REGISTER annnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn 23 14 0 INTERRUPTS Eea aeee asail 24 14 1 Interrupt Vectors ssssssssssse em nn norr nn nn nn eren nne sensn
52. ddress 0x1F Bit 7 6 5 4 3 2 1 0 Bit Name Endpoint Endpoint D D Bus Activity Control Control Control Size Mode Upstream Upstream Action Action Action Bit 2 Bit 1 Bit 0 Read Write R W R W R R R W R W R W R W Reset 0 0 0 0 0 0 0 0 Bits 2 0 Control Action Figure 16 10 USB Status and Control Register Set to control action as per Table 16 2 The three control bits allow the upstream port to be driven manually by firmware For normal USB operation all of these bits must be cleared Table 16 2 shows how the control bits affect the upstream port Document 38 08002 Rev D Page 33 of 49 Feedback CYPRESS CY7C65113C PERFORM Table 16 2 Control Bit Definition for Upstream Port Control Bits Control Action 000 Not Forcing SIE Controls Driver 001 Force D 0 HIGH D 0 LOW 010 Force D 0 LOW D 0 HIGH 011 Force SEO D 0 LOW D 0 LOW 100 Force D 0 LOW D 0 LOW 101 Force D 0 HiZ D 0 LOW 110 Force D 0 LOW D 0 Hiz 111 Force D 0 HiZ D 0 HiZ Bit 3 Bus Activity This is a sticky bit that indicates if any non idle USB event has occurred on the upstream USB port Firmware should check and clear this bit periodically to detect any loss of bus activity Writing a 0 to the Bus Activity bit clears it while writing a 1 preserves the current value In other words the firmware can clear the Bus Activity bit but o
53. e R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Figure 17 2 USB Device Endpoint Zero Mode Registers Bits 3 0 Mode These sets the mode which control how the control endpoint responds to traffic Bit 4 ACK This bit is set whenever the SIE engages in a transaction to the register s endpoint that completes with an ACK packet Bit 5 Endpoint O OUT Received 1 Token received is an OUT token 0 Token received is not an OUT token This bit is set by the SIE to report the type of token received by the corresponding device address is an OUT token The bit must be cleared by firmware as part of the USB processing Bit 6 Endpoint O IN Received 1 Token received is an IN token 0 Token received is not an IN token This bit is set by the SIE to report the type of token received by the corresponding device address is an IN token The bit must be cleared by firmware as part of the USB processing Bit 7 Endpoint 0 SETUP Received 1 Token received is a SETUP token 0 Token received is not a SETUP token This bit is set ONLY by the SIE to report the type of token received by the corresponding device address is a SETUP token Any write to this bit by the CPU will clear it set it to 0 The bit is forced HIGH from the start of the data packet phase of the SETUP transaction until the start of the ACK packet returned by the SIE The CPU should not clear this bit during this interval and subsequently until the CPU first does an IORD to
54. endpoint interrupt occurs but Data Valid is cleared to a zero Bit 7 Data 0 1 Toggle This bit selects the DATA packet s toggle state 0 for DATAO 1 for DATA1 For IN transactions firmware must set this bit to the desired state For OUT or SETUP transactions the hardware sets this bit to the state of the received Data Toggle bit Whenever the count updates from a SETUP or OUT transaction on endpoint 0 the counter register locks and cannot be written by the CPU Reading the register unlocks it This prevents firmware from overwriting a status update on incoming SETUP or OUT transactions before firmware has a chance to read the data Only endpoint 0 counter register is locked when updated The locking mechanism does not apply to the count registers of other endpoints 17 6 Endpoint Mode Count Registers Update and Locking Mechanism The contents of the endpoint mode and counter registers are updated based on the packet flow diagram in Figure 17 5 Two time points SETUP and UPDATE are shown in the same figure The following activities occur at each time point SETUP The SETUP bit of the endpoint 0 mode register is forced HIGH at this time This bit is forced HIGH by the SIE until the end of the data phase of a control write transfer The SETUP bit can not be cleared by firmware during this time The affected mode and counter registers of endpoint 0 are locked from any CPU writes once they are updated These registers can be unlocked by a CPU
55. eset 0 0 0 1 0 0 0 1 Figure 13 1 Processor Status and Control Register Bit 0 Run This bit is manipulated by the HALT instruction When Halt is executed all the bits of the Processor Status and Control Register are cleared to 0 Since the run bit is cleared the processor stops at the end ofthe current instruction The processor remains halted until an appropriate reset occurs power on or Watchdog This bit should normally be written as a 1 Bit 1 Reserved Bit 1 is reserved and must be written as a zero Bit 2 Interrupt Enable Sense This bit indicates whether interrupts are enabled or disabled Firmware has no direct control over this bit as writing a zero or one to this bit position has no effect on interrupts A 0 indicates that interrupts are masked off and a 1 indicates that the interrupts are enabled This bit is further gated with the bit settings of the Global Interrupt Enable Register Figure 14 1 and USB End Point Interrupt Enable Register Figure 14 2 Instructions DI El and RETI manipulate the state of this bit Bit 3 Suspend Writing a 1 to the Suspend bit halts the processor and cause the microcontroller to enter the suspend mode that signifi cantly reduces power consumption A pending enabled interrupt or USB bus activity causes the device to come out of suspend After coming out of suspend the device resumes firmware execution at the instruction following the IOWR which put the part into suspend An I
56. esistive Mode The pin s Data Register is set to 1 and the Port Configuration Bits 1 0 is set to 11 Q2 and Q3 are OFF Q1 is ON The GPIO pin is pulled up with an internal 14kQ resistor In resistive mode the pin may serve as an input Reading the pin s Data Register returns a logic HIGH if the pin is not driven LOW by an external source Hi Z Mode The pin s Data Register is set to1 and Port Configuration Bits 1 0 is set either 00 or 01 Q1 Q2 and Q3 are all OFF The GPIO pin is not driven internally In this mode the pin may serve as an input Reading the Port Data Register returns the actual logic value on the port pins 9 2 GPIO Interrupt Enable Ports Each GPIO pin can be individually enabled or disabled as an interrupt source The Port 0 1 Interrupt Enable Registers provide this feature with an Interrupt Enable bit for each GPIO pin During a reset GPIO interrupts are disabled by clearing all of the GPIO Interrupt Enable bits Writing a 1 to a GPIO Interrupt Enable bit enables GPIO interrupts from the corresponding input pin All GPIO pins share a common interrupt as discussed in Section 14 7 Port 0 Interrupt Enable Address 0x04 Bit 7 6 5 4 3 2 1 0 Bit Name PO 7 Intr PO 6 Intr PO 5 Intr DO A Intr P0 3 Intr P0 2 Intr P0 1 Intr PO 0 Intr Enable Enable Enable Enable Enable Enable Enable Enable Read Write W W W W W W W W
57. exed address mode allows the firmware to manipulate arrays of data stored in SRAM The address of the data operand is the sum of a constant encoded in the instruction and the contents of the X register Normally the constant is the base address of an array of data and the X register contains an index that indicates which element of the array is actually addressed array EQU 10h MOV X 3 MOV A X array This would have the effect of loading A with the fourth element of the SRAM array that begins at address 0x10 The fourth element would be at address 0x13 Document 38 08002 Rev D Page 14 of 49 CYPRESS CY7C65113C 6 PERFORM 0 Clocking XTALOUT E pin 1 E Lum XTALIN X oe f pin 2 To Internal PLL 77430 pF 75330 pF NM 7v Figure 6 1 Clock Oscillator On Chip Circuit The XTALIN and XTALOUT are the clock pins to the microcontroller The user can connect an external oscillator or a crystal to these pins When using an external crystal keep PCB traces between the chip leads and crystal as short as possible less than 2 cm A 6 MHz fundamental frequency parallel resonant crystal can be connected to these pins to provide a reference frequency for the internal PLL The two internal 30 pF load caps appear in series to the external crystal and would be equivalent to a 15 pF load Therefore the crystal must have a required load capacitance of about 15 18 pF A ceramic re
58. fferential i e not a SEO or SE1 Bit 4 7 Reserved Set to 0 16 4 Downstream Port Suspend and Resume The Hub Ports Suspend Register Figure 16 8 and Hub Ports Resume Status Register Figure 16 9 indicate the suspend and resume conditions on downstream ports The suspend register must be set by firmware for any ports that are selectively suspended Also this register is only valid for ports that are selectively suspended If a port is marked as selectively suspended normal USB traffic is not sent to that port Resume traffic is also prevented from going to that port unless the Resume comes from the selectively suspended port If a resume condition is detected on the port hardware reflects a Resume back to the port sets the Resume bit in the Hub Ports Resume Register and generates a hub interrupt If a disconnect occurs on a port marked as selectively suspended the suspend bit is cleared The Device Remote Wakeup bit bit 7 of the Hub Ports Suspend Register controls whether or not the resume signal is propagated by the hub after a connect or a disconnect event If the Device Remote Wakeup bit is set the hub will automatically propagate the resume signal after a connect or a disconnect event If the Device Remote Wakeup bit is cleared the hub will not propagate the resume signal The setting of the Device Remote Wakeup flag has no impact on the propagation of the resume signal after a downstream remote wakeup event The hub will au
59. he hub is enumerated first followed by any integrated compound function After the hub is enumerated the USB host can read hub connection status to determine which if any of the downstream ports need to be enumerated The following is a brief summary of the typical enumeration process of the CY7C65113C by the USB host For a detailed description of the enumeration process refer to the USB specifi cation In this description Firmware refers to embedded firmware in the CY7C65113C controller 1 The host computer sends a SETUP packet followed by a DATA packet to USB address 0 requesting the Device descriptor 2 Firmware decodes the request and retrieves its Device descriptor from the program memory tables 3 The host computer performs a control read sequence and Firmware responds by sending the Device descriptor over the USB bus via the on chip FIFOs 4 After receiving the descriptor the host sends a SETUP packet followed by a DATA packet to address 0 assigning a new USB address to the device 5 Firmware stores the new address in its USB Device Address Register for example as Address B after the no data control sequence completes Document 38 08002 Rev D Page 28 of 49 Feedback 7 CYPRESS PERFORM CY7C65113C 6 The host sends a request for the Device descriptor using the new USB address 7 Firmware decodes the request and retrieves the Device descriptor from program memory tables 8 The host performs a con
60. he memory addressed by the PSP then the PSP is incremented The second byte is stored in memory addressed by the PSP and the PSP is incremented again The overall effect is to store the program counter and flags on the program stack and increment the PSP by two The Return From Interrupt RETI instruction decrements the PSP then restores the second byte from memory addressed by the PSP The PSP is decremented again and the first byte is restored from memory addressed by the PSP After the program counter and flags have been restored from stack the interrupts are enabled The overall effect is to restore the program counter and flags from the program stack decrement the PSP by two and re enable interrupts The Call Subroutine CALL instruction stores the program counter and flags on the program stack and increments the PSP by two The Return From Subroutine RET instruction restores the program counter but not the flags from the program stack and decrements the PSP by two 5 4 1 Data Memory Organization The CY7C65113C microcontrollers provide 256 bytes of data RAM Normally the SRAM is partitioned into four areas program Stack user variables data stack and USB endpoint FIFOs The following is one example of where the program stack data stack and user variables areas could be located After reset Address 8 bit DSP 8 bit PSP 3 gt 0x00 Program Stack Growth Move DSP 8 bit DS
61. ice is disconnected from the Hub the downstream signal pair eventually floats to a single ended zero state The hub repeater recognizes a disconnect once the SEO state on a downstream port lasts from 2 0 to 2 5 us On a disconnect the corresponding bit in the Hub Ports Connect Status register is cleared and the Hub Interrupt is generated Hub Ports Connect Status Address 0x48 Bit 7 6 5 4 3 2 1 0 Bit Name Reserved Reserved Reserved Reserved Port 4 Port 3 Port 2 Port 1 Connect Connect Connect Connect Status Status Status Status Read Write R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Figure 16 1 Hub Ports Connect Status Bit 0 3 Port x Connect Status where x 1 4 When set to 1 Port x is connected When set to 0 Port x is disconnected Bit 4 7 Reserved Set to 0 The Hub Ports Connect Status register is cleared to zero by reset or USB bus reset then set to match the hardware configuration by the hub repeater hardware The Reserved bits 4 7 should always read as 0 to indicate no connection Document 38 08002 Rev D Page 29 of 49 Feedback CYPRESS CY7C65113C PERFORM Hub Ports Speed Address 0x4A Bit 7 6 5 4 3 2 1 0 Bit Name Reserved Reserved Reserved Reserved Port 4 Speed Port 3 Speed Port 2 Speed Port 1 Speed Read Write RAV R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Figure 16 2
62. imer E E Figure 10 2 Timer MSB Register eeeeessseesseeeee nennen nnne nnne innen Figure 10 3 Timer Block Diagram eeeesseeeeeeseeeeeenne nennen nnne Figure 11 1 I C Configuration Register ssssssssseeeneen Figure 121 ele EE EE Figure 12 2 PC Status and Control Register ccccssccscsssssssssssseessnsesseesees Figure 13 1 Processor Status and Control Register eseese Figure 14 1 Global Interrupt Enable Register seseseeeeeeeeess Figure 14 2 USB Endpoint Interrupt Enable Register ssss Figure 14 3 Interrupt Controller Function Diagram seeeeeeeeeeess Figure 14 4 GPIO Interrupt Structure AA Figure 16 1 Hub Ports Connect Status seessessesseeeeeenus Figure 16 2 Hub Ports Speed WEE Figure 16 3 Hub Ports Enable Register cccccccccescceeeeeeeensseneeeeseeeeseeneees Figure 16 4 Hub Downstream Ports Control Register Document 38 08002 Rev D CY7C65113C Page 3 of 49 Feedback CYPRESS CY7C65113C PERFORM Figure 16 5 Hub Ports Force Low Register aad tec pn tasa bad Roda telat tentanntanbecleanuelentenduindnts 31 Figure 16 6 Hub Ports SED Status e EE 31 Figure 16 7 Hub Ports Data Register isccscciccvsatenecstivsnticedoucndncknectiasavaxededectaemeadetudhaneecadducka dukceenevkadenabens 32 Figure 16 8 Hub Ports Suspend Register
63. instruction 5 clock cycles for the JMP instruction For example if a 5 clock cycle instruction such as JC is being executed when an interrupt occurs the first instruction of the Interrupt Service Routine executes a minimum of 16 clocks 1410 5 or a maximum of 20 clocks 5 10 5 after the interrupt is issued For a 12 MHz internal clock 6 MHz crystal 20 clock periods is 20 12 MHz 1 667 us 14 3 USB Bus Reset Interrupt The USB Controller recognizes a USB Reset when a Single Ended Zero SEO condition persists on the upstream USB port for 12 16 us SEO is defined as the condition in which both the D line and the D line are LOW A USB Bus Reset may be recognized for an SEO as short as 12 us but is always recognized for an SEO longer than 16 us When a USB Bus Reset is detected bit 5 ofthe Processor Status and Control Register Figure 13 1 is setto record this event In addition the controller clears the following registers SIE Section USB Device Address Registers 0x10 0x40 Hub Section Hub Ports Connect Status 0x48 M Hub Ports Enable 0x49 Hub Ports Speed 0x4A Hub Ports Suspend 0x4D mE Hub Ports Resume Status Ox4E o Hub Ports SEO Status 0x4F M HT Hub Ports Data 0x50 Hub Downstream Force 0x51 A USB Bus Reset Interrupt is generated at the end
64. it 4 Bit 3 Bit 2 Bit 1 Bit 0 Read Write R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Figure 17 1 USB Device Address Registers Bits 6 0 Device Address Firmware writes this bits during the USB enumeration process to the non zero address assigned by the USB host Bit 7 Device Address Enable Must be set by firmware before the SIE can respond to USB traffic to the Device Address 17 2 USB Device Endpoints The CY7C65113C controller supports up to two addresses and five endpoints for communication with the host The configuration of these endpoints and associated FIFOs is controlled by bits 7 6 of the USB Status and Control Register Figure 16 10 Bit 7 controls the size of the endpoints and bit 6 controls the number of addresses These configuration options are detailed in Table 17 1 Endpoint FIFOs are part of user RAM as shown in Section 5 4 1 Document 38 08002 Rev D Page 34 of 49 Feedback CYPRESS CY7C65113C PERFORM Table 17 1 Memory Allocation for Endpoints USB Status And Control Register 0x1F Bits 7 6 0 0 1 0 0 1 1 1 Two USB Addresses Two USB Addresses A 3 Endpoints and A 3 Endpoints and One USB Address One USB Address B 2 Endpoints B 2 Endpoints A 5 Endpoints A 5 Endpoints Label Start Address Size Label Start Address Size Label Start Address Size Label Start Address Size EPB1 OxD8 8 EPB
65. its as defined in Table 16 1 below The Hub Downstream Ports Control Register is cleared upon reset or bus reset and the reset state is the state for normal USB traffic Any downstream port being forced must be marked as disabled Figure 16 3 for proper operation of the hub repeater Firmware should use this register for driving bus reset and resume signaling to downstream ports Controlling the port pins through this register uses standard USB edge rate control according to the speed of the port set in the Hub Port Speed Register Document 38 08002 Rev D Page 30 of 49 Feedback CYPRESS PERFORM CY7C65113C The downstream USB ports are designed for connection of USB devices but can also serve as output ports under firmware control This allows unused USB ports to be used for functions such as driving LEDs or providing additional input signals Pulling up these pins to voltages above Vgge may cause current flow into the pin This register is not reset by USB bus reset These bits must be cleared before going into suspend Hub Downstream Ports Control Register Address 0x4B Bit 4 7 6 5 4 3 2 1 0 Bit Name Port 4 Port 4 Port 3 Port 3 Port 2 Port 2 Port 1 Port 1 Control Bit 1 Control Bit 0 Control Bit 1 Control Bit 0 Control Bit 1 Control Bit 0 Control Bit 1 Control Bit 0 Read Write R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Figure 16 4 Hub Do
66. nly and is independent of the settings of the Hub Ports Speed Register Figure 16 2 When the SEO condition is sensed on a downstream port the corresponding bits of the Hub Ports Data Register hold the last differential data state before the SEO Hub Ports SEO Status Register and Hub Ports Data Register are cleared upon reset or bus reset Hub Ports SEO Status Address 0x4F Bit 7 6 5 4 3 2 1 0 Bit Name Reserved Reserved Reserved Reserved Port 4 Port 3 Port 2 Port 1 SEO Status SEO Status SEO Status SEO Status Read Write R R R R R R R R Reset 0 0 0 0 0 0 0 0 Bit 0 3 Port x SEO Status where x 7 1 4 Figure 16 6 Hub Ports SEO Status Register Set to 1 if a SEO is output on the Port x bus Set to 0 if a Non SEO is output on the Port x bus Bit 4 7 Reserved Set to 0 Document 38 08002 Rev D Page 31 of 49 Feedback CYPRESS CY7C65113C PERFORM Hub Ports Data ADDRESS 0x50 Bit 2 7 6 5 4 3 2 1 0 Bit Name Reserved Reserved Reserved Reserved Port 4 Diff Port 3 Diff Port 2 Diff Port 1 Diff Data Data Data Data Read Write R R R R R R R R Reset 0 0 0 0 0 0 0 0 Figure 16 7 Hub Ports Data Register Bit 0 3 Port x Diff Data where x 7 1 4 Set to 1 if D gt D forced differential 1 if signal is differential i e not a SEO or SE1 Set to 0 if D gt D forced differential 0 if signal is di
67. nly the SIE can set it Bits 4 and 5 D Upstream and D Upstream These bits give the state of each upstream port pin individually 1 HIGH 0 LOW Bit 6 Endpoint Mode This bit used to configure the number of USB endpoints See Section 17 2 for a detailed description Bit 7 Endpoint Size This bit used to configure the number of USB endpoints See Section 17 2 for a detailed description The hub generates an EOP at EOF1 in accordance with the USB 1 1 Specification Section 11 2 2 as well as USB 2 0 specification section 11 2 5 page 304 17 0 USB Serial Interface Engine Operation The CY7C65113C SIE supports operation as a single device or a compound device This section describes the two device addresses the configurable endpoints and the endpoint function 17 1 USB Device Addresses The USB Controller provides two USB Device Address Registers A addressed at 0x10 and B addressed at 0x40 Upon reset and under default conditions Device A has three endpoints and Device B has two endpoints The USB Device Address Register contents are cleared during a reset setting the USB device addresses to zero and disabling these addresses Figure 17 1 shows the format of the USB Address Registers USB Device Address Device A B Addresses 0x10 A and 0x40 B Bit 7 6 5 4 3 2 1 0 Bit Name Device Device Device Device Device Device Device Device Address Address Address Address Address Address Address Address Enable Bit 6 Bit 5 B
68. nstruction The program counters CF and ZF are restored and interrupts are enabled when the RETI instruction is executed The IDI and EI instruction can be used to disable and enable interrupts respectively These instruction affect only the Global Interrupt Enable bit of the CPU If desired El can be used to re enable interrupts while inside an ISR instead of waiting for the RETI that exits the ISR While the global interrupt enable bit is cleared the presence of a pending interrupt can be detected by examining the IRQ Sense bit Bit 7 in the Processor Status and Control Register 14 1 Interrupt Vectors The Interrupt Vectors supported by the USB Controller are listed in Table 14 1 The lowest numbered interrupt USB Bus Reset interrupt has the highest priority and the highest numbered interrupt 1 C interrupt has the lowest priority TT USB Reset Clear Interrupt CLR Vector Tesch 1 lp USB Reset IRQ Q Enable 0 41128 us CLR Reg 0x20 428 us IRQ 1 ms CLR o 341 ms IRQ o o AddrA EPO CLR o JAddrA EPO IRQ o AddrA EP1 CLR AddrA EP1 IRQ CLR AddrA EP2 CLR 1 p Q AddrA EP2 IRQ AddrB EPO CLR AddrB EPO IRQ AddrB EP1 CLR AddrB EP1 IRQ Hub CLR Hub IRQ DAC CLR DAC IRQ GPIO CLR GPIO IRQ ck P CLR SCH IC IR 1 D HI Enable 6 L Q Reg 0x20 2 Interrupt Priority Encoder I C Int CLK CPU zm Sense IRQ USB Reset Int CLK IRQout o
69. nter Registers eseeeeeeeeeeeeneere 17 6 Endpoint Mode Count Registers Update and Locking Mechanism 16 0 USB MODE TABLES n teoiatrpa kir inar o pbxI UE neninn PIN a EE HQ Cun a DE UG RMEE 19 0 REGISTER SUMMARY iuusciescnuuux tico qaa iere Gai Ru Ree a Rc E o On EC B C ER 20 0 SAMPLE SCHEMA UNG orit reatasE rario a aub axons brav euuD EU KEpxE cux akku USE nsaan sannana 21 0 ABSOLUTE MAXIMUM RATINGS eese 22 0 ELECTRICAL CHARACTERISTICS esee 23 0 SWITCHING CHARACTERISTICS revernnnnnvvnnnnnnnnvennnnvvnnnnnnnnennnnnnnnennnnnnenenr 24 0 ORDERING INFORMATION gugeeeteeiekesbasege iku ok a c RR XR C ern SUR C ale 25 0 PACKAGE DIAGRAM 152 iscan cu iran sa nRkd AS DOLAR ES skkL E KENE EE Y SE CCP M eu dn LIST OF FIGURES Figure 5 1 Program Memory Space with Interrupt Vector Table Figure 6 1 Clock Oscillator On Chip Circuit rrrrrnnnnrrrnnnnnnnrnnnnrrrrnnnnnvnnrrrnnnnnnn Figure 7 1 Watchdog Reset Address 0x26 ssseeeeeee Figure 9 1 Block Diagram of a GPIO Pin rrrnrnnnnnnnnnnnnrrnnnnnnnvnnvrnnnnrnnnnnnnerernnnnnnn oe Port O Data vere gos Sc cu Nb erm Figure 9 4 GPIO Configuration Register rrrnnnnnnrnnnnnrvrnnnnnnvnrnrnnnnnnnnnnnnevrrnnnnnnn Figure 9 5 Port O Interrupt Enable rrrnnnnnnnvnorrrnnnnnnnnavvnvnenenennnnnnvnonnnnnnennnnnnne Figure 9 6 Port 1 Interrupt Enable EE Figure 10 1 T
70. nterrupts on all I O pins 12 bit free running timer with one microsecond clock ticks Watchdog timer WDT Internal Power on Reset POR USB Specification compliance Conforms to USB Specification Version 1 1 Conforms to USB HID Specification Version 1 1 Supports one or two device addresses with up to 5 user configured endpoints Up to two 8 byte control endpoints Up to four 8 byte data endpoints Up to two 32 byte data endpoints Integrated USB transceivers Supports four downstream USB ports GPIO pins can provide individual power control outputs for each downstream USB port GPIO pins can provide individual port over current inputs for each downstream USB port Improved output drivers to reduce electromagnetic interference EMI Operating voltage from 4 0V to 5 5V DC Operating temperature from 0 to 70 C Available in 28 pin SOIC SXC package Industry standard programmer support Document 38 08002 Rev D Page 5 of 49 Feedback pr E CYPRESS E PERFORM 2 0 Functional Overview The CY7C65113C device is a one time programmable 8 bit microcontroller with a built in 12 Mbps USB hub that supports up to four downstream ports The microcontroller instruction set has been optimized specifically for USB operations although the microcontrollers can be used for a variety of non USB embedded applications GPIO The CY7C65113C has 11 GPIO pins PO 7 0 P1 2 0 both rated at 7 mA per
71. o connect state The hub must have a resistor Ryyp connected between its upstream D line and Vggg to indicate it is a full speed USB device The hub generates an EOP at EOF1 in accordance with the USB 1 1 Specification section 11 2 2 page 234 as well as USB 2 0 specification section 11 2 5 page 304 16 1 Connecting Disconnecting a USB Device A low speed 1 5 Mbps USB device has a pull up resistor on the D pin At connect time the bias resistors set the signal levels on the D and D lines When a low speed device is connected to a hub port the hub sees a LOW on D and a HIGH on D This causes the hub repeater to set a connect bit in the Hub Ports Connect Status register for the downstream port see Figure 16 1 Then the hub repeater generates a Hub Interrupt to notify the microcontroller that there has been a change in the Hub downstream status The firmware sets the speed of this port in the Hub Ports Speed Register see Figure 16 2 A full speed 12 Mbps USB device has a pull up resistor from the D pin so the hub sees a HIGH on D and a LOW on D In this case the hub repeater sets a connect bit in the Hub Ports Connect Status register and generates a Hub Interrupt to notify the microcontroller of the change in Hub status The firmware sets the speed of this port in the Hub Ports Speed Register see Figure 16 2 Connects are recorded by the time a non SEO state lasts for more than 2 5 us on a downstream port When a USB dev
72. oding is shown in Table 18 1 Additional information on the mode bits can be found in Table 18 2 and Table 18 3 17 4 USB Non control Endpoint Mode Registers The format of the non control endpoint mode registers is shown in Figure 17 3 USB Non control Device Endpoint Mode Addresses 0x14 0x16 0x44 lg 7 5 4 3 2 4 0 Bit Name STALL Reserved Reserved ACK Mode Bit 3 Mode Bit2 Mode Bit 1 Mode Bit 0 Read Write R W R W R W R W R W R W R W R W Ret 0 0 0 o o o o o0 Figure 17 3 USB Non control Device Endpoint Mode Registers Bits 3 0 Mode These sets the mode which control how the control endpoint responds to traffic The mode bit encoding is shown in Table 18 1 Bit 4 ACK This bit is set whenever the SIE engages in a transaction to the register s endpoint that completes with an ACK packet Bits 6 5 Reserved Must be written zero during register writes Bit 7 STALL If this STALL is set the SIE stalls an OUT packet if the mode bits are set to ACK IN and the SIE stalls an IN packet if the mode bits are set to ACK OUT For all other modes the STALL bit must be a LOW 17 5 USB Endpoint Counter Registers There are five Endpoint Counter registers with identical formats for both control and non control endpoints These registers contain byte count information for USB transactions as well as bits for data packet status The format of these register
73. of the USB Bus Reset condition when the SEO state is deasserted If the USB reset occurs during the start up delay following a POR the delay is aborted as described in Section 7 1 SS 2 wre vo vor a 14 4 Timer Interrupt There are two periodic timer interrupts the 128 us interrupt and the 1 024 ms interrupt The user should disable both timer interrupts before going into the suspend mode to avoid possible conflicts between servicing the timer interrupts first or the suspend request first Document 38 08002 Rev D Page 26 of 49 Feedback Z CYPRESS CY7C65113C PERFORM 14 5 USB Endpoint Interrupts There are five USB endpoint interrupts one per endpoint A USB endpoint interrupt is generated after the USB host writes to a USB endpoint FIFO or after the USB controller sends a packet to the USB host The interrupt is generated on the last packet of the transaction e g on the host s ACK on an IN transfer or on the device ACK on an OUT transfer If no ACK is received during an IN transaction no interrupt is generated 14 6 USB Hub Interrupt A USB hub interrupt is generated by the hardware after a connect disconnect change babble or a resume event is detected by the USB repeater hardware The babble and resume events are additionally gated by the corresponding bits of the Hub Port Enable Register Figure 16 3 The connect disconnect event on a port does not generate an interrupt if the SIE does not drive the port i e
74. om 1 to 0 generates Stop bit Bit 7 MSTR Mode Setting this bitto 1 causes the I C compatible block to initiate a master mode transaction by sending a start bit and transmitting the first data byte from the data register this typically holds the target address and R W bit Subsequent bytes are initiated by setting the Continue bit as described below Clearing this bit set to 0 causes the GPIO pins to operate normally In master mode the I C compatible block generates the clock SCK and drives the data line as required depending on transmit or receive state The I C compatible block performs any required arbitration and clock synchronization IN the event of a loss of arbitration this MSTR bit is cleared the ARB Lost bit is set and an interrupt is generated by the microcontroller If the chip is the target of an external master that wins arbitration then the interrupt is held off until the transaction from the external master is completed When MSTR Mode is cleared from 1 to 0 by a firmware write an 2c Stop bit is generated Bit 6 Continue Busy This bit is written by the firmware to indicate that the firmware is ready for the next byte transaction to begin In other words the bit has responded to an interrupt request and has completed the required update or read of the data register During a read this bit indicates if the hardware is busy and is locking out additional writes to the VC Status and Control register This
75. on an ACK from mode 1101 Ack In Ack Out Status In 1011 accept TX0 Byte ACK On issuance of an ACK this mode is changed by SIE to 1010 NAK Ack IN STALL l 0 1101 ignore TX Count ignore On issuance of an ACK this mode is changed by SIE to 1100 NAK In Ack IN STALL l 1 1101 ignore stall ignore Nak In Status Out 1110 accept NAK check Is set by SIE on an ACK from mode 1111 Ack In Status Out Ack In Status Out 1111 accept TX Count check On issuance of an ACK this mode is changed by SIE to 1110 NAK In Status Out Mode This lists the mnemonic given to the different modes that can be set in the Endpoint Mode Register by writing to the lower nibble bits 0 3 The bit settings for different modes are covered in the column marked Mode Bits The Status IN and Status OUT represent the Status stage in the IN or OUT transfer involving the control endpoint Mode Bits These column lists the encoding for different modes by setting Bits 3 0 of the Endpoint Mode register This modes represents how the SIE responds to different tokens sent by the host to an endpoint For instance if the mode bits are set to 0001 NAK IN OUT the SIE will respond with an ACK on receiving a SETUP token from the host NAK on receiving an OUT token from the host NAK on receiving an IN token from the host Refer to Section 13 0 for more information on the SIE functioning SE
76. part in PDIP package Modified Table 18 1 and provided more explanation regarding locking unlocking mechanism of the mode register Removed any information regarding the speed detect bit in Hub Port Speed register being set by hardware Fixed the figure on page 42 regarding the update of mode registers The arrows in the figure were misplaced and the figure was unreadable This is an important figure for understanding mode register functioning C 368601 See ECN BHA Added Lead free Package Information Removed CY7C65013 Information Updated Package Drawing D 429098 See ECN Document 38 08002 Rev D TYJ Part numbers changed to C types Cypress Perform logo added Part numbers updated in the ordering section Page 49 of 49 Feedback
77. pin typical sink current Multiple GPIO pins can be connected together to drive a single output for more drive current capacity Clock The microcontroller uses an external 6 MHz crystal and an internal oscillator to provide a reference to an internal phase locked loop PLL based clock generator This technology allows the customer application to use an inexpensive 6 MHz fundamental crystal that reduces the clock related noise emissions EMI A PLL clock generator provides the 6 12 and 48 MHz clock signals for distribution within the microcontroller Memory The CY7C65113C is offered with 8 KB of PROM Power on Reset Watchdog and Free running Timer These parts include power on reset logic a Watchdog timer and a 12 bit free running timer The POR logic detects when power is applied to the device resets the logic to a known state and begins executing instructions at PROM address 0x0000 The Watchdog timer is used to ensure the microcontroller recovers after a period of inactivity The firmware may become inactive for a variety of reasons including errors in the code or a hardware failure such as waiting for an interrupt that never occurs Pc The microcontroller can communicate with external electronics through the GPIO pins An I C compatible interface accommo dates a 100 kHz serial link with an external device Timer The free running 12 bit timer clocked at 1 MHz provides two interrupt sources 128 us and 1 024 ms The timer can be
78. ple if the Mode Bits 3 0 are set to 1111 which is ACK IN Status OUT mode as shown in Table 18 1 the SIE will change the endpoint Mode Bits 3 0 to NAK IN Status OUT mode 1110 after ACK ing a valid status stage OUT token The firmware needs to update the mode for the SIE to respond appropriately See Table 18 1 for more details on what modes will be changed by the SIE A disabled endpoint will remain disabled until changed by firmware and all endpoints reset to the disabled mode 0000 Firmware normally enables the endpoint mode after a SetConfiguration request Any SETUP packet to an enabled endpoint with mode set to accept SETUPs will be changed by the SIE to 0001 NAKing INs and OUTs Any mode set to accept a SETUP will send an ACK handshake to a valid SETUP token The control endpoint has three status bits for identifying the token type received SETUP IN or OUT but the endpoint must be placed in the correct mode to function as such Non control endpoints should not be placed into modes that accept SETUPs Note that most modes that control transactions involving an ending ACK are changed by the SIE to a corresponding mode which NAKs subsequent packets following the ACK Exceptions are modes 1010 and 1110 Table 18 2 Decode table for Table 18 3 Details of Modes for Differing Traffic Condition Properties of Incoming Changes to the Internal Register made by the SIE on receiving an incoming packet Packets 1 from the host Interr
79. point 2 interrupt vector USB address B endpoint 0 interrupt vector USB address B endpoint 1 interrupt vector Hub interrupt vector Reserved GPIO interrupt vector Ic interrupt vector 8 KB 32 PROM ends here CY7C65113C Figure 5 1 Program Memory Space with Interrupt Vector Table Program Memory begins here Note that the upper 32 bytes of the 8K PROM are reserved Therefore user s program must not overwrite this space Document 38 08002 Rev D Page 12 of 49 Feedback CYPRESS CY7C65113C PERFORM 5 2 8 bit Accumulator A The accumulator is the general purpose register for the microcontroller 5 3 8 bit Temporary Register X The X register is available to the firmware for temporary storage of intermediate results The microcontroller can perform indexed operations based on the value in X Refer to Section 5 6 3 for additional information 5 4 8 bit Program Stack Pointer PSP During a reset the Program Stack Pointer PSP is set to 0x00 and grows upward from this address The PSP may be set by firmware using the MOV PSBAA instruction The PSP supports interrupt service under hardware control and CALL RET and RETI instructions under firmware control The PSP is not readable by the firmware During an interrupt acknowledge interrupts are disabled and the 14 bit program counter carry flag and zero flag are written as two bytes of data memory The first byte is stored in t
80. quest if it is enabled by the corresponding bit in the interrupt enable registers The highest priority interrupt request is serviced following the completion of the currently executing instruction When servicing an interrupt the hardware does the following 1 Disables all interrupts by clearing the Global Interrupt Enable bit in the CPU the state of this bit can be read at Bit 2 of the Processor Status and Control Register Figure 13 1 2 Clears the flip flop of the current interrupt 3 Generates an automatic CALL instruction to the ROM address associated with the interrupt being serviced i e the Interrupt Vector see Section 14 1 The instruction in the interrupt table is typically a JMP instruction to the address of the Interrupt Service Routine ISR The user can reenable interrupts in the interrupt service routine by executing an EI instruction Interrupts can be nested to a level limited only by the available stack space The Program Counter value as well as the Carry and Zero flags CF ZF are stored onto the Program Stack by the automatic CALL instruction generated as part of the interrupt acknowledge process The user firmware is responsible for ensuring that the processor state is preserved and restored during an interrupt The PUSH A instruction should typically be used as the first command in the ISR to save the accumulator value and the POP A instruction should be used to restore the accumulator value just before the RETI i
81. rt 2 Port 1 Port 1 BBBBBBBB 00000000 E 4 1 Control Bit 1 Control Bit 0 Control Bit 1 Control Bit 0 Control Bit 1 Control Bit 0 Control Bit 1 Control Bit 0 E Ox4D Hub Port Suspend Device Reserved Reserved Reserved Port 4 Port 3 Port 2 Port 1 BBBBBBBB 00000000 of Remote Selective Selective Selective Selective z Wakeup Suspend Suspend Suspend Suspend Ox4E Hub Port Resume Status Reserved Reserved Reserved Reserved Resume 4 Resume 3 Resume 2 Resume 1 RRRRRRR 00000000 a Ox4F Hub Port SEO Status Reserved Reserved Reserved Reserved Port 4 Port 3 Port 2 Port 1 RRRRRRRR 00000000 9 SEO Status SEO Status SEO Status SEO Status H 0x50 Hub Ports Data Reserved Reserved Reserved Reserved Port 4 Port 3 Port 2 Port 1 RRRRRRRR 00000000 s Diff Data Diff Data Diff Data Diff Data o 0x51 Hub Port Force Low Force Low Force Low Force Low Force Low Force Low Force Low Force Low Force Low BBBBBBBB 00000000 9 Ports 4 1 D 4 D 4 D 3 D 3 D 2 D 2 D 1 D 1 S E 7 d o D E E o o amp o a a 2 r OxFF Process Status amp Control IRQ Watchdog USB Bus Power on Suspend Interrupt Reserved Run RBBBBRBB 00010001 Pending Reset Reset Reset Enable Interrupt Sense Document 38 08002 Rev D Page 44 of 49 Feedback CYPRESS CY7C65113C PERFORM 20 0 Sample Schematic
82. s i e JC JNC JZ JNZ take five cycles if jump is taken four cycles if no jump Table 4 3 Instruction Set Summary MNEMONIC operand opcode cycles MNEMONIC operand opcode cycles HALT 00 7 NOP 20 4 ADD A expr data 01 4 INCA acc 21 4 ADD A expr direct 02 6 INC X x 22 4 ADD A X expr index 03 7 INC expr direct 23 7 ADC A expr data 04 4 INC X expr index 24 8 ADC A expr direct 05 6 DECA acc 25 4 ADC A X expr index 06 7 DEC X x 26 4 SUB A expr data 07 4 DEC expr direct 27 7 SUB A expr direct 08 6 DEC X expr index 28 8 SUB A X expr index 09 7 IORD expr address 29 5 SBB A expr data 0A 4 IOWR expr address 2A 5 SBB A expr direct 0B 6 POPA 2B 4 SBB A X expr index OG 7 POP X 2C 4 OR A expr data OD A PUSHA 2D 5 OR A expr direct 0E 6 PUSH X 2E 5 OR A X expr index OF 7 SWAP A X 2F 5 AND A expr data 10 4 SWAP A DSP 30 5 AND A expr direct 11 6 MOV expr A direct 31 5 AND A X expr index 12 7 MOV X expr A index 32 6 XOR A expr data 13 4 OR expr A direct 33 7 XOR A expr direct 14 6 OR X expr A index 34 8 XOR A X expr index 15 7 AND expr A direct 35 7 CMP A expr data 16 5 AND X expr A index 36 8 CMP A expr direct 17 7 XOR expr A direct 37 7 CMP A X expr index 18 8 XOR X expr A index 38 8
83. s is shown in Figure 17 4 USB Endpoint Counter Addresses 0x11 0x13 0x15 0x44 0x43 Bit 7 6 5 4 3 2 1 0 Bit Name Data 0 1 Data Valid Byte Count Byte Count Byte Count Byte Count Byte Count Byte Count Toggle Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 Read Write R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Figure 17 4 USB Endpoint Counter Registers Bits 5 0 Byte Count These counter bits indicate the number of data bytes in a transaction For IN transactions firmware loads the count with the number of bytes to be transmitted to the host from the endpoint FIFO Valid values are 0 to 32 inclusive For OUT or SETUP transactions the count is updated by hardware to the number of data bytes received plus two for the CRC bytes Valid values are 2 to 34 inclusive Note 5 TheSIE offers an Ack out Status in mode and not an Ack out Nak in mode Therefore if following the status stage of a Control Write transfer a USB host were to immediately start the next transfer the new Setup packet could override the data payload of the data stage of the previous Control Write Document 38 08002 Rev D Page 36 of 49 Feedback CYPRESS CY7C65113C PERFORM Bit 6 Data Valid This bit is set on receiving a proper CRC when the endpoint FIFO buffer is loaded with data during transactions This bit is used OUT and SETUP tokens only If the CRC is not correct the
84. sonator does not allow the microcontroller to meet the timing specifications of full speed USB and therefore a ceramic resonator is not recommended with these parts An external 6 MHz clock can be applied to the XTALIN pin if the XTALOUT pin is left open Grounding the XTALOUT pin when driving XTALIN with an oscillator does not work because the internal clock is effectively shorted to ground T 0 Reset The CY7C65113C supports two resets POR and WDR Each of these resets causes all registers to be restored to their default states the USB device addresses to be set to 0 all interrupts to be disabled the PSP and DSP to be set to memory address 0x00 The occurrence of a reset is recorded in the Processor Status and Control Register as described in Section Bits 4 and 6 are used to record the occurrence of POR and WDR respectively Firmware can interrogate these bits to determine the cause of a reset Program execution starts at ROM address 0x0000 after a reset Although this looks like interrupt vector 0 there is an important difference Reset processing does NOT push the program counter carry flag and zero flag onto program stack The firmware reset handler should configure the hardware before the main loop of code Attempting to execute a RET or RETI in the firmware reset handler causes unpredictable execution results 7 1 Power on Reset When Vee is first applied to the chip the POR signal is asserted and the CY7C65113C enters a
85. sume when the hub is suspended typically involves these actions 1 Hardware detects the Resume drives a K on the upstream which is then reflected to all downstream enabled ports and generates the hub interrupt 2 The part comes out of suspend and the clocks start 3 Once the clocks are stable firmware execution resumes An internal counter ensures that this takes at least 1 ms Firmware should check for Resume from any selectively suspended ports If found the Selective Suspend bit for the port should be cleared no other action is necessary 4 The Resume ends when the host stops sending K from upstream Firmware should check for changes to the Enable and Connect Registers If a port has become disabled but is still connected an SEO has been detected on the port The port should be treated as having been reset and should be reported to the host as newly connected Firmware can choose to clear the Device Remote Wake up bit if set to implement firmware timed states for port changes All allowed port changes wake the part Then the part can use internal timing to determine whether to take action or return to suspend If Device Remote Wake up is set automatic hardware assertions take place on Resume events 16 5 USB Upstream Port Status and Control USB status and control is regulated by the USB Status and Control Register as shown in Figure 16 10 All bits in the register are cleared during reset USB Status and Control A
86. t 0 0 0 0 0 Figure 14 2 USB Endpoint Interrupt Enable Register Bit 0 EPAO Interrupt Enable 1 Enable Interrupt on data activity through endpoint AO 0 Disable Interrupt on data activity through endpoint AO Bit 1 EPA1 Interrupt Enable 1 Enable Interrupt on data activity through endpoint A1 0 Disable Interrupt on data activity through endpoint A1 Bit 2 EPA2 Interrupt Enable 1 Enable Interrupt on data activity through endpoint A2 0 Disable Interrupt on data activity through endpoint A2 Bit 3 EPBO Interrupt Enable 1 Enable Interrupt on data activity through endpoint BO 0 Disable Interrupt on data activity through endpoint BO Bit 4 EPB1 Interrupt Enable 1 Enable Interrupt on data activity through endpoint B1 0 Disable Interrupt on data activity through endpoint B1 Bit 7 5 Reserved Document 38 08002 Rev D Page 24 of 49 Feedback e x SACYPRESS EE PERFORM During a reset the contents of the Global Interrupt Enable Register and USB End Point Interrupt Enable Register are cleared effectively disabling all interrupts The interrupt controller contains a separate flip flop for each interrupt See Figure 14 3 for the logic block diagram of the interrupt controller When an interrupt is generated it is first registered as a pending interrupt It stays pending until it is serviced or a reset occurs A pending interrupt only generates an interrupt re
87. t GPIO Reserved USB Hub 1 024 ms 128 us USB Bus Enable Interrupt Interrupt Interrupt Interrupt RST Enable Enable Enable Enable Interrupt Enable Read Write R W R W R W R W R W R W Reset 0 0 X 0 0 0 0 Figure 14 1 Global Interrupt Enable Register Bit 0 USB Bus RST Interrupt Enable 1 Enable Interrupt on a USB Bus Reset 0 Disable interrupt on a USB Bus Reset Refer to section 14 3 Bit 1 128 us Interrupt Enable 1 Enable Timer interrupt every 128 us 0 Disable Timer Interrupt for every 128 us Bit 2 1 024 ms Interrupt Enable 1 Enable Timer interrupt every 1 024 ms 0 Disable Timer Interrupt every 1 024 ms Bit 3 USB Hub Interrupt Enable 1 Enable Interrupt on a Hub status change 0 Disable interrupt due to hub status change Refer to section 14 6 Bit 4 Reserved Bit 5 GPIO Interrupt Enable 1 Enable Interrupt on falling rising edge on any GPIO 0 Disable Interrupt on falling rising edge on any GPIO Refer to section 14 7 9 1 and 9 2 Bit 6 GC Interrupt Enable 1 Enable Interrupt on 12C related activity 0 Disable I2C related activity interrupt Refer to section 14 8 Bit 7 Reserved USB Endpoint Interrupt Enable Address 0X21 Bit 4 7 6 5 4 3 2 1 0 Bit Name Reserved Reserved Reserved EPB1 EPBO EPA2 EPA1 EPAO Interrupt Interrupt Interrupt Interrupt Interrupt Enable Enable Enable Enable Enable Read Write R W R W R W R W R W Rese
88. t used in 5 endpoint mode 34 EP BO Counter Register 0x41 R W USB Address B Endpoint 0 Counter 36 EP BO Mode Register 0x42 R W USB Address B Endpoint 0 Configuration or 35 USB Address A Endpoint 3 in 5 endpoint mode EP B1 Counter Register 0x43 R W USB Address B Endpoint 1 Counter 36 EP B1 Mode Register 0x44 R W USB Address B Endpoint 1 Configuration or 36 USB Address A Endpoint 4 in 5 endpoint mode Hub Port Connect Status 0x48 R W Hub Downstream Port Connect Status 29 Hub Port Enable 0x49 R W Hub Downstream Ports Enable 30 Hub Port Speed Ox4A R W Hub Downstream Ports Speed 30 Document 38 08002 Rev D Page 9 of 49 Feedback CYPRESS CY7C65113C PERFORM Table 4 2 I O Register Summary continued Register Name I O Address Read Write Function Page Hub Port Control Ports 4 1 0x4B R W Hub Downstream Ports Control Ports 4 1 31 Hub Port Suspend 0x4D R W Hub Downstream Port Suspend Control 32 Hub Port Resume Status Ox4E R Hub Downstream Ports Resume Status 33 Hub Ports SEO Status Ox4F R Hub Downstream Ports SEO Status 31 Hub Ports Data 0x50 R Hub Downstream Ports Differential Data 32 Hub Downstream Force Low 0x51 R W Hub Downstream Ports Force LOW Ports 1 4 31 Processor Status amp Control OxFF R W Microprocessor Status and Control Register 23 4 3 Instruction Set Summary Refer to the CYASM Assembler User s Guide for more details Note that conditional jump instruction
89. ter Endpoint 0 Endpoint 0 Endpoint 0 ACK Mode Bit 3 Mode Bit 2 Mode Bit 1 Mode Bit 0 BBBBBBBB 00000000 o SETUP IN OUT 2 Received Received Received m 0x43 EP B1 Counter Register Data 0 1 Data Valid Byte Count Byte Count Byte Count Byte Count Byte Count Byte Count BBBBBBBB 00000000 a Toggle Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 5 0x44 EP B1 Mode Register STALL ACK Mode Bit3 Mode Bit2 Mode Bit1 Mode Bit 0 BBBBBBBB 00000000 2 a z DI Note 7 B Read and Write W Write R Read Document 38 08002 Rev D Page 43 of 49 Feedback CYPRESS CY7C65113C PERFORM 19 0 Register Summary continued Address Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read Write B Default oth 7 Reset z 0x48 Hub Port Connect Status Reserved Reserved Reserved Reserved Port 4 Port 3 Port 2 Port 1 BBBBBBBB 00000000 E Connect Connect Connect Connect 4 Status Status Status Status ul o D o Lu ei ul o ul z 2 o ul D a z ul a 7 2 7 o 2 lt 7 d o D E z o o E o a a gt 0x49 Hub Port Enable Reserved Reserved Reserved Reserved Port 4 Port 3 Port 2 Port 1 BBBBBBBB 00000000 o Enable Enable Enable Enable m Ox4A Hub Port Speed Reserved Reserved Reserved Reserved Port 4 Port 3 Port 2 Port 1 BBBBBBBB 00000000 9 Speed Speed Speed Speed 9 Ox4B Hub Port Control Ports Port 4 Port A Port 3 Port 3 Port 2 Po
90. ter various events on the I C compatible bus to signal the need for firmware interaction This generally involves reading the IC Status and Control Register Figure 12 2 to determine the cause of the interrupt loading reading the lC Data Register as appropriate and finally writing the Processor Status and Control Register Figure 13 1 to initiate the subsequent transaction The interrupt indicates that status bits are stable and it is safe to read and write the Ic registers Refer to Section 12 0 for details on the VC registers When enabled the 2C compatible state machines generate interrupts on completion of the following conditions The referenced bits are in the IC Status and Control Register 1 In slave receive mode after the slave receives a byte of data The Adar bit is set if this is the first byte since a start or restart signal was sent by the external master Firmware must read or write the data register as necessary then set the ACK Xmit MODE and Continue Busy bits appropriately for the next byte 2 In slave receive mode after a stop bit is detected The Received Stop bit is set if the stop bit follows a slave receive transaction where the ACK bit was cleared to 0 no stop bit detection occurs Document 38 08002 Rev D Page 27 of 49 Feedback CYPRESS CY7C65113C PERFORM 3 In slave transmit mode after the slave transmits a byte of data The ACK bit indicates if the master that requested the byte acknowledged
91. ternal Watchdog Timer rolls over Writing any value to the write only Watchdog Reset Clear Register Figure 7 1 clears the timer The timer rolls over and WDR occurs if it is not cleared within twatcu of the last clear see Section 23 0 for the value of twatcy Bit 6 of the Processor Status and Control Register Figure 13 1 is set to record this event the register contents are set to 010X0001 by the WDR A Watchdog Timer Reset lasts for 2 ms after which the microcontroller begins execution at ROM address 0x0000 H t Fd twatcH 2 ms Last write to No write to WDT Execution begins at Watchdog Timer register so WDR Reset Vector 0x0000 Register goes HIGH Figure 7 1 Watchdog Reset Address 0x26 The USB transmitter is disabled by a Watchdog Reset because the USB Device Address Registers are cleared see Section 17 1 Otherwise the USB Controller would respond to all address 0 transactions It is possible for the WDR bit of the Processor Status and Control Register Figure 13 1 to be set following a POR event If a firmware interrogates the Processor Status and Control Register for a set condition on the WDR bit the WDR bit should be ignored if the POR bit is set Bit 3 of the Processor Status and Control Register 8 0 Suspend Mode The CY7C65113C can be placed into a low power state by setting the Suspend bit of the Processor Status and Control register All logic blocks in the device are turned
92. tomatically propagate the resume signal after a remote wakeup event regardless of the state of the Device Remote wakeup bit The state of this bit has no impact on the generation of the hub interrupt A resume bit is set automatically when hardware detects a resume condition on a selectively suspended downstream port The resume condition is a differential 1 for a low speed device and a differential 0 for a full speed device These registers are cleared on reset or USB bus reset Hub Ports Suspend Address 0x4D Bit 7 6 5 4 3 2 1 0 Bit Name Device Reserved Reserved Reserved Port 4 Port 3 Port 2 Port 1 Remote Selective Selective Selective Selective Wakeup Suspend Suspend Suspend Suspend Read Write R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 Figure 16 8 Hub Ports Suspend Register Bit 0 3 Port x Selective Suspend where x 1 4 Set to 1 if Port x is Selectively Suspended Set to 0 if Port x Do not suspend Bit 7 Device Remote Wakeup When set to 1 Enable hardware upstream resume signaling for connect disconnect events during global resume When set to 0 Disable hardware upstream resume signaling for connect disconnect events during global resume Document 38 08002 Rev D Page 32 of 49 CYPRESS PERFORM Hub Ports Resume CY7C65113C Address 0x4E Bit 7 6 5 4 3 2 1 0 Bit Name Reserved Reserved Reserved
93. tor must be D8h or less SWAP A DSP swap accumulator value into DSP register 5 6 Address Modes The CY7C65113 microcontrollers support three addressing modes for instructions that require data operands data direct and indexed 5 6 1 Data Immediate Data address mode refers to a data operand that is actually a constant encoded in the instruction As an example consider the instruction that loads A with the constant OxD8 MOV A OD8h This instruction requires two bytes of code where the first byte identifies the MOV AT instruction with a data operand as the second byte The second byte of the instruction is the constant OxD8 A constant may be referred to by name if a prior EQU statement assigns the constant value to the name For example the following code is equivalent to the example shown above DSPINIT EQU OD8h MOV A DSPINIT 5 6 2 Direct Direct address mode is used when the data operand is a variable stored in SRAM In that case the one byte address of the variable is encoded in the instruction As an example consider an instruction that loads A with the contents of memory address location 0x10 MOV A 10h Normally variable names are assigned to variable addresses using EQU statements to improve the readability of the assembler Source code As an example the following code is equivalent to the example shown above buttons EQU 10h MOV A buttons 5 6 3 Indexed Ind
94. trol read sequence and Firmware responds by sending its Device descriptor over the USB bus 9 The host generates control reads from the device to request the Configuration and Report descriptors 10 Once the device receives a Set Configuration request its functions may now be used 11 Following enumeration as a hub Firmware can optionally indicate to the host that a compound device exists for example the keyboard in a keyboard hub device 12 The host carries out the enumeration process with this additional function as though it were attached downstream from the hub 13 When the host assigns an address to this device it is stored as the other USB address for example Address A 16 0 USB Hub A USB hub is required to support Connectivity behavior service connect disconnect detection Bus fault detection and recovery Full Low speed device support These features are mapped onto a hub repeater and a hub controller The hub controller is supported by the processor integrated into the CY7C65113C microcontroller The hardware in the hub repeater detects whether a USB device is connected to a downstream port The connection to a downstream port is through a differential signal pair D and D Each downstream port provided by the hub requires external Rypn resistors from each signal line to ground so that when a downstream port has no device connected the hub reads a LOW zero on both D and D This condition is used to identify the n
95. tus and Control register bits are defined in Table 12 1 with a more detailed description following Table 12 1 DC Status and Control Register Bit Definitions Bit Name Description 0 IC Enable When set to 1 the I C compatible function is enabled When cleared IC GPIO pins operate normally 1 Received Stop Reads 1 only in slave receive mode when Ko Stop bit detected unless firmware did not ACK the last transaction 2 ARB Lost Restart Reads 1 to indicate master has lost arbitration Reads 0 otherwise Write to 1 in master mode to perform a restart sequence also set Continue bit 3 Addr Reads 1 during first byte after start restart in slave mode or if master loses arbitration Reads 0 otherwise This bit should always be written as O 4 ACK In receive mode write 1 to generate ACK 0 for no ACK In transmit mode reads 1 if ACK was received 0 if no ACK received 5 Xmit Mode Write to 1 for transmit mode 0 for receive mode Document 38 08002 Rev D Page 21 of 49 Feedback 7 CYPRESS CY7C65113C PERFORM Table 12 1 DC Status and Control Register Bit Definitions continued Bit Name Description 6 Continue Busy Write 1 to indicate ready for next transaction Reads 1 when I C compatible block is busy with a transaction 0 when transaction is complete 7 MSTR Mode Write to 1 for master mode 0 for slave mode This bit is cleared if master loses arbitration Clearing fr
96. u Input Hysteresis Voltage All ports high to low edge 2 8 Vec VoL Port 0 1 Output Low Voltage lop 3 mA 0 4 V lo 8 mA 2 0 V Vou Output High Voltage lop 1 9 mA all ports 0 1 24 V Notes 8 Add 18 mA per driven USB cable upstream or downstream This is based on transitions every 2 full speed bit times on average 9 Power on Reset occurs whenever the voltage on Vcc is below approximately 2 5V Document 38 08002 Rev D Page 46 of 49 Feedback CYPRESS CY7C65113C PERFORM 23 0 Switching Characteristics fosc 6 0 MHz Parameter Description Min Max Unit Clock Source fosc Clock Rate 6 0 25 MHz teye Clock Period 166 25 167 08 ns tcu Clock HIGH time 0 45 teyc ns teL Clock LOW time 0 45 teyc ns USB Full speed Signaling trts Transition Rise Time 4 20 ns tifs Transition Fall Time 4 20 ns tfmfs Rise Fall Time Matching db 90 111 t ratefs Full Speed Date Rate 12 0 25 Mb s Timer Signals twatch Watchdog Timer Period 8 192 14 336 ms Note 10 Per Table 7 6 of revision 1 1 of USB specification CLOCK Document 38 08002 Rev D Page 47 of 49 Feedback YPRES CY7C65113C PERFORM 24 0 Ordering Information Ordering Code PROM Size Package Type Operating Range CY7C65113C SXC 8KB 28 pin SOIC Commercial CY7C65113C SXCT 8 KB 28 pin SOIC Tape Reel Commercial 25 0 Package Diagram
97. upt 4 M 4 Byte Count bits 0 5 Figtire 17 4 Endpoint Mode Data Valid bit 6 Figure 17 4 SIE s Response encoding to the Host Received Token Data0 1 bit Figure 17 4 SETUP IN OUT PID Status Bits Endpoint Mode bits The validity of the received data Bit 7 5 Figure 17 2 Changed by the SIE The quality status of the DMA buffer The number of received bytes Acknowledge phase completed Legend TX transmit UC unchanged RX receive TXO Transmit 0 length packet Teese for Control endpoint only x don t care The response of the SIE can be summarized as follows 1 The SIE will only respond to valid transactions and will ignore non valid ones 2 The SIE will generate an interrupt when a valid transaction is completed or when the FIFO is corrupted FIFO corruption occurs during an OUT or SETUP transaction to a valid internal address that ends with a non valid CRC An incoming Data packet is valid if the count is Endpoint Size 2 includes CRC and passes all error checking An IN will be ignored by an OUT configured endpoint and visa versa The IN and OUT PID status is updated at the end of a transaction The SETUP PID status is updated at the beginning of the Data packet phase o0 A Oo The entire Endpoint 0 mode register and the Count register are locked to CPU writes at the end of any transaction to that endpoint in which
98. wnstream Ports Control Register Table 16 1 Control Bit Definition for Downstream Ports Control Bits Bit1 Bit 0 Control Action 0 0 Not Forcing Normal USB Function Force Differential 1 D HIGH D LOW Force Differential 0 D LOW D HIGH 0 1 1 0 1 1 Force SEO state An alternate means of forcing the downstream ports is through the Hub Ports Force Low Register Figure 16 5 Register With this register the pins of the downstream ports can be individually forced LOW or left unforced Unlike the Hub Downstream Ports Control Register above the Force Low Register does not produce standard USB edge rate control on the forced pins However this register allows downstream port pins to be held LOW in suspend This register can be used to drive SEO on all downstream ports when unconfigured as required in the USB 1 1 specification Hub Ports Force Low Bit 7 Address 0x51 Figure 16 5 Hub Ports Force Low Register 6 5 4 3 2 1 0 Bit Name Force Low Force Low Force Low Force Low Force Low Force Low Force Low Force Low D 4 D 4 D 3 D 3 D 2 D 2 D 1 D 1 Read Write R W R W R W R W R W R W R W R W Reset 0 0 0 0 0 0 0 0 The data state of downstream ports can be read through the HUB Ports SEO Status Register Figure 16 6 and the Hub Ports Data Register Figure 16 7 The data read from the Hub Ports Data Register is the differential data o

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