Cypress CY7C1516KV18 User's Manual
Contents
1. 1 2 3 4 5 6 7 8 9 10 11 A ca A A R W NWS K NC 144M LD A A CO B NC NC NC A NC 288M K NWS A NC NC DQ3 e NC NC NC Vss A A A Vss NC NC NC D NC NC NC Mas Vss Vss Vss Vss NC NC NC E NC NC DQ4 VDDQ Vss Vss Vss Vppa NC NC DQ2 F NC NC NC Vida Von Vss Soe Mop NC NC NC G NC NC DQ5 Vppa Vpp Vss Vop Vppa NC NC NC H DOFF Ver Vopa Vppo Von Vss Vop Vopa Vopa VREF ZQ J NC NC NC VDDQ Vop Vss Mop Vppa NC DO1 NC K NC NC NC Voba Von Vss Me VDDQ NC NC NC L NC DO6 NC Vppa Vss Vss Vss Vppa NC NC DQO M NC NC NC Vss Vss Vss Vss Vss NC NC NC N NC NC NC Vss A A A Vss NC NC NC P NC NC DQ7 A A C A A NC NC NC R TDO TCK A A A C A A A TMS TDI CY7C1527KV18 8M x 9 1 2 3 4 5 6 7 8 9 10 11 A CQ A A R W NC K NC 144M LD A A CO B NC NC NC A NC 288M K BWSg A NC NC DO3 C NC NC NC Vss A A A Vss NC NC NC D NC NC NC Vss Vss Vss Vss Vss NC NC NC E NC NC DQ4 Vppa Vss Vss Vss Vppa NC NC DQ2 F NC NC NC Vppa Vni Vss Ke Vppa NC NC NC G NC NC DQ5 VDDQ Vpp Vss Vpp Vppa NC NC NC H DOFF VREF VDDQ VDDQ VDD Vss VDD VDDQ VDDQ VREF ZQ J NC NC NC Vopa Vop Vss Von Vppa NC DO1 NC K NC NC NC Vopa Mag Vss Me Vppa NC NC NC L NC DQ6 NC VDDQ Vss Vss Vss Vppa NC NC DQO M NC NC NC Vss Vss Vss Vss Vss NC NC NC N NC NC NC Vss A A A Vss NC NC NC P NC NC DQ7 A A C A A NC NC DO8 R TDO TCK A A A A A A TMS TDI Note 1 NC 144M and NC 288M are not connected to the die and can be tied to any voltage level Document Number 001 00437 Rev E Pa2. 0 50 ns ise tcap tcaHav Echo Clock High to Data Valid 10 251 027 030 035 0 40 ns tcoDoH tcoHox Echo Clock High to Data Invalid 0 25 027 030 0 335 0 40 ns tcou tcoHcat Output Clock CQ CQ HIGH PSI 125 140 175 225 275 ns tcoHcOH coHcaH CQ Clock Rise to CQ Clock Rise 1 25 140 175 225 275 ns rising edge to rising edge tcuz tcHoz Clock C C Rise to GN Z 10 451 045 045 045 0 50 ns Active to High Z l terz tcHax1 Clock C C Rise to Low Z 4 251 9 45 o45 0 45 045 0 50 ns PLL Timing tke var tkc var Clock Phase Jitter 1020 020 020 020 0 20 ns Der lock Der lock PLL Lock Time K C 20 20 20 20 20 us lkC Reset Der Reset K Static to PLL Reset 30 30 30 30 30 ns Notes 23 These parameters are extrapolated from the input timing parameters tcyc 2 250 ps where 250 ps is the internal jitter These parameters are only guaranteed by design and are not tested in production 24 tenz tcz are specified with a load capacitance of 5 pF as in b of AC Test Loads and Waveforms Transition is measured 100 mV from steady state voltage 25 At any voltage and temperature toyz is less than tc 7 and toyz less than tco Document Number 001 00437 Rev E Page 24 of 30 Feedback y CY7C1516KV18 CY7C1527KV18 YPRESS CY7C1518K
3. Feedback YPRESS PERFORM Mi Ma Functional Overview The CY7C1516KV18 CY7C1527KV18 CY7C1518KV18 and CY7C1520KV18 are synchronous pipelined Burst SRAMs equipped with a DDR interface which operates with a read latency of one and a half cycles when DOFF pin is tied HIGH When DOFF pin is set LOW or connected to Vgg the device behaves in DDR I mode with a read latency of one clock cycle Accesses are initiated on the rising edge of the positive input clock K All synchronous input timing is referenced from the rising edge of the input clocks K and K and all output timing is referenced to the rising edge of the output clocks C C or K K when in single clock mode All synchronous data inputs Dr al pass through input registers controlled by the rising edge of the input clocks K and K All synchronous data outputs Ur au pass through output registers controlled by the rising edge of the output clocks C C or K K when in single clock mode All synchronous control R W LD BWS o xj inputs pass through input registers controlled by the rising edge of the input clock K CY7C1518KV18 is described in the following sections The same basic descriptions apply to CY7C1516KV18 CY7C1527KV18 and CY7C1520KV18 Read Operations The CY7C1518KV18 is organized internally as a two arrays of 2M x 18 Accesses are completed in a burst of 2 sequential 18 bit data words Read operations are initiated by asserting R W HIGH
4. 035 04 05 ns Clock K K Rise BWSo BWS BWS5 BWS3 tup tkHDx Dpco Hold after Clock K K Rise 0 3 103 035 04 05 ns Notes 21 When a part with a maximum frequency above 167 MHz is operating at a lower clock frequency it requires the input timings of the frequency range in which it is operated and outputs data with the output timings of that frequency range 22 This part has an internal voltage regulator tpowe is the time that the power is supplied above Vpp min initially before a read or write operation can be initiated Document Number 001 00437 Rev E Page 23 of 30 Feedback PERFORM Switching Characteristics continued Over the Operating Range 20 21 CY7C1516KV18 CY7C1527KV18 CY7C1518KV18 CY7C1520KV18 Cypress Gonsortium Description MHz 200 MHz gen MHz 200 MHz e MHz Jm in Max Min Max Min Max Min Max Min Max Output Times tco tcHov C C Clock Rise or K K in single 10451 1045 045 O45 0 50 ns clock mode to Data Valid tpou tcHax Data Output Hold after Output C C 0 45 0 45 0 45 045 0 50 ns Clock Rise Active to Active tccoo tcHcov C C Clock Rise to Echo Clock Valid 0 45 0 45 045 045 0 50 ns tcooH tcucox E Clock Hold after C C Clock 0 45 0 45 0 45 0 45
5. CY7C1518KV18 only the lower byte Djg o Is written into the device D 7 9 remains unaltered L H L H During the data portion of a write sequence CY7C1516KV18 only the lower nibble D g oj is written into the device Dr7 4j remains unaltered CY7C1518KV18 only the lower byte Dr al is written into the device Du o remains unaltered H L L H During the data portion of a write sequence CY7C1516KV18 only the upper nibble Dr al is written into the device Dr o remains unaltered CY7C1518KV18 only the upper byte Dara is written into the device Djg o remains unaltered H L L H During the data portion of a write sequence CY7C1516KV18 only the upper nibble Dr Al is written into the device Dr o remains unaltered CY7C1518KV18 only the upper byte Dara is written into the device Dr a remains unaltered H H L H No data is written into the devices during this portion of a write operation H H L H No data is written into the devices during this portion of a write operation Notes 2 X Don t Care H Logic HIGH L Logic LOW f represents rising edge 3 Device powers up deselected with the outputs in a tristate condition 4 On CY7C1518KV18 and CY7C1520KV18 A1 represents address location latched by the devices when transaction was initiated and A2 represents the addresses sequence in the burst On CY7C1516KV18 and CY7C1527KV18 A1 repre
6. Write Cycle Descriptions The write cycle description table for CY7C1520KV18 follows gt 8 BWS BWS BWS BWS K K Comments L L L L L H During the data portion of a write sequence all four bytes Dr35 9j are written into the device L L L L L H During the data portion of a write sequence all four bytes Urs ol are written into the device L H H H L H During the data portion of a write sequence only the lower byte Djg o is written into the device Droe o remains unaltered L H H H L H During the data portion of a write sequence only the lower byte Djg o is written into the device Drea remains unaltered H L H H L H During the data portion of a write sequence only the byte Dr17 9j is written into the device Drg oj and Dee remains unaltered H L H H L H During the data portion of a write sequence only the byte D 47 gj is written into the device Drg oj and Droe remains unaltered H H L H L H During the data portion of a write sequence only the byte Dpe 18 is written into the device Dr7 o and Djg5 27 remains unaltered H H L H L H During the data portion of a write sequence only the byte D 26 1gj is written into the device Dr47 oj and Djg5 27 remains unaltered H H H L L H During the data portion of a write sequence only the byte D 35 27 is written into the device De o remains unaltered H H H L L H Durin
7. Do Document Number 001 00437 Rev E Page 2 of 30 Feedback m x CY7C1516KV18 CY7C1527KV18 CY7C1518KV18 CY7C1520KV18 PERFORM Logic Block Diagram CY7C1518KV18 A0 af Write Write 22 hein Be Address z Register ki M N g 18 LD o lt lt 9 A x x A S oo o 3 K E gt gt lt K N 2 9 9 3 gt Gen ok ZS DOFF l gt Read Data Reg 36 VREF gt gt gt ca RW Control gt CO YY 18 BWS rg P gt lt a gt 0017 0 Do Logic Block Diagram CY7C1520KV18 Y T Write N Write A 20 0 Reg Reg Address pe S Register 2 ke A E o 8 z z 8 36y o x x o a a sl 8 8 s 2 3 5 a Output R W 2 2 8 Logic z ha DOFF l gt Read Data Reg Ps D gt ca ca 36 ee ae DO 35 0 Document Number 001 00437 Rev E Page 3 of 30 Feedback Lc CY7C1516KV18 CY7C1527KV18 ESL CYPRESS CY7C1518KV18 CY7C1520KV18 PERFORM Pin Configuration The pin configurations for CY7C1516KV18 CY7C1527KV18 CY7C1518KV18 and CY7C1520KV18 follow 1 165 Ball FBGA 13 x 15 x 1 4 mm Pinout CY7C1516KV18 8M x 8
8. 11 1 identification of SRAM vendor ID Register 1 1 1 1 Indicates the Presence 0 presence of an ID register Scan Register Sizes Register Name Bit Size Instruction 3 Bypass 1 ID 32 Boundary Scan 109 Instruction Codes Instruction Code Description EXTEST 000 Captures the input and output ring contents IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO This operation does not affect SRAM operation SAMPLE Z 010 Captures the input and output contents Places the boundary scan register between TDI and TDO Forces all SRAM output drivers to a High Z state RESERVED 011 Do Not Use This instruction is reserved for future use SAMPLE PRELOAD 100 Captures the input and output ring contents Places the boundary scan register between TDI and TDO Does not affect the SRAM operation RESERVED 101 Do Not Use This instruction is reserved for future use RESERVED 110 Do Not Use This instruction is reserved for future use BYPASS 111 Places the bypass register between TDI and TDO This operation does not affect SRAM operation Document Number 001 00437 Rev E Page 17 of 30 Feedback Boundary Scan Order PERFORM CY7C1516KV18 CY7C1527KV18 CY7C1518KV18 CY7C1520KV18 Bit Bump ID Bit Bump ID Bit Bump I
9. 333 MHz 300MHz 250 MHz 200 MHz 167 MHz P SEI Parameter dA Min Max Min Max Min Max Min Max Min Max SC tPOWER Vpp Typical to the First Access 22 4 1 1 1 1 ms tcvc tKHKH K Clock and C Clock Cycle Time 3 0 84 3 3 84 4 0 84 5 0 8 4 6 0 84 ns Det tKHKL Input Clock K K and C C HIGH 1 20 1132 16 20 24 ns tkL tKLKH Input Clock K K and C C LOW 120 132 16 20 24 ns tKHKH tkHKH K Clock Rise to K Clock Rise and C 1 35 149 18 22 27 ns to C Rise rising edge to rising edge tKHCH tkHcH K K Clock Rise to C C Clock Rise 0 0 1 30 0 0 1 45 0 0 1 8 0 0 2 2 0 0 27 ns rising edge to rising edge Setup Times tsa tAVKH Address Setup to K Clock Rise 04 O4 1051 06 07 ns tsc tivKH Control Setup to K Clock Rise 04 04 05 06 07 ns LD R W tscDDR tivkH Double Data Rate Control Setup to 0 3 1037 035 04 05 ns Clock K K Rise BWSp BWS BWS5 BWS3 tsp tovKH Dro Setup to Clock K K Rise 0 3 03 035 04 05 ns Hold Times tha tKHAX Address Hold after K Clock Rise 04 04 05 06 07 ns tuc tkHIx Control_Hold after K Clock Rise 04 O4 1051 06 07 ns LD R W tuCDDR tkHIX Double Data Rate Control Holdafter 0 3 03
10. This pin may be left unconnected if the TAP is not used The pin is pulled up inter nally resulting in a logic HIGH level Test Data ln TDI The TDI pin is used to serially input information into the registers and can be connected to the input of any of the registers The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register For information about loading the instruction register see the TAP Controller State Diagram on page 14 TDI is internally pulled up and can be unconnected if the TAP is unused in an application TDI is connected to the most significant bit MSB on any register Test Data Out TDO The TDO output pin is used to serially clock data out from the registers The output is active depending upon the current state of the TAP state machine see Instruction Codes on page 17 The output changes on the falling edge of TCK TDO is connected to the least significant bit LSB of any register Performing a TAP Reset A Reset is performed by forcing TMS HIGH Vpp for five rising edges of TCK This Reset does not affect the operation of the SRAM and is performed when the SRAM is operating At power up the TAP is reset internally to ensure that TDO comes up in a High Z state TAP Registers Registers are connected between the TDI and TDO pins to scan the data in and out of the SRAM test circuitry Only one register can be selected at a time through the instruction regis
11. and LD LOW at the rising edge of the positive input clock K The address presented to address inputs is stored in the read address register and the least significant bit of the address is presented to the burst counter The burst counter increments the address in a linear fashion Following the next K clock rise the corresponding 18 bit word of data from this address location is driven onto the Ou o using C as the output timing reference On the eibsequcnt rising edge of C the next 18 bit data word from the address location generated by the burst counter is driven onto the Qji7 0 The requested data is valid 0 45 ns from the rising edge of the output clock C or C or K and K when in single clock mode 200 MHz 250 MHz and 300 MHz device To maintain the internal logic each read access must be allowed to complete Read accesses can be initiated on every rising edge of the positive input clock K When read access is deselected the CY7C1518KV18 first completes the pending read transactions Synchronous internal circuitry automatically tristates the output following the next rising edge of the positive output clock C This enables for a transition between devices without the insertion of wait states in a depth expanded memory Write Operations Write operations are initiated by asserting R W LOW and LD LOW at the rising edge of the positive input clock K The address presented to address inputs is stored in the write address registe
12. instruction register through the TDI and TDO pins To execute the instruction after it is shifted in the TAP controller must be moved into the Update IR state Page 12 of 30 Feedback PERFORM The IDCODE instruction loads a vendor specific 32 bit code into the instruction register It also places the instruction register between the TDI and TDO pins and shifts the IDCODE out of the device when the TAP controller enters the Shift DR state The IDCODE instruction is loaded into the instruction register at power up or whenever the TAP controller is supplied a Test Logic Reset state SAMPLE Z The SAMPLE Z instruction connects the boundary scan register between the TDI and TDO pins when the TAP controller is in a Shift DR state The SAMPLE Z command puts the output bus into a High Z state until the next command is supplied during the Update IR state SAMPLE PRELOAD SAMPLE PRELOAD is a 1149 1 mandatory instruction When the SAMPLE PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture DR state a snapshot of data on the input and output pins is captured in the boundary scan register The TAP controller clock can only operate at a freguency up to 20 MHz while the SRAM clock operates more than an order of magnitude faster Because there is a large difference in the clock freguencies it is possible that during the Capture DR state an input or output undergoes a transition The TAP ma
13. lists all possible speed package and temperature range options supported for these devices Note that some options listed may not be available for order entry To verify the availability of a specific option visit the Cypress website at www cypress com and refer to the product summary page at hitp www cypress com products or contact your local sales representative for the status of availability of parts Cypress maintains a worldwide network of offices solution centers manufacturer s representatives and distributors To find the office closest to you visit us at http app cypress com portal server pt space CommunityPage amp control SetCommunity amp CommunityID 201 amp PageID 230 Table 2 Ordering Information Speed MHz Ordering Code Package Diagram Package Type Operating Range 333 CY7C1516KV18 333BZC CY7C1527KV18 333BZC CY7C1518KV18 333BZC CY7C1520KV18 333BZC 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm CY7C1516KV18 333BZXC CY7C1527KV18 333BZXC CY7C1518KV18 333BZXC CY7C1520KV18 333BZXC 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb Free Commercial CY7C1516KV18 333BZI CY7C1527KV18 333BZI CY7C1518KV18 333BZI CY7C1520KV18 333BZI 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Industrial CY7C1516KV18 333BZXI CY7C1527KV18 333BZXI CY7C1518KV18 333BZXI CY7C1520
14. ns tcH Capture Hold after Clock Rise 5 ns Output Times trpov TCK Clock LOW to TDO Valid 10 ns trpox TCK Clock LOW to TDO Invalid 0 ns TAP Timing and Test Conditions Figure 2 shows the TAP timing and test conditions 14 Figure 2 TAP Timing and Test Conditions 0 9V ALL INPUT PULSES 1 8V 0 9V TDO OV dp L c 20pF a GND tty tre p NEN Test Clock N N TCK trcvc trusH rm dM trMss 48 a a Test Mode Select TMS WK YG trpis i TDIH tl m UK A ZA 1 MZ TDI Test Data Out TDO 4 A trpov XS trpox Notes 13 tes and tcp refer to the setup and hold time requirements of latching data from the bou 14 Test conditions are specified using the load in TAP AC Test Conditions tp te 1 ns Document Number 001 00437 Rev E ndary scan register Page 16 of 30 Feedback PER FORM Identification Register Definitions CY7C1516KV18 CY7C1527KV18 CY7C1518KV18 CY7C1520KV18 Value Instruction Field Description CY7C1516KV18 CY7C1527KV18 CY7C1518KV18 CY7C1520KV18 Revision Number 000 000 000 000 Version number 31 29 Cypress Device ID 11010100010000100 11010100010001100 11010100010010100 11010100010100100 Defines the type of 28 12 SRAM Cypress JEDEC ID 00000110100 00000110100 00000110100 00000110100 Allows unigue
15. oO o d oo oo d preoooo dooooo 3 ooooooooooo ooooo6ooooo oooooo ooooo ooooooooooo oooooo9oooooo g a s o 5 o e e o 8 oooooo ooooo E ooooo ooooo ooooooooooo R oooooo ooooo ooooo6ooooo ooooooooooo 600000000996 A Sa a 10 00 B Ha 13 00 0 10 C 0 15 4X SOLDER PAD TYPE NON SOLDER MASK DEFINED NSMD PACKAGE WEIGHT 0 475g JEDEC REFERENCE MO 216 DESIGN 4 6C PACKAGE CODE BBOAC 51 85180 A Page 29 of 30 Feedback pd CY7C1516KV18 CY7C1527KV18 ESL CYPRESS CY7C1518KV18 CY7C1520KV18 PERFORM LM L Document History Page Document Title CY7C1516KV18 CY7C1527KV18 CY7C1518KV18 CY7C1520KV18 72 Mbit DDR II SRAM 2 Word Burst Architecture Document Number 001 00437 Rev ECN No Orig of Submission Description of Change Change Date We 374703 SYT See ECN New Data Sheet A 1103864 VKN See ECN Updated Ipp spec Updated ordering information table B 1699246 VKN AESA See ECN Converted from Advance Information to Preliminary C 1939726 VKN AESA See ECN Changed PLL lock time from 1024 cycles to 20 us Added footnote 19 related to Ipp Corrected typo in the footnote 23 D 2606839 VKN PYRS 11 13 08 Changed JTAG ID 31 29 from 001 to 000 Updated power up sequence waveform and its description Changed Ambient Temperature with Power Applied from 10 C to 85 C to 55 C to 125 C in the Maximum Ratings on page 20 In
16. or process change that may affect these parameters Parameter Description Test Conditions Max Unit CiN Input Capacitance TA 25 C f 1 MHz Vpp 1 8V Vppa 1 5V 2 pF Co Output Capacitance 3 pF Thermal Resistance Tested initially and after any design or process change that may affect these parameters S 165 FBGA R Parameter Description Test Conditions Package Unit OJA Thermal Resistance Test conditions follow standard test methods and 13 7 C W Junction to Ambient procedures for measuring thermal impedance in Em Thermal Resistance accordance with EIA JESD51 373 C W Junction to Case Figure 4 AC Test Loads and Waveforms VREF 0 75V Vace o 075V OUTPUT VREF t e 0 75V R 50Q 20 ALL INPUT PULSES TN S R 50q OUTPUT 1 25V Under Device am N Test Under 5pF 025V VREF 0 75V ect ZQ T Slew Rate 2 V ns ZQ T RQ L 250Q 250Q a INCLUDING JIGAND b SCOPE Note 20 Unless otherwise noted test conditions assume signal transition time of 2V ns timing reference levels of 0 75V Veer 0 75V RQ 2500 Vppa 1 5V input pulse levels of 0 25V to 1 25V and output loading of the specified lo Tou and load capacitance shown in a of AC Test Loads and Waveforms Page 22 of 30 Document Number 001 00437 Rev E Feedback Lc CY7C1516KV18 CY7C1527KV18 ESL CYPRESS CY7C1518KV18 CY7C1520KV18 PERFORM Switching Characteristics Over the Operating Range 20 21
17. register is placed between the TDI and TDO pins The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board EXTEST The EXTEST instruction drives the preloaded data out through the system output pins This instruction also connects the boundary scan register for serial access between the TDI and TDO in the Shift DR controller state EXTEST OUTPUT BUS TRISTATE IEEE Standard 1149 1 mandates that the TAP controller be able to put the output bus into a tristate mode The boundary scan register has a special bit located at bit 108 When this scan cell called the extest output bus tristate is latched into the preload register during the Update DR state in the TAP controller it directly controls the state of the output O bus pins when the EXTEST is entered as the current instruction When HIGH it enables the output buffers to drive the output bus When LOW this bit places the output bus into a High Z condition This bit is set by entering the SAMPLE PRELOAD or EXTEST command and then shifting the desired bit into that cell during the Shift DR state During Update DR the value loaded into that shift register cell latches into the preload register When the EXTEST instruction is entered this bit directly controls the output O bus pins Note that this bit is preset HIGH to enable the output when the device is powered up and also when the TAP control
18. the read s the stored data from the earlier write is written into the SRAM array This is called a posted write If a read is performed on the same address on which a write is performed in the previous cycle the SRAM reads out the most current data The SRAM does this by bypassing the memory array and reading the data from the registers Depth Expansion Depth expansion requires replicating the LD control signal for each bank All other control signals can be common between banks as appropriate Page 8 of 30 Feedback PERFORM Programmable Impedance An external resistor RO must be connected between the ZO pin on the SRAM and Vss to allow the SRAM to adjust its output driver impedance The value of RO must be 5x the value of the intended line impedance driven by the SRAM The allowable range of RO to guarantee impedance matching with a tolerance of 15 is between 1750 and 3500 with Vppo 1 5V The output impedance is adjusted every 1024 cycles upon power up to account for drifts in supply voltage and temperature Echo Clocks Echo clocks are provided on the DDR II to simplify data capture on high speed systems Two echo clocks are generated by the DDR II CO is referenced with respect to C and CO is referenced with respect to C These are free running clocks and are synchro nized to the output clock of the DDR II In single clock mode CO is generated with respect to K and CO is generated with respect to K The timing
19. 1518KV18 CY7C1520KV18 PERFORM Truth Table The truth table for the CY7C1516KV18 CY7C1527KV18 CY7C1518KV18 and CY7C1520KV18 follow Z 3 4 5 6 7 Operation K LD R W DQ DQ Write Cycle L H L L D A1 at K t 1 T D A2 at K t 1 1 Load address wait one cycle E input write data on consecutive K and K rising edges Read Cycle L H L H Load address wait one and a half cycle read data on consecutive C and C rising edges Q A1 at C t 1 Q A2 at C t 2 NOP No Operation L H H X High Z High Z Standby Clock Stopped Stopped X X Previous State Previous State Burst Address Table CY7C1518KV18 CY7C1520KV18 First Address External Second Address Internal X X0 X X1 X X1 X X0 Write Cycle Descriptions The write cycle description table for CY7C1516KV18 and CY7C1518KV18 follows 2 8l BWSy BWS4 eu ia K K Comments NWS NWS L L L H During the data portion of a write sequence CY7C1516KV18 both nibbles Dro are written into the device CY7C1518KV18 both bytes i Ol are written into the device L L L H During the data portion of a write sequence CY7C1516KV18 both nibbles Djz oj are written into the device CY7C1518KV18 both bytes Ba are written into the device L H L H During the data portion of a write sequence CY7C1516KV18 only the lower nibble Dr o is written into the device Dr A remains unaltered
20. 9 for CY7C1527KV18 4M x 18 2 arrays each of 2M x 18 for CY7C1518KV18 and 2M x 36 2 arrays each of 1M x 36 for CY7C1520KV18 CY7C1516KV18 Since the least significant bit of the address internally is a O only 22 external address inputs are needed to access the entire memory array CY7C1527KV18 Since the least significant bit of the address internally is a O only 22 external address inputs are needed to access the entire memory array CY7C1518KV18 AQ is the input to the burst counter These are incremented in a linear fashion internally 22 address inputs are needed to access the entire memory array CY7C1520KV18 AO is the input to the burst counter These are incremented in a linear fashion internally 21 address inputs are needed to access the entire memory array All the address inputs are ignored when the appropriate port is deselected R W Input Synchronous Read or Write Input When LD is LOW this input designates the access type read when Synchronous R W is HIGH write when R W is LOW for loaded address R W must meet the setup and hold times around edge of K C Input Clock Positive Input Clock for Output Data C is used in conjunction with C to clock out the read data from the device C and C can be used together to deskew the flight times of various devices on the board back to the controller See application example for further details C Input Clock Negative Input Clock for Output Data C is used in conj
21. Array 13 x 15 x 1 4 mm Commercial CY7C1527KV18 250BZC CY7C1518KV18 250BZC CY7C1520KV18 250BZC CY7C1516KV18 250BZXC 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb Free CY7C1527KV18 250BZXC CY7C1518KV18 250BZXC CY7C1520KV18 250BZXC 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Industrial 200 CY7C1516KV18 200BZC CY7C1527KV18 200BZC CY7C1518KV18 200BZC CY7C1520KV18 200BZC 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm CY7C1516KV18 200BZXC CY7C1527KV18 200BZXC CY7C1518KV18 200BZXC CY7C1520KV18 200BZXC CY7C1516KV18 200BZI CY7C1527KV18 200BZI CY7C1518KV18 200BZI CY7C1520KV18 200BZI 51 85180 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb Free 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Commercial Industrial CY7C1516KV18 200BZXI CY7C1527KV18 200BZXI CY7C1518KV18 200BZXI CY7C1520KV18 200BZXI 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb Free Document Number 001 00437 Rev E Page 27 of 30 Feedback PERFORM Table 2 Ordering Information continued CY7C1516KV18 CY7C1527KV18 CY7C1518KV18 CY7C1520KV18 CY7C1527KV18 167BZC CY7C1518KV18 167BZC CY7C1520KV18 167BZC Speed Package Operating MHz Ordering Code Diagram Package Type Range 167 CY7C1516KV18 167BZC 51 85180 165
22. Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Commercial CY7C1516KV18 167BZXC CY7C1527KV18 167BZXC CY7C1518KV18 167BZXC CY7C1520KV18 167BZXC 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb Free CY7C1516KV18 167BZI CY7C1527KV18 167BZI CY7C1518KV18 167BZI CY7C1520KV18 167BZI CY7C1516KV18 167BZXI CY7C1527KV18 167BZXI CY7C1518KV18 167BZXI CY7C1520KV18 167BZXI 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb Free Industrial Document Number 001 00437 Rev E Page 28 of 30 Feedback PERFORM Package Diagram CY7C1516KV18 CY7C1527KV18 CY7C1518KV18 CY7C1520KV18 Figure 6 165 Ball FBGA 13 x 15 x 1 4 mm 51 85180 TOP VIEW x PIN 1 CORNER Pran 15 00 0 10 gt o zgra Bt 13 00 0 10 0 53 0 05 140 MAX m 025 C BOTTOM VIEW PIN 1 CORNER L 9005MC V go25MC B 90 50 85x 0 14 Ss o D EI 6 5 4 3 D 0 15 C al SEATING PLANE 0 36 Document Number 001 00437 Rev E 0 35 0 06 NOTES 1 le oO oO
23. C Applied to Outputs in High Z 0 5V to Vppa 0 3V Industrial 40 C to 85 C VoD DC Input Voltage N 0 5V to Vpp 0 3V Electrical Characteristics DC Electrical Characteristics Over the Operating Range 12 Parameter Description Test Conditions Min Typ Max Unit Vpp Power Supply Voltage 1 7 1 8 1 9 V Vppa IO Supply Voltage 1 4 1 5 Vpp V Vou Output HIGH Voltage Note 16 Vppo 2 0 12 Vppo 2 0 12 V VoL Output LOW Voltage Note 17 Vppo 2 0 12 Vppo 2 012 V VoH Low Output HIGH Voltage lou z 0 1 mA Nominal Impedance Vppo 0 2 Vppa V VouLow Output LOW Voltage lon 0 1 mA Nominal Impedance Vss 0 2 V VIH Input HIGH Voltage Vner 0 1 Vppa 0 3 V Vu Input LOW Voltage 0 3 Vner 0 1 V Ix Input Leakage Current GND lt Vi lt Vppa 5 5 LA loz Output Leakage Current GND lt V lt Vppa Output Disabled 5 5 LA VREF Input Reference Voltage Typical Value 0 75V 0 68 0 75 0 95 V Ibp FI Vpp Operating Supply Von Max 333 MHz x8 510 mA GE a E am x18 520 x36 640 300MHz x8 480 mA x9 480 x18 490 x36 600 250MHz x8 420 mA x9 420 x18 430 x36 530 Notes 16 Outputs are impedance controlled lou Vpn for values of 1750 lt R 3 00 POs PP 17 Outputs are impedance controlled lo Vppq 2 RQ 5 for values of 1750 lt RO lt 3500 19 The operation currentis calodated with 50 read cy
24. D Bit ff Bump ID 0 6R 28 10G 56 6A 84 1J 1 6P 29 9G 57 5B 85 2J 2 6N 30 11F 58 5A 86 3K 3 7P 31 11G 59 4A 87 3J 4 7N 32 9F 60 5C 88 2K 5 7R 33 10F 61 4B 89 1K 6 8R 34 11E 62 3A 90 2L 7 8P 35 10E 63 2A 91 3L 8 9R 36 10D 64 1A 92 1M 9 11P 37 9E 65 2B 93 1L 10 10P 38 10C 66 3B 94 3N 11 10N 39 11D 67 1C 95 3M 12 9P 40 9C 68 1B 96 1N 13 10M 41 9D 69 3D 97 2M 14 11N 42 11B 70 3C 98 3P 15 9M 43 11C 71 1D 99 2N 16 9N 44 9B 72 2C 100 2P 17 11L 45 10B 73 3E 101 1P 18 11M 46 11A 74 2D 102 3R 19 9L 47 10A 75 2E 103 4R 20 10L 48 9A 76 1E 104 4P 21 11K 49 8B TT 2F 105 5P 22 10K 50 7C 78 3F 106 5N 23 9J 51 6C 79 1G 107 5R 24 9K 52 8A 80 1F 108 Internal 25 10J 53 7A 81 3G 26 11J 54 7B 82 2G 27 11H 55 6B 83 1H Document Number 001 00437 Rev E Page 18 of 30 Feedback pd CY7C1516KV18 CY7C1527KV18 CY7C1518KV18 CY7C1520KV18 PERFORM Power Up Seguence in DDR II SRAM PLL Constraints m PLL uses K clock as its synchronizing input The input must DDR II SRAMs must be powered up and initialized in a h h jitt hich nad asi predefined manner to prevent undefined operations ave do Phase E Cer m The PLL functions at frequencies down to 120 MHz m f the input clock is unstable and the PLL is enabled then the Power Up Sequence PLL may lock onto an incorrect frequency causing unstable m Apply power and drive DOFF either HIGH or LOW All other inputs can be HIGH or LOW SRAM behavior To avoid
25. DQ30 DQ21 Mass Vop Vss Voo Yopa NC NC DQ5 G NC DQ31 DQ22 Vppa Vpp Vex Voo Wong NC NC DQ14 H DOFF VREF VDDQ Vopa Vpp Vss Vpp Vopa VDDQ VREF ZQ J NC NC DQ32 Vase Wea Vss Voo Vee NC DQ13 DO4 K NC NC DQ23 Vboa Voo Vss Vou Vova NC DQ12 DQ L NC peas DQ24 Vooo Vss Ves Vis Wong NC NC DQ2 M NC NC DOS Vss Vss Vex Ves Vss NC pati Dat N NC DO35 DO25 Vss A A A Vss NC NC DQ10 P NC NC DQ26 A A C A A NC DQ9 DQO R TDO TCK A A A A A A TMS TDI Document Number 001 00437 Rev E Page 5 of 30 Feedback CY7C1516KV18 CY7C1527KV18 CY7C1518KV18 CY7C1520KV18 PERFORM Pin Definitions Document Number 001 00437 Rev E Pin Name UO Pin Description DQix 0 Input Output Data Input Output Signals Inputs are sampled on the rising edge of K and K clocks during valid write Synchronous operations These pins drive out the requested data when the read operation is active Valid data is driven out on the rising edge of both the C and C clocks during read operations or K and K when in single clock mode When read access is deselected Qr are automatically tristated CY7C1516KV18 DQr gj CY7C1527KV18 Dro CY7C1518KV18 DQqy 7 0 CY7C1520KV18 DO g5 0 LD Input Synchronous Load This input is brought LOW when a bus cycle seguence is defined This definition Synchronous includes address and read write direction All transactions operate on a burst of 2
26. KV18 333BZXI 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb Free 300 CY7C1516KV18 300BZC CY7C1527KV18 300BZC CY7C1518KV18 300BZC CY7C1520KV18 300BZC 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Commercial CY7C1516KV18 300BZXC CY7C1527KV18 300BZXC CY7C1518KV18 300BZXC CY7C1520KV18 300BZXC 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb Free CY7C1516KV18 300BZI CY7C1527KV18 300BZI CY7C1518KV18 300BZI CY7C1520KV18 300BZI 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Industrial CY7C1516KV18 300BZXI CY7C1527KV18 300BZXI CY7C1518KV18 300BZXI CY7C1520KV18 300BZXI 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb Free Document Number 001 00437 Rev E Page 26 of 30 Feedback PERFORM Table 2 Ordering Information continued CY7C1516KV18 CY7C1527KV18 CY7C1518KV18 CY7C1520KV18 CY7C1516KV18 250BZI CY7C1527KV18 250BZI CY7C1518KV18 250BZI CY7C1520KV18 250BZI CY7C1516KV18 250BZXI CY7C1527KV18 250BZXI CY7C1518KV18 250BZXI CY7C1520KV18 250BZXI 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb Free Speed Package Operating MHz Ordering Code Diagram Package Type Range 250 CY7C1516KV18 250BZC 51 85180 165 Ball Fine Pitch Ball Grid
27. PERFORM Features m 72 Mbit Density 8M x 8 8M x 9 4M x 18 2M x 36 m 333 MHz Clock for High Bandwidth m 2 word Burst for reducing Address Bus Frequency m Double Data Rate DDR Interfaces data transferred at 666 MHz at 333 MHz m Two Input Clocks K and K for precise DDR Timing a SRAM uses rising edges only m Two Input Clocks for Output Data C and C to minimize Clock Skew and Flight Time mismatches m Echo Clocks CO and CQ simplify Data Capture in High Speed Systems m Synchronous Internally Self timed Writes m DDR II operates with 1 5 Cycle Read Latency when DOFF is asserted HIGH m Operates similar to DDR I Device with 1 Cycle Read Latency when DOFF is asserted LOW m 1 8V Core Power Supply with HSTL Inputs and Outputs m Variable Drive HSTL Output Buffers m Expanded HSTL Output Voltage 1 4V Vpp a Supports both 1 5V and 1 8V IO supply m Available in 165 Ball FBGA Package 13 x 15 x 1 4 mm m Offered in both Pb free and non Pb free Packages m JTAG 1149 1 compatible Test Access Port m Phase Locked Loop PLL for Accurate Data Placement Configurations CY7C1516KV18 8M x 8 CY7C1527KV18 8M x 9 CY7C1518KV18 4M x 18 CY7C1520KV18 2M x 36 Table 1 Selection Guide CY7C1516KV18 CY7C1527KV18 CY7C1518KV18 CY7C1520KV18 72 Mbit DDR II SRAM 2 Word Burst Architecture Functional Description The CY7C1516KV18 CY7C1527KV18 CY7C1518KV18 and CY7C1520KV18 are 1 8V Synchronous Pipelined S
28. RAM equipped with DDR II architecture The DDR II consists of an SRAM core with advanced synchronous peripheral circuitry and a 1 bit burst counter Addresses for read and write are latched on alternate rising edges of the input K clock Write data is registered on the rising edges of both K and K Read data is driven on the rising edges of C and C if provided or on the rising edge of K and K if C C are not provided Each address location is associated with two 8 bit words in the case of CY7C1516KV18 and two 9 bit words in the case of CY7C1527KV18 that burst sequentially into or out of the device The burst counter always starts with a 0 internally in the case of CY7C1516KV18 and CY7C1527KV18 On CY7C1518KV18 and CY7C1520KV18 the burst counter takes in the least significant bit of the external address and bursts two 18 bit words in the case of CY7C1518KV18 and two 36 bit words in the case of CY7C1520KV18 sequentially into or out of the device Asynchronous inputs include an output impedance matching input ZQ Synchronous data outputs Q sharing the same physical pins as the data inputs D are tightly matched to the two output echo clocks CQ CQ eliminating the need for separately capturing data from each individual DDR SRAM in the system design Output data clocks C C enable maximum system clocking and data synchronization flexibility All synchronous inputs pass through input registers controlled by the K or K input clocks All dat
29. TMS p TAP Electrical Characteristics Over the Operating Range HO 11 12 Parameter Description Test Conditions Min Max Unit Mou Output HIGH Voltage lou 2 0 mA 1 4 V Vou2 Output HIGH Voltage lou 100 LA 1 6 V VoL1 Output LOW Voltage lon 2 0 mA 0 4 V Voi2 Output LOW Voltage lo 100 pA 0 2 V Vin Input HIGH Voltage 0 65Vpp Vpp 0 3 V Vu Input LOW Voltage 0 3 0 35Vpp V Ix Input and Output Load Current GND lt Vi Vpp 5 5 uA Notes 10 These characteristics pertain to the TAP inputs TMS TCK TDI and TDO Parallel load levels are specified in the Electrical Characteristics Table 11 Overshoot ViH AC lt Vppa 0 85V Pulse width less than tcyc 2 Undershoot Vi AC gt 1 5V Pulse width less than tcyc 2 12 All voltage referenced to Ground Document Number 001 00437 Rev E Page 15 of 30 Feedback PERFORM TAP AC Switching Characteristics Over the Operating Range l19 14 CY7C1516KV18 CY7C1527KV18 CY7C1518KV18 CY7C1520KV18 Parameter Description Min Max Unit trcvc TCK Clock Cycle Time 50 ns trr TCK Clock Freguency 20 MHz tru TCK Clock HIGH 20 ns tn TCK Clock LOW 20 ns Setup Times ttuss TMS Setup to TCK Clock Rise 5 ns trpis TDI Setup to TCK Clock Rise 5 ns tcs Capture Setup to TCK Rise ns Hold Times trmsH TMS Hold after TCK Clock Rise 5 ns trpiH TDI Hold after Clock Rise 5
30. V18 CY7C1520KV18 PERFORM D Ew C3 Switching Waveforms Figure 5 Read Write Deselect Seguence 26 27 28 NOP READ READ NOP NOP WRITE WRITE READ 1 4 5 6 8 9 l i tkH KL oe Ka e lee N di t IA Adoos Hon E l l THD tHD 1 ASA F gt je HD 4 tsp je tsp la l i DO Q00 ao a10 Q11 D20 D21 V D30 D31 aso Q41 L w d l i e b copoH gt i l 1 FKHCH tCLZ s 1 i l lt i 1 t tcuz DOH x T l tom Re a es pi i i l CQD 1 1 l LA KM v i i fou tcyc KHKH I lat gt lt gt lt gt 1 AAA LC eee koze y Spe a ZE ot See di Q si he m sd ez a d DAL LIE Te Je CO tCQHCOQH ar DON T CARE RW UNDEFINED Notes 26 Q00 refers to output from address AO Q01 refers to output from the next internal burst address following AO that is AO 1 27 Outputs are disabled High Z one clock cycle after a NOP 28 In this example if address A4 A3 then data Q40 D30 and Q41 D31 Write data is forwarded immediately as read results This note applies to the whole diagram Document Number 001 00437 Rev E Page 25 of 30 Feedback PERFORM Ordering Information CY7C1516KV18 CY7C1527KV18 CY7C1518KV18 CY7C1520KV18 The following table
31. a outputs pass through output registers controlled by the C or C or K or K in a single clock domain input clocks Writes are conducted with on chip synchronous self timed write circuitry Description 333 MHz 300 MHz 250 MHz 200 MHz 167 MHz Unit Maximum Operating Frequency 333 300 250 200 167 MHz Maximum Operating Current x8 510 480 420 370 340 mA x9 510 480 420 370 340 x18 520 490 430 380 340 x36 640 600 530 450 400 Cypress Semiconductor Corporation Document Number 001 00437 Rev E 198 Champion Court San Jose CA 95134 1709 408 943 2600 Revised March 30 2009 Feedback m x CY7C1516KV18 CY7C1527KV18 CY7C1518KV18 CY7C1520KV18 PERFORM Logic Block Diagram CY7C1516KV18 T N Write Write A 21 0 Reg Reg Address 3 a 2 Register 9 EN g 8 LD 8 2 2 8 A a x x a kel a o kel K z 2 E 2 E o 9 9 o R W K lt lt ES z x DOFF Read Data Reg VREF D gt ca Control CO Logic gt a 007 0 Logic Block Diagram CY7C1527KV18 Y T N Write N Write Ac21 0 Reg Reg Address m a Register o o LD S 8 2 2 8 y x x K E 2 2 2 o 3 d Output R W K E 8 Logic DOFF gt Read Data Reg V l gt ca jou ca RW BWS a 2 a DQ
32. cle and 50 wri cycle E HIT Document Number 001 00437 Rev E Page 20 of 30 Feedback aps CY7C1516KV18 CY7C1527KV18 ESL CYPRESS CY7C1518KV18 CY7C1520KV18 PERFORM Electrical Characteristics continued DC Electrical Characteristics Over the Operating Range 12 Parameter Description Test Conditions Min Typ Max Unit Ibp A Vpp Operating Supply Vpp Max 200 MHz x8 370 mA P Sore ve om x18 380 x36 450 167 MHz x8 340 mA x9 340 x18 340 x36 400 Isp1 Automatic Power Down Max Vpp 333 MHz x8 290 mA Current Both Ports Deselected Vin 2 Vit or Vin lt Vi x9 290 f fmax ice x18 290 Inputs Static x36 290 300 MHz x8 280 mA x9 280 x18 280 x36 280 250 MHz x8 270 mA x9 270 x18 270 x36 270 200 MHz x8 250 mA x9 250 x18 250 x36 250 167 MHz x8 250 mA x9 250 x18 250 x36 250 AC Electrical Characteristics Over the Operating Range 111 Parameter Description Test Conditions Min Typ Max Unit Vin Input HIGH Voltage VREF 0 2 V Vu Input LOW Voltage Vner 0 2 V Document Number 001 00437 Rev E Page 21 of 30 Feedback pe CY7C1516KV18 CY7C1527KV18 CY7C1518KV18 CY7C1520KV18 PERFORM Capacitance Tested initially and after any design
33. cluded Thermal Resistance values Changed the package size from 15 x 17 x 1 4 mm to 13 x 15 x 1 4 mm E 2681899 VKN PYRS 04 01 2009 Converted from preliminary to final Added note on top of the Ordering Information table Moved to external web Sales Solutions and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices solution centers manufacturer s representatives and distributors To find the office closest to you visit us at cypress com sales Products PSoC Solutions PSoC psoc cypress com General psoc cypress com solutions Clocks amp Buffers clocks cypress com Low Power Low Voltage psoc cypress com low power Wireless wireless cypress com Precision Analog psoc cypress com precision analog Memories memory cypress com LCD Drive psoc cypress com lcd drive Image Sensors image cypress com CAN 2 0b psoc cypress com can USB psoc cypress com usb Cypress Semiconductor Corporation 2005 2009 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement
34. data NWSp Input Nibble Write Select 0 1 Active LOW CY7C1516KV18 Only Sampled on the rising edge of the K NWS Synchronous and K clocks during write operations Used to select which nibble is written into the device during the current portion of the write operations Nibbles not written remain unaltered NWS controls Dr o and NWS controls Dr 4j All the Nibble Write Selects are sampled on the same edge as the data Deselecting a Nibble Write Select ignores the corresponding nibble of data and it is not written into the device BWSp Input Byte Write Select 0 1 2 and 3 Active LOW Sampled on the rising edge of the K and K clocks during BWS Synchronous write operations Used to select which byte is written into the device during the current portion of the write BWS operations Bytes not written remain unaltered BWS3 CY7C1527KV18 BWSj controls Djg oj CY7C1518KV18 BWSp controls Dro and BWS controls Djaz CY7C1520KV18 BWSg controls D o BWS controls Du ot BWS controls Djpe 18j and BWS3 controls D 35 27 Ali the Byte Write Selects are sampled on the same edge as the data Deselecting a Byte Write Select ignores the corresponding byte of data and it is not written into the device A A0 Input Address Inputs These address inputs are multiplexed for both read and write operations Internally the Synchronous device is organized as 8M x 8 2 arrays each of 4M x 8 for CY7C1516KV18 and 8M x 9 2 arrays each of 4M x
35. for the echo clocks is shown in the Switching Characteristics on page 23 Application Example Figure 1 shows two DDR II used in an application CY7C1516KV18 CY7C1527KV18 CY7C1518KV18 CY7C1520KV18 PLL These chips use a PLL that is designed to function between 120 MHz and the specified maximum clock freguency During power up when the DOFF is tied HIGH the PLL is locked after 20 us of stable clock The PLL can also be reset by slowing or stopping the input clock K and K for a minimum of 30 ns However it is not necessary to reset the PLL to lock to the desired freguency The PLL automatically locks 20 us after a stable clock is presented The PLL may be disabled by applying ground to the DOFF pin When the PLL is turned off the device behaves in DDR I mode with one cycle latency and a longer access time Figure 1 Application Example SRAM 1 DQ A LD R W C CH K Ki ZQ CQ CQ WWW R 250ohms SRAM 2 zo R 250ohms DQ CQ CQ LD R W C CH K K DQ BUS Addresses MASTER Cycle Start CPU R W i Or Return CLK ka e ASIC Source CLK a n Se Return CLK Source CLK ive Mee Echo Clock1 Echo Clockt1 Echo Clock2 Echo Clock 2 t Document Number 001 00437 Rev E Page 9 of 30 Feedback CY7C1516KV18 CY7C1527KV18 7 CYPRESS CY7C
36. g the data portion of a write sequence only the byte D 35 27 is written into the device De o remains unaltered L H No data is written into the device during this portion of a write operation L H No data is written into the device during this portion of a write operation Document Number 001 00437 Rev E Page 11 of 30 Feedback YPRESS PERFORM Ml Mi C3 IEEE 1149 1 Serial Boundary Scan JTAG These SRAMs incorporate a serial boundary scan Test Access Port TAP in the FBGA package This part is fully compliant with IEEE Standard 1149 1 2001 The TAP operates using JEDEC standard 1 8V IO logic levels Disabling the JTAG Feature lt is possible to operate the SRAM without using the JTAG feature To disable the TAP controller TCK must be tied LOW Vgg to prevent clocking of the device TDI and TMS are inter nally pulled up and may be unconnected They may alternatively be connected to Vpp through a pull up resistor TDO must be left unconnected Upon power up the device comes up in a reset state which does not interfere with the operation of the device Test Access Port Test Clock The test clock is used only with the TAP controller All inputs are captured on the rising edge of TCK All outputs are driven from the falling edge of TCK Test Mode Select TMS The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK
37. ge 4 of 30 Feedback Lc CY7C1516KV18 CY7C1527KV18 ESL CYPRESS CY7C1518KV18 CY7C1520KV18 PERFORM Pin Configuration continued The pin configurations for CY7C1516KV18 CY7C1527KV18 CY7C1518KV18 and CY7C1520KV18 follow M 165 Ball FBGA 13 x 15 x 1 4 mm Pinout CY7C1518KV18 4M x 18 1 2 3 4 5 6 7 8 9 10 11 A ca A A R W BWS K NC 144M LD A A CO B NC DO9 NC A NC 288M K BWSg A NC NC DO8 C NC NC NC Vss A A0 A Vss NC DQ7 NC D NC NC DQ10 Vss Vss Vss Vss Vss NC NC NC E NC NC DOM Vooo Vss Ves Vas Voba NC NC DQ6 F NC DQ12 NC Vida V t Vss Voo Vona NC NC DO5 G NC NC DQ13 Wesel Voo Vss Von Mena NC NC NC H DOFF Ver Vopa Vppo Von Vss Vop Vopa Vopa VREF ZQ J NC NC NC Vooa ep Vas Vbo Vona NC DQ4 NC K NC NC DQ14 Voss V b Mae Voo Voba NC NC DQ3 L NC DQ15 NC Vus Vss Vas Ves d Wena NC NC DQ2 M NC NC NC Vss Vss Vss Vss Vss NC DO1 NC N NC NC DO16 Vss A A A Ves NC NC NC P NC NC DQ17 A A C A A NC NC DQO R TDO TCK A A A C A A A TMS TDI CY7C1520KV18 2M x 36 1 2 3 4 5 6 7 8 9 10 11 A CQ NCM44M A RW BWS K BWS LD A A cQ B NC DQ27 DQ18 A BWS K BWSo A NC NC DQ8 C NC NC DQ28 Vss A A0 A Vss NC DO17 DO7 D NC DQ29 DQ19 Vss Vss Vss Vea Vss NC NC DQ16 E NC NC DQ20 Vooo Vss Vss Vss Vane NC DQ15 DO6 F NC
38. he Byte Write Select input during the data portion of a write enables the data stored in the device for that byte to remain unaltered This feature is used to simplify read modify or write operations to a byte write operation Single Clock Mode The CY7C1518KV18 is used with a single clock that controls both the input and output registers In this mode the device recognizes only a single pair of input clocks K and K that control both the input and output registers This operation is identical to the operation if the device had zero skew between the K K and C C clocks All timing parameters remain the same in this mode To use this mode of operation the user must tie C and C HIGH at power on This function is a strap option and not alterable during device operation DDR Operation The CY7C1518KV18 enables high performance operation through high clock frequencies achieved through pipelining and DDR mode of operation The CY7C1518KV18 requires a single No Operation NOP cycle during transition from a read to a write cycle At higher frequencies some applications may require a second NOP cycle to avoid contention If a read occurs after a write cycle address and data for the write are stored in registers The write information must be stored because the SRAM cannot perform the last word write to the array without conflicting with the read The data stays in this register until the next write cycle occurs On the first write cycle after
39. ht to make changes without further notice to the materials described herein Cypress does not assume any liability arising out of the application or use of any product or circuit described herein Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress product in a life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Use may be limited by and subject to the applicable Cypress software license agreement Document Number 001 00437 Rev E Revised March 30 2009 Page 30 of 30 ODR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress IDT NEC Renesas and Samsung All product and company names mentioned in this document are the trademarks of their respective holders Feedback
40. ler is in the Test Logic Reset state Reserved These instructions are not implemented but are reserved for future use Do not use these instructions Page 13 of 30 Feedback PERFORM TAP Controller State Diagram The state diagram for the TAP controller follows 9 is CY7C1516KV18 CY7C1527KV18 CY7C1518KV18 CY7C1520KV18 TEST LOGIC a RESET d 1 TEST LOGIC 1 SELECT SELECT L gt y IDLE DR SCAN IR SCAN d d 1 CAPTURE DR CAPTURE IR 0 0 SHIFT DR SHIFT IR 0 Y Y 1 po EXIT1 DR p EXIT1 IR d a PAUSE DR PAUSE IR 0 Y Y 0 EXIT2 DR EXIT2 IR Y y UPDATE DR UPDATE IR 1 0 Note Y 9 The 0 1 next to each state represents the value at TMS at the rising edge of TCK Document Number 001 00437 Rev E Page 14 of 30 Feedback MAE CY7C1516KV18 CY7C1527KV18 3 CY7C1518KV18 CY7C1520KV18 PERFORM TAP Controller Block Diagram z 0 Bypass Register B2170 mn Selection TDO Selection TDI Instruction Register Circuitry EE Circuitry m 34 30129393 12 1 0 gt Identification Register 2 1 0 gt l p gt 108 Boundary Scan Register LIT tt t ft d TAP Controller TCK
41. r and the least significant bit of the address is presented to the burst counter The burst counter increments the address in a linear fashion On the following K clock rise the data presented to D 17 9 is latched and stored into the 18 bit write Document Number 001 00437 Rev E CY7C1516KV18 CY7C1527KV18 CY7C1518KV18 CY7C1520KV18 data register provided BWS 1 0 are both asserted active On the subseguent rising edge of the Negative Input Clock K the infor mation presented to Drir o is also stored into the write data register provided DW Sr o are both asserted active The 36 bits of data are then written into the memory array at the specified location Write accesses can be initiated on every rising edge of the positive input clock K Doing so pipelines the data flow such that 18 bits of data can be transferred into the device on every rising edge of the input clocks K and K When the write access is deselected the device ignores all inputs after the pending write operations have been completed Byte Write Operations Byte write operations are supported by the CY7C1518KV18 A write operation is initiated as described in the Write Operations section The bytes that are written are determined by BWSg and BWS which are sampled with each set of 18 bit data words Asserting the appropriate Byte Write Select input during the data portion of a write latches the data being presented and writes it into the device Deasserting t
42. s to the system data bus impedance CG CO and O x 0 output impedance are set to 0 2 x RQ where RQ is a resistor connected between ZQ and ground Alismatively this pin can be connected directly to Vppa which enables the minimum impedance mode This pin cannot be connected directly to GND or left unconnected DOFF Input PLL Turn Off Active LOW Connecting this pin to ground turns off the PLL inside the device The timing in the PLL turned off operation differs from those listed in this data sheet For normal operation this pin is connected to a pull up through a 10 KO or less pull up resistor The device behaves in DDR I mode when the PLL is turned off In this mode the device can be operated at a frequency of up to 167 MHz with DDR I timing TDO Output TDO for JTAG TCK Input TCK Pin for JTAG TDI Input TDI Pin for JTAG TMS Input TMS Pin for JTAG NC N A Not Connected to the Die Can be tied to any voltage level NC 144M Input Not Connected to the Die Can be tied to any voltage level NC 288M Input Not Connected to the Die Can be tied to any voltage level VREF Input Reference Voltage Input Static input used to set the reference level for HSTL inputs outputs and AC Reference measurement points Von Power Supply Power supply Inputs to the Core of the Device Vss Ground Ground for the Device Vppa Power Supply Power Supply Inputs for the Outputs of the Device Document Number 001 00437 Rev E Page 7 of 30
43. sents A 0 and A2 represents A 1 5 t represents the cycle at which a read write operation is started t 1 and t 2 are the first and second clock cycles succeeding the t clock cycle 6 7 8 Data inputs are registered at K and K rising edges Data outputs are delivered on C and C rising edges except when in single clock mode Ensure that when the clock is stopped K K and C C HIGH This is not essential but permits most rapid restart by overcoming transmission line charging symmetrically Is based on a write cycle that was initiated in accordance with the Write Cycle Descriptions table NWSg NWS BWSp BWS BWS and BWS can be altered on different portions of a write cycle as long as the setup and hold reguirements are achieved Document Number 001 00437 Rev E Page 10 of 30 Feedback Ese CY7C1516KV18 CY7C1527KV18 SSF CYPRESS CY7C1518KV18 CY7C1520KV18 PERFORM Write Cycle Descriptions The write cycle description table for CY7C1527KV18 follows 2 8 BWS K K L L H During the data portion of a write sequence the single byte Dra oj is written into the device L L H During the data portion of a write sequence the single byte Djg o is written into the device H L H No data is written into the device during this portion of a write operation H L H No data is written into the device during this portion of a write operation
44. ter is loaded with the contents of the RAM input and output ring when the TAP controller is in the Capture DR state and is then placed between the TDI and TDO pins when the controller is moved to the Shift DR state The EXTEST SAMPLE PRELOAD and SAMPLE Z instructions are used to capture the contents of the input and output ring The Boundary Scan Order on page 18 shows the order in which the bits are connected Each bit corresponds to one of the bumps on the SRAM package The MSB of the register is connected to TDI and the LSB is connected to TDO Identification ID Register The ID register is loaded with a vendor specific 32 bit code during the Capture DR state when the IDCODE command is loaded in the instruction register The IDCODE is hardwired into the SRAM and is shifted out when the TAP controller is in the Shift DR state The ID register has a vendor code and other infor mation described in Identification Register Definitions on page 17 TAP Instruction Set Eight different instructions are possible with the three bit instruction register All combinations are listed in Instruction Codes on page 17 Three of these instructions are listed as RESERVED and must not be used The other five instructions are described in this section in detail Instructions are loaded into the TAP controller during the Shift IR state when the instruction register is placed between TDI and TDO During this state instructions are shifted through the
45. ters Data is serially loaded into the TDI pin on the rising edge of TCK Data is output on the TDO pin on the falling edge of TCK Document Number 001 00437 Rev E CY7C1516KV18 CY7C1527KV18 CY7C1518KV18 CY7C1520KV18 Instruction Register Three bit instructions are serially loaded into the instruction register This register is loaded when it is placed between the TDI and TDO pins as shown in TAP Controller Block Diagram on page 15 Upon power up the instruction register is loaded with the IDCODE instruction lt is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section When the TAP controller is in the Capture lR state the two least significant bits are loaded with a binary 01 pattern to allow for fault isolation of the board level serial test path Bypass Register To save time when serially shifting data through registers it is sometimes advantageous to skip certain chips The bypass register is a single bit register that can be placed between TDI and TDO pins This enables shifting of data through the SRAM with minimal delay The bypass register is set LOW Vss when the BYPASS instruction is executed Boundary Scan Register The boundary scan register is connected to all the input and output pins on the SRAM Several No Connect NC pins are also included in the scan register to reserve pins for higher density devices The boundary scan regis
46. this provide 20 us of stable clock to a Apply Vpp before Vppo relock to the desired clock frequency a Apply Vppo before VRE or at the same time as VREF a Drive DOFF HIGH m Provide stable DOFF HIGH power and clock K K for 20 us to lock the PLL Figure 3 Power Up Waveforms d HX Aeg XJ Xu Xu o el bi K oV v W uuu Unene Clock gt 20us Stable clock Start Noel Operation Clock Start Clock Starts after Vpp Vppa Stable Vpp Vppa gt Vpp Vppo Stable lt 0 1V DC per 50ns OR Fix HIGH or tie to po Page 19 of 30 Document Number 001 00437 Rev E Feedback MAE CY7C1516KV18 CY7C1527KV18 EE CYPRESS CY7C1518KV18 CY7C1520KV18 PERFORM Maximum Ratings Current into Outputs OW 20 mA F i Static Discharge Voltage MIL STD 883 M 3015 gt 2001V Exceeding maximum ratings may impair the useful life of the device These user guidelines are not tested Latch up Current eee eeeeeeeseeeeeeeeeeneeeeeneeeeeneees gt 200 mA Storage Temperature 65 C to 150 C Operating Range Ambient Temperature with Power Applied 55 C to 125 C A Range Ambient 15 15 Supply Voltage on Vpp Relative to GND 0 5V to 2 9V g Temperature TA Vpp h Vppa Supply Voltage on Vppa Relative to GND 0 5V to Vpp Commercial 0 C to 70 C 1 8 01V 1 4V to D
47. unction with C to clock out the read data from the device C and C can be used together to deskew the flight times of various devices on the board back to the controller See application example for further details K Input Clock Positive Input Clock Input The rising edge of K is used to capture synchronous inputs to the device and to drive out data through Or o when in single clock mode All accesses are initiated on the rising edge of K K Input Clock Negative Input Clock Input K is used to capture synchronous data being presented to the device and to drive out data through Or o when in single clock mode Page 6 of 30 Feedback PERFOR CY7C1516KV18 CY7C1527KV18 CY7C1518KV18 CY7C1520KV18 M Pin Definitions continued Pin Name y o Pin Description CO Output Clock CG Referenced with Respect to C This is a free running clock and is synchronized to the input clock for output data C of the DDR II In the single clock mode CO is generated with respect to K The timing for the echo clocks is shown in the AC Timing table CO Output Clock CO Referenced with Respect to C This is a free running clock and is synchronized to the input clock for output data C of the DDR II In the single clock mode CO is generated with respect to K The timing for the echo clocks is shown in the AC Timing table ZO Input Output Impedance Matching Input This input is used to tune the device output
48. with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Any Source Code software and or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign United States copyright laws and international treaty provisions Cypress hereby grants to licensee a personal non exclusive non transferable license to copy use modify create derivative works of and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement Any reproduction modification translation compilation or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Cypress reserves the rig
49. y then try to capture a signal while in transition metastable state This does not harm the device but there is no guarantee as to the value that is captured Repeatable results may not be possible To guarantee that the boundary scan register captures the correct value of a signal the SRAM signal must be stabilized long enough to meet the TAP controller s capture setup plus hold times tcs and tcp The SRAM clock input might not be captured correctly if there is no way in a design to stop or slow the clock during a SAMPLE PRELOAD instruction If this is an issue it is still possible to capture all other signals and simply ignore the value of the CK and CK captured in the boundary scan register After the data is captured it is possible to shift out the data by putting the TAP into the Shift DR state This places the boundary scan register between the TDI and TDO pins Document Number 001 00437 Rev E CY7C1516KV18 CY7C1527KV18 CY7C1518KV18 CY7C1520KV18 PRELOAD places an initial data pattern at the latched parallel outputs of the boundary scan register cells before the selection of another boundary scan test operation The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when reguired that is while the data captured is shifted out the preloaded data can be shifted in BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift DR state the bypass
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