Cypress CY7C1410JV18 User's Manual
Contents
1. i 1 Me Ne a SARA RA Vu K He UN UN i Unstable Glo V gt 1024 Stable clock Start Kuna Operation Clock Start Clock Starts after Vpp Vppo Stable Man Vina po i Vpp Vppo Stable lt 0 1V DC per 50ns H a Fix High or tied toVppo Document 001 12561 Rev D Page 19 of 26 Feedback Maximum Ratings Exceeding maximum ratings may impair the useful life of the CY7C1410JV18 CY7C1425JV18 CY7C1412JV18 CY7C1414JV18 Current into Outputs LOW Static Discharge Voltage MIL STD 883 M 3015 gt 2001V device These user guidelines are not tested Latch up Current gt 200 mA Storage Temperature 65 C to 150 C Operating Range Ambient Temperature with Power Applied 10 to 85 C Ambient Supply Voltage on Vpp Relative to GND 0 5V to 2 9V Range Temperature TA Voo Vona Supply Voltage on Vppo Relative to GND 0 5V to Vpp Commercial 0 C to 70 C 1 8 0 1V 1 4V to DC Applied to Outputs in High Z 0 5V to Vppo 0 3V Industrial 40 C to 85 C VoD DC Input Voltage 111 0 5V to Vpp 0 3V Electrical Characteristics DC Electrical Characteristics Over the Operating Range 2l Parameter Description Test Conditions2. CY7C1410JV18 4M x 8 1 2 3 4 5 6 7 8 9 10 11 A CQ NC 72M A WPS NWS K NC 144M RPS A A ca B NC NC NC A NC 288M K NWS A NC NC Q3 C NC NC NC Vss A A A Vss NC NC D3 D NC D4 NC Vss Vss Vss Vss Vss NC NC NC E NC NC Q4 VDDQ Vss Vss Vss Vppo NC D2 Q2 F NC NC NC VDDQ Vpp Vss Vpp Von NC NC NC G NC D5 Q5 VDDQ Vpo Ves Vou Vong NC NC NC H DOFF Veer Vppa Vppa Vpp Vss VDD Vppa Vppa VREF ZQ J NC NC NC VDDQ Vpn Veg Vpp VDDQ NC Q1 D1 K NC NC NC VDDQ Vien Vss Vpn Vane NC NC NC L NC Q6 D6 VDDQ Vss Vss Vss Vppo NC NC Q0 M NC NC NC Vas Vss Vss Vss Vss NC NC DO N NC D7 NC Vss A A A Vss NC NC NC P NC NC Q7 A A C A A NC NC NC R TDO TCK A A A Cc A A A TMS TDI CY7C1425JV18 4M x 9 1 2 3 4 5 6 7 8 9 10 11 A CQ NC 72M A WPS NC K NC 144M RPS A A CQ B NC NC NC A NC 288M K BWS A NC NC Q4 C NC NC NC Vss A A A Vss NC NC D4 D NC D5 NC Vss Vss Ves Vss Vss NC NC NC E NC NC Q5 VDDQ Vss Vss Vss Vppo NC D3 Q3 F NC NC NC VDDQ Vpp Ves Vpn Vong NC NC NC G NC D6 Q6 VDDQ Uns Veg Vpp Veno NC NC NC H DOFF Vmgr VDDQ VDDQ VDD Vss VDD VDDQ VDDQ VREF ZQ J NC NC NC VDDQ Vpp Ves Vpp VDDQ NC Q2 D2 K NC NC NC VDDQ Vpp Vss Vpp VDDQ NC NC NC L NC Q7 D7 VDDQ Vss Vss Vss Vppo NC NC Q1 M NC NC NC Vss Vss Ves Vss Vss NC NC Di N NC D8 NC Vss A A A Vss NC NC NC P NC NC Q8 A A C A A NC DO GO R TDO TCK A A A g A A A TMS TDI Note 1 NC 72M NC 144M and NC 288M are not connected to the die and can be tied to any voltage level Document 001 12561 Rev D Page 4 of
3. The state diagram for the TAP controller follows l TEST LOGIC RESET Y 1 TEST LOGIC 1 SELECT 1 SELECT IDLE A DR SCAN IR SCAN A 0 Y 0 1 CAPTURE DR CAPTURE IR 0 0 al SHIFT DR E SHIFT IR 0 y y 1 mi EXIT1 DR p EXIT1 IR y o Y PAUSE DR PAUSE IR 0 y Y 0 0 EXIT2 DR EXIT2 IR ty Y UPDATE DR r2 UPDATE IR r2 1 1 Y Y Ji Note Document 001 12561 Rev D 9 The 0 1 next to each state represents the value at TMS at the rising edge of TCK Page 14 of 26 Feedback Ee CY7C1410JV18 CY7C1425JV18 P CYPRESS CY7C1412JV18 CY7C1414JV18 PERFORM TAP Controller Block Diagram p 0 Bypass Register 2 1 0 Selection s TDI nee Instruction Register Selection y TDO Circuitry ODD NTI Circuitry m 31 30 29 2 1 0 Identification Register 108 2 10 Boundary Scan Register TCK TMS TAP Controller TAP Electrical Characteristics Over the Operating Range l9 11 12 Parameter Description Test Conditions Min Max Unit VoHi Output HIGH Voltage lon 2 0 mA 14 V Von2 Output HIGH Voltage lou 100 pA 1 6 V Vout Output LOW Voltage lo 2 0 mA 0 4 V Voi Output LOW Voltage lo 100 pA 0 2 V Vin Input HIGH Voltage 0 65Vpp Vpp 0 3 V Vu Input LOW Voltage 0 3 0 35Vpp V lx Input and Output Loa
4. AM x 9 CY7C1412JV18 2M x 18 CY7C1414JV18 1M x 36 Functional Description The CY7C1410JV18 CY7C1425JV18 CY7C1412JV18 and CY7C1414JV18 are 1 8V Synchronous Pipelined SRAMs equipped with QDR II architecture QDR II architecture consists of two separate ports the read port and the write port to access the memory array The read port has data outputs to support read operations and the write port has data inputs to support write operations QDR II architecture has separate data inputs and data outputs to completely eliminate the need to turn around the data bus required with common IO devices Access to each port is accomplished through a common address bus The read address is latched on the rising edge of the K clock and the write address is latched on the rising edge of the K clock Accesses to the QDR II read and write ports are completely independent of one another To maximize data throughput both read and write ports are provided with DDR interfaces Each address location is associated with two 8 bit words CY7C1410JV18 9 bit words CY7C1425JV18 18 bit words CY7C1412JV18 or 36 bit words CY7C1414JV18 that burst sequentially into or out of the device Because data can be transferred into and out of the device on every rising edge of both input clocks K and K and C and C memory bandwidth is maximized while simplifying system design by eliminating bus turn arounds Depth expansion is accomplished with port selects wh
5. pu Logic B BWS o 4 gt Qj Page 2 of 26 Document 001 12561 Rev D Feedback i act CY7C1410JV18 CY7C1425JV18 Z7 CYPRESS CY7C1412JV18 CY7C1414JV18 PERFORM Logic Block Diagram CY7C1412JV18 18 Dj17 0 y t Writ Writ d NE Address Aoo A 20 Address gt Register 19 0 Register Hi B o lt lt o 8 x x Ke co co ke E gt gt E e 3 a s z DOFF Read Data Reg VREF gt WPS Control BWS Logic Block Diagram CY7C1414JV18 36 Dt5 0j t Write Write Reg Reg Address Register ZN Address A 18 0 pe id Control Logic Key 9 X MZLS Read Add Decode keny 9 X MZLS Write Add Decode K gt DOFF Read Data Reg VREF ca WPS Control Logic 36 BWS s7j 4 8 Qrs oj Document 001 12561 Rev D Page 3 of 26 Feedback SS ao LL BA E pe SL Amr a J CYPRESS PERFORM Pin Configuration The pin configuration for CY7C1410JV18 CY7C1412JV18 and CY7C1414JV18 follow n 165 Ball FBGA 15 x 17 x 1 4 mm Pinout CY7C1410JV18 CY7C1425JV18 CY7C1412JV18 CY7C1414JV18
6. range in which it is being operated and outputs data with the output timings of that freguency range 21 This part has a voltage regulator internally tpowgg is the time that the power is supplied above Vpp minimum initially before a read or write operation can be initiated 22 These parameters are extrapolated from the input timing parameters tkH4KH 250 ps where 250 ps is the internal jitter An input jitter of 200 ps tkc Var is already included in the txyKy These parameters are only guaranteed by design and are not tested in production 23 tcHz toz are specified with a load capacitance of 5 pF as in part b of AC Test Loads and Waveforms on page 21 Transition is measured 100 mV from steady state voltage 24 At any voltage and temperature toyz is less than te z and toyz less than tco Document 001 12561 Rev D Page 22 of 26 Feedback o EC E CY7C1410JV18 CY7C1425JV18 A CYPRESS CY7C1412JV18 CY7C1414JV18 5 PERFORM Switching Waveforms Figure 3 Read Write Deselect Sequence 5 26 27 READ WRITE READ WRITE READ WRITE NOP WRITE NOP RPS WPS O O E o OD LE ie w o ie 35 IA oso VV os Z oto YY voe VII l Il gt lt gt tsp tup tsp tup DON T CARE RY UNDEFINED Notes 25 Q00 refers to output from address AO Q01 refers to output from the next internal burst address following
7. the TAP controller be able to put the output bus into a tri state mode The boundary scan register has a special bit located at bit 4108 When this scan cell called the extest output bus tri state is latched into the preload register during the Update DR state in the TAP controller it directly controls the state of the output Q bus pins when the EXTEST is entered as the current instruction When HIGH it enables the output buffers to drive the output bus When LOW this bit places the output bus into a High Z condition This bit can be set by entering the SAMPLE PRELOAD or EXTEST command and then shifting the desired bit into that cell during the Shift DR state During Update DR the value loaded into that shift register cell latches into the preload register When the EXTEST instruction is entered this bit directly controls the output Q bus pins Note that this bit is pre set LOW to enable the output when the device is powered up and also when the TAP controller is in the Test Logic Reset state Reserved These instructions are not implemented but are reserved for future use Do not use these instructions Page 13 of 26 Feedback TAP Controller State Diagram id YPRESS PERFORM CY7C1410JV18 CY7C1425JV18 CY7C1412JV18 CY7C1414JV18
8. to the rising edge of the output clocks C and C or K and K when in single clock mode All synchronous data inputs Dp oj pass through input registers controlled by the input clocks K and K All synchronous data outputs Qhx o pass through output registers controlled by the rising edge of the output clocks C and C or K and K when in single clock mode All synchronous control RPS WPS BWS o inputs pass through input registers controlled by the rising edge of the input clocks K and K CY7C1412JV18 is described in the following sections The same basic descriptions apply to CY7C1410JV18 CY7C1425JV18 and CY7C1414JV18 Read Operations The CY7C1412JV18 is organized internally as two arrays of 1M x 18 Accesses are completed in a burst of two sequential 18 bit data words Read operations are initiated by asserting RPS active at the rising edge of the positive input clock K The address is latched on the rising edge of the K clock The address presented to the address inputs is stored in the read address register Following the next K clock rise the corresponding lowest order 18 bit word of data is driven onto the Qr47 o using C as the output timing reference On the subsequent rising edge of C the next 18 bit data word is driven onto the Q 17 9 The requested data is valid 0 45 ns from the rising edge of the output clock C and C or K and K when in single clock mode Synchronous internal circuitry automatically tri s
9. written into the device Dr35 gj remains unaltered L H H H L H During the Data portion of a write sequence only the lower byte Djg o is written into the device D 35 9 remains unaltered H L H H L H During the Data portion of a write sequence only the byte Dr7 gj is written into the device Dig and Drss 1gj remains unaltered H L H H L H During the Data portion of a write sequence only the byte Dr7 gj is written into the device Dyg oj and Di35 1g remains unaltered H H L H L H During the Data portion of a write sequence only the byte Dja 1g is written into the device Dr 7 9j and Djgs 27 remains unaltered H H L H L H During the Data portion of a write sequence only the byte Droe 18 is written into the device D 7 oj and Dras 7 remains unaltered H H H L L H During the Data portion of a write sequence only the byte Dras 27 is written into the device Drog oj remains unaltered H H H L L H During the Data portion of a write sequence only the byte Dr35 27 is written into the device Drog oj remains unaltered L H No data is written into the device during this portion of a write operation L H No data is written into the device during this portion of a write operation Document 001 12561 Rev D Page 11 of 26 Feedback CYPRESS PERFORM IEEE 1149 1 Serial Boundary Scan JTAG These SRAMs incorporate a serial boundary scan Test Acc
10. 0 25V to 1 25V and output loading of the specified lo loy and load capacitance shown in a of AC Test Loads and Waveforms Document 001 12561 Rev D 19 Unless otherwise noted test conditions are based on signal transition time of 2V ns timing reference levels of 0 75V Vref 0 75V RQ 2500 Vppo 1 5V input Page 21 of 26 Feedback s i CY7C1410JV18 CY7C1425JV18 CYPRESS CY7C1412JV18 CY7C1414JV18 PERFORM Switching Characteristics Over the Operating Range l9 20 pr Consortium Description een Whe 220 MEJ i arameter Parameter Min Max Min Max POWER Vpp Typical to the first access 1 1 1 ms teyc tkKHKH K Clock and C Clock Cycle Time 3 75 8 4 4 0 8 4 ns tkH tKHKL Input Clock K K and C C HIGH 15 16 ns tk IKLKH Input Clock K K and C C LOW 15 16 ns tkHKH KHKH K Clock Rise to K Clock Rise and C to C Rise rising edge to rising edge 1 68 1 8 ns tkHCH KHCH K K Clock Rise to C C Clock Rise rising edge to rising edge 0 1 68 0 1 8 ns Setup Times tsa tAVKH Address Setup to K Clock Rise 0 3 0 35 ns tsc tivKH Control Setup to K Clock Rise RPS WPS 0 3 0 35 ns tecppR ltivkH DDR Control Setup to Clock K K Rise BWS BWS BWS3 BWS 0 3 035 ns tsp tovKH Dix 0 Setup to Clock K K Rise 0 3 0 35
11. 0 3C 98 3P 15 9M 43 11C 71 1D 99 2N 16 9N 44 9B 72 2C 100 2P 17 11L 45 10B 73 3E 101 1P 18 11M 46 11A 74 102 3R 19 9L 47 10A 75 2E 103 4R 20 10L 48 9A 76 1E 104 4P 21 11K 49 8B 77 2F 105 5P 22 OK 50 7C 78 3F 106 5N 23 9J 51 6C 79 1G 107 5R 24 9K 52 8A 80 1F 108 Internal 25 10J 53 7A 81 3G 26 11J 54 7B 82 2G 27 11H 55 6B 83 1H Document 001 12561 Rev D Page 18 of 26 Feedback SS Cypress PERFORM aM Power Up Sequence in QDR II SRAM QDR II SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations During Power Up when the DOFF is tied HIGH the DLL gets locked after 1024 cycles of stable clock Power Up Sequence m Apply power with DOFF tied HIGH All other inputs can be HIGH or LOW 3 Apply Vpp before Vppo a Apply Vppq before Vref or at the same time as VREF m Provide stable power and clock K K for 1024 cycles to lock the DLL Power Up Waveforms CY7C1410JV18 CY7C1425JV18 CY7C1412JV18 CY7C1414JV18 DLL Constraints m DLL uses K clock as its synchronizing input The input must have low phase jitter which is specified as tkc var m The DLL functions at frequencies down to 120 MHz m If the input clock is unstable and the DLL is enabled then the DLL may lock onto an incorrect frequency causing unstable SRAM behavior To avoid DLL locking provide 1024 cycles stable clock to relock to the desired clock frequency
12. 26 Feedback IT T Amr a J CYPRESS PERFORM Pin Configuration CY7C1410JV18 CY7C1425JV18 CY7C1412JV18 CY7C1414JV18 The pin configuration for CY7C1410JV18 CY7C1412JV18 and CY7C1414JV18 follow l continued 165 Ball FBGA 15 x 17 x 1 4 mm Pinout CY7C1412JV18 2M x 18 1 2 3 4 5 6 7 8 9 10 11 A CQ NC 144M A WPS BWS K NC 288M RPS A NC 72M CQ B NC Q9 D9 A NC K BWS A NC NC Q8 C NC NC D10 Vss A A A Vss NC Q7 D8 D NC D11 Q10 Vss Vss Ves Vss Vss NC NC D7 E NC NC Qt Vooo Vss Vss Vss Vena NC D6 Q6 F NC Q12 Dij Vasa Ven Vss Voo Vova NC NC Q5 G NC D13 Q13 Vasa Voo Vag Voo Nene NC NC D5 H DOFF Veer Vppa Vppa Vpp Vss VDD Vppa Vppa VREF ZQ J NC NC D14 Visa Voo Vss Von VpBa NC Q4 D4 K NC NC Q14 Visa Veo Vise Voo Vova NC D3 Q3 L NC Q15 D15 Voa Ves Ves Vss Vong NC NC Q2 M NC NC D16 Vss Ves Vss Vss Vss NC Q1 D2 N NC D17 Q16 Vss A A A Vss NC NC D1 P NC NC Q17 A A C A A NC DO GO R TDO TCK A A A Cc A A A TMS TDI CY7C1414JV18 1M x 36 1 2 3 4 5 6 7 8 9 10 11 A CQ NC 288M NC 72M WPS BWS K BWS RPS A NC 144M CQ B Q27 Q18 D18 A BWS K BWS A D17 017 Q8 C D27 Q28 D19 Vss A A A Ves D16 Q7 D8 D D28 D20 Q19 Vss Vss Vss Vss Vss Q16 D15 D7 E Q29 D29 Q20 Voa Vss Vss Vss
13. 50BZC CY7C1414JV18 250BZC 51 85195 165 Ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Commercial CY7C1410JV18 250BZXC CY7C1425JV18 250BZXC CY7C1412JV18 250BZXC CY7C1414JV18 250BZXC 51 85195 165 Ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Pb Free CY7C1410JV18 250BZi CY7C1425JV18 250BZi CY7C1412JV18 250BZi CY7C1414JV18 250BZI 51 85195 165 Ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Industrial CY7C1410JV18 250BZXI CY7C1425JV18 250BZXI CY7C1412JV18 250BZXI CY7C1414JV18 250BZXI 51 85195 165 Ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Pb Free Document 001 12561 Rev D Page 24 of 26 Feedback MW Fh CYPRESS PERFORM Package Diagram CY7C1410JV18 CY7C1425JV18 CY7C1412JV18 CY7C1414JV18 Figure 4 165 ball FBGA 15 x 17 x 1 40 mm 51 85195 TOP VIEW lt PIN 1 CORNER 1 2 3 4 5 6 7 8 9 10 11 A B c D E B G H J K L M N P R El a d E S e S A Cu N 2 e q ni SEATING PLANE POJ s 0 36 Document 001 12561 Rev D 1 40 MAX BOTTOM VIEW p ps PIN 1 CORNER T go25 M
14. AO that is AO 1 26 Outputs are disabled High Z one clock cycle after a NOP 27 In this example if address A2 A1 then data Q20 D10 and Q21 D11 Write data is forwarded immediately as read results This note applies to the whole diagram Document 001 12561 Rev D Page 23 of 26 Feedback ZP CYPRESS PERFORM Ordering Information Not all of the speed package and temperature ranges are available Please contact your local sales representative or visit www cypress com for actual products offered CY7C1410JV18 CY7C1425JV18 CY7C1412JV18 CY7C1414JV18 Ordering Code Package Diagram Package Type Operating Range CY7C1410JV18 267BZC CY7C1425JV18 267BZC CY7C1412JV18 267BZC CY7C1414JV18 267BZC 51 85195 165 Ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm CY7C1410JV18 267BZXC CY7C1425JV18 267BZXC CY7C1412JV18 267BZXC CY7C1414JV18 267BZXC CY7C1410JV18 267BZI CY7C1425JV18 267BZI CY7C1412JV18 267BZI CY7C1414JV18 267BZI 51 85195 51 85195 165 Ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Pb Free 165 Ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Commercial Industrial CY7C1410JV18 267BZXI CY7C1425JV18 267BZXI CY7C1412JV18 267BZXI CY7C1414JV18 267BZXI 51 85195 165 Ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Pb Free 250 CY7C1410JV18 250BZC CY7C1425JV18 250BZC CY7C1412JV18 2
15. DI and the LSB is connected to TDO Identification ID Register The ID register is loaded with a vendor specific 32 bit code during the Capture DR state when the IDCODE command is loaded in the instruction register The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift DR state The ID register has a vendor code and other information described in Identification Register Definitions on page 17 TAP Instruction Set Eight different instructions are possible with the three bit instruction register All combinations are listed in Instruction Codes on page 17 Three of these instructions are listed as RESERVED and must not be used The other five instructions are described in this section in detail Instructions are loaded into the TAP controller during the Shift IR state when the instruction register is placed between TDI and TDO During this state instructions are shifted through the instruction register through the TDI and TDO pins To execute the instruction after it is shifted in the TAP controller must be moved into the Update IR state Page 12 of 26 Feedback YPRESS PERFORM The IDCODE instruction loads a vendor specific 32 bit code into the instruction register It also places the instruction register between the TDI and TDO pins and shifts the IDCODE out of the device when the TAP controller enters the Shift DR state The IDCODE instruction is loaded into the instr
16. EAIB 2050 ifek 11 10 9 8 7 6 5 4 3 2 1 Fi gx eoooo oooodg T 80000000000 8 C0000 v 00000 c 8 Oooooo ooooo D o0oooo ooooo0 E 0000000000 F 00000 v00000 S e o 3 i o 8 o Oo 5 C H E o000ooo ooooo J 00000020000 K S OOOOOGJGOOOOO L H OO00 00000 00 M OOOCOO0OOOOO N 20000020000 P 8000000008989 R A 3l 5 00 10 00 B 15 00 0 10 O 0 15 4Xx NOTES SOLDER PAD TYPE NON SOLDER MASK DEFINED NSMD PACKAGE WEIGHT 0 65g JEDEC REFERENCE MO 216 DESIGN 4 6C PACKAGE CODE BBOAD 51 85195 A Page 25 of 26 Feedback CY7C1410JV18 CY7C1425JV18 a a CYPRESS CY7C1412JV18 CY7C1414JV18 Document History Page Document Title CY7C1410JV18 CY7C1425JV18 CY7C1412JV18 CY7C1414JV18 36 Mbit QDR II SRAM 2 Word Burst Architecture Document Number 001 12561 ISSUE ORIG OF REV ECN NO DATE CHANGE DESCRIPTION OF CHANGE m 808457 See ECN VKN New Data Sheet A 1061960 See ECN VKN Removed 300MHz speed bin B 1397384 See ECN VKN Added 267MHz speed bin C 1462587 See ECN VKN AESA Converted from preliminary to final Removed 200MHz speed bin Updated Ipp Isg specs Changed DLL minimum operating frequency from 80MHz to 120MHz Changed tcyc max spec to 8 4ns for all speed bins D 2189567 See ECN VKN AESA Minor Change Moved to the external web Cypress Semiconductor Corporation 2007 2008 The information contained herein is subject to chang
17. Min Typ Max Unit Vpp Power Supply Voltage 1 7 1 8 1 9 V VDDQ IO Supply Voltage 1 4 1 5 Vpp V Vou Output HIGH Voltage Note 16 Vppo 2 0 12 Vppo 2 0 12 V VoL Output LOW Voltage Note 17 Vppo 2 0 12 Vppo 2 0 12 V VoH Low Output HIGH Voltage lou 0 1 mA Nominal Impedance Vppo 0 2 VDDQ V Vot Low Output LOW Voltage lo 0 1 mA Nominal Impedance Vss 0 2 V Vin Input HIGH Voltage Vngr 0 1 Vppo 0 3 V ViL Input LOW Voltage 0 3 Vngr 0 1 V Ix Input Leakage Current GND x V Vppo 5 5 uA loz Output Leakage Current GND lt V lt Vppo Output Disabled 5 5 pA VREF Input Reference Voltage 78 Typical Value 0 75V 0 68 0 75 0 95 V Ipp Vpp Operating Supply Vpp Max 267MHz x8 1330 mA RI To 5 x18 1370 x36 1460 250MHz x8 1200 mA x9 1200 x18 1230 x36 1290 IsB1 Automatic Power down Max Vpp 267MHz x8 375 mA Current Both Ports Deselected x9 375 Vin 2 Vin Or Vin S Vi f fmax 1 toyc x18 380 Inputs Static x36 385 250MHz x8 345 mA x9 345 x18 350 x36 350 Notes 15 Power up Assumes a linear ramp from OV to Vpp min within 200 ms During this time Vi lt Vpp and Vppo lt Vpp 16 Output are impedance controlled loj Vppq 2 RQ 5 for values of 175 ohms lt RQ lt 350 ohms 17 Output are impedance controlled lo Vppo 2 RQ 5 for values of 175 ohms lt RQ lt 350 ohms 18 Vmep min 0 68V or 0 46Vppq whichever is larger Vpep max 0 95V or 0 54Vppq whichever is
18. PERFORM Features m Separate independent read and write data ports a Supports concurrent transactions m 267 MHz clock for high bandwidth m 2 word burst on all accesses m Double Data Rate DDR interfaces on both read and write ports data transferred at 534 MHz at 267 MHz m Two input clocks K and K for precise DDR timing a SRAM uses rising edges only m Two input clocks for output data C and C to minimize clock skew and flight time mismatches m Echo clocks CQ and CQ simplify data capture in high speed systems m Single multiplexed address input bus latches address inputs for both read and write ports m Separate port selects for depth expansion m Synchronous internally self timed writes m QDR II operates with 1 5 cycle read latency when Delay Lock Loop DLL is enabled m Operates like a QDR I device with 1 cycle read latency in DLL off mode m Available in x8 x9 x18 and x36 configurations m Full data coherency providing most current data m Core Vpp 1 8V 0 1V IO Vppg 1 4V to Vpp m Available in 165 Ball FBGA package 15 x 17 x 1 4 mm m Offered in both Pb free and non Pb free packages m Variable drive HSTL output buffers m JTAG 1149 1 compatible test access port m Delay Lock Loop DLL for accurate data placement Selection Guide CY7C1410JV18 CY7C1425JV18 CY7C1412JV18 CY7C1414JV18 36 Mbit ODR M SRAM 2 Word Burst Architecture Configurations CY7C1410JV18 4M x 8 CY7C1425JV18
19. This operation does not affect SRAM operation SAMPLE Z 010 Captures the input and output contents Places the boundary scan register between TDI and TDO Forces all SRAM output drivers to a High Z state RESERVED 011 Do Not Use This instruction is reserved for future use SAMPLE PRELOAD 100 Captures the input and output ring contents Places the boundary scan register between TDI and TDO Does not affect the SRAM operation RESERVED 101 Do Not Use This instruction is reserved for future use RESERVED 110 Do Not Use This instruction is reserved for future use BYPASS 111 Places the bypass register between TDI and TDO This operation does not affect SRAM operation Document 001 12561 Rev D Page 17 of 26 Feedback 1 1 1 EE CY7C1410JV18 CY7C1425JV18 CYPRESS CY7C1412JV18 CY7C1414JV18 PERFORM Boundary Scan Order Bit Bump ID Bit Bump ID Bit Bump ID Bit Bump ID 0 6R 28 10G 56 6A 84 1J 1 6P 29 9G 57 5B 85 2J 2 6N 30 1F 58 5A 86 3K 3 7P 31 11G 59 4A 3J 4 7N 32 9F 60 5C 2K 5 7R 33 10F 61 4B 89 1K 6 8R 34 11E 62 3A 90 2L 7 8P 35 10E 63 2A 91 3L 8 9R 36 10D 64 1A 92 1M 9 11P 37 9E 65 2B 93 1L 10 10P 38 10C 66 3B 94 3N 11 10N 39 11D 67 1C 95 3M 12 9P 40 9C 68 1B 96 1N 13 10M 4 9D 69 3D 97 2M 14 11N 42 11B 7
20. Vooo Q5 D6 Q6 F a30 Q21 D21 Vans Ven Vss Voo Vena D14 Q14 Q5 G D30 D22 Q22 Vooo Voo Vss Voo Voa 13 D13 D5 H DOFF Vmgr VDDQ VDDQ VDD Vss VDD VDDQ VDDQ VREF ZQ J D31 Q31 D23 Vooo Voo Vss Voo Voa D12 Q4 D4 K Q32 D32 Q23 Masa Vea Vss Voo Voa 12 D3 Q3 L Q33 Q24 D24 Vppo Vss Vss Vss Voo DN Qi Q2 M D33 a34 D25 Vss Vss Vss Vss Vss D10 Q1 D2 N D34 D26 Q25 Vss A A A Ves Q10 D9 D1 P Q35 D35 Q26 A A C A A Q9 DO QO R TDO TCK A A A g A A A TMS TDI Document 001 12561 Rev D Page 5 of 26 Feedback CY7C1410JV18 CY7C1425JV18 YPRESS CY7C1412JV18 CY7C1414JV18 PERFORM Pin Definitions 10 Pin Description Input Synchronous Data Input Signals Sampled on the rising edge of K and K clocks during valid write operations CY7C1410JV18 Drz gj CY7C1425JV18 Dig j CY7C1412JV18 Dri CY7C1414JV18 Drs Input Synchronous Write Port Select Active LOW Sampled on the rising edge of the K clock When asserted active a write operation is initiated Deasserting deselects the write port Deselecting the write port ignores Dro Nibble Write Select 0 1 Active LOW CY7C1410JV18 Only Sampled on the rising edge of the K and K clocks during Write operations Used to select which nibble is written into the device during the current portion of the Write operations Nibbles not written remain unaltered NWS controls Drs o and NWS controls Dr 4j All Nibble Write Sel
21. a stored in the device for that byte to remain unaltered This feature can be used to simplify read modify or write operations to a byte write operation Single Clock Mode The CY7C1412JV18 can be used with a single clock that controls both the input and output registers In this mode the device recognizes only a single pair of input clocks K and K that control both the input and output registers This operation is identical to the operation if the device had zero skew between the K K and C C clocks All timing parameters remain the same in this mode To use this mode of operation the user must tie C and C HIGH at power on This function is a strap option and not alterable during device operation Concurrent Transactions The read and write ports on the CY7C1412JV18 operate independently of one another As each port latches the address inputs on different clock edges the user can read or write to any location regardless of the transaction on the other port The user can start reads and writes in the same clock cycle If the ports access the same location at the same time the SRAM delivers the most recent information associated with the specified address location This includes forwarding data from a write cycle that was initiated on the previous K clock rise Depth Expansion The CY7C1412JV18 has a port select input for each port This enables for easy depth expansion Both port selects are sampled on the rising edge of the posit
22. ased on a write cycle that was initiated in accordance with the Write Cycle Descriptions table NWSo NWS BWSp BWS BWS and BWS can be altered on different portions of a write cycle as long as the setup and hold requirements are achieved Document 001 12561 Rev D Page 10 of 26 Feedback LE CY7C1410JV18 CY7C1425JV18 4 CYPRESS CY7C1412JV18 CY7C1414JV18 PERFORM Write Cycle Descriptions The write cycle description table for CY7C1425JV18 follows 2 81 BWS K K Comments i During the Data portion of a write sequence the single byte Dyg oj is written into the device L H During the Data portion of a write sequence the single byte Djg o is written into the device No data is written into the device during this portion of a write operation E ET T d L H No data is written into the device during this portion of a write operation Write Cycle Descriptions The write cycle description table for CY7C1414JV18 follows gt 81 BWS BWS BWS BWS3 K K Comments L L L L L H During the Data portion of a write sequence all four bytes D 35 0j are written into the device L L B L L H During the Data portion of a write sequence all four bytes Dy35 0 are written into the device L H H H L H During the Data portion of a write sequence only the lower byte Djg o is
23. ce are set to 0 2 x RQ where RQ is a resistor connected between ZQ and ground Alternatively this pin can be connected directly to Vppq which enables the amp O Input minimum impedance mode This pin cannot be connected directly to GND or left unconnected x 0 DLL Turn Off Active LOW Connecting this pin to ground turns off the DLL inside the device The timing in the DLL turned off operation differs from those listed in this data sheet For normal operation this pin can be connected to a pull up through a 10 Kohm or less pull up resistor The device behaves in DDR I mode when the DLL is turned off In this mode the device can be operated at a frequency of up to 167 Input MHz with QDR I timing DOFF TDO for JTAG TCK Pin for JTAG Not Connected to the Die Can be tied to any voltage level TDO Output TCK Input TDI Input TMS Input NC N A NC 72M N A NC 144M N A NC 288M N A VREF Input Reference Vpp Power Supply Ground Power Supply TDI Pin for JTAG Not Connected to the Die Can be tied to any voltage level TMS Pin for JTAG Not Connected to the Die Can be tied to any voltage level Reference Voltage Input Static input used to set the reference level for HSTL inputs outputs and AC Not Connected to the Die Can be tied to any voltage level measurement points Power Supply Inputs to the Core of the Device Ground for the Device Power Supply Inputs for the Ou
24. d 19 address inputs for CY7C1414JV18 These inputs are ignored when the appro priate port is deselected Qpcoj Outputs Synchronous Data Output Signals These pins drive out the requested data during a read operation Valid data is driven out on the rising edge of both the C and C clocks during read operations or K and K when in single clock mode When the read port is deselected Qyx 9 are automatically tri stated CY7C1410JV18 Org CY7C1425JV18 Qig 0 CY7C1412JV18 Qhi7 0 CY7C1414JV18 Qi35 0 RPS Input Synchronous Read Port Select Active LOW Sampled on the rising edge of positive input clock K When active a read operation is initiated Deasserting deselects the read port When deselected the pending access is allowed to complete and the output drivers are automatically tri stated following the next rising edge of the C clock Each read access consists of a burst of two sequential transfers Input Clock Positive Input Clock for Output Data C is used in conjunction with C to clock out the read data from the device C and C can be used together to deskew the flight times of various devices on the board back to the controller See Application Example on page 9 for further details Ol Input Clock Negative Input Clock for Output Data C is used in conjunction with C to clock out the read data from the device C and C can be used together to deskew the flight times of various devices on the b
25. d Current GND lt V x Vpp 5 5 HA Notes 10 These characteristics pertain to the TAP inputs TMS TCK TDI and TDO Parallel load levels are specified in the Electrical Characteristics table 11 Overshoot Viy AC lt Vppq 0 85V Pulse width less than teyc 2 Undershoot Vi AC gt 1 5V Pulse width less than teyc 2 12 All Voltage referenced to Ground Document 001 12561 Rev D Page 15 of 26 Feedback Y PRESS PERFORM TAP AC Switching Characteristics CY7C1410JV18 CY7C1425JV18 CY7C1412JV18 CY7C1414JV18 Over the Operating Range 14 Parameter Description Min Max Unit trcvc TCK Clock Cycle Time 50 ns trp TCK Clock Freguency 20 MHz tty TCK Clock HIGH 20 ns tn TCK Clock LOW 20 ns Setup Times truss TMS Setup to TCK Clock Rise 5 ns trois TDI Setup to TCK Clock Rise 5 ns tes Capture Setup to TCK Rise 5 ns Hold Times trusH TMS Hold after TCK Clock Rise 5 ns trpiH TDI Hold after Clock Rise 5 ns tcu Capture Hold after Clock Rise 5 ns Output Times trpov TCK Clock LOW to TDO Valid 10 ns trpox TCK Clock LOW to TDO Invalid 0 ns TAP Timing and Test Conditions Figure 2 shows the TAP timing and test conditions Notes 14 Figure 2 TAP Timing and Test Conditions 0 9V ALL INPUT PULSES 500 b 0 9V TDO Bi Zo 500 L C 20 pF a GND fH me qra m Test Clock X m MU mi TCK revo trusH pesi e tr
26. duction modification translation compilation or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Cypress reserves the right to make changes without further notice to the materials described herein Cypress does not assume any liability arising out of the application or use of any product or circuit described herein Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress product in a life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Use may be limited by and subject to the applicable Cypress software license agreement Document 001 12561 Rev D Revised March 10 2007 Page 26 of 26 QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress IDT NEC Renesas and Samsung All product and company names mentioned in this document are the trademarks of their respective holders Feedback
27. e unconnected if the TAP is unused in an application TDI is connected to the most significant bit MSB on any register Test Data Out TDO The TDO output pin is used to serially clock data out from the registers The output is active depending upon the current state of the TAP state machine see Instruction Codes on page 17 The output changes on the falling edge of TCK TDO is connected to the least significant bit LSB of any register Performing a TAP Reset A Reset is performed by forcing TMS HIGH Vpp for five rising edges of TCK This Reset does not affect the operation of the SRAM and can be performed while the SRAM is operating At power up the TAP is reset internally to ensure that TDO comes up in a high Z state TAP Registers Registers are connected between the TDI and TDO pins to scan the data in and out of the SRAM test circuitry Only one register can be selected at a time through the instruction registers Data is serially loaded into the TDI pin on the rising edge of TCK Data is output on the TDO pin on the falling edge of TCK Document 001 12561 Rev D CY7C1410JV18 CY7C1425JV18 CY7C1412JV18 CY7C1414JV18 Instruction Register Three bit instructions can be serially loaded into the instruction register This register is loaded when it is placed between the TDI and TDO pins as shown in TAP Controller Block Diagram on page 15 Upon power up the instruction register is loaded with the IDCODE instruct
28. e without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Any Source Code software and or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign United States copyright laws and international treaty provisions Cypress hereby grants to licensee a personal non exclusive non transferable license to copy use modify create derivative works of and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement Any repro
29. ects are sampled on the same edge as the data Deselecting a Nibble Write Select ignores the corresponding nibble of data and it is not written into the device Input Synchronous Byte Write Select 0 1 2 and 3 Active LOW Sampled on the rising edge of the K and K clocks during write operations Used to select which byte is written into the device during the current portion of the write operations Bytes not written remain unaltered CY7C1425JV18 BWS controls Dyg oj CY7C1412JV18 BWSp controls Drg oj BWS controls Dr 7 9 CY7C1414JV18 BWSj controls Drg gj BWS controls Dr 7 BWSs controls D26 48j and BWS controls D 35 27 Al the Byte Write Selects are sampled on the same edge as the data Deselecting a Byte Write Select ignores the corresponding byte of data and it is not written into the device Input Synchronous Address Inputs Sampled on the rising edge of the K Read address and K Write address clocks during active read and write operations These address inputs are multiplexed for both read and write operations Internally the device is organized as 4M x 8 2 arrays each of 2M x 8 for CY7C1410JV18 4M x 9 2 arrays each of 2M x 9 for CY7C1425JV18 2M x 18 2 arrays each of 1M x 18 for CY7C1412JV18 and 1M x 36 2 arrays each of 512K x 36 for CY7C1414JV18 Therefore only 21 address inputs are needed to access the entire memory array of CY7C1410JV18 and CY7C1425JV18 20 address inputs for CY7C1412JV18 an
30. elay Lock Loop DLL that is designed to function between 120 MHz and the specified maximum clock frequency During power up when the DOFF is tied HIGH the DLL is locked after 1024 cycles of stable clock The DLL can also be reset by slowing or stopping the input clock K and K for a minimum of 30 ns However it is not necessary to reset the DLL to lock to the desired frequency The DLL automatically locks 1024 clock cycles after a stable clock is presented The DLL may be disabled by applying ground to the DOFF pin When the DLL is turned off the device behaves in ODR I mode with one cycle latency and a longer access time For information refer to the application note DLL Considerations in QDRII DDRII Figure 1 Application Example SRAM 1 DATA IN DATA OUT Address RPSH R 2500hms SRAM 2 zQ R 2500hms BUS WPS BWS CLKIN CLKIN MASTER CPU or Source K ASIC Source K Delayed K WW R R 500hms Vt Vddq 2 Delayed K Document 001 12561 Rev D Page 9 of 26 Feedback LE CY7C1410JV18 CY7C1425JV18 CYPRESS CY7C1412JV18 CY7C1414JV18 Truth Table The truth table for CY7C1410JV18 CY7C1425JV18 CY7C1412JV18 and CY7C1414JV18 follows 2 9 4 5 6 7 Operation K RPS WPS DQ DQ Write Cycle L H X L D A O atK t f D A 1 at K t T Load address on the rising edge of K input write data
31. ess Port TAP in the FBGA package This part is fully compliant with IEEE Standard 1149 1 2001 The TAP operates using JEDEC standard 1 8V IO logic levels Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature To disable the TAP controller TCK must be tied LOW Vss to prevent clocking of the device TDI and TMS are inter nally pulled up and may be unconnected They may alternatively be connected to Vpp through a pull up resistor TDO must be left unconnected Upon power up the device comes up in a reset state which does not interfere with the operation of the device Test Access Port Test Clock The test clock is used only with the TAP controller All inouts are captured on the rising edge of TCK All outputs are driven from the falling edge of TCK Test Mode Select TMS The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK This pin may be left unconnected if the TAP is not used The pin is pulled up inter nally resulting in a logic HIGH level Test Data In TDI The TDI pin is used to serially input information into the registers and can be connected to the input of any of the registers The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register For information on loading the instruction register see the TAP Controller State Diagram on page 14 TDI is internally pulled up and can b
32. ich enables each port to operate independently All synchronous inputs pass through input registers controlled by the K or K input clocks All data outputs pass through output registers controlled by the C or C or K or K in a single clock domain input clocks Writes are conducted with on chip synchronous self timed write circuitry Description 267 MHz 250 MHz Unit Maximum Operating Frequency 267 250 MHz Maximum Operating Current x8 1330 1200 mA x9 1330 1200 x18 1370 1230 x36 1460 1290 Cypress Semiconductor Corporation Document 4 001 12561 Rev D 198 Champion Court San Jose CA 95134 1709 408 943 2600 Revised March 10 2007 Feedback LE CY7C1410JV18 CY7C1425JV18 Sag CYPRESS CY7C1412JV18 CY7C1414JV18 PERFORM Logic Block Diagram CY7C1410JV18 Address Register Write Write gt Reg Reg Address 21 A 20 0 7 gt Register 3 5 o E lt o o co a x x a co co O O K 9p z F F E 2 z E 8 i i Read Data Reg Control Logic Block Diagram CY7C1425JV18 9 Dis 0 Address Register ZN A 20 0 Address Register Keny 6 X NZ Kelly 6 x WZ Control Logic Write Add Decode Read Add Decode Read Data Reg VREF ca WPS Control
33. ion It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section When the TAP controller is in the Capture IR state the two least significant bits are loaded with a binary 01 pattern to allow for fault isolation of the board level serial test path Bypass Register To save time when serially shifting data through registers it is sometimes advantageous to skip certain chips The bypass register is a single bit register that can be placed between TDI and TDO pins This enables shifting of data through the SRAM with minimal delay The bypass register is set LOW Vss when the BYPASS instruction is executed Boundary Scan Register The boundary scan register is connected to all of the input and output pins on the SRAM Several No Connect NC pins are also included in the scan register to reserve pins for higher density devices The boundary scan register is loaded with the contents of the RAM input and output ring when the TAP controller is in the Capture DR state and is then placed between the TDI and TDO pins when the controller is moved to the Shift DR state The EXTEST SAMPLE PRELOAD and SAMPLE Z instructions can be used to capture the contents of the input and output ring The Boundary Scan Order on page 18 shows the order in which the bits are connected Each bit corresponds to one of the bumps on the SRAM package The MSB of the register is connected to T
34. ive input clock only K Each port select input can deselect the specified port Deselecting a port does not affect the other port All pending transactions read and write are completed prior to the device being deselected Page 8 of 26 Feedback gt S ae 2 CYPRESS s PERFORM 4 Programmable Impedance An external resistor RQ must be connected between the ZQ pin on the SRAM and Vss to allow the SRAM to adjust its output driver impedance The value of RQ must be 5x the value of the intended line impedance driven by the SRAM The allowable range of RQ to guarantee impedance matching with a tolerance of 15 is between 1750 and 350Q with Vppq 1 5V The output impedance is adjusted every 1024 cycles upon power up to account for drifts in supply voltage and temperature Echo Clocks Echo clocks are provided on the QDR II to simplify data capture on high speed systems Two echo clocks are generated by the QDR II CQ is referenced with respect to C and CQ is referenced with respect to C These are free running clocks and are synchronized to the output clock C C of the QDR II In single Application Example Figure 1 shows two QDR II used in an application CY7C1410JV18 CY7C1425JV18 CY7C1412JV18 CY7C1414JV18 clock mode CQ is generated with respect to K and CQ is generated with respect to K The timing for the echo clocks is shown in the Switching Characteristics on page 22 DLL These chips utilize a D
35. n a design to stop or slow the clock during a SAMPLE PRELOAD instruction If this is an issue it is still possible to capture all other signals and simply ignore the value of the CK and CK captured in the boundary scan register After the data is captured it is possible to shift out the data by putting the TAP into the Shift DR state This places the boundary scan register between the TDI and TDO pins PRELOAD places an initial data pattern at the latched parallel outputs of the boundary scan register cells before the selection of another boundary scan test operation The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required that is while the data captured is shifted out the preloaded data can be shifted in Document 001 12561 Rev D CY7C1410JV18 CY7C1425JV18 CY7C1412JV18 CY7C1414JV18 BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift DR state the bypass register is placed between the TDI and TDO pins The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board EXTEST The EXTEST instruction drives the preloaded data out through the system output pins This instruction also connects the boundary scan register for serial access between the TDI and TDO in the Shift DR controller state EXTEST OUTPUT BUS TRI STATE IEEE Standard 1149 1 mandates that
36. nce CY7C1410JV18 only the upper nibble Drz 4 is written into the device Drs 9j remains unaltered CY7C1412JV18 only the upper byte Doa is written into the device Dig remains unaltered H L L H During the data portion of a write sequence CY7C1410JV18 only the upper nibble Drz 4 is written into the device Dr 9j remains unaltered CY7C1412JV18 only the upper byte Dasa is written into the device Dig remains unaltered L H No data is written into the devices during this portion of a write operation L H No data is written into the devices during this portion of a write operation Notes 2 X Don t Care H Logic HIGH L Logic LOW f represents rising edge 3 Device powers up deselected with the outputs in a tri state condition 4 A represents address location latched by the devices when transaction was initiated A 0 A 1 represents the internal address sequence in the burst 5 i represents the cycle at which a Read Write operation is started t 1 and t 2 are the first and second clock cycles respectively succeeding the t clock cycle 6 Data inputs are registered at K and K rising edges Data outputs are delivered on C and C rising edges except when in single clock mode 7 Itis Me that K K and C C HIGH when clock is stopped This is not essential but permits most rapid restart by overcoming transmission line charging symmetrically Ls 8 Is b
37. ns Hold Times tha tkKHAX Address Hold after K Clock Rise 0 3 0 35 ns tuc tKHIX Control Hold after K Clock Rise RPS WPS 0 3 035 ns tucppR tkHIX DDR Control Hold after Clock K K Rise BWS BWS BWS BWS 0 3 0 35 ns tup tKHDX Dyx oj Hold after Clock K K Rise 0 3 035 ns Output Times tco tcHav C C Clock Rise or K K in Single Clock Mode to Data Valid 045 0 45 ns tDoH tcHax Data Output Hold after Output C C Clock Rise Active to Active 0 45 0 45 ns tccoo tcHcav C C Clock Rise to Echo Clock Valid 10 45 045 ns tcaoH tcHcax Echo Clock Hold after C C Clock Rise 0 45 0 45 ns tcap tcaHav Echo Clock High to Data Valid 027 0 30 ns tcopoH tcoHox Echo Clock High to Data Invalid 0 27 0 30 ns tcu tcaHcaL lOutput Clock CQ CQ HIGH 2l 143 155 ns icoHcaH icoHcaH CQ Clock Rise to CQ Clock Rise rising edge to rising edge 72 1 43 1 55 ns tcuz tcHaz Clock C C Rise to High Z Active to High Z 23 24 045 0 45 ns terz tcHaxi Clock C C Rise to Low z PS 24 0 45 0 45 ns DLL Timing tke Var tkc Var Clock Phase Jitter 020 0 20 ns tkc lock KC lock DLL Lock Time K C 1024 1024 Cycles tkc Reset tKC Reset K Static to DLL Reset 30 30 ns Notes 20 When a part with a maximum freguency above 250 MHz is operating at a lower clock freguency it reguires the input timing of the freguency
38. oard back to the controller See Application Example on page 9 for further details Input Clock Positive Input Clock Input The rising edge of K is used to capture synchronous inputs to the device and to drive out data through Qro when in single clock mode All accesses are initiated on the rising edge of K Al Input Clock Negative Input Clock Input K is used to capture synchronous inputs being presented to the device and to drive out data through Qr when in single clock mode Document 001 12561 Rev D Page 6 of 26 Feedback CY7C1410JV18 CY7C1425JV18 CY7C1412JV18 CY7C1414JV18 Pin Description CQ is Referenced with Respect to C This is a free running clock and is synchronized to the Input clock for output data C of the QDR II In the single clock mode CQ is generated with respect to K The Pin Name Echo Clock timings for the echo clocks is shown in the Switching Characteristics on page 22 CQ is Referenced with Respect to C This is a free running clock and is synchronized to the Input clock for output data C of the QDR II In the single clock mode CQ is generated with respect to K The CO Echo Clock Pin Definitions continued IO timings for the echo clocks is shown in the Switching Characteristics on page 22 Output Impedance Matching Input This input is used to tune the device outputs to the system data bus impedance CQ CQ and Q 9 output impedan
39. on K and K rising edges Read Cycle L H L X Q A 0 at C t 1 T Q A 1 at C t 2 T Load address on the rising edge of K _ wait one and a half cycle read data on C and C rising edges NOP No Operation L H H H D X D X Q High Z Q High Z Standby Clock Stopped Stopped X X Previous State Previous State Write Cycle Descriptions The write cycle description table for CY7C1410JV18 and CY7C1412JV18 follows I 8 BWS BWS NWS NWS L L L H During the data portion of a write sequence CY7C1410JV18 both nibbles Dr oj are written into the device CY7C1412JV18 both bytes Dri cg are written into the device L L L H During the data portion of a write sequence CY7C1410JV18 both nibbles Dr oj are written into the device CY7C1412JV18 both bytes Do are written into the device L H L H During the data portion of a write sequence CY7C1410JV18 only the lower nibble Dr is written into the device Dr7 4 remains unaltered CY7C1412JV18 only the lower byte Dya oj is written into the device Dr7 9 remains unaltered K K Comments L H L H During the data portion of a write sequence CY7C1410JV18 only the lower nibble Djs is written into the device Dr 4j remains unaltered CY7C1412JV18 only the lower byte Djg o is written into the device Dr7 9j remains unaltered H L L H During the data portion of a write seque
40. smaller Document 001 12561 Rev D Page 20 of 26 Feedback CY7C1410JV18 CY7C1425JV18 CY7C1412JV18 CY7C1414JV18 AC Electrical Characteristics Over the Operating Range Parameter Description Test Conditions Min Typ Max Unit Vin Input HIGH Voltage VRep 0 2 V Vi Input LOW Voltage E Vrer 0 2 V Capacitance Tested initially and after any design or process change that may affect these parameters Parameter Description Test Conditions Max Unit Cin Input Capacitance Ta 25 C f 1 MHz Vpp 1 8V Vppo 1 5V 5 pF Celk Clock Input Capacitance 4 pF Co Output Capacitance 5 pF Thermal Resistance Tested initially and after any design or process change that may affect these parameters ii 165 FBGA 1 Parameter Description Test Conditions Package Unit OJA Thermal Resistance Test conditions follow standard test methods and 17 2 C W Junction to Ambient procedures for measuring thermal impedance in 8jc Thermal Resistance accordance with EIA JESDS51 32 C W Junction to Case AC Test Loads and Waveforms Vngr 0 75V Vner o 9 75V OUTPUT VREF 9075V R 500 19 ALL INPUT PULSES Device OUTPUT 1 25V Under Devi TN NI Test tinder 5 pF 0 25V ma Vper 075V test ZO IL Slew Rate 2 V ns RO RO 2500 2500 a INCLUDING JIG AND b SCOPE Note pulse levels of
41. tates the outputs following the next rising edge of the output clocks C C This allows for a seamless transition between devices without the insertion of wait states in a depth expanded memory Document 001 12561 Rev D CY7C1410JV18 CY7C1425JV18 CY7C1412JV18 CY7C1414JV18 Write Operations Write operations are initiated by asserting WPS active at the rising edge of the positive input clock K On the same K clock rise the data presented to Dr 7 9 is latched and stored into the lower 18 bit write data register provided BWSj1 9 are both asserted active On the subsequent rising edge of the negative input clock K the address is latched and the information presented to Dr 7 oj is stored into the write data register provided BWS oj are both asserted active The 36 bits of data are then written into the memory array at the specified location When deselected the write port ignores all inputs after completion of pending write operations Byte Write Operations Byte write operations are supported by the CY7C1412JV18 A write operation is initiated as described in the Write Operations section The bytes that are written are determined by BWS and BWS which are sampled with each 18 bit data word Asserting the byte write select input during the data portion of a write latches the data being presented and writes it into the device Deasserting the byte write select input during the data portion of a write allows the dat
42. tputs of the Device Vppa Page 7 of 26 Feedback Document 001 12561 Rev D P CYPRESS PERFORM Functional Overview The CY7C1410JV18 CY7C1425JV18 CY7C1412JV18 and CY7C1414JV18 are synchronous pipelined Burst SRAMs with a read port and a write port The read port is dedicated to read operations and the write port is dedicated to write operations Data flows into the SRAM through the write port and flows out through the read port These devices multiplex the address inputs to minimize the number of address pins required By having separate read and write ports the QDR II completely eliminates the need to turn around the data bus and avoids any possible data contention thereby simplifying system design Each access consists of two 8 bit data transfers in the case of CY7C1410JV18 two 9 bit data transfers in the case of CY7C1425JV18 two 18 bit data transfers in the case of CY7C1412JV18 and two 36 bit data transfers in the case of CY7C1414JV18 in one clock cycle This device operates with a read latency of one and half cycles when DOFF pin is tied HIGH When DOFF pin is set LOW or connected to Vss then the device behaves in QDR I mode with a read latency of one clock cycle Accesses for both ports are initiated on the rising edge of the positive input clock K All synchronous input timing is referenced from the rising edge of the input clocks K and K and all output timing is referenced
43. uction register at power up or whenever the TAP controller is given a Test Logic Reset state SAMPLE Z The SAMPLE Z instruction connects the boundary scan register between the TDI and TDO pins when the TAP controller is ina Shift DR state The SAMPLE Z command puts the output bus into a High Z state until the next command is given during the Update IR state SAMPLE PRELOAD SAMPLE PRELOAD is a 1149 1 mandatory instruction When the SAMPLE PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture DR state a snapshot of data on the input and output pins is captured in the boundary scan register The user must be aware that the TAP controller clock can only operate at a freguency up to 20 MHz while the SRAM clock operates more than an order of magnitude faster Because there is a large difference in the clock freguencies it is possible that during the Capture DR state an input or output undergoes a transition The TAP may then try to capture a signal while in transition metastable state This does not harm the device but there is no guarantee as to the value that is captured Repeatable results may not be possible To guarantee that the boundary scan register captures the correct value of a signal the SRAM signal must be stabilized long enough to meet the TAP controller s capture setup plus hold times tcs and toy The SRAM clock input might not be captured correctly if there is no way i
44. uss Test Mode Select TYE C NI Kix TDIS Test Data In a TDI s NA a XE Test Data Out TDO trpov trpox 13 tcs and toy refer to the setup and hold time requirements of latching data from the boundary scan register 14 Test conditions are specified using the load in TAP AC Test Conditions tp tp lt 1 ns Document 001 12561 Rev D Page 16 of 26 Feedback pe a J CYPRESS PER FORM Identification Register Definitions CY7C1410JV18 CY7C1425JV18 CY7C1412JV18 CY7C1414JV18 Value Instruction Field Description CY7C1410JV18 CY7C1425JV18 CY7C1412JV18 CY7C1414JV18 Revision Number 001 001 001 001 Version number 31 29 Cypress Device ID 11010011010000111 11010011010001111 11010011010010111 11010011010100111 Defines the type of 28 12 SRAM Cypress JEDEC ID 00000110100 00000110100 00000110100 00000110100 Allows unigue 11 1 identification of SRAM vendor ID Register 1 1 1 1 Indicates the Presence 0 presence of an ID register Scan Register Sizes Register Name Bit Size Instruction 3 Bypass 1 ID 32 Boundary Scan 109 Instruction Codes Instruction Code Description EXTEST 000 Captures the input and output ring contents IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO
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