Cypress CY7C1386D User's Manual
Contents
1. l W W T x SZ gt Truth Table for Read Write 5 91 Function CY7C1387D CY7C1387F m gt Write Byte A DQ Write Byte B DQg DQPg Write All Bytes Write All Bytes z 8 x gt x 2 Note 9 Table only lists a partial listing of the byte write combinations Any Combination of BW is valid Appropriate write will be done based on which byte write is active Document Number 38 05545 Rev E Page 10 of 30 Feedback CYPRESS PERFORM III IEEE 1149 1 Serial Boundary Scan JTAG The CY7C1386D CY7C1387D CY7C1386F CY7C1387F incorporates a serial boundary scan test access port TAP This part is fully compliant with 1149 1 The TAP operates using JEDEC standard 3 3V or 2 5V IO logic levels The CY7C1386D CY7C1387D CY7C1386F CY7C1387F contains a TAP controller instruction register boundary scan register bypass register and ID register Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature To disable the TAP controller TCK must be tied LOW Vss to preven2. PEE p DQP p DQpoDQPo BWo N BYTE J y WRITE REGISTER D WRITE DRIVER DQ DOP c DQcDOP seii BWc BYTE Be L D TDH WRITEREGISTER 4 WRITE DRIVER ARRAY E OUTPUT OUTPUT ids N AMPS REGISTERS iis Loa 2 N p BYTE i bar 8 aD D TDH WRITE REGISTER _ WRITE DRIVER 5 __ 4 DQXDQP A ae ato BWa BYTE p wRITEDRIVER BWE D WRITEREGISTER me INPUT GW ENABLE REGISTERS REGISTER PIPELINED ENABLE OE hd Ld SLEEP 2 CONTROL Logic Block Diagram CY7C1387D CY7C1387F F 1M x 18 A0 AT A ADDRESS REGISTER 21 MODE ADV Q BURST COUNTER AND LOGIC an 00 4 ADSC ADSP DOP DOP s SN BYTE RE BYTE 3 3 awe N N WRITE REGISTER J y NHN SENSE OUTPUT OUTPUT 00 V MEMORY AMPS gt REGISTERS BUFFERS ie A 00 DOP A e E Tr BYTE e gt ware DRIVER E D O WRITE REGISTER T INPUT GW ENABLE REGISTERS REGISTER PIPELINED dH ENABLE H OE e 7 SLEEP i CONTROL Note 22 3 CY7C1386F and CY7C1387F have only 1 Chip Enable CE Document Number 38 05545 Rev E Page 2 of 30 Feedback YPRESS PERFORM i s Pin Configurations CY7C1386D CY7C1386F CY7C1387D CY7C1387F 100 pin TQFP Pinout 3 Chip Enables
3. tas 17 ADSP initiates burst m A LZ o twes A 2 D XT y zu 7 Z m ADVH E lt gt x VALL 2 i ADV suspends burst i CL Data in D WES You ZTE DAS gt X BURST READ gt single WRITE BURST WRITE Extended BURST WRITE ER DON T CARE Ke UNDEFINED Note 27 Full width write can be initiated by either GW LOW or by GW HIGH BWE LOW BW LOW Document Number 38 05545 Rev E Page 22 of 30 Feedback e CY7C1386D CY7C1386F CYPRESS CY7C1387D CY7C1387F PERFORM Switching Waveforms continued Read Write Cycle Timing 26 28 29 ADDRESS A X m X M AS A6 BWE BW x ADV Data In D pts oa Data Out Q X Kona Yanna Los Back to Back READs WRITE lt BURST READ gt Back to Back WRITEs DON T CARE UNDEFINED Notes 28 The data bus Q remains in high Z following a Write cycle unless a new read access is initiated by ADSP or ADSC 29 GW is HIGH Document Number 38 05545 Rev E Page 23 of 30 Feedback CYPRESS PERFORM Switching Waveforms continu
4. s r b crr a SSE rsh smmr T YPRESS CY7C1386D CY7C1386F CY7C1387D CY7C1387F PERFORM 18 Mbit 512K x 36 1 Mbit x 18 Pipelined DCD Sync SRAM Features Supports bus operation up to 250 MHz Available speed grades 250 200 and 167 MHz Registered inputs and outputs for pipelined operation Optimal for performance double cycle deselect Depth expansion without wait state 3 3V core power supply Vpp 2 5V or 33V IO power supply Vppq Fast clock to output times 2 6 ns for 250 MHz device Provides high performance 3 1 1 1 access rate User selectable burst counter supporting Intel Pentium interleaved or linear burst sequences Separate processor and controller address strobes Synchronous self timed writes Asynchronous output enable CY7C1386D CY7C1387D available in JEDEC standard Pb free 100 pin TQFP Pb free and non Pb free 165 ball FBGA package CY7C1386F CY7C1387F available in Pb free and non Pb free 119 ball BGA package IEEE 1149 1 JTAG Compatible Boundary Scan ZZ sleep mode option Selection Guide Functional Description 1 The CY7C1386D CY7C1387D CY7C1386F CY7C1387F SRAM integrates 512K x 36 1M x 18 SRAM cells with advanced synchronous peripheral circuitry and a two bit counter for internal burst operation All synchronous inputs are gated by registers controlled by a positive e
5. A A CE CE BWp BW BW BW CE Vss CLK GW BWE OE ADSC ADSP 99 98 97 96 95 94 93 92 91 90 89 88 87 86 Q O Q gt Q N 100 15 CY7C1386D 17 512K X 36 Vss DQPpL 43 34 45 C cO st 41 31 32 33 35 36 37 38 39 85 84 2 1 47 4 4 5 UU UU lt lt lt lt 4 gt 72 NC 36M Document Number 38 05545 Rev E 8 8 lt lt lt lt lt lt lt lt lt DOP Vssa DOs DQs DQs Vssa DQg DQg Vss NC ZZ DQ DQ Vssa DQ DQ DQ Vssa DQ DQ DOP NC NC NC Vssa NC NC Vssa NC NC Vss Vppo Vssa DQ DOP NC Vssa NC NC A A CE CE NC NC BWB BWA Vpp Vss CLK GW BWE OE ADSC ADSP LOTT CTE ATE n N 100 99 98 97 96 95 94 9 92 91
6. 0 165V unless otherwise noted 12 Parameter Description Test Conditions Min Max Unit Output HIGH Voltage lou 4 0 mA VDDQ 3 3V 2 4 V loH 1 0 mA VDDQ 2 5 2 0 V Output HIGH Voltage lon 100 Vppo 9 3V 2 9 V Vppo 2 5 2 1 V Output LOW Voltage lot 8 0 mA VDDQ 3 3V 0 4 V loL 8 0 mA Vppo 2 5 0 4 V Voi2 Output LOW Voltage 100 Vppo 9 3V 0 2 V Vppo 2 5 0 2 V Input HIGH Voltage Vppq 3 3V 2 0 Vpp 0 3 V VDDQ 2 5V 1 7 Vpp 0 3 V Vit Input LOW Voltage Vppo 3 3V 0 5 0 7 V Vppo 2 5V 0 3 0 7 V Ix Input Load Current GND lt Vin Vppo 5 5 Note 12 All voltages referenced to Vss GND Document Number 38 05545 Rev E Page 14 of 30 Feedback 2 CYPRESS j PERFORM Identification Register Definitions CY7C1386D CY7C1386F CY7C1387D CY7C1387F Instruction Field CC SI x 96 nur Description Revision Number 31 29 000 000 Describes the version number Device Depth 28 24 113 01011 01011 Reserved for internal use Device Width 23 18 119 BGA 101110 101110 Defines the memory type and architecture Device Width 23 18 165 FBGA 000110 000110 Defines the memory type and architecture Cypress Device ID 17 12 100101 010101 Defines the width and density Cypress JEDEC ID Code 11 1 00000110100 00000110100 Allows unique identifica
7. 10 2 5V 5 0 5V to Vppo 0 5V Industrial 40 to 85 C to Vpp Electrical Characteristics Over the Operating Range 17 18 Parameter Description Test Conditions Min Max Unit Vpp Power Supply Voltage 3 135 3 6 V Vppo IO Supply Voltage for 3 3V IO 3 135 Vpp V for 2 5V IO 2 375 2 625 V VoH Output HIGH Voltage for 3 3V IO lop 4 0 mA 2 4 V for 2 5V IO lop 1 0 mA 2 0 V VoL Output LOW Voltage for 3 3V IO Io 8 0 mA 0 4 V for 2 5V IO Io 1 0 mA 0 4 V Input HIGH Voltage for 3 3V IO 20 Vpp 0 3V V for 2 5V IO 1 7 Vpp 03V V Input LOW Voltage for 3 3V IO 0 3 0 8 V for 2 5V IO 0 3 0 7 V lx Input Leakage Current GND lt lt Vppo 5 5 uA except ZZ and MODE Input Current of MODE Input Vas 30 uA Input Vpp 5 Input Current of ZZ Input Vss 5 uA Input Vpp 30 loz Output Leakage Current GND lt V lt Output Disabled 5 5 uA 155 Vpp Operating Supply Vpp Max 0 4 ns cycle 250 MHz 350 mA Current f fmax 1 tcyc 5 ns cycle 200 MHz 300 mA 6 ns cycle 167 MHz 275 mA Isp4 Automatic CE Vpp Max Device Deselected 4 ns cycle 250 MHz 160 mA 6 ns cycle 167 MHz 140 mA Isp2 Automatic CE Vpp Max Device Deselected All speeds 70 mA Power Down Vin lt 0 3V or Vin Vppo 0 3V Current CMOS Inputs f 0 Automatic CE Vpp Max Device Deselected or 4 ns cycle 250 MHz 135 mA lt DOMOS inputs Vov
8. Pipelined DCD Sync SRAM Document Number 38 05545 REV NO Issue Date Change Description of Change 254550 See ECN RKF New data sheet A 288531 See ECN SYT Edited description under IEEE 1149 1 Serial Boundary Scan JTAG for non compliance with 1149 1 Removed 225Mhz Speed Bin Added Pb free information for 100 pin TQFP 119 BGA and 165 FBGA Packages Added comment of Pb free BG packages availability below the Ordering Information B 326078 See ECN PCI Address expansion pins balls in the pinouts for all packages are modified as per JEDEC standard Added description on EXTEST Output Bus Tri State Changed description on the Tap Instruction Set Overview and Extest Changed Device Width 23 18 for 119 BGA from 000110 to 101110 Added separate row for 165 FBGA Device Width 23 18 Changed and for TQFP Package from 31 and 6 C W to 28 66 and 4 08 C W respectively Changed j4 and jc for BGA Package from 45 and 7 C W to 23 8 and 6 2 C W respectively Changed 4 and for FBGA Package from 46 and 3 C W to 20 7 4 0 C W respectively Modified VoL Vox test conditions Removed comment of Pb free BG packages availability below the Ordering Information Updated Ordering Information Table 418125 NXR Converted from Preliminary to Final Changed address of Cypress Semiconductor Corporation on Page 1 from 3901 North First Street to 198 Champion
9. 4 1 5 ns tcEs Chip Enable Set Up Before CLK Rise 1 2 1 4 1 5 ns Hold Times tay Address Hold After CLK Rise 0 3 0 4 0 5 ns tADH ADSP ADSC Hold After CLK Rise 0 3 0 4 0 5 ns tADVH ADV Hold After CLK Rise 0 3 0 4 0 5 ns GW BWE BW Hold After CLK Rise 0 3 0 4 0 5 ns Data Input Hold After CLK Rise 0 3 0 4 0 5 ns tcEH Chip Enable Hold After CLK Rise 0 3 0 4 0 5 ns Notes 20 Timing reference level is 1 5V when Vppq 3 3V and is 1 25V when 2 5V 21 Test conditions shown in a of AC Test Loads unless otherwise noted 22 This part has a voltage regulator internally tpower is the time that the power needs to be supplied above Vpp minimum initially before a read or write operation can be initiated 23 tcHz tcLz toELz and are specified with AC test conditions shown b of AC Test Loads Transition is measured 200 mV from steady state voltage 24 At any given voltage and temperature togpz is less than tog z and is less than tc z to eliminate bus contention between SRAMs when sharing the same data bus These specifications do not imply a bus contention condition but reflect parameters guaranteed over worst case user conditions Device is designed to achieve High Z prior to Low Z under the same system conditions 25 This parameter is sampled and not 100 tested Document Number 38 05545 Rev E Page 20 of 30 Feedback gt CY7C1386D CY7C1386F CYPRESS CY7C1387D CY7C1387F PERFO
10. CY7C1387D 250BZl CY7C1386D 250BZXI 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb Free CY7C1387D 250BZXI Document Number 38 05545 Rev E Page 26 of 30 Feedback CY7C1386D CY7C1386F F CYPRESS CY7C1387D CY7C1387F PERFORM Package Diagrams Figure 1 100 Pin Thin Plastic Quad Flat pack 14 x 20 x 1 4 mm 51 85050 16 00 0 20 La 14004010 1 40 0 05 100 ABAAAAS AARAARAARAAAR Fal Toy 80 En 0 30 0 08 l ES I I co 8 Es 8 8 jJ T E ES En 0 65 12 41 SEE DETAIL A 8 A FS 51 ed 1 BHBHBHHHHHHBHHHHHHHBHHH v a 31 50 0 20 MAX 1 60 R 0 08 MIN 0 20 MAX 0 MIN SEATING PLANE STAND OFF q 0 05 MIN NOTE 0 15 J 1 JEDEC STD REF 5 026 i 2 BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION END FLASH R 0 08 MIN MOLD PROTRUSION END FLASH SHALL NOT EXCEED 0 0098 in 0 25 mm PER SIDE 0 7 020 BODY LENGTH DIMENSIONS ARE PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 3 DIMENSIONS IN MILLIMETERS 0 60 0 15 0 20 MIN 51 85050 B 1 00 REF DETAIL A Document Number 38 05545 Rev E Page 27 of 30 Feedback CY7C1386D CY7C1386F CY7C1387D CY7C1387F CYPRESS Package Diagrams continu
11. Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb Free CY7C1387D 167BZXC CY7C1386D 167AXI 51 85050 100 pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Pb Free Industrial CY7C1387D 167AXI CY7C1386F 167BGI 51 85115 119 ball Ball Grid Array 14 x 22 x 2 4 mm CY7C1387F 167BGI CY7C1386F 167BGXI 51 85115 119 ball Ball Grid Array 14 x 22 x 2 4 mm Pb Free CY7C1387F 167BGXI CY7C1386D 167BZl 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm CY7C1387D 167BZl CY7C1386D 167BZXl 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb Free CY7C1387D 167BZXl 200 CY7C1386D 200AXC 51 85050 100 pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Pb Free Commercial CY7C1387D 200AXC CY7C1386F 200BGC 51 85115 119 ball Ball Grid Array 14 x 22 x 2 4 mm CY7C1387F 200BGC CY7C1386F 200BGXC 51 85115 119 ball Ball Grid Array 14 x 22 x 2 4 mm Pb Free CY7C1387F 200BGXC CY7C1386D 200BZC 51 85180 165 ball Fine Pitch Ball Grid Array 13 15 x 1 4 mm CY7C1387D 200BZC CY7C1386D 200BZXC 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb Free CY7C1387D 200BZXC CY7C1386D 200AXI 51 85050 100 pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Pb Free Industrial CY7C1387D 200AXI CY7C1386F 200BGI 51 85115 119 ball Ball Grid Array 14 x 22 x 2 4 mm CY7C1387F 200BGI CY7C1386F 200BGXI 51 85115 119 ball Ball Grid Array 14 x 22 x 2 4 mm Pb Free CY7C1387F 200BGXI CY7C1386D 200BZl 51 85180 165 ball Fine Pitch Bal
12. Vss NC DQ F Vss OE Vss DQA Vppo G NC DQ BWB ADV NC NC DQA H DQg NC Vss GW Vss DQ NC J VDDQ VDD NC VDD NC VDD VDDQ K NC Dg Vss CLK Vss NC DQ L BWA DQA NC M Vppo DQg Vss BWE Vss NC Vppo N DQg NC Vss A1 Vss DQ NC P DGP amp Vss Vss NC DQA R NC MODE NC A NC T NC 72M A A NC 36M A A ZZ Voo TMS TDI TCK TDO NC Wigs Document Number 38 05545 Rev E Page 4 of 30 Feedback CY7C1386D CY7C1386F CYPRESS CY7C1387D CY7C1387F Pin Configurations continued 165 Ball FBGA Pinout 3 Chip Enable CY7C1386D 512K x 36 1 2 3 4 5 6 7 8 9 10 11 288 CE BWc BWg CE3 BWE ADSC ADV A NC B NC 44M A CE BWp BWA CLK GW OE ADSP A NC 512M C DQPc NC Vppo Vss Vss Vss Vss Vss Vppo NC 1G DQPg D DQc DQc Vpp Vss Vss Vss Vpp Vppo DQg E Vss Vss Vss Vpp Vppo DQg F DQc Vpp Vss Vss Vss Vpp Vppo DQc DQc Vppo Vpp Vss Vss Vss Vpp Vppo DQg Vpp Vss Vss Vss Vpp NC NC ZZ J DQp DQp Vppa Vpp Vss Vss Vss Vpp DQA K DQp Vppo Vpp Vss Vss Vss Vpp Vppo DQA DQA L DQp Vpp Vss Vss Vss Vpp VDDQ DQA DQA M DQp Vss Vss Vss V
13. register The user must be aware that the TAP controller clock can only operate at a frequency up to 20 MHz while the SRAM clock operates more than an order of magnitude faster As there is a large difference in the clock frequencies it is possible that during the Capture DR state an input or output will undergo a transition The TAP may then try to capture a signal while in transition metastable state This will not harm the device but there is no guarantee as to the value that will be captured Repeatable results may not be possible To guarantee that the boundary scan register will capture the correct value of a signal the SRAM signal must be stabilized long enough to meet the TAP controller s capture setup plus hold times tcs and The SRAM clock input might not be captured correctly if there is no way in a design to stop or slow the clock during a SAMPLE PRELOAD instruction If this is an issue it is still possible to capture all other signals and simply ignore the value of the CK and CK captured in the boundary scan register Once the data is captured it is possible to shift out the data by putting the TAP into the Shift DR state This places the boundary scan register between the TDI and TDO pins PRELOAD allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells prior to the selection of another boundary scan test operation The shifting of data for the SAMPLE an
14. 5 2 16 K11 46 B5 76 N1 17 J11 47 AS 77 N2 18 M10 48 A4 78 P1 19 L10 49 B4 79 R1 20 K10 50 B3 80 R2 21 J10 51 A3 81 P3 22 H9 52 A2 82 R3 23 H10 53 B2 83 P2 24 G11 54 2 84 R4 25 F11 55 B1 85 P4 26 E11 56 A1 86 N5 27 D11 57 C1 87 P6 28 G10 58 D1 88 R6 29 F10 59 E1 89 Internal 30 E10 60 F1 Note 16 Bit 89 is preset HIGH Document Number 38 05545 Rev E Page 17 of 30 Feedback CYPRESS PERFORM Maximum Ratings Exceeding the maximum ratings may impair the useful life of CY7C1386D CY7C1386F CY7C1387D CY7C1387F DC Input Voltage 0 5V to Vpp 0 5V Current into Outputs 24 20 mA the device For user guidelines not tested Static Discharge Voltage gt 2001V Storage Temperature 65 C to 150 C POr MIE STB oio s Ambient Temperature with Latch up Current gt 200 mA Power 55 C to 125 C Operating Range Supply Voltage on Vpp Relative to GND 0 5V to 4 6V Ambient Supply Voltage Relative to GND 0 5V to Vpp Range Temperature DC Voltage Applied to Outputs Commercial 0 C to 70 C 3 3 5
15. 7C1386D CY7C1386F CY7C1387D CY7C1387F Bit Ball ID Bit Ball ID Bit Ball ID Bit Ball ID 1 H4 23 F6 45 G4 67 L1 2 T4 24 E7 46 A4 68 M2 3 T5 25 D7 47 G3 69 N1 4 T6 26 H7 48 C3 70 P1 5 R5 27 G6 49 B2 71 K1 6 L5 28 EG 50 B3 72 L2 7 R6 29 D6 51 A3 73 N2 8 U6 30 C7 52 C2 74 P2 9 R7 31 B7 53 A2 75 R3 10 T7 32 C6 54 B1 76 T1 11 P6 33 A6 55 C1 77 R1 12 N7 34 C5 56 D2 78 T2 13 M6 35 BS 57 E1 79 L3 14 L7 36 G5 58 F2 80 R2 15 K6 37 B6 59 G1 81 T3 16 P7 38 D4 60 H2 82 L4 17 N6 39 B4 61 D1 83 N4 18 L6 40 F4 62 E2 84 P4 19 K7 41 M4 63 G2 85 Internal 20 J5 42 AS 64 H1 21 H6 43 K4 65 J3 22 G7 44 E4 66 2K Notes 14 Balls that are NC No Connect are preset LOW 15 Bit 85 is preset HIGH Document Number 38 05545 Rev E Page 16 of 30 Feedback PERFORM 165 Ball BGA Boundary Scan Order 4 16 CY7C1386D CY7C1386F CY7C1387D CY7C1387F Bit Ball ID Bit Ball ID Bit Ball ID 1 N6 31 D10 61 G1 2 N7 32 C11 62 D2 3 N10 33 A11 63 E2 4 P11 34 B11 64 F2 5 P8 35 A10 65 G2 6 R8 36 B10 66 H1 7 R9 37 A9 67 H3 8 P9 38 B9 68 J1 9 P10 39 C10 69 K1 10 R10 40 A8 70 L1 11 R11 41 B8 71 M1 12 H11 42 AT 72 J2 13 N11 43 B7 73 K2 14 M11 44 B6 74 L2 15 L11 45 7
16. 90 89 88 87 CY7C1387D IM x 18 NC 72M 86 85 84 Page 3 of 30 NC NC DOP DQA Vss NC Vpp ZZ DQ DQ Vsso DQ NC NC Vsso NC NC Feedback e CY7C1386D CY7C1386F Z CYPRESS CY7C1387D CY7C1387F j PERFORM Pin Configurations continued 119 Ball BGA Pinout 1 Chip Enable CY7C1386F 512K x 36 1 2 3 4 5 6 7 A Vppo A A ADSP A A Vppo B NC 28M A ADSC A A NC 576M C 144 A A Vpp A A NC 1G DQPc Vss NC Vss DQg E DQc DQc Vss CE Vss DQg F DQc Vss OE Vss DQg G DQc BWc ADV BW DQg H 0 Vss GW Vss J DQ DQ Vea Vss DQ DO L DQp DQp BWp NC BWA DQA DQA M Vppo DQp Vss BWE Vss DQA Vppo DQ Vss 1 Vss DQa 006 Vss AO Vss DQA R NC A MODE Vpp NC A NC T NC NC 72M A A A NC 36M ZZ U TMS TDI TCK TDO NC CY7C1387F 1M x 18 1 2 3 4 5 6 7 A Vppo A A ADSP A A Vppo B NC 288M A A ADSC A A NC 576M C NC 144M A A Vpp A A NC 1G D DQg NC Ves NC Vss E NC Bag Vss CE
17. CLK As outputs they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle The direction of the pins is controlled by OE When OE is asserted LOW the pins behave as outputs When HIGH DQs and DQPx are placed in a tri state condition Vpp Power Supply Power supply inputs to the core of the device 38 05545 Rev E Page 6 of 30 Feedback CY7C1386D CY7C1386F CY7C1387D CY7C1387F Pin Definitions continued Name IO Description Vss Ground Ground for the core of the device Vsso IO Ground Ground for the IO circuitry VDDQ IO Power Supply Power supply for the IO circuitry MODE Input Selects burst order When tied to GND selects linear burst sequence When tied Static to Vpp or left floating selects interleaved burst sequence This is a strap pin and must remain static during device operation Mode pin has an internal pull up TDO JTAG serial output Serial data out to the JTAG circuit Delivers data on the negative edge of TCK If Synchronous the JTAG feature is not used this pin must be disconnected This pin is not available on TQFP packages TDI JTAG serial Serial data in to the JTAG circuit Sampled on the rising edge of TCK If the JTAG input feature is not used this pin can be disconnected or connected to Vpp This pin is Synchronous not available on TQFP packages TMS JTAG serial Serial data in t
18. Court Changed the description of ly from Input Load Current to Input Leakage Current on page 18 Changed the lx current values of MODE on page 18 from 5 pA and 30 pA to 30 and 5 pA Changed the lx current values of ZZ page 18 from 30 uA and 5 pA to 5 and 30 pA Changed lt Vpp to lt Vppon page 18 Replaced Package Name column with Package Diagram in the Ordering Information table Updated Ordering Information Table D 475009 See ECN VKN Added the Maximum Rating for Supply Voltage on Vppq Relative to GND Changed trr ty from 25 ns to 20 ns and trpov from 5 ns to 10 ns in TAP AC Switching Characteristics table Updated the Ordering Information table E 793579 See ECN VKN Added Part numbers CY7C1386F and CY7C1387F Added footnote 3 regarding Chip Enable Updated Ordering Information table Document Number 38 05545 Rev E Page 30 of 30 Feedback
19. D CY7C1386F CY7C1387D CY7C1387F register When the EXTEST instruction is entered this bit will directly control the output Q bus pins Note that this bit is preset HIGH to enable the output when the device is powered up and also when the TAP controller is in the Test Logic Reset state Reserved These instructions are not implemented but are reserved for future use Do not use these instructions TCK UMSS Pise Test Clock Test Mode Select ac TMS trpis I Test Data In Y 77 TDI 2 trpoy KA 27 E Test Data Out XS XX RY RY X5 TDO DON T CARE UNDEFINED TAP AC Switching Characteristics Over the Operating Range 119 11 Parameter Description Min Max Unit Clock trcvc TCK Clock Cycle Time 50 ns Clock Frequency 20 MHz tty TCK Clock HIGH time 20 ns tr TCK Clock LOW time 20 ns Output Times trpov TCK Clock LOW to TDO Valid 10 ns trpox TCK Clock LOW to TDO Invalid 0 ns Set up Times ttuss TMS Set up to TCK Clock Rise 5 ns trpis TDI Set up to TCK Clock Rise 5 ns Capture Set up to Rise 5 ns Hold Times trMsH TMS Hold after TCK Clock Rise 5 ns trpiH TDI Hold after Clock Rise 5 ns tcH Capture Hold after Clock Rise ns Notes 10 tcs and refer to t
20. D c SCOPE b 2 5V IO Test Load R 16670 OUTPUT 2 5V T ALL INPUT PULSES OUTPUT gio R 500 5 pF R 15380 Vr 1 25V INCLUDING JIG AND c a a scope 9 Note 19 Tested initially and after any design or process change that may affect these parameters Page 19 of 30 Document Number 38 05545 Rev E Feedback 4 Switching Characteristics Over the Operating Range 211 CYPRESS PERFORM CY7C1386D CY7C1386F CY7C1387D CY7C1387F 250 200 167 Parameter tPOWER Vpp Typical to the First Access 22 1 1 1 ms Clock Clock Cycle Time 4 0 5 0 6 0 ns tcH Clock HIGH 1 7 2 0 2 2 ns tcL Clock LOW 1 7 2 0 2 2 ns Output Times tco Data Output Valid after CLK Rise 2 6 3 0 3 4 ns Data Output Hold after CLK Rise 1 0 1 3 1 3 ns iei Clock to Low Z 24 25 1 0 1 3 1 3 ns toyz Clock to High Z 3 24 25 2 6 3 0 3 4 ns OE LOW to Output Valid 2 6 3 0 3 4 ns toELZ OE LOW to Output Low Z 23 24 25 0 0 0 ns toEuz OE HIGH to Output High Z 123 24 251 2 6 3 0 34 ns Set up Times tas Address Set up Before CLK Rise 1 2 1 4 1 5 ns taps ADSC ADSP Set up Before CLK Rise 1 2 1 4 1 5 ns tapvs ADV Set up Before CLK Rise 1 2 1 4 1 5 ns twes GW BWE BW Set up Before CLK Rise 1 2 1 4 1 5 ns tps Data Input Set up Before CLK Rise 1 2 1
21. O A1 4 0 A1 operations 00 01 10 11 CY7C1386D CY7C1387D CY7C1386F CY7C1387F is a common IO device the output enable OE must be 01 10 1 00 deasserted HIGH before presenting data to the inputs 10 11 00 01 Doing so will tri state the output drivers As a safety 11 00 01 10 precaution DQx are automatically tri stated whenever a write cycle is detected regardless of the state of OE ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min Max Unit Ippzz Sleep mode standby current ZZ gt Vpp 0 2V 80 mA 1775 Device operation to ZZ ZZ gt Vpp 0 2V 2tcvc ns tzZREC ZZ recovery time ZZ lt 0 2 2tcyc ns ZZ Active to sleep current This parameter is sampled 2tcvc ns tRzzi ZZ Inactive to exit sleep current This parameter is sampled 0 ns Document Number 38 05545 Rev E Page 8 of 30 Feedback e CY7C1386D CY7C1386F Z CYPRESS CY7C1387D CY7C1387F j PERFORM Truth Table 5 6 7 8 Operation Add Used CE ZZ ADSP ADSC ADV WRITE OE CLK pQ Deselect Cycle Power Down None H X X L X L X X X L H Tri State Deselect Cycle Power Down None L L X L L X X X X L H Tri State Deselect Cycle Power Down None L X H L L X X X X L H Tri State Deselect Cycle Power Down None L L X L H L X X X L H Tri State Deselect Cycle Power Down None L X H L H L X X X L H Tri Sta
22. PLANE f 4 S 51 85180 A 8 S d 5 Intel and Pentium are registered trademarks and i486 is a trademark of Intel Corporation PowerPC is a trademark of IBM Corporation All product and company names mentioned in this document are the trademarks of their respective holders Document Number 38 05545 Rev E Page 29 of 30 Cypress Semiconductor Corporation 2006 2007 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Feedback CY7C1386D CY7C1386F SSSA CYPRESS CY 7013870 CY7C1387F PERFORM III Document History Page Document Title CY7C1386D CY7C1387D CY7C1386F CY7C1387F 18 Mbit 512K x 36 1 Mbit x 18
23. RM Switching Waveforms Read Cycle Timing 26 Wr V g gU G bbb bi OO WIEN ADDRESS 7 Y x YZ Y Burst continued with 1 new base address wes w U w tADVS ADVH 7 D ADV ADV suspends burst AE 1 OE tco t m l l Data Out 00 omea XW on Wan XX as Burst wraps around to its initial state Single READ gt lt BURST READ gt was unoerinen Note __ __ I HR n m 26 On this diagram when is LOW CE is LOW CE is HIGH and CE is LOW When CE is HIGH CE is HIGH or is LOW or CE is HIGH Document Number 38 05545 Rev E Page 21 of 30 Feedback gt CY7C1386D CY7C1386F CYPRESS CY7C1387D CY7C1387F PERFORM Switching Waveforms continued Write Cycle Timing 26 271 I VIN lt i ADS ADH CUT OLD NE X Nr a x 4770 EO 5 Vu VOD V ADDRESS Z 7 5 MLL x y Byte write signals are ignored for first cycle when
24. a DV ns cycle 200 MHz 130 mA 6 ns cycle 167 MHz 125 mA Isp4 Automatic CE Vpp Max Device Deselected All Speeds 80 mA Power Down Vin 2 Vin or Vy lt f 0 Current TTL Inputs Notes 17 Overshoot lt Vpp 1 5V pulse width less than tcyc 2 undershoot Vj AC gt 2V pulse width less than 2 18 up assumes a linear ramp from OV to Vpp min within 200 ms During this time Vi lt and lt Vpp Document Number 38 05545 Rev E Page 18 of 30 Feedback e CY7C1386D CY7C1386F CY7C1387D CY7C1387F Z CYPRESS a a PERFORM 4 Capacitance 91 i 100 TQFP 119 BGA 165 FBGA Parameter Description Test Conditions Max Max Max Unit Cin Input Capacitance TA 25 C f 1 MHz 5 8 9 pF Vpp 9 3V Clock Input Capacitance Vppo 2 5V 5 8 9 pF Cio Input Output Capacitance 5 8 9 pF Thermal Resistance 19 or 100 TQFP 119 BGA 165 FBGA Parameter Description Test Conditions Package Package Package Unit OJA Thermal Resistance Test conditions follow standard 28 66 23 8 20 7 C W Junction to Ambient test methods and procedures for measuring thermal B uc impedance in accordance with ae gt GIW EIA JESD51 AC Test Loads and Waveforms 3 3V IO Test Load R 3170 OUTPUT 3 3V ALL INPUT PULSES OUTPUT 500 5 pF 3510 Vy 1 5V INCLUDING JIG AN
25. d PRELOAD phases can occur concurrently when required that is while data captured is shifted out the preloaded data can be shifted in BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift DR state the bypass register is placed between the TDI and TDO balls The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board EXTEST Output Bus Tri State IEEE Standard 1149 1 mandates that the TAP controller be able to put the output bus into a tri state mode The boundary scan register has a special bit located at bit 85 for 119 BGA package or bit 89 for 165 FBGA package When this scan cell called the extest output bus tri state is latched into the preload register during the Update DR state in Page 12 of 30 Feedback CYPRESS PERFORM III the controller it will directly control the state of the output Q bus pins when the EXTEST is entered as the current instruction When HIGH it will enable the output buffers to drive the output bus When LOW this bit will place the output bus into a High Z condition This bit can be set by entering the SAMPLE PRELOAD or EXTEST command and then shifting the desired bit into that cell during the Shift DR state During Update DR the value loaded into that shift register cell will latch into the preload TAP Timing CY7C1386
26. dge triggered clock input CLK The synchronous inputs include all addresses all data inputs address pipelining chip enable CE4 depth expansion chip enables CE and CE 21 burst control inputs ADSC ADSP and ADV write enables BW and BWE and global write GW Asynchronous inputs include the output enable OE and the ZZ pin Addresses and chip enables are registered at rising edge of clock when either address strobe processor ADSP or address strobe controller ADSC are active Subsequent burst addresses can be internally generated as controlled by the advance pin ADV Address data inputs and write controls are registered on chip to initiate a self timed write cycle This part supports byte write operations see Pin Configurations on page 3 and Truth Table 4 5 6 7 8 page 9 for further details Write cycles can be one to four bytes wide as controlled by the byte write control inputs GW active LOW causes all bytes to be written This device incorporates an additional pipelined enable register which delays turning off the output buffers an additional cycle when a deselect is executed This feature allows depth expansion without penalizing system performance The CY7C1386D CY7C1387D CY7C1386F CY7C1387F operates from a 3 3V core power supply while all outputs operate with a 3 3V or 2 5V supply All inputs and outputs are JEDEC standard and JESD8 5 compatible 250 MHz 200 MH
27. e mechanism has been provided to simplify the write operations The CY7C1386D CY7C1387D CY7C1386F CY7C1387F is a common device the output enable OE must be deasserted HIGH before presenting data to the DQ inputs Doing so will tri state the output drivers As a safety precaution DQ are automatically tri stated whenever a write cycle is detected regardless of the state of OE Single Write Accesses Initiated by ADSC ADSC write accesses are initiated when the following conditions are satisfied 1 ADSC is asserted LOW 2 ADSP is deasserted HIGH 3 chip select is asserted active and 4 the appropriate combination of the write inputs GW BWE and BW are asserted active to conduct a write to the desired byte s ADSC triggered write accesses require a single clock cycle to complete The address presented is loaded into the address register and the address advancement logic while being delivered to the memory core The ADV input is ignored during this cycle If a global write is conducted the data presented to the DQy is written into the corresponding address location in the memory core If a byte write is conducted only the selected bytes are written Bytes not selected during a byte CY7C1386D CY7C1386F CY7C1387D CY7C1387F Burst Sequences The CY7C1386D CY7C1387D CY7C1386F CY7C1387F provides a two bit wraparound counter fed by that implements either an interleaved or linear burst sequence The
28. ed CY7C1386D CY7C1386F CY7C1387D CY7C1387F ZZ Mode Timing 32 31 CLK T z tZZREC ZZ 2 suppLy Ippzz taza ALL INPUTS DESELECT or READ Only except ZZ Outputs Q Highz Y DON T CARE Notes 31 DQs are in high Z when exiting ZZ sleep mode Document Number 38 05545 Rev E 30 Device must be deselected when entering ZZ sleep mode See cycle descriptions table for all possible signal conditions to deselect the device Page 24 of 30 Feedback h e 2 CYPRESS PERFORM Ordering Information CY7C1386D CY7C1386F CY7C1387D CY7C1387F Not all of the speed package and temperature ranges are available Please contact your local sales representative or visit www cypress com for actual products offered MH Ordering Code Part and Package Type 167 CY7C1386D 167AXC 51 85050 100 pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Pb Free Commercial CY7C1387D 167AXC CY7C1386F 167BGC 51 85115 119 ball Ball Grid Array 14 x 22 x 2 4 mm CY7C1387F 167BGC CY7C1386F 167BGXC 51 85115 119 ball Ball Grid Array 14 x 22 x 2 4 mm Pb Free CY7C1387F 167BGXC CY7C1386D 167BZC 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm CY7C1387D 167BZC CY7C1386D 167BZXC 51 85180 165 ball
29. ed Figure 2 119 Ball BGA 14 x 22 x 2 4 mm 51 85115 51 85115 Page 28 of 30 Document Number 38 05545 Rev E Feedback CY7C1386D CY7C1386F CYPRESS CY7C1387D CY7C1387F PERFORM Package Diagrams continued Figure 3 165 Ball FBGA 13 x 15 x 1 4 mm 51 85180 BOTTOM VIEW PIN1CORNER TOP VIEW 4 19005 1 PIN 1 CORNER 20 25 MEAP 20 50 85x 0 14 1 2 3 4 5 6 7 8 9 10 11 17 10 5 8 7 6 5 4 3 2 1 A 4 e oooo ooood Ma B e O O O O O O 00 B c oOo Dp O O c o D Ov OO OG D E Or Q OG OQ F G O O O O O O O O G o 5 53 H d a J a oO Oo O oO Q Q Q J K O G O O O Q OQ GO O O O K L L 8 M b Q oo O OQ O 00 M N O O O OQ 00000 0 N P p R 9990090000 R A A 1 00 500 10 00 B 13004010 B 13004010 c5 015 4 8 x NOTES M S s 8 5 SOLDER PAD TYPE NON SOLDER MASK DEFINED NSMD S 5 1 S PACKAGE WEIGHT 0 475g q JEDEC REFERENCE MO 216 DESIGN 4 6C J 1 PACKAGE CODE BB0AC SEATING
30. gnal Consecutive single read cycles are supported The CY7C1386D CY7C1387D CY7C1386F CY7C1387F is a double cycle deselect part Once the SRAM is deselected at clock rise by the chip select and either ADSP or ADSC signals its output will tri state immediately after the next clock rise Single Write Accesses Initiated by ADSP This access is initiated when both of the following conditions are satisfied at clock rise 1 ADSP is asserted LOW and 2 chip select is asserted active The address presented is loaded into the address register and the address advancement logic while being delivered to the memory core Page 7 of 30 Feedback CYPRESS PERFORM III The write signals GW BWE BW and ADV inputs are ignored during this first cycle ADSP triggered write accesses require two clock cycles to complete If GW is asserted LOW on the second clock rise the data presented to the DQ inputs is written into the corresponding address location in the memory core If GW is HIGH then the write operation is controlled by BWE and BWy signals The CY7C1386D CY7C1387D CY7C1386F CY7C1387F provides byte write capability that is described in the write cycle description table Asserting the byte write enable input BWE with the selected byte write input will selectively write to only the desired bytes Bytes not selected during a byte write operation will remain unaltered A synchronous self timed writ
31. he setup and hold time requirements of latching data from the boundary scan register 11 Test conditions are specified using the load in TAP AC test conditions tpg tp 1 ns Document Number 38 05545 Rev E Page 13 of 30 CYPRESS PERFORM 3 3V AC Test Conditions Input pulse Vgg to 3 3V Input rise and fall times ins Input timing reference 1 5V Output reference levels 1 5V Test load termination supply voltage 1 5V 3 3V TAP AC Output Load Equivalent CY7C1386D CY7C1386F CY7C1387D CY7C1387F 2 5V TAP AC Test Conditions Input pulse Vgs to 2 5V Input rise and fall time 1ns Input timing reference levels 1 25V Output reference levels 1 25V Test load termination supply voltage 1 25V 2 5V TAP AC Output Load Equivalent 1 5V 1 25V 500 500 109 z 20pF 20 500 20pF TAP DC Electrical Characteristics And Operating Conditions 0 C lt lt 70 C Vpp 3 3V
32. ifted through the instruction register through the TDI and TDO balls To execute the instruction once it is shifted in the TAP controller needs to be moved into the Update IR state EXTEST The EXTEST instruction enables the preloaded data to be driven out through the system output pins This instruction also selects the boundary scan register to be connected for serial access between the TDI and TDO in the Shift DR controller state IDCODE The IDCODE instruction causes a vendor specific 32 bit code to be loaded into the instruction register It also places the instruction register between the TDI and TDO balls and allows Document Number 38 05545 Rev E CY7C1386D CY7C1386F CY7C1387D CY7C1387F the IDCODE to be shifted out of the device when the TAP controller enters the Shift DR state The IDCODE instruction is loaded into the instruction register upon power up or whenever the TAP controller is given a test logic reset state SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO balls when the TAP controller is in a Shift DR state The SAMPLE Z command places all SRAM outputs into a High Z state SAMPLE PRELOAD SAMPLE PRELOAD is a 1149 1 mandatory instruction When the SAMPLE PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture DR state a snapshot of data on the input and output pins is captured in the boundary scan
33. interleaved burst sequence is designed specifically to support Intel Pentium applications The linear burst sequence is designed to support processors that follow a linear burst sequence The burst sequence is user selectable through the MODE input Asserting ADV LOW at clock rise will automatically increment the burst counter to the next address in the burst sequence Both read and write burst operations are supported Sleep Mode The ZZ input pin is an asynchronous input Asserting ZZ places the SRAM in a power conservation sleep mode Two clock cycles are required to enter into or exit from this sleep mode While in this mode data integrity is guaranteed Accesses pending when entering the sleep mode are not considered valid nor is the completion of the operation guaranteed The device must be deselected prior to entering the sleep mode CEs ADSP and ADSC must remain inactive for the duration of tzzggc after the ZZ input returns LOW Interleaved Burst Address Table MODE Floating or VDD First Second Third Fourth Address Address Address Address A1 A1 A1 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 Linear Burst Address Table MODE GND write operation will remain unaltered A synchronous self mus ROGO Peake x un i i i i imoli i ress ress ress ress timed write mechanism has been provided to simplify the write A1 A
34. l Grid Array 13 x 15 x 1 4 mm CY7C1387D 200BZ CY7C1386D 200BZX 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb Free CY7C1387D 200BZXI Document Number 38 05545 Rev E Page 25 of 30 Feedback Ordering Information continued Not all of the speed package and temperature ranges are available Please contact your local sales representative or visit www cypress com for actual products offered CY7C1386D CY7C1386F CY7C1387D CY7C1387F 250 CY7C1386D 250AXC 51 85050 100 pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Pb Free Commercial CY7C1387D 250AXC CY7C1386F 250BGC 51 85115 119 ball Ball Grid Array 14 x 22 x 2 4 mm CY7C1387F 250BGC CY7C1386F 250BGXC 51 85115 119 ball Ball Grid Array 14 x 22 x 2 4 mm Pb Free CY7C1387F 250BGXC CY7C1386D 250BZC 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm CY7C1387D 250BZC CY7C1386D 250BZXC 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb Free CY7C1387D 250BZXC CY7C1386D 250AXI 51 85050 100 pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Pb Free Industrial CY7C1387D 250AXI CY7C1386F 250BGI 51 85115 119 ball Ball Grid Array 14 x 22 x 2 4 mm CY7C1387F 250BGI CY7C1386F 250BGXI 51 85115 119 ball Ball Grid Array 14 x 22 x 2 4 mm Pb Free CY7C1387F 250BGXI CY7C1386D 250BZI 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm
35. nput of any of the registers The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register TDI is internally pulled up and can be unconnected if the TAP is unused in an application TDI is connected to the most signif icant bit MSB of any register See TAP Controller Block Diagram Test Data Out TDO The TDO output ball is used to serially clock data out from the registers The output is active depending upon the current state of the TAP state machine The output changes on the falling edge of TCK TDO is connected to the least significant bit LSB of any register See TAP Controller State Diagram TAP Controller Block Diagram gt 0 Bypass Register gt 2 1 0 Selection nstruction Register TDI Circuitry 3 5 election TDO 313029 2 10 Circuitr y Identification Register xy 1 121110 Boundary Scan Register ttt t t1 141 TAP CONTROLLER TMS Performing a TAP Reset A Reset is performed by forcing TMS HIGH Vpp for five rising edges of TCK This Reset does not affect the operation of the SRAM and may be performed while the SRAM is operating At power up the TAP is reset internally to ensure that TDO comes up in a High Z state TAP Registers Registers are connected between the TDI and TDO balls and allo
36. o the JTAG circuit Sampled on the rising edge of TCK If the JTAG input feature is not used this pin can be disconnected or connected to Vpp This pin is Synchronous not available on TQFP packages TCK JTAG Clock input to the JTAG circuitry If the JTAG feature is not used this pin must Clock be connected to Vss This pin is not available on TQFP packages NC _ No Connects Not internally connected to the die NC 36M 72M These pins not connected They will be used for expansion to the 36M 72M 144M 288M 144M 288M 576M and 1G densities 576M 1G Functional Overview All synchronous inputs pass through input registers controlled by the rising edge of the clock All data outputs pass through output registers controlled by the rising edge of the clock The CY7C1386D CY7C1387D CY7C1386F CY7C1387F supports secondary cache in systems using either a linear or interleaved burst sequence The interleaved burst order supports Pentium and i486 processors The linear burst sequence is suited for processors that use a linear burst sequence The burst order is user selectable and is determined by sampling the MODE input Accesses can be initiated with either the processor address strobe ADSP or the controller address strobe ADSC Address advancement through the burst sequence is controlled by the ADV input A two bit on chip wraparound burst counter captures the first address in a burst sequence and automatically increments
37. pp Vppo DQA DQA N DQPp NC Vppo Vss NC A NC Vss Vppo NC DQPA P NC NC 72M A A TDI A1 TDO A A A A R MODE NC 36M A A TMS AO TCK A A A A CY7C1387D 1M x 18 1 2 3 4 5 6 7 8 9 10 11 288 CE BWg NC BWE ADSC ADV A A 144 CE NC BWA CLK GW OE ADSP A NC 576M C NC NC Wess Vss Vss Vss Vss Vss NOHG DOP D NC Vppo Vpp Vss Vss Vss Vpp Vppo NC DQA E NC DQg Vss Vss Vss Vpp Vppo NC DQA F NC VDD Vss Vss Vss VDD NC DQA G NC DQg Vss Vss Vss Vpp Vppo NC DQA H NC NC NC Vip Vss Vss Vss Von NC NC 77 J NC Vss Vss Vss Vpp Vppo DQA NC K DQg NC Vpp Vss Vss Vss Vpp DQA NC L NC Vppo Vpp Vss Vss Vss Vpp Vppo DQA NC M NC VDDQ VDD Vss Vss Vss VDD VDDQ DQA NC N DQPg NC Vppo Vss NC A NC Vss Vppo NC NC P NC NC 72M A A TDI A1 TDO A A A A R MODE NC 36M A A TMS AO TCK A A A A Document Number 38 05545 Rev E Page 5 of 30 Feedback CY7C1386D CY7C1386F CY7C1387D CY7C1387F Document Number Name IO Description Ao A4 Input Address inputs used to select one of the address locations Sampled at the Synchronous rising edge of the CLK if ADSP or ADSC is active LOW and CE4 CE and CE are sampled active A1 AO are fed to the two bit counter BWA BWg Input Byte write select inputs active LOW Qualified with BWE
38. put active LOW Controls the direction of the Asynchronous IO pins When LOW the IO pins behave as outputs When deasserted HIGH DQ pins are tri stated and act as input data pins OE is masked during the first clock of a read cycle when emerging from a deselected state ADV Input Advance input signal sampled on the rising edge of CLK active LOW When Synchronous asserted it automatically increments the address in a burst cycle ADSP Input Address strobe from processor sampled on the rising edge of CLK active Synchronous LOW When asserted LOW addresses presented to the device are captured in the address registers A1 AO are also loaded into the burst counter When ADSP and ADSC are both asserted only ADSP is recognized ASDP is ignored when CE is deasserted HIGH ADSC Input Address strobe from controller sampled on the rising edge of CLK active Synchronous LOW When asserted LOW addresses presented to the device are captured in the address registers A1 AO are also loaded into the burst counter When ADSP and ADSC are both asserted only ADSP is recognized ZZ Input ZZ sleep input active HIGH When asserted HIGH places the device in a non time Asynchronous critical sleep condition with data integrity preserved For normal operation this pin has to be LOW ZZ pin has an internal pull down DQs DQPx Bidirectional data IO lines As inputs they feed into an on chip data register that Synchronous is triggered by the rising edge of
39. register is loaded with the contents of the RAM input and output ring when the TAP controller is in the Capture DR state and is then placed between the TDI and TDO balls when the controller is moved to the Shift DR state The EXTEST SAMPLE PRELOAD and SAMPLE Z instructions can be used to capture the contents of the input and output ring The boundary scan order tables show the order in which the bits are connected Each bit corresponds to one of the bumps on the SRAM package The MSB of the register is connected to TDI and the LSB is connected to TDO Identification ID Register The ID register is loaded with a vendor specific 32 bit code during the Capture DR state when the IDCODE command is loaded in the instruction register The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift DR state The ID register has a vendor code and other information described in the Identification Register Definitions on page 15 TAP Instruction Set Overview Eight different instructions are possible with the three bit instruction register All combinations are listed in Identification Codes on page 15 Three of these instructions are listed as RESERVED and must not be used The other five instructions are described in detail below Instructions are loaded into the TAP controller during the Shift IR state when the instruction register is placed between TDI and During this state instructions are sh
40. sampled with the clock 7 SRAM always initiates a read cycle when ADSP is asserted regardless of the state of GW BWE or BW x Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC As a result OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri state OE is a don t care for the remainder of the write cycle 8 OEis asynchronous and is not sampled with the clock rise It is masked internally during write cycles During a read cycle all data bits are tri state when OE is inactive or when the device is deselected and all data bits behave as output when OE is active LOW Document Number 38 05545 Rev E Page 9 of 30 Feedback CYPRESS j PERFORM Truth Table for Read Write 5 91 CY7C1386D CY7C1386F CY7C1387D CY7C1387F Function CY7C1386D CY7C1386F m Write Byte A DQ and Write Byte B DQg and Write Bytes B A Write Byte C DQc and DQPc Write Bytes C A Write Bytes C B Write Bytes C B A Write Byte D DQp and DQPp Write Bytes D A Write Bytes D B Write Bytes D B A Write Bytes D C Write Bytes D C A Write Bytes D C B Write All Bytes Write All Bytes 31e 3 mi ml a a mun mel mimi si x r r r Zx lt Ww
41. t clocking of the device TDI and TMS are internally pulled up and may be unconnected They may alternately be connected to Vpp through a pull up resistor TDO can be left unconnected Upon power up the device will come up in a reset state which will not interfere with the operation of the device TAP Controller State Diagram TEST LOGIC i RESET 0 Y q RUN TEST IDLE 4 4 SELECT 1 IR SCAN SELECT DR SCAN 0 0 Y Y CAPTURE DR CAPTURE IR EXIT2 IR 1 1 Y Y UPDATE DR UPDATE IR 2 1 0 1 0 1 next to each state represents the value of TMS at the rising edge of TCK Test Access Port TAP Test Clock TCK The test clock is used only with the TAP controller All inputs are captured on the rising edge of TCK All outputs are driven from the falling edge of TCK Test Mode Select TMS The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK This pin may be left unconnected if the TAP is not used The ball is pulled up internally resulting in a logic HIGH level Document Number 38 05545 Rev E CY7C1386D CY7C1386F CY7C1387D CY7C1387F Test Data In TDI The TDI ball is used to serially input information into the registers and can be connected to the i
42. te Sleep Mode Power Down None X X X H X X X X X X Tri State Read Cycle Begin Burst External L H L L L x x X L L H Q Read Cycle Begin Burst External L H L L L X X X H L H Tri State Write Cycle Begin Burst External L H L L H L X L X L H D Read Cycle Begin Burst External L H L L H L x H L L H Q Read Cycle Begin Burst External L H L L H L X H H L H Tri State Read Cycle Continue Burst Next X X X L H H L H L L H Q Read Cycle Continue Burst Next X X X L H H L H H L H Tri State Read Cycle Continue Burst Next H X X L X H L H L L H Q Read Cycle Continue Burst Next H X X L X H L H H L H Tri State Write Cycle Continue Burst Next X X X L H H L L X L H D Write Cycle Continue Burst Next H X X L X H L L X L H D Read Cycle Suspend Burst Current X X X L H H H H L L H Q Read Cycle Suspend Burst Current X X X L H H H H H L H Tri State Read Cycle Suspend Burst Current H x x L x H H H L L H Q Read Cycle Suspend Burst Current H X X L X H H H H L H Tri State Write Cycle Suspend Burst Current X X X L H H H L X L H D Write Cycle Suspend Burst Current H X X L X H H L X L H D Notes 4 X Don t Care H Logic HIGH L Logic LOW 5 WRITE L when any one or more byte write enable signals and BWE L or GW L WRITE H when all byte write enable signals BWE GW H 6 The DQ pins are controlled by the current cycle and the OE signal OE is asynchronous and is not
43. the address for the rest of the burst access Byte write operations are qualified with the byte write enable BWE and byte write select BW x inputs A global write enable GW overrides all byte write inputs and writes data to all four bytes All writes are simplified with on chip synchronous self timed write circuitry Synchronous chip selects l and an asynchronous output enable OE provide for easy bank selection and output tri state control ADSP is ignored if CE is HIGH Document Number 38 05545 Rev E Single Read Accesses This access is initiated when the following conditions are satisfied at clock rise 1 ADSP or ADSC is asserted LOW 2 chip selects are all asserted active and 3 the write signals GW BWE are all deasserted HIGH ADSP is ignored if CE is HIGH The address presented to the address inputs is stored into the address advancement logic and the address register while being presented to the memory core The corresponding data is allowed to propagate to the input of the output registers At the rising edge of the next clock the data is allowed to propagate through the output register and onto the data bus within tco if OE is active LOW The only exception occurs when the SRAM is emerging from a deselected state to a selected state its outputs are always tri stated during the first cycle of the access After the first cycle of the access the outputs are controlled by the OE si
44. tion of SRAM vendor ID Register Presence Indicator 0 1 1 Indicates the presence of an ID register Scan Register Sizes Register Name Bit Size x18 Bit Size x36 Instruction 3 3 Bypass 1 1 ID 32 32 Boundary Scan Order 119 ball BGA package 85 85 Boundary Scan Order 165 ball FBGA package 89 89 Identification Codes Instruction Code Description EXTEST 000 Captures IO ring contents Places the boundary scan register between TDI and TDO Forces all SRAM outputs to High Z state IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO This operation does not affect SRAM operations SAMPLE Z 010 Captures IO ring contents Places the boundary scan register between TDI and TDO Forces all SRAM output drivers to a High Z state RESERVED 011 Do Not Use This instruction is reserved for future use SAMPLE PRELOA 100 Captures IO ring contents Places the boundary scan register between TDI and TDO D Does not affect SRAM operation RESERVED 101 Do Not Use This instruction is reserved for future use RESERVED 110 Do Not Use This instruction is reserved for future use BYPASS 111 Places the bypass register between TDI and TDO This operation does not affect SRAM operations Note 13 Bit 24 is 1 in the register definitions for both 2 5V and 3 3V versions of this device Document Number 38 05545 Rev E Page 15 of 30 Feedback PERFORM 119 Ball BGA Boundary Scan Order 17 151 CY
45. to conduct byte writes BWc BWp Synchronous to the SRAM Sampled on the rising edge of CLK GW Input Global write enable input active LOW When asserted LOW on the rising edge Synchronous of CLK a global write is conducted all bytes are written regardless of the values on BW BWE BWE Input Byte write enable input active LOW Sampled on the rising edge of CLK This Synchronous signal must be asserted LOW to conduct a byte write CLK Input Clock input Used to capture all synchronous inputs to the device Also used to Clock increment the burst counter when ADV is asserted LOW during a burst operation CE Input Chip enable 1 input active LOW Sampled on the rising edge of CLK Used in Synchronous conjunction with and to select or deselect the device ADSP is ignored if CE is HIGH CE is sampled only when a new external address is loaded CE 2 Input Chip enable 2 input active HIGH Sampled on the rising edge of CLK Used in Synchronous conjunction with CE and CE to select or deselect the device CE is sampled only when a new external address is loaded CE3 2 Input Chip enable 3 input active LOW Sampled on the rising edge of CLK Used in Synchronous conjunction with CE and CE to select or deselect the device Not connected for BGA Where referenced CE3 2 is assumed active throughout this document for BGA CE is sampled only when new external address is loaded OE Input Output enable asynchronous in
46. w data to be scanned into and out of the SRAM test circuitry Only one register can be selected at a time through the instruction register Data is serially loaded into the TDI ball on the rising edge of TCK Data is output on the TDO ball on the falling edge of TCK Instruction Register Three bit instructions can be serially loaded into the instruction register This register is loaded when it is placed between the TDI and TDO balls as shown in the TAP Controller Block Diagram Upon power up the instruction register is loaded with the IDCODE instruction It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section Page 11 of 30 Feedback CYPRESS PERFORM III QQ When the TAP controller is in the Capture IR state the two least significant bits are loaded with a binary 01 pattern to allow for fault isolation of the board level serial test data path Bypass Register To save time when serially shifting data through registers it is sometimes advantageous to skip certain chips The bypass register is a single bit register that can be placed between the TDI and TDO balls This allows data to be shifted through the SRAM with minimal delay The bypass register is set LOW Vss when the BYPASS instruction is executed Boundary Scan Register The boundary scan register is connected to all the input and bidirectional balls on the SRAM The boundary scan
47. z 167 MHz Unit Maximum Access Time 2 6 3 0 3 4 ns Maximum Operating Current 350 300 275 mA Maximum CMOS Standby Current 70 70 70 mA Notes 1 For best practices or recommendations please refer to the Cypress application note AN1064 SRAM System Design Guidelines on www cypress com 2 CE3 and CE are for TQFP and 165 FBGA packages only 119 BGA is offered only in Single Chip Enable San Jose CA 95134 1709 408 943 2600 Revised Feburary 09 2007 Cypress Semiconductor Corporation Document Number 38 05545 Rev E 198 Champion Court Feedback Logic Block Diagram CY7C1386D CY7C1386F 512K x 36 CY7C1386D CY7C1386F CY7C1387D CY7C1387F ADDRESS MODE REGISTER ADSP JY DQ 01 COUNTER AND LOGIC 00 rey H
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