Cypress CY7C1380C User's Manual
Contents
1. ADDRESS A0 A1 A gt REGISTER A 2 pon MODE ADV BURST Q1 COUNTER AND LOGIC CR Q0 ADS um Lf N RES gt B WRITE REGISTER A gt OUTPUT DQs N MEMORY SNS b OUTPUT BUFFERS DQPa q ARRAY AMPS REGISTERS DOP b DQADQP 2 2 DQADQPA N WWE im 4 i BWA WRITE REGISTER gt BWE D Ee hs ow ENABLE Qi REGISTER 9 PIPELINED CE2 H ENABLE P OE e z CONTROL Document 38 05237 Rev D Page 2 of 36 Feedback CYPRESS 100 pin TQFP Pinout UUUUUUUDUUUUUHULULUUDUUUIUDUUUUUUUU Pin Configurations O 212120 8 lt lt lo Oimmimmio gt gt lt lt lt xt CGN O O C QO LO x QN O O5 O O O CO OO CO cO DQPcL 1 80 DQc Co 2 79 DQ 3 78 4 77 Vsso H 5 76 DQc 6 75 L j 7 74 poc C 73 L j 9 72 Vsso2. CY7C1382C Ordering Information Speed Package Operating MHz Ordering Code Name Part and Package Type Range 250 CY7C1380C 250AG A101 100 lead Thin Quad Flat Pack 14 x 20 x 1 4mm Commercial CY7C1382C 250AG CY7C1380C 250BGG BG119 119 PBGA CY7C1382C 250BGC CY7C1380C 250BZC 165 165 fBGA CY7C1382C 250BZC 225 CY7C1380C 225AC A101 100 lead Thin Quad Flat Pack 14 x 20 x 1 4mm CY7C1382C 225AC CY7C1380C 225BGC BG119 119 PBGA CY7C1382C 225BGC CY7C1380C 225BZC 165 165 fBGA CY7C1382C 225BZC 200 CY7C1380C 200AC A101 100 lead Thin Quad Flat Pack 14 x 20 x 1 4mm CY7C1382C 200AC CY7C1380C 200BGC BG119 119 CY7C1382C 200BGC CY7C1380C 200BZC BB165A 165 fBGA CY7C1382C 200BZC 167 CY7C1380C 167AC A101 100 lead Thin Quad Flat Pack 14 x 20 x 1 4mm CY7C1382C 167AC CY7C1380C 167BGC BG119 119 PBGA CY7C1382C 167BGC CY7C1380C 167BZC BB165A 165 fBGA CY7C1382C 167BZG 133 CY7C1380C 133AC A101 100 lead Thin Quad Flat Pack 14 x 20 x 1 4mm 167 CY7C1380C 167AI A101 100 lead Thin Quad Flat Pack 14 x 20 x 1 4mm Industrial CY7C1382C 167Al CY7C1380C 167BGI BG119 119 PBGA CY7C1382C 167BGI CY7C1380C 167BZI BB165A 1651 Shaded areas contain advance information CY7C1382C 167BZI Please contact your local sales representative for availability of these parts Document 38 05237 Rev D Page 32 of 36 Feedback CY7C1380C CY7C1382C we CYPRESS
3. R NC MODE Vpop NC A NC T NC NC 72M A A A NC 36M ZZ U Vppo TMS TDI TCK TDO NC Vppo CY7C1382C 512K x 18 1 2 3 4 5 6 7 A A A ADSP A A B NC A A ADSG A A NC C NC A A VpD A A NC D DQ NC Wee NC Vss NC E NC DQg Vss CE Vss NC DQA F Vppo NC Vss OE Vss DQA VDDQ G NC ADV Vss NC DQA H DQ NC Vss GW Vsg DQ NC J Vppo Vpp NC Vpp NC Vpp VDDQ K NC Vss CLK Vss NC L NC Vss NC BWA DQA NC M Vss BWE Vss NC Vppo N DQg NC Vss A1 Vss DOR NC P NC DGP amp Vss A0 Vss NC DQA R NC A MODE Vep NC A NC T NC 72M A A NC 36M A A ZZ Voo TMS TDI TCK TDO NC Vooo Document 38 05237 Rev D CY7C1380C CY7C1382C Page 4 of 36 Feedback CY7C1380C CY7C1382C CYPRESS Pin Configurations continued 165 ball fBGA CY7C1380C 512K x 36 1 2 3 4 5 6 7 8 9 10 11 NC 288M CE BWc BWg CE BWE ADSC ADV A NC B NC A BWp BWA CLK GW OE ADSP A NC 144M C DQPc NC Vss Vss Vss Vss Vss Vppo NC DQPg D DQc DQc Vpp Vss Vss Vss Vpp DQg E Vpp Vss Vss Vss Vpp Vppa DQg F DQc DQc Vppo Vpp Vss Vss Vss VDD G DQc DQc Vppa Vp
4. S37 rss 165 Ball fBGA Boundary Scan Order CY7C1380C 512K x 36 BIT BALL ID BIT BALL ID 1 B6 37 N6 2 B7 38 R6 3 A7 39 P6 4 B8 40 R4 5 A8 41 R3 6 B9 42 P4 7 A9 43 P3 8 B10 44 R1 9 A10 45 N1 10 C11 46 L2 11 E10 47 K2 12 F10 48 J2 13 G10 49 M2 14 D10 50 M1 15 D11 51 L1 16 E11 52 K1 17 F11 53 J1 18 G11 54 Internal 19 H11 55 G2 20 J10 56 F2 21 K10 57 E2 22 L10 58 D2 23 M10 59 G1 24 J11 60 F1 25 K11 61 E1 26 L11 62 D1 27 M11 63 C1 28 11 64 2 29 R11 65 B2 30 R10 66 A3 31 R9 67 B3 32 R8 68 B4 33 P10 69 A4 34 P9 70 A5 35 P8 71 B5 36 P11 72 A6 Document 38 05237 Rev D CY7C1380C CY7C1382C Page 22 of 36 Feedback CY7C1380C CY7C1382C CYPRESS 165 Ball fBGA Boundary Scan Order CY7C1382C 1M x 18 BIT BALL ID BIT BALL ID 0 B6 36 N6 1 B7 37 R6 2 A7 38 P6 3 B8 39 R4 4 A8 40 R3 5 B9 41 P4 6 A9 42 P3 7 B10 43 R1 8 A10 44 Not Bonded Preset to 0 9 A11 45 Not Bonded Preset to 0 10 Not Bonded Preset to 0 46 Not Bonded Preset to 0 11 Not Bonded Preset to 0 47 Not Bonded Preset to 0 12 Not Bonded Preset to 0 48 N1 13 C11 49 M1 14 D11 50 L1 15 E11 51 K1 16 F11 52 J1 17 G11 53 Internal 18 H11 54 G2 19 J10 55 F2 20 K10 56 E2 21 L10 57 D2 22 M10 58 Not Bonded Preset to 0 23 Not Bonded Preset to 0 59 No
5. CY7C1380C CY7C1382C CYPRESS CY7C1382C Pin Definitions continued Name TQFP BGA fBGA Description Vppo 4 11 20 27 54 A1 A7 F1 F7 C3 C9 D3 D9 l O Power Sup Power supply for the I O circuitry 61 70 J1 J7 M1 M7 E3 E9 ply 77 U1 U7 F3 F9 G3 G9 J3 J9 K3 K9 L3 L9 M3 M9 N3 N9 MODE 31 R3 R1 Input Selects Burst Order When tied to GND selects Static linear burst sequence When tied to Vpp or left floating selects interleaved burst sequence This is a strap pin and should remain static during device operation Mode Pin has an internal pull up TDO U5 P7 JTAG serial Serial data out to the JTAG circuit Delivers data output on the negative edge of TCK If the JTAG feature is Synchronous not being utilized this pin should be left uncon nected This pin is not available on TQFP packages TDI U3 P5 JTAG serial Serial data In to the JTAG circuit Sampled on the input rising edge of TCK If the JTAG feature is not being Synchronous utilized this pin can be left floating or connected to Vpp through a pull up resistor This pin is not avail able on TQFP packages TMS U2 R5 JTAG serial Serial data In to the JTAG circuit Sampled on the input rising edge of TCK If the JTAG feature is not being Synchronous utilized this pin can be disconnected or connected to Vpp This pin is not available on TQFP packages TCK U4 R7 JTAG Clock Clock input to the JTAG circuitry If the JTAG feature is
6. 9 72 10 71 FE 11 70 Vppa 12 69 13 68 14 67 F3 v 15 CY7C1382C 66 NC 16 65 FE Vpp dz 1M x 18 64 E 22 18 63 DQa 19 62 20 61 21 60 Vsso 22 59 23 58 24 57 NC 25 56 E NC 26 55 27 54 Vppa 28 53 NC 29 52 NC m 30 51 NC CO lt LO XO OO O O LO F OQO CO CO CO CO CO CO CO CO t s s b s b b s s ob lt lt lt lt ENS 8 lt lt lt lt lt lt lt lt ue 3 of 36 Feedback Z Z CYPRESS Pin Configurations continued 119 ball BGA 1 Chip Enable with JTAG CY7C1380C 512K x 36 1 2 3 4 5 6 7 ADSP A A Vppo B NC A A ADSC A A NC C NC A A VoD A A NC D DQPe Vss NC Vss E DQc Vss CE Vss DQg DQg F Vppo DQc Vss OE Vss Vppo G DQc BWc ADV BWg DQg DQg H oe DQc Vss GW Vss Dds J Vppo Vpp NC Vpp NC Vpp Vppo K DQ Veg CLK Vss DQA L DQp DQp BWp NC BWA DQA DQA M Vppo DQp Vss BWE Vss DQA Vppo DQ 04 Vss A1 Vss DQ DQA P 005 DQPp Vss A0 Vss
7. Package Diagrams 100 Pin Thin Plastic Quad Flatpack 14 x 20 1 4 mm A101 DIMENSIONS ARE IN MILLIMETERS 16004020 14000 10 1 40 0 05 100 81 7 HHHRHHHHHHHdHHHHBHHH ue Teo E E E 0 30 0 08 22 00 0 20 20 00 0 10 HRHRRHRRRRRRRRRRRRRRRRHRHRRHRR ES 0 65 ES TYP SEE DETAIL A ES ad 1 30 o 51 3 HHHHHHHUHBHHHHHHUHHHH 31 50 0 20 MAX R0 08 MIN 0 20 N 0 MIN 1 60 MAX b fo NS STAND OFF Ei e 0 05 MIN 0 25 SEATING PLANE 0 15 GAUGE PLANE J NA 1 O N i R 0 08 MIN 0 7 0 20 0 60 0 15 0 20 MIN ae 51 85050 DETAIL Document 38 05237 Rev D Page 33 of 36 Cypress Semiconductor Corporation 2004 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product Nor does it convey or imply any license under patent or other rights Cypress Semiconductor does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress Semiconductor products in life support systems appl
8. Q Q A1 MA QAO Q A2 1 X Q A2 42 Xon n XX QUA2 A oen ico L to its initial state 21 this diagram when CE is LOW CE is LOW CE is HIGH and CEg is LOW When CE is HIGH CE is HIGH or is LOW or is HIGH 22 Full width write can be initiated by either GW LOW or by GW HIGH BWE LOW BWy LOW Page 28 of 36 Feedback CY7C1380C CY7C1382C Ea 2 CYPRESS Switching Waveforms continued Write Cycle Timingl 221 Se et tf eee taps ADH w RR C ADSC extei ndsburi 7 UL ZA BZA V V Z CDL V BZ SZC T 77770 Dh PE PE v uo ZZ s Byte write signa 8 eo ode when es bur 27 ZZ EL WEH 7 zz zz www wu dum DNE z ura gn Z BAV ADV ADV suspends bur zam OE 051 DH High Z iz D A1 D A2 Ly D A2 es os on D A3 Won on 2X Data In D a Extended BURST WRITE Data Out Q BURST WRITE 22 BURST READ EN Single WRITE l DON T CARE RY UNDEFINED Page 29 of 36 Document 38 05237 Rev D Feedback F CYPRESS Switching Waveforms continued Read Write Cycle Timing CY7C1380C CY7C1382C 21 23 24 JUL EPIS lt
9. 33 C2 69 G3 34 A2 70 G5 35 T4 71 L5 36 B6 72 Internal Document 38 05237 Rev D Page 20 of 36 Feedback ae Zz CYPRESS 119 Ball BGA Boundary Scan Order CY7C1380C CY7C1382C CY7C1382C 1M x 18 BIT BALL ID BIT BALL ID 1 K4 37 B2 2 H4 38 P4 3 M4 39 N4 4 F4 40 R6 5 B4 41 T5 6 A4 42 T3 7 G4 43 R2 8 C6 44 R3 9 A6 45 Not Bonded Preset to 0 10 T6 46 Not Bonded Preset to 0 11 Not Bonded Preset to 0 47 Not Bonded Preset to 0 12 Not Bonded Preset to 0 48 Not Bonded Preset to 0 13 Not Bonded Preset to 0 49 P2 14 D6 50 N1 15 E7 51 M2 16 F6 52 L1 17 G7 53 K2 18 H6 54 Not Bonded Preset to 1 19 T7 55 H1 20 K7 56 G2 21 L6 57 E2 22 N6 58 D1 23 P7 59 Not Bonded Preset to 0 24 Not Bonded Preset to 0 60 Not Bonded Preset to 0 25 Not Bonded Preset to 0 61 Not Bonded Preset to 0 26 Not Bonded Preset to 0 62 Not Bonded Preset to 0 27 Not Bonded Preset to 0 63 Not Bonded Preset to 0 28 Not Bonded Preset to 0 64 A5 29 B5 65 A3 30 B3 66 E4 31 C5 67 Internal 32 C3 68 Not Bonded Preset to 0 33 C2 69 Internal 34 A2 70 G3 35 T2 71 L5 36 B6 72 Internal Document 38 05237 Rev D Page 21 of 36 Feedback
10. R3 R4 R8 R9 99 100 B5 C5 R10 T5 A6 R11 B6 C6 R6 T6 BWABWg 93 94 G3 L5 B5 A4 Input Byte Write Select Inputs active LOW Qualified Synchronous with BWE to conduct byte writes to the SRAM Sampled on the rising edge of GW 88 H4 B7 Input Global Write Enable Input active LOW When Synchronous asserted LOW on the rising edge of CLK a global write is conducted ALL bytes are written regardless of the values on BWy and BWE BWE 87 M4 A7 Input Byte Write Enable Input active LOW Sampled Synchronous the rising edge of CLK This signal must be asserted LOW to conduct a byte write CLK 89 K4 B6 Input Clock Input Used to capture all synchronous Clock inputs to the device Also used to increment the burst counter when ADV is asserted LOW during a burst operation CE 98 E4 A3 Input Chip Enable 1 Input active LOW Sampled on the L Synchronous rising edge of CLK Used in conjunction with CE and CE to select deselect the device ADSP is ignored if CE is HIGH CEPI 97 B3 Input Chip Enable 2 Input active HIGH Sampled on Synchronous the rising edge of CLK Used in conjunction with CE and to select deselect the device CE 2 92 A6 Input Chip Enable 3 Input active LOW Sampled on the Synchronous rising edge of CLK Used in conjunction with CE and CE to select deselectthe device Not available for AJ package version Not connected for BGA Where referenced is assumed active throughout this document
11. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board Reserved These instructions are not implemented but are reserved for future use Do not use these instructions TAP Timing 1 2 3 4 5 6 Test Clock y i trMSs TMS tTDIS I IH O WQ UC XQ TDI j i DON T RY UNDEFINED TAP AC Switching Characteristics Over the operating Rangel 10 Parameter Symbol Min Max Units Clock TCK Clock Cycle Time trcvc 100 ns TCK Clock Frequency tre 10 MHz TCK Clock HIGH time tty 40 ns TCK Clock LOW time tn 40 ns Output Times TCK Clock LOW to TDO Valid trpov 20 ns TCK Clock LOW to TDO Invalid ttpox 0 ns Setup Times TMS Set Up to TCK Clock Rise truss 10 ns TDI Set Up to TCK Clock Rise trpis 10 ns Capture Set Up to TCK Rise tcs 10 Hold Times TMS hold after TCK Clock Rise 10 ns TDI Hold after Clock Rise 10 ns Capture Hold after Clock Rise tcH 10 ns Notes 9 CS and CH refer to the setup and hold time requirements of latching data from the boundary scan register 10 Test conditions are specified using the load in AC test Conditions tp te 1ns Document 38 05237 Rev D Page 17 of 36 Feedback C
12. Vin Input HIGH Voltage Vppo 3 3V 2 0 Vpp 0 3 V Vppo 2 5V 1 7 Vpp 0 3 V ViL Input LOW Voltage Vppo 3 3V 0 3 0 8 V Vppo 2 5V 0 3 0 7 V lx Input Load Current GND lt Vin lt Vppo 5 5 Note 11 All voltages referenced to Vss GND Document 38 05237 Rev D Page 18 of 36 Identification Register Definitions CY7C1380C CY7C1382C CY7C1380C CY7C1382C DESCRIPTION INSTRUCTION FIELD 512KX36 1MX18 Revision Number 31 29 010 0100 Describes the version number Device Depth 28 24 01010 1010 Reserved for Internal Use Device Width 23 18 000000 000000 Defines memory type and architecture Cypress Device ID 17 12 100101 010101 Defines width and density Cypress JEDEC ID Code 11 1 00000110100 00000110100 Allows unique identification of SRAM vendor ID Register Presence Indicator 0 1 1 Indicates the presence of an ID register Scan Register Sizes REGISTER NAME BIT SIZE X36 BIT SIZE X18 Instruction 3 3 Bypass 1 1 ID 32 32 Boundary Scan Order 72 72 Identification Codes INSTRUCTION CODE DESCRIPTION EXTEST 000 Captures ring contents Places the boundary scan register between TDI and Forces all SRAM outputs to High Z state This instruction is not 1149 1 compliant IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO This operation does not
13. 10 71 11 70 C 12 69 poc 13 68 Nc 5 44 67 NC te CY7C1380C S Vss 17 512K X 36 64 18 63 Dao 19 62 20 61 Vssa 21 60 DAD C 25 59 23 58 DaD L 24 57 Da 56 Vsso 26 55 27 54 DQD 28 53 2 29 52 DQPDL 30 51 CN CO t LO XO O t LO CO OQO CO CO CO CO CO CO CO CO s sb b xb ob O40 lt lt lt lt lt lt lt lt lt lt lt lt lt lt gt gt NC 72M NC 36M Document 38 05237 Rev D DQPB DQB DQB Vsso DQB DQB DQB DQB Vssa Vppa DQB DQB Vss NC ZZ DQA DQA Vsso DQA DQA DQA DQA Vsso DQPA NC NC NC Vppo Vsso NC NC Vsso DQB NC NC Vss DQB DQB Vsso DQB DQB DQPB NC Vsso NC NC NC CY7C1380C CY7C1382C a m lt o o wx gt gt 452 lt iO O Z zimimio gt lt lt lt lt lt O O O5 O O5 O O CO CO 1 80 MIA 2 79 NC 3 78 NC 4 7 ES Voa 5 76 1 Vssa C4 6 75 E3 NC 7 74 DQPA 8 73
14. 6 17 18 1 0 1 0 1 3 1 3 1 3 ns lcHz Clock to High ZL 9 17 18 2 6 2 8 3 0 3 4 3 4 ns loEv OE LOW to Output Valid 2 6 2 8 3 0 3 4 4 2 ns loELZ OE LOW to Output Low ZI 6 17 18 0 0 0 0 0 ns OE HIGH to Output 218 17 18 2 6 2 8 3 0 3 4 4 0 ns Setup Times tas Address Set up Before CLK Rise 1 2 1 4 1 4 1 5 1 5 ns taps ADSC ADSP Set up Before CLK 1 2 1 4 1 4 1 5 1 5 ns ss j tADVS ADV Set up Before CLK Rise 1 2 1 4 1 4 1 5 1 5 ns twes GW BWE BW Set up Before CLK 1 2 1 4 1 4 1 5 1 5 ns ise tps Data Input Set up Before CLK Rise 1 2 1 4 1 4 1 5 1 5 ns tcEs Chip Enable Set Up Before CLK Rise 1 2 1 4 1 4 1 5 1 5 ns Hold Times Address Hold After CLK Rise 0 3 0 4 0 4 0 5 0 5 ns tADH ADSP ADSC Hold After CLK Rise 0 3 0 4 0 4 0 5 0 5 ns ADV Hold After Rise 0 3 0 4 0 4 0 5 0 5 ns tWeH GW BWE BWy Hold After CLK Rise 0 3 0 4 0 4 0 5 0 5 ns toy Data Input Hold After CLK Rise 0 3 0 4 0 4 0 5 0 5 ns Chip Enable Hold After CLK Rise 0 3 0 4 0 4 0 5 0 5 ns Shaded areas contain advance information Notes 15 part has voltage regulator internally tpower is the time that the power needs to be supplied above Vpp minimum initially before a read or write operation can be initiated 16 tonz tcr z togr 7 and toguz are specified with AC test conditions shown in part b of AC Test Loads Transition is measured 200 mV from steady state voltage 17 At any give
15. Bytes z z z z z z z xX r ririrmirmirrirrirri rir rir rs Uu 1 5 Uu x zz x zz z lt 2 0 x rle ziz lz z zx 2 0 x z i zi 2 Truth Table for Read Write Function CY7C1382C m gt Read Read Write Byte A DQ and DQP4 Write Byte B DQg and DQPg Write Bytes B A Write All Bytes Write All Bytes z z gt lt r r I cy cls Uu x ziz x 2 0 111 x 2 Document 38 05237 Rev D Page 14 of 36 Feedback La XE CYPRESS IEEE 1149 1 Serial Boundary Scan JTAG The CY7C1380C incorporates a serial boundary scan test access port TAP This port operates in accordance with IEEE Standard 1149 1 1990 but does not have the set of functions required for full 1149 1 compliance These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM Note that the TAP controller functions in a manner that does not conflict with the operation of other devices using 1149 1 fully compliant TAPs The operates using JEDEC standard 3 3V or 2 5V I O logic levels The CY7C1380C contains a TAP controller instruction register boundary scan register bypass register and ID register Disabling the JTAG Feature
16. H Tri State WRITE Cycle Begin Burst External L H L L H L X L X L H D READ Cycle Begin Burst External L H L L H L X H L L H Q READ Cycle Begin Burst External L H L L H L X H H Tri State READ Cycle Continue Burst Next X X X L H H L H L L H Q READ Cycle Continue Burst Next X X X L H H L H H Tri State READ Cycle Continue Burst Next H X X L X H L H L L H Q Document 38 05237 Rev D Page 13 of 36 Feedback CY7C1380C y o CY7C1382C Truth Tablel 4 5 6 7 8 Operation Add Used CE ZZ ADSP ADSC ADV WRITE OE DQ READ Cycle Continue Burst Next H X X L X H L H H Tri State WRITE Cycle Continue Burst Next X X X L H H L L X L H D WRITE Cycle Continue Burst Next H X X L X H L L X L H D READ Cycle Suspend Burst Current X X X L H H H H L L H Q READ Cycle Suspend Burst Current X X X L H H H H H L H Tri State READ Cycle Suspend Burst Current H X X L X H H H L L H Q READ Cycle Suspend Burst Current H X X L X H H H H L H Tri State WRITE Cycle Suspend Burst Current X X X L H H H L X L H D WRITE Cycle Suspend Burst Current H X X L X H H L X L H D Notes 3 X Don t Care H Logic HIGH L Logic LOW EDO EJ 4 WRITE L when any one or more Byte Write enable signals and BWE L or GW L WRITE H when all Byt
17. f 1 MHz 5 8 9 pF Vpp 3 3V Clock Input Capacitance vopo 2 5V 5 8 9 Cyo Input Output Capacitance 5 8 9 pF Notes 14 Tested initially and after any design or process change that may affect these parameters Document 38 05237 Rev D Page 25 of 36 Feedback C Te gt 3 OUTPUT Z CYPRESS st Loads and Waveforms R 3170 Test Load 3 3V OUTPUT RL 500 5pF 1 5V INCLUDING JIG AND scope 0 2 5V I O Test Load 2 5V OUTPUT OUTPUT JIG AND SCOPE a Document 38 05237 Rev D R_ 500 5pF L 1 25 INCLUDING 3510 R 16670 215380 5 CY7C1380C CY7C1382C ALL INPUT PULSES Page 26 of 36 Feedback CY7C1380C CY7C1382C F CYPRESS Switching Characteristics Over the Operating Rangel 9 20 250 MHz 225 MHz 200 MHz 167 MHz 133 MHz Parameter Description Min Max Min Max Min Max Unit tPowER Vpp Typical to the first Access 1 1 1 1 1 ms Clock tcyc Clock Cycle Time 4 0 4 4 5 6 7 5 ns icu Clock HIGH 1 7 2 0 2 0 2 2 2 5 ns teL Clock LOW 1 7 2 0 2 0 2 2 2 5 ns Output Times tco Data Output Valid After CLK Rise 2 6 2 8 3 0 3 4 4 2 ns tpoH Data Output Hold After CLK Rise 1 0 1 0 1 3 1 3 1 3 ns tcLz Clock to Low zl
18. for BGA 86 F4 B8 Input Output Enable asynchronous input active Asynchronous LOW Controls the direction of the I O pins When LOW the I O pins behave as outputs When deasserted HIGH I O pins are tri stated and act as input data pins OE is masked during the first clock of a read cycle when emerging from a deselected state ADV 83 G4 A9 Input Advance Input signal sampled on the rising Synchronous edge of CLK active LOW When asserted it automatically increments the address in a burst cycle Document 38 05237 Rev D Page 9 of 36 Feedback CY7C1380C CY7C1382C CYPRESS CY7C1382C Pin Definitions continued Name TQFP BGA fBGA Description ADSP 84 A4 B9 Input Address Strobe from Processor sampled on Synchronous the rising edge of CLK active LOW When asserted LOW addresses presented to the device are captured in the address registers A1 AO are also loaded into the burst counter When ADSP and ADSC are both asserted only ADSP is recognized ASDP is ignored when CE is deasserted HIGH 0 85 4 A8 Input Address Strobe from Controller sampled on the Synchronous rising edge of CLK active LOW When asserted LOW addresses presented to the device are captured in the address registers A1 AO are also loaded into the burst counter When ADSP and ADSC are both asserted only ADSP is recognized ZZ 64 T7 H11 Input ZZ slee
19. is one difference between the two instructions Unlike the SAMPLE PRELOAD instruction EXTEST places the SRAM outputs in a High Z state IDCODE The IDCODE instruction causes a vendor specific 32 bit code to be loaded into the instruction register It also places the instruction register between the TDI and TDO balls and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift DR state The IDCODE instruction is loaded into the instruction register upon power up or whenever the TAP controller is given a test logic reset state SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO balls when the TAP controller is in a Shift DR state It also places all SRAM outputs into a High Z state SAMPLE PRELOAD SAMPLE PRELOAD is a 1149 1 mandatory instruction The PRELOAD portion of this instruction is not implemented so the device TAP controller is not fully 1149 1 compliant When the SAMPLE PRELOAD instruction is loaded into the instruction register and the TAP controller is in the Capture DR state a snapshot of data on the inputs and bidirectional balls is captured in the boundary scan register The user must be aware that the TAP controller clock can only operate at a frequency up to 10 MHz while the SRAM clock operates more than an order of magnitude faster Because there is a large difference in the clock frequencies it is possible that during
20. not being utilized this pin must be connected to Vas This pin is not available on TQFP packages NC 1 2 3 6 7 B1 B7 A5 B1 B4 No Connects Not internally connected to the die 14 16 25 C1 C7 C1 C2 C10 D1 28 29 30 D2 D4 D10 38 39 D7 E1 E1 E10 F1 51 52 53 E6 H2 F10 G1 56 57 66 F2 G1 G10 H1 H3 H9 75 78 79 G6 H7 10 2 11 95 96 J3 J5 K1 K2 K6 L4 L2 L7 K11 L2 L1 M2 M6 M11 N2 L7 P1 P6 N2 N10 N5 N7 R1 N11 P1 A1 R5 R7 B11 T1 T4 U6 P2 R2 Document 38 05237 Rev D Page 11 of 36 Feedback i 2 5 CYPRESS Functional Overview All synchronous inputs pass through input registers controlled by the rising edge of the clock All data outputs pass through output registers controlled by the rising edge of the clock Maximum access delay from the clock rise tco is 3 0ns 200 MHz device The CY7C1380C supports secondary cache in systems utilizing either a linear or interleaved burst sequence The interleaved burst order supports Pentium i486 processors The linear burst sequence is suited for processors that utilize a linear burst sequence The burst order is user selectable and is determined by sampling the MODE input Accesses can be initiated with either the Processor Address Strobe ADSP or the Controller Address Strobe ADSC Address advancement through the burst sequence is controlled by the ADV input A two bit on chip wraparound bur
21. of these instructions are listed as RESERVED and should not be used The other five instruc tions are described in detail below The TAP controller used in this SRAM is not fully compliant to the 1149 1 convention because some of the mandatory 1149 1 instructions are not fully implemented The TAP controller cannot be used to load address data or control signals into the SRAM and cannot preload the I O buffers The SRAM does not implement the 1149 1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE PRELOAD rather it performs a capture of the I O ring when these instructions are executed Instructions are loaded into the TAP controller during the Shift IR state when the instruction register is placed between TDI and TDO During this state instructions are shifted through the instruction register through the TDI and TDO balls Document 38 05237 Rev D CY7C1380C CY7C1382C To execute the instruction once it is shifted in the TAP controller needs to be moved into the Update IR state EXTEST EXTEST is a mandatory 1149 1 instruction which is to be executed whenever the instruction register is loaded with all 05 EXTEST is not implemented in this SRAM controller and therefore this device is not compliant to 1149 1 The TAP controller does recognize an all O instruction When an EXTEST instruction is loaded into the instruction register the SRAM responds as if a SAMPLE PRELOAD instruction has been loaded There
22. the Capture DR state an input or output will undergo a transition The TAP may then try to capture a signal while in transition metastable state This will not harm the device but there is no guarantee as to the value that will be captured Repeatable results may not be possible To guarantee that the boundary scan register will capture the correct value of a signal the SRAM signal must be stabilized long enough to meet the TAP controller s capture setup plus hold time CS plus The SRAM clock input might not be captured correctly if there is no way in a design to stop or slow the clock during a SAMPLE PRELOAD instruction If this is an issue it is still possible to capture all other signals and simply ignore the value of the CLK captured in the boundary scan register Once the data is captured it is possible to shift out the data by putting the TAP into the Shift DR state This places the boundary scan register between the TDI and TDO balls Page 16 of 36 Feedback 7 CYPRESS Note that since the PRELOAD part of the command is not implemented putting the TAP to the Update DR state while performing a SAMPLE PRELOAD instruction will have the same effect as the Pause DR command BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift DR state the bypass CY7C1380C CY7C1382C register is placed between the TDI and TDO balls
23. 0C CY7C1382C Electrical Characteristics Over the Operating Rangel 2 13 continued Parameter Description Test Conditions Min Max Unit Automatic Vpp Device Deselected or 4 0 ns cycle 250 MHz 105 mA Power down Vin lt 0 3V or ViN Vppo 0 3V 4 4 le 225 MH 1 A Current CMOS Inputs f fmax 1 Hs eyes MN m 5 0 ns cycle 200 MHz 95 mA 6 0 ns cycle 167 MHz 85 mA 7 5 ns cycle 133 MHz 80 mA Automatic Vpp Max Device Deselected All speeds 80 mA Power down Vin gt ViH or VIN lt Vi f 0 Current TTL Inputs Shaded areas contain advance information Notes 12 Overshoot VIH AC lt Vpp 1 5V Pulse width less than tcyc 2 undershoot AC gt 2V Pulse width less than tcyc 2 13 TPower up Assumes a linear ramp from Ov to Vpp min within 200ms During this time lt Vpp and Vppg lt Vpp Thermal Resistance TQFP BGA fBGA Parameter Description Test Conditions Package Package Package Unit OA Thermal Resistance Test conditions follow standard 31 45 46 C W Junction to Ambient test methods and procedures for measuring thermal Thermal Resistance impedence per JESD51 6 7 3 C W Junction to Case Capacitance 4 TQFP BGA fBGA Parameter Description Test Conditions Package Package Package Unit Cin Input Capacitance TA 25 C
24. 2 C4 J4 R4 D4 D8 E4 E8 Power Supply Power supply inputs to the core of the de 91 J6 F4 F8 vice G4 G8 H4 H8 J4 J8 K4 K8 L4 L8 M4 M8 Vss 17 40 67 D3 E3 C4 C5 C6 C7 Ground Ground for the core of the device 90 F3 H3 C8 D5 D6 D7 K3 M3 E5 E6 E7 F5 N3 P3 F6 F7 G5 G6 D5 E5 G7 H2 H5 H6 F5 H5 H7 J5 J6 J7 K5 M5 K5 K6 K7 N5 P5 L5 L6 L7 M5 M6 M7 N4 N8 Document 38 05237 Rev D Page 7 of 36 Feedback CY7C1380C E CY7C1382C z CYPRESS CY7C1380C Pin Definitions continued Name TQFP BGA fBGA 1 0 Description Vsso 5 10 21 26 55 gt Ground Ground for the I O circuitry 60 71 76 VDDQ 4 11 20 27 54 A1 F1 J1 M1 C3 C9 D3 D9 I O Power Power supply for the I O circuitry 61 70 U1 E3 E9 F3 F9 G Supply 77 A7 F7 J7 M7 3 U7 G9 J3 J9 K3 K9 L3 L9 M3 M9 N3 N9 MODE 31 R3 R1 Input Selects Burst Order When tied to GND Static selects linear burst sequence When tied to Vpp or left floating selects interleaved burst sequence This is a strap pin and should remain static during device operation Mode Pin has an internal pull up TDO U5 P7 JTAG serial Serial data out to the JTAG circuit Delivers output data on the negative edge of TCK If the JTAG Synchronous feature is not being utilized this pin should be disconnected This pin is not available on TQFP packages TDI U3 P5 JTAG serial Serial data In to the
25. CY7C1380C CY7C1382C Features Supports bus operation up to 250 MHz Available speed grades are 250 225 200 166 and 133MHz Registered inputs and outputs for pipelined operation 3 3V core power supply 2 5V 3 3V operation Fast clock to output times 2 6 ns for 250 MHz device 2 8 ns for 225 MHz device 3 0 ns for 200 MHz device 3 4 ns for 166 MHz device 4 2 ns for 133 MHz device Provide high performance 3 1 1 1 access rate User selectable burst counter supporting Intel Pentium interleaved or linear burst sequences Separate processor and controller address strobes Synchronous self timed writes Asynchronous output enable Single Cycle Chip Deselect Offered in JEDEC standard 100 pin TQFP 119 ball BGA and 165 Ball fBGA packages IEEE 1149 1 JTAG Compatible Boundary Scan ZZ Sleep Mode Option Selection Guide 18 Mb 512K x 36 1M x 18 Pipelined SRAM Functional Description The CY7C1380C CY7C1382C SRAM integrates 524 288 x 36 and 1 048 576 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two bit counter for internal burst operation All synchronous inputs are gated by registers controlled by a positive edge triggered Clock Input CLK The synchronous inputs include all addresses all data inputs address pipelining Cr Sn Enable depth expansion Chip Enables CE and 2 Burst Control inputs ADSC and ADV Write Enables BW
26. It is possible to operate the SRAM without using the JTAG feature To disable the TAP controller TCK must be tied LOW VSS to prevent clocking of the device TDI and TMS are internally pulled up and may be unconnected They may alter nately be connected to Vpp through a pull up resistor TDO should be left unconnected Upon power up the device will come up in a reset state which will not interfere with the operation of the device TAP Controller State Diagram d TESTLOGIC RESET 0 Y 1 RUN TEST 1 SELECT 1 SELECT 1 IDLE n DRSCAN IR SCAN 0 0 1 1 CAPTURE DR CAPTURE IR 0 0 Y Y SHIFT DR 0 SHIFT IR D 0D 1 1 1 1 EXITLDR EXITLIR 0 0 Y Y PAUSEDR 0 PAUSE IR 0 92 1 1 0 0 i EXIT2 DR EXIT2 IR 1 1 Y UPDATEDR UPDATEIR 0 1 0 Y The 0 1 next to each state represents the value of TMS at the rising edge of TCK Test Access Port TAP Test Clock TCK The test clock is used only with the TAP controller All inputs are captured on the rising edge of TCK All outputs are driven from the falling edge of TCK Instruction Register Document 38 05237 Rev D CY7C1380C CY7C1382C Test MODE SELECT TMS The TMS input is used to give commands to the TAP controller and is sampled on the
27. JTAG circuit Sampled input on the rising edge of TCK If the JTAG feature Synchronous is not being utilized this pin can be discon nected or connected to Vpp This pin is not available on TQFP packages TMS U2 R5 JTAG serial Serial data In to the JTAG circuit Sampled input on the rising edge of TCK If the JTAG feature Synchronous is not being utilized this pin can be discon nected or connected to Vpp This pin is not available on TQFP packages TCK U4 R7 JTAG Clock Clock input to the JTAG circuitry If the JTAG feature is not being utilized this pin must be connected to Vss This pin is not available on TQFP packages NC 14 16 66 B1 C1 A11 B1 C2 C1 No Connects Not internally connected to the 39 38 R1 T1 T2 78 0 H1 H3 H9 die 04 H10 L4 J5 R5 6T N2 N5 N7 N10 6U PT A1 B11 P2 B7 C7 R2 N6 R7 Document 38 05237 Rev D Page 8 of 36 Feedback CY7C1380C CY7C1382C CYPRESS CY7C1382C Pin Definitions Name TQFP BGA fBGA Description Ag A4 37 36 32 P4 N4 R6 P6 A2 Input Address Inputs used to select one of the 512K 33 34 35 A2 B2 A10 A11 Synchronous address locations Sampled at the rising edge of 42 43 44 C2 R2 B2 B10 P3 P4 the CLK if ADSP or ADSC is active LOW and CE 45 46 47 T2 A3 N6 P8 P9 and are sampled active A1 AO are fed 48 49 50 B3 C3 P10 P11 to the two bit counter 80 81 82 T3 A5
28. Pipelined Read Write Timing diagram Added tpower specification in Switching Characteristics table D 206081 02 13 04 RKF Final Datasheet Document 38 05237 Rev D Page 36 of 36 Feedback
29. Y7C1380C CY7C1382C 3 3V TAP AC Test Conditions 2 5V TAP AC Test Conditions Input pulse levels sse Vss to 3 3V Input pulse levels Vss to 2 5V Input rise and fall times sese ins Input rise and fall time ins Input timing reference 1 5V Input timing reference 1 25V Output reference levels sse 1 5V Output reference levels 1 25V Test load termination supply voltage 1 5V Test load termination supply voltage 1 25V 3 3V TAP AC Output Load Equivalent 2 5V TAP AC Output Load Equivalent 1 5V 1 25V 50Q 500 TDO TDO 20 500 20pF Zo 502 20pF TAP DC Electrical Characteristics And Operating Conditions 0 C lt TA lt 70 Vdd 3 3V 0 165V unless otherwise noted PARAMETER DESCRIPTION TEST CONDITIONS MIN MAX UNITS VoH1 Output HIGH Voltage loH 4 0 mA Vppo 3 3V 2 4 V lou 1 0 mA Vppo 2 5 2 0 V Output HIGH Voltage 1 100 pA Vppo 3 3V 2 9 V Vppo 2 5V 2 1 V Vout Output LOW Voltage loj 8 0 mA Vppo 3 3V 0 4 V Vppo 2 5V 0 4 V Voi Output LOW Voltage lo 100 HA Vppo 3 3V 0 2 V Vppo 2 5V 0 2 V
30. affect SRAM operations SAMPLE Z 010 Captures ring contents Places the boundary scan register between TDI and Forces all SRAM output drivers to a High Z state RESERVED 011 Do Not Use This instruction is reserved for future use SAMPLE PRELOAD 100 Captures ring contents Places the boundary scan register between TDI and Does not affect SRAM operation This instruction does not implement 1149 1 preload function and is therefore not 1149 1 compliant RESERVED 101 Do Not Use This instruction is reserved for future use RESERVED 110 Do Not Use This instruction is reserved for future use BYPASS 111 Places the bypass register between TDI and TDO This operation does not affect SRAM operations Document 38 05237 Rev D Page 19 of 36 Feedback 119 Ball BGA Boundary Scan Order CY7C1380C CY7C1382C CY7C1380C 512K x 36 BIT BALL ID BIT BALL ID 1 K4 37 B2 2 H4 38 P4 3 M4 39 N4 4 F4 40 R6 5 B4 41 T5 6 A4 42 T3 7 G4 43 R2 8 C6 44 R3 9 A6 45 P2 10 D6 46 P1 11 D7 47 N2 12 E6 48 L2 13 G6 49 K1 14 H7 50 N1 15 E7 51 M2 16 F6 52 L1 17 G7 53 K2 18 H6 54 Not Bonded Preset to 1 19 T7 55 H1 20 K7 56 G2 21 L6 57 E2 22 N6 58 D1 23 P7 59 H2 24 K6 60 G1 25 L7 61 F2 26 M6 62 E1 27 N7 63 D2 28 P6 64 A5 29 B5 65 A3 30 B3 66 E4 31 C5 67 Internal 32 C3 68 L3
31. and BWE and Global Write GW Asynchronous inputs iriclude the Output Enable OE and the ZZ pin Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor ADSP or Address Strobe Controller ADSC are active Subsequent burst addresses can be internally generated as controlled by the Advance pin ADV Address data inputs and write controls are registered on chip to initiate a self timed Write cycle This part supports Byte Write operations see Pin Descriptions and Truth Table for further details Write cycles can be one to two or four bytes wide as controlled by the byte write control inputs GW when active LOW causes all bytes to be written The CY7C1380C CY7C1382C operates from a 3 3V core power supply while all outputs may operate with either a 2 5 or 3 3V supply All inputs and outputs are JEDEC standard JESD8 5 compatible 250 MHz 225 MHz 200 MHz 167 MHz 133 MHz Unit Maximum Access Time 2 6 2 8 3 0 3 4 4 2 ns Maximum Operating Current 350 325 300 275 245 mA Maximum CMOS Standby Current 70 70 70 70 70 mA Shaded areas contain advance information Please contact your local Cypress sales representative for availability of these parts Notes 1 For best practices recommendations please refer to the Cypress application note System Design Guidelines on www cypress com 2 are for TQFP and 165 fBGA packag
32. d TDO balls This allows data to be shifted through the SRAM with minimal delay The bypass register is set LOW Vss when the BYPASS instruction is executed Boundary Scan Register The boundary scan register is connected to all the input and bidirectional balls on the SRAM The SRAM has a 75 bit long register The boundary scan register is loaded with the contents of the RAM ring when the TAP controller is in the Capture DR state and is then placed between the TDI and TDO balls when the controller is moved to the Shift DR state The EXTEST SAMPLE PRELOAD and SAMPLE Z instructions can be used to capture the contents of the ring The Boundary Scan Order tables show the order in which the bits are connected Each bit corresponds to one of the bumps on the SRAM package The MSB of the register is connected to TDI and the LSB is connected to TDO Identification ID Register The ID register is loaded with a vendor specific 32 bit code during the Capture DR state when the IDCODE command is loaded in the instruction register The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift DR state The ID register has a vendor code and other information described in the Identification Register Definitions table TAP Instruction Set Overview Eight different instructions are possible with the three bit instruction register All combinations are listed in the Instruction Codes table Three
33. e 33 34 35 A2 B2 A10 B2 Synchronous 256K address locations Sampled atthe rising 42 43 44 45 C2 R2 B10 N6 P3 P4 edge of the CLK if ADSP or ADSC is active 46 47 48 A3 B3 C3 P8 P9 P10 LOW CE and CE3 Jare sampled 49 50 81 T3 T4 A5 B5 P11 R3 R4 R8 active A1 AO are fed to the two bit counter 82 99 100 C5 R9 R10 R11 T5 A6 B6 C6 R6 BW BWg 93 94 95 L5 G5 5 5 4 Input Byte Write Select Inputs active LOW BW BW 96 G3 L3 B4 Synchronous Qualified with BWE to conduct byte writes to the eru SRAM Sampled on the rising edge of CLK GW 88 H4 B7 Input Global Write Enable Input active LOW Synchronous When asserted LOW on the rising edge of CLK a global write is conducted ALL bytes are written regardless of the values on BWy and BWE BWE 87 4 A7 Input Byte Write Enable Input active LOW Sam Synchronous pled on the rising edge of CLK This signal must be asserted LOW to conduct a byte write CLK 89 4 B6 Input Clock Input Used to capture all synchronous Clock inputs to the device Also used to increment the burst counter when ADV is asserted LOW during a burst operation 98 4 Input Chip Enable 1 Input active LOW Sampled on 1 Synchronous the rising edge of CLK Used in conjunction with CE and CE to select deselect the device ADSP is ignored if is HIGH CE 97 B3 Input Chip Enable 2 Input active HIGH Sampled Synchronous on the rising edge of CLK Used in conjunction wit
34. e rising edges of TCK This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating At power up the TAP is reset internally to ensure that TDO comes up in a High Z state TAP Registers Registers are connected between the TDI and TDO balls and allow data to be scanned into and out of the SRAM test circuitry Only one register can be selected at a time through the instruction register Data is serially loaded into the TDI ball on the rising edge of TCK Data is output on the TDO ball on the falling edge of TCK Three bit instructions can be serially loaded into the instruction register This register is loaded when it is placed between the Page 15 of 36 Feedback am 7 CYPRESS TDI and TDO balls as shown in the Tap Controller Block Diagram Upon power up the instruction register is loaded with the IDCODE instruction It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section When the TAP controller is in the Capture IR state the two least significant bits are loaded with a binary 01 pattern to allow for fault isolation of the board level serial test data path Bypass Register To save time when serially shifting data through registers it is sometimes advantageous to skip certain chips The bypass register is a single bit register that can be placed between the TDI an
35. e only 119 BGA is offered only in 1 Chip Enable Cypress Semiconductor Corporation Document 38 05237 Rev D 3901 North First Street San Jose CA 95134 408 943 2600 Revised February 26 2004 Feedback NN CY7C1380C CY7C1382C Logic Block Diagram CY7C1380C 512K x 36 A1 gt ADDRESS gt REGISTER 2 ADV b Ql CLK BURST COUNTER ar AND qo RBS t apn LOGIC 4 0000 DQo DOP D WRITE REGISTER WRITE DRIVER n 50 09 DOcDOPC BWc BYTE T IDH warRGsER LI gt WRITE DRIVER AENOR E OUTPUT OUTPUT H ARRAY gt AMPS REGISTERS BUFFERS DOPA b DQsDQPs 008 A E DOP up i A DQPc D WRITE REGISTER nee Lai 095 gt DQADQPA gt D ave k WRITE DRIVER BWE y REGISTER T INPUT aw L E b ENABLE _ PIPELINED REGISTERS i REGISTER ENABLE 1j CE N SLEEP 2 CONTROL Logic Block Diagram CY7C1382C 1M x 18
36. e write enable signals BWE GW H The DQ pins are controlled by the current cycle and the OE signal OE is asynchronous and is not sampled with the clock gt o o CE4 are available only in the TQFP package BGA package has only 2 chip selects CE and CE The SRAM always initiates a read cycle when ADSP is asserted regardless of the state of GW BWE BWy Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC As a result OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri state OE is a don t care for the remainder of the write cycle 8 OE is asynchronous and is not sampled with the clock rise It is masked internally during write cycles During a read cycle all data bits are Tri State when is inactive or when the device is deselected and all data bits behave as output when OE is active LOW Truth Table for Read Write Function CY7C1380C m o gt Read Read Write Byte A DQ and DQPA Write Byte B DQg Write Bytes B A Write Byte C DQc and DQPc Write Bytes C A Write Bytes C B Write Bytes C B A Write Byte D DQp DQPp Write Bytes D A Write Bytes D B Write Bytes D B A Write Bytes D C Write Bytes D C A Write Bytes D C B Write All Bytes Write All
37. ed HIGH ADSC 85 B4 A8 Input Address Strobe from Controller sampled on Synchronous the rising edge of CLK active LOW When asserted LOW addresses presented to the device are captured in the address registers A1 A0 are also loaded into the burst counter When ADSP and ADSC are both asserted only ADSP is recognized ZZ 64 T7 H11 Input ZZ sleep Input active HIGH When Asynchronous asserted HIGH places the device in a non time critical sleep condition with data integrity preserved For normal operation this pin has to be LOW or left floating ZZ pin has an internal pull down DQPs 52 53 56 K6 L6 M11 L11 Bidirectional Data I O lines As inputs they 57 58 59 K11 J11 Synchronous feed into an on chip data register that is 62 63 68 K7 L7 J10 K10 triggered by the rising edge of CLK As outputs 69 72 73 N7 P7 L10 M10 they deliver the data contained in the memory 74 75 78 E6 F6 D10 E10 location specified by the addresses presented 79 2 3 6 7 8 9 G6 H6 F10 G10 during the previous clock rise of the read cycle 12 13 18 19 22 D7 E7 D11 E11 The direction of the pins is controlled by OE G7 H7 F11 G11 When OE is asserted LOW the pins behave as 23 24 25 D1 E1 D1 E1 F1 outputs When HIGH DQs and DQPy are 28 29 51 G1 H1 G1 D2 E2 F2 placed in a tri state condition 80 1 30 E2 F2 G2 41 G2 H2 K1 L1 M1 K1 L1 J2 K2 L2 N1 P1 M2 N11 K2 L2 C11 C1 N1 M2 N2 P6 D6 D2 P2 Vpp 15 41 65 J
38. enter into or exit from this sleep mode While in this mode data integrity is guaranteed Accesses pending when entering the sleep mode are not considered valid nor is the completion of the operation guaranteed The device must be deselected prior to entering the sleep mode ADSP and ADSC must remain inactive for the duration of tzzngc after the ZZ input returns LOW Parameter Description Test Conditions Min Max Unit Ippzz Snooze mode standby current ZZ gt Vpp 0 2V 60mA mA 1775 Device operation to ZZ ZZ gt Vpp 0 2V 2tcvc ns tz7REC ZZ recovery time ZZ lt 0 2V 2tcyc ns tzzi ZZ Active to snooze current This parameter is sampled 2tcvc ns 1377 ZZ Inactive to exit snooze current This parameter is sampled 0 ns Truth Table 3 4 5 6 7 8 Operation Add Used CE CE ZZ ADSP ADSC ADV WRITE DQ Deselect Cycle Power Down None H X X L X L X X X L H Tri State Deselect Cycle Power Down None L L X L L X X X X L H Tri State Deselect Cycle Power Down None L X H L L X X X X L H Tri State Deselect Cycle Power Down None L L X L H L X X X L H Tri State Deselect Cycle Power Down None L X H L H L X X X L H Tri State Snooze Mode Power Down None X X X H X X X X X X Tri State READ Cycle Begin Burst External L H L L L X X X L L H Q READ Cycle Begin Burst External L H L L L X X X
39. gt lt 1 tas lt gt lt gt ADDRESS Al A2 IK Zm A x BWE twES BWx wm tces lt gt V m IN I d 77 D m N VM ____ OE tco tos i lt lt gt tOELZ Data In D High Z 0043 D A5 DA gt az pez 4 5 A A WWW aou nz an one Back to Back READs 5 Single WRITE DON T CARE BURST READ UNDEFINED Note 23 The data bus Q remains in high Z following a WRITE cycle unless a new read access is initiated by ADSP or ADSC 24 GW is HIGH Document 38 05237 Rev D Badeto Back 9 gt WRITEs Page 30 of 36 CY7C1380C CY7C1382C gt CYPRESS Switching Waveforms continued e a kachkas yn lt ZZ t zZ cuppLy UN Ippzz teza except ZZ DON T CARE Notes 25 Device must be deselected when entering ZZ mode See Cycle Descriptions table for all possible signal conditions to deselect the device 26 DGs are in high Z when exiting ZZ sleep mode Document 38 05237 Rev D Page 31 of 36 Feedback CY7C1380C
40. h CE and CE to select deselect the device 92 A6 Input Chip Enable 3 Input active LOW Sampled Synchronous the rising edge of CLK Used in conjunction with CE and CE to select deselect the device Not available for AJ package version Not connected for BGA Where referenced CE is assumed active throughout this document for BGA 86 4 B8 Input Output Enable asynchronous input active Asynchronous LOW Controls the direction of the I O pins When LOW the pins behave as outputs When deasserted HIGH I O pins are tri stated and act as input data pins OE is masked during the first clock of a read cycle when emerging from a deselected state ADV 83 G4 AQ Input Advance Input signal sampled on the rising Synchronous edge of CLK active LOW When asserted it automatically increments the address in a burst cycle Document 38 05237 Rev D Page 6 of 36 Feedback CY7C1380C E CY7C1382C CYPRESS CY7C1380C Pin Definitions continued Name TQFP BGA fBGA 1 0 Description ADSP 84 A4 B9 Input Address Strobe from Processor sampled Synchronous on the rising edge of CLK active LOW When asserted LOW addresses presented to the device are captured in the address registers A1 A0 are also loaded into the burst counter When ADSP and ADSC are both asserted only ADSP is recognized ASDP is ignored when CE is deassert
41. ication implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges Feedback CY7C1380C CY7C1382C SSF CYPRESS n Package Diagrams continued 119 Lead PBGA 14 x 22 x 2 4 mm BG119 51 85115 B Document 38 05237 Rev D Page 34 of 36 Feedback gt CYPRESS Package Diagrams continued 165 Ball FBGA 13 x 15 x 1 2 mm BB165A CY7C1380C CY7C1382C 51 85122 i486 is a trademark and Intel and Pentium are registered trademarks of Intel Corporation PowerPC is trademark of IBM Corporation All product and company names mentioned in this document are the trademarks of their respective holders Document 38 05237 Rev D Page 35 of 36 Feedback CYPRESS Document History Page CY7C1380C CY7C1382C Document Title CY7C1380C CY7C1382C 18 Mb 512K x 36 1M x 18 Pipelined SRAM Document Number 38 05237 Orig of REV NO Issue Date Change Description of Change Tt 116277 08 27 02 SKX New Data Sheet 121540 11 21 02 DSG Updated package diagrams 51 85115 BG119 to rev B and 51 85122 BB165A to rev C B 121797 11 21 02 CJM Added 7C1380C 133 spec Updated Ordering Information 128904 09 11 03 Changed ordering of notes Updated JTAG Boundary Scan order Removed
42. ided to simplify the Write operations Because the CY7C1380C is a common I O device the Output Enable OE must be deserted HIGH before presenting data to the DQs inputs Doing so will tri state the output drivers As a safety precaution DQs are automatically tri stated whenever a Write cycle is detected regardless of the state of OE Single Write Accesses Initiated by ADSC ADSC Write accesses are initiated when the following condi tions are satisfied 1 ADSC is asserted LOW 2 ADSP is deserted HIGH 3 CE CEs are all asserted active and 4 the appropriate combination of the Write inputs GW BWE and BWy are asserted active to conduct a Write to the desired byte s ADSC triggered Write accesses require a single clock cycle to complete The address presented to A is loaded into the address register and the address advancement logic while being delivered to the memory array The ADV input is ignored during this cycle If a global Write is conducted the data presented to the DQs is written into the corresponding address location in the memory core If a Byte Write is conducted only the selected bytes are written Bytes not selected during a Byte Write operation will remain unaltered A synchronous self timed Write mechanism has been provided to simplify the Write operations Because the CY7C1380C is a common I O device the Output Enable OE must be deserted HIGH before presenting data to the DQs inputs Doing so will t
43. n voltage and temperature togpz is less than tog 7 and is less than tc to eliminate bus contention between SRAMs when sharing the same data bus These specifications do not imply a bus contention condition but reflect parameters guaranteed over worst case user conditions Device is designed to achieve High Z prior to Low Z under the same system conditions 18 This parameter is sampled and not 100 tested 19 Timing reference level is 1 5V when Vppo 3 3V and is 1 25V when 2 5V 20 Test conditions shown in a of AC Test Loads unless otherwise noted Document 38 05237 Rev D Page 27 of 36 Feedback Ea CYPRESS Switching Waveforms Read Cycle Timing CY7C1380C CY7C1382C V W W W W W u ATA gt gt ADS pH a lt gt ui ww taps ADH W W 077 0 W ADSC w Ui m 7 TO Burst continued with T gt TI om mmm 0 Q WW T mm 7 D 7 WI a 70 Nnm T High Z tco Data Out Q Notes Burst wraps around F Single READ Document 38 05237 Rev D DON T CARE UNDEFINED BURST READ OE t lt 4 gt t 08 toez az gt
44. ns Min Max Unit Vpp Power Supply Voltage 3 135 3 6 V VDDQ Supply Voltage Vppo 3 3V 3 135 Vpp V Vppo 2 5V 2 375 2 625 V VoH Output HIGH Voltage Vppo 3 3V Vpp Min 4 0 mA 2 4 V Vppo 2 5V Vpp Min 1 0 mA 2 0 V VoL Output LOW Voltage Vppo 3 3V Vpp Min Io 8 0 mA 0 4 V Vppo 2 5V Vpp Min loj 1 0 mA 0 4 V Input HIGH Voltage 3 3V 2 0 Vpp 03V V Vppo 2 5V 1 7 Vpp 0 3V V Vi Input LOW Voltage 2 Vppo 3 3V 0 3 0 8 Vppo 2 5V 0 3 0 7 V lx Input Load Current ex GND lt Vi lt 5 5 ZZ and MODE Input Current of MODE Input Vss 30 Input Vpp 5 uA Input Current of ZZ Input Vss 30 Input Vpp 5 loz Output Leakage Current GND lt V x Vppo Output Disabled 5 5 155 Vpp Operating Supply Vpp Max lour 0 4 0 ns cycle 250 MHz 350 mA Current f fmax 1 4 4 ns cycle 225 MHz 325 mA 5 0 ns cycle 200 MHz 300 mA 6 0 ns cycle 167 MHz 275 mA 7 5 ns cycle 133 MHz 245 mA Ispi Automatic CE Vpp Max Device Deselected 4 0 ns cycle 250 MHz 120 mA 5 0 ns cycle 200 MHz 100 mA 6 0 ns cycle 167 MHz 90 mA 7 5 ns cycle 133 MHz 85 mA Ispo Automatic CE Vpp Max Device Deselected All speeds 70 mA Power down Vin lt 0 3V or Vin gt Vppo 0 3V Current CMOS Inputs f 0 Document 38 05237 Rev D Page 24 of 36 Feedback CY7C138
45. p Input active HIGH When asserted Asynchronous HIGH places the device in a non time critical sleep condition with data integrity preserved For normal operation this pin has to be LOW or left floating ZZ pin has an internal pull down 00 58 59 62 P7 K7 J10 K10 I O Bidirectional Data I O lines As inputs they feed DQPs 63 68 69 G7 E7 L10 M10 Synchronous into an on chip data register that is triggered by the 72 73 8 9 F6 H6 L6 N6 D11 E11 rising edge of CLK As outputs they deliver the data 12 13 18 D1 F11 G11 J1 K1 contained in the memory location specified by the 19 22 23 H1 L1 L1 M1 D2 E2 addresses presented during the previous clock rise 74 24 N1 E2 F2 of the read cycle The direction of the pins is G2 K2 G2 C11 N1 controlled by OE When OE is asserted LOW the M2 D6 pins behave as outputs When HIGH DQs and P2 DQPx are placed in a tri state condition Vpp 15 41 65 C4 J2 J4 J6 D4 D8 E4 E8 Power Supply Power supply inputs to the core of the device 91 R4 F4 F8 G4 G8 H4 H8 J4 J8 K4 K8 L4 L8 M4 M8 Vss 17 40 67 D3 D5 H2 C4 C5 C6 Ground Ground for the core of the device 90 E5 E3 F3 F5 C7 C8 D5 D6 G5 D7 E5 E6 E7 H3 H5 F5 F6 F7 K3 K5 L3 M3 G5 G6 G7 M5 H5 H6 H7 J5 J N3 N5 6 J7 P3 P5 K5 K6 K7 L5 L6 L7 M5 M6 M7 N4 N8 Vsso 5 10 21 26 55 Ground Ground for the I O circuitry 60 71 76 Document 38 05237 Rev D Page 10 of 36 Feedback
46. p Vss Vss Vss VDD Vppo DQg NC Vss NC Vas Vss Vss Vss Vpp NC NC 77 J DQp DQp Vpp Vss Vss Vss VDD Vppo DQA DQA K DQp DQp Vpp Vss Vss Vss Vpp DQA DQA L DQp DQp Vpp Vss Vss Vss Vpp DQA DQA M DQp DQp Vppo Vpp Vss Vss Vss Vpp Vppa DQA DQA N DQPp NC Vppo Vss NC A NG Vss Vppo NC NC 72M A A TDI A1 TDO A A A A R MODE NC 36M A A TMS A0 TCK A A A A CY7C1382C 1M x 18 1 2 3 4 5 6 7 8 9 10 11 NC 28M A CE BWg NC CEs BWE ADSC ADV A A B NC A NC BWA CLK GW OE ADSP A NC 144M C NC NC Vppo Vss Vss Vss Vss Vss Vppo NC DQPA D NC DQg Vppo Vpp Vss Vss Vss Vpp Vppo NC DQA E NC DQg Vppo Vpp Vss Vss Vss Vpp Vppo NC DQA F NC Vpp Vss Vss Vss Vpp NC DQA G NC DQg Vppo Vpp Vss Vss Vss Vpp Vppo NC DQA H NC MES NC Vss Vss Vss Wop NC NC 77 J DQg NC VDDQ Vpp Vss Vss Vss Vpp VDDQ DQA NC K DQg NC Vppo Vpp Vss Vss Vss Vpp Vppo DQA NC L DQg NC Vppo Vpp Vss Vss Vss Vpp Vppo DQA NC M DQg NC Vppo Vpp Vss Vss Vss Vpp Vppo DQA NC N DQPp NC Vppo Vss NC A NC Vss NC 72M A A TDI A1 TDO A A A A R MODE NC 36M A A TMS TCK A A A A Document 38 05237 Rev D Page 5 of 36 Feedback CY7C1380C LE CY7C1382C Z CYPRESS CY7C1380C Pin Definitions Name TQFP BGA fBGA Description A4 37 36 32 P4 N4 R6 P6 A2 Input Address Inputs used to select one of th
47. ri state the output drivers As safety precaution DQs are automatically tri stated whenever a Write cycle is detected regardless of the state of OE Burst Sequences The CY7C1380C provides a two bit wraparound counter fed by A1 AO that implements either an interleaved or linear burst sequence The interleaved burst sequence is designed specif ically to support Intel Pentium applications The linear burst sequence is designed to support processors that follow a linear burst sequence The burst sequence is user selectable through the MODE input Page 12 of 36 Feedback i CYPRESS Asserting ADV LOW at clock rise will automatically increment the burst counter to the next address in the burst sequence Both Read and Write burst operations are supported Interleaved Burst Address Table MODE Floating or Vpp First Second Third Fourth Address Address Address Address A1 AO A1 AO A1 AO A1 AO 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 Linear Burst Address Table MODE GND First Second Third Fourth Address Address Address Address A1 AO A1 AO A1 AO A1 AO 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 ZZ Mode Electrical Characteristics CY7C1380C CY7C1382C Sleep Mode The ZZ input pin is an asynchronous input Asserting ZZ places the SRAM in a power conservation sleep mode Two clock cycles are required to
48. rising edge of TCK It is allowable to leave this ball unconnected if the TAP is not used The ball is pulled up internally resulting in a logic HIGH level Test Data In TDI The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register For information on loading the instruction register see Figure TDI is internally pulled up and can be unconnected if the TAP is unused in an application TDI is connected to the most signif icant bit MSB of any register See Tap Controller Block Diagram Test Data Out TDO The TDO output ball is used to serially clock data out from the registers The output is active depending upon the current state of the TAP state machine The output changes on the falling edge of TCK TDO is connected to the least significant bit LSB of any register See Tap Controller State Diagram TAP Controller Block Diagram 0 1m Bypass Register gt 2 10 Selection MS Instruction Register Circuitry Selection 813029 2 1 0 Circuitry Identification Register Boundary Scan Register S g Ip TDI TDO o TMS CONTROLLER Performing Reset A RESET is performed by forcing TMS HIGH VDD for fiv
49. st counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access Byte Write operations are qualified with the Byte Write Enable BWE and Byte Write Select BWy inputs A Global Write Enable GW overrides all Byte Write inputs and writes data to all four bytes All writes are simplified with on chip synchronous self timed Write circuitry Three synchronous Chip Selects and asynchronous Output Enable OE provide for easy bank selection and output tri state control ADSP is ignored if CE is HIGH Single Read Accesses This access is initiated when the_following conditions are satisfied at clock rise 1 ADSP or ADSC is asserted LOW 2 CE4 CE3 are all asserted active and 3 the Write signals GW BWE are all deserted HIGH ADSP is ignored if CE is HIGH The address presented to the address inputs A is stored into the address advancement logic and the Address Register while being presented to the memory array The corresponding data is allowed to propagate to the input of the Output Registers At the rising edge of the next clock the data is allowed to propagate through the output register and onto the data bus within 3 0 ns 200 MHz device if OE is active LOW The only exception occurs when the SRAM is emerging from a deselected state to a selected state its outputs are always tri stated during the fir
50. st cycle of the access After the first cycle of the access the outputs are controlled by the OE signal Consecutive single Read cycles are supported Once the SRAM is deselected at clock rise by the chip select and either ADSP or ADSC signals its output will tri state immedi ately Single Write Accesses Initiated by ADSP This access is initiated when both of the following conditions are satisfied at clock rise 1 ADSP is asserted LOW and 2 CE4 CEs are all asserted active The address Document 38 05237 Rev D CY7C1380C CY7C1382C presented to A is loaded into the address register and the address advancement logic while being delivered to the memory array The Write signals GW BWE and BWy and ADV inputs are ignored during this first cycle ADSP triggered Write accesses require two clock cycles to complete If GW is asserted LOW on the second clock rise the data presented to the DQs inputs is written into the corre sponding address location in the memory array If GW is HIGH then the Write operation is controlled by BWE BWy signals The CY7C1380C provides Byte Write capability that is described in the Write Cycle Descriptions table Asserting the Byte Write Enable input BWE with the selected Byte Write BWy input will selectively write to only the desired bytes Bytes not selected during a Byte Write operation will remain unaltered A synchronous self timed Write mechanism has been prov
51. t Bonded Preset to 0 24 Not Bonded Preset to 0 60 Not Bonded Preset to 0 25 Not Bonded Preset to 0 61 Not Bonded Preset to 0 26 Not Bonded Preset to 0 62 Not Bonded Preset to 0 27 Not Bonded Preset to 0 63 A2 28 R11 64 B2 29 R10 65 A3 30 R9 66 B3 31 R8 67 Not Bonded Preset to 0 32 P10 68 Not Bonded Preset to 0 33 P9 69 A4 34 P8 70 B5 35 P11 71 A6 Document 38 05237 Rev D Page 23 of 36 Feedback CY7C1380C CY7C1382C CYPRESS Maximum Ratings Current into Outputs LOW 20 mA Above which the useful life may be impaired For user guide DSTI RS Were QOIS CHA E Y REDUX lines not tested Storage Temperaire _65 C to 150 C Latch up Current esee gt 200 mA Ambient Temperature with Power Applied 55 C to 125 Operating Range Supply Voltage on Vpp Relative to GND 0 3V to 4 6V Ambient DC Voltage Applied to Outputs Range Temperature Vpp Vppo IN Tri State 0 5V to Vppo 0 5V Commercial 0 C to 70 5 10 2 5V 5 DC Input 0 5V to Vpp 0 5V Industrial 40 C to 85 to Vpp Electrical Characteristics Over the Operating Rangel 13 Parameter Description Test Conditio
Download Pdf Manuals
Related Search