Cypress CY7C138 User's Manual
Contents
1. 7C138 15 7138 25 7138 35 7138 55 Parameter Description 7C139 15 7139 25 7C139 35 7C139 55 Unit Min Max Min Max Min Max Min Max tup Data Hold From Write End 0 0 0 0 ns tuzwe 171 R W LOW to High Z 10 15 20 25 ns tizwe R W HIGH to Low Z 3 3 3 3 ns twop Write Pulse to Data Delay 30 50 60 70 ns tppp Write Data Valid to Read Data Valid 25 30 35 40 ns BUSY TIMING 4 tBLA BUSY LOW from Address Match 15 20 20 45 ns tBHA BUSY HIGH from Address Mismatch 15 20 20 40 ns tic BUSY LOW from CE LOW 15 20 20 40 ns tuc BUSY HIGH from CE HIGH 15 20 20 35 ns tps Port Set Up for Priority 5 5 5 5 ns twp R W LOW after BUSY LOW 0 0 0 0 ns twn R W HIGH after BUSY HIGH 13 20 30 40 ns tgpp l BUSY HIGH to Data Valid Note 15 Note 15 Note 15 Note 15 ns INTERRUPT TIMING 4 tins INT Set Time 15 25 25 30 ns tine INT Reset Time 15 25 25 30 ns SEMAPHORE TIMING tsop SEM Flag Update Pulse OE or SEM 10 10 15 20 ns tewRD SEM Flag Write to Read Time 5 5 5 5 ns tsps SEM Flag Contention Window 5 5 5 5 ns Switching Waveforms Figure 3 Read Cycle No 1 Either Port Address Access M tre ADDRESS DATA OUT PREVIOUS DATA VALID DATA VALID Figure 4 Read Cycle No 2 Either Port CE OE Access 6 18 19 Notes 9 Test conditions assume signal transition time of 3 ns or less timing reference levels of 1 5V input pulse levels of 0 to 3 0V and output loading of the sp2. Cypress Semiconductor Corporation Document 38 06037 Rev D 198 Champion Court San Jose CA 95134 1709 408 943 2600 Revised March 12 2009 Feedback CY7C138 CY7C139 Pin Configurations Figure 1 68 Pin PLCC Top View 9876 5432 168 6766 65 64 63 62 61 CY7C138 9 6 2728 29 30 3132 33 34 35 36 37 38 39 40 41 42 43 ecm ruoonoomtm grmumxrmut j hep ee se Free tee Table 1 Pin Definitions Left Port Right Port Description l Ooi 71 eL l Oon 7R 8R Data Bus Input Output Ag 44L Aor 11R Address Lines CE CER Chip Enable OE OER Output Enable RW R Wg Read Write Enable SEM SEMg Semaphore Enable When asserted LOW allows access to eight semaphores The three least significant bits of the address lines will determine which semaphore to write or read The l Og pin is used when writing to a semaphore Semaphores are requested by writing a 0 into the respective location INTL INTR Interrupt Flag INT is set when right port writes location FFE and is cleared when left port reads location FFE INTg is set when left port writes location FFF and is cleared when right port reads location FFF BUSY BUSYg Busy Flag M S Master or Slave Select Vcc Power GND Ground Table 2 Selection Guide 7C138 15 7C138 25 7C138 35 7C138 55 pescnption 7C139 45 7C139 25 7C139 35 7C139 55 Unit Maximum Access Time ns 15 25 35 55 ns M
3. lt Vcc 10 10 10 10 LA loz Output Leakage Current Output Disabled GND lt Vo lt Vcc 10 10 10 10 LA lec Operating Current Vcc Max Commercial 220 180 mA louT 0 mA Outputs Disabled ingusimal 130 leg4 Standby Current CE and CER gt Vi Commercial 60 40 mA Both Ports TTL Levels f fax Industrial 50 Isp2 Standby Current CE and CER gt Vin Commercial 130 110 mA One Port TTL Level f fmax Industrial 120 Isp3 Standby Current Both Ports Commercial 15 15 mA Both Ports CMOS Levels CE and CEg gt Vcg 0 2V Vin gt Vee 02V Industrial 30 or Vi lt 0 2V f ol Ispa Standby Current One Port _ Commercial 125 100 mA One Port CMOS Level CE or CER gt Vec 0 2V Industrial 115 Vin 2 Vec 0 2V or Vin lt 0 2V Active Port Outputs f fmax Notes 5 The Voltage on any input or I O pin cannot exceed the power pin during power up 6 Pulse width 20 ns T fmax T RC All inputs cycling at f 1 tac except output enable f 0 means no address or control lines change This applies only to inputs at CMOS level standby lspa Document 38 06037 Rev D Page 3 of 17 Feedback PERFORM Electrical Characteristics Over the Operating Range continued CY7C138 CY7C139 7C138 35 7C138 55 Parameter Description Test Conditions 7C139 35 7C139 55 Unit Min Max Min Max Vou Output HI
4. 0 Right port obtains semaphore Right port writes 1 to semaphore 1 1 No port accessing semaphore Left port writes 0 to semaphore 0 1 Left port obtains semaphore Left port writes 1 to semaphore 1 1 No port accessing semaphore Document 38 06037 Rev D Page 14 of 17 Feedback CY7C138 CY7C139 PERFORM Figure 15 Typical DC and AC Characteristics NORMALIZED SUPPLY CURRENT NORMALIZED SUPPLY CURRENT OUTPUT SOURCE CURRENT vs AMBIENT TEMPERATURE vs OUTPUT VOLTAGE 200 vs SUPPLY VOLTAGE 4 80 NORMALIZED Icc Isp NORMALIZED l cc Isp OUTPUT SOURCE CURRENT mA 0 10 20 30 40 5 0 4 0 4 5 5 0 5 5 6 0 SUPPLY VOLTAGE V AMBIENT TEMPERATURE C OUTPUT VOLTAGE V NORMALIZED ACCESS TIME NORMALIZED ACCESS TIME OUTPUT SINK CURRENT vs SUPPLY VOLTAGE vs AMBIENT TEMPERATURE vs OUTPUT VOLTAGE 0 NORMALIZED taa NORMALIZED taa OUTPUT SINK CURRENT mA 0 0 0 8 j 0 4 0 4 5 5 0 5 5 6 0 55 25 125 00 10 20 30 40 5 0 SUPPLY VOLTAGE V AMBIENT TEMPERATURE C OUTPUT VOLTAGE V ViN 5 0V TYPICAL POWER ON CURRENT TYPICAL ACCESS TIME CHANGE vs SUPPLY VOLTAGE vs OUTPUT LOADING NORMALIZED Icc vs CYCLE TIME 1 00 1 25 g 8 o gt i 048 D 1 0 N g N J Es d 0 50 c D X 9 a z075 0 25 0 0 0 0 50 0 10 20 30 40 50 O 200 400 600 800 1000 10 SUPPLY VOLTAGE V CAPACITANCE pF CYCLE FREQUENCY MHz Document 38 06037 Rev D Page 15 of 17 Feedback PERFORM Ord
5. EquivalenfLoad 1 9 VTH 1 4V ALL INPUT PULSES Switching Characteristics Over the Operating Rangel CY7C138 CY7C139 OUTPUT C 5pF T V R1 8930 R2 3470 c Three State Delay Load 3 7C138 15 7C138 25 7C138 35 7C138 55 Parameter Description 7C139 15 7C139 25 7C139 35 7C139 55 Unit Min Max Min Max Min Max Min Max READ CYCLE tre Read Cycle Time 15 25 35 55 ns tAA Address to Data Valid 15 25 35 55 ns toHA Output Hold From Address Change 3 3 3 3 ns tACE CE LOW to Data Valid 15 25 35 55 ns tpoE OE LOW to Data Valid 10 15 20 25 ns tizog 015121 OE Low to Low Z 3 3 3 3 ns tuzogl 0 11121 OE HIGH to High Z 10 15 20 25 ns tizcg 91121 ICE LOW to Low Z 3 3 3 3 ns tuzce 011121 CE HIGH to High Z 10 15 20 25 ns tp al CE LOW to Power Up 0 0 0 0 ns tepl CE HIGH to Power Down 15 25 35 55 ns WRITE CYCLE twe Write Cycle Time 15 25 35 55 ns tscE CE LOW to Write End 12 20 30 40 ns taw Address Set Up to Write End 12 20 30 40 ns tha Address Hold From Write End 2 2 ns tsa Address Set Up to Write Start 0 ns tpwe Write Pulse Width 12 20 25 30 ns tsp Data Set Up to Write End 10 15 15 20 ns Note 8 Tested initially and after any design or process changes that may affect these parameters Document 38 06037 Rev D Page 5 of 17 Feedback PERFORM Switching Characteristics Over the Operating Rangel continued
6. for port to port communication Two semaphore SEM control pins are used for allocating shared resources With the M S pin the CY7C138 9 can function as a master BUSY pins are outputs or as a slave BUSY pins are inputs The CY7C138 9 has an automatic power down feature controlled by CE Each port is provided with its own output enable control OE which enables data to be read from the device Functional Description Write Operation Data must be set up for a duration of tsp before the rising edge of R W in order to guarantee a valid write A write operation is controlled by either the OE pin see Write Cycle No 1 waveform or the R W pin see Write Cycle No 2 waveform Data can be written to the device tijzog after the OE is deasserted or tyzwe after the falling edge of R W Required inputs for non contention operations are summarized in Table 3 If a location is being written to by one port and the opposite port attempts to read that location a port to port flowthrough delay must be met before the data is read on the output otherwise the data read is not deterministic Data is valid on the port tppp after the data is presented on the other port Read Operation When reading the device the user must assert both the OE and CE pins Data is available tace after CE or tpog after OE is asserted If the user of the CY7C138 9 wishes to access a semaphore flag then the SEM pin must be asserted instead of the CE pin Interr
7. DATA OUT Figure 7 Write Cycle No 2 R W Three States Data I Os Either Port 22 24 25 tuzwE li zwE HIGH IMPEDANCE DATA OUT Notes 20 BUSY HIGH for the writing port 21 CE CEg LOW x 2r 22 The internal write time of the memory is defined by the overlap of CE or SEM LOW and R W LOW Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH The data input set up and hold timing should be referenced to the rising edge of the signal that terminates the write 23 If OE is LOW during a R W controlled write cycle the write pulse width must be the larger of tpyg or tuzwg tsp to allow the I O drivers to turn off and data to be placed on the bus for the required tgp If OE is HIGH during a R W controlled write cycle as in this example this requirement does not apply and the write pulse can be as short as the specified tpyg 24 R W must be HIGH during all address transitions Figure 8 Semaphore Read After Write Timing Either Sidel 6l Document 38 06037 Rev D Page 8 of 17 Feedback CY7C138 CY7C139 gt eL PERFORM ton gt Switching Waveforms continued taa aaz DXX van ADDRESSIK XCX vaim ADDRESS AKA XX y j lt _ taw vee DATA VALID Xy DATAour VALID tpoE NE I ELALLA L LLALLA ALL AE j WRITE CYCLE Figure 9 Timing Diagram of Semaphore Contention 27 28 29 AoL P
8. GH Voltage Voc Min lop 4 0 mA 2 4 24 V VoL Output LOW Voltage Vcc Min loj 4 0 mA 0 4 0 4 V Vin 2 2 2 2 V Vi Input LOW Voltage 0 8 0 8 V lix Input Leakage Current GND lt Vi lt Vcc 10 10 10 10 LA loz Output Leakage Current Output Disabled GND lt Vo lt Vcc 10 10 10 10 pA lec Operating Current Vcc Max Commercial 160 160 mA lout 0mA A Outputs Disabled Industrial 180 180 Isp4 Standby Current CE and CER gt Vin Commercial 30 30 mA Both Ports TTL Levels f fax Industrial 40 40 Ispo Standby Current CE and CEg gt Vi Commercial 100 100 mA One Port TTL Level f fax REA 110 T10 Isp3 Standby Current Both Ports Commercial 15 15 mA Both Ports CMOS Levels CE and CEg gt Vcc 0 2V Vin Vcc 0 2V Industrial 30 30 or Vix lt 0 2V f oU Isp4 Standby Current One Port Commercial 90 90 mA One Port CMOS Level CE or CER gt Voc 0 2V Vin Voc 0 2V or Industrial 100 100 Vin lt 0 2V Active Port Outputs f fmax Capacitance Parameter Description Test Conditions Max Unit Cin Input Capacitance TA 25 C f 1 MHz 10 pF Vec 5 0V Cour Output Capacitance 15 pF Document 38 06037 Rev D Page 4 of 17 Feedback CYPRESS OUTPUT C 30 pF T PERFORM Figure 2 AC Test Loads and Waveforms RTH 2500 OUTPUT V R1 8930 R2 3470 a Normal Load Load 1 OUTPUT ii C 30 pF I Load Load 2 C 30pF T b Th venin
9. aximum Operating Current Commercial 220 180 160 160 mA Maximum Standby Current for lsg4 Commercial 60 40 30 30 mA Notes 3 l Ogg on the CY7C139 4 Og on the CY7C139 Page 2 of 17 Document 38 06037 Rev D Feedback PERFORM CY7C138 CY7C139 Maximum Ratings Output Current into Outputs LOW 20 mA Static Discharge Voltage 22001V Exceeding maximum ratings may impair the useful life of the per MIL STD 883 Method 3015 device These user guidelines are not tested Latch Up Current 2200 mA Storage Temperature sssse 65 C to 150 C Ambient Temperature with Operating Range Power Applied eene 55 C to 125 C GNE Ambient F Supply Voltage to Ground Potential 0 5V to 7 0V 9 Temperature cc DC Voltage Applied to Outputs Commercial 0 C to 70 C 5V 10 in High Z eter 0 5V to 7 0V Industrial 40 C to 85 C BV 10 DC Input Voltage ool eee 0 5V to 7 0V Electrical Characteristics Over the Operating Range 7C138 15 7C138 25 Parameter Description Test Conditions 7C139 15 7C139 25 Unit Min Max Min Max Vou Output HIGH Voltage Vec Min lop 4 0 mA 24 2 4 V VoL Output LOW Voltage Vec Min Io 4 0 mA 0 4 0 4 V Vin 2 2 2 2 V Vi Input LOW Voltage 0 8 0 8 V lix Input Leakage Current GND lt Vi
10. ecified lo loy and 30 pF load capacitance 10 At any given temperature and voltage condition for any given device tyzce is less than tj zcg and tuzog is less than tj zog 11 Test conditions used are Load 3 12 This parameter is guaranteed but not tested 13 For information on part to part delay through RAM cells from writing port to reading port refer to Read Timing with Port to Port Delay waveform 14 Test conditions used are Load 2 15 tgpp is a calculated parameter and is the greater of twpp tpyyg actual or tppp tgp actual Document 38 06037 Rev D Page 6 of 17 Feedback CY7C138 CY7C139 PERFORM Switching Waveforms continued OE KG wwe 3 DATA OUT Aue DATA VALID lt tpp lcc Isp Figure 5 Read Timing with Port to Port Delay M S L 20 211 twc RWR owe tu DATA na CD tppp DATAnuR T VALID twDD Notes 16 R W is HIGH for read cycle uH 17 Device is continuously selected CE LOW and OE LOW This waveform cannot be used for semaphore reads 18 Address valid prior to or coincident with CE transition LOW 19 CE L SEM H when accessing RAM CE H SEM L when accessing semaphores Figure 6 Write Cycle No 1 OE Three States Data I Os Either Port 23 24 Document 38 06037 Rev D Page 7 of 17 Feedback PERFORM Switching Waveforms continued ADDRESS SEM OR CE RW DATA IN GE RXSSS GY HIGH IMPEDANCE
11. ed Pb Free Logo Added Pb Free parts to ordering information CY7C138 15JXC CY7C138 25JXC CY7C139 25JXC C 2623658 VKN PYRS 12 17 08 Added CY7C138 25JXI part Removed CY7C139 from the Ordering information table D 2672737 GNKK 03 12 2009 Updated title in the Document History table Sales Solutions and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices solution centers manufacturer s representatives and distributors To find the office closest to you visit us at cypress com sales Products PSoC Solutions PSoC psoc cypress com General psoc cypress com solutions Clocks amp Buffers clocks cypress com Low Power Low Voltage psoc cypress com low power Wireless wireless cypress com Precision Analog psoc cypress com precision analog Memories memory cypress com LCD Drive psoc cypress com cd drive Image Sensors image cypress com CAN 2 0b psoc cypress com can USB psoc cypress com usb Cypress Semiconductor Corporation 2005 2009 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an exp
12. ering Information 4K x8 Dual Port SRAM CY7C138 CY7C139 ER Ordering Code Enid Package Type Celene 15 CY7C138 15JC J81 68 Lead Plastic Leaded Chip Carrier Commercial CY7C138 15JXC J81 68 Lead Pb Free Plastic Leaded Chip Carrier 25 CY7C138 25JC J81 68 Lead Plastic Leaded Chip Carrier Commercial CY7C138 25JXC J81 68 Lead Pb Free Plastic Leaded Chip Carrier CY7C138 25Jl J81 68 Lead Plastic Leaded Chip Carrier Industrial CY7C138 25JXI J81 68 Lead Pb Free Plastic Leaded Chip Carrier 35 CY7C138 35JC J81 68 Lead Plastic Leaded Chip Carrier Commercial CY7C138 35Jl J81 68 Lead Plastic Leaded Chip Carrier Industrial 55 CY7C138 55JC J81 68 Lead Plastic Leaded Chip Carrier Commercial CY7C138 55JI J81 68 Lead Plastic Leaded Chip Carrier Industrial Package Diagram Document 38 06037 Rev D Figure 16 68 Pin Plastic Leaded Chip Carrier J81 51 85005 DIMENSIONS IN INCHES MIN MAX SEATING PLANE 0 990 0 930 0 026 0 032 0 020 MIN 0 200 51 85005 A Page 16 of 17 Feedback CY7C138 CY7C139 PERFORM Document History Page Document Title CY7C138 CY7C139 4K x 8 9 Dual Port Static RAM with Sem Int Busy Document Number 38 06037 Rev ECN No Ghee n Description of Change 110180 SZV 09 29 01 Change from Spec number 38 00536 to 38 06037 A 122287 RBI 12 27 02 Power up requirements added to Maximum Ratings Information B 393403 YIM See ECN Add
13. h sides should have a 1 written into them at initialization from both sides to assure that they are free when needed Page 13 of 17 Feedback PERFORM Table 3 Non Contending Read Write CY7C138 CY7C139 Inputs Outputs Operation CE R W OE SEM 1 09 7 8 H X X H High Z Power Down H H L L Data Out Read Data in Semaphore X X H X High Z I O Lines Disabled H I X L Data In Write to Semaphore L H L H Data Out Read L L X H Data In Write L X X L Illegal Condition Table 4 Interrupt Operation Example assumes BUSY BUSY p HIGH Left Port Right Port Function RW CE OE Aga INT RW CE OE Aga INT Set Left INT X X X X L L L X FFE X Reset Left INT X L L FFE H X X X X X Set Right INT L L X FFF X X X X X L Reset Right INT X X X X X X L L FFF H Table 5 Semaphore Operation Example Function l Og 7 g Left 1 O9 7 3 Right Status No action 1 1 Semaphore free Left port writes semaphore 0 1 Left port obtains semaphore Right port writes 0 to semaphore 0 1 Right side is denied access Left port writes 1 to semaphore 1 0 Right port is granted access to semaphore Left port writes 0 to semaphore 1 0 No change Left port is denied access Right port writes 1 to semaphore 0 1 Left port obtains semaphore Left port writes 1 to semaphore 1 1 No port accessing semaphore address Right port writes 0 to semaphore 1
14. n H Wy Q YPRESS PERFORM Features m True Dual Ported memory cells that enable simultaneous reads of the same memory location m 4K x 8 organization CY7C138 m 4K x 9 organization CY7C139 m 0 65 micron CMOS for optimum speed and power m High speed access 15 ns m Low operating power Icc 160 mA max m Fully asynchronous operation m Automatic power down m TTL compatible m Expandable data bus to 32 36 bits or more using Master Slave chip select when using more than one device m On chip arbitration logic m Semaphores included to permit software handshaking between ports m INT flag for port to port communication m Available in 68 pin PLCC m Pb free packages available Logic Block Diagram G C139 rO8L VOL BUSY Ll 2 AL a L1 L _SEML INTL 7 vo yoo C CN TROL ADDRESS DECODER CY7C138 CY7C139 4K x 8 9 Dual Port Static RAM with Sem Int Busy Functional Description The CY7C138 and CY7C139 are high speed CMOS 4K x 8 and 4K x 9 dual port static RAMs Various arbitration schemes are included on the CY7C138 9 to handle situations when multiple processors access the same piece of data Two ports are provided permitting independent asynchronous access for reads and writes to any location in memory The CY7C138 9 can be used as a standalone 8 9 bit dual port static RAM or multiple devices can be combined to function as a 16 18 bit or wider master slave dual por
15. oL MATCH RW SEM tsps AoR AoR MATCH R Wp SEMR Notes 25 Data I O pins enter high impedance when OE is held LOW during write 26 CE HIGH for the duration of the above timing both write and read cycle Figure 10 Timing Diagram of Read with BUSY M S HIGH Page 9 of 17 Feedback Document 38 06037 Rev D CYPRESS PERFORM CY7C138 CY7C139 Switching Waveforms continued ADDRESSg R Wg DATA INR tps ADDRESS BUSY DATAourL UJ c n lt Notes twc MATCH tup CO owe D MATCH I tBLA lus H tBDD 1 toop twDD Figure 11 Write Timing with Busy Input M S LOW tpwe lt twe twH 27 Oo l Og LOW request semaphore CEg CE HIGH 28 Semaphores are reset available to both ports at cycle start 29 If tsps is violated the semaphore will definitely be obtained by one side or the other but there is no guarantee which side will control the semaphore Document 38 06037 Rev D Figure 12 Busy Timing Diagram No 1 CE Arbitration 0 Page 10 of 17 Feedback PERFORM Switching Waveforms continued CE Valid First ADDRESS R ADDRESS MATCH CE CER BUSY CEg Valid First ADDRESS R ADDRESS MATCH CER CEL BUSY Figure 13 Busy Timing Diagram No 2 Address Arbitration Left Address Valid First trc or twe ADDRESS ADDRESS MATCH ADDRESS MISMATCH ADDRESSg BUSY Righ
16. ress written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Any Source Code software and or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign United States copyright laws and international treaty provisions Cypress hereby grants to licensee a personal non exclusive non transferable license to copy use modify create derivative works of and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement Any reproduction modification translation compilation or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE C
17. slave devices must be delayed until after the BUSY input has settled Otherwise the slave chip may begin a write cycle during a contention situation When presented as a HIGH input the M S pin allows the device to be used as a master and therefore the BUSY line is an output BUSY can then be used to send the arbitration outcome to a slave Semaphore Operation The CY7C138 9 provides eight semaphore latches which are separate from the dual port memory locations Semaphores are used to reserve resources that are shared between the two ports The state of the semaphore indicates that a resource is in use For example if the left port wants to request a given resource it sets a latch by writing a zero to a semaphore location The left port then verifies its success in setting the latch by reading it After writing to the semaphore SEM or OE must be deasserted for tsop before attempting to read the semaphore The semaphore value is available tswrp tpog after the rising edge of the semaphore write If the left port was successful reads a zero it assumes control over the shared resource otherwise reads a one it assumes the right port has control and continues to poll the semaphore When the right side has relin quished control of the semaphore by writing a one the left side succeeds in gaining control of the a semaphore If the left side no longer requires the semaphore a 1 is written to cancel its request Semaphores are acce
18. ssed by asserting SEM LOW The SEM pin functions as a chip enable for the semaphore latches CE must remain HIGH during SEM LOW Ag represents the semaphore address OE and R W are used in the same manner as a normal memory access When writing or reading a semaphore the other address pins have no effect When writing to the semaphore only l Og is used If a zero is written to the left port of an unused semaphore a one will appear at the same semaphore address on the right port That semaphore can now only be modified by the side showing zero the left port in this case If the left port now relinquishes control by writing a one to the semaphore the semaphore is set to 1 for both sides However if the right port had requested the semaphore written a zero while the left port had control the right port immediately owns the semaphore after the left port releases it Table 5 shows sample semaphore operations When reading a semaphore all eight or nine data lines output the semaphore value The read value is latched in an output register to prevent the semaphore from changing state during a write from the other port If both ports attempt to access the semaphore within tsps of each other the semaphore is definitely obtained by one side orthe other butthere is no guarantee which side controls the semaphore Initialization of the semaphore is not automatic and must be reset during initialization program at power up All semaphores on bot
19. t Address Valid First tec or twc ADDRESSR ADDRESS MATCH ADDRESS MISMATCH tps ADDRESS BUSY Note 30 If tps is violated the busy signal will be asserted on one side or the other but there is no guarantee on which side BUSY will be asserted Z CYPRESS CY7C138 CY7C139 Document 38 06037 Rev D Page 11 of 17 Feedback YPRESO CY7C138 CY7C139 PERFORM Switching Waveforms continued Figure 14 Interrupt Timing Diagrams Left Side Sets INTg icones OX gt tiNgd 32 Right Side Clears INTg ADDRESS MOX OXOXX XXX XXX GO CER tre READ FFF tinr 32 vite ZZ ZR Er AAA INTR Right Side Sets INT twc ADDRESSg XXX C were OK XX INT tig 21 Left Side Clears INT ADDRESS XX XX XXX XXX trc READ FFE tinr 82 RWL M V4 o AASS INT Notes 31 tya depends on which enable pin CE or R W is deasserted first 32 ting OF tiyr depends on which enable pin CE or R W is asserted last Document 38 06037 Rev D Page 12 of 17 Feedback PERFORM Architecture The CY7C138 9 consists of an array of 4K words of 8 9 bits each of dual port RAM cells I O and address lines and control signals CE OE R W These control pins permit independent access for reads or writes to any location in memory To handle simulta neous writes and reads to the same location a BUSY pin is provided on each port Two interrupt INT pins can be used
20. t static RAM An M S pin is provided for implementing 16 18 bit or wider memory applications without the need for separate master and slave devices or additional discrete logic Application areas include interprocessor multipro cessor designs communications status buffering and dual port video graphics memory Each port has independent control pins chip enable CE read or write enable R W and output enable OE Two flags are provided on each port BUSY and INT BUSY signals that the port is trying to access the same location currently being accessed by the other port The interrupt flag INT permits communication between ports or systems by means of a mail box The semaphores are used to pass a flag or token from one port to the other to indicate that a shared resource is in use The semaphore logic is comprised of eight shared latches Only one side can control the latch semaphore at any time Control of a semaphore indicates that a shared resource is in use An automatic power down feature is controlled independently on each port by a chip enable CE pin or SEM pin The CY7C138 and CY7C139 are available in a 68 pin PLCC a RAM Ge p OER gt Ueoncret 39 o Z lt A 2o a r um voor Bu svg 4 AMR MEMORY z ARR AY AR INTERRUPT SEMAPH OR E ARBITR ATI ON Notes 1 BUSY is an output in master mode and an input in slave mode 2 Interrupt push pull output and requires no pull up resistor
21. upts The interrupt flag INT permits communications between ports When the left port writes to location FFF the right port s interrupt flag INTg is set This flag is cleared when the right port reads that same location Setting the left port s interrupt flag INT is accomplished when the right port writes to location FFE This flag is cleared when the left port reads location FFE The message at FFF or FFE is user defined See Table 4 for input requirements for INT INTp and INT are push pull outputs and do not require pull up resistors to operate BUSY and BUSYg in master mode are push pull outputs and do not require pull up resistors to operate Busy The CY7C138 9 provides on chip arbitration to alleviate simulta neous memory location access contention If both ports CEs are asserted and an address match occurs within tps of each other the Busy logic determines which port has access If tps is violated one port definitely gains permission to the location but it is not guaranteed which one BUSY will be asserted tg A after an address match or tg c after CE is taken LOW Document 38 06037 Rev D CY7C138 CY7C139 Master Slave A M S pin is provided in order to expand the word width by config uring the device as either a master or a slave The BUSY output of the master is connected to the BUSY input of the slave This enables the device to interface to a master device with no external components Writing of
22. ypress reserves the right to make changes without further notice to the materials described herein Cypress does not assume any liability arising out of the application or use of any product or circuit described herein Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress product in a life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Use may be limited by and subject to the applicable Cypress software license agreement Document 38 06037 Rev D Revised March 12 2009 Page 17 of 17 All products and company names mentioned in this document may be the trademarks of their respective holders Feedback
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