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Cypress CY7C1361C User's Manual

1. CY7C1361C 256K x 36 1 2 3 4 5 6 7 8 9 10 11 NC 28M CE BWg CE BWE ADSC ADV A NC B NCA44M A CE BWp BW CLK GW OE ADSP A NC 576M C NC Vppa Vss Vss Vss Vss Vss Vppa NC 1G DQPg D VDDQ Vpp Vss Vss Vss VDD VDDQ DQg DQc DQc Vppa Vpp Vss Vss Vss Vpp DQg DQg F DQc VDDQ Vpp Vss Vss Vss VDD DQc VDDQ Vss Vss Vss Vpp DQg DQg H NC Vss NC Vss Vss Vss Vo NC NC ZZ J DQp DQp Vppo Vpp Vss Vss Vss Vpp VDDQ K DQp DQp Vppo Vpp Vss Vss Vss Vpp VDDQ L DQp DQp VDDQ VDD Vss Vss Vss VDD VDDQ DQp DQp Vss Vss Vss Vpp VDDQ DQA N NC Vba Vss NC NCA8M NC Ves NC DOR P NC NC 72M A A TDI A1 TDO A A A A R MODE NC 36M A A TMS A0 TCK A A A A CY7C1363C 512K x 18 1 2 3 4 5 6 7 8 9 10 11 NC 28M A BW NC BWE ADSC ADV A A B NC 44M CE NC BWA CLK GW OE ADSP NC 576M C NC NO Wong Was Vss Vss Vss Vss Vopa DOP D NC DQg Vss Vss Vss NC DQA E NC DQg Vss Vss Vss Vpp NC F NC DQg Vpp Vss Vss Vss Vpp NC DQa G NC DQg Vss Vss Vss Vpp NC H Vss Vss NC Vpop Vss Vss Vss Wan NC NC ZZ J NC Vpp Vs
2. 55 to 125 C Ambient Supply Voltage on Relative to GND 0 5V to 4 6V Range Temperature Vpp Supply Voltage on Vppq Relative to GND 0 5V to Commercial 0 C to 70 3 3V 5 10 2 5V 5 DC Voltage Applied to Outputs Industrial 40 C to 85 C Vo Yap iN tri Stale oin etes 0 5V to 0 5V Automotive 40 C to 125 C DC Input 0 5V to Vpp 0 5V Electrical Characteristics Over the Operating Range 3 14 Parameter Description Test Conditions Min Max Unit Vpp Power Supply Voltage 3 135 3 6 V VDDQ Supply Voltage for 3 3V I O 3 135 Vpp V for 2 5V 2 375 2 625 V Vou Output HIGH Voltage for 3 3V I O lop 4 0 mA 2 4 V ffor25Vl O lgy2 1 00mA 20 VoL Output LOW Voltage for 3 3V I O loj 8 0 mA 0 4 V for 2 5V I O lg 1 0 mA 0 4 V InputHIGH Voltage ftor33VU O Voos V for 2 5V I O 1 7 0 3V V Vit Input LOW Voltage 3 3V 0 3 0 8 V for 2 5V 0 3 0 7 lx Input Leakage Current GND lt VDDQ 5 5 except ZZ MODE Input Current of MODE Input Vss 30 Input Vpp 5 Input Current of ZZ Input Vss 5 Input Vpp 30 loz Output Leakage Current GND lt lt Output Disabled 5 5 155 Vpp Operating Supply Max lour 0 mA 7 5 ns cycl
3. PN BYTE gt WRITE REGISTER tU d WRITE REGISTER 7 DQa DQPA BYTE BWa HHN BYTE D 5 gt WRITE REGISTER BWE WRITE REGISTER ee aw INPUT REGISTERS REGISTER FEN A D D D 47 SLEEP CONTROL Logic Block Diagram CY7C1363C 512K x 18 ADDRESS 0 REGISTER A A 1 0 MODE a sce CLK COUNTER AND LOGIC cir Q0 9 is 791 i DQs DQPs ps DQ amp DQPe WRITE DRIVER BWe WRITE REGISTER MEMORY sense A OUTPUT 005 ARRAY AMPS BUFFERS DQPa e DQa DQPa DQPs DQa DQPA gt WRITE DRIVER BWa WRITE REGISTER gt i BWE a AN INPUT REGISTERS s dv REGISTER CB aH 7 SLEEP CONTROL Document 38 05541 Rev F Page 2 of 31 Feedback CY7C1361C CY7C1363C CE CYPRESS PERFORM Pin Configurations 100 Pin TQFP Pinout 3 Chip Enables A version 22 507 rio of Sur ase ew BOB 2 286286 lt lt lt lt lt lt FSSSSSSSSSSISSSSSS
4. 20 J10 56 2 DQc 20 J10 56 2 21 K10 DQA 57 D2 21 K10 DQA 57 D2 22 10 DQa 58 G1 DQc 22 L10 58 Internal Internal 23 M10 DQA 59 F1 DQc 23 M10 59 Internal Internal 24 J11 60 E1 DQc 24 Internal Internal 60 Internal Internal 25 K11 DQa 61 D1 DQc 25 Internal Internal 61 Internal Internal 26 L11 62 C1 DQPc 26 Internal Internal 62 Internal Internal 27 M11 DQA 63 B2 A 27 Internal Internal 63 B2 A 28 N11 DQPA 64 A2 A 28 Internal Internal 64 A2 A 29 R1 A 65 A3 CE 29 R11 A 65 A3 CE 30 R10 A 66 30 R10 A 66 B3 31 P10 A 67 B4 BWp 31 P10 A 67 Internal Internal 32 R9 A 68 A4 BWc 32 R9 A 68 Internal Internal 33 P9 A 69 A5 33 9 69 4 34 R8 A 70 B5 34 R8 A 70 B5 BWa 35 P8 A 71 35 8 71 CE3 36 P11 A 36 P11 A Document 38 05541 Rev F Page 18 of 31 Feedback CY7C1361C CYPRESS CY7C1363C PERFORM Maximum Ratings Current into Outputs 20 mA Above which the useful life may be impaired For user guide T N co lines not tested Storage Temperature 65C to 150 C Latch up Current esee 2200 mA Ambient Temperature with Operating Range Power
5. PACKAGE CODE l SEATING PLANE 8 51 85180 A 0 35 0 06 1486 is a trademark and Intel and Pentium are registered trademarks of Intel Corporation PowerPC is a trademark of IBM Corporation All product and company names mentioned in this document are the trademarks of their respective holders Document 38 05541 Rev F Page 30 of 31 Cypress Semiconductor Corporation 2006 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Feedback e s CY7C1361C F CYPRESS CY7CI363C PERFORM Document History Page Document Title CY7
6. These instructions are not implemented but are reserved for future use Do not use these instructions Test Mode Select S Test Data In TDI Test Data Out TDO XC 9C OC DON T UNDEFINED TAP AC Switching Characteristics Over the Operating Rangel 1 Parameter Parameter Min Max Unit Clock trcvc TCK Clock Cycle Time 50 ns TCK Clock Frequency 20 MHz tty TCK Clock HIGH Time 20 ns tr TCK Clock LOW Time 20 ns Output Times trpov TCK Clock LOW to TDO Valid 10 ns trpox TCK Clock LOW to TDO Invalid 0 ns Set up Times truss TMS Set Up to TCK Clock Rise 5 ns trois TDI Set Up to TCK Clock Rise 5 ns tes Capture Set Up to TCK Rise 5 ns Hold Times TMS Hold after Clock Rise 5 ns TDIH TDI Hold after Clock Rise 5 ns Capture Hold after Clock Rise 5 ns Notes 9 tcs and toy refer to the setup and hold time requirements of latching data from the boundary scan register 10 Test conditions are specified using the load TAP AC test conditions tg te 1 ns Document 38 05541 Rev F Page 14 of 31 Feedback CY7C1361C CYPRESS CY7C1363C PERFORM 3 3V TAP AC Test Conditions 2 5V TAP AC Test Conditions
7. Document 38 05541 Rev F Page 17 of 31 Feedback CY7C1361C CYPRESS CY7C1363C 165 Ball FBGA Boundary Scan Order CY7C1361C 256K x 36 CY7C1363C 512K x 18 Signal Signal Signal Signal Bit ball ID Name Bit ball ID Name Bit ball ID Name Bit ball ID Name 1 B6 CLK 37 R6 1 B6 CLK 37 R6 AO 2 B7 GW 38 P6 A1 2 B7 GW 38 P6 A1 3 A7 BWE 39 R4 A 3 A7 BWE 39 R4 A 4 B8 OE 40 P4 A 4 B8 OE 40 P4 A 5 A8 ADSC 41 R3 A 5 A8 ADSC 41 R3 A 6 B9 ADSP 42 P3 A 6 B9 ADSP 42 P3 A 7 9 ADV 43 R1 MODE 7 A9 ADV 43 R1 MODE 8 B10 A 44 N1 DQPp 8 B10 A 44 Internal Internal 9 A10 A 45 L2 DQp 9 A10 A 45 Internal Internal 10 C11 DQPg 46 K2 DQp 10 A11 A 46 Internal Internal 11 E10 DQg 47 J2 DQp 11 Internal Internal 47 Internal Interna 12 F10 48 2 DQp 12 Internal Internal 48 N1 13 G10 49 1 DQp 13 Internal Internal 49 M1 14 010 DQg 50 L1 DQp 14 C11 DOP 50 L1 DQg 15 Dii 51 K1 DQp 15 D11 DQa 51 K1 16 E11 52 J1 DQp 16 E11 DQ 52 J1 DQg 17 F11 DQg 53 Internal Internal 17 F11 53 Internal Interna 18 G11 54 G2 DQc 18 G11 54 G2 19 H11 ZZ 55 F2 DQc 19 H11 ZZ 55 F2
8. Ls gt 4 __ T W CY7C1361C CY7C1363C YPRESS PERFORM 9 Mbit 256K x 36 512 x 18 Flow Through SRAM Features Supports 100 133 MHz bus operations Supports 100 MHz bus operations Automotive 256K x 36 512K x 18 common I O 3 3V 5 and 10 core power supply Vpp 2 5V or 3 3V I O power supply Vppq Fast clock to output times 6 5 ns 133 MHz version Provide high performance 2 1 1 1 access rate User selectable burst counter supporting Intel Pentium interleaved or linear burst sequences Separate processor and controller address strobes Synchronous self timed write Asynchronous output enable Available in lead free 100 Pin TQFP package lead free and non lead free 119 Ball BGA package and 165 Ball FBGA package TQFP Available with 3 Chip Enable and 2 Chip Enable IEEE 1149 1 JTAG Compatible Boundary Scan 22 Sleep Mode option Selection Guide Functional Description The CY7C1361C CY7C1363C is a 3 3V 256K x 36 512K x 18 Synchronous Flow through SRAMs respectively designed to interface with high speed microprocessors with minimum glue logic Maximum access delay from clock rise is 6 5 ns 133 MHz version A 2 bit on chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access All synchronous inputs are gated by registers controlled by a positive edge triggered Clock Input CLK
9. UUUUUUUUU 99889 lt lt lt lt lt lt lt lt E Document 38 05541 Rev F Page 3 of 31 Feedback CY7C1361C CE CYPRESS CY7C1363C PERFORM Pin Configurations continued 100 Pin TQFP Pinout 2 Chip Enables AJ Version Be a lt 915 euo lt lt E lt 238 lt lt TETT T 858 LET IT 0000 _ nanmnunuunuunmnurnrnunumuumunurn e CFR RISUS IUE ae DQPcLC 1 80 DQPg NC 80 2 79 NC Co 79 78 F3 NC 43 78 m NC 4 77 Vppa Vooo L d4 77 Vppa ssa 5 76 F3 5 76 Vsgq DQc 6 75 fo NC L dg 75 p NC DQc H 7 74 NC 7 74 FA 8 73 E3 8 73 E DO DQc L 4 9 72 1 49 72 1 10 71 Vssa 71 11 70 F4 L3 11 70 12 69 DQ 212 DO 13 68 13 68 3 DO dris 14 67 Vss Vgg DNU C 144 67 Vss DD 15 66 NC 4 Y7C1 r1 7 1361 CY SIE V
10. 2 OE HIGH to Output High z 18 19 3 5 3 5 ns Set up Times tas Address Set up Before CLK Rise 1 5 1 5 ns taps ADSP ADSC Set up Before CLK Rise 1 5 1 5 ns tapvs ADV Set up Before CLK Rise 1 5 1 5 ns twes GW BWE Set up Before CLK Rise 1 5 1 5 ns tps Data Input Set up Before CLK Rise 1 5 1 5 ns tces Chip Enable Set up 1 5 1 5 ns Hold Times Address Hold After CLK Rise 0 5 0 5 ns tADH ADSP ADSC Hold After CLK Rise 0 5 0 5 ns twEH GW BWE Hold After CLK Rise 0 5 0 5 ns tADVH ADV Hold After CLK Rise 0 5 0 5 ns tDH Data Input Hold After CLK Rise 0 5 0 5 ns Chip Enable Hold After CLK Rise 0 5 0 5 ns Notes 16 This part has a voltage regulator internally tpgwer is the time that the power needs to be supplied above Vpp minimum initially before a read or write operation can be initiated 17 7 and are specified with AC test conditions shown part b of AC Test Loads Transition is measured 200 mV from steady state voltage 18 At any given voltage and temperature togpz is less than tog and is less than to eliminate bus contention between SRAMs when sharing the same data bus These specifications do not imply a bus contention condition but reflect parameters guaranteed over worst case user conditions Device is designed to achieve High Z prior to Low Z under the same system conditions 19 This parameter is sampled and not 100 tested 20 Timing re
11. the TAP is reset internally to ensure that TDO comes up in a High Z state TAP Registers Registers are connected between the TDI and TDO balls and allow data to be scanned into and out of the SRAM test circuitry Only one register can be selected at a time through the instruction register Data is serially loaded into the TDI ball on the rising edge of TCK Data is output on the TDO ball on the falling edge of TCK Instruction Register Three bit instructions can be serially loaded into the instruction register This register is loaded when it is placed between the Page 12 of 31 Feedback cypress CYPRESS PERFORM TDI and TDO balls as shown in the Tap Controller Block Diagram Upon power up the instruction register is loaded with the IDCODE instruction It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section When the TAP controller is in the Capture IR state the two least significant bits are loaded with a binary 01 pattern to allow for fault isolation of the board level serial test data path Bypass Register To save time when serially shifting data through registers it is sometimes advantageous to skip certain chips The bypass register is a single bit register that can be placed between the TDI and TDO balls This allows data to be shifted through the SRAM with minimal delay The bypass register is set LOW Vss when the BYPASS i
12. High Z state IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO This operation does not affect SRAM operations SAMPLE Z 010 Captures I O ring contents Places the boundary scan register between TDI Forces all SRAM output drivers to a High Z state RESERVED 011 Do Not Use This instruction is reserved for future use SAMPLE PRELOAD 100 Captures I O ring contents Places the boundary scan register between TDI and TDO Does not affect SRAM operation RESERVED 101 Do Not Use This instruction is reserved for future use RESERVED 110 Do Not Use This instruction is reserved for future use BYPASS 111 Places the bypass register between TDI and TDO This operation does not affect SRAM operations Document 38 05541 Rev F Page 16 of 31 Feedback CY7C1361C CY7C1363C 119 Ball BGA Boundary Scan Order CY7C1361C 256K x 36 CY7C1363C 512K x 18 Signal Signal Signal Signal Bit ball ID Name Bit ballID Name Bit ball ID Name Bit ball ID Name 1 K4 CLK 37 P4 AO 1 K4 CLK 37 P4 AO 2 H4 GW 38 N4 A1 2 H4 GW 38 N4 A1 3 M4 BWE 39 R6 A 3 M4 BWE 39 R6 A 4 F4 OE 40 T5 A 4 F4 OE 40 T5 A 5 B4 ADSC 41 T3 A 5 B4 ADSC 41 T3 A 6 A4 ADSP 42 R2 A 6 A4 ADSP 42 R2 A 7 G4 ADV 43 R3 MODE 7 G4 ADV 43 R3 MODE 8 C3 A 44 P2 DQPp 8 C3 A 44 Inte
13. Input pulse levels Vgg to 3 3V Input pulse Vgg to 2 5V Input rise and fall 1ns Input rise and fall time 1ns Input timing reference 1 5V Input timing reference 1 25V Output reference 5 1 5V Output reference levels 1 25V Test load termination supply voltage 1 5V Test load termination supply voltage 1 25V 3 3V TAP AC Output Load Equivalent 2 5V TAP AC Output Load Equivalent 1 5V 1 25V 50Q 500 TDO TDO Zo 502 20pF Zo 502 20pF TAP DC Electrical Characteristics And Operating Conditions 0 C lt lt 70 C VDD 3 3V 0 165V unless otherwise noted Parameter Description Description Conditions Min Max Unit Vout Output HIGH Voltage 4 0 mA 3 3V 2 4 1 0 mA 2 5V 2 0 V Output HIGH Voltage 7100 pA Vppo 3 3V 2 9 2 5V 2 1 V Vout Output LOW Voltage lo 8 0 mA Vppo 3 3V 0 4 lo 8 0 mA Vppo 2 5V 0 4 V Voi Output LOW Voltage lo 100 pA Vppo 3 3V 0 2 V 2 5V 0 2 V Vin Input HIGH Voltage 3 3V 2 0 0 3 V 2 5V 17 0 3 V ViL Input
14. The synchronous inputs include all addresses all data inputs address pipelining Chip Enable CE depth expansion Chip Enables and 2 Burst Control inputs ADSC ADSP and ADV Write Enables BW and BWE and Global Write GW Asynchronous inputs include the Output Enable OE and the ZZ pin The CY7C1361C CY7C1363C allows either interleaved or linear burst sequences selected by the MODE input pin A HIGH selects an interleaved burst sequence while a LOW selects a linear burst sequence Burst accesses can be initiated with the Processor Address Strobe ADSP or the cache Controller Address Strobe ADSC inputs Address advancement is controlled by the Address Advancement ADV input Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor ADSP or Address Strobe Controller ADSC are active Subsequent burst addresses can be internally generated as controlled by the Advance pin ADV The CY7C1361C CY7C1363C operates from a 3 3V core power supply while all outputs may operate with either a 2 5 or 3 3V supply All inputs and outputs are JEDEC standard JESD8 5 compatible 133 MHz 100 MHz Unit Maximum Access Time 6 5 8 5 ns Maximum Operating Current 250 180 mA Maximum CMOS Standby Current 40 40 mA Automotive 60 mA Notes 1 For best practices recommendations please refer to the Cypress application note Sy
15. UU SEATING PLANE d o in c 60 0 10 Document 38 05541 Rev F 7 62 B 4 14 00 0 20 D 0 15 4X 51 85115 02592 _ TA VA F gt 1 27 Page 29 of 31 Feedback gt Cd CY7C1361C PE CYPRESS CY7C1363C PERFORM Package Diagrams continued 165 Ball FBGA 13 x 15 x 1 4 mm 51 85180 BOTTOM VIEW PINTCORNER TOP VIEW 4 2005MC PIN 1 CORNER V go25MC B 00 50 7906 165X 30 14 1 2 3 4 5 6 7 8 9 10 11 11 10 9 8 7 6 5 4 3 2 1 Ma B 90000 Ooo 0 0 0 B 0G O CO c 8 D Rai Oo OQ OO 0 OO OO D E F Cx O Ove O0 0 F G O0 00 O Oo G o o 5 S 3 G C 9 H E d J OO Q 0 OO OO 0 0 OQ J n 000000700000 L S Q Q Q O Q X GO L 8 M us Oo QOO Oo o Oo M N N P O Oo 0 R 6 O O O O Q 000 O0 6 R 1 00 5 00 10 00 13 002010 4 B e 1300 010 au A 0 15 4x o 8 x NOTES e S _ S 8 5 aa SOLDER PAD TYPE NON SOLDER MASK DEFINED NSMD N PACKAGE WEIGHT 0 475g q JEDEC REFERENCE MO 216 DESIGN 4 6C ee
16. not available on TQFP packages TCK JTAG Clock input to the JTAG circuitry If the JTAG feature is not being utilized this pin must Clock be connected to Vgs This pin is not available on TQFP packages NC No Connects Not internally connected to the die 18M 36M 72M 144M 288M 576M and 1G are address expansion pins and are not internally connected to the die Vss DNU Ground DNU This pin can be connected to Ground or should be left floating Page 8 of 31 Feedback H CYPRESS PERFORM Functional Overview All synchronous inputs pass through input registers controlled by the rising edge of the clock Maximum access delay from the clock rise tcpy is 6 5 ns 133 MHz device The CY7C1361C CY7C1363C supports secondary cache in Systems utilizing either a linear or interleaved burst sequence The interleaved burst order supports Pentium and i486 processors The linear burst sequence is suited for processors that utilize a linear burst sequence The burst order is user selectable and is determined by sampling the MODE input Accesses can be initiated with either the Processor Address Strobe ADSP or the Controller Address Strobe ADSC Address advancement through the burst sequence is controlled by the ADV input A two bit on chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access Byte write operations are qua
17. unconnected if the TAP is not used The ball is pulled up internally resulting in a logic HIGH level Test Data In TDI The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register TDI is internally pulled up and can be unconnected if the TAP is unused in an application TDI is connected to the most signif icant bit MSB of any register See Tap Controller Block Diagram Test Data Out TDO The TDO output ball is used to serially clock data out from the registers The output is active depending upon the current state of the TAP state machine The output changes on the falling edge of TCK TDO is connected to the least significant bit LSB of any register See Tap Controller State Diagram TAP Controller Block Diagram rR 0 Bypass Register 2 1 0 Selection de Instruction Register Circuitry Selection 313029 21 0 Ciruitry TDI TDO Identification Register Boundary Scan Register TMS TAP CONTROLLER Performing a TAP Reset A RESET is performed by forcing TMS HIGH Vpp for five rising edges of TCK This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating At power up
18. 77 apvs Data in 0 High Z D A2 ves cmm Xo 243 XX D A3 Woms oe Ea L BURST READ Single WRITE BURST WRITE le Extended BURST WRITE _ von care UNDEFINED Data Out Q Note 23 Full width write can be initiated by either GW LOW or by GW HIGH BWE LOW and BWy LOW Document 38 05541 Rev F Page 23 of 31 Feedback CY7C1361C v ae CYPRESS CY7C1363C PERFORM Timing Diagrams continued Read Write Cycle 22 24 25 WU UU Xu ub OOV eee eee BWE BWx tces gt gt a ZDA LLL ULLA 0817 Data In 0 High Z t D A3 D A5 D A6 m tcov Data Out 9 amp oan KY 062 ll Q4 E Back to Back READS Single WRITE _ Back to Back EM BURST READ WRITEs R UNDEFINED Notes es 24 The data bus Q remains in high Z following a WRITE cycle unless a new read access is initiated by ADSP or ADSC 25 GW is HIGH Document 38 05541 Rev F Page 24 of 31 Feedback dy CY7C1361C _ Timing Diagrams continued ZZ Mode Timing 27 ALL INPUTS DESELECT or READ Only except ZZ D
19. 8 Function CY7C1363C U m U Read Read Write Byte DQ and Write Byte B and Write All Bytes Write All Bytes 0 Note 8 Table only lists a partial listing of the byte write combinations Any Combination of BW is valid Appropriate write will be done based on which byte write is active Document 38 05541 Rev F Page 11 of 31 Feedback CYPRESS CYPRESS PERFORM IEEE 1149 1 Serial Boundary Scan JTAG The CY7C1361C CY7C1363C incorporates a serial boundary scan test access port TAP in the BGA package only The TQFP package does not offer this functionality This part operates in accordance with IEEE Standard 1149 1 1900 but doesn t have the set of functions required for full 1149 1 compliance These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM Note the TAP controller functions in a manner that does not conflict with the operation of other devices using 1149 1 fully compliant TAPs The TAP operates using JEDEC standard 3 3V or 2 5V I O logic levels The CY7C1361C CY7C1363C contains a TAP controller instruction register boundary scan register bypass register and ID register Disabling the JTAG Feature It is possible to operate the SRAM
20. AND OFF q dE Ld 0 05 MIN NOTE H 0 15 MAX GAUGE PLANE 1 STD REF MS 026 2 BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION END FLASH R38 MIN MOLD PROTRUSION END FLASH SHALL NOT EXCEED 0 0098 in 0 25 mm PER SIDE 0 7 C 20 MAX BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 3 DIMENSIONS IN MILLIMETERS 0 60 0 15 Uer p 020MIN 51 85050 B 1 00 REF DETAIL Document 38 05541 Rev F Page 28 of 31 Feedback Package Diagrams continued 119 Ball BGA 14 x 22 x 2 4 mm 51 85115 60 05 M e CY7C1361C CY7C1363C 60 25 0 75 0 15 119X 20 32 T 600o00 GE GE cies C a y 2000000 10 16 OO OO OO Lor OOO F 2 ORD one OO OO 0 SE gt em 22 00 0 20 A1 CORNER 1 00 3X REF 1234567 B G H J H 4 a M El L M N P R T uhh ME 12 00 _ d _ S 30 TYP E 2 t x 13 I 1 C XU
21. C1361C CY7C1363C 9 Mbit 256K x 36 512K x 18 Flow Through SRAM Document Number 38 05541 Orig of REV ECN NO Issue Date Change Description of Change zi 241690 See ECN RKF New data sheet A 278969 See ECN RKF Changed Boundary Scan order to match the B rev of these devices B 332059 See ECN PCI Removed 117 MHz Speed Bin Address expansion pins balls in the pinouts for all packages are modified as per JEDEC standard Added Address Expansion pins in the Pin Definitions Table Changed Device Width 23 18 for 119 BGA from 000001 to 101001 Added separate row for 165 FBGA Device Width 23 18 Changed Ippzz from 35 mA to 50 mA Changed Isp and 15 from 40 mA to 110 and 100 mA respectively Modified VoL test conditions Corrected 5 Test Condition from Vin gt Vpp 0 3V or Viy lt 0 3V to Vin Or Vin lt Vj in the Electrical Characteristics table Changed and for TQFP Package from 25 and 9 C W to 29 41 and 6 13 C W respectively Changed and for BGA Package from 25 and 6 C W to 34 1 and 14 0 C W respectively Changed 0 4 and for FBGA Package from 27 and 6 C W to 16 8 and 3 0 C W respectively Added lead free information for 100 pin TQFP 119 BGA and 165 FBGA packages Updated Ordering Information Table 377095 PCI Changed laps from 30 to 40 mA Modified test condition in note 14 from lt Vpp to Vi lt Vpp D 408298 See ECN RXU Changed address of Cypress Se
22. L H L X H L L H Q Read Cycle Begin Burst External L H 1 H L X H H L H Tri state Read Cycle Continue Burst Next X X X JIL H H L H L L H Q Read Cycle Continue Burst Next X X H H L H H L H Tri state Read Cycle Continue Burst Next H X X X H L H L L H Q Read Cycle Continue Burst Next H X X X H L H H L H Tri state Write Cycle Continue Burst Next X X X H H L L X L H D Write Cycle Continue Burst Next H X X H L L X L H D Read Cycle Suspend Burst Current X X X H H H H L L H Q Read Cycle Suspend Burst Current X X IL H H H H H L H Tri state Read Cycle Suspend Burst Current H X XIL X H H H L L H Q Read Cycle Suspend Burst Current X X X H H H H L H Tri state Write Cycle Suspend Burst Current X X XL H H H L X L H D Write Cycle Suspend Burst Current H X X X H H L X L H D Notes 3 X Don t Care H Logic HIGH L Logic LOW 2 2 4 WRITE L when any one more Byte Write enable signals BWE L GW L WRITE when all Byte write enable signals BWE GW 5 The DQ pins are controlled by the current cycle and the OE signal OE is asynchronous and is not sampled with the clock 6 The SRAM always initiates a read cycle when ADSP is asserted regardless of the state of GW BWE or BW Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC As a result OE must be driven HIGH prior to the start of the write cycle to a
23. LOW Voltage Vppo 3 3V 0 5 0 7 V 2 5V 0 3 0 7 V lx Input Load Current GND lt lt 5 5 Identification Register Definitions CY7C1361C CY7C1363C Instruction Field 256K x36 512K x18 Description Revision Number 31 29 000 000 Describes the version number Device Depth 28 24 172 01011 01011 Reserved for Internal Use Device Width 23 18 119 BGA 101001 101001 Defines memory type and architecture Device Width 23 18 165 FBGA 000001 000001 Defines memory type and architecture Cypress Device ID 17 12 100110 010110 Defines width and density Cypress JEDEC ID Code 11 1 00000110100 00000110100 Allows unique identification of SRAM vendor ID Register Presence Indicator 0 1 1 Indicates the presence of an ID register Notes 11 All voltages referenced to Vss GND 12 Bit 24 is 1 in the Register Definitions for both 2 5V and 3 3V versions of this device Document 38 05541 Rev F Page 15 of 31 Feedback EIE CY7C1361C CYPRESS CY7C1363C Scan Register Sizes Register Name Bit Size x 36 Bit Size x 18 Instruction 3 3 Bypass 1 1 ID 32 32 Boundary Scan Order 119 ball BGA package 71 71 Boundary Scan Order 165 ball FBGA package 71 71 Identification Codes Instruction Code Description EXTEST 000 Captures I O ring contents Places the boundary scan register between TDI Forces all SRAM outputs to
24. LSS 1 80 L3 NC 1 FIA 5 2 79 NC C4 2 79 Fo NC 78 C 3 78 E NC 4 77 E43 H 4 77 H 5 76 Vssa Vsso 5 76 Vaso C 6 75 6 75 NC DQc 7 74 NC Co 7 2 73 8 pa 9 72 9 72 Vssa 10 71 Vsso 10 71 Vssa DDQ 11 70 11 70 3 Vppa DQc 12 69 DQg 12 69 F 4 68 DQg 13 68 14 67 Vss VssDNU H 14 67 Vss i CY7C1361C No i5 CY7C1363C 66 F NC DD 1 Vss C 17 256 36 F3 zz Vss 15 512 18 E zz ZH DQp 18 63 H DQ DAs ig 6 FA DQ 4 19 62 19 62 20 61 5 Voa 20 61 Vssa 21 60 Vssq Vsso I 21 60 22 59 DQ 22 59 23 58 F DQ 23 58 DO DQp 24 57 H DQPg 4 24 57 E NC 095 25 56 3 DQ 25 56 NC Vssa 26 55 Vsso Vssa 4 26 55 Vssq DDQ 27 54 27 54 Vppo 28 53 Fo DQ NC C4 28 53 2 NC 29 52 L3 Co 29 52 NC 30 51 F3 DOP 30 51 E NC 59932995999 299399999525 59930999 9 9919959929
25. ON T CARE Notes 26 Device must be deselected when entering ZZ mode See Cycle Descriptions table for all possible signal conditions to deselect the device 27 DQs are in high Z when exiting ZZ sleep mode Document 38 05541 Rev F Page 25 of 31 Feedback il on P CYPRESS PERFORM Ordering Information CY7C1361C CY7C1363C Not all of the speed package and temperature ranges are available Please contact your local sales representative or visit www cypress com for actual products offered Speed Package Operating MHz Ordering Code Diagram Part and Package Type Range 133 CY7C1361C 133AXC 51 85050 100 Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Commercial CY7C1363C 133AXC 3 Chip Enable CY7C1361C 133AJXC 51 85050 100 Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free CY7C1363C 133AJXC 2 Chip Enable CY7C1361C 133BGC 51 85115 119 ball Ball Grid Array 14 x 22 x 2 4 mm CY7C1363C 133BGC CY7C1361C 133BGXC 51 85115 119 Ball Grid Array 14 x 22 x 2 4 mm Lead Free CY7C1363C 133BGXC CY7C1361C 133BZC 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm CY7C1363C 133BZC CY7C1361C 133BZXC 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Lead Free CY7C1363C 133BZXC CY7C13610C 133AXI 51 85050 100 Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Industrial CY7C1363C 133AXI 3 Chip En
26. Y7C1361C 100BZC 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm CY7C1363C 100BZC CY7C1361C 100BZXC 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Lead Free CY7C1363C 100BZXC CY7C1361C 100AXI 51 85050 100 Thin Quad Flat Pack 14 x 20 x 1 4 mm _ Industrial CY7C1363C 100AXI 3 Chip Enable CY7C1361C 100AJXI 51 85050 100 Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free CY7C13636C 100AJXl 2 Chip Enable CY7C1361C 100BGI 51 85115 119 ball Ball Grid Array 14 x 22 x 2 4 CY7C1363C 100BGI CY7C1361C 100BGXI 51 85115 119 ball Ball Grid Array 14 x 22 x 2 4 mm Lead Free _____ CY7C1363C 100BGXI CY7C1361C 100BZI 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm CY7C1363C 100BZI CY7C1361C 100BZXI 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Lead Free CY7C1363C 100BZXI 100 CY7C1361C 100AXE 51 85050 100 Pin Thin Quad Flat 14 x 20 x 1 4 mm Lead Free Automotive Document 38 05541 Rev F Page 27 of 31 Feedback CY7C1361C ESZCYPRES 1 1 CYrci3eac PERFORM Package Diagrams 100 Pin TQFP 14 x 20 x 1 4 mm 51 85050 16 00 0 20 14 00 0 10 1 40 0 05 0 30 0 08 22 00 0 20 20 00 0 10 DETAIL 0 20 MAX 1 60 R 0 08 MIN 0 20 0 MIN 2 SEATING PLANE ST
27. able CY7C1361C 133AJXI 51 85050 100 Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free CY7C13636C 133AJX 2 Chip Enable CY7C1361C 133BGI 51 85115 119 ball Ball Grid Array 14 x 22 x 2 4 mm CY7C1363C 133BGI CY7C1361C 133BGXI 51 85115 119 ball Ball Grid Array 14 x 22 x 2 4 mm Lead Free CY7C1363C 133BGXI CY7C1361C 133BZI 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm CY7C1363C 133BZI CY7C1361C 133BZXI 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Lead Free CY7C1363C 133BZXI Document 38 05541 Rev F Page 26 of 31 Feedback il oN P CYPRESS PERFORM Ordering Information continued CY7C1361C CY7C1363C Not all of the speed package and temperature ranges are available Please contact your local sales representative or visit www cypress com for actual products offered Speed Package Operating MHz Ordering Code Diagram Part and Package Type Range 100 CY7C1361C 100AXC 51 85050 100 Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Commercial CY7C1363C 100AXC 3 Chip Enable CY7C1361C 100AJXC 51 85050 100 Thin Quad Flat 14 x 20 x 1 4 mm Lead Free CY7C1363C 100AJXC 2 Chip Enable CY7C1361C 100BGC 51 85115 119 ball Ball Grid Array 14 x 22 x 2 4 mm CY7C1363C 100BGC CY7C1361C 100BGXC 51 85115 119 Ball Grid Array 14 x 22 x 2 4 mm Lead Free CY7C1363C 100BGXC C
28. dingly MODE Input Selects Burst Order When tied to GND selects linear burst sequence When tied to Vpp Static or left floating selects interleaved burst sequence This is a strap pin and should remain static during device operation Mode Pin has an internal pull up Power Supply Power supply inputs to the core of the device VDDQ Power Supply Power supply for the I O circuitry Document 38 05541 Rev F Page 7 of 31 Feedback 9 CYPRESS PERFORM Pin Definitions continued CY7C1361C CY7C1363C Document 38 05541 Rev F Name Description Vss Ground Ground for the core of the device Ground Ground for the I O circuitry TDO JTAG serial output Serial data out to the JTAG circuit Delivers data on the negative edge of TCK If the Synchronous JTAG feature is not being utilized this pin should be left unconnected This pin is not available on TQFP packages TDI JTAG serial input Serial data In to the JTAG circuit Sampled on the rising edge of TCK If the JTAG Synchronous feature is not being utilized this pin can be left floating or connected to Vpp through a pull up resistor This pin is not available on TQFP packages TMS JTAG serial input Serial data In to the JTAG circuit Sampled on the rising edge of TCK If the JTAG Synchronous feature is not being utilized this pin can be disconnected or connected Vpp This pin is
29. e 133 MHz 250 mA Current f fmax l tevc 10 ns cycle 100 MHz 180 Automatic Vpp Device Deselected All speeds Comm Ind l 110 mA Current TTL Inputs passing MM IOS cycle 100 MHz dii Ispo Automatic CE Max Vpp Device Deselected All speeds 40 mA Power down Vin gt Vpp 0 3V or lt 0 3V Current CMOS Inputs f 0 inputs static Isp3 Automatic CE Vpp Device Deselected All speeds Comm Ind l 100 mA Curent Inputs ac puis suteng excl 100 15 Automatic hs P dte oo All speeds Comm Ind l 40 mA inputs t2 inputs static oe oe a Notes 13 Overshoot lt Vpp 1 5V Pulse width less than 1 2 undershoot AC gt 2V Pulse width less than 2 14 TPower up Assumes a linear ramp from OV to Vpp min within 200ms During this time lt and Vppa lt Vpp Document 38 05541 Rev F Page 19 of 31 Feedback CY7C1361C CYPRESS CY7C1363C PERFORM Capacitance 100 TQFP 119 BGA 165 FBGA Parameter Description Test Conditions Max Max Max Unit Cin Input Capacitance 25 C f 1 MHz 5 5 5 pF Clock Input Capacitance DD 5 5 5 pF Cio Input Output Capacitance pages 5 7 7 pF Thermal Resistance 100 TQFP 119 BGA 165 FBGA Parameter Description Test Conditions Package Package Package Unit Thermal R
30. ect the device ADSP is ignored if CE is HIGH CE is sampled only when a new external address is loaded Input Chip Enable 2 Input active HIGH Sampled on the rising edge of CLK Used in Synchronous conjunction with CE and to select deselect the device CE is sampled only when a new external address is loaded CE Input Chip Enable 3 Input active LOW Sampled on the rising edge of CLK Used in Synchronous _ conjunction with CE and to select deselect the device CE3 is sampled only when a new external address is loaded OE Input Output Enable asynchronous input active LOW Controls the direction of the I O pins Asynchronous When LOW the I O pins behave as outputs When deasserted HIGH pins are tri stated and act as input data pins OE is masked during the first clock of a read cycle when emerging from a deselected state ADV Input Advance Input signal sampled on the rising edge of CLK When asserted it automat Synchronous ically increments the address in a burst cycle ADSP Input Address Strobe from Processor sampled on the rising edge of CLK active LOW Synchronous When asserted LOW addresses presented to the device are captured in the address registers are also loaded into the burst counter When ADSP and ADSC are both asserted only ADSP is recognized ASDP is ignored when CE is deasserted HIGH ADSC Input Address Strobe from Controller sampled on the rising edge of CLK active LOW Synch
31. ee that the boundary scan register will capture the correct value of a signal the SRAM signal must be stabilized long enough to meet the TAP controller s capture set up plus hold times tcs and tc The SRAM clock input might not be captured correctly if there is no way in a design to stop or slow the clock during a SAMPLE PRELOAD instruction If this is an issue it is still possible to capture all other signals and simply ignore the value of the CK and CK captured in the boundary scan register Once the data is captured it is possible to shift out the data by putting the TAP into the Shift DR state This places the bound ary scan register between the TDI and TDO pins Page 13 of 31 Feedback PRELOAD allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells prior to the selection of another boundary scan test operation The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required that is while data captured is shifted out the preloaded data can be shifted in TAP Timing Test Clock TCK CY7C1361C CY7C1363C BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift DR state the bypass register is placed between the TDI and TDO balls The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board Heserved
32. esistance Test conditions follow standard 29 41 34 1 16 8 C W Junction to Ambient test methods and procedures Thermal Resistance __ 0 measuring thermal 6 31 14 0 3 0 G W Junction to Case impedance per EIA JESD51 AC Test Loads and Waveforms 3 3V I O Test Load OUTPUT 3 3V I m OUTPUT 500 5pF L INCLUDING 1 5V SCOPE b 2 5V I O Test Load OUTPUT 2 5V OUTPUT 500 5 pF R 15380 1 25V scope 0 Note 15 Tested initially and after any design or process change that may affect these parameters Document 38 05541 Rev F ALL INPUT PULSES Page 20 of 31 Feedback Q CY7C1361C CYPRESS CY7C1363C PERFORM Switching Characteristics Over the Operating Rangel 21 133 100 Parameter Description Min Max Min Max Unit tPOWER Vpp Typical to the first Access 9 1 1 ms Clock Clock Cycle Time 7 5 10 ns tcu Clock HIGH 3 0 4 0 ns teL Clock LOW 3 0 4 0 ns Output Times lcpv Data Output Valid After CLK Rise 6 5 8 5 ns Data Output Hold After CLK Rise 2 0 2 0 ns telz Clock to 2117 18 19 0 0 ns Clock to High Zl 18 19 3 5 3 5 ns loEv OE LOW to Output Valid 3 5 3 5 ns toELz OE LOW to Output Low zl 7 18 19 0 0 ns
33. ference level is 1 5V when 3 3V and is 1 25V when 2 5V 21 Test conditions shown in a of AC Test Loads unless otherwise noted Document 38 05541 Rev F Page 21 of 31 Feedback CY7C1361C CY7C1363C J CYPRESS PERFOR Timing Read Cycle Timing WU Ww UM do www DD ID t suspends burst ADV OE tov they tev ex Ex 2 XX Q A2 2 Hwa XK Q A2 Xa rst wraps around taz lt 1 Data Out M Al ata Out 0 High Z M toitsi ital date Single READ DON T R UNDEFINED 22 this diagram when is LOW CE is LOW is HIGH d CE is LOW When CE is HIGH CE is HIGH is LOW or is HIGH Page 22 of 31 Feedback Document 38 05541 Rev F CY7C1361C CYPRESS CY7C1363C PERFORM Timing Diagrams continued tas Write Cycle 23 fs er rs A DOO OOO x 2 wow ww lt gt 77 wma LLL Byte write Bored for first of when ADSP initiates burst ou Z CLD _ 2 029 A Da ay M wes A V ur KA UU ces CEH E
34. for the duration of beeen after the ZZ input returns LOW Page 9 of 31 Feedback cL CY7C1361C ZCYPRESS JA CYrCi363C PERFORM ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min Max Unit Ippzz Sleep mode standby current ZZ gt Vpp 0 2V Comm ind l 50 mA Automotive 60 mA 1775 Device operation to ZZ ZZ gt Vpp 0 2V 2tcyc ns tzzREC ZZ recovery time ZZ 0 2N 2lcvc ns tzzi ZZ active to sleep current This parameter is sampled 2tcyc ns 8771 ZZ Inactive to exit sleep current This parameter is sampled 0 ns Truth Table 4 5 6 7 Cycle Description od i CE CE CE ZZ ADSP ADSC ADV WRITE OE CLK DQ Deselected Cycle Power down None H X X L X X X Tri state Deselected Cycle Power down None L L X L X X X X L H Tri state Deselected Cycle Power down None L X H IL L X X X X L H Tri state Deselected Cycle Power down None L L X H L X X X LH Tri state Deselected Cycle Power down None X X X H L X X X LH Tri state Sleep Mode Power down None X X X IH X X X X X X Tri state Read Cycle Begin Burst External L H L L L X X X L L H Q Read Cycle Begin Burst External L H LIL L X X X H L H Tri state Write Cycle Begin Burst External L H L IL H L X L X L H D Read Cycle Begin Burst External L H L I
35. is detected regardless of the state of OE Burst Sequences The CY7C1361C CY7C1363C provides an on chip two bit wraparound burst counter inside the SRAM The burst counter is fed by and can follow either a linear or interleaved burst order The burst order is determined by the state of the MODE input A LOW on MODE will select a linear burst sequence A HIGH on MODE will select an interleaved burst order Leaving MODE unconnected will cause the device to default to a interleaved burst sequence Interleaved Burst Address Table MODE Floating or Vpp First Second Third Fourth Address Address Address Address A1 AO A1 AO A1 AO A1 AO 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 Linear Burst Address Table MODE GND First Second Third Fourth Address Address Address Address A1 AO A1 AO A1 AO A1 AO 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 Sleep Mode The ZZ input pin is an asynchronous input Asserting ZZ places the SRAM in a power conservation sleep mode Two clock cycles are required to enter into or exit from this sleep mode While in this mode data integrity is guaranteed Accesses pending when entering the sleep mode are not considered valid nor is the completion of the operation guaranteed The device must prior to entering the sleep mode CE4 CEA ADSP and ADSC must remain inactive
36. le Descriptions table for appropriate states that indicate a write on the next clock rise the appropriate data will be latched and written into the device Byte writes are allowed All I Os are tri stated during a byte write Since this is common device the asynchronous OE input signal must be deasserted and the I Os must be tri stated prior to the presentation of data to DQs As a safety precaution the data lines are tri stated once a write cycle is detected regardless of the state of OE Single Write Accesses Initiated by ADSC This write access is initiated when the following conditions are satisfied at clock rise 1 CE4 and CEj4l are all asserted Document 38 05541 Rev F CY7C1361C CY7C1363C active 2 ADSC is asserted LOW 3 ADSP is deasserted HIGH and 4 the write input signals GW BWE and BWy indicate a write access ADSC is ignored if ADSP is active LOW The addresses presented are loaded into the address register and the burst counter control logic and delivered to the memory core The information presented to DQja p will be written into the specified address location Byte writes are allowed All I Os are tri stated when a write is detected even a byte write Since this is a common I O device the asynchronous OE input signal must be deasserted and the l Os must be tri stated prior to the presentation of data to As a safety precaution the data lines are tri stated once a write cycle
37. lified with the Byte Write Enable BWE and Byte Write Select BWy inputs A Global Write Enable GW overrides all byte write inputs and writes data to all four bytes All writes are simplified with on chip synchronous self timed write circuitry Three synchronous Chip Selects CE4 CE and an asynchronous Output Enable OE provide for easy bank selection and output tri state control ADSP is ignored if CE is HIGH Single Read Accesses A single read access is initiated when the following conditions are satisfied at clock rise 1 CE and are all asserted active and 2 ADSP or ADSC is asserted LOW if the access is initiated by ADSC the write inputs must be deasserted during this first cycle The address presented to the address inputs is latched into the address register and the burst counter control logic and presented to the memory core If the OE input is asserted LOW the requested data will be available at the data outputs a maximum to after clock rise ADSP is ignored if CE is HIGH Single Write Accesses Initiated by ADSP This access is initiated when the following conditions are satisfied at clock rise 1 CE4 CE are all asserted active and 2 ADSP is asserted LOW The addresses presented are loaded into the address register and the burst inputs GW BWE BW are ignored during this first clock cycle If the write inputs are asserted active see Write Cyc
38. llow the outputs to tri state OE is a don t care for the remainder of the write cycle 7 OE is asynchronous and is not sampled with the clock rise It is masked internally during write cycles During a read cycle all data bits are tri state when OE is inactive or when the device is deselected and all data bits behave as output when OE is active LOW Document 38 05541 Rev F Page 10 of 31 Feedback CYPRESS PERFORM Partial Truth Table for Read Write 9 CY7C1361C CY7C1363C Function CY7C1361C U m Write Byte A Write Byte B DQPp Write Bytes B A Write Byte C DQPc Write Bytes A DQPc Write Bytes B DQPg Write Bytes C B A DQPg Write Byte D DQPp Write Bytes D A DQPp Write Bytes D B DQPp Write Bytes D B A DQPp Write Bytes D B DQPp DQPp Write Bytes D B A DQPc Write Bytes D C A DQPp DQPp Write All Bytes Write All Bytes lt 0 11111 11 15 18 Uu 111 11111 1 8 2 gt Truth Table for Read Writel
39. miconductor Corporation on Page 1 from 3901 North First Street to 198 Champion Court Changed tri state to tri state Modified Input Load to Input Leakage Current except ZZ and MODE in the Electrical Characteristics Table Replaced Package Name column with Package Diagram in the Ordering Information table Updated the ordering information E 433033 See ECN NXR Included Automotive range 501793 VKN Added the Maximum Rating for Supply Voltage on Relative to GND Changed try tr from 25 ns to 20 ns and trpoy from 5 ns to 10 ns in TAP AC Switching Characteristics table Updated the Ordering Information table Document 38 05541 Rev F Page 31 of 31 Feedback
40. not fully compliant to the 1149 1 convention because some of the mandatory 1149 1 instructions are not fully implemented The TAP controller cannot be used to load address data or control signals into the SRAM and cannot preload the I O buffers The SRAM does not implement the 1149 1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE PRELOAD rather it performs a capture of the I O ring when these instructions are executed Instructions are loaded into the TAP controller during the Shift IR state when the instruction register is placed between TDI and TDO During this state instructions are shifted Document 38 05541 Rev F CY7C1361C CY7C1363C through the instruction register through the TDI and TDO balls To execute the instruction once it is shifted in the TAP controller needs to be moved into the Update IR state EXTEST EXTEST is a mandatory 1149 1 instruction which is to be executed whenever the instruction register is loaded with all Os EXTEST is not implemented in this SRAM TAP controller and therefore this device is not compliant to 1149 1 The TAP controller does recognize an all 0 instruction When an EXTEST instruction is loaded into the instruction register the SRAM responds as if a SAMPLE PRELOAD instruction has been loaded There is one difference between the two instructions Unlike the SAMPLE PRELOAD instruction EXTEST places the SRAM outputs in a High Z state IDCODE The IDCODE instruction ca
41. nstruction is executed Boundary Scan Register The boundary scan register is connected to all the input and bidirectional balls on the SRAM The boundary scan register is loaded with the contents of the RAM ring when the TAP controller is in the Capture DR state and is then placed between the TDI and TDO balls when the controller is moved to the Shift DR state The EXTEST SAMPLE PRELOAD and SAMPLE Z instructions can be used to capture the contents of the ring The Boundary Scan Order tables show the order in which the bits are connected Each bit corresponds to one of the bumps on the SRAM package The MSB of the register is connected to TDI and the LSB is connected to TDO Identification ID Register The ID register is loaded with a vendor specific 32 bit code during the Capture DR state when the IDCODE command is loaded in the instruction register The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift DR state The ID register has a vendor code and other information described in the ldentification Register Definitions table TAP Instruction Set Overview Eight different instructions are possible with the three bit instruction register All combinations are listed in the Instruction Codes table Three of these instructions are listed as RESERVED and should not be used The other five instruc tions are described in detail below The TAP controller used in this SRAM is
42. o G DQc DQc BWc ADV BWg DQg H 0 Vss GW Vss J NC NC CLK Vss DQ L DQ BW5 NC BW DO DO M DQp Vss BWE Vss DQ Vss A1 Vss DQ BG P Vss AO Vss DOP DQ R NC A MODE Vpp NC A NC T NC NC 72M A A A NC 36M ZZ U Voa TMS TDO NC Vom CY7C1363C 512K x 18 1 2 3 4 5 6 7 A ADSP A A VDDQ B NC 288M A ADSG A A NC 512M NC 144M A A NC 1G D NC Vss NC Vss NC E DQ Vas Vas F NC Vss OE Vss DQa G NC Vss NC DQ NC Ves GW NC J VDDQ Vpp NC Vpp NC Vpp VDDQ K NC DAs Vss CLK Vss NC L NC Vss NC BW M DQg Vss BWE Vss NC N NC Vee 1 Vss DQ NC P NC A0 Vss NC DOA R NC MODE NC A NC T NC 72M A A NC 36M A A ZZ U Vba TMS TDI TCK TDO NC Vooo Document 38 05541 Rev F CY7C1361C CY7C1363C Page 5 of 31 Feedback _ CY7C1361C CYPRESS CY7C1363C PERFORM aH Pin Configurations continued 165 Ball FBGA Pinout 3 Chip Enable
43. rnal Internal 9 B3 A 45 P1 DQp 9 B3 A 45 Internal Internal 10 D6 DQPp 46 L2 DQp 10 T2 A 46 Internal Internal 11 H7 DQg 47 K1 DQp 11 Internal Internal 47 Internal Internal 12 G6 DQg 48 N2 DQp 12 Internal Internal 48 P2 13 DQg 49 N1 DQp 13 Internal Internal 49 N1 14 07 50 2 DQp 14 06 DQPA 50 M2 DQg 15 E7 51 L1 DQp 15 E7 51 L1 DQg 16 F6 52 2 DQp 16 F6 52 K2 17 G7 DQg 53 Internal Internal 17 G7 DQA 53 Internal Internal 18 H6 54 H1 DQc 18 H6 54 H1 DQg 19 T7 77 55 G2 DQc 19 T7 ZZ 55 G2 DQg 20 K7 56 2 DQc 20 K7 56 2 21 L6 57 01 DQc 21 L6 57 01 22 58 H2 DQc 22 N6 58 Internal Internal 23 P7 59 G1 DQc 23 P7 DQA 59 Internal Internal 24 N7 60 F2 DQc 24 Internal Internal 60 Internal Internal 25 M6 61 1 DQc 25 Internal Internal 61 Internal Internal 26 L7 62 D2 DQPc 26 Internal Internal 62 Internal Internal 27 K6 63 C2 A 27 Internal Internal 63 C2 A 28 P6 64 A2 A 28 Internal Internal 64 A2 A 29 T4 65 E4 29 T6 A 65 E4 CE 30 A3 A 66 B2 30 66 B2 CE 31 C5 A 67 L3 BWD 31 C5 A 67 Internal Internal 32 B5 A 68 G3 BWc 32 B5 A 68 Internal Internal 33 A 69 G5 BWg 33 A5 A 69 G3 BWp 34 C6 A 70 L5 34 C6 A 70 L5 BWa 35 A6 A 71 Internal Internal 35 71 Internal Internal 36 B6 A 36 B6 A
44. ronous When asserted LOW addresses presented to the device are captured in the address registers are also loaded into the burst counter When ADSP and ADSC are both asserted only ADSP is recognized BWE Input Byte Write Enable Input active LOW Sampled on the rising edge of CLK This signal Synchronous must be asserted LOW to conduct a byte write ZZ Input ZZ sleep Input active HIGH When asserted HIGH places the device in a Asynchronous non time critical sleep condition with data integrity preserved For normal operation this pin has to be LOW or left floating ZZ pin has an internal pull down DQ Bidirectional Data I O lines As inputs they feed into an on chip data register that is Synchronous triggered by the rising edge of CLK As outputs they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle The direction of the pins is controlled by OE When OE is asserted LOW the pins behave as outputs When HIGH DQ DQPy are placed in a tri state condition The outputs are automatically tri stated during the data portion of a write sequence during the first clock when emerging from a deselected state and when the device is deselected regardless of the state of OE Bidirectional Data Parity I O Lines Functionally these signals are identical to DQg Synchronous During write sequences DQPy is controlled by BWy correspon
45. s Vss Vss Vpp NC K NC Vpp Vss Vss Vss Vpp DQA NC L DQg NC Vpp Vss Vss Vss Vpp DQ NC M DQg NC VDD Vss Vss Vss VDD VDDQ DQA NC N DQPg NC VDDQ Vss NC NC 18M NC Vss VDDQ NC NC P NC NC 72M A A TDI Al TDO A A A A R MODE NC 36M A A TMS TCK A A A A Document 38 05541 Rev F Page 6 of 31 Feedback Z CYPRESS PERFORM Pin Definitions CY7C1361C CY7C1363C Name Description Ag Ay Input Address Inputs used to select one of the address locations Sampled at the rising Synchronous edge of the CLK if ADSP or ADSC is active LOW CE4 CEs and are sampled active Aj1 0 feed the 2 bit counter BW BWp Input Byte Write Select Inputs active LOW Qualified with BWE to conduct byte writes to the BWc BWp Synchronous SRAM Sampled on the rising edge of CLK GW Input Global Write Enable Input active LOW When asserted LOW on the rising edge of CLK a Synchronous global write is conducted ALL bytes are written regardless of the values on BWy and BWE CLK Input Clock Input Used to capture all synchronous inputs to the device Also used to increment Clock the burst counter when ADV is asserted LOW during a burst operation CE Input Chip Enable 1 Input active LOW Sampled on the rising edge of CLK Usedin Synchronous conjunction with and to select desel
46. ss 17 256 36 22 V s 2217 512 18 Oz DQp 18 63 Fo ig 63 H 19 62 Fo lt 49 62 Vona 20 61 Vppa 20 61 5 Vo ssa 21 60 Vssq 24 60 DQp L 22 59 F3 DQ DQg 22 59 DQ DQp 23 58 F3 lt 23 58 L1 DO EH 24 57 DQPg 24 57 EL NC DQp 25 56 NC 425 56 H NC 26 55 lt 26 55 Vssa 27 54 Vppa Vooo 27 54 DQp 28 53 NC 04 53 DQp 29 52 NC 52 30 51 DQP NC 30 51 NC 5985995999929 939999930 lt lt lt lt lt lt lt a r 9 aoo lt lt 22 002 2 lt lt lt lt lt lt 99 lt lt lt lt 4 Document 38 05541 Rev F Page 4 of 31 Feedback Pin Configurations continued 119 Ball BGA Pinout 2 Chip Enables with JTAG CY7C1361C 256K x 36 1 2 3 4 5 6 7 A ADSP A A NC 288M ADSG A A NC 512M C NC 44M A A Vip A A D DGPc NC Vas DOP DOs E Bde Ves Vas Dp F VDDQ DQc Vss OE Vss DQg Vpp
47. stem Design Guidelines on www cypress com 2 is for A version of TQFP 3 Chip Enable Option and 165 FBGA package only 119 BGA is offered only in 2 Chip Enable Cypress Semiconductor Corporation Document 38 05541 Rev F 198 Champion Court Jose CA 95134 1709 408 943 2600 Revised September 14 2006 n QW P CYPRESS CY7C1361C CY7C1363C PERFORM Logic Block Diagram CY7C1361C 256K x 36 AQ ATA ADDRESS A REGISTER gt MODE Burst Qi COUNTER AND LOGIC 00 a t ADSC NES n ca BYTE E Ld WRITE REGISTER r WRITE REGISTER L pgs N I t D Lc WRITE REGISTER eH gt WRITE REGISTER MEMORY OUTPUT A DQs Ly SENSE BUFFERS gt DQPs ARRAY AMPS DOPA DQPs m DQPs BW
48. uses a vendor specific 32 bit code to be loaded into the instruction register It also places the instruction register between the TDI and TDO balls and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift DR state The IDCODE instruction is loaded into the instruction register upon power up or whenever the TAP controller is given a test logic reset state SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO balls when the TAP controller is in a Shift DR state It also places all SRAM outputs into a High Z state SAMPLE PRELOAD SAMPLE PRELOAD is a 1149 1 mandatory instruction When the SAMPLE PRELOAD instructions are loaded into the in struction register and the TAP controller is in the Capture DR state a snapshot of data on the inputs and output pins is cap tured in the boundary scan register The user must be aware that the TAP controller clock can only operate at a frequency up to 20 MHz while the SRAM clock operates more than an order of magnitude faster Because there is a large difference in the clock frequencies it is possi ble that during the Capture DR state an input or output will undergo a transition The TAP may then try to capture a signal while in transition metastable state This will not harm the device but there is no guarantee as to the value that will be captured Repeatable results may not be possible To guarant
49. without using the JTAG feature To disable the TAP controller TCK must be tied LOW Vss to prevent clocking of the device TDI and TMS inter nally pulled up and may be unconnected They may alternately be connected to Vpp through a pull up resistor TDO should be left unconnected Upon power up the device will come up in a reset state which will not interfere with the operation of the device TAP Controller State Diagram TEST LOGIC RESET 0 C RUN TEST 1 SELECT 1 SELECT 1 IDLE 1 DRSCAN IR SCAN 0 0 1 1 CAPTURE DR CAPTURE IR 0 0 3 T SHIFT DR D SHIFTIR CO 92 1 1 1 1 Le EXITLDR Le EXITHR 0 0 Y Y PAUSEDR 0 PAUSE IR D 02 1 1 0 0 EXIT2 DR EXIT2IR 1 1 Y i d UPDATEDR UPDATER 0 1 0 Y The 0 1 next to each state represents the value of TMS at the rising edge of TCK Test Access Port TAP Test Clock TCK The test clock is used only with the TAP controller All inputs are captured on the rising edge of TCK All outputs are driven from the falling edge of TCK Document 38 05541 Rev F CY7C1361C CY7C1363C Test MODE SELECT TMS The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK It is allowable to leave this ball

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