Cypress CY7C1346H User's Manual
Contents
1. 2 CYPRESS CY7C1346H PERFORM Switching Characteristics Over the Operating Rangel 12 166 Parameter Description Min Max Unit POWER Vpp Typical to the First Access l 1 ms Clock Clock Cycle Time 6 0 ns tcu Clock HIGH 2 5 ns teL Clock LOW 2 5 ns Output Times tco Data Output Valid after CLK Rise 3 5 ns Data Output Hold after CLK Rise 1 5 ns telz Clock to 2114 15 16 0 ns tcHz Clock to High z 4 15 16 3 5 ns toev OE LOW to Output Valid 3 5 ns toELz OE LOW to Output Low z 4 15 16 0 ns loEuz OE HIGH to Output 211 15 16 3 5 ns Set up Times tas Address Set up before CLK Rise 1 5 ns taps ADSC ADSP Set up before CLK Rise 1 5 ns tapvs ADV Set up before CLK Rise 1 5 ns twes GW BWE BWia p Set up before CLK Rise 1 5 ns tps Data Input Set up before CLK Rise 1 5 ns tcEs Chip Enable Set Up before CLK Rise 1 5 ns Hold Times Address Hold after CLK Rise 0 5 ns tADH ADSP ADSC Hold after CLK Rise 0 5 ns ADV Hold after CLK Rise 0 5 ns twEH GW BWE Hold after CLK Rise 0 5 ns 1 Data Input Hold after CLK Rise 0 5 ns Chip Enable Hold after CLK Rise 0 5 ns Notes 11 Timing reference level is 1 5V when Vppq 3 3V and 1 25V when Vppq 2 5V 12 Test conditions shown in a of AC Test Loads unless otherwise noted 13 This part has a voltage regulator internally tpgwer is the time that the power nee2. CONTROL SLEEP Note 1 For best practices recommendations please refer to the Cypress application note System Design Guidelines on www cypress com Cypress Semiconductor Corporation Document 38 05672 Rev B 198 Champion Court San Jose CA 95134 1709 408 943 2600 Revised April 26 2006 Feedback PER FQ RM Selection Guide CY7C1346H 166 MHz Unit Maximum Access Time 3 5 ns Maximum Operating Current 240 mA Maximum CMOS Standby Current 40 mA Pin Configuration 100 pin TQFP Pinout t lt S BB lt O Olmimimim O gt gt lt lt lt lt Socordoiuousowa osocdrmoiddow EN O O O O O O O O O CO CO CO CO CO 1 80 DQPg DQ 2 79 D
3. fh Mom Lom IM I _ tos gt lt gt toez Data In D High Z D A3 D A5 gt az ir NN Data Out 0 A oaa Back to Back READs t SingleWRITE gt DON T CARE UNDEFINED Notes 19 The data bus remains in High Z following a Write cycle unless an ADSP ADSC or ADV cycle is performed 20 GW is HIGH AXXO KAMARA AA YON RK aman m BURST READ gt r Back to Back E WRITES Document 38 05672 Rev B Page 13 of 16 Feedback EU CYPRESS CY7C1346H PERFORM Switching Waveforms continued ZZ Mode Timing P1 221 SUPPLY ALL INPUTS except ZZ Outputs Q DON T CARE Notes 21 Device must be deselected when entering ZZ mode See Cycle Descriptions table for all possible signal conditions to deselect the device 22 DGs are in High Z when exiting ZZ sleep mode Document 38 05672 Rev B Page 14 of 16 Feedback 2 CYPRESS PERFORM Ordering Information CY7C1346H Not all of the speed package and temperature ranges are available Please contact your local sales representative or visit www cypress com for actual products offered Speed Package Operating MHz Ordering Code Diagram Package Type Range 166 CY7C1346H 166
4. 8 9 Parameter Description Test Conditions Min Max Unit Vpp Power Supply Voltage 3 135 3 6 V VDDQ Supply Voltage for 3 3V I O 3 135 Vpp V for 2 5V I O 2 375 2 625 Vou Output HIGH Voltage for 3 3V I O 4 0 mA 2 4 for 2 5V I O 1 0 mA 2 0 VoL Output LOW Voltage for 3 3V I O Io 8 0 mA 0 4 V for 2 5V I O lp 1 0 mA 0 4 InputHIGH Voltage for33Vl O 20 03 V for 2 5V I O 1 7 Vpp 0 3V V ViL Input LOW Voltage for 3 3V 0 3 0 8 V for 2 5V I O 0 3 0 7 V Ix Input Leakage Current GND lt Vi VDDQ 5 5 except ZZ and MODE Input Current of MODE Input 30 Input Vpp 5 HA Input Current of ZZ Input Vas 5 Input Vpp 30 loz Output Leakage Current GND lt V lt Vppo Output Disabled 5 5 uA 155 Vpp Operating Supply Current Vpp Max 0 mA 240 mA f fmax 1 1 Automatic CS Power down Vpp Max Device Deselected Vin gt or 100 mA Current TTL Inputs Vin lt f fmax 1 Ispo Automatic CS Power down Vpp Max Device Deselected Viv lt 0 3V or 40 mA Current CMOS Inputs Vin 0 3V f 0 Automatic CS Power down Vpp Max Device Deselected or Viy lt 0 3V 85 mA Current CMOS Inputs or Vin gt 0 3V f fmax 1 15 Automatic CS Power down Vpp Max Device Deselected Vin gt or 45 mA Current TTL Inputs Vin lt Vif 0 Notes 8 Ove
5. Write is conducted ALL bytes are written regardless of the values on 0 and BWE BWE Input Byte Write Enable Input active LOW Sampled on the rising edge of CLK This signal must be Synchronous asserted LOW to conduct a Byte Write CLK Input Clock Input Used to capture all synchronous inputs to the device Also used to increment the burst Clock counter when ADV is asserted LOW during a burst operation CE Input Chip Enable 1 Input active LOW Sampled on the rising edge of CLK Used in conjunction with Synchronous and CE to select deselect the device ADSP is ignored if CE is HIGH CE is sampled only when a new external address is loaded Input Chip Enable 2 Input active HIGH Sampled on the rising edge of CLK Used in conjunction with Synchronous CE and CE to select deselect the device is sampled only when a new external address is loaded CEs Input Chip Enable 3 Input active LOW Sampled on the rising edge of CLK Used in conjunction with Synchronous CE and to select deselect the device CE3 is sampled only when a new external address is loaded OE Input Output Enable asynchronous input active LOW Controls the direction of the I O pins When Asynchronous LOW the I O pins behave as outputs When deasserted HIGH I O pins tri stated and act as input data pins OE is masked during the first clock of a Read cycle when emerging from a deselected state ADV Input Advance Input signal s
6. in the TQFP package ZEND 6 The SRAM always initiates a read cycle when ADSP is asserted regardless of the state of GW BWE Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC As a result OE must be driven HIGH prior to the start of the don t care for the remainder of the Write cycle rite cycle to allow the outputs to Tri State OE is a 7 OE is asynchronous and is not sampled with the clock rise It is masked internally during Write cycles During a Read cycle all data bits are Tri State when OE is inactive or when the device is deselected and all data bits behave as output when OE is active LOW Document 38 05672 Rev B Page 6 of 16 Feedback CYPRESS PERFORM Truth Table continued 3 5 6 7 CY7C1346H Next Cycle Add Used CE CE CE ZZ ADSP ADSC ADV WRITE CLK WRITE Cycle Suspend Burst Current X X L H D WRITE Cycle Suspend Burst Current H Truth Table for Read Write 31 r X L H D Function U m o gt Read Read Write Byte A and Write Byte B DQg and Write Bytes B A Write Byte C DQg and Write Bytes C A Write Bytes C B Write Bytes C B A Write Byte D DQp and DQPp Write Bytes D A Write Bytes D B Wr
7. 46H is a common I O device the Output Enable OE must be deserted HIGH before presenting data to the DQ inputs Doing so will tri state the output drivers As a safety precaution DQs are automatically tri stated whenever a Write cycle is detected regardless of the state of OE Page 4 of 16 Feedback CYPRESS PERFORM Burst Sequences The CY7C1346H provides a two bit wraparound counter fed by Aj Ag that implements either an interleaved or linear burst CY7C1346H Interleaved Burst Address Table MODE Floating or Vpp First Second Third Fourth sequence The interleaved burst sequence is designed specif Address Address Address Address ically to support Intel Pentium applications The linear burst A4 Ag Ay Ag Ag Ay Ag sequence is designed to support processors that follow a 00 01 10 11 linear burst sequence The burst sequence is user selectable through the MODE input 01 00 11 10 Asserting ADV LOW at clock rise will automatically increment 10 11 00 01 the burst counter to the next address in the burst sequence 11 10 01 00 Both Read and Write burst operations are supported Sleep Mode Linear Burst Address Table MODE GND The ZZ input pin is an asynchronous input Asserting ZZ First Second Third Fourth places the SRAM in a power conservation sleep mode Two clock cycles are req
8. ADV Address data inputs and write controls are registered on chip to initiate a self timed Write cycle This part supports Byte Write operations see Pin Descriptions and Truth Table for further details Write cycles can be one to four bytes wide as controlled by the Byte Write control inputs GW when active LOW causes all bytes to be written The CY7C1346H operates from a 3 3V core power supply while all outputs also operate with either a 3 3V 2 5V supply All inputs and outputs are JEDEC standard JESD8 5 compatible Logic Block Diagram ADDRESS gt REGISTER BW 2 I A10 DQoDQo BYTE BURST COUNTER 4 anR AND LOGIC WRITE REGISTER tb ID WRITE REGISTER DQc DQPc BYTE WRITE DRIVER DQsDQPs BYTE WRITE REGISTER WRITE DRIVER DQs OUTPUT OUTPUT DQPa MEMORY SENSE ARRAY AMPS REGISTERS BUFFERS DQPs WRITE REGISTER DQa DQPa BYTE ENABLE WRITE DRIVER DQPc 4 A DQPo OF PIPELINED vii INPUT REGISTERS REGISTER _ ENABLE
9. AXC 51 85050 100 pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Commercial CY7C1346H 166AXI 51 85050 100 pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Industrial Package Diagrams 100 pin 14 x 20 x 1 4 mm 51 85050 16 00 0 20 14004010 1 40 0 05 100 81 I go ES ES Es 0 30 0 08 ES ES ES ES ES ES e Eo d EH H 8 ES ES e EH Y N o d ES 065 A 5 SEE DETAIL ES ES ES ES ES ES 30 c Fo 51 31 50 i 0 20 MAX 1 60 R 0 08 MIN 5 0 20 OF MIN e SEATING PLANE EP N STAND OFF RR 0 05 MIN NOTE 0 25 4 fa H 0 15 MAX GAUGE PLANE 1 STD REF MS 026 po CA 2 BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION END FLASH B MOLD PROTRUSION END FLASH SHALL NOT EXCEED 0 0098 in 0 25 mm PER SIDE 0 7 C 020 MAX BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 3 DIMENSIONS IN MILLIMETERS 0 60 0 15 Cer O20 MIN 51 85050 B 1 00 REF DETAIL 1486 is trademark and Intel and Pentium are registered trademarks of Intel Corporation PowerPC is registered trademark of IBM Corporation All product and company n
10. DEFINED Note 17 On this diagram when CE is LOW CE is LOW CE is HIGH and CE is LOW When CE is HIGH CE is HIGH or CE is LOW or CE is HIGH Document 38 05672 Rev B Page 11 of 16 Feedback 7 CYPRESS CY7C1346H PERFORM Switching Waveforms continued Write Cycle Timing 18 _ ren eee taps ADH tas T VO Byte write signals are ignored for first when ADS initiates burst a I WD Lll Wes lt lt 77 UWL MUN A i au WW Ww ces gt Th Mf TM ND SU T ED ED E ADV suspends burst tos High Z Nc D A1 VW D A2 NOK 182 nX om YE 2K D A2 XX D A3 XX A3 E BURST READ Single WRITE BURST WRITE 2 Extended BURST WRITE DON T CARE UNDEFINED Note 18 Full width Write can be initiated by either GW LOW or by GW HIGH BWE LOW and BWra p LOW Data In D Document 38 05672 Rev B Page 12 of 16 Feedback CY7C1346H Switching Waveforms continued Read Write Cycle Timing 13 20 a d V a a a to ta lt taps DH 7 V M c mi SR Cs COO TTD s X Cs mo VE LIU D toes lt gt 4 6
11. Features CY7C1346H PERF 3 5 ns 166 MHz device RM Provide high performance 3 1 1 1 access rate User selectable burst counter supporting Intel Registered inputs and outputs for pipelined operation 64K x 36 common I O architecture 3 3V core power supply 3 3V 2 5V I O operation Fast clock to output times Pentium interleaved or linear burst sequences package ZZ Sleep Mode Option Separate processor and controller address strobes Synchronous self timed writes Asynchronous output enable Offered in JEDEC standard lead free 100 pin TQFP 2 Mbit 64K x 36 Pipelined Sync SRAM Functional Description The CY7C1346H SRAM integrates 64K x 36 SRAM cells with advanced synchronous peripheral circuitry and a two bit counter for internal burst operation All synchronous inputs are gated by registers controlled by a positive edge triggered Clock Input CLK The synchronous inputs include all addresses all data inputs address pipelining Chip Enable depth expansion Chip Enables gt and CE Burst Control inputs ADSC ADSP and ADV Write Enables BWya pp and BWE and Global Write GW Asynchronous Mclude the Output Enable OE and the ZZ pin Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor ADSP or Address Strobe Controller ADSC are active Subsequent burst addresses can be internally generated as controlled by the Advance pin
12. Qc 4 3 78 DQs 4 77 Vssa 5 76 L3 Vsso Qc 6 75 DQg BYTEC DQg 4 7 74 DQc 8 73 DQg DQc 9 72 DQg Vssa 10 71 00 11 70 VDDQ DQc 12 69 DQg 13 68 NC 14 67 Vss 15 CY7C1346H 66 NC NC 16 65 Vpp Vss 17 64 ZZ DQp 18 63 DQ DQp 19 62 DQa 20 61 Vssa 21 60 DQp CH 22 59 DQa DQp 23 58 DQA BYTED DQp 24 57 DQp 25 56 Vssa 26 55 Vssa Vppa 27 54 DQp 28 53 Qa DQp 29 52 DQPp 30 51 T NW CO st LO CO 10 C00 OO CO CO CO CO st SF SF SF SF SF oSB SF vw _ 2 gt lt lt lt lt 8 8 5 5 lt lt lt lt lt lt o9 22 gt 2 2 Document 38 05672 Rev B Page 2 of 16 Feedback CIPHESS PERFORM CY7C1346H Pin Definitions Name y o Description Ag Ay Input Address Inputs used to select one of the 64K address locations Sampled at the rising edge Synchronous of the CLK if ADSP or ADSC is active LOW and CE4 CEs and CE3 are sampled active A4 Ag feed the 2 bit counter BW BWp Input Byte Write Select Inputs active LOW Qualified with BWE to conduct Byte Writes to the SRAM BWc BWp Synchronous Sampled on the rising edge of CLK GW Input Global Write Enable Input active LOW When asserted LOW on the rising edge of CLK a global Synchronous
13. ames mentioned in this document may be trademarks of their respective holders Document 38 05672 Rev B Page 15 of 16 Cypress Semiconductor Corporation 2006 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Feedback CYPRESS PERFORM Document History Page CY7C1346H Document Title CY7C1346H 2 Mbit 64K x 36 Pipelined Sync SRAM Document Number 38 05672 REV ECN NO Issue Date Orig of Change Description of Change 347357 420879 459347 Document 38 05672 Rev B RXU NXR New Data s
14. ampled on the rising edge of CLK active LOW When asserted it Synchronous automatically increments the address in a burst cycle ADSP Input Address Strobe from Processor sampled on the rising edge of CLK active LOW When Synchronous asserted LOW is captured in the address registers A4 Ag are also loaded into the burst counter When ADSP and ADSC are both asserted only ADSP is recognized ASDP is ignored when CE is deasserted HIGH ADSC Input Address Strobe from Controller sampled on the rising edge of CLK active LOW When Synchronous asserted LOW A is captured in the address registers A4 Ap are also loaded into the burst counter When ADSP and ADSC are both asserted only ADSP is recognized ZZ Input ZZ Sleep Input active HIGH This input when HIGH places the device in a non time critical Asynchronous sleep condition with data integrity preserved For normal operation this pin has to be LOW or left floating ZZ pin has an internal pull down DQp I O Bidirectional Data I O lines As inputs they feed into an on chip data register that is triggered by DQc DQp Synchronous the rising edge of CLK As outputs they deliver the data contained in the memory location specified by A during the previous clock rise of the Read cycle The direction the pins is controlled by OE When OE is asserted LOW the pins behave as outputs When HIGH DQs DQPs are placed DQPc DQP in a tri state
15. condition Vpp Power Supply Power supply inputs to the core of the device Vss Ground Ground for the core of the device Document 38 05672 Rev B Page 3 of 16 Feedback CYPRESS PERFORM Pin Definitions continued CY7C1346H Name Description VDDQ Power Power supply for the I O circuitry Supply Vssq Ground Ground for the I O circuitry MODE Input Selects Burst Order When tied to GND selects linear burst sequence When tied to Vpp or left Static floating selects interleaved burst sequence This is a strap pin and should remain static during device operation Mode Pin has an internal pull up NC No Connects Not internally connected to the die 4M 9M 18M 72M 144M 288M 576M and 1G are address expansion pins and are not internally connected to the die Functional Overview All synchronous inputs pass through input registers controlled by the rising edge of the clock All data outputs pass through output registers controlled by the rising edge of the clock The CY7C1346H supports secondary cache in systems utilizing either a linear or interleaved burst sequence The interleaved burst order supports Pentium and i486 processors The linear burst sequence is suited for processors that utilize a linear burst sequence The burst order is user selectable and is determined by sampling the MODE input Accesses can be initiated with either the Processor Addr
16. ds to be supplied above Vpp minimum initially before a Read or Write operation can be initiated 14 tciz toeLz and are specified with AC test conditions shown in part b of AC Test Loads Transition is measured 200 mV from steady state voltage 15 At any given voltage and temperature tog is less than tog and toy is less than 7 to eliminate bus contention between SRAMs when sharing the same data bus These specifications do not imply a bus contention condition but reflect parameters guaranteed over worst case user conditions Device is designed to achieve High Z prior to Low Z under the same system conditions 16 This parameter is sampled and not 100 tested Document 38 05672 Rev B Page 10 of 16 Feedback CY7C1346H Switching Waveforms Read Cycle Timing 7 POU TO ovum e TU Nh E IW wiw ww we woes THT a VRAC M AMI twes Burst continued with I new base address me MEME zc M im T D OE burst t t OEHZ toon CHZ Cu gt lt gt AX oaza 3 Burst wraps around to its initial state Data Out Q 1 41 High Z Single READ gt BURST READ care UN
17. ected during a Byte Write operation will remain unaltered A synchronous self timed Write mechanism has been provided to simplify the Write operations Because the CY7C1346H is a common I O device the Output Enable OE must be deasserted HIGH before presenting data to the DQ inputs Doing so will tri state the output drivers As a safety precaution DQ are automatically tri stated whenever a Write cycle is detected regardless of the state of OE Single Write Accesses Initiated by ADSC ADSC Write accesses are initiated when the following condi tions are satisfied 1 ADSC is asserted LOW 2 ADSP is deasserted HIGH 8 CE4 CE are all asserted active and 4 the appropriate combination of the Write inputs GW BWE are asserted active to conduct a Write to the desired byte s ADSC triggered Write accesses require a single clock cycle to complete The address presented to A is loaded into the address register and the address advancement logic while being delivered to the memory array The ADV input is ignored during this cycle If a global Write is conducted the data presented to DQ is written into the corre sponding address location in the memory core If a Byte Write is conducted only the selected bytes are written Bytes not selected during a Byte Write operation will remain unaltered A synchronous self timed Write mechanism has been provided to simplify the Write operations Because the CY7C13
18. ess Strobe ADSP or the Controller Address Strobe ADSC Address advancement through the burst sequence is controlled by the ADV input A two bit on chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access Byte Write operations are qualified with the Byte Write Enable BWE and Byte Write Select BWia p inputs A Global Write Enable GW overrides all Byte Write inputs and writes data to four bytes All writes are simplified with on chip synchronous self timed Write circuitry Three synchronous Chip Selects CE3 and asynchronous Output Enable OE provide for easy bank selection and output tri state control ADSP is ignored if CE is HIGH Single Read Accesses This access is initiated when the following conditions are satisfied at clock rise 1 ADSP or ADSC is asserted LOW 2 are all asserted active and 3 the Write signals GW BWE are all deasserted HIGH ADSP is ignored if CE is HIGH The address presented to the address inputs A is stored into the address advancement logic and the address register while being presented to the memory array The corresponding data is allowed to propagate to the input of the output registers At the rising edge of the next clock the data is allowed to propagate through the output register and onto the data bus within tco if OE is active LOW The on
19. heet Converted from Preliminary to Final Changed address of Cypress Semiconductor Corporation on Page 1 from 3901 North First Street to 198 Champion Court Removed 133MHz Speed bin Changed three state to tri state Modified test condition from Vin lt Vpp to Vin lt Vpp Modified Input Load to Input Leakage Current except ZZ and MODE in the Electrical Characteristics Table Replaced Package Name column with Package Diagram in the Ordering Information table Replaced Package Diagram of 51 85050 from A to B Included 2 5V I O option Updated the Ordering Information table Page 16 of 16 Feedback
20. ite Bytes D B A Write Bytes D C Write Bytes D C A Write Bytes D C B Write All Bytes Write All Bytes rz Uu 18 0 _ W x 2 00 Document 38 05672 Rev B Page 7 of 16 Feedback CYPRESS PERFORM Maximum Ratings DC Input Voltage CY7C1 346H imped For aserauides Current into Outputs LOW eene 20 mA lines not tested Static Discharge gt 2001V Storage Temperature 65 to 150 Ambient Temperature with Latch up Current sene 2200 mA Power 55 to 125 Operating Range Supply Voltage on Vpp Relative to GND 0 5 to 4 6V Ambient Supply Voltage on Vppq Relative to GND 0 5V to Vpp Range Temperature Vpp Vppa DC Voltage Applied to Outputs Commercial 0 C to 70 3 3V 5 10 2 5V 5 Tri State 0 5V to 0 5V Industrial 40 to 85 C to Vpp Electrical Characteristics Over the Operating Range
21. ly exception occurs when the SRAM is emerging from a deselected state to a selected state its outputs are always tri stated during the first cycle of the access After the first cycle of the access the outputs are controlled by the OE signal Consecutive single Read cycles are supported Once the SRAM is deselected at clock rise by the chip select and either ADSP or ADSC signals its output will tri state immediately Document 38 05672 Rev B Single Write Accesses Initiated by ADSP This access is initiated when both of the following conditions are satisfied at clock rise 1 ADSP is asserted LOW and 2 CE are all asserted active The address presented to A is loaded into the address register and the address advancement logic while being delivered to the RAM array The Write signals GW BWE and BWia p and ADV inputs are ignored during this first cycle ADSP triggered Write accesses require two clock cycles to complete If GW is asserted LOW on the second clock rise the data presented to the DQ inputs is written into the corre sponding address location in the memory array If GW is HIGH then the Write operation is controlled by BWE and BWra p signals The CY7C1346H provides Byte Write capability that is described in the Write Cycle Descriptions table Asserting the Byte Write Enable input BWE with the selected Byte Write BWrA pj input will selectively write to only the desired bytes Bytes not sel
22. n Deselect Cycle None L X H L H L X X X L H Tri State Power down Sleep Mode None X X X H X X X X X X Tri State Power down READ Cycle External L H L L L X X X L L H Q Begin Burst READ Cycle External L H L L L X X X H L H Tri State Begin Burst WRITE Cycle External L H L L H L X L X L H D Begin Burst READ Cycle External L H L L H L X H L L H Q Begin Burst READ Cycle External L H L L H L X H H L H Tri State Begin Burst READ Cycle Next X X X L H L L H Q Continue Burst READ Cycle Next X X X L H H L H H L H Tri State Continue Burst READ Cycle Next H X X L X H L H L L H Q Continue Burst READ Cycle Next H X X L X H L H H L H Tri State Continue Burst WRITE Cycle Next X X X L H H L L X L H D Continue Burst WRITE Cycle Next H X X L X H L L X L H D Continue Burst READ Cycle Current X X X L H H H H L L H Q Suspend Burst READ Cycle Current X X X L H H H H H L H Tri State Suspend Burst READ Cycle Current H X X L X H H H L L H Q Suspend Burst READ Cycle Current H X X L X H H H H L H Tri State Suspend Burst Notes 2 X Don t Care H Logic HIGH L Logic LOW 3 WRITE L when any one or more Byte Write Enable signals BWA BWg BWc BWp and BWE L GW L WRITE when all Byte Write Enable signals BWA BWg BWc BWp BWE GW a a 4 The DQ pins are controlled by the current cycle and the OE signal OE is asynchronous and is not sampled with the clock 5 CE4 CE and are available only
23. rshoot lt Vpp 1 5V Pulse width less than 2 undershoot AC gt 2 Pulse width less than 2 9 Tpower up Assumes a linear ramp from OV to Vpp min within 200 ms During this time lt Vpp and lt Vpp Document 38 05672 Rev B Page 8 of 16 Feedback CYPRESS CY7C1346H Capacitance 100 TQFP Parameter Description Test Conditions Max Unit Cin Input Capacitance 25 C f 1 MHz 5 pF Vpp 3 3V Clock Input Capacitance 25 5 pF Cio Input Output Capacitance 5 pF Thermal Resistance 100 TQFP Parameter Description Test Conditions Package Unit OJA Thermal Resistance Test conditions follow standard test 30 32 C W Junction to Ambient methods and procedures for measuring a Thermal Resistance thermal impedance per EIA JESD51 685 C W Junction to Case AC Test Loads and Waveforms 3 3V I O Test Load R 3170 OUTPUT OUTPUT R 50Q 5 pF R 3510 M 1 5 INCLUDING JIG AND c a a scope 0 2 5V Test Load R 16670 OUTPUT OUTPUT 500 SPF 15380 Vr 1 25V INCLUDING D JIG AND SCOPE 5 Note 10 Tested initially and after any design or process change that may affect these parameters Document 38 05672 Rev B Page 9 of 16 Feedback ue 294
24. uired to enter into or exit from this sleep roe ae ie vs mode While in this mode data integrity is guaranteed 19 0 HE Accesses pending when entering the sleep mode are 00 01 10 11 considered valid is the completion of the operation 01 10 11 00 guaranteed The device must be deselected prior to entering 10 11 50 01 the sleep mode CE4 CEs CE3 ADSP and ADSC must remain inactive for the duration of tzzngc after the ZZ input 11 00 01 10 returns LOW ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min Max Unit Ippzz Sleep mode standby current ZZ gt Vpp 0 2V 40 mA 1775 Device operation to ZZ ZZ gt Vpp 0 2V 2tcyc ns tzzREC ZZ recovery time ZZ lt 0 2 2tcyc ns tzzi ZZ Active to sleep current This parameter is sampled 2tcvc ns 8771 ZZ Inactive to exit sleep current This parameter is sampled 0 ns Document 38 05672 Rev B Page 5 of 16 Feedback CYPRESO CY7C1346H PER P ORM Truth Table 2 3 4 5 6 7 Next Cycle Add Used CE CE CE ZZ ADSP ADSC ADV OE Deselect Cycle None H X X L X L X X X L H Tri State Power down Deselect Cycle None L L X L L X X X X L H Tri State Power down Deselect Cycle None L X H L L X X X X L H Tri State Power down Deselect Cycle None L L X L H L X X X L H Tri State Power dow
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