Cypress CY7C1316CV18 User's Manual
Contents
1. p 0 Bypass Register Dm 2 1 0 Selection s TDI nee Instruction Register Selection y TDO Circuitry ODD NTI Circuitry m 31 30 29 2 1 oO gt Identification Register 1106 2 10 Boundary Scan Register TCK TMS TAP Controller TAP Electrical Characteristics Over the Operating Range l9 11 12 Parameter Description Test Conditions Min Max Unit VoHi Output HIGH Voltage lon 2 0 mA 14 V VoH2 Output HIGH Voltage lon 100 pA 1 6 V Vout Output LOW Voltage lou 2 0 mA 0 4 V VoL2 Output LOW Voltage lou 100 pA 0 2 V Vin Input HIGH Voltage 0 65Vpp Vpp 0 3 V Vu Input LOW Voltage 0 3 0 35Vpp V lx Input and Output Load Current GND lt V x Vpp 5 5 HA Notes 10 These characteristics pertain to the TAP inputs TMS TCK TDI and TDO Parallel load levels are specified in the Electrical Characteristics Table 11 Overshoot Viy AC lt Vppq 0 85V Pulse width less than tcyc 2 Undershoot Vi AC gt 1 5V Pulse width less than tcyc 2 12 All Voltage referenced to Ground Document Number 001 07160 Rev E Page 15 of 29 Feedback Y PRESS PERFORM TAP AC Switching Characteristics CY7C1316CV18 CY7C1916CV18 CY7C1318CV18 CY7C1320CV18 Over the Operating Range 15 14 Parameter Description Min Ma2. Value Instruction Field Description CY7C1316CV18 CY7C1916CV18 CY7C1318CV18 CY7C1320CV18 Revision Number 000 000 000 000 Version number 31 29 Cypress Device ID 11010100010000101 11010100010001101 11010100010010101 11010100010100101 Defines the type of 28 12 SRAM Cypress JEDEC ID 00000110100 00000110100 00000110100 00000110100 Allows unique 11 1 identification of SRAM vendor ID Register 1 1 1 1 Indicates the Presence 0 presence of an ID register Scan Register Sizes Register Name Bit Size Instruction 3 Bypass 1 ID 32 Boundary Scan 107 Instruction Codes Instruction Code Description EXTEST 000 Captures the input and output ring contents IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO This operation does not affect SRAM operation SAMPLE Z 010 Captures the input and output contents Places the boundary scan register between TDI and TDO Forces all SRAM output drivers to a High Z state RESERVED 011 Do Not Use This instruction is reserved for future use SAMPLE PRELOAD 100 Captures the input and output ring contents Places the boundary scan register between TDI and TDO Does not affect the SRAM operation RESERVED 101 Do Not Use This instruction is reserved for future use RESERVED 110 Do Not Use This instruction is reserved for future use BYPASS 111 Places the bypass register between TDI and TDO T
3. Document Number 001 07160 Rev E Page 2 of 29 Feedback T ET dl CYPRESS PERFORM ki Logic Block Diagram CY7C1318CV18 CY7C1316CV18 CY7C1916CV18 CY7C1318CV18 CY7C1320CV18 AO Address Register Write Add Decode Control Write Add Decode A 18 0 Pes Address Register K K DOFF VREF R W Control MM Logic BWSrs gi i ry Write Write B s E 18 x x e o co 8 ta R W E E o lt lt ao Read Data Reg 36 gt ea T ca gt t Drs y o o E 36 3 2 x x a 8 8 3 gt gt Output R W D D o Logic lt lt tc C Read Data Reg ge gt pe ca M gt ca PL po DO55 0 Page 3 of 29 Document Number 001 07160 Rev E Feedback CY7C1316CV18 CY7C1916CV18 CY7C1318CV18 CY7C1320CV18 11 CQ DG3 NC NC 9 10 NC 36M NC NC 7 CYPRESS NC Pin Configuration 1 2 NC 72M 165 Ball FBGA 13 x 15 x 1 4 mm Pinout CY7C1316CV18 2M x 8 7 NC NC 144M NWS A NWS 5 6 K NC 288M K A 4 PERFORM The pin configuration for CY7C1316CV18 CY7C1916CV18 CY7C1318CV18 and CY7C1320CV18 follow 1 8 A NC NC NC NC
4. Static Discharge Voltage MIL STD 883 M 3015 gt 2001V Exceeding maximum ratings may impair the useful life of the device These user guidelines are not tested Latch up Current 2200 mA Storage Temperature 65 C to 150 C Operating Range Ambient Temperature with Power Applied 55 C to 125 C Ambient Supply Voltage on Vpp Relative to GND 0 5V to 2 9V Range Temperature TA Von Vonal Supply Voltage on Vppo Relative to GND 0 5V to Vpp Commercial 0 C to 70 C 1 8 0 1V 1 4V to DC Applied to Outputs in High Z 0 5V to Vppo 0 3V Industrial 40 C to 85 C VoD DC Input Voltage 1 0 5V to Vpp 0 3V Electrical Characteristics DC Electrical Characteristics Over the Operating Range 12 Parameter Description Test Conditions Min Typ Max Unit Vpp Power Supply Voltage 1 7 1 8 1 9 V VDDQ IO Supply Voltage 1 4 1 5 Vpp V Vou Output HIGH Voltage Note 16 Vppo 2 0 12 Vppo 2 0 12 V VoL Output LOW Voltage Note 17 Vppo 2 0 12 Vppo 2 0 12 V VoH Low Output HIGH Voltage lou 0 1 mA Nominal Impedance Vppo 0 2 VDDQ V VoLLow Output LOW Voltage lou 0 1 mA Nominal Impedance Vss 0 2 V Vin Input HIGH Voltage Vngr 0 1 Vppo 0 3 V Vu Input LOW Voltage 0 3 Vngr 0 1 V lx Input Leakage Current GND lt V s Vppo 5 5 pA loz Output Leakage Current GND lt V lt Vppo Output Disabled 5 5 uA VREF Input Reference Voltag
5. NC VREF DQ32 DOFF NC DQ23 NC NC DQ24 NC DQ33 DQ34 Q25 A TDI Page 5 of 29 NC NC D Feedback N C DQ35 DQ26 NC NC A NC TCK D V Z Tr ACIO nm Oo Om gt TDO Document Number 001 07160 Rev E CY7C1316CV18 CY7C1916CV18 P J CYPRESS CY7C1318CV18 CY7C1320CV18 PERFORM Pin Definitions Document Number 001 07160 Rev E Pin Name 10 Pin Description DQix 0 Input Output Data Input Output Signals Inputs are sampled on the rising edge of K and K clocks during valid write Synchronous operations These pins drive out the requested data during a read operation Valid data is driven out on the rising edge of both the C and C clocks during read operations or K and K when in single clock mode When read access is deselected Qr are automatically tri stated CY7C1316CV18 DO CY7C1916CV18 DQjg 0 CY7C1318CV18 DO7 o CY7C1320CV18 DQi35 0 LD Input Synchronous Load This input is brought LOW when a bus cycle sequence is defined This definition Synchronous includes address and read write direction All transactions operate on a burst of 2 data NWS Input Nibble Write Select 0 1 Active LOW CY7C1316CV18 only Sampled on the rising edge of the K NWS Synchronous and K clocks during write operations Used to select which nibble is written into t
6. Echo Clock2 Echo Clock4t2 Document Number 001 07160 Rev E Page 9 of 29 Feedback ER x CY7C1316CV18 CY7C1916CV18 WJ CYPRESS CY7C1318CV18 CY7C1320CV18 Truth Table The truth table for the CY7C1316CV18 CY7C1916CV18 CY7C1318CV18 and CY7C1320CV18 follows L 3 4 5 6 7 Operation K LD R W DO DQ Write Cycle L H L L D A1 at K t 1 T D A2 at K t 1 t Load address wait one cycle input write data on consecutive K and K rising edges Read Cycle L H L H Q A1 at C t 1 Q A2 at C t 2 t Load address wait one and a half cycle read data on consecutive C and C rising edges NOP No Operation L H H X High Z High Z Standby Clock Stopped Stopped X X Previous State Previous State Burst Address Table CY7C1318CV18 CY7C1320CV18 First Address External Second Address Internal X X0 X X1 X X1 X X0 Write Cycle Descriptions The write cycle description table for CY7C1316CV18 and CY7C1318CV18 follows L 8l BWSy BWS NWS NWS L L LH During the data portion of a write sequence CY7C1316CV18 both nibbles Dj7 9 are written into the device CY7C1318CV18 both bytes Dro are written into the device L L L H During the data portion of a write sequence CY7C1316CV18 both nibbles Dr oy are written into the device CY7C1318CV18 both bytes Deo are
7. NC VDDQ NC NC NC NC NC VREF DQ1 N DQ2 NC NC ZQ NC C NC DGO NC NC N C NC NC NC NC NC NC NC DQ4 NC DQ5 NC NC NC NC NC NC TMS TDI NC NC NC NC Vppa DOFF VREF NC NC NC NC 10 11 NC NC NC DQ6 NC 9 NC 36M NC NC NC NC A A 7 NC NC NC NC NC NC NC A NC DQ7 A CY7C1916CV18 2M x 9 6 NC 144M BWS NC NC NC TCK 5 NC A NC NC J v Z rx CT Oo nm Oo Oo wv gt TDO 4 AOI VDDQ NC NC CQ NC 288M VDDQ NC VREF DQ3 NC NC DQ2 NC NC ZQ NC 1 2 NC 72M A NC A A Vp Vpp V DQ DDQ VDDQ NC DQ1 NC NC DQO ca NC NC VDDQ NC NC NC NC NC VDDQ NC NC NC NC NC NC DQ4 NC NC NC VDDQ NC NC NC DQ8 NC NC NC DQ5 NC TMS NC NC Vppa NC VREF NC DOFF NC NC NC NC NC NC DQ6 NC TDI Page 4 of 29 NC NC NC A Feedback NC NC DQ7 A NC NC A NC TCK TDO D V Z Tr ACIO nm Oo Om gt Not 1 Document Number 001 07160 Rev E e NC 36M NC 72M NC 144M and NC 288M are not connected to the die and can be tied to any voltage level CY7C1316CV18 CY7C1916CV18 CY7C1318CV18 CY7C1320CV18
8. CY7C1318CV18 267BZXI CY7C1320CV18 267BZXI 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb Free 250 CY7C1316CV18 250BZC CY7C1916CV18 250BZC CY7C1318CV18 250BZC CY7C1320CV18 250BZC 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Commercial CY7C1316CV18 250BZXC CY7C1916CV18 250BZXC CY7C1318CV18 250BZXC CY7C1320CV18 250BZXC 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb Free CY7C1316CV18 250BZI CY7C1916CV18 250BZI CY7C1318CV18 250BZl CY7C1320CV18 250BZI 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Industrial CY7C1316CV18 250BZXI CY7C1916CV18 250BZXI CY7C1318CV18 250BZXI CY7C1320CV18 250BZXI 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb Free Document Number 001 07160 Rev E Page 26 of 29 Feedback 7 CYPRESS Ordering Information continued Not all of the speed package and temperature ranges are available Please contact your local sales representative or PERFORM visit www cypress com for actual products offered CY7C1316CV18 CY7C1916CV18 CY7C1318CV18 CY7C1320CV18 Ordering Code Package Diagram Package Type Operating Range CY7C1316CV18 200BZC CY7C1916CV18 200BZC CY7C1318CV18 200BZC CY7C1320CV18 200BZC 51 85180 165 Ball Fine Pitch Ball Grid
9. 11 CQ DQ8 NC NC DQ6 9 10 NC 36M NC DQ7 NC 7 CYPRESS NC V NC 18CV18 1M x 18 6 NC 144M A Pin Configuration continued CY7C13 1 2 NC 72M A NC A BWS NC 288M K 165 Ball FBGA 13 x 15 x 1 4 mm Pinout 7 5 K BWS 4 PERFORM The pin configuration for CY7C1316CV18 CY7C1916CV18 CY7C1318CV18 and CY7C1320CV18 follow 1 8 A DQ5 NC ZQ NC DQ3 DQ2 NC NC NC VREF DQ4 NC NC NC NC NC VDDQ NC DQ9 NC NC NC NC NC DQ10 NC DQ1 NC NC DQ11 NC NC DQO NC NC NC TDI NC DQ12 DQ13 V NC TMS NC Vppa VREF NC DOFF NC DQ14 A 1 10 NC DQ15 NC NC NC NC 8 9 A NC 72M NC NC DQ16 A NC 7 NC DQ17 NC NC DQ 17 A BWS A NC NC NC NC CY7C1320CV18 512K x 36 6 K NC DQ15 NC TCK 5 BWS A Vss NC NC TDO BWS NC N 1 CQ DQ8 DQ7 DQ16 DQ6 DQ5 C DQ14 ZQ DU Zi rx CT Oo nm Oo Oo wv gt 3 R W BWS VDDQ VDDQ NC V REF DO4 1 2 NC 144M NC 36M DQ18 A Vppa NC VDDQ DQ13 DQ12 DQ3 DQ2 ca DQ27 DQ28 VDDQ VDDQ NC NC NC NC 29 DQ19 V VDDQ NC DQ11 NC NC DQ DQ20 NC DQ21 NC NC VDDQ NC DQ1 DQ10 DQO DQ9 NC DQ30 DQ22 NC TMS NC DQ31 VDDQ
10. 29 Feedback Document Number 001 07160 Rev E EP CYPRESS PERFORM Functional Overview The CY7C1316CV18 CY7C1916CV18 CY7C1318CV18 and CY7C1320CV18 are synchronous pipelined Burst SRAMs equipped with a DDR interface which operates with a read latency of one and half cycles when DOFF pin is tied HIGH When DOFF pin is set LOW or connected to Vss the device behaves in DDR I mode with a read latency of one clock cycle Accesses are initiated on the rising edge of the positive input clock K All synchronous input timing is referenced from the rising edge of the input clocks K and K and all output timing is referenced to the rising edge of the output clocks C C or K K when in single clock mode All synchronous data inputs Dr g pass through input registers controlled by the rising edge of the input clocks K and K All synchronous data outputs Qix 0 pass through output registers controlled by the rising edge of the output clocks C C or K K when in single clock mode All synchronous control R W LD BWS x inputs pass through input registers controlled by the rising edge of the input clock K CY7C1318CV18 is described in the following sections The same basic descriptions apply to CY7C1316CV18 CY7C1916CV18 and CY7C1320CV18 Read Operations The CY7C1318CV18 is organized internally as two arrays of 512K x 18 Accesses are completed in a burst of two seguential 18 bit data words Read o
11. Update DR the value loaded into that shift register cell latches into the preload register When the EXTEST instruction is entered this bit directly controls the output Q bus pins Note that this bit is pre set HIGH to enable the output when the device is powered up and also when the TAP controller is in the Test Logic Reset state Heserved These instructions are not implemented but are reserved for future use Do not use these instructions Page 13 of 29 Feedback TAP Controller State Diagram id YPRESS PERFORM CY7C1316CV18 CY7C1916CV18 CY7C1318CV18 CY7C1320CV18 The state diagram for the TAP controller follows l TEST LOGIC RESET Y 1 TEST LOGIC 1 SELECT 1 SELECT IDLE A DR SCAN IR SCAN A 0 Y 0 1 CAPTURE DR CAPTURE IR 0 0 al SHIFT DR E SHIFT IR 0 y y 1 mi EXIT1 DR p EXIT1 IR y o Y PAUSE DR PAUSE IR 0 y Y 0 0 EXIT2 DR EXIT2 IR ty Y UPDATE DR r2 UPDATE IR r2 1 1 Y Y Ji Note 9 The 0 1 next to each state represents the value at TMS at the rising edge of TCK Document Number 001 07160 Rev E Page 14 of 29 Feedback CY7C1316CV18 CY7C1916CV18 CYPRESS CY7C1318CV18 CY7C1320CV18 PERFORM TAP Controller Block Diagram
12. continued Over the Operating Range 2 21 267 MHz 250 MHz 200 MHz 167 MHz Parameter Parameter soli Min Max Min Max Min Max Min Max Output Times tco tcHav C C Clock Rise or K K in single clock mode to 0 45 0 45 0 45 0 50 ns Data Valid tDoH tcHax Data Output Hold after Output C C Clock Rise 0 45 0 45 0 45 0 50 ns Active to Active tccao tcHcav C C Clock Rise to Echo Clock Valid 045 045 045 0 50 ns tcaoH tcHcax Echo Clock Hold after C C Clock Rise 0 45 F 0 458 045 0 50 ns tcap tconav Echo Clock High to Data Valid 0 27 030 0 35 040 ns icopoH ltcaHax Echo Clock High to Data Invalid 0 27 0 30 0 35 0 40 ns tcoH coco Output Clock CQ CQ HIGH 4 143 155 195 1245 ns coco ltcacan ICQ Clock Rise to CQ Clock Rise 143 155 1 95 245 ns rising edge to rising edge tcHz tcHaz Clock C C Rise to High Z 045 10 45 0 45 0 50 ns Active to High Z 25 28 terz tcHoxi Clock C C Rise to Low Z 25 26 0 45 0 45 0 45 050 ns DLL Timing tke Var tkc Var Clock Phase Jitter 020 0 20 020 0 20 ns tKG lock IC lock DLL Lock Time K C 1024 1024 1024 1024 Cycles tkc Reset IKC Reset K
13. must predefined manner to prevent undefined operations have low phase jitter which is specified as tkc var Power Up Sequence in DDR II SRAM m The DLL functions at frequencies down to 120 MHz Power Up Seguence ne m If the input clock is unstable and the DLL is enabled then the m Apply power and drive DOFF either HIGH or LOW all other DLL may lock onto an incorrect frequency causing unstable SRAM behavior To avoid this provide1024 cycles stable clock inputs can be HIGH or LOW a Apply Vpp before Vppo a Apply Vppo before Vggr or at the same time as Vngr a Drive DOFF HIGH m Provide stable DOFF HIGH power and clock K K for 1024 cycles to lock the DLL to relock to the desired clock frequency Figure 3 Power Up Waveforms 1 JU LU UP LU UT LT 7 K EJ A X a Ss sud s gt lt gt gt Unstable Clock gt 1024 Stable clock Start Normal Operation Clock Start Clock Starts after Vpp Vpp Stable Vbp Vppa Vpp Vppo Stable lt 0 1V DC per 50ns EE LC Fix High or tie to VDDQ Page 19 of 29 Document Number 001 07160 Rev E Feedback CY7C1316CV18 CY7C1916CV18 mE GE 7 CYPRESS CY7C1318CV18 CY7C1320CV18 PERFORM Maximum Ratings Current into Outputs LOW 20 mA
14. 16CV18 CY7C1916CV18 CY7C1318CV18 CY7C1320CV18 18 Mbit DDR II SRAM 2 Word Burst Architecture Document Number 001 07160 Submission Date See ECN See ECN Orig of Change NXR NXR ECN No 433284 462615 Description of Change New data sheet Changed try and t from 40 ns to 20 ns changed truss trois tes tTMSH tin tcu from 10 ns to 5 ns and changed trpov from 20 ns to 10 ns in TAP AC Switching Characteristics table Modified Power Up waveform Minor change Moved data sheet to web Converted from preliminary to final Updated Logic Block diagram Removed 300 MHz and 278 MHz speed bins Added 267 MHz speed bin Updated lpp lsg specs Changed DLL minimum operating frequency from 80MHz to 120MHz Changed teyc max spec to 8 4ns Modified footnotes 20 and 28 Changed Ambient Temperature with Power Applied from 10 C to 85 C to 55 to 125 C in the Maximum Ratings on page 20 Updated power up sequence waveform and its description Added footnote 19 related to Ipp Changed spec from 28 51 to 18 7 Changed Ojc spec from 5 91 to 4 5 Changed JTAG ID 31 29 from 001 to 000 VKN VKN AESA See ECN See ECN 503690 1523383 D 2507747 See ECN VKN PYRS E 2518624 See ECN NXR PYRS Sales Solutions and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices solution centers manufacturer s representative
15. 20CV18 PERFORM Package Diagram Figure 6 165 Ball FBGA 13 x 15 x 1 4 mm 51 85180 BOTTOM VIEW PIN 1 CORNER 2005 M V go2sMCAB PIN 1 CORNER I amp 90 50 85x 0 14 TOP VIEW N w P u L3 E o i Ss o a 6 5 4 3 N 1 A J 8000000000 d Ma B p eoooo oo0oo0oo0o0 c M 00000 00000 e 8 D o0000o oooooQo D E 00000 00000 fe F 00000 00000 r S 00000 00000 s 2 2 8 e T a s G Ge G H 8 J S 000000600000 p T k E 0000000000 L e 00000 00000 ft M m o 6 0 O0000o N OOOO0OO0OOGCOOOO In P Ooooooooooo P R 0000 00099 r A A 1 00 a 5 00 10 00 B j 13 00 0 10 B 41 13 00 0 10 A 0 15 4X e 8 z NOTES 3 i HI SOLDER PAD TYPE NON SOLDER MASK DEFINED NSMD wo i S PACKAGE WEIGHT 0 475g q JEDEC REFERENCE MO 216 DESIGN 4 6C t z i PACKAGE CODE BBOAC OT SEATING PLANE vo c 3 B 51 85180 A 3 Document Number 001 07160 Rev E Page 28 of 29 Feedback CY7C1316CV18 CY7C1916CV18 s CYPRESS CY7C1318CV18 CY7C1320CV18 PERFORM Document History Page Document Title CY7C13
16. 320CV18 A1 represents address location latched by the devices when transaction was initiated and A2 represents the addresses sequence in the burst On CY7C1316CV18 and CY7C1916CV18 A1 represents A 0 and A2 represents A 1 5 t represents the cycle at which a read write operation is started t 1 and t 2 are the first and second clock cycles succeeding the t clock cycle 6 Data inputs are registered at K and K rising edges Data outputs are delivered on C and C rising edges except when in single clock mode 7 Itis recommended that K K and C C HIGH when clock is stopped This is not essential but permits most rapid restart by overcoming transmission line charging symmetrically 8 Is based on a write cycle that was initiated in accordance with the Write Cycle Descriptions table NWS NWS BWS BWS BWS and BWS can be altered on different portions of a write cycle as long as the setup and hold requirements are achieved Document Number 001 07160 Rev E Page 10 of 29 Feedback CY7C1316CV18 CY7C1916CV18 7 CYPRESS CY7C1318CV18 CY7C1320CV18 PERFORM Write Cycle Descriptions The write cycle description table for CY7C1916CV18 follows 2 8 BWS K K Comments ia During the data portion of a write sequence the single byte Drg oy is written into the device L H During the data portion of a write sequence the single b
17. Array 13 x 15 x 1 4 mm CY7C1316CV18 200BZXC CY7C1916CV18 200BZXC CY7C1318CV18 200BZXC CY7C1320CV18 200BZXC CY7C1316CV18 200BZI CY7C1916CV18 200BZI CY7C1318CV18 200BZI CY7C1320CV18 200BZI 51 85180 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb Free 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Commercial Industrial CY7C1316CV18 200BZXI CY7C1916CV18 200BZXI CY7C1318CV18 200BZXI CY7C1320CV18 200BZXI 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb Free 167 CY7C1316CV18 167BZC CY7C1916CV18 167BZC CY7C1318CV18 167BZC CY7C1320CV18 167BZC 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Commercial CY7C1316CV18 167BZXC CY7C1916CV18 167BZXC CY7C1318CV18 167BZXC CY7C1320CV18 167BZXC 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb Free CY7C1316CV18 167BZI CY7C1916CV18 167BZl CY7C1318CV18 167BZl CY7C1320CV18 167BZI 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Industrial CY7C1316CV18 167BZXI CY7C1916CV18 167BZXI CY7C1318CV18 167BZXI CY7C1320CV18 167BZXI 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb Free Document Number 001 07160 Rev E Page 27 of 29 Feedback ke CY7C1316CV18 CY7C1916CV18 277 CYPRESS CY7C1318CV18 CY7C13
18. C or K or K in a single clock domain input clocks Writes are conducted with on chip synchronous self timed write circuitry Cypress Semiconductor Corporation Document Number 001 07160 Rev E 198 Champion Court Description 267 MHz 250 MHz 200 MHz 167 MHz Unit Maximum Operating Frequency 267 250 200 167 MHz Maximum Operating Current x8 775 705 575 490 mA x9 780 710 580 490 x18 805 730 600 510 x36 855 775 635 540 San Jose CA 95134 1709 408 943 2600 Revised June 18 2008 Feedback CY7C1316CV18 CY7C1916CV18 T E CYPRESS CY7C1318CV18 CY7C1320CV18 ki PERFORM Logic Block Diagram CY7C1316CV18 V T Write h Write A 19 0 Reg Reg 19 0 Address m a Register 3 La B 8 LD 8 z 8 O x x O ke co ke 2 z z z a E R W z c DOFF Read Data Reg VREF P gt ca RAW Control f ca 8 1 m 107 0 Logic Block Diagram CY7C1916CV18 ij T S Write Write A 19 0 Reg Reg Address m o Register pi ES o 9 LD 8 z z 8 A e x x O ke so o 5 K 2 x gt 8 z 5 a Output R W K ES Logic DOFF gt Read Data Reg VREF T a ca RW Control Mm ca Logic gt DQ
19. PERFORM Features m 18 Mbit density 2M x 8 2M x 9 1M x 18 512K x 36 m 267 MHz clock for high bandwidth m 2 word burst for reducing address bus frequency m Double Data Rate DDR interfaces data transferred at 534 MHz at 267 MHz m Two input clocks K and K for precise DDR timing a SRAM uses rising edges only m Two input clocks for output data C and C to minimize clock skew and flight time mismatches m Echo clocks CQ and CQ simplify data capture in high speed systems m Synchronous internally self timed writes m DDR II operates with 1 5 cycle read latency when the DLL is enabled m Operates similar to a DDR I device with 1 cycle read latency in DLL off mode m 1 8V core power supply with HSTL inputs and outputs m Variable drive HSTL output buffers m Expanded HSTL output voltage 1 4V Vpp m Available in 165 Ball FBGA package 13 x 15 x 1 4 mm m Offered in both Pb free and non Pb free packages m JTAG 1149 1 compatible test access port m Delay Lock Loop DLL for accurate data placement Configurations CY7C1316CV18 2M x 8 CY7C1916CV18 2M x 9 CY7C1318CV18 1M x 18 CY7C1320CV18 512K x 36 Selection Guide CY7C1316CV18 CY7C1916CV18 CY7C1318CV18 CY7C1320CV18 18 Mbit DDR II SRAM 2 Word Burst Architecture Functional Description The CY7C1316CV18 CY7C1916CV18 CY7C1318CV18 and CY7C1320CV18 are 1 8V Synchronous Pipelined SRAMs equipped with DDR II architecture The DDR II consists of a
20. Static to DLL Reset 30 30 30 30 ns Notes 24 These parameters are extrapolated from the input timing parameters tkHKH 250 ps where 250 ps is the internal jitter An input jitter of 200 ps tkc var is already included in the tkyKH These parameters are only guaranteed by design and are not tested in production 25 tez teiz are specified with a load capacitance of 5 pF as in b of AC Test Loads and Waveforms Transition is measured 100 mV from steady state voltage 26 At any voltage and temperature toyz is less than tc z and toyz less than tco Document Number 001 07160 Rev E Page 24 of 29 Feedback CY7C1316CV18 CY7C1916CV18 REP CYPRESS CY7C1318CV18 CY7C1320CV18 PERFORM Switching Waveforms Figure 5 Read Write Deselect Sequence 2 28 29 NOP READ READ 1 2 turn pr EAD w N Co D VO E i Sal em d KHKH gt f A ee A E A ZT Y A P A V TRS ot ol ES A ne ES tsc itc LHC Ur Wr vA Im TMT J Lr V gm mmm OO CHE R W ST ii CN BEJ b J z x S I tsa HA HD I O Q dentes DO SD I T Q00 ao a10 Q11 D21 i S D31 KHCH taz 1 tcap TA DA vas tKHCH tcyc KHKH E ee i 143 3415257 1734 1 tccao tCQOH amp g xod Wu ci xy 3 Le Frt
21. a write sequence only the byte Dr2g 1gj is written into the device D 7 oj and Dras 7 remains unaltered H H H L L H During the data portion of a write sequence only the byte Dr35 27j is written into the device Drog oj remains unaltered H H H L L H During the data portion of a write sequence only the byte D 35 27 is written into the device Drog oj remains unaltered L H No data is written into the device during this portion of a write operation L H No data is written into the device during this portion of a write operation Document Number 001 07160 Rev E Page 11 of 29 Feedback CYPRESS PERFORM IEEE 1149 1 Serial Boundary Scan JTAG These SRAMs incorporate a serial boundary scan Test Access Port TAP in the FBGA package This part is fully compliant with IEEE Standard 1149 1 2001 The TAP operates using JEDEC standard 1 8V IO logic levels Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature To disable the TAP controller TCK must be tied LOW Vss to prevent clocking of the device TDI and TMS are inter nally pulled up and may be unconnected They may alternatively be connected to Vpp through a pull up resistor TDO must be left unconnected Upon power up the device comes up in a reset state which does not interfere with the operation of the device Test Access Port Test Clock The test clock is used only with th
22. atic x36 330 250 MHz x8 300 mA x9 300 x18 300 x36 320 200 MHz x8 285 mA x9 285 x18 290 x36 300 167 MHz x8 280 mA x9 280 x18 285 x36 295 AC Electrical Characteristics Over the Operating Range 11 Parameter Description Test Conditions Min Typ Max Unit Vin Input HIGH Voltage Vrer 0 2 7 V Vi Input LOW Voltage Vrer 0 2 V Document Number 001 07160 Rev E Page 21 of 29 Feedback Capacitance Tested initially and after any design or process change that may affect these parameters CY7C1316CV18 CY7C1916CV18 CY7C1318CV18 CY7C1320CV18 Parameter Description Test Conditions Max Unit Cin Input Capacitance Ta 25 C f 1 MHz Vpp 1 8V Vppo 1 5V 5 pF Ccik Clock Input Capacitance 6 pF Co Output Capacitance 7 pF Thermal Resistance Tested initially and after any design or process change that may affect these parameters Ee se 165 FBGA Parameter Description Test Conditions Package Unit OJA Thermal Resistance Test conditions follow standard test methods and 18 7 C W Junction to Ambient procedures for measuring thermal impedance in jc Thermal Resistance accordance with EIA JESD51 45 C W Junction to Case Figure 4 AC Test Loads and Waveforms VREE 0 75V Vner o 0 75V OUTPUT Res a o 20 ALL INPUT PULSES Device R 5o0o0 OUTPUT 1 25V Under Device Oo fw NO Test Un
23. ce Deasserting the Byte Write Select input during the data portion of a write enables the data stored in the device for that byte to remain unaltered This feature can be used to simplify read modify write operations to a byte write operation Single Clock Mode The CY7C1318CV18 can be used with a single clock that controls both the input and output registers In this mode the device recognizes only a single pair of input clocks K and K that control both the input and output registers This operation is identical to the operation if the device had zero skew between the K K and C C clocks All timing parameters remain the same in this mode To use this mode of operation tie C and C HIGH at power on This function is a strap option and not alterable during device operation DDR Operation The CY7C1318CV18 enables high performance operation through high clock frequencies achieved through pipelining and double data rate mode of operation The CY7C1318CV18 requires a single No Operation NOP cycle when transitioning from a read to a write cycle At higher frequencies some appli cations may require a second NOP cycle to avoid contention If a read occurs after a write cycle address and data for the write are stored in registers The write information must be stored because the SRAM cannot perform the last word write to the array without conflicting with the read The data stays in this register until the next write cycle occurs On the fir
24. controller clock can only operate at a freguency up to 20 MHz while the SRAM clock operates more than an order of magnitude faster Because there is a large difference in the clock freguencies it is possible that during the Capture DR state an input or output undergoes a transition The TAP may then try to capture a signal while in transition metastable state This does not harm the device but there is no guarantee as to the value that is captured Repeatable results may not be possible To guarantee that the boundary scan register captures the correct value of a signal the SRAM signal must be stabilized long enough to meet the TAP controller s capture setup plus hold times tcs and toy The SRAM clock input might not be captured correctly if there is no way in a design to stop or slow the clock during a SAMPLE PRELOAD instruction If this is an issue it is still possible to capture all other signals and simply ignore the value of the CK and CK captured in the boundary scan register Once the data is captured it is possible to shift out the data by putting the TAP into the Shift DR state This places the boundary scan register between the TDI and TDO pins Document Number 001 07160 Rev E CY7C1316CV18 CY7C1916CV18 CY7C1318CV18 CY7C1320CV18 PRELOAD places an initial data pattern at the latched parallel outputs of the boundary scan register cells before the selection of another boundary scan test operation The shifting o
25. d The other five instructions are described in detail below Instructions are loaded into the TAP controller during the Shift IR state when the instruction register is placed between TDI and TDO During this state instructions are shifted through the instruction register through the TDI and TDO pins To execute the instruction once it is shifted in the TAP controller must be moved into the Update IR state Page 12 of 29 Feedback YPRESS PERFORM The IDCODE instruction loads a vendor specific 32 bit code into the instruction register It also places the instruction register between the TDI and TDO pins and shifts the IDCODE out of the device when the TAP controller enters the Shift DR state The IDCODE instruction is loaded into the instruction register at power up or whenever the TAP controller is supplied a Test Logic Reset state SAMPLE Z The SAMPLE Z instruction connects the boundary scan register between the TDI and TDO pins when the TAP controller is ina Shift DR state The SAMPLE Z command puts the output bus into a High Z state until the next command is supplied during the Update IR state SAMPLE PRELOAD SAMPLE PRELOAD is a 1149 1 mandatory instruction When the SAMPLE PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture DR state a snapshot of data on the input and output pins is captured in the boundary scan register The user must be aware that the TAP
26. der 5 pF 0 25V za Vper 0 75V test ZO l Slew Rate 2 V ns RQ RO 2500 2500 a INCLUDING JIG AND b SCOPE Note 20 Unless otherwise noted test conditions assume signal transition time of 2V ns timing reference levels of 0 75V Vpep 0 75V RQ 2500 Vppo 1 5V input pulse levels of 0 25V to 1 25V and output loading of the specified lo Ioj and load capacitance shown in a of AC Test Loads and Waveforms Document Number 001 07160 Rev E Page 22 of 29 Feedback mx CY7C1316CV18 CY7C1916CV18 CYPRESS CY7C1318CV18 CY7C1320CV18 PERFORM Switching Characteristics Over the Operating Range 2 21 Cypress Consortium 267 MHz 250 MHz 200 MHz 167 MHz SENTE EN parans sodi Min Max Min Max Min Max Min Max tPOWER Vpp Typical to the First Access 221 1 4 ht h 4 ms tcvc tKHKH K Clock and C Clock Cycle Time 8 75 8 4 4 0 8 4 5 0 8 4 6 0 84 ns tkH kHKL Input Clock K K and C C HIGH ib 16 ae Ba lt lt ans tk tKLKH Input Clock K K and C C LOW 15 16 20 24 ns tKHKH KUKH K Clock Rise to K Clock Rise and to C Rise 1 68 1 8 22 27 ns rising edge to rising edge tKHCH tKHCH K K Clock Rise to C C Clock Rise 0 00 1 68 0 00 1 8 0 00 2 2 0 00 2 7 ns rising edge to rising edge Setup Tim
27. e 78 Typical Value 0 75V 0 68 0 75 0 95 V IDD 19 Vpp Operating Supply Vpp Max 267 MHz x8 775 mA lour 0 mA x9 780 f fmax l tcvc X18 805 x36 855 250 MHz x8 705 mA x9 710 x18 730 x36 775 200 MHz x8 575 mA x9 580 x18 600 x36 635 167 MHz x8 490 mA x9 490 x18 510 x36 540 Notes 15 Power up assumes a linear ramp from OV to Vpp min within 200 ms During this time Vi lt Vpp and Vppo lt Vpp 16 Outputs are impedance controlled lo Vppo 2 RQ 5 for values of 1750 lt RQ lt 3500 17 Outputs are impedance controlled lo Vppq 2 RQ 5 for values of 1750 lt RQ lt 3500 18 VRer min 0 68V or 0 46Vppq whichever is larger VRep max 0 95V or 0 54Vppq whichever is smaller 19 The operation current is calculated with 50 read cycle and 50 write cycle Document Number 001 07160 Rev E Page 20 of 29 Feedback E CY7C1316CV18 CY7C1916CV18 YPRESS CY7C1318CV18 CY7C1320CV18 PERFORM Electrical Characteristics continued DC Electrical Characteristics Over the Operating Range 12 Parameter Description Test Conditions Min Typ Max Unit Ispi Automatic Power Down Max Vpp 267 MHz x8 305 mA Current Both Ports Deselected x9 305 Vin 2 Vin Or Vin S Vi f fyax Moyo x18 315 Inputs St
28. e TAP controller All inouts are captured on the rising edge of TCK All outputs are driven from the falling edge of TCK Test Mode Select TMS The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK This pin may be left unconnected if the TAP is not used The pin is pulled up inter nally resulting in a logic HIGH level Test Data In TDI The TDI pin is used to serially input information into the registers and can be connected to the input of any of the registers The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register For information on loading the instruction register see the TAP Controller State Diagram on page 14 TDI is internally pulled up and can be unconnected if the TAP is unused in an application TDI is connected to the most significant bit MSB on any register Test Data Out TDO The TDO output pin is used to serially clock data out from the registers The output is active depending upon the current state of the TAP state machine see Instruction Codes on page 17 The output changes on the falling edge of TCK TDO is connected to the least significant bit LSB of any register Performing a TAP Reset A Reset is performed by forcing TMS HIGH Vpp for five rising edges of TCK This Reset does not affect the operation of the SRAM and can be performed while the SRAM is operating At power up the TAP is reset inter
29. ecoo ia tCQOH gt COH DON T CARE RY UNDEFINED Notes 27 Q00 refers to output from address A0 Q01 refers to output from the next internal burst address following AO that is AO 1 28 Outputs are disabled High Z one clock cycle after a NOP 29 In this example if address A4 A3 then data Q40 D30 and Q41 D31 Write data is forwarded immediately as read results This note applies to the whole diagram Document Number 001 07160 Rev E Page 25 of 29 Feedback 7 CYPRESS PERFORM Ordering Information Not all of the speed package and temperature ranges are available Please contact your local sales representative or visit www cypress com for actual products offered CY7C1316CV18 CY7C1916CV18 CY7C1318CV18 CY7C1320CV18 Ordering Code Package Diagram Package Type Operating Range CY7C1316CV18 267BZC CY7C1916CV18 267BZC CY7C1318CV18 267BZC CY7C1320CV18 267BZC 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm CY7C1316CV18 267BZXC CY7C1916CV18 267BZXC CY7C1318CV18 267BZXC CY7C1320CV18 267BZXC CY7C1316CV18 267BZI CY7C1916CV18 267BZl CY7C1318CV18 267BZl CY7C1320CV18 267BZI 51 85180 51 85180 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Pb Free 165 Ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Commercial Industrial CY7C1316CV18 267BZXI CY7C1916CV18 267BZXI
30. es tsa tAVKH Address Setup to K Clock Rise 0 3 05 06 0 7 ns tsc tivKH Control Setup to K Clock Rise LD R W 0 3 05 06 07 ns tscDDR tivkH Double Data Rate Control Setup to Clock K K 0 3 035 04 05 ns Rise BWS BWS BWS BWS tsp 5 toy Dix 0 Setup to Clock K and K Rise 0 3 0 35 04 0 5 ns Hold Times tHa tKHAX Address Hold after K Clock Rise 0 3 105 0 6 0 7 ns tuc tkuix Control Hold after K Clock Rise LD R W 63 45 los 107 ns tHCDDR tKHIX Double Data Rate Control Hold after Clock K K 0 3 0 35 04 05 ns Rise BWS BWS BWS BWS tup tkHDx Dyx oj Hold after Clock K K Rise 0 3 10 35 10 4 05 ns Notes 21 When a part with a maximum freguency above 167 MHz is operating at a lower clock freguency it reguires the input timings of the freguency range in which it is being operated and outputs data with the output timings of that freguency range 22 This part has an internal voltage regulator tpower is the time that the power is supplied above Vpp minimum initially before a read or write operation can be initiated 23 For DQ2 data signal on CY7C1916CV18 device tsp is 0 5 ns for 200 MHz 250 MHz and 267 MHz frequencies Document Number 001 07160 Rev E Page 23 of 29 Feedback LE CY7C1316CV18 CY7C1916CV18 2 CYPRESS CY7C1318CV18 CY7C1320CV18 Switching Characteristics
31. f data for the SAMPLE and PRELOAD phases can occur concurrently when required that is while the data captured is shifted out the preloaded data can be shifted in BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift DR state the bypass register is placed between the TDI and TDO pins The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board EXTEST The EXTEST instruction drives the preloaded data out through the system output pins This instruction also connects the boundary scan register for serial access between the TDI and TDO in the Shift DR controller state EXTEST OUTPUT BUS TRI STATE IEEE Standard 1149 1 mandates that the TAP controller be able to put the output bus into a tri state mode The boundary scan register has a special bit located at bit 47 When this scan cell called the extest output bus tri state is latched into the preload register during the Update DR state in the TAP controller it directly controls the state of the output Q bus pins when the EXTEST is entered as the current instruction When HIGH it enables the output buffers to drive the output bus When LOW this bit places the output bus into a High Z condition This bit can be set by entering the SAMPLE PRELOAD or EXTEST command and then shifting the desired bit into that cell during the Shift DR state During
32. he device during the current portion of the write operations Nibbles not written remain unaltered NWS controls Dj3 9 and NWS controls Dj7 4 All the Nibble Write Selects are sampled on the same edge as the data Deselecting a Nibble Write Select ignores the corresponding nibble of data and it is not written into the device BWS Input Byte Write Select 0 1 2 and 3 Active LOW Sampled on the rising edge of the K and K clocks during BWS Synchronous write operations Used to select which byte is written into the device during the current portion of the Write BWS operations Bytes not written remain unaltered BWS CY7C1916CV18 BWS controls D g 0 CY7C1318CV18 BWS controls Dre oj and BWS controls Dyz CY7C1320CV18 BWS controls Drg oj BWS controls D 7 oy BWS controls Di26 18 and BWS controls Driaz o7 35 27 All the Byte Write Selects are sampled on the same edge as the data Deselecting a Byte Write Select ignores the corresponding byte of data and it is not written into the device A A0 Input Address Inputs These address inputs are multiplexed for both read and write operations Internally the Synchronous device is organized as 2M x 8 2 arrays each of 1M x 8 for CY7C1316CV18 and 2M x 9 2 arrays each of 1M x 9 for CY7C1916CV18 1M x 18 2 arrays each of 512K x 18 for CY7C1318CV18 and 512K x 36 2 arrays each of 256K x 36 for CY7C1320CV18 CY7C1316CV18 Because the least significant bit of the address
33. his operation does not affect SRAM operation Document Number 001 07160 Rev E Page 17 of 29 Feedback CY7C1316CV18 CY7C1916CV18 EP CYPRESS CY7C1318CV18 CY7C1320CV18 PERFORM Boundary Scan Order Bit Bump ID Bit Bump ID Bit Bump ID Bit Bump ID 0 6R 28 10G 56 6A 84 2J 1 6P 29 9G 57 5B 85 3K 2 6N 30 HF 58 5A 86 3J 3 7P 81 11G 59 4A 87 2K 4 7N 32 9F 60 5C 88 IK 5 7R 33 10F 61 4B 89 2L 6 8R 34 11E 62 3A 90 3L 7 8P 35 10E 63 1H 91 1M 8 9R 36 10D 64 1A 92 1L 9 11P 37 9E 65 2B 93 10 10P 38 10C 66 3B 94 3M 11 10N 39 11D 67 1C 95 1N 12 9P 40 9C 68 1B 96 2M 13 10M 41 9D 69 3D 97 3P 14 11N 42 11B 70 3C 98 2N 15 9M 43 ti 71 1D 99 2P 16 9N 44 9B 72 2C 100 1P 17 11L 45 10B 73 3E 101 3R 18 11M 46 11A 74 2D 102 4R 19 9L 47 Internal 75 2E 103 4P 20 10L 48 9A 76 1E 104 5P 21 11K 49 8B 77 2F 105 5N 22 10K 50 7C 78 3F 106 5R 23 9J 51 6C 79 1G 24 9K 52 8A 80 1F 25 10J 53 7A 81 3G 26 11J 54 7B 82 2G 27 11H 55 6B 83 1J Document Number 001 07160 Rev E Page 18 of 29 Feedback I CY7C1316CV18 CY7C1916CV18 cc IE 2 cypress CY7C1318CV18 CY7C1320CV18 PERFORM DLL Constraints DDR II SRAMs must be powered up and initialized in a DLL uses K clock as its synchronizing input The input
34. internally is a 0 only 20 external address inputs are needed to access the entire memory array CY7C1916CV18 Because the least significant bit of the address internally is a 0 only 20 external address inputs are needed to access the entire memory array CY7C1318CV18 A0 is the input to the burst counter These are incremented internally in a linear fashion 20 address inputs are needed to access the entire memory array CY7C1320CV18 A0 is the input to the burst counter These are incremented internally in a linear fashion 19 address inputs are needed to access the entire memory array All the address inputs are ignored when the appropriate port is deselected R W Input Synchronous Read Write Input When LD is LOW this input designates the access type read when Synchronous R W is HIGH write when R W is LOW for the loaded address R W must meet the setup and hold times around the edge of K C Input Clock Positive Input Clock for Output Data C is used in conjunction with C to clock out the read data from the device C and C can be used together to deskew the flight times of various devices on the board back to the controller See Application Example on page 9 for more information o Input Clock Negative Input Clock for Output Data C is used in conjunction with C to clock out the read data from the device C and C can be used together to deskew the flight times of various devices on the board back to the controller See A
35. n SRAM core with advanced synchronous peripheral circuitry and a one bit burst counter Addresses for read and write are latched on alternate rising edges of the input K clock Write data is registered on the rising edges of both K and K Read data is driven on the rising edges of C and C if provided or on the rising edge of K and K if C C are not provided Each address location is associated with two 8 bit words in the case of CY7C1316CV18 and two 9 bit words in the case of CY7C1916CV18 that burst sequentially into or out of the device The burst counter always starts with a 0 internally in the case of CY7C1316CV18 and CY7C1916CV18 For CY7C1318CV18 and CY7C1320CV18 the burst counter takes in the least significant bit of the external address and bursts two 18 bit words in the case of CY7C1318CV18 of two 36 bit words in the case of CY7C1320CV18 sequentially into or out of the device Asynchronous inputs include an output impedance matching input ZQ Synchronous data outputs Q sharing the same physical pins as the data inputs D are tightly matched to the two output echo clocks CQ CQ eliminating the need to capture data separately from each individual DDR SRAM in the system design Output data clocks C C enable maximum system clocking and data synchronization flexibility All synchronous inputs pass through input registers controlled by the K or K input clocks All data outputs pass through output registers controlled by the C or
36. nally to ensure that TDO comes up in a high Z state TAP Registers Registers are connected between the TDI and TDO pins to scan the data in and out of the SRAM test circuitry Only one register can be selected at a time through the instruction registers Data is serially loaded into the TDI pin on the rising edge of TCK Data is output on the TDO pin on the falling edge of TCK Document Number 001 07160 Rev E CY7C1316CV18 CY7C1916CV18 CY7C1318CV18 CY7C1320CV18 Instruction Register Three bit instructions can be serially loaded into the instruction register This register is loaded when it is placed between the TDI and TDO pins as shown in TAP Controller Block Diagram on page 15 Upon power up the instruction register is loaded with the IDCODE instruction It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section When the TAP controller is in the Capture IR state the two least significant bits are loaded with a binary 01 pattern to allow for fault isolation of the board level serial test path Bypass Register To save time when serially shifting data through registers it is sometimes advantageous to skip certain chips The bypass register is a single bit register that can be placed between TDI and TDO pins This enables shifting of data through the SRAM with minimal delay The bypass register is set LOW Vss when the BYPASS instruction is execu
37. nductor Corporation Cypress and is protected by United States copyright laws and international treaty provisions Cypress hereby grants to licensee a personal non exclusive and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in integrated circuit as specified in the applicable agreement Any reproduction modification translation compilation or represen the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATER charges and subject to worldwide patent protection United States and foreign non transferable license to copy use modify create derivative works of support of licensee product to be used only in conjunction with a Cypress ation of this Source Code except as specified above is prohibited without AL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Cypress reserves the right to make changes wi assume any liability arising out of the application or use of any product or circuit described herein Cypress does not authorize hout further notice to the materials described herein Cypress does not its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress product in a life support
38. nerated with respect to K The timing for the echo clocks is shown in Switching Characteristics on page 23 Application Example Figure 1 shows two DDR II used in an application CY7C1316CV18 CY7C1916CV18 CY7C1318CV18 CY7C1320CV18 DLL These chips use a Delay Lock Loop DLL that is designed to function between 120 MHz and the specified maximum clock freguency During power up when the DOFF is tied HIGH the DLL is locked after 1024 cycles of stable clock The DLL can also be reset by slowing or stopping the input clocks K and K for a minimum of 30 ns However it is not necessary to reset the DLL to lock it to the desired freguency The DLL automatically locks 1024 clock cycles after a stable clock is presented The DLL may be disabled by applying ground to the DOFF pin When the DLL is turned off the device behaves in DDR I mode with one cycle latency and a longer access time For information refer to the application note DLL Considerations in QDRIITV DDRII Figure 1 Application Example SRAM 1 Zo R 250ohms SRAM 2 zo R 2500hms DQ CQ CQ DQ CQ CQ A LD R W C CH K K LD R W C CH K KE Adda EN DQ BUS Addresses MASTER Cycle Start CPU R W i Or Return CLK lt ASIC Source CLK en Sala b Return CLK Vierm 0 75V 9 e Source CLKH L e Echo Clock1 Echo Clock 1
39. perations are initiated by asserting R W HIGH and LD LOW at the rising edge of the positive input clock K The address presented to address inputs is stored in the read address register and the least significant bit of the address is presented to the burst counter The burst counter increments the address in a linear fashion Following the next K clock rise the corresponding 18 bit word of data from this address location is driven onto Qr using C as the output timing reference On the subsequent rising edge of C the next 18 bit data word from the address location generated by the burst counter is driven onto Qi17 9 The requested data is valid 0 45 ns from the rising edge of the output clock C or C or K and K when in single clock mode 200 MHz and 250 MHz device To maintain the internal logic each read access must be allowed to complete Read accesses can be initiated on every rising edge of the positive input clock K The CY7C1318CV18 first completes the pending read transac tions when read access is deselected Synchronous internal circuitry automatically tri states the output following the next rising edge of the positive output clock C This enables a seamless transition between devices without the insertion of wait states in a depth expanded memory Write Operations Write operations are initiated by asserting R W LOW and LD LOW at the rising edge of the positive input clock K The address presented to address inputs is sto
40. pplication Example on page 9 for more information K Input Clock Positive Input Clock Input The rising edge of K is used to capture synchronous inputs to the device and to drive out data through Qro when in single clock mode All accesses are initiated on the rising edge of K K Input Clock Negative Input Clock Input K is used to capture synchronous data being presented to the device and to drive out data through Qr when in single clock mode Page 6 of 29 Feedback CY7C1316CV18 CY7C1916CV18 CY7C1318CV18 CY7C1320CV18 Pin Description CQ Referenced with Respect to C This is a free running clock and is synchronized to the input clock for output data C of the DDR II In single clock mode CQ is generated with respect to K The timing for 10 Output Clock the echo clocks is shown in Switching Characteristics on page 23 Pin Definitions continued ca Referenced with Respect to C This is a free running clock and is synchronized to the input clock for output data C of the DDR II In single clock mode CQ is generated with respect to K The timing for Pin Name CQ Output Clock the echo clocks is shown in Switching Characteristics on page 23 Output Impedance Matching Input This input is used to tune the device outputs to the system data bus impedance CQ CQ and Q 9 output impedance are set to 0 2 x RQ where RO is a resistor connected between ZQ and ground Alternatively this pin can be connec
41. red in the write address register and the least significant bit of the address is presented to the burst counter The burst counter increments the address in a linear fashion On the following K clock rise the data presented to D 47 9 is latched and stored into the 18 bit write data register provided BWS 9 are both asserted active On the subsequent rising edge of the negative input clock K the infor Document Number 001 07160 Rev E CY7C1316CV18 CY7C1916CV18 CY7C1318CV18 CY7C1320CV18 mation presented to Dr7 9j is also stored into the write data register provided BWS 4 are both asserted active The 36 bits of data are then written into the memory array at the specified location Write accesses can be initiated on every rising edge of the positive input clock K This pipelines the data flow such that 18 bits of data can be transferred into the device on every rising edge of the input clocks K and K When Write access is deselected the device ignores all inputs after the pending write operations are completed Byte Write Operations Byte write operations are supported by the CY7C1318CV18 A write operation is initiated as described in the Write Operations section The bytes that are written are determined by BWS and BWS which are sampled with each set of 18 bit data words Asserting the appropriate Byte Write Select input during the data portion of a write latches the data being presented and writes it into the devi
42. s and distributors To find the office closest to you visit us at cypress com sales Products PSoC Solutions PSoC psoc cypress com General psoc cypress com solutions Clocks 8 Buffers clocks cypress com Low Power Low Voltage psoc cypress com low power Wireless wireless cypress com Precision Analog psoc cypress com precision analog Memories memory cypress com LCD Drive psoc cypress com lcd drive Image Sensors image cypress com CAN 2 0b psoc cypress com can USB psoc cypress com usb Cypress Semiconductor Corporation 2006 2008 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against al Any Source Code software and or firmware is owned by Cypress Semico
43. st write cycle after the read s the stored data from the earlier write is written into the SRAM array This is called a posted write If a read is performed on the same address on which a write is performed in the previous cycle the SRAM reads out the most current data The SRAM does this by bypassing the memory array and reading the data from the registers Depth Expansion Depth expansion requires replicating the LD control signal for each bank All other control signals can be common between banks as appropriate Programmable Impedance An external resistor RQ must be connected between the ZQ pin on the SRAM and Vgg to enable the SRAM to adjust its output Page 8 of 29 Feedback SES Cypress PERFORM driver impedance The value of RO must be 5x the value of the intended line impedance driven by the SRAM The allowable range of RQ to guarantee impedance matching with a tolerance of 15 is between 1750 and 3509 with Vppq 1 5V The output impedance is adjusted every 1024 cycles at power up to account for drifts in supply voltage and temperature Echo Clocks Echo clocks are provided on the DDR II to simplify data capture on high speed systems Two echo clocks are generated by the DDR II CQ is referenced with respect to C and CQ is referenced with respect to C These are free running clocks and are synchro nized to the output clock of the DDR II In the single clock mode CQ is generated with respect to K and CQ is ge
44. systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Use may be limited by and subject to the applicable Cypress software license agreement Document Number 001 07160 Rev E QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress IDT NEC Renesas and are the trademarks of their respective holders Revised June 18 2008 Page 29 of 29 Samsung All product and company names mentioned in this document Feedback
45. ted Boundary Scan Register The boundary scan register is connected to all of the input and output pins on the SRAM Several No Connect NC pins are also included in the scan register to reserve pins for higher density devices The boundary scan register is loaded with the contents of the RAM input and output ring when the TAP controller is in the Capture DR state and is then placed between the TDI and TDO pins when the controller is moved to the Shift DR state The EXTEST SAMPLE PRELOAD and SAMPLE Z instructions can be used to capture the contents of the input and output ring The Boundary Scan Order on page 18 shows the order in which the bits are connected Each bit corresponds to one of the bumps on the SRAM package The MSB of the register is connected to TDI and the LSB is connected to TDO Identification ID Register The ID register is loaded with a vendor specific 32 bit code during the Capture DR state when the IDCODE command is loaded in the instruction register The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift DR state The ID register has a vendor code and other information described in Identification Register Definitions on page 17 TAP Instruction Set Eight different instructions are possible with the three bit instruction register All combinations are listed in Instruction Codes on page 17 Three of these instructions are listed as RESERVED and must not be use
46. ted directly to Vppq which enables the a O Input minimum impedance mode This pin cannot be connected directly to GND or left unconnected x 0 DLL Turn Off Active LOW Connecting this pin to ground turns off the DLL inside the device The timing in the DLL turned off operation is different from that listed in this data sheet For normal operation this pin can be connected to a pull up through a 10 KO or less pull up resistor The device behaves in DDR I mode when the DLL is turned off In this mode the device can be operated at a frequency of up to 167 Input MHz with DDR I timing DOFF TDO for JTAG TCK Pin for JTAG Not Connected to the Die Can be tied to any voltage level TDO Output TCK Input TDI Input TMS Input NC N A NC 36M N A NC 72M N A NC 144M N A NC 288M N A VREF Input Reference Vpp Power Supply Vss Ground VDDQ Power Supply TDI Pin for JTAG Not Connected to the Die Can be tied to any voltage level TMS Pin for JTAG Not Connected to the Die Can be tied to any voltage level Reference Voltage Input Static input used to set the reference level for HSTL inputs outputs and AC Not Connected to the Die Can be tied to any voltage level Not Connected to the Die Can be tied to any voltage level measurement points Power Supply Inputs to the Core of the Device Ground for the Device Power Supply Inputs for the Outputs of the Device Page 7 of
47. written into the device L H L H During the data portion of a write sequence CY7C1316CV18 only the lower nibble Dj3 9 is written into the device Dr7 remains unaltered CY7C1318CV18 only the lower byte Djg o Is written into the device Dr7 9j remains unaltered L H LH During the data portion of a write sequence CY7C1316CV18 only the lower nibble Dis oj is written into the device Dr 4j remains unaltered CY7C1318CV18 only the lower byte Dje oj is written into the device Dr7 9j remains unaltered H L L H During the data portion of a write sequence CY7C1316CV18 only the upper nibble Drz 4 is written into the device Dj 9j remains unaltered CY7C1318CV18 only the upper byte Duos is written into the device Djg o remains unaltered H L L H During the data portion of a write sequence CY7C1316CV18 only the upper nibble D 7 4 is written into the device Djs 9j remains unaltered CY7C1318CV18 only the upper byte Dos is written into the device Dig o remains unaltered K K Comments H H LH No data is written into the devices during this portion of a write operation H H L H No data is written into the devices during this portion of a write operation Notes 2 X Don t Care H Logic HIGH L Logic LOW f represents rising edge 3 Device powers up deselected with the outputs in a tri state condition 4 On CY7C1318CV18 and CY7C1
48. x Unit treyc TCK Clock Cycle Time 50 ns trp TCK Clock Freguency 20 MHz tty TCK Clock HIGH 20 ns tn TCK Clock LOW 20 ns Setup Times truss TMS Setup to TCK Clock Rise 5 ns trois TDI Setup to TCK Clock Rise 5 ns tes Capture Setup to TCK Rise 5 ns Hold Times trusH TMS Hold after TCK Clock Rise 5 ns trpiH TDI Hold after Clock Rise 5 ns tcu Capture Hold after Clock Rise 5 ns Output Times trpov TCK Clock LOW to TDO Valid 10 ns trpox TCK Clock LOW to TDO Invalid 0 ns TAP Timing and Test Conditions Figure 2 shows the TAP timing and test conditions Notes 14 Figure 2 TAP Timing and Test Conditions 0 9V ALL INPUT PULSES 500 b 0 9V TDO Bi Zo 500 L C 20 pF a GND TH me qra m Test Clock X m MU mi TCK revo trusH pesi e truss Test Mode Select TYE C NI ji TDIS Test Data In a TDI s NA a XE Test Data Out TDO trpov trpox 13 tcs and toy refer to the setup and hold time requirements of latching data from the boundary scan register 14 Test conditions are specified using the load in TAP AC Test Conditions tp tp lt 1 ns Document Number 001 07160 Rev E Page 16 of 29 Feedback a L E ed J CYPRESS PER FORM Identification Register Definitions CY7C1316CV18 CY7C1916CV18 CY7C1318CV18 CY7C1320CV18
49. yte Djg o is written into the device No data is written into the device during this portion of a write operation LL Er T d L H No data is written into the device during this portion of a write operation Write Cycle Descriptions The write cycle description table for CY7C1320CV18 follows L 8l BWS BWS BWS BWS3 K K Comments L L L L L H During the data portion of a write sequence all four bytes Dy35 oj are written into the device L L B L L H During the data portion of a write sequence all four bytes Dy35 oj are written into the device L H H H L H During the data portion of a write sequence only the lower byte Drg oj is written into the device D 35 gj remains unaltered L H H H L H During the data portion of a write sequence only the lower byte Dyg oj is written into the device D 35 oj remains unaltered H L H H L H During the data portion of a write sequence only the byte D7 9 is written into the device Dig and Dj35 18 remains unaltered H L H H L H During the data portion of a write sequence only the byte Dr 7 9 is written into the device Dyg oj and Dj35 18 remains unaltered H H L H L H During the data portion of a write sequence only the byte D 2g 18j is written into the device Dr 7 9j and Djss 27 remains unaltered H H L H L H During the data portion of
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