Cypress CY7C1303BV25 User's Manual
Contents
1. Feedback YE CY7C1303BV25 CY7C1306BV25 Wns O D y de de PERFORM Boundary Scan Order Bump ID 11B Document 38 05627 Rev A Page 14 of 19 Feedback CY7C1303BV25 e CY7C1306BV25 PERFORM Maximum Ratings DC Input Voltagel 7 rodeo E E 0 5V to Vpp 0 5V Above which the usetuliiremay be Impaked ORLING Outputs LOW asias 20 mA Static Discharge Voltage ooccccccccocococncnnnccccononnnons gt 2001V Storage Temperature cceeeeeeeeeeeees 65 C to 150 C Ambient Temperature with Power Applied ccccccccccceccceceeeeeeeeeeeeeaeeees 55 C to 125 C Supply Voltage on Vpp Relative to GND 0 5V to 3 6V Supply Voltage on Vppg Relative to GND 0 5V to Vpp DC Applied to Outputs in High Z State per MIL STD 883 Method 3015 Latch up CurTOlMt oocccccnnnccccccccncncnnnonnnnnononononononononans Operating Range Ambient Range Temperature Ta pp Vona 0 5V to VDDQ 0 5V Electrical Characteristics Over the Operating Rangel Comi 0 C to 70 C EN 1 4V to 1 9V 40 C to 85 C DC Electrical Characteristics Over the Operating Range Parameter Description tesitondiion Min 1p Wer ui Voa VO Supply Votage o f a e e y Von Output HIGH Votage Noes vooo 0 Vooo 0e V c CTI LEC O UTE Voncom Output HIGH Votage Ion 01 mA Nominal impedance Vopa 02 Vooo V Voom Ou LOW Vege ll 0 1 mA K2. C E YPRE S S CY7C1303BV25 gt CY7C1306BV25 PERFORM MMMM 18 Mbit Burst of 2 Pipelined SRAM with QDR Architecture Features Functional Description e Separate independent Read and Write data ports The CY7C1303BV25 and CY7C1306BV25 are 2 5V Supports concurrent transactions Synchronous Pipelined SRAMs equipped with QDR archi 167 MHz Clock for hiah bandwidth tecture QDR architecture consists of two separate ports to O ee access the memory array The Read port has dedicated Data 2 5 ns Clock to Valid access time Outputs to support Read operations and the Write Port has 2 Word Burst on all accesses dedicated Data inputs to support Write operations Access to each port is accomplished through a common address bus GP ie ee see fi ae oa The Read address is latched on the rising edge of the K clock rite Ports data transferred at 333 MHz 16 a and the Write address is latched on the rising edge of K clock Two input clocks K and K for precise DDR timing QDR has separate data inputs and data outputs to completely SRAM uses rising edges only eliminate the need to turn around the data bus required with Twoi locks f d Cand EE common l O devices Accesses to the CY7C1303BV25 a pe pie ata val to minimize CY7C1306BV25 Read and Write ports are completely clock skew and flight time mismatches independent of one another All accesses are initiated Single multiplexed address input bus latches address synchronously on the
3. Wns C operation is identical to the operation if the device had zero skew between the K K and C C clocks All timing parameters remain the same in this mode To use this mode of operation the user must tie C and C HIGH at power up This function is a strap option and not alterable during device operation Concurrent Transactions The Read and Write ports on the CY7C1303BV25 operate completely independently of one another Since each port latches the address inputs on different clock edges the user can Read or Write to any location regardless of the trans action on the other port Also reads and writes can be started in the same clock cycle If the ports access the same location at the same time the SRAM will deliver the most recent infor mation associated with the specified address location This includes forwarding data from a Write cycle that was initiated on the previous K clock rise Application Example CY7C1303BV25 CY7C1306BV25 Depth Expansion The CY7C1303BV25 has a Port Select input for each port This allows for easy depth expansion Both Port Selects are sampled on the rising edge of the Positive Input Clock only K Each port select input can deselect the specified port Deselecting a port will not affect the other port All pending transactions Read and Write will be completed prior to the device being deselected Programmable Impedance An external resistor
4. vena j vos ves voo vooa ne j 08 os E no os ois vooo vss vss vss vovo ne ne 02 Cne f ore vss vss vss y MSN KANE E MEE MC A O AA CY7C1306BV25 512K x 36 E AC E A AO PANA A AO Man NG Beer SO Pie O L Wet 00 07 6 E 107 22 00 4571 2712471211 nel er _ Db des Ape aro vss vss vss vss vss aie Dis 07 ae et a AM MEA _F oso es ba vopa VDD vss VDD vopa Dia Qs 05 a boo oa ae vena voo ves woo vona ais br os Lod NG Er ETE COIE AE De fee ee E ee ee ee ee A ee ee ee veo eb ene er LL pas es bea vopa vss vss vss vopa Dir an 02 QM 033 Gea bes vss vss vss vss vss Dio a1 02 a ee ee ee 1007 Le oe oe ee 0 eA ee 107 BEI SESE BE Pe SE PERE SE ELS Document 38 05627 Rev A Page 3 of 19 Feedback CY7C1303BV25 CYPRESS OYZCABO6BV25 PERFORM Pin Definitions Input Data input signals sampled on the rising edge of K and K clocks during valid write opera Synchronous tions CY7C1303BV25 D 17 0 CY7C1306BV25 Di35 0 Dix 0 Input Write Port Select active LOW Sampled on the rising edge ofthe K clock When asserted active Y VS 4 Synchronous a Write operation is initiated Deasserting will deselect the Write port Deselecting the Write port will cause D z py to be ignored BWSo BWS Input Byte Write Select 0 1 2 and 3 active LOW Sampled on th
5. remains unaltered No data is written into the device during this portion of a write operation No data is written into the device during this portion of a write operation Comments During the Data portion of a Write sequence all four bytes D 35 p are written into the device During the Data portion of a Write sequence all four bytes Dj35 p are L H L H L H written into the device Ea During the Data portion of a Write sequence only the lower byte Dig 0 is written into the device Dy35 9 will remain unaltered H During the Data portion of a Write sequence only the lower byte Drg p7 is written into the device Dy35 9 will remain unaltered During the Data portion of a Write sequence only the byte D 7 9 is written into the device D g p and D y35 48 will remain unaltered L L L H During the Data portion of a Write sequence only the byte Dj47 9 is written into the device Drg p and Dj35 48 Will remain unaltered L L During the Data portion of a Write sequence only the byte D gt g 8 is written into the device Dry7 p and Dy35 27 will remain unaltered During the Data portion of a Write sequence only the byte D gt g 18 is written into the device Dy 47 9 and D 35 gt 71 will remain unaltered During the Data portion of a Write sequence only the byte D 35 277 is NA oo into the device Di gt 6 p will remain unaltered a Di35 27 IS H During the Data portion of a Wri
6. Ground Ground for the device Power Supply Power supply inputs for the outputs of the device Introduction Functional Overview The CY7C1303BV25 CY7C1306BV25 are synchronous pipelined Burst SRAM equipped with both a Read port and a Write port The Read port is dedicated to Read operations and the Write port is dedicated to Write operations Data flows into the SRAM through the Write port and out through the Read port These devices multiplex the address inputs in order to minimize the number of address pins required By having separate Read and Write ports this architecture completely eliminates the need to turn around the data bus and avoids any possible data contention thereby simplifying system design 38 05627Each access consists of two 18 bit data transfers in the case of CY7C1303BV25 and two 36 bit data transfers in the case of CY7C1306BV25 in one clock cycle Accesses for both ports are initiated on the rising edge of the Positive Input Clock K All synchronous input timing is refer enced from the rising edge of the input clocks K and K and all output timings are referenced to rising edge of output clocks C and C or K and K when in single clock mode All synchronous data inputs Dix 0 Pass through input registers controlled by the rising edge of the input clocks K and K All synchronous data outputs Qix 0 Pass through output registers controlled by the rising edge of the output clocks C and C or K and K
7. Jose CA 95134 1709 e 408 943 2600 Document 38 05627 Rev A Revised April 3 2006 Feedback Ze CY7C1303BV25 s CYPRESS CY7C1306BV25 PERFORM Logic Block Diagram CY7C1303BV25 Di17 0 Write Write gt Data Reg gt Data Reg Address Register i Address Airs Register 19 pa 512Kx18 512Kx18 Memory Memory Array Array Write Add Decod Read Add Decode Control Logic Logic Block Diagram CY7C1306BV25 Write Write gt Data Reg gt Data Reg Address p E Register Dr35 0 e 256Kx36 256Kx36 Memory Memory Array Array Write Add Decod Read Add Decode Control Logic Selection Guide CY7C1303BV25 167 CY7C1306BV25 167 Document 38 05627 Rev A Page 2 of 19 Feedback CY7C1303BV25 CYPRESS CY7C1306BV25 PERFORM Pin Configuration 165 ball FBGA 13 x 15 x 1 4 mm Pinout CY7C1303BV25 1M x 18 type fs 7 typ sy ey 7p eye yy wp A no enarraan NGrseM WPS EWS K NO RPS e w m o0 ves AAA S NG o ne on oo vss vss vss vss vss ne NC nce no on vooa vss vss vss vooa no me e no oz oe vooa voo vss voo vona no No e ne me os vooa voo vss voo vona no No 05 MM MOM A A 112 01 Ee 62 Ne O D8 gt a ne veer voa vona von vss vop vovo vona vaer za 3 ne ne om vooa voo vss voo vona No o oa x e Ne ate
8. can occur concurrently when required that is while data captured is shifted out the preloaded data can be shifted in Document 38 05627 Rev A CY7C1303BV25 CY7C1306BV25 BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift DR state the bypass register is placed between the TDI and TDO pins The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board EXTEST The EXTEST instruction enables the preloaded data to be driven out through the system output pins This instruction also selects the boundary scan register to be connected for serial access between the TDI and TDO in the shift DR controller state EXTEST Output Bus Tri state IEEE Standard 1149 1 mandates that the TAP controller be able to put the output bus into a tri state mode The boundary scan register has a special bit located at bit 47 When this scan cell called the extest output bus tri state is latched into the preload register during the Update DR state in the TAP controller it will directly control the state of the output Q bus pins when the EXTEST is entered as the current instruction When HIGH it will enable the output buffers to drive the output bus When LOW this bit will place the output bus into a High Z condition This bit can be set by entering the SAMPLE PRELOAD or EXTEST command and then shif
9. o y Var Output Low Votage fazom a v Vow Output LOWVotage fosoa ooo Vie nput GH Votage a ig vu pato Wvotage oo SYS TAP AC Switching Characteristics Over the Operating Rangel t 12 A E E A CI A O CN CI O Set up Times SE mm O E TDI Set up to TCK clock Rise los Sapte Setup to TOK Ae 0 usn TMS Hold aer TOK Glock Rise JO Js From TDT Hoidafer look Rise A Ys n Capture Hold afer lock Rise O Ys Notes 10 These characteristic pertain to the TAP inputs TMS TCK TDI and TDO Parallel load levels are specified in the Electrical Characteristics table 11 tcs and tcy refer to the set up and hold time requirements of latching data from the boundary scan register 12 Test conditions are specified using the load in TAP AC test conditions tp te 1 ns Document 38 05627 Rev A Page 11 of 19 Feedback es CY7C1303BV25 CYPRESS CY 7C1306BV25 Q PERFORM TAP AC Switching Characteristics Over the Operating Range 121 continued Parameter Desp mn Output Times toov TCK Clock LOW to TOO Vali afe roo TCK Clock LOW to TDO invalid os TAP Timing and Test Conditions 1 25V 500 ALL INPUT PULSES aa 2 5V 9 900 LH 1 25V 20 pF C 20p ov a G lt I Test Clock EN f Ff TCK TDO 6 I Test Mode Select TMS Test Data In TDI Test Data Out TDO ttpox ttpov Identification Register Definitions Cypress Device ID 28 12 01011010010010101 010
10. rising edge of the positive input clock inputs for both Read and Write ports K In order to maximize data throughput both Read and Write ports are equipped with Double Data Rate DDR inter P l f h pepo EON Beier ven een faces Therefore data can be transferred into the device on Synchronous internally self timed writes every rising edge of both input clocks K and K and out of the 2 5V core power supply with HSTL Inputs and Outputs device on every rising edge of the output clock C and GC or K l A E and K when in single clock mode thereby maximizing perfor Available in 165 ball FBGA package 13 x 15 x 1 4 mm mance while simplifying system design Each address location Variable drive HSTL output buffers is associated with two 18 bit words CY7C1303BV25 or two Expanded HSTL output voltage 1 4V 1 9V 36 bit words CY7C1306BV25 that burst sequentially into or out of the device JTAG Interface o Depth expansion is accomplished with a Port Select input for Variable Impedance HSTL each port Each Port Selects allow each port to operate Configurations eee T All synchronous inputs pass through input registers controlled CY7C1303BV25 1M x 18 by the K or K input clocks All data outputs pass through output registers controlled by the C or C input clocks Writes are CY7C1306BV25 512K x 36 conducted with on chip synchronous self timed write circuitry Cypress Semiconductor Corporation 198 Champion Court San
11. when in single clock mode All synchronous control RPS WPS BWS 0 inputs pass through input registers controlled by the rising edge of input clocks K and K The following descriptions take CY7C1303BV25 as an example The same basic descriptions apply to CY7C1306BV25 Read Operations The CY7C1303BV25 is organized internally as 2 arrays of 512K x 18 Accesses are completed in a burst of two sequential 18 bit data words Read operations are initiated by asserting RPS active at the rising edge of the positive input clock K The address is latched on the rising edge of the K clock Following the next K clock rise the corresponding lower order 18 bit word of data is driven onto the Qy7 p using C as Document 38 05627 Rev A the output timing reference On the subsequent rising edge of C the higher order data word is driven onto the Qpy7 9 The requested data will be valid 2 5 ns from the rising edge of the output clock C and C or K and K when in single clock mode 250 MHz device Synchronous internal circuitry will automatically three state the outputs following the next rising edge of the positive output clock C This will allow for a seamless transition between devices without the insertion of wait states in a depth expanded memory Write Operations Write operations are initiated by asserting WPS active at the rising edge of the positive input clock K On the same K clock rise the data presented to D 47 0 is l
12. 11010010100101 Defines the type of SRAM Cypress JEDEC ID 11 1 00000110100 00000110100 Allows unique identification of SRAM vendor ID Register Presence 0 Indicate the presence of an ID register Document 38 05627 Rev A Page 12 of 19 Feedback Fe CY7C1303BV25 CY7C1306BV25 Wns O D y de de PERFORM Scan Register Sizes Register Name BS poo o f e Boundary Scan Instruction Codes EXTEST 000 Captures the Input Output ring contents the Input Output Captures the Input Output ring contents contents IDCODE _ hap the ID register with the vendor ID code and places the register between TDI and TDO This operation does not affect SRAM operation SAMPLE Z Captures the Input Output contents Places the boundary scan register between TDI and TDO Forces all SRAM output drivers to a High Z state RESERVED Do Not Use This instruction is reserved for future use Not Use This instruction is reserved for future use a 100 AAA II the Input Output ring contents Places the boundary scan register between TDI and TDO Does not affect the SRAM operation RESERVED Do Not Use This instruction is reserved for future use Not Use This instruction is reserved for future use o accio Not Use This instruction is reserved for future use BYPASS 111 Places the bypass register between TDI and TDO This operation does not affect SRAM operation Document 38 05627 Rev A Page 13 of 19
13. 25 Q 35 0 Input Read Port Select active LOW Sampled on the rising edge of positive input clock K When Synchronous active a Read operation is initiated Deasserting will cause the Read port to be deselected When deselected the pending access is allowed to complete and the output drivers are automatically three stated following the next rising edge of the K clock Each read access consists of a burst of two sequential 18 bit or 36 bit transfers nput Clock Positive Input Clock for Output Data C is used in conjunction with C to clock out the Read data from the device C and C can be used together to deskew the flight times of various devices on the board back to the controller See application example for further details z Input Clock Negative Input Clock for Output Data C is used in conjunction with C to clock out the Read data from the device C and C can be used together to deskew the flight times of various devices on the board back to the controller See application example for further details nput Clock Positive Input Clock Input The rising edge of K is used to capture synchronous inputs to the device and to drive out data through Qyy o when in single clock mode All accesses are initiated on the rising edge of K Input Clock Negative Input Clock Input K is used to capture synchronous inputs to the device and to drive out data through Qy 9 when in single clock mode Input Output Impedance Matchi
14. ASES OO Oo Oo oC E 0 0000 0 00 0 000 c a o oo 0 00 000 00 D COO 0000000 E oD oO Oo 6 Oo Oo oS F 00000 00000 G o Jo S if I CO e 0 6 S 0 0 H S 0000003000 00000000000 K o 00000000000 L a ES O 0 000 0000 00 M Oe OOO 0 0 0 00 oO N Oooo oo ooo oo p o 00000000000 R LA 100 E 5 00 10 00 B H 13 00 0 10 CM 0 15 4X NOTES SOLDER PAD TYPE NON SOLDER MASK DEFINED NSMD PACKAGE WEIGHT 0 4759 JEDEC REFERENCE MO 216 DESIGN 4 6C PACKAGE CODE BBOAC 51 85180 A Quad Data Rate SRAM and QDR SRAM comprise a new family of products developed by Cypress IDT NEC Renesas and Samsung All products and company names mentioned in this document may be the trademarks of their respective holders Document 38 05627 Rev A Page 18 of 19 O Cypress Semiconductor Corporation 2006 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be exp
15. Column with Package Diagram Document 38 05627 Rev A Page 19 of 19 Feedback
16. P controller All inputs are captured on the rising edge of TCK All outputs are driven from the falling edge of TCK Test Mode Select The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK It is allowable to leave this pin unconnected if the TAP is not used The pin is pulled up internally resulting in a logic HIGH level Test Data In TDI The TDI pin is used to serially input information into the registers and can be connected to the input of any of the registers The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register For information on loading the instruction register see the TAP Controller State Diagram TDI is internally pulled up and can be unconnected if the TAP is unused in an application TDI is connected to the most significant bit MSB on any register Test Data Out TDO The TDO output pin is used to serially clock data out from the registers The output is active depending upon the current state of the TAP state machine see Instruction codes The output changes on the falling edge of TCK TDO is connected to the least significant bit LSB of any register Performing a TAP Reset A Reset is performed by forcing TMS HIGH Vpp for five rising edges of TCK This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating At power up the TAP is reset internally to ensure that
17. RQ must be connected between the ZQ pin on the SRAM and Vss to allow the SRAM to adjust its output driver impedance The value of RQ must be 5X the value of the intended line impedance driven by the SRAM The allowable range of RQ to guarantee impedance matching with a tolerance of 15 is between 1750 and 3500 with Vopo 1 5V The output impedance is adjusted every 1024 cycles to account for drifts in supply voltage and temperature 1 SRAM 1 ze SRAM 24 20 T A o vt i w B s ei TN B lt P W R 2500hm W A b E 55 5 o R 2500hms Ss lt o En 2500nms ER A TE COCA K Ke la 4 q 8 E C K kajf l j 1 a O e al a j DATA IN DATA OUT MA Address BUS RPS areas WPS hi agi ER BW Se or Source KARA ASIC E a on e aj a Source KE RAYA AH ARK he Delayed K HAAAA E 2 Delayed K AAA R R 5pohms Vt Vddg2 Truth Tablel 3 4 5 6 7 Write Cycle Load address on the rising edge of K clock input write data on K and K rising edges Read Cycle Load address on the rising edge of K clock wait one cycle read data on 2 consecutive C and C rising edges NOP No Operation D X D X Q High Z IQ High Z Q A 0 at C t 1 Standby Clock Stopped Stopped Previous Previous State State Notes The above application shows 4 QDR I being used X Don t Care H Logic HIGH L Logic LOW Prepresents rising edge ND eO OS symm
18. TDO comes up in a high Z state TAP Registers Registers are connected between the TDI and TDO pins and allow data to be scanned into and out of the SRAM test circuitry Only one register can be selected at a time through the instruction registers Data is serially loaded into the TDI pin on the rising edge of TCK Data is output on the TDO pin on the falling edge of TCK Instruction Register Three bit instructions can be serially loaded into the instruction register This register is loaded when it is placed between the Document 38 05627 Rev A CY7C1303BV25 CY7C1306BV25 TDl and TDO pins as shown in TAP Controller Block Diagram Upon power up the instruction register is loaded with the IDCODE instruction It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section When the TAP controller is in the Capture IR state the two least significant bits are loaded with a binary 01 pattern to allow for fault isolation of the board level serial test path Bypass Register To save time when serially shifting data through registers it is sometimes advantageous to skip certain chips The bypass register is a single bit register that can be placed between TDI and TDO pins This allows data to be shifted through the SRAM with minimal delay The bypass register is set LOW Vss when the BYPASS instruction is executed Boundary Scan Register The boundary scan re
19. atched and stored into the lower 18 bit Write Data register provided BWS o are both asserted active On the subsequent rising edge of the negative input clock K the address is latched and the information presented_to_Dj 47 0 is stored into the Write Data register provided BWS 9 are both asserted active The 36 bits of data are then written into the memory array at the specified location When deselected the Write port will ignore all inputs after the pending Write operations have been completed Byte Write Operations Byte Write operations are supported by the CY7C1303BV25 A Write operation is initiated as described in the Write Operation section above The bytes that are written are deter mined by BWS and BWS which are sampled with each set of 18 bit data word Asserting the appropriate Byte Write Select input during the data portion of a write will allow the data being presented to be latched and written into the device Deasserting the Byte Write Select input during the data portion of a write will allow the data stored in the device for that byte to remain unaltered This feature can be used to simplify Read Modify Write operations to a Byte Write operation Single Clock Mode The CY7C1303BV25 can be used with a single clock mode In this mode the device will recognize only the pair of input clocks K and K that control both the input and output registers This Page 5 of 19 Feedback IRE o PERFORM i
20. below Instructions are loaded into the TAP controller during the Shift IR state when the instruction register is placed between TDI and TDO During this state instructions are shifted through the instruction register through the TDI and TDO pins To execute the instruction once it is shifted in the TAP controller needs to be moved into the Update IR state IDCODE The IDCODE instruction causes a vendor specific 32 bit code to be loaded into the instruction register It also places the instruction register between the TDI and TDO pins and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift DR state The IDCODE instruction Page 8 of 19 Feedback Does CYPRESS PERF PERFORM R M is loaded into the instruction register upon power up or whenever the TAP controller is given a test logic reset state SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins when the TAP controller is in a Shift DR state The SAMPLE Z command puts the output bus into a High Z state until the next command is given during the Update IR state SAMPLE PRELOAD SAMPLE PRELOAD is a 1149 1 mandatory instruction When the SAMPLE PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture DR state a snapshot of data on the inputs and output pins is captured in the boundary scan register Th
21. e rising edge of the K and K clocks BWS BWSz Synchronous during Write operations Used to select which byte is written into the device during the current portion of the Write operations CY7C1303BV25 BWSy controls Drg p and BWS controls Djy7 CY7C1306BV25 BWS controls Dyg o BWS controls Dj 7 9 BWS controls Dj26 18 and BWS3 controls D 35 27 Bytes not written remain unaltered Deselecting a Byte Write Select will cause the corresponding byte of data to be ignored and not written into the device A Input Address Inputs Sampled on the rising edge of the K clock during active Read operations and Synchronous on the rising edge of K for Write operations These address inputs are multiplexed for both Read and Write operations Internally the device is organized as 1M x 18 2 arrays each of 512K x 18 for CY7C1303BV25 and 512K x 36 2 arrays each of 256K x 36 for CY7C1306BV25 Therefore only 19 address inputs are needed to access the entire memory array of CY7C1303BV25 and 18 address inputs for CY7C1306BV25 These inputs are ignored when the appropriate port is deselected Qix 0 Outputs Data Output signals These pins drive out the requested data during a Read operation Valid Synchronous data is driven out on the rising edge of both the C and C clocks during Read operations or K and K when in single clock mode When the Read port is deselected Q 9 are automatically three stated CY7C1303BV25 Qj17 0 CY7C1306BV
22. e user must be aware that the TAP controller clock can only operate at a frequency up to 10 MHz while the SRAM clock operates more than an order of magnitude faster Because there is a large difference in the clock frequencies it is possible that during the Capture DR state an input or output will undergo a transition The TAP may then try to capture a signal while in transition metastable state This will not harm the device but there is no guarantee as to the value that will be captured Repeatable results may not be possible To guarantee that the boundary scan register will capture the correct value of a signal the SRAM signal must be stabilized long enough to meet the TAP controller s capture set up plus hold times tcs and tcp The SRAM clock input might not be captured correctly if there is no way in a design to stop or slow the clock during a SAMPLE PRELOAD instruction If this is an issue it is still possible to capture all other signals and simply ignore the value of the CK and CK captured in the boundary scan register Once the data is captured it is possible to shift out the data by putting the TAP into the Shift DR state This places the boundary scan register between the TDI and TDO pins PRELOAD allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells prior to the selection of another boundary scan test operation The shifting of data for the SAMPLE and PRELOAD phases
23. ected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Feedback YE CY7C1303BV25 CY7C1306BV25 Wns O D y de de PERFORM Document History Page Document Title CY7C1303BV25 CY7C1306BV25 18 Mbit Burst of 2 Pipelined SRAM with QDR Architecture Document Number 38 05627 Orig of ECN NO Issue Date Change Description of Change 253010 See ECN AN New Data Sheet 436864 See ECN Converted from Preliminary to Final Removed 133 MHz amp 100 MHz from product offering Included the Industrial Operating Range Changed C C Description in the Features Section amp Pin Description Table Changed trcyc from 100 ns to 50 ns changed trf from 10 MHz to 20 MHz and changed ty and ty from 40 ns to 20 ns in TAP AC Switching Characteristics table Modified the ZQ pin definition as follows Alternately this pin can be connected directly to Vppq which enables the minimum impedance mode Included Maximum Ratings for Supply Voltage on Vppqg Relative to GND Changed the Maximum Ratings for DC Input Voltage from Vppq to Vpp Modified the Description of ly from Input Load current to Input Leakage Current on page 15 Modified test condition in note 13 from Vppq lt Vpp to Vppa lt Vpp Updated the Ordering Information table and replaced the Package Name
24. erence levels of 0 75V Vref 0 75V RQ 250Q Vopa 1 5V input pulse levels of 0 25V to 1 25V and output loading of the specified ly loy and load capacitance shown in a of AC test loads 22 This part has a voltage regulator that steps down the voltage internally tPower is the time power needs to be supplied above Vpp minimum initially before a read or write operation can be initiated 23 At any given voltage and temperature toyz is less than tc z and toyz less than tco Document 38 05627 Rev A Page 16 of 19 Feedback E CY7C1303BV25 RE o CY7C1306BV25 PERFORM il Q Switching Waveforms 28 27 READ WRITE READ WRITE READ WRITE NOP WRITE NOP tSC 4 lt gt tHC I I l l I xX i tCLZ tDOH tDOH Pucci l 1 tKHCH tKHCH tco tco lt gt i lt gt gt gt c tKH tKL tKHKH DON T CARE XX UNDEFINED Notes 24 tchz tcLz are specified with a load capacitance of 5 pF as in part b of AC Test Loads Transition is measured 100 mV from steady state voltage 25 Q00 refers to output from address AO Q01 refers to output from the next internal burst address following AO i e AO 1 26 Outputs are disabled High Z one clock cycle after a NOP 27 In this example if address A2 A1 then data Q2 0 D10 and Q21 D11 Write data is forwarded immediately as read results This note applies to the whole diagram Document 38 05627 Rev A Page 17
25. etrically Document 38 05627 Rev A Device will power up deselected and the outputs in a three state condition A represents address location latched by the devices when transaction was initiated A 0 A 1 represent the addresses sequence in the burst represents the cycle at which a Read Write operation is started t 1 is the first clock cycle succeeding the t clock cycle Data inputs are registered at K and K rising edges Data outputs are delivered on C and C rising edges except when in single clock mode It is recommended that K K and C C when clock is stopped This is not essential but permits most rapid restart by overcoming transmission line charging Page 6 of 19 gt gt CY7C1303BV25 CY7C1306BV25 Wo O D y de de During the Data portion of a Write sequence both bytes D 7 p1 are written into the device L H During the Data portion of a Write sequence both bytes D 47 9 are written into the device During the Data portion of a Write sequence only the lower byte Drg p is written into the device D 47 9 remains unaltered During the Data portion of a Write sequence only the lower byte Drg p is written into the device D 47 9 remains unaltered During the Data portion of a Write sequence only the byte D 7 91 is written into the device Dig o remains unaltered During the Data portion of a Write sequence only the byte D 17 9 is written into the device Dig o
26. gister is connected to all of the input and output pins on the SRAM Several no connect NC pins are also included in the scan register to reserve pins for higher density devices The boundary scan register is loaded with the contents of the RAM Input and Output ring when the TAP controller is in the Capture DR state and is then placed between the TDI and TDO pins when the controller is moved to the Shift DR state The EXTEST SAMPLE PRELOAD and SAMPLE Z instruc tions can be used to capture the contents of the Input and Output ring The Boundary Scan Order tables show the order in which the bits are connected Each bit corresponds to one of the bumps on the SRAM package The MSB of the register is connected to TDI and the LSB is connected to TDO Identification ID Register The ID register is loaded with a vendor specific 32 bit code during the Capture DR state when the IDCODE command is loaded in the instruction register The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift DR state The ID register has a vendor code and other information described in the Identification Register Definitions table TAP Instruction Set Eight different instructions are possible with the three bit instruction register All combinations are listed in the Instruction Code table Three of these instructions are listed as RESERVED and should not be used The other five instruc tions are described in detail
27. ially and after any design or process change that may affect these parameters Document 38 05627 Rev A Page 15 of 19 Feedback E CY7C1303BV25 RE o CY7C1306BV25 PERFORM i Wo C Capacitancel F Clock Input Capacitance ioe Output Capacitance AC Test Loads and Waveforms VREF o 0 75V R 50Q 21 ALL INPUT PULSES Device OUTPUT 1 25V Under 0 75V Device 5 pF 0 254 Q Test Under Test Slew Rate 2 V ns Switching Characteristics Over the Operating Range 1 AI O E Parameter Parameter Description Min Max tpower tf o Vcc typical to the First Access Read or Write 10 Je Cycle Time tvc awn KClockand C Clock Cycle Time Y J input Clock K K and C C HIGH r24 ns input Clock K K and C C LOW P24 ns tKHKH tKHKH K K Clock Rise to K K Clock Rise and C C to C C Rise 2 7 Spe ns rising edge to rising edge K K Clock Rise to C C Clock Rise rising edge to rising edge 0 0 20 ns Set up Times Address Set up to Clock K and K Rise 07 ns Control Set up to Clock K and K Rise RPS WPS BWSp BWS 07 ns Dix 0 Set up to Clock K and K Rise 07 ns Hold Times tua Address Hold after Clock K and K Rise 07 ns tuc Control Signals Hold after Clock K and K Rise RPS WPS BWS BWS 0 7 Dix 0 Hold after Clock K and K Rise Notes 21 Unless otherwise noted test conditions assume signal transition time of 2V ns timing ref
28. ng Input This input is used to tune the device outputs to the system data bus impedance Qy 9 output impedance are set to 0 2 x RQ where RQ is a resistor connected between ZQ and ground Alternately this pin can be connected directly to Vppq which enables the minimum impedance mode This pin cannot be connected directly to GND or left unconnected RPS C C K K ZQ Document 38 05627 Rev A Page 4 of 19 Feedback Wns O D y de de PERFORM Pin Definitions continued CY7C1303BV25 CY7C1306BV25 Cnm o o o NC 36M N A Address expansion for 36M This pin is not connected to the die and so can be tied to any voltage level on CY7C1303BV25 CY7C1306BV25 GND 72M Address expansion for 72M This pin has to be tied to GND on CY7C1303BV25 NC 72M Address expansion for 72M This pin can be tied to any voltage level on CY7C1306BV25 GND 144M Input Address expansion for 144M This pin has to be tied to GND on CY7C1303BV25 CY7C1306BV25 ee Address expansion for 288M This pin has to be tied to GND on CY7C1306BV25 NA Not connected to the die Not connected to the die Can be tied to any voltage level 0 be tied to any Not connected to the die Can be tied to any voltage level level mo Reference Voltage Input Static input used to set the reference level for HSTL inputs and Outputs Reference as well as AC measurement points v Power Supply Power supply inputs to the core of the device
29. of 19 Feedback RE o PERFORM i Wo C Ordering Information CY7C1303BV25 CY7C1306BV25 Not all of the speed package and temperature ranges are available Please contact your local sales representative or visit www cypress com for actual products offered Package Ordering Code Diagram Package Type 167 CY7C1303BV25 167BZC 51 85180 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm CY7C1306BV25 167BZC CY7C1303BV25 167BZXC Package Diagram 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Operating Range Commercial 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Lead free Industrial 165 ball Fine Pitch Ball Grid Array 13 x 15 x 1 4 mm Lead free 165 ball FBGA 13 x 15 x 1 4 mm 51 85180 TOP VIEW PIN 1 CORNER A B C D E F G o o H l Q J Ln K L M N P R 4 LA B 13 00 0 10 U rA 2 pe gt So E A x A 2 o o A l _ oK l I y kZ wi ka F w y yv Eg wl SEATING PLANE f Ko M o 0 35 0 06 BOTTOM VIEW PIN 1 CORNER o pala 90 25 M B 0 50 70 06 165X 0 14 11 10 9 8 7 6 5 4 3 2 1 E i 2560000000000 Va B eo
30. ominal pedane Vs oa VW T TO ag E W u pmuowvor a 08 f O vea v Neer input Reference Voltage Typical value z070 oe 075 os v k iputLeakage Current SNOW 5 Vago s s m w a poe Vpp Operating Supply Vop Max lour 0 mA f fmax 1tovo Automatic Max Vpp Both Ports Deselected Power Down Vin Vin Or Vins Vit f fyax 1 tcyc Current Inputs Static AC Input peduremen A Over the Operating Range Parameter Test Conditions COS IEEE EI CI E Y mwee o O o Thermal Resistance OJA Test conditions follow standard test methods and Thermal Resistance Junction to Ambient procedures for measuring thermal impedance per EIA JESD51 Thermal Resistance Junction to Case Notes 13 Power up Assumes a linear ramp from OV to Vpp min within 200 ms During this time Vi lt Vpp and Vppo lt Vpp 14 All Voltage referenced to Ground 15 Output are impedance controlled lo Vppq 2 RQ 5 for values of 175Q lt RQ lt 3500 16 Output are impedance controlled lo VppQ 2 RQ 5 for values of 175Q lt RQ lt 3500 17 Overshoot V y AC lt Vopa 0 85V Pulse width less than tey 2 Undershoot V AC gt 1 5V Pulse width less than tcyc 2 18 This spec is for all inputs except C and C Clock For C and C Clock Vi Max VreF 0 2V 19 Vrer Min 0 68V or 0 46Vppq whichever is larger Vaer Max 0 95V or 0 54Vppq whichever is smaller 20 Tested init
31. te sequence only the byte written into the device Dyo will remain unaltered Le No data is written into the device during this portion of a Write operation No data is written into the device during this portion of a Write operation H H Note 8 Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table BWS BWS in the case of CY7C1303BV25 and also BWS and BWS3 in the case of CY7C1306BV25 can be altered on different portions of a write cycle as long as the set up and hold requirements are achieved 38 05627 Document 38 05627 Rev A Page 7 of 19 Feedback Does CYPRESS PERF PERFORM RM IEEE 1149 1 Serial Boundary Scan JTAG These SRAMs incorporate a serial boundary scan test access port TAP in the FBGA package This part is fully compliant with IEEE Standard 1149 1 1900 The TAP operates using JEDEC standard 2 5V I O logic levels Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature To disable the TAP controller TCK must be tied LOW Vss to prevent clocking of the device TDI and TMS are inter nally pulled up and may be unconnected They may alternately be connected to Vpp through a pull up resistor TDO should be left unconnected Upon power up the device will come up in a reset state which will not interfere with the operation of the device Test Access Port Test Clock The test clock is used only with the TA
32. ting the desired bit into that cell during the Shift DR state During Update DR the value loaded into that shift register cell will latch into the preload register When the EXTEST instruction is entered this bit will directly control the output Q bus pins Note that this bit is pre set HIGH to enable the output when the device is powered up and also when the TAP controller is in the Test Logic Reset state Reserved These instructions are not implemented but are reserved for future use Do not use these instructions Page 9 of 19 Feedback CY7C1303BV25 CY7C1306BV25 W e 4 TR 2 CYPRESS PERFORM AP Controller State Diagram 4 TEST LOGIC RESET o TEST LOGIC IDLE SELECT IR SCAN SELECT DR SCAN CAPTURE DR SHIFT DR o EXIT1 DR PAUSE DR o EXIT2 DR EXIT2 IR UPDATE DR UPDATE IR Note 9 The 0 1 next to each state represents the value at TMS at the rising edge of TCK CAPTURE DR SHIFT IR o re EXIT1 IR Page 10 of 19 Document 38 05627 Rev A Feedback YE CY7C1303BV25 CY7C1306BV25 Wns O a y de de PERFORM TAP Controller Block Diagram TDI Selection Circuitry selection TDO Circuitry TCK TMS TAP Electrical Characteristics Over the Operating Range 19 14 17 Parameter Description TestGonditons Win Wax Unt Vom Ouput HIGH Volage foom f 7a f fv Voe Ouiput HIGH Vote fonoa a
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