Cypress CY7C1019D User's Manual
Contents
1. PIN 1 LD Le 1 A435 DIMENSIONS IN INCHES MIN 3a5 443 MAX A05 7 32 820 830 SEATING PLANE 128 l ay ae a HARAARA Rt tas fT F on UU OU UU WU UU UU rae gt 013 050 e zu Jes l S Bee TYP 032 025 MIN 380 O15 020 51 85033 B Document 38 05464 Rev E Page 9 of 11 Feedback eg e KN CYPRESS CY7C1019D Eng GE A PERFORM Package Diagrams continued Figure 2 32 pin Thin Small Outline Package Type II 51 85095 ti SEE DETAIL r DIMENSIONS IN MILLIMETERS MIN MAX ENN TOP VIEW 1 27 BSC Nei 1 20 MAX o 5 DETAIL A 51 85095 All product or company names mentioned in this document may be the trademarks of their respective holders Document 38 05464 Rev E Page 10 of 11 Cypress Semiconductor Corporation 2006 2007 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress product2. tLZcE CE LOW to Low Z l8 3 ns tuzce CE HIGH to High z F 81 5 ns tpu P CE LOW to Power Up 0 ns tep CE HIGH to Power Down 10 ns Write Cycle D 11 twe Write Cycle Time 10 ns tscE CE LOW to Write End 7 ns taw Address Set Up to Write End 7 ns tHa Address Hold from Write End 0 ns tsa Address Set Up to Write Start 0 ns tpwe WE Pulse Width 7 ns tsp Data Set Up to Write End 6 ns bm Data Hold from Write End 0 ns tLzwe WE HIGH to Low Z 8 3 ns we WE LOW to High 278 5 ns Notes 5 Test conditions assume signal transition time of 3 ns or less timing reference levels of 1 5V input pulse levels of 0 to 3 0V and output loading of the specified lor lop and 30 pF load capacitance 6 tpower gives the minimum amount of time that the power supply should be at typical Voc values until the first memory access can be performed 7 tyzoe tuzce and tyzwe are specified with a load capacitance of 5 pF as in c of AC Test Loads and Waveforms Di on page 4 Transition is measured when the outputs enter a high impedance state 8 At any given temperature and voltage condition cr is less than t zce boor is less than t zog and tyzwe is less than t_zwe_ for any given device This parameter is guaranteed by design and is not tested 10 The internal write time of the memory is defined by the overlap of CE LOW and WE LOW CE and WE must be LOW to initiate a write and the transition of any of these signals can terminate the write The input data set up and h
3. the device by taking Chip Enable CE and Output Enable OE LOW while forcing Write Enable WE HIGH Under these conditions the contents of the memory location specified by the address pins appears on the IO pins Note 1 For guidelines on SRAM system design please refer to the System Design Guidelines Cypress application note available on the internet at www cypress com Cypress Semiconductor Corporation e Document 38 05464 Rev E 198 Champion Court San Jose CA 95134 1709 e 408 943 2600 Revised February 22 2007 Feedback d AN Ji CYPRESS CY7C1019D Pin Configuration SOJ TSOPII Top View Selection Guide 10 Industrial Unit Maximum Access Time 10 ns Maximum Operating Current 80 mA Maximum Standby Current 3 mA Document 38 05464 Rev E Page 2 of 11 Feedback s CYPRESS PERFORM Maximum Ratings Exceeding the maximum ratings may impair the useful life of the device These user guidelines are not tested Storage Temperature ceeeeeeeeeeeeeeeeeeeee 65 C to 150 C Ambient Temperature with Power Apple EE 55 C to 125 C Supply Voltage on Vec to Relative GND FI 0 5V to 6 0V DC Voltage Applied to Outputs in High Z State Pl amtegregua ren 0 5V to Mee 0 5V DC Input Voltage II 0 5V to Voc 0 5V Electrical Characteristics Over the Operating Range CY7C1019D Current into Outputs OW 20 m
4. A Static Discharge Votage A gt 2001V per MIL STD 883 Method 3015 Latch Up Current ecceeceeseeeeeeeeneeeeeeteeeeeneeeeeeeeaes gt 200 mA Operating Range Ambient Range Temperature Vcc Speed Industrial 40 C to 85 C 5V 0 5V 10 ns 10 Industrial Parameter Description Test Conditions Unit Min Max Vou Output HIGH Voltage loH 4 0 mA 2 4 V VoL Output LOW Voltage lo 8 0 mA 0 4 V Vu Input HIGH Voltage 2 2 Vcc 0 5 V Vu Input LOW Voltage DI 0 5 0 8 V lix Input Leakage Current GND lt Vi lt Vcc 1 1 pA loz Output Leakage Current GND lt Vi lt Vcc Output Disabled 1 1 uA loc Voc Operating Supply Current Voc Max 100 MHz 80 mA lout 0 mA f fmax line 83 MHz 72 mA 66 MHz 58 mA 40 MHz 37 mA Jee Automatic CE Power Down Max Vcc CE gt Vu 10 mA Current TTL Inputs ViN gt Vin or Vin lt Vu f fmax Ispo Automatic CE Power Down Max Vcc CE gt Voc 0 39 3 mA Current CMOS Inputs Vin Vcc 0 3V or Vin lt 0 3V f 0 Note 2 Vit min 2 0V and Vj4 max Vcc 1V for pulse durations of less than 5 ns Document 38 05464 Rev E Page 3 of 11 Feedback a d CYPRESS CY7C1019D PERFORM Capacitance 2 Parameter Description Test Conditions Max Unit Cin Input Capacitance Ta 25 C f 1 MHz Vec 5 0V 6 pF Cout Output Capacitance 8 pF Thermal Resistance l Param
5. eter Description Test Conditions 400 Mil TSOP Il Unit Wide SOJ OJA Thermal Resistance Still Air soldered on a 3 x 4 5 inch 56 29 62 22 C W Junction to Ambient four layer printed circuit board Ojc Thermal Resistance 38 14 21 43 C W Junction to Case AC Test Loads and Waveforms Z 500 3 0V 30 pF GND CAPACITIVE LOAD CONSISTS db OF ALL COMPONENTS OF THE 1 5V TEST ENVIRONMENT High Z characteristics R1 4800 5V OUTPUT 5 pF R2 INCLUDING I 2990 JIG AND SCOPE c Notes 3 Tested initially and after any design or process changes that may affect these parameters Rise Time lt 3 ns ALL INPUT PULSES Fall Time lt 3 ns 4 AC characteristics except High Z are tested using the load conditions shown in Figure a High Z characteristics are tested for all speeds using the test load shown in Figure c Document 38 05464 Rev E Page 4 of 11 Feedback SE Cypress CY7C1019D Switching Characteristics Over the Operating Range Pl 10 Industrial Parameter Description Unit Min Max Read Cycle toower 6 Voec typical to the first access 100 us tre Read Cycle Time 10 ns tana Address to Data Valid 10 ns toHA Data Hold from Address Change 3 ns tace CE LOW to Data Valid 10 ns DOE OE LOW to Data Valid 5 ns tLZ0E OE LOW to Low Z 0 ns tHZ0E OE HIGH to High z F 8 5 ns
6. mmm r ME Eeer MV E rer e gees ecr ee bw Ee CY7C1019D YPRESS PERFORM Features e Pin and function compatible with CY7C1019B High speed e taa 10 ns D Low active power Icc 80 mA 10 ns Low CMOS standby power D Ispo 3mA 2 0V Data retention Automatic power down when deselected e e D CMOS for optimum speed power D Center power ground pinout Easy memory expansion with CE and OE options Functionally equivalent to CY7C1019B e Available in Pb free 32 pin 400 Mil wide Molded SOJ and 32 pin TSOP II packages e Logic Block Diagram 1 Mbit 128K x 8 Static RAM Functional Description l The CY7C1019D is a high performance CMOS static RAM organized as 131 072 words by 8 bits Easy memory expansion is provided by an active LOW Chip Enable CE an active LOW Output Enable OE and tri state drivers This device has an automatic power down feature that significantly reduces power consumption when deselected The eight input and output pins IO through 107 are placed in a high impedance state when Deselected CE HIGH Outputs are disabled OE HIGH When the write operation is active CE LOW and WE LOW Write to the device by taking Chip Enable CE and Write Enable WE inputs LOW Data on the eight IO pins IO through Oz is then written into the location specified on the address pins Ag through A46 Read from
7. n Table Changed Overshoot spec from Vec 2V to Vec 1V in footnote 2 Ee 802877 See ECN VKN Changed Icc spec from 60 mA to 80 mA for 100MHz 55 mA to 72 mA for 83MHz 45 mA to 58 mA for 66MHz 30 mA to 37 mA for 40MHz Document 38 05464 Rev E Page 11 of 11 Feedback
8. old timing should be referenced to the leading edge of the signal that terminates the write 11 The minimum write cycle time for Write Cycle no 3 WE controlled OE LOW is the sum of tyzwe and tgp Document 38 05464 Rev E Page 5 of 11 Feedback i di CYPRESS CY7C1019D PERFORM d QW Data Retention Characteristics Over the Operating Range Parameter Description Conditions Min Max Unit VDR Vcc for Data Retention 2 0 V ICCDR Data Retention Current Voc Vor 2 0V CE gt Vec 0 3V 3 mA Vin Vec 0 3V or Viy lt 0 3V tcpr 3 Chip Deselect to Data Retention Time 0 ns tg H Operation Recovery Time tac ns Data Retention Waveform DATA RETENTION MODE Vopz 2V 4 5V tR Switching Waveforms Read Cycle No 1 Address Transition Controlled 3 14 tRC ADDRESS DATA OUT PREVIOUS DATA VALID DATA VALID Read Cycle No 2 OE Controlled l4 15 ADDRESS HIGH DATA OUT IMPEDANCE ES SE DATA VALID E NXAAANSA Voc ICC SUPPLY CURRENT ISB Notes 12 Full device operation requires linear Voc ramp from Vpp to Vcc min 50 us or stable at Voc min 2 50 us 13 Device is continuously selected OE CE V 14 WE is HIGH for Read cycle 15 Address valid prior to or coincident with CE transition LOW Document 38 05464 Rev E Page 6 of 11 Feedback S CYPRESS CY7C1019D PERFORM Switching Waveforms continued Write Cycle No 1 CE Con
9. s are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Feedback N Z CYPRESS o SSS o ooo PERFORM Document History Page Document Title CY7C1019D 1 Mbit 128K x 8 Static RAM Document Number 38 05464 REV ECN NO Issue Date GE SW Description of Change E 201560 See ECN SWI Advance Information data sheet for C9 IPP A 233715 See ECN RKF DC parameters are modified as per EROS Spec 01 2165 Pb free offering in the Ordering Information B 262950 See ECN RKF Added Tpower Spec in Switching Characteristics table Added Data Retention Characteristics table and waveforms Shaded Ordering Information C 307598 See ECN RKF Reduced Speed bins to 10 and 12 ns D 520647 See ECN VKN Converted from Preliminary to Final Removed Commercial Operating range Removed 12 ns speed bin Added Icc values for the frequencies 883MHz 66MHz and 40MHz Updated Thermal Resistance table Updated Ordering Informatio
10. trolled D8 17 e gt DATA IO DATA VALID Write Cycle No 2 WE Controlled OE HIGH During Write 17 ADDRESS 3 SA KE PWE ZR tHZOE Notes a 16 Data IO is high impedance if OE Vu 17 If CE goes HIGH simultaneously with WE going HIGH the output remains in a high impedance state 18 During this period the IOs are in the output state and input signals should not be applied Document 38 05464 Rev E Page 7 of 11 Feedback 7 5 zm ee E LE oa Om Sef CYPRESS CC C1OIVD PERFORM Switching Waveforms continued Write Cycle No 3 WE Controlled OE LOW DT 17 ADDRESS NNN PORRUA taw tHa tsa tpwe K Es CC tHD un ZE XXX tHZWE tLzwE m Truth Table CE OE WE 10 40 Mode Power H X X Hoh Power Down Standby Isp L L H Data Out Head Active cc L X L Data In Write Active lcc L H H High Z Selected Outputs Disabled Active Icc Ordering Information SE Ordering Code Began Package Type eae 10 CY7C1019D 10VXI 51 85033 32 pin 400 Mil Molded SOJ Pb free Industrial CY7C1019D 10ZSXI 51 85095 32 pin TSOP Type II Pb free Please contact your local Cypress sales representative for availability of these parts Document 38 05464 Rev E Page 8 of 11 Feedback l E zm SFCYPRESS C CCC7C101D Package Diagrams Figure 1 32 pin 400 Mil Molded SOJ 51 85033
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