Cypress CY7C1019CV33 User's Manual
Contents
1. Read Cycle No 11 12 inc ADDRESS DATA OUT PREVIOUS DATA VALID DATA VALID Read Cycle No 2 OE Controlled 2 13 ADDRESS tLZ0E HIGH HIGH IMPEDANCE IMPEDANCE Vcc SUPPLY CURRENT Write Cycle No 1 CE Controlled 151 two lt lt lt lt gt ADDRESS tsce CE tsa tsce taw lA tup iPwE TE SSS DATA I O tsp DATA VALID Notes 11 Device is continuously selected OE CE Vi 12 WE is HIGH for read cycle 13 Address valid prior to or coincident with CE transition LOW 14 Data I O is high impedance if OE Vig 15 If CE goes HIGH simultaneously with WE going HIGH the output remains in a high impedance state Document 38 05130 Rev F Page 5 of 10 Feedback gt amp CYPRESS 0 7010196133 PERFORM Switching Waveforms continued Write Cycle No 2 WE Controlled OE HIGH During Write 4 15 twc 7 tHa T taw tsa iPwE 5 RSs ara vo EEX tuzoE Write Cycle No 3 WE Controlled OE Low 5 twc tHA taw tsa tpwe WE Ags peas KPTEEX KX SK owe XXX tLZwe tHZWE Truth Table CE OE WE l 0Og 1 O Mode Power H X X High Z Power Down Standby lag L L H Data Out Read Active Icc L X L Data In Write Active loc L H H High Z Selected Outputs Disabled Active loc Note 16 During this peri2. output pins l Og through l O7 are placed in a high impedance state when the device is deselected CE HIGH the outputs are disabled OE HIGH or during a write operation CE LOW and WE LOW The CY7C1019CV33 is available in Standard 48 ball FBGA 32 pin TSOP II and 400 mil wide SOJ packages Pin Configuration SOJ TSOP II Top View Ao Ay Ao O As CE oes 00 JO VO Voc o Vss 02 05 WE O A 4 As O As A O 7 San Jose CA 95134 1709 e 408 943 2600 Revised August 3 2006 Feedback A CYPRESS CYPRESS CY7C1019CV33 PERFORM Pin Configuration 48 ball VFBGA Top View 2 3 4 5 O QDOH DOODO s Ca 8 8 99099 es Ne e n9 Qe o Kee e 6 999 eS 0 ie no 89 62 Qe e wo An 896 n Selection Guide 10 12 15 Unit Maximum Access Time 10 12 15 ns Maximum Operating Current 80 75 70 mA Maximum Standby Current 5 5 5 mA Note 1 NC pins are not connected on the die Document 38 05130 Rev F Page 2 of 10 Feedback Jj f CYPRESS CY7C1019CV33 PERFORM OO eee Maximum Ratings Current into Outputs 6 20 mA ic Disch Vollag Gis sinensis 2001V Above which the useful life may be impaired For user gu
3. 1 LD l6 1 435 DIMENSIONS IN INCHES MIN ass 443 MAX 405 HU j 7 32 820 830 p SEATING PLANE EE F L 148 o p I S 013 0 004 050 I 026 360 TYP 032 025 MIN 380 015 020 51 85033 8 Document 38 05130 Rev F Page 7 of 10 Feedback Package Diagrams continued 32 pin TSOP II 51 85095 20 82 SEE DETAIL 0 DIMENSIONS IN MILLIMETERS MIN MAX 15 5 TOP VIEW DETAIL A 51 85095 Document 38 05130 Rev F Page 8 of 10 Feedback F CYPRESS CY7C1019CV33 PERFORM Package Diagrams continued 48 ball VFBGA 6 x 8 x 1 mm 51 85150 TOP VIEW BOTTOM VIEW A1 CORNER amp 0 05 MC i A1 CORNER 0 30 0 05 48X 1 7 3 Ae 5 6 6 5 4 3 2 1 2 A 3 6OOJ OOQO 8 y 900000 je c OOOOOO E D e LS OOO OOO p 8 E i 66 666 S F G 4 OOOOOO r G E OOOOOO H 1 i 0000 H A A 1 875 p B 4 6 00 0 10 0 75 3 75 B 6 00 0 10 x C 0 15 47 q 51 85150 D 2 52 VUES l T SEATING PLANE bA 3 8 All product and company names mentioned in thi
4. CY7C1019CV33 CYPRESS PERFORM Features Pin and function compatible with CY7C1019BV33 High speed taa 10ns CMOS for optimum speed power Data retention at 2 0V Center power ground pinout Automatic power down when deselected Easy memory expansion with CE and OE options Available in Pb free and non Pb free 48 ball VFBGA 32 pin TSOP Il and 400 mil SOJ package Functional Description The CY7C1019CV33 is a high performance CMOS static RAM organized as 131 072 words by 8 bits Easy memory expansion is provided by an active LOW Chip Enable CE an active LOW Output Enable OE and tri state drivers This Logic Block Diagram ROW DECODER al m lt lt lt lt lt lt lt lt Ol mi Cypress Semiconductor Corporation Document 38 05130 Rev F 198 Champion Court 128K x 8 Static RAM device has an automatic power down feature that significantly reduces power consumption when deselected Writing to the device is accomplished by taking Chip Enable CE and Write Enable WE inputs LOW Data on the eight I O pins l Og through l Oz7 is then written into the location specified on the address pins Ag through A46 Reading from the device is accomplished by taking Chip Enable CE and Output Enable OE LOW while forcing Write Enable WE HIGH Under these conditions the contents of the memory location specified by the address pins will appear on the I O pins The eight input
5. by current from 5 nA to 5 mA D 123030 12 17 02 DFP Updated Truth Table to reflect single Chip Enable option E 419983 See ECN NXR Added 48 ball VFBGA Package Added lead free parts in Ordering Information Table Replaced Package Name column with Package Diagram in the Ordering Information Table AF 493543 See ECN NXR Removed 8 ns speed bin from Product offering Added note 1 on page 2 Changed the description of lix from Input Load Current to Input Leakage Current in DC Electrical Characteristics table Removed los parameter from DC Electrical Characteristics table Updated Ordering Information Document 38 05130 Rev F Page 10 of 10 Feedback
6. ide i s MOD 3015 lines not tested ques t i 65 C to 150 C atch up Current sse gt Ambient Temperature with Operating Range Power 0 8 55 C to 125 C Supply Voltage on Voc to Relative GND I 0 5 to 4 6V Pino pply 9 66 EE i Range Temperature Vec DC Voltage Applied to Outputs 4 109 in High Z Salo ie e 0 5V to Veg 05 Commercial ees Ben ue DC Input Voltagel 0 5Vto Vog 0 sv Industrial 40 C to 85 C 3 3V 10 Electrical Characteristics Over the Operating Range 10 12 15 Parameter Description Test Conditions Min Max Min Max Min Max Unit VoH Output HIGH Voltage Vcc Min 2 4 2 4 2 4 V lou 4 0 mA VoL Output LOW Voltage Voc Min 0 4 0 4 0 4 V lo 8 0 mA Vin Input HIGH Voltage 2 0 Voo 0 3 20 Vocot 0 3 2 0 Voc 0 3 V Mi Input LOW Voltagel 0 3 0 8 0 3 0 8 0 3 0 8 V lix Input Leakage Current GND lt V lt Vcc 1 1 1 1 1 1 pA loz Output Leakage GND lt Vi lt Vec 1 1 1 1 1 pA Current Output Disabled loc Voc Operating Voc Max 80 75 70 mA Supply Current loyt 0 mA f fmax 1 trc leg Automatic CE Max Vcc CE gt Vin 15 15 15 mA Power down Current Viy gt Vi or TTL Inputs Vin lt f fMAX 582 Automatic CE Max Vcc 5 5 5 mA Power down Current CE gt Vcc 0 3V CMOS Inputs Vin Vcc 0 3V or Vin lt 0 3V f 0 Ca
7. od the I Os are in the output state and input signals should not be applied Page 6 of 10 Document 38 05130 Rev F Feedback il I YPRESS CY7C1019CV33 PERFORM Ordering Information Speed Package Operating ns Ordering Code Diagram Package Type Range 10 CY7C1019CV33 10VC 51 85033 32 pin 400 Mil Molded SOJ Commercial CY7C1019CV33 10ZXC 51 85095 32 pin TSOP II Pb Free CY7C1019CV33 10ZXI 32 TSOP II Pb Free Industrial 12 CY7C1019CV33 12VC 51 85033 32 pin 400 Mil Molded SOJ Commercial CY7C1019CV33 12ZC 51 85095 32 pin TSOP II CY7C1019CV33 12ZXC 32 pin TSOP II Pb Free CY7C1019CV33 12VI 51 85033 32 pin 400 Mil Molded SOJ Industrial CY7C1019CV33 12BVXI 51 85150 48 ball VFBGA Pb Free 15 CY7C1019CV33 15VC 51 85033 32 pin 400 Mil Molded SOJ Commercial CY7C1019CV33 15VXC 51 85033 32 pin 400 Mil Molded SOJ Pb Free CY7C1019CV33 15ZXC 51 85095 32 pin TSOP II Pb Free CY7C1019CV33 15ZX 51 85095 32pin TSOP ll Pb Free Industrial Package Diagrams 32 pin 400 Mil Molded SOJ 51 85033 PIN
8. p to Write Start 0 0 0 ns tpwe WE Pulse Width 7 8 10 ns tsp Data Set Up to Write End 5 6 8 ns tup Data Hold from Write End 0 0 0 ns lizwE WE HIGH to Low Zl 3 3 3 ns tuzwE WE LOW to High 219 7 5 6 7 ns Notes 4 AC characteristics except High Z for all speeds are tested using the Thevenin load shown in Figure a High Z characteristics are tested for all speeds using the test load shown in Figure c o0 0o 01 Test conditions assume signal transition time of 3 ns or less timing reference levels of 1 5V input pulse levels of 0 to 3 0V tuzoE tHzce and tuzwe are specified with a load capacitance of 5 pF as in part d of AC Test Loads Transition is measured 500 mV from steady state voltage At any given temperature and voltage condition tuzcg is less than tj zcg tuzog is less than tj zog and tyzwe is less than tj zwg for any given device This parameter is guaranteed by design and is not tested The internal write time of the memory is defined by the overlap of CE LOW and WE LOW CE and WE must be LOW to initiate a write and the transition of any of these signals can terminate the write The input data set up and hold timing should be referenced to the leading edge of the signal thatterminates the write 10 The minimum write cycle time for Write Cycle no 3 WE controlled OE LOW is the sum of tyzwe and tgp Document 38 05130 Rev F Page 4 of 10 Feedback CYPRESS CY7C1019CV33 Switching Waveforms
9. pacitance Parameter Description Test Conditions Max Unit Cin Input Capacitance TA 25 f 2 1 MHz 8 pF Cour Output Capacitance 8 pF Notes 2 Vit min 2 0V for pulse durations of less than 20 ns 3 Tested initially and after any design or process changes that may affect these parameters Document 38 05130 Rev F Page 3 of 10 Feedback H CYPRESS g PERFORM AC Test Loads and Waveforms CY7C1019CV33 R3170 a ALL INPUT PULSES High Z characteristics 90 3 3V OUTPUT 10 OUTPUT 30 pF R2 GND I 3510 5 pF R2 I 3510 Rise Time 1 V ns b Fall Time 1 V ns a c Switching Characteristics Over the Operating Rangel 10 12 15 Parameter Description Min Max Min Max Min Max Unit Read Cycle Read Cycle Time 10 12 15 ns tAA Address to Data Valid 10 12 15 ns toHa Data Hold from Address Change 3 3 3 ns tACE CE LOW to Data Valid 10 12 15 ns tpoE OE LOW to Data Valid 5 7 ns tizoE OE LOW to Low Z 0 0 0 ns tuzoE OE HIGH to High 76 71 5 6 7 ns lizcE CE LOW to Low 217 3 3 3 ns tuzcE CE HIGH to High Zl l 5 6 7 ns pud CE LOW to Power Up 0 0 0 ns CE HIGH to Power Down 10 12 15 ns Write Cycle 101 twc Write Cycle Time 10 12 15 ns tscE CE LOW to Write End 8 9 10 ns taw Address Set Up to Write End 8 9 10 ns tHa Address Hold from Write End 0 0 0 ns tsa Address Set U
10. s document are the trademarks of their respective holders Document 38 05130 Rev F Page 9 of 10 Cypress Semiconductor Corporation 2006 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges 1 Feedback Feeabac 7 CYPRESS CY7C1019CV33 Document History Page Document Title CY7C1019CV33 128K x 8 Static RAM Document Number 38 05130 Issue Orig of REV ECN NO Date Change Description of Change 109245 12 16 01 HGK New Data Sheet A 113431 04 10 02 NSL AC Test Loads split based on speed B 115047 08 01 02 HGK Added TSOP II Package and Temp Improved Icc limits C 119796 10 11 02 DFP Updated stand
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