Cypress CY7C1019BN User's Manual
Contents
1. 12 15 Parameter Description Min Max Min Max Unit Read Cycle tre Read Cycle Time 12 15 ns taa Address to Data Valid 12 15 ns toHa Data Hold from Address Change 3 3 ns tace CE LOW to Data Valid 12 15 ns tDOE OE LOW to Data Valid 6 7 ns tLZ0E OE LOW to Low Z 0 0 ns HZOE OE HIGH to High z 8l 6 7 ns LZCE CE LOW to Low Z l 3 3 ns tHzcE CE HIGH to High Z gt 6l 6 7 ns tpy CE LOW to Power Up 0 0 ns tpp CE HIGH to Power Down 12 15 ns Write Cycle 8l twe Write Cycle Time 12 15 ns tscE CE LOW to Write End 9 10 ns taw Address Set Up to Write End 8 10 ns tHa Address Hold from Write End 0 0 ns tsa Address Set Up to Write Start 0 0 ns tpwe WE Pulse Width 8 10 ns tsp Data Set Up to Write End 6 8 ns tub Data Hold from Write End 0 0 ns tLzwe WE HIGH to Low Zl 3 3 ns tHzwe WE LOW to High Zi 6l 6 7 ns Notes 4 Test conditions assume signal transition time of 3 ns or less timing reference levels of 1 5V input pulse levels of 0 to 3 0V and output loading of the specified loL Ioy and 30 pF load capacitance NOOO tuzoe tuzce and tyzwe are specified with a load capacitance of 5 pF as in part b of AC Test Loads Transition is measured 500 mV from steady state voltage At any given temperature and voltage condition tuzce is less than t 7 e tyzog is less than t 7o _and tyzwe is less than t_zwe for any given device The internal write time of2. Max Unit VoH Output HIGH Voltage Voc Min lop 4 0 mA 2 4 2 4 V VoL Output LOW Voltage Vcc Min Io 8 0 mA 0 4 0 4 V Vin Input HIGH Voltage 2 2 Vect 0 3 2 2 Vect 0 3 V Vi Input LOW Voltage 0 3 0 8 0 3 0 8 V lix Input Leakage GND lt VI lt Vee 1 1 1 1 LA Current loz Output Leakage GND lt Vi lt Vec 5 5 5 5 uA Current Output Disabled loc Voc Operating Voc Max lout 0 mA 140 130 mA Supply Current f fmax t trc Ispy Automatic CE Max Voc CE gt Vin 40 40 mA Power Down Current Vin gt Viy Or L 20 20 Ispo Automatic CE Max Vcc 10 10 mA Power Down Current CE gt Vcc 0 3V L 1 1 CMOS Inputs Vin gt Voc 0 3V or Vin lt 0 3V f 0 Capacitance Parameter Description Test Conditions Max Unit Cin Input Capacitance Ta 25 f 1 MHz 6 pF Court Output Capacitance Vcc 5 0V 8 pF Notes 1 Vi_ min 2 0V for pulse durations of less than 20 ns 2 Ta is the Instant On case temperature 3 Tested initially and after any design or process changes that may affect these parameters Document 001 06425 Rev Page 2 of 8 Feedback a CYPRESS PERFORM CY7C1019BN AC Test Loads and Waveforms R1 4800 R1 4809 ALL INPUT PULSES OV OUTPUT OUTPUT ND 39 PT a 2 in oes INCLUDING INCLUDING lt 3ns JIG AND JIG AND SCOPE a SCOPE Equivalent to THEVENIN EQUIVALENT OUTPUT O vww O Switching Characteristics Over the Operating Range We 1 73V
3. wide SOJ packages Pin Configurations SOJ TSOPII Top View Ao 1 Ay 2 Ao 03 Oo As 4 CE 5 1 01 1 00 6 1 04 7 Oo Vec 8 Vss VOs I 02 vo 1 03 WE 1 05 A4 A5 1 O6 Ag A7 1 07 Cypress Semiconductor Corporation Document 001 06425 Rev 198 Champion Court San Jose CA 95134 1709 e 408 943 2600 Revised February 1 2006 Feedback CYPRESS CY7C1019BN PERFORM Selection Guide 7C1019BN 12 7C1019BN 15 Unit Maximum Access Time 12 15 ns Maximum Operating Current 140 130 mA Maximum Standby Current 10 10 mA L 1 1 mA Maximum Ratings Current into Outputs LOW cccceeesseeeeteeeeeteeees 20 mA Above which the useful life may be impaired For user guide il ee SS A eS ey z200ty lines not tested Sorge Tenpera 65C to 150 C Latch Up CUNE Ntasri ronianer gt 200 mA Ambient Temperature with Operating Range Power Applied 55 C to 125 C Supply Voltage on Voc to Relative GND 0 5V to 7 0V Ambient DC Voltage oped to Outputs Temperature in High Z Stateless 0 5V to Veg 0 5y Commercial peas chisel Ess DC Input Voltage os cccsssssssssssssessesee 0 5V to Vog 0 5V Industrial 40 C to 85 C SV 10 Electrical Characteristics Over the Operating Range 12 15 Parameter Description Test Conditions Min Max Min
4. BN 15ZXC 51 85095 32 Lead TSOP Type II Pb free Please contact local sales representative regarding availability of these parts Document 001 06425 Rev Page 6 of 8 PRESS CY7C1019BN PERFORM Package Diagrams 32 pin 400 mil Molded SOJ 51 85033 PIN 1 LD 435 DIMENSIONS IN INCHES MIN 295 A MAX 405 7 32 820 830 SEATING PLANE J 1 ON o ji F a 0 004 i a50 J 026 360 TYP 032 025 MIN 380 DIS th 51 85033 B 020 ES 32 pin TSOP II 51 85095 Y F SEE DETAIL A DIMENSIONS IN MILLIMETERS MIN 15 45 31 32 i TOP VIEW R 0 12 MIN R 0 1270 25 1 27 BSC 0 5 DETAIL A 51 85095 All product or company names mentioned in this document may be the trademarks of their respective holders Document 001 06425 Rev Page 7 of 8 Cypress Semiconductor Corporation 2006 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or o
5. CY7C1019BN PERFORM Features High speed taa 12 15 ns CMOS for optimum speed power Center power ground pinout Automatic power down when deselected Easy memory expansion with CE and OE options Functionally equivalent to CY7C1019 Logic Block Diagram fan wW a Q O wW a O 128K x 8 Static RAM Functional Description The CY7C1019BN is a high performance CMOS static RAM organized as 131 072 words by 8 bits Easy memory expansion is provided by an active LOW Chip Enable CE an active LOW Output Enable OE and three state drivers This device has an automatic power down feature that significantly reduces power consumption when deselected Writing to the device is accomplished by taking Chip Enable CE and Write Enable WE inputs LOW Data on the eight I O pins I Og through I O7 is then written into the location specified on the address pins Ag through A46 Reading_from the device is accomplished by taking Chip Enable CE and Output Enable OE LOW while forcing Write Enable WE HIGH Under these conditions the contents of the memory location specified by the address pins will appear on the I O pins The eight input output pins I Og through I O7 are placed ina high impedance state when the_device is deselected CE HIGH the outputs are disabled OE HIGH or during a write operation CE LOW and WE LOW The CY7C1019BN is available in standard 32 pin TSOP Type I and 400 mil
6. the memory is defined by the overlap of CE LOW and WE LOW CE and WE must be LOW to initiate a write and the transition of any of these signals can terminate the write The input data set up and hold timing should be referenced to the leading edge of the signal that terminates the write o Document 001 06425 Rev The minimum write cycle time for Write Cycle no 3 WE controlled OE LOW is the sum of tyzwe and tgp Page 3 of 8 Feedback 2 CYPRESS CY7C1019 BN PERFORM Data Retention Characteristics Over the Operating Range L Version Only Parameter Description Conditions Min Max Unit VDR Vcc for Data Retention No input may exceed Vcc 0 5V 2 0 V Voc Vpr 2 0V ICCDR Data Retention Current T gt Voc 0 3V 300 pA tcpr Chip Deselect to Data Retention Time Vin Voc 0 3V or Vin lt 0 3V 0 ns tr Operation Recovery Time 200 us Data Retention Waveform DATA RETENTION MODE Vpr gt 2V Switching Waveforms Read Cycle No 1 9 10 tRC ADDRESS DATA OUT PREVIOUS DATA VALID DATA VALID Read Cycle No 2 OE Controlled 111 ADDRESS tbo tLZ0E HIGH HIGH IMPEDANCE f V IMPEDANCE omTaoUt KRO m O gt Vcc SUPPLY CURRENT Notes ee 9 Device is continuously selected OE CE V 10 WE is HIGH for read cycle 11 Address valid prior to or coincident with CE transition LOW Document 001 06425 Re
7. ther rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Feedback CYPRESS PERFORM Document History Page CY7C1019BN Document Title CY7C1019BN 128K x 8 Static RAM Document Number 001 06425 Document 001 06425 Rev Orig of REV ECN NO Issue Date Change Description of Change kid 423847 See ECN NXR New Data Sheet Page 8 of 8 Feedback
8. v Page 4 of 8 Feedback Z CypRESS CY 7C1019BN PERFORM Switching Waveforms continued Write Cycle No 1 CE Controlled 2 13 DATA I O DATA VALID Write Cycle No 2 WE Controlled OE HIGH During Write 2 13 ADDRESS ___ T r RAD oa ro SEO tHZOE Notes BES 12 Data I O is high impedance if OE Viy _ 13 If CE goes HIGH simultaneously with WE going HIGH the output remains in a high impedance state 14 During this period the I Os are in the output state and input signals should not be applied Document 001 06425 Rev Page 5 of 8 Feedback CYPRESS PERFORM Switching Waveforms continued Write Cycle No 3 WE Controlled OE Low 3 CY7C1019BN two ADDRESS _ N SS Z Ee OSs LLM LLL LLL taw tsa tPwE NE QXx tHo OOO OO a OS XX DATA vo NCTE BX DX QAO paravan OOOO tHZWE Truth Table CE OE WE VO V 07 Mode Power H X X High Z Power Down Standby lsg L L H Data Out Read Active Icc L X L Data In Write Active lcc L H H High Z Selected Outputs Disabled Active Icc Ordering Information Speed Package Operating ns Ordering Code Diagram Package Type Range 12 CY7C1019BN 12VC 51 85033 32 Lead 400 Mil Molded SOJ Commercial CY7C1019BN 12ZC 51 85095 32 Lead TSOP Type II CY7C1019BN 12ZXC 51 85095 32 Lead TSOP Type II Pb free 15 CY7C1019BN 15VC 51 85033 32 Lead 400 Mil Molded SOJ Commercial CY7C1019
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