Cypress CY7C1012DV33 User's Manual
Contents
1. O E F SSF CYPRESS PERFORM Ordering Information Speed r Package Operating ns Ordering Code Nama Package Type Range 10 CY7C1012DV33 10BGXI 51 85115 119 Ball Plastic Ball Grid Array 14 x 22 x 2 4 mm Pb Free Industrial Package Diagram Figure 8 119 Ball PBGA 14 x 22 x 2 4 mm A RNER 540 a1 00 3X REF l l d 4 i amp E E S S 7 7 1 a e eB OOO Kd Gl ee l L ooa 7 _ BEBE tf 666 REF A z B 14 000 200 f P tal SAK L H a Document Number 38 05610 Rev D 51 85115 B Page 9 of 11 Feedback Document History Page YPRESS PERFORM CY7C1012DV33 Document Title CY7C1012DV33 12 Mbit 512K X 24 Static RAM Document Number 38 05610 ECN No Orig of Change Submission Date Description of Change 250650 SYT See ECN New data sheet 469517 NXR See ECN Converted from Advance Information to Preliminary Corrected typo in the Document Title Removed 10 and 12 speed bins from product offering Changed J7 Ball of BGA from DNU to NC Removed Industrial Operating range from product offering Included t2. Input LOW Voltage 0 3 0 8 V lix Input Leakage Current GND lt V lt Vcc 1 1 uA loz Output Leakage Current GND lt Vout lt Vcc output disabled 1 1 uA loc Voc Operating Supply Voc Max f fmax 1 trco 175 mA Current lout 0 mA CMOS levels Ispy Automatic CE Power Down Max Vcc CE gt Vin 30 mA Current TTL Inputs Vin Vin OF Vin lt Vib f fmax lans Automatic CE Power Down Max Vcc CE gt Voc 0 3V 25 mA Current CMOS Inputs Vin Voc 0 3V or Vy lt 0 3V f 0 Notes 2 Viz min 2 0V and V 4 max Vcc 2V for pulse durations of less than 20 ns soe eae _ osha oe 3 SE indicates a combination of all three chip enables When active LOW CE indicates the CE4 or CE3 or CE3 is LOW When HIGH CE indicates the CE CE and Eg are HIGH Document Number 38 05610 Rev D Page 3 of 11 Feedback 2 CYPRESS CY7C1012DV33 PERFORM Capacitance Tested initially and after any design or process changes that may affect these parameters Parameter Description Test Conditions Max Unit Cin Input Capacitance Ta 25 C f 1 MHZ Vec 3 3V 8 pF Cout I O Capacitance 10 pF Thermal Resistance Tested initially and after any design or process changes that may affect these parameters Parameter Description Test Conditions ie Bell Unit OJA Thermal Resistance Still air soldered on a 3 x 4 5 inch 20 31 C W junction to ambient four
3. 9 10 ns Write Cycle 9 70 twe Write Cycle Time 10 ns lact CE Active LOW to Write End l 7 ns taw Address Setup to Write End 7 ns tHa Address Hold from Write End 0 ns tsa Address Setup to Write Start 0 ns tpwe WE Pulse Width 7 ns tsp Data Setup to Write End 5 5 ns thp Data Hold from Write End 0 ns l awe WE HIGH to Low Z l 3 ns tHzwe WE LOW to High Z l 5 ns Notes Test conditions assume signal transition time of 3 ns or less timing reference levels of 1 5V and input pulse levels of 0 to 3 0V Test conditions for the read cycle use output loading as shown in part a of Figure 2 unless specified otherwise tpower gives the minimum amount of time that the power supply is at typical Vcc values until the first memory access is performed tuzoe tyzce tyzwe tLzoe t zce and tLzwe are specified with a load capacitance of 5 pF as in part b of Figure 2 Transition is measured 200 mV from steady state voltage These parameters are guaranteed by design and are not tested ___ ___ or The internal write time of the memory is defined by the overlap of CE4 or CE or CE3 LOW and WE LOW Chip enables must be active and WE must be LOW to initiate awrite The transition of any of these signals terminate the write The input data setup and hold timing are referenced to the leading edge of the signal that terminates the write 10 The minimum write cycle time for Write Cycle No 3 WE controlled OE LOW is the sum of tyzwe and
4. tgp oo NO Oo Document Number 38 05610 Rev D Page 5 of 11 Feedback S as 2 EZ CYPRESS CY7C1012DV33 i PERFORM Data Retention Characteristics Over the Operating Range Parameter Description Conditions 2 Min Typ Max Unit VDR Vcc for Data Retention 2 V locpR Data Retention Current vee 7A CE zo c K Vac a 25 mA Lon DH Chip Deselect to Data Retention 0 ns Time iQue Operation Recovery Time trc ns Data Retention Waveform DATA RETENTION MODE VprR2 2V 3 0V tR Switching Waveforms Figure 3 Read Cycle No 1 13 14 tRC ADDRESS DATA OUT PREVIOUS DATA VALID DATA VALID Figure 4 Read Cycle No 2 OE Controlled DR 14 15 ADDRESS d CE OE tHZOE wees HIGH IMPEDANCE DATA OUT Cee DATA VALID gt Od LZCE T tpu lcc Vec 50 50 SUPPLY Isp CURRENT Notes 11 Tested initially and after any design or process changes that may affect these parameters 12 Full device operation requires linear Voc ramp from Vpp to Vec min 50 uS or stable at Vec min 2 50 ps 13 Device is continuously selected OE CE Vi 14 WE is HIGH for read cycle oe 15 Address valid before or similar to CE transition LOW Document Number 38 05610 Rev D Page 6 of 11 Feedback E CYPRESS CY7C1012DV33 Bnat PERFORM Switching Waveforms continued Figure 5 Write Cycle No 1 CE Controlled 8 16 171 twc e YX CE tsa tsc
5. while output enable OE remains LOW Under these conditions the contents of the memory location specified on the address pins appear on the specified data input and output I O pins Asserting all the chip selects LOW reads all 24 bits of data from the SRAM The 24 I O pins I O 1 O23 are placed in a high impedance state when all the chip selects are HIGH or when the output enable OE is HIGH during a READ mode For more infor mation see the Truth Table on page 8 Logic Block Diagram Aian S ROW DECODER SENSE AMPS 512K x 24 ARRAY COLUMN DECODER Cypress Semiconductor Corporation Document Number 38 05610 Rev D lt a 1 0 1 07 198 Champion Court N q UO 1 045 1O46 l O23 CE CE CE CONTROL LOGIC WE OE San Jose CA 95134 1709 408 943 2600 Revised November 6 2008 Feedback Z F CYPRESS CY7C1012DV33 PERFORM Selection Guide Description 10 Unit Maximum Access Time 10 ns Maximum Operating Current 175 mA Maximum CMOS Standby Current 25 mA Pin Configuration Figure 1 119 Ball PBGA Top View l 1 3 4 5 6 7 A NC A A A NC B NC A A CE A A NC C O45 NC CE NC CE NC Oo D 1 013 Vpp Vss Vss Vss Vpp VO E 1 044 Vss VDD Vss VDD Vss UO F VO45 VDD Vss Vss Vss Vpp U
6. S G 1 016 Vss VDD Vss VDD Vss UO H VO47 VDD Vss Vss Vss Vpp UO J NC Vss Vop Vss Vpp Vss NC K VO4g Vpp Vss Vss Vss VDD V Og L VO 9 Vss VDD Vss VDD Vss UO M O29 VDD Vss Vss Vss Vpp US N 1 021 Vss VDD Vss Vpp Vss UO P VOx9 VDD Vss Vss Vss Vpp VO 0 R 1 023 A NC NC NC A 1 044 T NC A A WE A A NC U NC A A OE A A NC Note 1 NC pins are not connected on the die Document Number 38 05610 Rev D Page 2 of 11 Feedback E Z Cypress CY7C1012DV33 Maximum Ratings Current into Outputs LOW eee eee 20 mA Exceeding maximum ratings may impair the useful life of the Static Discharge Voltage eee e gt 2001V device These user guidelines are not tested MIL STD 883 Method 3015 Storage Temperature eee eee 65 C to 150 C Latch Up Current sese gt 200 mA Ambient Temperature with O ti R Power Applied 55 C to 125 C perating Range Supply Voltage on Vgc Relative to GND F 0 5V to 4 6V Ambient Range Temperature Vcc DC Voltage Applied to Outputs in High Z State Sl 0 5V to Vec 0 5V Industrial 40 C to 85 C 3 3V 0 3V DC Input Voltage TS 0 5V to Voc 0 5V DC Electrical Characteristics Over the Operating Range 10 Parameter Description Test Conditions 2 Unit Min Max Vou Output HIGH Voltage Voc Min lop 4 0 mA 2 4 V VoL Output LOW Voltage Vec Min lo 8 0 mA 0 4 V Vin Input HIGH Voltage 2 0 Voc 0 3 V Vil
7. e taw tHA t FE MXXSYAAQAARAAK Vdd tsp tub Figure 6 Write Cycle No 2 WE Controlled OE HIGH During Write 1 17 twc ADDRESS e E T S E MAY PLLA LLL LLL taw tha gt _ tsa GWE ba AXA o SE Figure 7 Write Cycle No 3 WE Controlled OE LOW B 17 two ADDRESS oS DATA I O Notes 16 Data I O is high impedance if OE Vij 17 If CE goes HIGH simultaneously with WE going HIGH the output remains in a high impedance state 18 During this period the I Os are in output state Do not apply input signals Page 7 of 11 Document Number 38 05610 Rev D Feedback ann a CYPRESS CY7C1012DV33 PERFORM Truth Table CE CE CE OE WE WOo WO7 VOg WOy5 1 0416 1 023 Mode Power H H H X X High Z High Z High Z Power Down Standby lsp L H H L H Data Out High Z High Z Read Active Icc H L H L H High Z Data Out High Z Read Active lcc H H L L H HighZz High Z Data Out Read Active Icc L L L L H Full Data Out Full Data Out Full Data Out Read Active Icc L H H X L Data In High Z High Z Write Active lcc H L H X L High Z Data In High Z Write Active lcc H H L X L High Z High Z Data In Write Active lcc L L L X L Full Data In Full Data In Full Data In Write Active lcc L L L H H High Z High Z High Z Selected Active Icc Outputs Disabled Document Number 38 05610 Rev D Page 8 of 11 Feedback CY7C1012DV33
8. he Maximum ratings for Static Discharge Voltage and Latch Up Current on page 3 Changed Iccimax from 220 mA to 150 mA Changed sp4 Max from 70 mA to 30 mA Changed Isg2 max from 40 mA to 25 mA Specified the Overshoot specification in footnote 1 Updated the Truth Table Updated the Ordering Information table 499604 NXR See ECN Added note 1 for NC pins Changed Icc specification from 150 mA to 185 mA Updated Test Condition for Icc in DC Electrical Characteristics table Added note for tace tizce tuzce tpu tpp and tgce in AC Switching Characteristics Table on page 4 C 1462585 VKN See ECN Converted from preliminary to final Updated block diagram Changed Icc specification from 185 mA to 225 mA Updated thermal specs D 2604677 VKN PYRS 11 12 08 Removed Commercial operating range Added Indusirial operating range Removed 8 ns speed bin Added 10 ns speed bin Modified footnote 3 Document Number 38 05610 Rev D Page 10 of 11 Feedback F CYPRESS PERFORM poan Sales Solutions and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices solution centers manufacturer s representatives and distributors To find the office closest to you visit us at cypress com sales Products PSoC psoc cypress com Clocks amp Buffers clocks cypress com Wireless wireless cypress com Memories memory cypre
9. he applicable Cypress software license agreement Document Number 38 05610 Rev D Revised November 6 2008 All product and company names mentioned in this document are the trademarks of their respective holders Page 11 of 11 Feedback
10. l W Z CYPRESS PERFORM Wis Q Features m High speed o LAA 10ns m Low active power a lcc 175 mA at 10 ns Low CMOS standby power q Ispo 25 mA m Operating voltages of 3 3 0 3V m 2 0V data retention m Automatic power down when deselected m TTL compatible inputs and outputs m Available in Pb free standard 119 ball PBGA CY7C1012DV33 12 Mbit 512K X 24 Static RAM Functional Description The CY7C1012DV33 is a high performance CMOS static RAM organized as 512K words by 24 bits Each data byte is separately controlled by the individual chip selects CE CE gt and CE3 CE controls the data on the I O 1 07 while CE controls the data on I Og UO s and CE controls the data on the data pins 1 046 Oo3 This device has an automatic power down feature that significantly reduces power consumption when deselected Writing the data bytes into the SRAM is accomplished when the chip select controlling that byte is LOW and the write enable input WE input is LOW Data on the respective input and output I O pins is then written into the location specified on the address pins Ag A48 Asserting all of the chip selects LOW and write enable LOW writes all 24 bits of data into the SRAM Output enable OE is ignored while in WRITE mode Data bytes are also individually read from the device Reading a byte is accomplished when the chip select controlling that byte is LOW and write enable WE HIGH
11. layer printed circuit board Oje Thermal Resistance 8 35 C W junction to case Figure 2 AC Test Loads and Waveforms 509 R1317 Q OUTPUT Vp 1 5V 3 3V Zo 502 30 pF OUTPUT T 5 pF R2 S L 3519 Including jig gt and scope b a Capacitive Load consists of all components of the test environment All input pulses 3 0V GND Rise Time gt 1V ns c Fall Time gt 1V ns Note 4 Valid SRAM operation does not occur until the power supplies have reached the minimum operating Vpp 3 0V 100us tpower after reaching the minimum operating Vpp normal SRAM operation begins including reduction in Vpp to the data retention Vccpr 2 0V voltage Page 4 of 11 Document Number 38 05610 Rev D Feedback 2P CYPRESS CY7C1012DV33 AC Switching Characteristics Over the Operating Range l Parameter Description S Unit Min Max Read Cycle tower Voc Typical to the First Access 100 us tre Read Cycle Time 10 ns LAA Address to Data Valid 10 ns toHa Data Hold from Address Change 3 ns tace CE Active LOW to Data Valid 9 10 ns tpoE OE LOW to Data Valid 5 ns LZOE OE LOW to Low Z l 1 ns HZOE OE HIGH to High z l 5 ns tLZCE CE Active LOW to Low Z 7 3 ns tuzce CE Deselect HIGH to High Z 9 7 5 ns tpy CE Active LOW to Power Up 2 9 0 ns tpp CE Deselect HIGH to Power Down 2
12. on exclusive and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in integrated circuit as specified in the applicable agreement Any reproduction modification translation compilation or represen the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATER OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Cypress reserves the right to make changes wi and subject to worldwide patent protection United States and foreign non transferable license to copy use modify create derivative works of support of licensee product to be used only in conjunction with a Cypress ation of this Source Code except as specified above is prohibited without AL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES hout further notice to the materials described herein Cypress does not assume any liability arising out of the application or use of any product or circuit described herein Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress product in a life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Use may be limited by and subject to t
13. ss com Image Sensors image cypress com CY7C1012DV33 PSoC Solutions General Low Power Low Voltage Precision Analog psoc cypress com solutions psoc cypress com low power psoc cypress com precision analog LCD Drive psoc cypress com Icd drive CAN 2 0b psoc cypress com can USB psoc cypress com usb Cypress Semiconductor Corporation 2004 2008 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or o her rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Any Source Code software and or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by United States copyright laws and international treaty provisions Cypress hereby grants to licensee a personal n
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