Cypress CY7C1007BN User's Manual
Contents
1. 7C107BN 15 7C1007BN 15 Parameter Description Min Max Unit READ CYCLE tro Read Cycle Time 15 ns tana Address to Data Valid 15 ns toHa Data Hold from Address Change 3 ns tace CE LOW to Data Valid 15 ns tLzcE CE LOW to Low Z 3 ns tHzce CE HIGH to High Z 7 7 ns tpu CE LOW to Power Up 0 ns tpp CE HIGH to Power Down 15 ns WRITE CYCLE twe Write Cycle Time 15 ns tsce CE LOW to Write End 12 ns taw Address Set Up to Write End 12 ns tua Address Hold from Write End 0 ns tsa Address Set Up to Write Start 0 ns tpwe WE Pulse Width 12 ns tsp Data Set Up to Write End 8 ns tup Data Hold from Write End 0 ns LZWE WE HIGH to Low ZlS 3 ns tHzwE WE LOW to High Zl 7 7 ns Notes 5 Test conditions assume signal transition time of 3 ns or less timing reference levels of 1 5V input pulse levels of 0 to 3 0V and output loading of the specified lol lop and 30 pF load capacitance At any given temperature and voltage condition tyzce is less than t_zce and tyzwe is less than t_zwe for any given device 6 7 tuzce and tyzwe are specified with a load capacitance of 5 pF as in part b of AC Test Loads Transition is measured 500 mV from steady state voltage 8 The internal write time of the memory is defined by the overlap of CE LOW and WE LOW CE and WE must be LOW to initiate a write and the transition of any of these signals can terminate the write The input d2. Cypress Semiconductor Corporation Document 001 06426 Rev 7C107BN 15 7C01007BN 15 Maximum Access Time ns 15 Maximum Operating Current mA 80 Maximum CMOS Standby Current Ispo mA 2 198 Champion Court San Jose CA 95134 1709 e 408 943 2600 Revised February 1 2006 CY7C107BN CYPRESS CY7C1007BN PERFORM Maximum Ratings Current into Outputs LOW ccccccsecsscssecssesseeeeees 20 mA Above which the useful life may be impaired For user guide eae eee C yea 2001y lines not tested iene i oak Storage Temperate a siainen 65 to 150 ateh Up CUEN niisiis gt m Ambient Temperature with Operating Range Power Applied 55 C to 125 C Supply Voltage on Vcc Relative to GND 0 5V to 7 0V Range Ambient Temperature Voc DC Voltage Applied to Outputs Commercial O to 70 C 5V 10 in High Z State t ooo ceeeesteeeeneee 0 5V to Vcc 0 5V Industrial 40 C to 85 C 5V 10 DC Input Voltage ssescseessesssnsesseeses 0 5V to Vec 0 5V Electrical Characteristics Over the Operating Range 7C107BN 15 701007BN 15 Parameter Description Test Conditions Min Max Unit Vou Output HIGH Voltage Voc Min lop 4 0 mA 2 4 V VoL Output LOW Voltage Vec Min lo 8 0 mA 0 4 V Vin Input HIGH Voltage 2 2 Voc 0 3 V Vi Input LOW Voltage 0 3 0 8 V lix Input Leakage
3. c ON J i 0140 0 007 U uu UU yu U U r NZ S 0 013 A f O 0 004 L Pee J 0 050 La ene 51 85031 C TYP 0 025 MIN All product or company names mentioned in this document may be the trademarks of their respective holders Document 001 06426 Rev Page 6 of 7 Cypress Semiconductor Corporation 2006 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Feedback CY7C107BN YPREoo CY7C1007BN PERFORM Document History Page Document Title CY7C107BN CY7C1007BN 1M x 1 Static RAM Document Number 001 06426 Issue Orig of REV ECN NO Date Change Description of Change ie 423847 S
4. CY7C107BN CY7C1007BN PERFORM Features High speed taa 15 ns CMOS for optimum speed power Automatic power down when deselected TTL compatible inputs and outputs 1M x 1 Static RAM Functional Description The CY7C107BN and CY7C1007BN are high performance CMOS static RAMs organized as 1 048 576 words by 1 bit Easy memory expansion is provided by an active LOW Chip Enable CE and three state drivers These devices have an automatic power down feature that reduces power consumption by more than 65 when deselected Writing to the devices is accomplished by taking Chip Enable CE and Write Enable WE inputs LOW Data on the input pin D is written into the memory location specified on the address pins Ag through A49 Reading from the devices is accomplished by taking Chip Enable CE LOW while Write Enable WE remains HIGH Under these conditions the contents of the memory location specified by the address pins will appear on the data output Dour pin The output pin Dour is placed_in a high impedance state when the device is deselected CE HIGH or during a write operation CE and WE LOW The CY7C107BN is available in a standard 400 mil wide SOJ the CY7C1007BN is available in a standard 300 mil wide SOJ Logic Block Diagram Din INPUT BUFFER 512 x 2048 ARRAY Dout ROW DECODER SENSE AMPS it Pin Configuration SOJ Top View Selection Guide
5. Current GND lt VI lt Vcc 1 1 mA loz Output Leakage Current GND lt Vi lt Vcc 5 5 mA Output Disabled los Output Short Circuit Voc Max Vout GND 300 mA Current loc Voc Operating Supply Voc Max lour 0 mA 80 mA Current f fax T trac Ispi Automatic CE Power Down_ Max Vcc CE gt Vin Vin gt Vin Or 20 mA Current TTL Inputs VIN lt Vi f f MAX Igpo Automatic CE Power Down Max Vcc CE gt Voc 0 3V 2 mA Current CMOS Inputs Vin Vcc 0 3V or Vy lt 0 3V f 0 Capacitance Parameter Description Test Conditions Max Unit Ciy Addresses Input Capacitance Ta 25 x C f 1 MHz 7 pF Cin Controls Voc 5 0V 10 pF Cout Output Capacitance 10 pF Notes 1 Vi min 2 0V for pulse durations of less than 20 ns 2 Ta is the Instant On case temperature 3 Not more than 1 output should be shorted at one time Duration of the short circuit should not exceed 30 seconds 4 Tested initially and after any design or process changes that may affect these parameters Document 001 06426 Rev Page 2 of 7 Feedback i aE wea RY 53 CYPRESo PERFORM AC Test Loads and Waveforms R1 4809 R1 4809 ALL INPUT PULSES re ee 3 0V 90 10 30 pF 5 pF GND ai Ee Maan P lt 3ns gt lt 3ns JIGAND JIGAND SCOPE a SCOPE Equivalentto THEVENIN EQUIVALENT 167Q OUTPUT0 ww _0 1 73 Switching Characteristics Over the Operating Range CY7C107BN CY7C1007BN
6. age Type Range 15 CY7C107BN 15VC 51 85032 28 Lead 400 Mil Molded SOJ Commercial CY7C1007BN 15VC 51 85031 28 Lead 300 Mil Molded SOJ CY7C1007BN 15VXC 51 85031 28 Lead 300 Mil Molded SOJ Pb free CY7C107BN 15VI 51 85032 28 Lead 400 Mil Molded SOJ Industrial Please contact local sales representative regarding availability of these parts Document 001 06426 Rev Page 5 of 7 Feedback CYPRESS PERFORM Package Diagrams CY7C107BN CY7C1007BN 28 Lead 400 Mil Molded SOJ 51 85032 PIN 11 D 14 OOnAAnnnny Vaal i DIMENSIONS IN INCHES MIN 435 MAX 395 445 A05 1 15 720 730 SEATING PLANE f l a ARARARARARAR G J bom SS Y 013 A 0 004 050 026 L o TYP 032 025 MIN 015 020 51 85032 B 28 Lead 300 Mil Molded SOJ 51 85031 NOTE 1 JEDEC STD REF MO088 2 BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION END FLASH MOLD PROTRUSION END FLASH SHALL NOT EXCEED 0 006 in 0 152 mm PER SIDE 3 DIMENSIONS IN INCHES MIN MAX DETAIL PIN 1 ID EXTERNAL LEAD DESIGN 14 1 opononoanononye m F i TR ae 0 291 LEA a300 0330 0 350 a 0 026 Tmt 0 013 0 032 i 28 0 019 0 014 0 020 OPTION 1 OPTION 2 0 697 SEATING PLANE 0 713 S AN al 0120
7. ata set up and hold timing should be referenced to the leading edge of the signal that terminates the write Document 001 06426 Rev Page 3 of 7 Feedback CY7C107BN CYPRESS _CYCI007BN Switching Waveforms Read Cycle No 1 11 tac ADDRESS DATA OUT PREVIOUS DATA VALID DATA VALID Read Cycle No 201 12 ADDRESS tLZCE HIGH HIGH IMPEDANCE DATA OUT ALLS Wa IMPEDANCE KE m Voc SUPPLY CURRENT Write Cycle No 1 CE Controlled twe ADDRESS Co CE taw tHA t ANED LII tsp tHD DATA OUT HIGH IMPEDANCE Notes 9 No input may exceed Voc 0 5V __ 10 Device is continuously selected CE Vi 11 WE is HIGH for read cycle 12 Address valid prior to or coincident with CE transition LOW 13 If CE goes HIGH simultaneously with WE going HIGH the output remains in a high impedance state Document 001 06426 Rev Page 4 of 7 Feedback CY7C107BN PERFORM Switching Waveforms continued Write Cycle No 2 WE Controlled 3 two a NNN PAR UUU taw tsa tpwe a ESS y tHD DATA IN DATA VALID gt tHzwe gt tLZWE HIGH IMPEDANCE DATA OUT DATA UNDEFINED QO m tHA CYPRESS CY7C1007BN Truth Table CE WE Dout Mode Power H X High Z Power Down Standby Isp L H Data Out Read Active lcc L L High Z Write Active lcc Ordering Information Speed Package Operating ns Ordering Code Diagram Pack
8. ee ECN NXR New Data Sheet Document 001 06426 Rev Page 7 of 7 Feedback
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