Cypress CY62157ESL User's Manual
Contents
1. Exceeding the maximum ratings may impair the useful life of the device These user guidelines are not tested CY62157ESL MoBL Output Current into Outputs LOW 20 mA Voltage ueteres gt 2001V MIL STD 883 Method 3015 Static Discharge Latch up Current gt 200 mA Storage Temperature 65 C to 150 C aum with Operating Range ower Applied to 1259 Supply Voltage to Ground 0 5V to 6 0V paes Range Vec DC Voltage Ape to Outputs CY62157ESL Industrial 40 C to 85 2 2V 3 6V in High Z Statel 41 0 5V to 6 0V and DC Input Voltage 0 5V to 6 0V 4 5V 5 5V Electrical Characteristics Over the Operating Range 45 ns Parameter Description Test Conditions Min Typ 7 Max Unit Vou Output HIGH Voltage 2 2 lt lt 2 7 0 1 mA 2 0 V 2 7 lt Vcc lt 3 6 1 0 mA 2 4 4 5 lt Vcc lt 5 5 1 0 mA 2 4 VoL Output LOW Voltage 2 2 lt Vcc lt 2 7 lo 0 1 mA 0 4 V 2 7 lt lt 3 6 loL 2 1mA 0 4 4 5 lt Vcc lt 5 5 2 1mA 0 4 Vin Input HIGH Voltage 2 2 lt Vcc lt 2 7 1 8 Vcc 0 3 V 2 7 lt Vcc lt 3 6 2 2 Vcc 0 3 4 5 lt Voc lt 5 5 2 2 Vcc 0 5 VIL2. End 0 ns tuzwE WE LOW to 2110 11 18 ns tizwE WE HIGH to Low Z l 10 ns Notes 9 Test conditions for all parameters other than tri state parameters assume signal transition time of 3 ns or less timing reference levels of 1 5V input pulse levels of 0 to and output loading of the specified lo as shown in the AC Test Loads and Waveforms on page 4 10 At any temperature and voltage condition tuzcg is less than tj tHzBE is less than tLzBE tHzoE is less than tj zog and tyzwe is less than t zwg for any device 11 tHzoE tHzcE tHzBE and tyzwe transitions are measured when the outputs enter a high impedance state 12 If both byte enables are toggled together this value is 10 ns 13 The internal write time of the memory is defined by the overlap of WE CE Vi BHE BLE or both Vi All signals must be active to initiate a write and any of these signals can terminate a write by going inactive The data input setup and hold timing must be referenced to the edge of the signal that terminates the write Document 001 43141 Rev Page 6 of 12 Feedback CY62157ESL MoBL PI CYPRESS PERFORM Figure 2 Read Cycle No 1 Address Transition Controlled 15 Switching Waveforms inc DATA VALID ADDRESS PREVIOUS DATA VALID DATA OUT Figure 3 Read Cycle No 2 OE Controlled 15 16 tep lt tHZCE gt I ADDRESS CE tACE A BEBE HIGHMPEDANCE
3. IMPEDANCE DATA OUT lt DATA VALID tLZcE tpu Vcc 50 50 SUPPLY Isp CURRENT Notes 14 The device is continuously selected OE CE Vj BHE BLE or both Vj BHE BLE transition LOW Page 7 of 12 Feedback 15 WE is HIGH for read cycle Les 16 Address valid before or similar to CE Document 001 43141 Rev CY62157ESL MoBL CYPRFSS PERFORM Switching Waveforms continued Figure 4 Write Cycle No 1 WE Controlled 13 17 18 twc ADDRESS 37 E ALLY tw tH 5 tsa tewe AX REE AR OE to _________ DATAIO XX NOTE 1S LOO lt tHZOE gt m Figure 5 Write Cycle 2 CE Controlled 13 17 18 twc mores OK lt 2 I QO m taw tha gt lt FEE SS 1 Aa rem wmo luzoE gt o m Notes 17 Data IO is high impedance if OE 18 If CE goes HIGH simultaneously vii WE Vip the output remains a high impedance state 19 During this period the IOs are in output state Do not apply input signals Document 001 43141 Rev Page 8 of 12 Feedback CY62157ESL MoBL gt gt CYPRESS PERFORM an Switching Waveforms continued Figure 6 Write Cycle 3 WE controlled OE LOW 18 SS AZ lt 142 m tew BHEIBLE Wk taw gt tHA lt ipwE gt lt tsa W
4. Input LOW Voltage 2 2 lt Voc lt 2 7 0 3 0 6 V 2 7 lt Vcc lt 3 6 0 3 0 8 4 5 lt Vcc lt 5 5 0 5 0 8 lix Input Leakage Current GND lt VI lt Vcc 1 pA loz Output Leakage Current GND lt Vo lt Vcc Output Disabled 1 1 pA loc Vcc Operating Supply f fmax 1 Voc 18 25 mA Current f 1MHz lout 0 mA 1 8 3 CMOS levels 15 1 Automatic CE Power gt Vec 0 2V Vin gt Voc 0 2V or Vin lt 0 2V 2 8 pA down Current CMOS f fmax Address and Data Only Inputs f 0 OE BHE BLE and WE Vcc Vcc max lega Automatic CE Power gt Vec 0 2V Vin gt Vec 0 2V or Vin lt 0 2V 2 8 uA down Current CMOS f 0 Veg Inputs Notes 3 Vi min 2 0V for pulse durations less than 20 ns 4 Voc 0 75V for pulse durations less than 20 ns 5 Full Device AC operation assumes 100 us ramp time from 0 to Vcc min and 200 us wait time after Voc stabilization Document 001 43141 Rev Page 3 of 12 Feedback YPRESS PERFORM Capacitance Tested initially and after any design or process changes that may affect these parameters CY62157ESL MoBL Parameter Description Test Conditions Max Unit Cin Input Capacitance TA 25 f 1 MHZ Vec Vcc typ 10 pF Cout Output Capacitance 10 pF Thermal Resistance Tested in
5. device take Chip Enable CE and Write Enable WE inputs LOW If Byte Low Enable BLE is LOW then data from pins IOo through IO7 is written into the location specified on the address pins Ag through Ag If Byte High Enable BHE is LOW then data from IO pins 0 through IO 5 is written into the location specified on the address pins Ag through A48 To read from the device take Chip Enable CE and Output Enable OE LOW while forcing the Write Enable WE HIGH If Byte Low Enable BLE is LOW then data from the memory location specified by the address pins appear on IOo to IO7 If Byte High Enable BHE is LOW then data from memory appears on lOg to IO15 See the Truth Table on page 10 for a complete description of read and write modes For best practice recommendations refer to the Cypress application note AN1064 SRAM System Guidelines DATA IN DRIVERS lt gt ROW DECODER 512K x 16 RAM Array lt gt 0 10 SENSE AMPS gt 10 COLUMN DECODER PowerDown Circuit BHE BLE Ai Ai A15 p A44 Ais m Ais gt Aig GHE GE OP BLE Cypress Semiconductor Corporation Document 001 43141 Rev 198 Champion Court San Jose CA 95134 1709
6. 29 18 313 0 72 1194 0 047 gt 0 991 0 039 0 150 0 00595 Document 001 43141 Rev DIMENSION IN MM CINCH MAX MIN 10262 0 404 4 EJECTOR PIN BOTTOM VIEW 10 262 0 404 gt 10058 0 396 0 5 0 597 0 0235 0406 0 01605 0 210 0 0083 0120 0 0047 51 85087 A Page 11 of 12 Feedback aw ESI Cypress CY62157ESL MoBL PERFORM Document History Page Document Title CY62157ESL MoBL 8 Mbit 512K x 16 Static RAM Document Number 001 43141 Orig of REV ECN NO Issue Date Change Description of Change ii 1875228 See ECN VKN AESA New Data Sheet Cypress Semiconductor Corporation 2008 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems applicatio
7. 408 943 2600 Revised January 04 2008 Feedback CYPRESS CY62157ESL MoBL Pin Configuration Figure 1 44 Pin TSOP II Top View A4 1 44 A5 2 43 13 42 A7 4 41 Ao O5 40 BHE CE 16 39 O BLE lO 17 38 5 1045 IO 8 37 1044 9 36 O 1043 1 110 35 O 104 11 34 O Vss Vss 12 33 Voc 104 113 32 O IO lOs 115 30 5 10 107 16 29 O 10 WE 117 28 As Aig 18 27 Ag Ai7 19 26 O Ajo Aig 20 25 Aq A45 21 24 A44 22 23 O Aia Product Portfolio Power Dissipation Operating Ice mA S Product Range Vec Range V 11 Speed tandby IsB2 ns f 1MHz ie uA Typ Max Typ Max Typ Max CY62157ESL Industrial 2 2V 3 6V and 4 5V 5 5V 45 1 8 3 18 25 2 8 Notes 1 Datasheet specifications are not guaranteed for Voc in the range of 3 6V to 4 5V 2 Typical values are included for reference only and are not guaranteed or tested Typical values are measured at Voc and Vec 5V Ta 25 Document 001 43141 Rev Page 2 of 12 Feedback Maximum Ratings
8. E AK J lt 7 XX tLzWE gt DATAIO lt NOTE 9 XOXOXO tuzwe Figure 7 Write Cycle 4 BHE BLE Controlled OE Low 8 ADDRESS CE BHE BLE DATA IO Page 9 of 12 Feedback Document 001 43141 Rev CY62157ESL MoBL Truth Table CE WE OE BHE BLE Inputs Outputs Mode Power H X X X High Z Deselect Power down Standby lag X X X H H High Z Deselect Power down Standby lag L H L L L Data Out IOg 1O5 Read Active lec L H L H L Data Out 105 1075 Read Active lec IOa IO15 in High Z L H L L H Data Out lOg 1O 5 Read Active lec 100 105 in High Z L H H L L High Z Output Disabled Active loc L H H H L High Z Output Disabled Active loc L H H L H High Z Output Disabled Active loc L L X L L Data In 105 105 Write Active loc L L X H L Data In IOg 1O Write Active loc lOg 1O 5 in High Z L L X L H Data In IOg 1O 5 Write Active loc lOc 1O in High Z Ordering Information Ordering Code Package Type 45 CY62157ESL 45ZSXI 51 85087 44 pin Thin Small Outline Package Type II Pb free Industrial Document 001 43141 Rev Page 10 of 12 Feedback Package Diagrams CY62157ESL MoBL Figure 8 44 Pin TSOP Il 51 85087 TOP VIEW BASE PLANE A 0 800 BSC 2 400006 00315 0 300 0 012 18 517 0 7
9. SM 9 SN aS e er _ LA e u 5 MAE 2 m mM a YPRESS PERFORM Features Very high speed 45 ns m Wide voltage range 2 2V 3 6V and 4 5V 5 5V m Ultra low standby power Typical Standby current 2 pA Maximum Standby current 8 uA m Ultra low active power Typical active current 1 8 mA at f 1 MHz m Easy memory expansion with CE and OE features m Automatic power down when deselected m CMOS for optimum speed and power m Available in Pb free 44 pin TSOP Il package Functional Description The CY62157ESL is a high performance CMOS static RAM organized as 512K words by 16 bits This device features advanced circuit design to provide ultra low active current This is ideal for providing More Battery Life MoBL in portable applications such as cellular telephones The device also has an automatic power down feature that significantly reduces power consumption when addresses are not toggling Place the device Logic Block Diagram CY62157ESL MoBL 8 Mbit 512K x 16 Static RAM into standby mode when deselected CE HIGH or both BHE and BLE are HIGH The input or output pins IOo through 10 5 are placed in a high impedance state when m Deselected CE HIGH m Outputs are disabled OE HIGH m Both Byte High Enable and Byte Low Enable are disabled BHE BLE HIGH m Write operation is active CE LOW and WE LOW To write to the
10. esign or process changes that may affect these parameters 7 Full device operation requires linear Vcc ramp from Vpg to Vecimin gt 100 us or stable at Vccmin gt 100 us 8 BHE BLE is the AND of both BHE and BLE Deselect the chip by either disabling chip enable signals or by disabling both BHE and BLE Document 001 43141 Rev lt gt n F CYPRESS PERFORM CY62157ESL MoBL Switching Characteristics Over the Operating Range Parameter Description 2900 Unit Min Max Read Cycle Read Cycle Time 45 ns tAA Address to Data Valid 45 ns toHA Data Hold from Address Change 10 ns tAcE CE LOW to Data Valid 45 ns tpoE OE LOW to Data Valid 22 ns tizoE OE LOW to LOW ZI 0l 5 ns tuzoE OE HIGH to High zl10 11 18 ns lizcE CE LOW to Low z 0 10 ns tHzcE CE HIGH to 2110 11 18 ns tpu CE LOW to Power Up 0 ns HIGH Power Down 45 ns BLE BHE LOW to Data Valid 45 ns tLZBE BLE BHE LOW to Low Z 9 12 5 ns tHzBE BLE BHE HIGH to HIGH ZL10 111 18 ns Write Cyclel13 twc Write Cycle Time 45 ns tscE CE LOW to Write End 35 ns taw Address Setup to Write End 35 ns tua Address Hold from Write End 0 ns tsa Address Setup to Write Start 0 ns tpwe WE Pulse Width 35 ns tew BLE BHE LOW to Write End 35 ns tsp Data Setup to Write End 25 ns tHD Data Hold from Write
11. itially and after any design or process changes that may affect these parameters Parameter Description Test Conditions TSOP Il Unit OJA Thermal Resistance Still Air soldered on a 3 x 4 5 inch two layer 77 C W Junction to Ambient printed circuit board Thermal Resistance 13 C W Junction to Case AC Test Loads and Waveforms R1 ALL INPUT PULSES Vcc Yeo 90 OUTPUT 10 GND 30 pF R2 Rise Time 1 V ns Fall Time 1 V ns INCLUDING JIG AND m Equivalent to EQUIVALENT SCOPE R TH OUTPUT o v o Vy Parameters 2 5V 3 0V 5 0V Unit R1 16667 1103 1800 Q R2 15385 1554 990 Q RTH 8000 645 639 Q VTH 1 20 1 75 1 77 V Page 4 of 12 Document 001 43141 Rev Feedback L Ed CYPRESS CY62157ESL MoBL sd PERFORM Data Retention Characteristics Over the Operating Range Parameter Description Conditions Min Typ Max Unit VDR Vcc for Data Retention 1 5 V 6608 Data Retention Current CE gt Vcc 0 2V Vcc 1 5V 2 5 uA VIN 2 Voc 0 2V or Vin lt 0 2V Wee 20V 2 8 Ii Chip Deselect to Data 0 ns Retention Time 7 Recovery tRc ns Data Retention Waveform DATA RETENTION MODE Vccmin VpR gt 1 5V VcC min tcDR gt in CE or 8 BHE BLE Page 5 of 12 Feedback Notes 6 Tested initially and after any d
12. n implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Any Source Code software and or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign United States copyright laws and international treaty provisions Cypress hereby grants to licensee a personal non exclusive non transferable license to copy use modify create derivative works of and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement Any reproduction modification translation compilation or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Cypress reserves the right to make changes without further notice to the materials described herein Cypress does not assume any liability arising out of the application or use of any product or circuit described herein Cypress does not authorize its products for use as critical components in life support systems
13. where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress product in a life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Use may be limited by and subject to the applicable Cypress software license agreement Document 001 43141 Rev Revised January 04 2008 Page 12 of 12 is a registered trademark and More Battery Life is a trademark of Cypress Semiconductor All product and company names mentioned in this document are the trademarks of their respective holders Feedback
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