Cypress CY62148ESL User's Manual
Contents
1. LOW while forcing Write Enable WE HIGH Under these conditions the contents of the memory location specified by the address pins appear on the IO pins For best practice recommendations refer to the Cypress application note AN1064 SRAM System Guidelines a Typical standby current 1 uA a Maximum standby current 7 nA m Automatic power down when deselected Logic Block Diagram Cypress Semiconductor Corporation 198 Champion Court San Jose CA 95134 1709 408 943 2600 Document 001 50045 Rev Revised January 21 2009 Feedback Ea LW CYPRESS _ pe realestate PERFORM Pin Configuration Product Portfolio Figure 1 32 Pin STSOP Top View STSOP Top View not to scale CY62148ESL MoBL Power Dissipation Operating Icc mA Speed CC Standby Product Range Vec Range V 1 gt SB2 a ns f 1MHz ths uA Typ 1 Max Typ Max Typ Max CY62148ESL Industrial 2 2V to 3 6V and 4 5V to 5 5V 55 2 2 5 15 20 1 7 Notes 1 Data sheet specifications are not guaranteed for Vcc in the range of 3 6V to 4 5V 2 Typical values are included for reference only and are not guaranteed or tested Typical values are measured at Voc Vocityp Ta 25 C Page 2 of 10 Document 001 50045 Rev Feedback gt r F CYPRESS CY62148ESL MoBL PERFORM Maximum Ratings Output Current into Outputs L2. 4 5 lt Vcc lt 5 5 0 5 0 6 lix Input Leakage Current GND lt V lt Vec 1 1 pA loz Output Leakage Current GND lt Vo lt Vcc Output Disabled 1 1 pA loc Vcc Operating Supply f fmax I trc Voc Vccmax 15 20 mA Current f 1MHz lout 0 mA CMOS levels 25 Ispi Automatic CE Power CE gt Voc 0 2V Vin gt Voc 0 2V or Vin lt 0 2V 1 7 pA Down Current CMOS If fmax Address and Data Only f 0 OE and WE Inputs Vcc Voc max Ispe Automatic CE Power CE gt Vec 0 2V Vin gt Voc 0 2V or Vin lt 0 2V 1 7 pA Down Current CMOS f 0 Vec Voc max Inputs Notes 3 ViL min 2 0V for pulse durations less than 20 ns 4 Viy max Vcc 0 75V for pulse durations less than 20 ns 5 Full device AC operation assumes a minimum of 100 us ramp time from 0 to Vcc min and 200 us wait time after Vcc stabilization 6 Under DC conditions the device meets a V of 0 8V for Voc range of 2 7V to 3 6V and 4 5V to 5 5V and 0 6V for Voc range of 2 2V to 2 7V However in dynamic conditions Input LOW voltage applied to the device must not be higher than 0 6V and 0 4V for the above ranges Refer to AN13470 for details Document 001 50045 Rev Page 3 of 10 Feedback gt r a 7 CYPRESS CY62148ESL MoBL OO PERFORM Capacitance Tested initially and after any design or pr
3. before or similar to CE transition LOW 16 Data IO is high impedance if OE Viy _ 17 1f CE goes HIGH simultaneously with WE HIGH the output remains in high impedance state 18 During this period the IOs are in output state Do not apply input signals Document 001 50045 Rev Page 7 of 10 Feedback 7 CYPRESS CY62148ESL MoBL PERFORM Switching Waveforms continued Figure 6 Write Cycle No 2 CE Controlled 17 ADDRESS twe tso thp Figure 7 Write Cycle No 3 WE Controlled OE LOW P7 two appRESS OK O E MOQ JAIL LLL taw tHA tsa tpwe w TA aiaa CE AA C omn OX tHZWE tLZWE Truth Table CE WE OE Inputs Outputs Mode Power H X X High Z Deselect Power Down Standby lsp L H L Data Out Read Active lcc L H H High Z Output Disabled Active lcc L L X Data in Write Active lcc Document 001 50045 Rev Page 8 of 10 Feedback o CYPRESS PERFORM f i Ordering Information CY62148ESL MoBL Speed F Package Operating ns Ordering Code Diagram Package Type Range 55 CY62148ESL 55ZAXI 51 85094 32 Pin STSOP Pb Free Industrial Package Diagram Figure 8 32 Pin Shrunk Thin Small Outline Package 8 x 13 4 mm 51 85094 oO DIMENSION IN MM Alu 13 20 MIN var 13 60 MAX cola 1 20 11 70 a0 MAX 0 05 E 05
4. Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Cypress reserves the right to make changes without further notice to the materials described herein Cypress does not assume any liability arising out of the application or use of any product or circuit described herein Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress product in a life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Use may be limited by and subject to the applicable Cypress software license agreement Document 001 50045 Rev Revised January 21 2009 Page 10 of 10 MoBL is a registered trademark and More Battery Life is a trademark of Cypress Semiconductor All product and company names mentioned in this document are the trademarks of their respective holders Feedback
5. ORIENTATION ID aS Njo 0 95 ii ko SEATING PLANE s n i 1 A 010MM o 5 0 675 p25 MIN GAUGE PLANE 0 30 0 70 51 85094 D Page 9 of 10 Document 001 50045 Rev Feedback Ea o ya e CYPRESS CY62148ESL MoBL N PERFORM Document History Page Document Title CY62148ESL MoBL 4 Mbit 512K x 8 Static RAM Document Number 001 50045 Rev ECN No Orig of Submission Description of Change Change Date oe 2612938 VKN PYRS 01 21 09 New data sheet Sales Solutions and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices solution centers manufacturer s representatives and distributors To find the office closest to you visit us at cypress com sales Products PSoC Solutions PSoC psoc cypress com General psoc cypress com solutions Clocks amp Buffers clocks cypress com Low Power Low Voltage psoc cypress com low power Wireless wireless cypress com Precision Analog psoc cypress com precision analog Memories memory cypress com LCD Drive psoc cypress com Icd drive Image Sensors image cypress com ee pane cypress goign USB psoc cypress com usb Cypress Semiconductor Corporation 2009 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or im
6. OW 20 mA Static Discharge Voltage ccceceeeesseeeteeeeeerees gt 2001V Exceeding maximum ratings may impair the useful life of the f LANT MIL STD 883 Method 3015 device These user guidelines are not tested irage Teiopeie iien 65 C to 150 Latch Up Current ccecceeseeeeeeeneeeeeeseeeeneeeeeeeeaes gt 200 mA een et ala with PE E Operating Range ower JOG ihia ei O z Supply E to Ground Device Range recurs Veo Potential ciiges oti esac oera 0 5V to 6 0V CY62148ESL Industrial 40 C to 85 C 2 2V to 3 6V DC Voltage Applied to Outputs and in High Z State B 40 ol cceeeeseesesseeseseeneees 0 5V to 6 0V 4 5V to 5 5V DC Input Voltage 84 ooo ccceceessessesseeseeseeeees 0 5V to 6 0V Electrical Characteristics Over the Operating Range 55 ns Parameter Description Test Conditions Min Typ Max Unit Von Output HIGH Voltage 2 2 lt Voc lt 2 7 lon 0 1 mA 2 0 V 2 7 lt Voc lt 3 6 lon 1 0 mA 2 4 4 5 lt Vcc lt 5 5 lon 1 0 mA 2 4 VoL Output LOW Voltage 2 2 lt Voc lt 2 7 lo 0 1 mA 0 4 V 2 7 lt Vcc lt 3 6 loL 2 1 mA 0 4 4 5 lt Vcc lt 5 5 loL 2 1 mA 0 4 Vin Input HIGH Voltage 2 2 lt Vec lt 2 7 1 8 Voc 03 v 2 7 lt Vec lt 3 6 2 2 Voc 0 3 4 5 lt Vcc lt 5 5 2 2 Vcc 0 5 Vi 6 Input LOW Voltage 2 2 lt Voc lt 2 7 0 3 0 4 V 2 7 lt Vcc lt 3 6 0 3 0 6
7. R Vecimin tcpR gt Notes 7 Tested initially and after any design or process changes that may affect these parameters 8 Full device operation requires linear Voc ramp from Vpp to Vcc min 100 us or stable at Vec min gt 100 us Document 001 50045 Rev Page 5 of 10 Feedback a CY PERFORM PRESS Switching Characteristics Over the Operating Range CY62148ESL MoBL Parameter Description 2 Unit Min Max Read Cycle tre Read Cycle Time 55 ns tAA Address to Data Valid 55 ns toHa Data Hold from Address Change 10 ns tace CE LOW to Data Valid 55 ns tDOE OE LOW to Data Valid 25 ns LZOE OE LOW to Low Z M 5 ns tHz0E OE HIGH to High z 0 11 20 ns tLzcE CE LOW to Low Z 0 10 ns tuzceE CE HIGH to High Z 11 20 ns tpy CE LOW to Power Up 0 ns tpp CE HIGH to Power Up 55 ns Write Cycle 21 twe Write Cycle Time 55 ns scE CE LOW to Write End 40 ns taw Address Setup to Write End 40 ns tua Address Hold from Write End 0 ns tsa Address Setup to Write Start 0 ns tpwe WE Pulse Width 40 ns tsp Data Setup to Write End 25 ns tub Data Hold from Write End 0 ns tuzwe WE LOW to High Z 10 11 20 ns tLzwe WE HIGH to Low Z 0 10 ns Notes 9 Test conditions for all parameters other than tri state parameters assume signal transition time of 3 ns or less 1 V ns timing reference levels of Vec typ 2 inpu
8. WW ar o e A o e Pi CYPRESS CY62148ESL MoBL PERFORM 4 Mbit 512K x 8 Static RAM Features Functional Description m Very high speed 55 ns The CY62148ESL is a high performance CMOS static RAM i organized as 512K words by 8 bits This device features m Wide voltage range 2 2V to 3 6V and 4 5V to 5 5V advanced circuit design to provide ultra low active current This m Ultra low standby power is ideal for providing More Battery Life MoBL in portable applications such as cellular telephones The device also has an automatic power down feature that significantly reduces power consumption Placing the device into standby mode reduces m Ultra low active power power consumption by more than 99 percent when deselected o Typical active current 2 mA atf 1 MHz CE HIGH The eight input and output pins IO through 107 are a placed in a high impedance state when the device is deselected m Easy memory expansion with CE and OE features CE HIGH the outputs are disabled OE HIGH or during a write operation CE LOW and WE LOW To write to the device take Chip Enable CE and Write Enable E CMOS foroptimu m speed andPower WE inputs LOW Data on the eight IO pins IO through 10 is m Available in Pb free 32 pin STSOP package then written into the location specified on the address pins Ap through A48 To read from the device take Chip Enable CE and Output Enable OE
9. ocess changes that may affect these parameters Parameter Description Test Conditions Max Unit Cin Input Capacitance Ty 25 f 1 MHz 10 pF Cout Output Capacitance Vcc Veciyp 10 pF Thermal Resistance Tested initially and after any design or process changes that may affect these parameters Parameter Description Test Conditions STSOP Unit OJA Thermal Resistance Still Air soldered on a 3 x 4 5 inch two layer printed 49 02 C W Junction to Ambient circuit board Ojc Thermal Resistance 14 07 C W Junction to Case Figure 2 AC Test Loads and Waveforms R1 Voc ALL INPUT PULSES OUTPUT Vcc 90 10 30 pF R2 GND T Rise Time 1 V ns gt Fall Time 1 V ns INCLUDING 7 7 JIG AND SCOPE Equivalent to THEVENIN EQUIVALENT RTH OUTPUT o wmo V Parameters 2 50V 3 0V 5 0V Unit R1 16667 1103 1800 Q R2 15385 1554 990 Q RH 8000 645 639 Q VTH 1 20 1 75 1 77 V Document 001 50045 Rev Page 4 of 10 Feedback _ S amp A CYPRESS CY62148ESL MoBL PERFORM Data Retention Characteristics Over the Operating Range Parameter Description Conditions Min Typ Max Unit VDR Vcc for Data Retention 1 5 V locpr Data Retention Current CE gt Vcc 0 2V Voc 1 5V 1 7 uA Vin gt Voc 0 2V or VIN lt 0 2V tcpr Chip Deselect to Data Retention Time tR 8 Operation Recovery Time tro ns DATA RETENTION MODE Vpr gt 1 5V Vec min t
10. ply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical ife support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Any Source Code software and or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign United States copyright laws and international treaty provisions Cypress hereby grants to licensee a personal non exclusive non transferable license to copy use modify create derivative works of and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement Any reproduction modification translation compilation or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress
11. t pulse and output loading of the specified Io Io4 as shown in AC Test Loads and Waveforms on page 4 levels of 0 to Veci 10 At any given temperature and voltage condition tyzce is less than tLzce tyzoe is less than tLzog and tyzwe is less than t_zwe for any given device 11 tuzoe tuzce and tyzwe transitions are measured when the output enter a high impedance state 12 The internal write time of the memory is defined by the overlap of WE CE Vi All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE The data input setup and hold timing must be referenced to the edge of the signal that terminates the write Document 001 50045 Rev Page 6 of 10 Feedback E a ge J CYPRESS CY62148ESL MoBL PERFORM Switching Waveforms Figure 3 Read Cycle No 1 Address Transition Controlled H3 14 tRC ADDRESS DATA OUT PREVIOUS DATA VALID DATA VALID Figure 4 Read Cycle No 2 OE Controlled l4 15 ADDRESS CE OE tLZ0E HIGH HIGH IMPEDANCE f V IMPEDANCE DATA OUT KSA iui adit Voc lee SUPPLY CURRENT lop Figure 5 Write Cycle No 1 WE Controlled OE HIGH During Write 16 17 two aooress OX OOOO TE OX LLM LILLE OX NA ZL taw tHa tsa tpwe WE WX AAAS 5E We E LMI tHD DATA IO lt notes lt lt KX xX DATA VALID tHZOE Notes 13 Device is continuously selected OE CE Vj 14 WE is HIGH for read cycles 15 Address valid
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