Cypress CY62138FV30 User's Manual
Contents
1. Speed Package Operating ns Ordering Code Diagram Package Type Range 45 CY62138FV30LL 45BVXI 51 85149 36 ball VFBGA Pb free Industrial CY62138FV30LL 45ZSXI 51 85095 32 pin TSOP II Pb free CY62138FV30LL 45ZAXI 51 85094 32 STSOP Pb free CY62138FV30LL 45ZXI 51 85056 32 pin TSOP I Pb free CY62138FV30LL 45SXI 51 85081 32 SOIC Pb free Package Diagrams Figure 1 36 ball VFBGA 6 x 8 x 1 mm 51 85149 TOP VIEW BOTTOM VIEW A1 CORNER 7 0 05 M 1 CORNER 2025 MEAP 0 30 0 05 36X 12 3 4 5 6 6 5 4 3 2 1 7 N A A B 9000 B O OO O 2 D O E E 8 5 e n 4 O r 6 B H i 9 1 875 lt 6 00 0 10 0 75 3 75 lt 600400 bol x 0 15 4X 4 5 3 o 3 s I T 1 CZ X7 X71 1 SEATING PLANE s 2 51 85149 Document 001 08029 Rev E Page 8 of 13 Feedback CYPRESS Package Diagrams continued Figure 2 32 pin TSOP 51 85095 TOP VIEW 127 BSC Document 001 08029 Rev E 32 CY62138FV30 MoBL SEE DETAIL DIMENSIONS IN MILLIMETERS MIN MAX2. P gt r M 2 W ma r_w SSE rsh r m mr Y YPRESS CY62138FV30 MoBL PERFOR Mm Features Very high speed 45 ns Wide voltage range 2 20V 3 60V Pin compatible with CY62138CV25 30 33 Ultra low standby power Typical standby current 1 pA Maximum standby current 5 pA Ultra low active power Typical active current 1 6 mA f 1 MHz Easy memory expansion with features Automatic power down when deselected CMOS for optimum speed and power Offered in Pb free 36 ball VFBGA 32 pin TSOP II 32 pin SOIC 32 pin TSOP and 32 pin STSOP packages Logic Block Diagram CE CE2 2 Mbit 256K x 8 Static Functional Description 1 The CY62138FV30 is a high performance CMOS static RAM organized as 256K words by 8 bits This device features advanced circuit design to provide ultra low active current This is ideal for providing More Battery Life MoBL in portable applications such as cellular telephones The device also has an automatic power down feature that significantly reduces power consumption Place the device into standby mode reducing power consumption when deselected CE HIGH or CE LOW To write to the device take Chip Enable CE LOW and CE3 HIGH and Write Enable WE inputs LOW Data on the eight IO pins IO through 107 is then written int
3. Max Typ 8 CY62138FV30LL 2 2 3 0 3 6 45 1 6 2 5 13 18 1 5 Note 2 NC pins are not connected on the die Typical values are included for reference only and are not guaranteed or tested Typical values are measured at Ta 25 C Document 001 08029 Rev E Page 2 of 13 Feedback CYPRESS 2 CYG2I38FV30 MOBL PERFORM 4 Maximum Ratings DC Input Voltage 0 3V to 3 9V Exceeding maximum ratings may impair the useful life of the Copa into Outputs LOW 20 mA device These user guidelines are not tested 2 gt 2001V Storage Temperature 65 C to 150 C ad doen Ambient Temperature with atch up gt 200m Power 55 C to 125 Ambient 6 Supply Voltage to Ground Product Range Temperature Potential aw died 0 3V to 3 9V CY62138FV30LL Industrial 40 C to 85 2 2V to 3 6V DC Voltage Applied to Outputs in High Z State 0 3 to 3 9V Electrical Characteristics Over the Operating Range Parameter Description Test Conditions
4. us wait time after Vcc stabilization 7 Only chip enables CE and CE2 must be at CMOS level to meet the 5 2 spec Other inputs can be left floating 8 Tested initially and after any design or process changes that may affect these parameters Document 001 08029 Rev E Page 3 of 13 Feedback Thermal Resistance 81 CY62138FV30 MoB 19 Parameter Description Test Conditions SOIC VFBGA TSOP II STSOP TSOP I Unit OJA Thermal Resistance Still air soldered on a 3 x 4 5 44 53 38 49 44 16 59 72 50 19 C W Junction to Ambient inch two layer printed circuit Oje Thermal Resistance board 24 05 17 66 11 97 15 38 14 59 9 Junction to Case AC Test Loads and Waveforms R1 Vcc ALL INPUT PULSES OUTPUT 90 10 30 pF R2 GND Rise Time 1 V ns Fall Time 1 V ns INCLUDING 7 7 JIG AND Equivalent to THEVENIN EQUIVALENT RTH OUTPUT o v Y V Parameters 2 5V 2 2V to 2 7V 3 0V 2 7V to 3 6V Unit R1 16667 1103 R2 15385 1554 8000 645 VTH 1 20 1 75 V Data Retention Characteristics Over the Operating Range Parameter Description Conditions Min Typ 3 Max Unit VDR Vcc for Data Retention 1 5 V 2 Data Retention Current 1 5V 1 4 CE gt Vcc 0 2V lt 0 2V Vin gt Vec 0 2V or ViN lt 0 2 tcpR 8 Ch
5. 15 z5 V MIN R 0 12 MIN R 0 12 0 25 0 5 0 40 0 60 DETAIL A 51 85095 Page 9 of 13 Feedback CY62138FV30 MoBL R O Sey es _ CYPRESS Package Diagrams continued Figure 3 32 pin 450 Mil Molded SOIC 51 85081 0 546 13 868 0 566 14 376 0 440 11 176 0 450 11 430 CHAE 17 32 0 793 20 142 0 817 20 751 0 006 0 152 0 012 0 304 0 101 2 565 041802997 HII d H c 0 004 0 102 j 0 047 1 193 L 0 004 0 102 0 063 1 600 zn M N 0 023 0 584 i 0 014 0 355 0 039 0 990 SEATING PLANE 51 85081 0 020 0 508 Page 10 of 13 Document 001 08029 Rev Feedback PERFORM Package Diagrams continued Figure 4 32 TSOP I 8 x 20 51 85056 CY62138FV30 MoBL DIMENSION IN MM MIN MAX 19 80 20 20 ORIENTATION ID 18 30 1 20 18 50 SS 0 50 TYP ES t 017 0 27 040 0 95 b 1 05 Fi x Document 001 08029 Rev ojo gt SEATING Z 10 51 85056 Page 11 of 13 Feedback CYPRESS PERFORM 22222222 Package Diagra
6. UT Vcc SUPPLY CURRENT Isp Write Cycle No 1 WE controlled 10 14 18 19 twc lt tscE taw tha gt tsa tpwe E R RANNU E 10 lt NorE20 DATA VALID tuzoE Notes _ 15 The device is continuously selected OE Vi CE 16 WE is HIGH for read cycle 17 Address valid before or similar to CE transition LOW and transition HIGH 18 Data IO is high impedance if OE Vj 19 If CE goes HIGH goes LOW simultaneously with WE HIGH the output remains in high impedance state 20 During this period the IOs in output state Do not apply input signals Document 001 08029 Rev E Page 6 of 13 Feedback CYPRESS CY62138FV30 MoBL PERFORM Switching Waveforms continued Write Cycle No 2 CE2 controlled 119 14 18 19 tsp DATA IO DATA VALID Write Cycle 3 WE controlled OE LOW 119 19 ADDRESS IOs Rs K tHZWE tLZwe Truth Table CE CE WE OE Inputs Outputs Mode Power H X X X High Z Deselect Power Down Standby Isp X L X X High Z Deselect Power Down Standby Isp L H H L Data Out Read Active L H H H High Z Output Disabled Active L H L X Data in Write Active Document 001 08029 Rev E Page 7 of 13 Feedback CY62138FV30 MoBL
7. ip Deselect to Data Retention Time 0 ns tg Pl Operation Recovery Time tgc ns Data Retention Waveform 19 DATA RETENTION MODE Vpr gt 1 5V Notes 9 Full device AC operation requires linear Vcc ramp from Vpr to Vcc min gt 100 us or stable at Vcc min gt 100 us 10 CE is the logical combination of CE and When CE is LOW and CE is HIGH CE is LOW when CE is HIGH or is LOW CE is HIGH Document 001 08029 Rev E Page 4 of 13 Feedback CYPRESS PERFORM Switching Characteristics Over the Operating Range 1 CY62138FV30 MoBL 45 ns Parameter Description Unit Min Max Read Cycle tro Read Cycle Time 45 ns taa Address to Data Valid 45 ns toHA Data Hold from Address Change 10 ns tACE CE4 LOW and CE HIGH to Data Valid 45 ns tpoE OE LOW to Data Valid 22 ns tizoE OE LOW to Low Z 112 5 ns tuzoE OE HIGH to High Z 112 131 18 ns tizcE CE LOW and CE HIGH to Low 2 1172 10 ns tuzce CE HIGH or CE LOW to High z 112 19 18 ns tpu CE LOW and HIGH to Power Up 0 ns tpp CE HIGH or LOW to Power Down 45 ns Write Cycle 4l twc Write Cycle Time 45 ns tsce CE LOW and CE HIGH to Write End 35 ns taw Address Setup to Write End 35 ns tua Address Hold from Write End 0 ns tsa Address Setup to Write Start 0 ns tpwe WE Pulse Width 35 ns tsp Data Setup to Write End 25 ns tup Data Hold from Wri
8. ms continued Figure 5 32 pin STSOP 8 x 13 4 mm 51 85094 L9 DIMENSION IN MM Au 13 20 MIN a 13 60 M amp X ri s 11 70 11 90 0 05 0 15 0 50 E ORIENTATION LD Nloo 017 0 23 0 21 0 25 SEATING PLANE 10 1 iI Fd CX 0 10MM 97 47 025 0 675 MIN G 0 30 0 70 51 85094 D MoBL is a registered trademark and More Battery Life is a trademark of Cypress Semiconductor All product and company names mentioned in this document may be the trademarks of their respective holders Document 001 08029 Rev E Page 12 of 13 Cypress Semiconductor Corporation 2007 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies
9. o the location specified on the address pins Ag through A47 To read from the device take Chip Enable CE LOW and HIGH and Output Enable OE LOW while forcing Write Enable WE HIGH Under these conditions the contents of the memory location specified by the address pins appear on the IO pins The eight input and output pins IOo through 1 are placed a high impedance state when the device is deselected CE HIGH or LOW the outputs are disabled OE HIGH or during a write operation CE LOW and HIGH and WE LOW SENSE AMPS Note 1 For best practice recommendations refer to the Cypress application note System Design Guidelines at http www cypress com Cypress Semiconductor Corporation Document 001 08029 Rev E 198 Champion Court San Jose CA 95134 1709 408 943 2600 Revised March 26 2007 Pin Configuration 2 36 Ball Top View QOGOOO m e 60 60 6 G9 90969 TSOP View Top not to scale CY62138FV30 MoBL 32 SOIC TSOP II Top View 5 QO N STSOP Top View not to scale Product Portfolio Power Dissipation Vcc Range V Operating mA Product Speed Standby 15 2 uA 1 MHz 3 Max Typ 3 Max Typ 3
10. on Unit Min 8 Max Vou Output HIGH Voltage lop 0 1 mA 2 0 V 1 0 mA gt 2 70V 2 4 V VoL Output LOW Voltage lo 0 1 mA 0 4 V lo 2 1 mA Vcc gt 2 70V 0 4 V Input HIGH Voltage Vec 2 2V to 2 7V 1 8 0 3 V 2 7V to 3 6V 2 2 0 3 V Vit Input LOW Voltage Vec 2 2V to 2 7V For BGA package 0 3 0 6 V Vec 2 7V to 3 6V 0 3 0 8 V Vec 2 2V to 3 6V For other packages 0 3 0 6 V lix Input Leakage Current GND lt VI lt 1 1 loz Output Leakage Current GND lt Vo lt 1 1 uA output disabled lec Vec Operating Supply Current f fmax 1 tgc Voc 13 18 mA f 1MHz CU aoe 1 6 2 5 Isp1 Automatic CE Power Down CE gt 0 2V or CE lt 0 2V 1 5 Current CMOS Inputs Vin gt Vcc 0 2V Viy lt 0 2 f fmax address and data only f 0 OE and WE Vcc 3 60V 1582 171 Automatic Power Down CE gt Voc 0 2V or lt 0 2V 1 5 Current CMOS Inputs Vin gt Vcc 0 2V or Vin lt 0 2 f 0 3 60V Capacitance For all packages 81 Parameter Description Test Conditions Max Unit Cin Input Capacitance 25 C f 1 MHz 10 pF Output Capacitance 10 pF Notes 4 ViL min 2 0 for pulse durations less than 20 ns 5 Vect0 75V for pulse durations less than 20 ns 6 Full device AC operation assumes a 100 us ramp time from 0 to Vcc min and 200
11. te End 0 ns tuzwE WE LOW to High Z 172 13 18 ns tLzwE WE HIGH to Low Z 12 10 ns Notes 11 Test conditions for all parameters other than tri state parameters assume signal transition time of 3 ns or less 1 V ns timing reference levels 2 input pulse levels of 0 to and output loading of the specified lo as shown the Test Loads and Waveforms page 4 12 At any given temperature and voltage condition is less than tj is less than tj zog and tyzwe_ is less than tj for any given device 13 tuzog and tyzwe transitions are measured when the output enters a high impedance state All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE Reference the data input setup and hold timing to the edge of the signal that terminates the write 14 The internal write time of the memory is defined by the overlap of WE CE Document 001 08029 Rev E 5 of 13 Feedback 2138 30 MOBL PERFORM C Switching Waveforms Read Cycle 1 Address transition controlled 115 16 tRC ADDRESS DATA OUT PREVIOUS DATA VALID DATA VALID Read Cycle No 2 OE controlled 19 16 17 ADDRESS CE tpog lt HIGH IMPEDANCE tLZ0E HIGH IMPEDANCE DATA O
12. that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Feedback Wag CYPRESS PERFORM Document History Page CY62138FV30 MoBL Document Title CY62138FV30 MoBL 2 Mbit 256K x 8 Static RAM Document Number 001 08029 REV Ssue Orig Ke Description of Change S 463660 See New data sheet 467351 See Added 32 TSOP II package 32 TSOP and 32 STSOP packages Changed ball from NC to CE in 36 ball FBGA pin out B 566724 See Converted from Preliminary to Final Corrected typo in 32 pin TSOP II pin configuration diagram on page 2 changed pin 24 from CE4to OE and pin 22 from CE to CE4 Changed the value from 2 25 mA to 2 5 mA for test condition f 1 MHz Changed the value from 0 5 uA to 1 pA Changed the 15 2 value from 2 5 to 5 pA Changed the ICcCDR typ value from 0 5 uA to 1 and IcCDR max value from 2 5 HA to 4 C 797956 See VKN Added 32 pin SOIC package Updated VIL spec for SOIC TSOP I STSOP packages on Electrical characteristics table D 809101 See VKN Corrected typo in the Ordering Information table 940341 See Added footnote 7 related to Isp2 and Iccpr Document 001 08029 Rev E Page 13 of 13 Feedback
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