Cypress CY62137FV30 User's Manual
Contents
1. 20 05 MC V go25MC B 0 30 0 05 48X 6 5 4 3 2 1 d p 900 000 x al OOO OOO e s e lt og 1 875 0 75 3 75 6 00 0 10 0 15 4X 51 85150 D Page 10 of 12 Feedback f CYPRESS CY62137FV30 MoBL PERFORM Package Diagram continued Figure 12 44 Pin TSOP II DIMENSION IN MM INCH MAX MIN 10 262 0 404 EJECTDR PIN BOTTOM VIEW VIEW 10 262 0 4045 100585 0 3965 BASE PLANE 0 5 0 210 0 0083 gt 0150 0 00475 0 10 004 0 597 0 0235 0406 0 01605 0 0315 40060 0 800 2d F 0300 18 517 0 789 18313 0 721 51 85087 A 0 150 0 0059 gt 1194 0 0475 Document Number 001 07141 Rev F Page 11 of 12 Feedback F CYPRESS CY62137FV30 MoBL Document History Page Document Title CY62137FV30 MoBL 2 Mbit 128K x 16 Static RAM Document Number 001 07141 Issue Orig of REV ECN NO Date Change Description of Change P 449438 See ECN NXR New datasheet A 464509 See ECN NXR Changed the Isp ayp value from 1 0 uA to 0 5 HA Changed the 1 value from 4 uA to 2 5 uA Changed the Iccayp value from 2 mA to 1 6 mA and Icc max value from 2 5 m2. PERFORM Features m Very high speed 45 ns m Temperature ranges Industrial C40 C to 85 C Automotive A 40 C to 85 C Automotive E 40 C to 125 C m Wide voltage range 2 20V 3 60V m Pin compatible with CY62137CV CV25 CV30 CV33 CY62137V and CY62137EV30 m Ultra low standby power Typical standby current 1 pA Maximum standby current 5 pA Industrial m Ultra low active power Typical active current 1 6 mA at f 1 MHz 45 ns speed m Easy memory expansion with CE and OE features m Automatic power down when deselected m CMOS for optimum speed and power m Byte power down feature m Available in Pb free 48 Ball VFBGA and 44 pin TSOP II package Functional Description The CY62137FV30 is a high performance CMOS static RAM organized as 128K words by 16 bits This device features advanced circuit design to provide ultra low active current This CY62137FV30 MoBL 2 Mbit 128K x 16 Static RAM is ideal for providing More Battery Life MoBL in portable applications such as cellular telephones The device also has an automatic power down feature that significantly reduces power consumption by 90 when addresses are not toggling Placing the device into standby mode reduces power consumption by more than 99 when deselected CE HIGH or both BLE and are HIGH The input and output pins IOo through 10 5 are placed in a high impedance state in the following conditions m De
3. 16 The internal write time of the memory is defined by the overlap of WE CE Vi and or BLE Vj All signals are ACTIVE to initiate a write and any of these signals terminate a write by going INACTIVE The data input setup and hold timing are referenced to the edge of the signal that terminates the write Document Number 001 07141 Rev F Page 5 of 12 Feedback CY62137FV30 MoBL IJ CYPRESS i Figure 5 Read Cycle 1 Address Transition Controlled 17 18 Switching Waveforms ADDRESS PREVIOUS DATA VALID DATA VALID DATA OUT Figure 6 Read Cycle 2 OE Controlled 18 19 tep lt 7 ADDRESS CE tACE Z HIGH BEBE HIGHMPEDANCE E IMPEDANCE DATA OUT lt DATA VALID tLZCE tpu Voc 50 50 SUPPLY los CURRENT 17 The device is continuously selected OE CE Vi and or BLE Vy Page 6 of 12 Notes 18 WE is HIGH for read cycle nS 19 Address valid before or similar to CE and BHE BLE transition LOW Feedback Document Number 001 07141 Rev F P7 CYPRESS CY62137FV30 MoBL PERFORM Switching Waveforms continued Figure 7 Write Cycle 1 WE Controlled 6 20 21 twc ADDRESS CD taw itu gt tsa gt tewe NSSSSN REE OXXti amp 4 Wo OE tsp 9 DX NOTE 2 XO lt iuzoE gt m Figure 8 Write Cycle 2 CE C
4. Output Disabled Active lcc L H H L H IHigh Z Output Disabled Active loc L L X L L Data In lOo lO z Write Active lcc L L X H L Data In 105 105 Write Active loc lOg lO 5 in High Z L X L H Data In lOg lO5 Write Active loc 106 105 in High Z Document Number 001 07141 Rev F Page 9 of 12 Feedback YPRESS PERFORM Ordering Information CY62137FV30 MoBL eem Ordering Code Bee Package Type a 45 CY62137FV30LL 45BVI 51 85150 48 Ball VFBGA Industrial CY62137FV30LL 45BVXI 48 Ball VFBGA Pb free CY62137FV30LL 45ZSXI 51 85087 44 Pin TSOP II Pb free 45 CY62137FV30LL 45ZSXA 51 85087 44 Pin TSOP II Pb free Automotive A 55 CY62137FV30LL 55ZSXE 51 85087 44 Pin TSOP II Pb free Automotive E Contact your local Cypress sales representative for availability of these parts Package Diagram TOP VIEW A1 CORNER 12 3 4 5 6 rTOoOmmonsoscso Dje 8 00 0 10 m 6 00 0 10 m 025 Figure 11 48 Ball VFBGA 6 x 8 x 1 Document Number 001 07141 Rev F _ 0 55 MAX m 0 10C LN SEATING PLANE 0 26 MAX 9 7 0 21 0 05 1 00 MAX BOTTOM VIEW Al CORNER gt 8 00 0 10
5. 8 20 ns tPU CE LOW to Power Up 0 0 ns tpp CE HIGH to Power Down 45 55 ns BLE BHE LOW to Data Valid 45 55 ns tLzBE BLE BHE LOW to Low Z 3 15 5 10 ns tHzBE BLE BHE HIGH to High 7 1 14 18 20 ns Write Cycle 19 twc Write Cycle Time 45 55 ns tsce CE LOW to Write End 35 40 ns taw Address Setup to Write End 35 40 ns tua Address Hold from Write End 0 0 ns tsa Address Setup to Write Start 0 0 ns tpwe WE Pulse Width 35 40 ns taw BLE BHE LOW to Write End 35 40 ns tsp Data Setup to Write End 25 25 ns tup Data Hold From Write End 0 0 ns tHzwE WE LOW to High Z 113 14 18 20 ns tLzwe WE HIGH to Low Z 113 10 10 ns Notes 11 Test conditions for all parameters other than tri state parameters assume signal transition time of 3 ns 1V ns or less timing reference levels of Vocityp 2 input pulse levels of 0 to Vccayp and output loading of the specified lo as shown in AC Test Loads and Waveforms page 4 12 AC timing parameters are subject to byte enable signals BHE or BLE not switching when chip is disabled Please see application note AN13842 for further clarification 13 At any temperature and voltage condition tuzcg is less than tj tyzpe is less than tuzog is less than tj zog and tyzwe is less than t_zwe for any device 14 tuzog tHzcE tuzpe and tyzwe transitions are measured when the outputs enter a high impedance state 15 If both byte enables are toggled together this value is 10 ns REP
6. A to 2 25 mA for f 1 MHz test condition Changed the Iccayp value from 15 mA to 13 mA and Icc max value from 20 mA to 18 mA f r f 1 MHz test condition Changed the Iccpnqyp value from 0 7 uA to 0 5 HA and IccpR max Value from 3 pA to 2 5 uA B 566724 See ECN NXR Converted from preliminary to final Changed the lcc may value from 2 25 mA to 2 5 mA for test condition f 1 MHz Changed the Isp qyp value from 0 5 pA to 1 pA Changed the 1 value from 2 5 pA to 5 pA Changed the IccpRityp value from 0 5 pA to 1 pA and Iocpr max value from 2 5 pA to 4 uA C 869500 See ECN VKN Added Automotive A and Automotive E information Updated Ordering Information Table Added footnote 13 related to tace D 901800 See ECN VKN Added footnote 9 related to lago and Iccpr Made footnote 14 applicable to AC parameters from tace E 1371124 See ECN VKN AESA Converted Automotive information from preliminary to final Changed lj min spec from 1 uA to 4 uA and Ij max spec from 1 uA to 4 uA Changed loz min spec from 1 uA to 4 uA and loz max spec from 1 uA to 4 pA F 1875374 See ECN VKN AESA Added 45BVI part in the Ordering Information table Cypress Semiconductor Corporation 2006 2008 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a
7. Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Any Source Code software and or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign United States copyright laws and international treaty provisions Cypress hereby grants to licensee a personal non exclusive non transferable license to copy use modify create derivative works of and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement Any reproduction modification translation compilation or representation of this Source Code except as specified above is prohibited without the e
8. WER DOWN gt CE H CE CIRCUIT M LEE t t t t t BE Fig Z lt lt i Cypress Semiconductor Corporation Document Number 001 07141 Rev F 198 Champion Court San Jose CA 95134 1709 408 943 2600 Revised January 2 2008 Feedback P CYPRESS PERFORM Product Portfolio CY62137FV30 MoBL Power Dissipation Vcc Range V Operating Icc mA Product Range xe cc candy f 1MHz fi H Min Typ Max Typ Max Typ Max Typ Max CY62137FV30LL Ind l Auto A 2 2V 3 0V 3 6V 45 1 6 2 5 13 18 1 5 Auto E 2 2V 3 0V 3 6V 55 2 3 15 25 1 20 Pin Configuration Figure 1 48 Ball VFBGA Pinout 2 3 Figure 2 44 Pin TSOP II 2 1 2 3 4 5 6 A4 1 44 As A302 43 O Ae 4 41 B Ao 5 40 BHE 3 CE 16 39 BLE IOo 7 38 lO45 OOOO o 055 mper IOo L19 36 1043 Vcc 111 34 Vss Vss 12 33 Voc Are Q IO 113 32 D 104 lOs 114 31 O 1049 107 116 29 lOg WE L 17 28 N Ais 119 26 D Ag 69009696909 BE ho A13 121 24 O Aq A12 122 23 NC Notes 1 Typical values are included for reference only and are not guaranteed or tested Typica
9. l values are measured at Voc TA 25 C 2 NC pins are not connected on the die 3 Pins H1 G2 and H6 in the VFBGA package are address expansion pins for 4 Mb 8 Mb 16 Mb and 32 Mb respectively Document Number 001 07141 Rev F Page 2 of 12 Feedback z Z CYPRESS PERFORM gt Maximum Ratings Exceeding the maximum ratings may impair the useful life of the device These user guidelines are not tested Storage Temperature Ambient Temperature with Power Applied Supply Voltage to Ground Potential DC Voltage Applied to Outputs in High Z state Electrical Characteristics Over the Operating Range CY62137FV30 MoBL DC Input Voltage 0 3V to 3 9V Output Current into Outputs LOW 20 mA Static Discharge Voltage gt 2001V MIL STD 883 Method 3015 ius 65 C to 150 C Latch up Current gt 200 mA 55 C to 125 C Operating Range 0 3V to 3 9V i Ambient 6 Device Range Temperature Vec T 0 3V to 3 9V CY62137FV3OLL Ind l Auto A 40 C to 85 C 2 2V to 3 6V Auto E 40 C to 125 C M m 45 ns Ind l Auto A 55 ns Au
10. onditions Min Typ Max Unit Vpn Voc for Data Retention 1 5 V locpa Data Retention Current Voc 1 5V CE 0 2V Ind l Auto A 4 uA Vin gt 0 2V or V lt 0 2V Auto E 12 tcpr 8 Chip Deselect to Data Retention Time 0 ns tg P Operation Recovery Time tnc ns Data Retention Waveform Figure 4 Data Retention Waveform 0 DATA RETENTION MODE Vpn2 1 5V Vcc min in Feedback 8 Tested initially and after any design or process changes that may affect these parameters 9 Full device operation requires linear Vgc ramp from Vpg to Voc min gt 100 us or stable at Vcc min gt 100 us Notes 2 10 BHE BLE is the AND of both BHE and BLE Deselect the chip by either disabling chip enable signals or by disabling both BHE and BLE Document Number 001 07141 Rev F lt gt CYPRESS CY62137FV30 MoBL PERFORM Switching Characteristics Over the Operating Range lt 12 45 ns Ind l Auto A 55 ns Auto E Parameter Description Unit Min Max Min Max Read Cycle tnc Read Cycle Time 45 55 ns tana Address to Data Valid 45 55 ns Data Hold From Address Change 10 10 ns tace CE LOW to Data Valid 45 55 ns OE LOW to Data Valid 22 25 ns tLZ0E OE LOW to Low Z 3 5 5 ns tHZ0E OE HIGH to High 2 1 14 18 20 ns lizcE CE LOW to Low Z 73 10 10 ns tuzce CE HIGH to High 2 113 14 1
11. ontrolled 16 20 21 CE s ZC i z lt iPwE l BHERLE SSX os 1 Z ema A mmo EEOAE s LO lt thzoe gt m Notes 20 Data IO is high impedance if OE Vi _ 21 If CE goes HIGH simultaneously with WE Vip the output remains in a high impedance state 22 During this period the IOs are in output state Do not apply input signals Document Number 001 07141 Rev F Page 7 of 12 Feedback CYPRESS CY62137FV30 MoBL PERFORM i Switching Waveforms continued Figure 9 Write Cycle 3 WE Controlled OE LOW 21 OK Osx 24 tw tha gt lt WE lt NAS tHD lt XXXK C 207 KKK 7222 tuzwe tlizwE gt Figure 10 Write Cycle 4 BHE BLE Controlled OE Low 21 twc ADDRESS CE BHE BLE WE DATA IO Document Number 001 07141 Rev F Page 8 of 12 Feedback wi M CYPRESS PERFORM CY62137FV30 MoBL Truth Table CE WE OE BHE BLE Inputs or Outputs Mode Power H X X X X HighZ Deselect or Power Down Standby lag X X X H H High Z Deselect or Power Down Standby lag L H L L L Data Out lOg 1O 5 Read Active lec L H L H L Data Out IOg 1O7 Read Active loc lOg lO4s in High Z L H L L H Data Out lOg 1O 5 Read Active loc 100 105 in High Z L H H L L High Z Output Disabled Active lcc L H H H L High Z
12. or pulse durations less than 20 ns 5 0 75 for pulse durations less than 20 ns 6 Full device AC operation assumes a minimum of 100 us ramp time from 0 to Vcc min and 200 us wait time after Voc stabilization 7 Only chip enable CE and byte enables BHE and BLE are tied to CMOS levels to meet the 882 lccpn Specification Other inputs can be left floating Document Number 001 07141 Rev F Page 3 of 12 Feedback Page 4 of 12 CYPRESS CY62137FV30 MoBL PERFORM Thermal Resistance Tested initially and after any design or process changes that may affect these parameters Parameter Description Test Conditions VFBGA TSOP II Unit OJA Thermal Resistance Still air soldered on a 3 x 4 5 inch 75 77 C W Junction to Ambient two layer printed circuit board Oje Thermal Resistance 10 13 C W Junction to Case AC Test Loads and Waveforms Figure 3 AC Test Loads and Waveform R1 ALL INPUT PULSES Voc Vcc 90 OUTPUT 10 GND 30 pF R2 Rise Time 1 gt Fall Time 1 V ns INCLUDING Equivalent to TH VENIN EQUIVALENT RTH OUTPUT o rO V Parameters 2 5V 2 2V to 2 7V 3 0V 2 7V to 3 6V Unit R1 16667 1103 Q R2 15385 1554 Q 8000 645 Q VIH 1 20 1 75 V Data Retention Characteristics Over the Operating Range Parameter Description C
13. selected CE HIGH m Outputs are disabled OE HIGH m Both Byte High Enable and Byte Low Enable are disabled BHE BLE HIGH m Write operation is active CE LOW and WE LOW Write to the device by taking Chip Enable CE and Write Enable WE inputs LOW If Byte Low Enable BLE is LOW then data from pins IOo through 105 is written into the location specified on the address pins Ag through Ag If Byte High Enable is LOW then data from IO pins IOg through 1045 is written into the location specified on the address pins Ag through A46 Read from the device by taking Chip Enable CE and Output Enable OE LOW while forcing the Write Enable WE HIGH If Byte Low Enable BLE is LOW then data from the memory location specified by the address pins appear on IOo to 105 If Byte High Enable BHE is LOW then data from memory appears on 0 to 10 5 See the Truth Table on page 9 for a complete description of read and write modes For best practice recommendations refer to the Cypress application note AN1064 SRAM System Guidelines Logic Block Diagram DATA IN DRIVERS 2 q4 A10 i 9 5 A Q 0 Ag 128K x 16 2 A a s RAM Array mae L 4 5 0 As o HD 105 1045 Ap UT COLUMN DECODER aes PO
14. to E Parameter Description Test Conditions 1 1 Unit Min Typ Max Min Typ Max Vou Output HIGH Voltage 2 2 lt Vec lt 2 7 0 1 mA 2 0 2 0 V 2 7 lt Vcc lt 3 6 1 0 mA 2 4 2 4 V VoL Output LOW Voltage 2 2 lt Vec lt 2 7 lo 0 1 mA 0 4 0 4 V 2 7 lt Vcc lt 3 6 lot 2 1mA 0 4 0 4 V ViH Input HIGH Voltage 2 2 lt Vcc lt 2 7 1 8 Voc 0 3 1 8 Vcc 0 3 V 2 7 lt Vcc lt 3 6 2 2 Vec 0 3 2 2 Voc 0 3 V Vit Input LOW Voltage 2 2 lt Vcc lt 2 7 0 3 06 0 3 0 6 V 2 7 lt Vcc lt 3 6 0 3 08 0 3 0 8 V lix Input Leakage Current GND lt VI lt Vcc 1 1 4 4 pA loz Output Leakage GND lt Vo lt Vcc Output disabled 1 1 4 4 HA Current lec Voc Operating Supply f Trax 1 Voc Voccmax 13 18 15 25 mA Current lout 0 mA f 1 MHz GMOS levels 1 6 2 5 3 legi Automatic CE Power CE gt Voc 0 2V 1 5 1 20 pA Down Current CMOS VIN gt Voc 0 2V VIN lt 0 2V Inputs f fmax address and data only f 0 OE WE and BLE 3 60V 582 1 Automatic CE Power gt Vcc 0 2V 1 5 1 20 pA Down Current CMOS gt Vcc 0 2V or Vin lt 0 2V Inputs f 0 Voc 3 60V Capacitance Tested initially and after any design or process changes that may affect these parameters Parameter Description Test Conditions Max Unit Cin Input Capacitance Ta 25 f 1 MHz 10 pF Cour Output Capacitance Vecityp 10 pF Notes 4 Vit min 2 0V f
15. xpress written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Cypress reserves the right to make changes without further notice to the materials described herein Cypress does not assume any liability arising out of the application or use of any product or circuit described herein Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress product in a life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Use may be limited by and subject to the applicable Cypress software license agreement Document Number 001 07141 Rev F Revised January 2 2008 Page 12 of 12 is a registered trademark and More Battery Life is a trademark of Cypress Semiconductor All product and company names mentioned in this document are the trademarks of their respective holders Feedback
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