Cypress CY25822-2 User's Manual
Contents
1. a E cd ee E Ee a ee CYPRESS Features e 3 3V operation 48 and 66 MHz frequency support Selectable slew rate conirol 350 pS jitter CK SSC Spread Spectrum Clock Generator I2 C programmability CY25822 2 500 uA power down current Spread Spectrum for best electromagnetic interference EMI reduction e 8 pin SOIC package Block Diagram VDD REFOUT Clock Input CLKOUT 5 Phase Post Tr Divider Dividers SSGG Quiput Modulating SDATA C Waveform scLock j pele Feedback PWRDWN Divider Pin Configuration CLKIN 8 PWRDWN VDD 7 SCLOCK CY25822 2 GND 6 SDATA CLKOUT 5 REFOUT 150KQ Pull up Cypress Semiconductor Corporation Document 38 07531 Rev 3901 North First Street San Jose CA 95134 408 943 2600 Revised March 18 2003 Feedback io CY25822 2 S57 Cypress Pin Description Pin No Pin Name Pin Type Pin Description 1 CLKIN Input 48 MHz or 66 MHz Clock Input 2 VDD Power Power Supply for PLL and Outputs 3 GND Ground Ground for Outputs 4 CLKOUT Output 48 MHz or 66 MHz Spread Spectrum Clock Output 5 REFOUT Output Non spread Spectrum Reference Clock Output 6 SDATA I O I C compatible SDATA 7 SCLOCK Input I C compatible SCLOCK 8 PWRDWN Output LVTTL Input for PowerDown Active Low Serial Data Interface To enhance t2. Byte offset for byte read or byte write operation For block read or block write operations these bits should be 0000000 Table 2 Block Read and Block Write Protocol Block Write Protocol Block Read Protocol Bit Description Bit Description 1 Start 1 Start 2 8 Slave address 7 bits 2 8 Slave address 7 bits 9 Write 0 9 Write 0 10 Acknowledge from slave 10 Acknowledge from slave 11 18 Command Code 8 bits 00000000 stands for block operation Command Code 8 bits 00000000 stands for block operation 11 18 19 Acknowledge from slave 19 Acknowledge from slave 20 27 Byte Count 8 bits 20 Repeat start 28 Acknowledge from slave 21 27 Slave address 7 bits 29 36 Data byte 1 8 bits 28 Read 1 37 Acknowledge from slave 29 Acknowledge from slave 38 45 Data byte 2 8 bits 30 37 Byte count from slave 8 bits 46 Acknowledge from slave 38 Acknowledge ee i 39 46 Data byte from slave 8 bits Data Byte N 1 8 bits 47 Acknowledge Acknowledge from slave 48 55 Data byte from slave 8 bits Document 38 07531 Rev Page 2 of 9 Feedback __ S38 CYPRESS SS FI Ter CY25822 2 Table 2 Block Read and Block Write Protocol continued Data Byte N 8 bits 56 Acknowledge Acknowledge from slave Data bytes from slave Acknowledge Stop Data byte N from slave 8 bits Not Acknowl
3. Clarification The PWRDWN Power down pin is used to shut off ALL clocks prior to shutting off power to the device PWRDWNi is an asynchronous active LOW input This signal is synchro nized internally to the device powering down the clock synthe sizer PWRDWN is an asynchronous function for powering up the system When PWRDWN4 is low all clocks are driven to a LOW value and held there and the VCO and PLLs are also powered down All clocks are shut down in a synchronous manner so has not to cause glitches while transitioning to the low stopped state When PWRDWN is deasserted the clocks should remain stopped until the VCO is stable and within specification tstap_e A stopped clock is either tri stated or driven low depending on the state of the tri state enable 1 C register bit CY25822 clocks that are stopped in the driven state are driven low The CLKIN input must be on and within specified operating parameters before PWRDWN z is asserted and it must remain in this state while PWRDWN is asserted Page 4 of 9 Laing A CYPRESS CY25822 2 f PWRDWN CLKOUT REFOUT Figure 1 Power down Assertion l l PD oms gt CLKOUT FLIE LILI I REFOUT rFLJ LI LI Figure 2 Power down Deassertion CLKOUT and REFOUT Enable Clarification The CLKOUT enable and REFOUT enable IC register bits are used to shot off the CLKOUT and REFOUT clocks individually The VCO and cr
4. SOIC 8 pin SOIC Tape and Reel Document 38 07531 Rev Page 7 of 9 Feedback BaF ocs vase Package Diagram 8 lead 150 Mil SOIC S8 L DIRERSIONS IM JMCHESIMM BIN Max i Pil 1B S OPTLOMAL T EEEN POUND ON SINGLE LEAD PAME ik REL TANGAJLAR ON NATRIE LEAD FAME d a heer 3 g ere monks i mil P Ta Ea ETE RETE Pi f F ee jitia a UO Le Pa 51 85066 B Purchase of C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips C Patent Rights to use these components in an I C system provided that the system conforms to the I C Standard Specification as defined by Philips All product and company names mentioned in this document are trademarks of their respective holders Document 38 07531 Rev Page 8 of 9 Cypress Semiconductor Corporation 2003 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product Nor does it convey or imply any license under patent or other rights Cypress Semiconductor does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress Semiconductor products in life support
5. 07531 Rev Page 6 of 9 Feedback i DP rro CY25822 2 SA CYPRESS Table 7 AC Parameters T4 0 C to 70 C Vpp 3 3V 5 continued Parameter Description Conditions Min Max Unit Notes tFALLL1 Falling Edge Rate Measured from 2 4V to 0 4V 1 33 4 0 V ns_ Low Buffer Strength REFOUT and CLOCKOUT Refer to I2C Control tRISEH2 Rise Time Measured from 0 4V to 2 4V 0 4 1 0 ns High Buffer Strength REFOUT and CLOCKOUT Refer to I C Control tFALLH2 Fall Time Measured from 2 4V to 0 4V 0 4 1 0 ns High Buffer Strength REFOUT and CLOCKOUT Refer to I C Control tRISEL2 Rise Time Measured from 0 4V to 2 4V 0 5 1 5 ns Low Buffer Strength REFOUT and CLOCKOUT Refer to I C Control tFALLL2 Fall Time Measured from 2 4V to 0 4V 0 5 1 5 ns Low Buffer Strength REFOUT and CLOCKOUT Refer to I C Control Teyc1 Cycle to Cycle Jitter REFOUT 500 ps SSCG is ON Teyce Cycle to Cycle Jitter CLOCKOUT 250 ps SSCG is ON LTJ 10uS Period Jitter Applies to REFOUT at all 2 0 ns 100KHz Frequency Mod times and CLOCKOUT when ulation Amplitude SSCG is Off tsTART Start up time From VDD 2 0 V 3 0 ms All outputs disabled Table 8 Signal Loading Table Clock Name Max Load pF CLKOUT REFOUT 15 Ordering Information Part Number CY25822SC 2 CY25822SC 2T Product Flow Commercial 0 C to 70 C Commercial 0 C to 70 C Package Type 8 pin
6. edge Stop Table 3 Byte Read and Byte Write Protocol Byte Write Protocol Byte Read Protocol Bit Description Bit Description 1 Start 1 Start 2 8 Slave address 7 bits 2 8 Slave address 7 bits 9 Write 0 9 Write 0 10 Acknowledge from slave 10 Acknowledge from slave 11 18 Command Code 8 bits 11 18 Command Code 8 bits 1Xxxxxxx stands for byte operation bits 6 0 of 1Xxxxxxx stands for byte operation bits 6 0 the command code represents the offset of the of the command code represents the offset of byte to be accessed the byte to be accessed 19 Acknowledge from slave 19 Acknowledge from slave 20 27 Data byte from master 8 bits 20 Repeat start 28 Acknowledge from slave 21 27 Slave address 7 bits 29 Stop 28 Read 1 29 Acknowledge from slave 30 37 Data byte from slave 8 bits 38 Not Acknowledge 39 Stop Byte 0 Control Register Bit Pup Pin Name Pin Description 7 1 4 SSO 6 0 4 SS1 5 0 4 SS2 4 0 4 SS3 3 1 Not Applicable Reserved must be written as 1 2 1 4 5 CLKOUT Power down three state enable REFOUT 0 three state outputs 1 drive outputs low Applies only in Power Down State 1 1 4 CLKOUT Spread Spectrum enable 0 spread off 1 spread on 0 0 Not Applicable No Pins Table 4 Spread Spectrum Select SS3 SS2 SS1
7. he flexibility and function of the clock synthesizer a two signal serial interface is provided Through the Serial Data Interface various device functions such as individual clock output buffers etc can be individually enabled or disabled The registers associated with the Serial Data Interface initializes to their default setting upon power up and therefore use of this interface is optional Clock device register changes are normally made upon system initialization if any are required The interface can also be used during system operation for power management functions Table 1 Command Code Definition Data Protocol The clock driver serial protocol accepts byte write byte read block write and block read operation from the controller For block write read operation the bytes must be accessed in sequential order from lowest to highest byte most significant bit first with the ability to stop after any complete byte has been transferred For byte write and byte read operations the system controller can access individual indexed bytes The offset of the indexed byte is encoded in the command code as described in Table 1 The block write and block read protocol is outlined in Table 2 while Table 3 outlines the corresponding byte write and byte read protocol The slave receiver address is 11010100 D4h Bit Description 7 0 Block read or block write operation 1 Byte read or byte write operation 6 0 a
8. sso Spread Mode Spread Amount 0 0 0 0 Down 0 8 0 0 0 1 Down 1 0 0 0 1 0 Down 1 25 0 0 1 1 Down 1 5 0 1 0 0 Down 1 75 Document 38 07531 Rev Page 3 of 9 Feedback CY25822 2 a CYPRESS Table 4 Spread Spectrum Select continued Ss3 SS2 SS1 SS0 Spread Mode Spread Amount 0 1 0 1 Down 2 0 0 1 1 0 Down 2 5 0 1 1 1 Down 3 0 1 0 0 0 Center 0 3 1 0 0 1 Center 0 4 1 0 1 0 Center 0 5 1 0 1 1 Center 0 6 1 1 0 0 Center 0 8 1 1 0 1 Center 1 0 1 1 1 0 Center 1 25 1 1 1 1 Center 1 5 Byte 1 Control Register Bit Pup Pin Name Pin Description 7 1 5 REFEN REFOUT enable 0 disabled 1 enabled 6 1 5 REFSLEW REFOUT edge rate control 0 slow 1 nominal 5 0 Not Applicable Reserved 4 0 Not Applicable Reserved 3 1 4 CLKSLEW CLKOUT edge rate control 0 slow 1 nominal 2 1 4 CLKEN CLKOUT enable 0 disabled 1 enabled 0 Not Applicable Reserved 0 0 Not Applicable Reserved Bytes 2 through 5 Reserved Registers Byte 6 Vendor Revision ID Register Bit Pup Pin Name Pin Description 0 Revision ID Bit 3 Revision ID Bit 2 Revision ID Bit 1 Revision ID Bit 0 Vendor ID Bit 3 Vendor ID Bit 2 Vendor ID Bit 1 O N WS A MH m N oO oO O CO CO Vendor ID Bit 0 Document 38 07531 Rev PWRDWN Power down
9. systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges Feedback Laing SE Xl ppree CY25822 2 F CYPRESS Document History Page Document Title CY25822 2 CK SSC Spread Spectrum Clock Generator Document Number 38 07531 Issue Orig of REV ECN NO Date Change Description of Change ae 124462 03 19 03 RGL New Data Sheet Document 38 07531 Rev Page 9 of 9 Feedback
10. ut High Voltage lon 4 mA 2 4 V Single edge is required to be monotonic when transi tioning through this region VoL Output Low Voltage lop 4 mA 0 4 V Single edge is required to be monotonic when transi tioning through this region Cin Input Pin Capacitance 5 pF Cout Output Pin Capacitance 6 pF Lin Pin Inductance 7 nH Ta Ambient Temperature 0 70 C No air flow Ipp14 Supply Current 66 MHz 50 mA Ipp2 Supply Current 48 MHz 40 mA lpp Power Down Supply Current 500 uA Table 7 AC Parameters T4 0 C to 70 C Vpp 3 3V 5 Parameter Description Conditions Min Max Unit Notes THIGH CLK High Time 48MHz Measured 2 4V 9 45 10 95 ns Specification applies to 48MHz output mode tLow CLK Low Time 48MHz Measured 0 4V 8 50 10 10 ns Specification applies to 48MHz output mode tHIGH CLK High Time 66MHz Measured 2 4V 6 85 7 90 ns Specification applies to 66 7MHz output mode tLow CLK Low Time 66MHz Measured 0 4V 5 95 6 95 ns Specification applies to 66 7MHz output mode tRISEH1 Rising Edge Rate Measured from 0 4V to 2 4V 2 0 5 0 V ns High Buffer Strength REFOUT and CLOCKOUT Refer to I2C Control FALLH1 Falling Edge Rate Measured from 2 4V to 0 4V 2 0 5 0 V ns High Buffer Strength REFOUT and CLOCKOUT Refer to I C Control tRISEL1 Rising Edge Rate Measured from 0 4V to 2 4V 1 33 4 0 V ns Low Buffer Strength REFOUT and CLOCKOUT Refer to I C Control Document 38
11. ystal oscillator must remain on A shutdown clock is driven low ALL clocks need to be stopped in a predictable manner All clocks need to be shutdown without any glitches or other abnormal behavior while transitioning to a stopped state Similarly when CLKOUT or REFOUT is enabled the clock must start in a predictable manner without any glitches or abnormal behavior Document 38 07531 Rev Page 5 of 9 Feedback 2 CYPRESS CY25822 2 Table 5 Absolute Maximum Ratings Parameter Description Condition Min Max Unit Vpp Core Supply Voltage 0 5 4 6 V VDD A Analog Supply Voltage 0 5 4 6 V VIN Input Voltage Relative to V ss 0 5 Vpp 0 5 VDC Ts Temperature Storage Non Functional 65 150 C Ta Temperature Operating Ambient Functional 0 70 C Ty Temperature Junction Functional 150 C ESDuem ESD Protection Human Body Model MIL STD 883 Method 3015 2000 i Volts UL 94 Flammability Rating 1 8 in V 0 MSL Moisture Sensitivity Level 1 Table 6 DC Parameters T4 0 C to 70 Vpp 3 3V 5 Parameter Description Condition Min Max Unit Notes Vpp Supply Voltage 3 135 3 465 V Vpp 3 3 5 Vin Input High Voltage a 2 0 Vpp 0 3 V Vit Input Low Voltage Vss 0 3 0 8 V liL1 Input Leakage Current SCLOCK 25 25 uA or SDATA lite Input Leakage Current PWRDWN 75 15 uA VoH Outp
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