Cypress CY14B104LA User's Manual
Contents
1. E oooodo A 8 900000 4 e 3 p 4 jp E 19 E F 2 R G 6 H 1 1 00 009 A A 1875 B 4 6 00 0 10 0 75 3 75 A B r 6 00 0 10 y c 015 4 S 8 5 X 5 4 X X XJ SEATING PLANE T 51 85128 D Document 001 49918 Rev A Page 21 of 23 Feedback PERFORM Package Diagrams continued Z PRELIMINARY CY14B104LA CY14B104NA Figure 18 54 TSOP II 51 85160 22 313 0 8782 88517 0 886 LLEECLELELELELELELELELELELELELELELELELELELELELELELLLL 0180 lt 0 0047 0 810 19 0083 DETAIL N PIN 1 PE LY 4 IE 0058 0 3965 10 960 0 4049 11 735 40 469 11938 0 4709 1795 0468 11938 0 4705 15729 28 54 0 300 0 0122 9 800 BSC 020000165 0 0315 S 292 003742 105 00413 O MIN DIMENSION IN MM MIN MAX R 012 0 005 MINS R 012 0 0055 05 0 0105 025 GAUGE PLANE Y H 120 0 0478M X5 22 313 0878 22 317 0 882. Cs Gan ape Cs An Cay Ke Cec Ceo Gass Vous Ars Cay ss E Ne Aa As NE Car 693 3 cs e 69 e 8 808062 89699 8 0982695 Figure 2 Pin Diagram 44 Pin TSOP II x8 16 6 Neu 44 HSB 44L Ar NC NC AL 2 43L Ais 421 4217 Ais AL 4 41411 4 41L OE 5 401 5 400 06 3917 Ais J BLE 38 1 Ais 097 38 00 5 CEL 8 7 1 37 DQ 19 361100 9 44 TSOP II DQ 10 35 DQg DQsL 110 x16 35 DQ42 11 34L Vss VocL 11 34L Vss vssL 12 Top View Vec Vss 12 Top View po s Notto scale 55 Notto scale 33H pa 14 3110 DQ DQ L 114 31 I1 DQ4o WEL 15 30 006 15 30171 pos A 16 29 Au DQ L 16 29 As L 17 28 L1 A13 WEL 17 281 Vcap A L 18 27 As 27 Au 19 51 As 19 26 1 Aig Ag 120 25 Aio 20 25 1 Ayo NC 21 24 NC 21 241 NC C 22 23 NC Ag 22 23 Notes 4 Address expansion for 8 Mbit NC pin not connected to die 5 Address expansion for 16 Mbit NC pin not connected to die 6 HSB is not available in 44 TSOP x16 package Document 001 49918 Rev A Page 2 of 23 Feedback PRELIMINARY CYPRESS
3. Page 19 of 23 Feedback E PRELIMINARY CYPRESS CY14B104LA CY14B104NA PERFORM Package Diagrams Figure 16 44 Pin TSOP II 51 85087 DIMENSION IN MM INCH MAX MIN 10 262 0 404 10 058 0 396 REN K XA 80 HHHEHHEBHHBBHEBHHEHEBHEN BOTTOM VIEW TOP VIEW 10 262 0 404 0 400 0 016 10 058 0 396 0 800 BSC 0 300 0 012 0 0315 0 012 BASE PLANE Dum 0 210 0 0083 1 7 9120007 0 10 004 f 185170729 4 0 597 0 0235 18 313 0 721 SEATING 0 406 0 0160 5 8 B PLANE es es oo 51 85087 A Page 20 of 23 Document 001 49918 Rev A Feedback PRELIMINARY CYPRESS CY14B104LA CY14B104NA PERFORM Package Diagrams continued Figure 17 48 Ball FBGA 6 mm x 10 mm x 1 2 mm 51 85128 TOP VIEW BOTTOM VIEW 1 CORNER p 90 05 MC V A1 CORNER 0 30 0 05 48X 12 3 4 5 6 6 5 4 3
4. 2 mA 2 4 V VoL Output LOW Voltage lour 4 mA 0 4 V Vcapl Storage Capacitor Between pin and Vgg 5V Rated 61 180 uF Notes 9 Typical conditions for the active current shown on the DC Electrical characteristics are average values at 25 C room temperature and Vcc Not 100 tested 10 The HSB pin has lour 2 uA for Voy of 2 4V when both active HIGH and LOW drivers are disabled When they are enabled standard Voy and Vo are valid This parameter is characterized but not tested 11 Vcap Storage capacitor nominal value is 68 uF Document 001 49918 Rev A Page 8 of 23 Feedback PRELIMINARY EP CYPRESS CY14B104LA CY14B104NA PERFORM Data Retention and Endurance Parameter Description Min Unit DATAR Data Retention 20 Years NVc Nonvolatile STORE Operation 200 K Capacitance In the following table the capacitance parameters are listed 21 Description Test Conditions Max Unit Cin Input Capacitance TA 25 C f 1 MHz 7 pF Cour Output Capacitance Voc 010 3 0V 7 pF Thermal Resistance In the following table the thermal resistance parameters are listed 112 Parameter Description Test Conditions 48 FBGA 44 TSOP II 54 TSOP II Unit Oja Thermal Resistance Test conditions follow standard test methods 28 82 31 11 30 73 C W Junction to Ambient procedures
5. 001 49918 Rev A PRELIMINARY a J CYPRESS CY14B104LA CY14B104NA PERFORM AutoStore Power Up RECALL are 20 ns 25 ns 45 ns Parameters Description Min Max Min Max Min Max Unit tHRECALL 197 Power Up RECALL Duration 20 20 20 ms tsTORE STORE Cycle Duration 8 8 8 ms tpELAY 21 Time Allowed to Complete SRAM Cycle 20 25 25 ns VswitcH Low Voltage Trigger Level 2 65 2 65 2 65 V tvccRISE VCC Rise Time 150 150 150 us Vupis HSB Output Driver Disable Voltage 1 9 1 9 1 9 V ti zusp HSB To Output Active Time 5 5 5 us HSB High Active Time 500 500 500 ns Switching Waveforms Figure 11 AutoStore or Power Up 22 Vswreu yA ee hee Vvccrise Note tsrdRE STORE Note HSB OUT _ t zHsB tousp 7 4 Autostore gt lt t DELAY POWER UP oe gt PI o NN tuRECALL 56 Read amp Write Inhibited RWI md POWER UP Read amp Write BROWN POWER UP Read amp Write POWER RECALL OUT RECALL DOWN Autostore Autostore Notes 19 turecaLt Starts from the time Vcc rises above 20 If an SRAM write has not taken place since the last nonvolatile cycle no AutoStore or Hardware Store takes place 21 On a Hardware
6. O O ns tpp 4 tps Chip Disable to Power Standby 20 25 45 ns Byte Enable to Data Valid 10 12 20 ns 2 Byte Enable to Output Active 0 0 0 ns tian Byte Disable to Output Inactive 8 10 15 ns SRAM Write Cycle twc twc Write Cycle Time 20 25 45 ns tpwe twp Write Pulse Width 15 20 30 ns isce tew Chip Enable To End of Write 15 20 30 ns tsp tow Data Setup to End of Write 8 10 15 ns tup Data Hold After End of Write 0 0 0 ns taw taw Address Setup to End of Write 15 20 30 ns tsa tas Address Setup to Start of Write 0 0 0 ns twn Address Hold After End of Write 0 0 0 ns e IS Write Enable to Output Disable 8 10 15 ns 7 15 tow Output Active after End of Write 3 3 3 ns taw Byte Enable to End of Write 15 20 30 ns Switching Waveforms Figure 6 SRAM Read Cycle 1 Address Controlled 3 14 17 tre Address Address Valid Previous Data Valid Output Data Valid Data Output Notes 13 WE must be HIGH during SRAM read cycles 14 Device is continuously selected with CE OE BLE LOW 15 Measured 200 mV from steady state output voltage 16 If WE is LOW when CE goes LOW the outputs remain in the high impedance state 17 HSB must remain HIGH during read and write cycles Document 001 49918 Rev A Page 10 of 23 Feedback PRELIMINARY CY14B104LA CY14B104NA CYPRESS PERFORM Figure 7 SRAM Read Cycle 2 CE and OE Controlled
7. 13 17 Address Address Valid xX t lt HZCE CE tuzoe OE BHE BLE Data Output High Impedance Output Data Valid Active Standby lec Figure 8 SRAM Write Cycle 1 WE Controlled 16 17 18 twe Address Valid Address X tsce tua Y gt BHE BLE A t lt AW gt towe tsa tsp Input Data Valid WE Data Input 8 High Impedance 4 Previous Data Data Output Page 11 of 23 Feedback Note 18 CE or WE must be gt Vj during address transitions Document 001 49918 Rev A CY14B104LA CY14B104NA PRELIMINARY CYPRESS PERFORM Figure 9 SRAM Write Cycle 2 CE Controlled 16 17 18 twe lt Address Valid tha Address tsa A tew BHE BLE N gt 4 tewe gt WE t tup b 59 Input Data Valid High Impedance Data Input Data Output Figure 10 SRAM Write Cycle 3 and BLE Controlled 16 17 18 twe Address Valid Address c Y 4 tsa tow tha BHE BLE t Aw gt towe t t SD HD Input Data Valid High Impedance Data Input Data Output Page 12 of 23 Feedback Document
8. M CY14B104LA CY14B104NA 4 Mbit 512K x 8 256K x 16 nvSRAM PRELIMINARY CYPRESS PERFORM Features 20 ns 25 ns 45 ns access times m Internally organized as 512K x 8 CY14B104LA or 256K x 16 CY14B104NA m Hands off automatic STORE on power down with only a small capacitor m STORE to QuantumTrap nonvolatile elements initiated by software device pin or AutoStore on power down m RECALL to SRAM initiated by software or power up m Infinite Read Write and Recall cycles m 200 000 STORE cycles to QuantumTrap m 20 year data retention m Single 3V 20 10 operation m Commercial and industrial temperatures m 48 ball FBGA and 44 54 TSOP II packages m Pb free and RoHS compliance Functional Description The Cypress CY14B104LA CY14B104NA is a fast static RAM with a nonvolatile element in each memory cell The memory is organized as 512K bytes of 8 bits each or 256K words of 16 bits each The embedded nonvolatile elements incorporate QuantumTrap technology producing the world s most reliable nonvolatile memory The SRAM provides infinite read and write cycles while independent nonvolatile data resides in the highly reliable QuantumTrap cell Data transfers from the SRAM to the nonvolatile elements the STORE operation takes place automatically at power down On power up data is restored to the SRAM the RECALL operation from the nonvolatile memory Both the STORE and RECALL oper
9. CY14B104LA BA25XI 51 85128 48 ball FBGA CY14B104NA ZS25XCT 51 85087 44 pin TSOP II Commercial CY14B104NA ZS25XC 51 85087 44 pin TSOP Il CY14B104NA ZS25XIT 51 85087 44 pin TSOP II Industrial CY14B104NA ZS25XI 51 85087 44 pin TSOP Il CY14B104NA BA25XCT 51 85128 48 ball FBGA Commercial CY14B104NA BA25XC 51 85128 48 ball FBGA CY14B104NA BA25XIT 51 85128 48 ball FBGA Industrial CY14B104NA BA25XI 51 85128 48 ball FBGA CY14B104NA BA25I 51 85128 48 ball FBGA CY14B104NA ZSP25XCT 51 85160 54 pin TSOP II Commercial CY14B104NA ZSP25XC 51 85160 54 TSOP II CY14B104NA ZSP25XIT 51 85160 54 pin TSOP II Industrial CY14B104NA ZSP25XI 51 85160 54 pin TSOP Il Document 001 49918 Rev A Page 17 of 23 Feedback PRELIMINARY CY14B104LA CY14B104NA Ordering Code Package Type Ed 45 CY14B104LA ZS45XCT 51 85087 44 pin TSOP II Commercial CY14B104LA ZS45XC 51 85087 44 pin TSOP II CY14B104LA ZSA5XIT 51 85087 44 pin TSOP II Industrial CY14B104LA ZSA5XI 51 85087 44 pin TSOP II CY14B104LA BA45XCT 51 85128 48 ball FBGA Commercial CY14B104LA BA45XC 51 85128 48 ball FBGA CY14B104LA BA45XIT 51 85128 48 ball FBGA Industrial CY14B104LA BA45xI 51 85128 48 ball FBGA CY14B104NA ZS45XCT 51 85087 44 TSOP II Commercial CY14B104NA ZS45XC 51 85087
10. CY14B104NA poen Ordering Code borum Package Type Ed 20 CY14B104LA ZS20XCT 51 85087 44 pin TSOP II Commercial CY14B104LA ZS20XC 51 85087 44 pin TSOP II CY14B104LA ZS20XIT 51 85087 44 pin TSOP II Industrial CY14B104LA ZS20XI 51 85087 44 pin TSOP II CY14B104LA BA20XCT 51 85128 48 ball FBGA Commercial CY14B104LA BA20XC 51 85128 48 ball FBGA CY14B104LA BA20XIT 51 85128 48 ball FBGA Industrial CY14B104LA BA20XI 51 85128 48 ball FBGA CY14B104NA ZS20XCT 51 85087 44 pin TSOP II Commercial CY14B104NA ZS20XC 51 85087 44 pin TSOP Il CY14B104NA ZS20XIT 51 85087 44 pin TSOP II Industrial CY14B104NA ZS20XI 51 85087 44 pin TSOP Il CY14B104NA BA20XCT 51 85128 48 ball FBGA Commercial CY14B104NA BA20XC 51 85128 48 ball FBGA CY14B104NA BA20XIT 51 85128 48 ball FBGA Industrial CY14B104NA BA20XI 51 85128 48 ball FBGA CY14B104NA ZSP20XCT 51 85160 54 pin TSOP II Commercial CY14B104NA ZSP20XC 51 85160 54 pin TSOP Il CY14B104NA ZSP20XIT 51 85160 54 pin TSOP II Industrial CY14B104NA ZSP20XI 51 85160 54 pin TSOP II 25 CY14B104LA ZS25XCT 51 85087 44 pin TSOP II Commercial CY14B104LA ZS25XC 51 85087 44 pin TSOP Il CY14B104LA ZS25XIT 51 85087 44 pin TSOP II Industrial CY14B104LA ZS25XI 51 85087 44 pin TSOP II CY14B104LA BA25XCT 51 85128 48 ball FBGA Commercial CY14B104LA BA25XC 51 85128 48 ball FBGA CY14B104LA BA25XIT 51 85128 48 ball FBGA Industrial
11. cycles requested after HSB goes LOW are inhibited until HSB returns HIGH In case the write latch is not set HSB is not driven LOW by the CY14B104LA CY14B104NA But any SRAM read and write cycles are inhibited until HSB is returned HIGH by MPU or other external source During any STORE operation regardless of how it is initiated the CY14B104LA CY14B104NA continues to drive the HSB pin LOW releasing it only when the STORE is complete When the STORE operation is completed the CY14B104LA CY14B104NA Page 4 of 23 Feedback PRELIMINARY 2 remains disabled until the HSB pin returns HIGH Leave the HSB unconnected if it is not used Hardware RECALL Power Up During power up or after any low power condition lt VswircH an internal RECALL request is latched When Vcc again exceeds the sense voltage of Vswircu a RECALL cycle is automatically initiated and takes to complete During this time HSB is driven LOW by the HSB driver Software STORE Transfer data from the SRAM to the nonvolatile memory with a software address sequence The CY14B104LA CY14B104NA software STORE cycle is initiated by executing sequential CE controlled read cycles from six specific address locations in exact order During the STORE cycle an erase of the previous nonvolatile data is first performed followed by a program of the nonvolatile elements After a STORE cycle is initiated further input and output are disabled
12. 0xB1C7 Valid READ 3 Read Address 0x83E0 Valid READ 4 Read Address 0x7C1F Valid READ 5 Read Address 0x703F Valid READ 6 Read Address 0x4C63 Initiate RECALL Cycle Internally RECALL is a two step procedure First the SRAM data is cleared then the nonvolatile information is transferred into the SRAM cells After the tnagcALL cycle time the SRAM is again ready for read and write operations The RECALL operation does not alter the data in the nonvolatile elements CE WE OE BLE A15 AQ Mode Power H X X X Not Selected Output High Z Standby L H L X Read SRAM Output Data Active L L X X Write SRAM Input Data Active L H L 0 4 38 Read SRAM Output Data Activel8 0xB1C7 Read SRAM Output Data 0x83E0 Read SRAM Output Data 0x7C1F Read SRAM Output Data 0x703F Read SRAM Output Data 0x8B45 AutoStore Output Data Disable Notes 7 While there 19 address lines on the CY14B104LA 18 address lines on the 14 104 only the 13 address lines A44 are used to control software modes Rest of the address lines are don t care 8 The six consecutive address locations must be in the order listed WE must be HIGH during all six cycles to enable a nonvolatile cycle Document 001 49918 Rev A Page 5 of 23 Feedback Table 1 Mode Selection continued PRELIMINARY CY14B104LA CY14B104NA CE WE OE BLE A45 Aol Mo
13. 44 pin TSOP Il CY14B104NA ZS45XIT 51 85087 44 pin TSOP II Industrial CY14B104NA ZSA5XI 51 85087 44 pin TSOP Il CY14B104NA BA45XCT 51 85128 48 ball FBGA Commercial CY14B104NA BA45XC 51 85128 48 ball FBGA CY14B104NA BA45XIT 51 85128 48 ball FBGA Industrial CY14B104NA BA45XI 51 85128 48 ball FBGA CY14B104NA ZSP45XCT 51 85160 54 pin TSOP II Commercial CY14B104NA ZSP45XC 51 85160 54 pin TSOP Il CY14B104NA ZSP45XIT 51 85160 54 pin TSOP II Industrial CY14B104NA ZSP45xXI 51 85160 54 pin TSOP II The above table contains Preliminary information Contact your local Cypress sales representative for availability of these parts Document 001 49918 Rev A Page 18 of 23 Feedback PRELIMINARY Part Numbering Nomenclature CY 14 B 100L 25 20 Speed 20 20 ns 25 25ns 45 45 ns Option T Tape amp Reel Blank Std Temperature C Commercial 0 to 70 C X Pb Free Industrial 40 to 85 C Blank SnPb P 54 Pin Blank 44 Pin 48 Ball Package BA 48 FBGA ZS TSOP II Die Revision Blank No Rev st Data Bus A 1 Rev dee N x16 Density 104 4 Mb Voltage B 3 0V Cypress NVSRAM 14 Auto Store Software Store Hardware Store Document 001 49918 Rev A CY14B104LA CY14B104NA
14. CY14B104LA CY14B104NA PERFORM 2 Pinouts continued Figure 3 Pin Diagram 54 Pin TSOP II x16 54 TSOP Il x16 Top View not to scale Pin Definitions Pin Name Type Description Ao Aig Input Address Inputs Used to Select one of the 524 288 bytes of the nvSRAM for x8 Configuration Ag Address Inputs Used to Select one of the 262 144 words of the nvSRAM for x16 Configuration 0 DQ Input Output Bidirectional Data I O Lines for x8 Configuration Used as input or output lines depending on operation DQ45 Bidirectional Data I O Lines for x16 Configuration Used as input or output lines depending on operation WE Input Write Enable Input Active LOW When selected LOW data on the I O pins is written to the specific address location CE Input Chip Enable Input Active LOW When LOW selects the chip When HIGH deselects the chip OE Input Output Enable Active LOW The active LOW OE input enables the data output buffers during read cycles I O pins are tri stated on deasserting OE HIGH BHE Input Byte High Enable Active LOW Controls DQ45 DQg BLE Input Byte Low Enable Active LOW Controls DQ Vss Ground Ground for the Device Must be connected to the ground of the system Vcc Power Supply Power Supply Inputs to the Device HSBI l Input Output Hardware Store Busy HSB When LOW this output indicates that a hardware stor
15. CY14B104NA performs a read cycle when CE and OE are LOW and WE and HSB are HIGH The address specified on pins 18 or Ap 47 determines which of the 524 288 data bytes or 262 144 words of 16 bits each are accessed Byte enables BHE BLE determine which bytes are enabled to the output in the case of 16 bit words When the read is initiated by an address transition the outputs are valid after a delay of tay read cycle 1 If the read is initiated by CE or OE the outputs are valid at tace or at whichever is later read cycle 2 The data output repeatedly responds to address changes within the taa access time without the need for transitions on any control input pins This remains valid until another address change or until CE or OE is brought HIGH or WE or HSB is brought LOW SRAM Write A write cycle is performed when and WE are LOW HSB is HIGH The address inputs must be stable before entering the write cycle and must remain stable until CE or WE goes HIGH at the end of the cycle The data on the common I O pins DQo_15 are written into the memory if the data is valid tsp before the end of a WE controlled write or before the end of an CE controlled write The Byte Enable inputs BHE BLE determine which bytes are written in the case of 16 bit words It is recommended that OE be kept HIGH during the entire write cycle to avoid data bus contention on common l O lines If OE is left LOW internal circuitry turns off th
16. addresses must be read the order listed in Table 1 on page 5 WE must HIGH during all six consecutive cycles Document 001 49918 Rev Page 14 of 23 Feedback PRELIMINARY CY14B104LA CY14B104NA Hardware STORE Cycle SR 20 ns 25 ns 45 ns Parameters Description Unit Min Max Min Max Min Max tpHsB HSB To Output Active Time when write latch not set 20 25 25 ns tpusB Hardware STORE Pulse Width 15 15 15 ns tss lt gt Soft Sequence Processing Time 100 100 100 us Switching Waveforms Figure 14 Hardware STORE 0 Write latch set HSB IN HSB OUT ZHSI DQ Data Out RWI Write latch not set t PHSB HSB pin is driven high to Voc only by Internal HSB IN 100kOhm resistor HSB driver is disabled _ SRAM is disabled as long as HSB is driven low HSB OUT touse RWI Figure 15 Soft Sequence Processing 27 Soft Sequence Soft Sequence tos Command Command gt lt gt Address dress AN dress 650000 F lt AN dires FO tsa tew tew CE Notes 26 This is the amount of time it takes to take action on a soft sequence command Vcc power must remain HIGH to effectively register command 27 Commands such as STORE and RECALL lock out I O until opera
17. until the cycle is completed Because a sequence of READs from specific addresses is used for STORE initiation it is important that no other read or write accesses intervene in the sequence or the sequence is aborted and no STORE or RECALL takes place To initiate the software STORE cycle the following read sequence must be performed 1 Read Address 0x4E38 Valid READ 2 Read Address 0xB1C7 Valid READ 3 Read Address 0x83E0 Valid READ 4 Read Address 0x7C1F Valid READ 5 Read Address 0x703F Valid READ 6 Read Address 0x8FCO Initiate STORE Cycle Table 1 Mode Selection CY14B104LA CY14B104NA The software sequence may be clocked with CE controlled reads or OE controlled reads After the sixth address in the sequence is entered the STORE cycle commences and the chip is disabled HSB is driven LOW It is important to use read cycles and not write cycles in the sequence although it is not necessary that OE be LOW for a valid sequence After the cycle time is fulfilled the SRAM is activated again for the read and write operation Software RECALL Transfer the data from the nonvolatile memory to the SRAM with a software address sequence A software RECALL cycle is initiated with a sequence of read operations in a manner similar to the software STORE initiation To initiate the RECALL cycle the following sequence of CE controlled read operations must be performed 1 Read Address 0x4E38 Valid READ 2 Read Address
18. 6 Document 001 49918 Rev 0250 0 00595 004 0050 0 NAI SEATING PLANE DETAIL A Ti L 0 406 0 01602 0 597 0 08355 51 85160 Page 22 of 23 Feedback PRELIMINARY CYPRESS CY14B104LA CY14B104NA PERFORM Document History Page Document Title CY14B104LA CY14B104NA 4 Mbit 512K x 8 256K x 16 nvSRAM Document Number 001 49918 Rev ECN No Orig of Change ee Description of Change 2606696 GVCH PYRS 11 13 08 New Data Sheet 2672700 GVCH PYRS 03 12 09 Added best practices Added CY14B104NA BA25I part number Added footnote12 for HZ LZ parameters Sales Solutions and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices solution centers manufacturer s representatives and distributors To find the office closest to you visit us at cypress com sales Products PSoC Solutions PSoC psoc cypress com General psoc cypress com solutions Clocks amp Buffers clocks cypress com Low Power Low Voltage psoc cypress com low power Wireless wireless cypress com Precision Analog psoc cypress com precision analog Memories memory cypress com LCD Drive psoc cypress com lcd drive Image Sensors image cypress com CAN 2 0b psoc cypress com can USB psoc cypress com usb Cypress Semiconductor Corporation 2008 2009 The information contained herein is subject to change without n
19. STORE Software Store Recall AutoStore Enable Disable and AutoStore initiation SRAM operation continues to be enabled for time tpg 22 Read and write cycles are ignored during STORE RECALL and while VCC is below 23 HSB pin is driven HIGH to VCC only by internal 100 kOhm resistor HSB driver is disabled Document 001 49918 Rev Page 13 of 23 Feedback PRELIMINARY CYPRESS CY14B104LA CY14B104NA PERFORM Software Controlled STORE RECALL Cycle In the following table the software controlled STORE and RECALL cycle parameters listed 24 251 Parameters Description 20108 28103 dis Unit Min Max Min Max Min Max tnc STORE RECALL Initiation Cycle Time 20 25 45 ns tsa Address Setup Time 0 0 0 ns tow Clock Pulse Width 15 20 30 ns tua Address Hold Time 0 0 0 ns tRECALL RECALL Duration 200 200 200 us Switching Waveforms em Figure 12 and OE Controlled Software STORE RECALL 2 t tac Address 1 CN OX Address 6 E v tsa HSB STORE only tuzce DELAY tious K High Impedance K DA DATA o feo ens D RWI Figure 13 AutoStore Enable Disable Cycle tac tac Address Address 1 X A Ox Address 6 mi DQ DATA RWI Notes 24 The software sequence is clocked with CE controlled or OE controlled reads 25 The six consecutive
20. advertently such as program bugs and incoming inspection routines Best Practices nvSRAM products have been used effectively for over 15 years While ease of use is one of the product s main system values experience gained working with hundreds of applications has resulted in the following suggestions as best practices m The VcAP value specified in this data sheet includes a minimum m The nonvolatile cells in this nvSRAM product are delivered from and a maximum value size Best practice is to meet this Cypress with 0x00 written in all cells Incoming inspection routines at customer or contract manufacturer s sites sometimes reprogram these values Final NV patterns are typically repeating patterns of AA 55 00 FF A5 or 5A End product s firmware should not assume an NV array is in a set programmed state Routines that check memory content values to determine first time system configuration cold or requirement and not exceed the maximum value because the nvSRAM internal algorithm calculates VcAP charge and discharge time based on this max value Customers that want to use a larger VcAP value to make sure there is extra store charge and store time should discuss their VCAP size selection with Cypress to understand any impact on the warm boot status and so on should always program a unique voltage level at the end of a tkecau period NV pattern that is complex 4 byte pattern of 46 E6 49 53 hex or mor
21. ations are also available under software control Logic Block 2 3 R A A w gt A D A D Ag E R U Ugo poo e P PP P O P P ror Se wis 2 ox STATIC RAM 2048 X 2048 COLUMN I O COLUMN DEC A Ato Ay Vi V Quatrum Trap ye 2048 X 2048 RECALL POWER CONTROL Y STORE RECALL CONTROL ARRAY SOFTWARE DETECT BLE BHE Notes 1 Address Ao Ajg for x8 configuration and Address Ao A47 for x16 configuration 2 Data DQ DQ for x8 configuration and Data DQ DQ4s5 for x16 configuration 3 BHE and BLE are applicable for x16 configuration only Cypress Semiconductor Corporation Document 001 49918 Rev A 198 Champion Court San Jose CA 95134 1709 408 943 2600 Revised March 11 2009 Feedback ERG PRELIMINARY CYPRESS CY14B104LA CY14B104NA PERFORM Pinouts Figure 1 Pin Diagram 48 FBGA x8 x16 Top View Top View 1 FO 3 4 5 6 MEM MV 4 5 6 a SE 80 a e AIAIE 603 FEA e
22. de Vo Power L H L 0 4 38 Read SRAM Output Data Activel l OxB1C7 Read SRAM Output Data 0x83E0 Read SRAM Output Data 0x7C1F Read SRAM Output Data 0x703F Read SRAM Output Data 0x4B46 AutoStore Enable Output Data L H L 0 4 38 Read SRAM Output Data Active 2 OxB1C7 Read SRAM Output Data 0x83E0 Read SRAM Output Data 0x7C1F Read SRAM Output Data 0x703F Read SRAM Output Data 0x8FC0 Nonvolatile Store Output High Z L H L 0x4E38 Read SRAM Output Data 81 0xB1C7 Read SRAM Output Data 0x83E0 Read SRAM Output Data Ox7C1F Read SRAM Output Data 0x703F Read SRAM Output Data 0x4C63 Nonvolatile Output High Z Recall Preventing AutoStore The AutoStore function is disabled by initiating an AutoStore disable sequence A sequence of read operations is performed a manner similar to the software STORE initiation To initiate the AutoStore disable sequence the following sequence of CE controlled read operations must be performed 1 Read address Ox4E38 Valid READ 2 Read address OxB1C7 Valid READ 3 Read address 0x83E0 Valid READ 4 Read address 0x7C1F Valid READ 5 Read address 0x703F Valid READ 6 Read address 0x8B45 AutoStore Disable The AutoStore is re enabled by initiating an AutoStore enable sequence A sequence of read operations is performed in a manner similar to the software RECALL initiation To initiate the AutoStore enable sequence the following sequence of CE controlled read operations must be perfo
23. dification translation compilation or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Cypress reserves the right to make changes without further notice to the materials described herein Cypress does not assume any liability arising out of the application or use of any product or circuit described herein Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress product in a life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Use may be limited by and subject to the applicable Cypress software license agreement Document 001 49918 Rev A Revised March 11 2009 Page 23 of 23 AutoStore and QuantumTrap are registered trademarks of Cypress Semiconductors All other products and company names mentioned in this document are the trademarks of their respective holders Feedback
24. e is in progress When pulled LOW external to the chip it initiates a nonvolatile STORE operation A weak internal pull up resistor keeps this pin HIGH if not connected connection optional After each store operation HSB is driven HIGH for short time with standard output high current Power Supply AutoStore Capacitor Supplies power to the nvSRAM during power loss to store data from SRAM to nonvolatile elements NC No Connect No Connect This pin is not connected to the die Document 001 49918 Rev A Page 3 of 23 Feedback Device Operation The CY14B104LA CY14B104NA nvSRAM is made up of two functional components paired in the same physical cell They are a SRAM memory cell and a nonvolatile QuantumTrap cell The SRAM memory cell operates as a standard fast static RAM Data in the SRAM is transferred to the nonvolatile cell the STORE operation or from the nonvolatile cell to the SRAM the RECALL operation Using this unique architecture all cells are stored and recalled in parallel During the STORE and RECALL operations SRAM read and write operations are inhibited The CY14B104LA CY14B104NA supports infinite reads and writes similar to a typical SRAM In addition it provides infinite RECALL operations from the nonvolatile cells and up to 200K STORE operations See the Truth Table For SRAM Operations on page 16 for a complete description of read and write modes SRAM Read The CY14B104LA
25. e output buffers tyzwe after WE goes LOW AutoStore Operation The CY14B104LA CY14B104NA stores data to the nvSRAM using one of the following three storage operations Hardware Store activated by HSB Software Store activated by an address sequence AutoStore on device power down The AutoStore operation is a unique feature of QuantumTrap technology and is enabled by default on the CY14B104LA CY14B104NA During a normal operation the device draws current from Vcc to charge a capacitor connected to the pin This stored charge is used by the chip to perform a single STORE operation If the voltage on the Vcc pin drops below Vswircn the part automatically disconnects the pin from Voc A STORE operation is initiated with power provided by the capacitor Figure 4 shows the proper connection of the storage capacitor Vcap for automatic store operation Refer to DC Electrical Document 001 49918 Rev A PRELIMINARY CY14B104LA CY14B104NA Characteristics page 8 for the size of Vcap The voltage on the Vcap pin is driven to Vcc by a regulator on the chip A pull up should be placed on WE to hold it inactive during power up This pull up is effective only if the WE signal is tri state during power up Many MPUs tri state their controls on power up This should be verified when using the pull up When the nvSRAM comes out of power on recall the MPU must be active or the WE held inactive until the MPU co
26. e random bytes as part of the final system manufac turing test to ensure these system routines work consistently Document 001 49918 Rev A Page 7 of 23 Feedback Maximum Ratings Exceeding maximum ratings may impair the useful life of the device These user guidelines are not tested Storage Temperature Maximum Accumulated Storage Time At 150 C Ambient Temperature 1000h PRELIMINARY CY14B104LA CY14B104NA Transient Voltage lt 20 ns on Any Pin to Ground Potential Package Power Dissipation M 65 C to 150 C Surface Mount Pb Soldering Temperature 3 Seconds DC Output Current 1 output at a time 1s duration 15 mA 2 0V to Vcc 2 0V Capability TA 25 1 0W At 85 C Ambient Temperature 20 Years Static Discharge Voltage gt 2001 i per MIL STD 883 Method 3015 Ambient Temperature with Power 55 C to 150 C Latch Up Current 200 Supply Voltage Vcc Relative to GND 0 5V to 4 1V Operating Range Voltage Applied to Outputs in High Z State 0 5V to 0 5V sec Temp
27. erature Vcc Input Voltage 0 5V to Vcc 0 5V Commercial 0 C to 70 C Industrial 40 C to 85 C 2 7V to 3 6V DC Electrical Characteristics Over the Operating Range Vcc 2 7V to 3 6V Parameter Description Test Conditions Min Max Unit lect Average Vcc Current tac 20 ns Commercial 65 mA tro 25ns 65 mA tro 45 ns 50 mA Values obtained without output loads lour 0 mA Industrial 70 mA 70 mA 52 mA loce Average Vcc Current All Inputs Don t Care Voc 10 mA during STORE Average current for duration local Average Vcc Currentat All I P cycling at CMOS levels 35 mA trc 200 ns 25 C Values obtained without output loads lour 0 typical loca Average Vcap Current All Inputs Don t Care Vcc 5 mA during AutoStore Cycle Average current for duration tsTORE Isp Vcc Standby Current CE gt Voc 0 2 All others Viy lt 0 2V or gt Voc 0 2V Standby 5 mA current level after nonvolatile cycle is complete Inputs are static f 0 MHz Ixl 0 Input Leakage Current Voc Max Vss lt ViN lt Vec 1 1 uA except HSB Input Leakage Current Vcc Max Vss lt Vin lt Vcc 100 1 pA for HSB loz Off State Output Vcc Vss lt Vout lt Voc or OE gt Viy or BHE BBLE gt 1 1 uA Leakage Current or WE lt Vy Vin Input HIGH Voltage 2 0 Voc V 0 5 Vit Input LOW Voltage Vs 0 5 08 V Vou Output HIGH Voltage
28. for measuring thermal Osc Thermal Resistance _ in accordance with 5051 7 84 5 56 6 08 oC W Junction to Case Figure 5 AC Test Loads 5770 5770 for tri state specs 3 0V 3 0V R1 R1 OUTPUT OUTPUT 30 pF R2 5 pF R2 7890 7890 AC Test Conditions Input Pulse Levels OV to 3V Input Rise and Fall Times 10 9095 lt 3 ns Input and Output Timing Reference Levels 1 5V Note 12 These parameters are guaranteed but not tested Page 9 of 23 Document 001 49918 Rev A Feedback 5 2 55 PERFORM PRELIMINARY AC Switching Characteristics CY14B104LA CY14B104NA Parameters 20 ns 25 ns 45 ns Description ni Parameters Min Max Min Max Min Max SRAM Read Cycle tACE tacs Chip Enable Access Time 20 25 45 ns trel thc Read Cycle Time 20 25 45 ns m tan Address Access Time 20 25 45 ns tpoE tog Output Enable to Data Valid 10 12 20 ns tonal toH Output Hold After Address Change 3 3 ns 2 17 tuz Chip Enable to Output Active 3 3 3 ns I Chip Disable to Output Inactive 8 10 15 ns tizog 19 tolz Output Enable to Output Active 0 0 0 ns 2 15 touz Output Disable to Output Inactive 8 10 15 ns pu fia X Chip EnabletoPoweractve 0
29. mes out of reset To reduce unnecessary nonvolatile stores AutoStore and hardware store operations are ignored unless at least one write operation has taken place since the most recent STORE or RECALL cycle Software initiated STORE cycles are performed regardless of whether a write operation has taken place The HSB signal is monitored by the system to detect if an AutoStore cycle is in progress Figure 4 AutoStore Mode Vcc e 0 1uF Vcc 10kOhm z m V px ss Hardware STORE Operation The CY14B104LA CY14B104NA provides the HSB pin to control and acknowledge the STORE operations Use the HSB pin to request a hardware STORE cycle When the HSB pin is driven LOW the CY14B104LA CY14B104NA conditionally initiates a STORE operation after An actual STORE cycle only begins if a write to the SRAM has taken place since the last STORE or RECALL cycle The HSB pin also acts as an open drain driver that is internally driven LOW to indicate a busy condition when the STORE initiated by any means is in progress SRAM read and write operations that are in progress when HSB is driven LOW by any means are given time to complete before the STORE operation is initiated After HSB goes LOW the CY14B104LA CY14B104NA continues SRAM operations for tpELAY If a write is in progress when HSB is pulled LOW it is enabled a time to complete However any SRAM write
30. otice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Any Source Code software and or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign United States copyright laws and international treaty provisions Cypress hereby grants to licensee a personal non exclusive non transferable license to copy use modify create derivative works of and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement Any reproduction mo
31. rmed 1 Read address 0x4E38 Valid READ 2 Read address 0xB1C7 Valid READ 3 Read address 0x83E0 Valid READ 4 Read address 0x7C1F Valid READ 5 Read address 0x703F Valid READ 6 Read address 0x4B46 AutoStore Enable If the AutoStore function is disabled or re enabled a manual STORE operation hardware or software must be issued to save the AutoStore state through subsequent power down cycles The part comes from the factory with AutoStore enabled Document 001 49918 Rev A Data Protection The CY14B104LA CY14B104NA protects data from corruption during low voltage conditions by inhibiting all externally initiated STORE and write operations The low voltage condition is detected when Vec lt Vswitcu Af the CY14B104LA CY14B104NA is in a write mode both CE and WE are LOW at power up after a RECALL or STORE the write is inhibited until the SRAM is enabled after tj 2745p HSB to output active This protects against inadvertent writes during power up or brown out conditions Noise Considerations Refer to CY application note AN1064 Page 6 of 23 Feedback PRELIMINARY 23 IJ CYPRESS PERFORM CY14B104LA CY14B104NA m Power up boot firmware routines should rewrite the nvSRAM into the desired state for example autostore enabled While the nvSRAM is shipped in a preset state best practice is to again rewrite the nvSRAM into the desired state as a safeguard against events that might flip the bit in
32. tion is complete which further increases this time See the specific command Document 001 49918 Rev A Page 15 of 23 Feedback e 24 lt lt CYPRESS PERFORM PRELIMINARY CY14B104LA CY14B104NA Truth Table For SRAM Operations HSB should remain HIGH for SRAM Operations For x8 Configuration CE WE OE Inputs Outputs 2 Mode Power H X X High Z Deselect Power down Standby L H L Data Out DQg DQ7 Read Active L H H High Z Output Disabled Active L L X Data in DQg DQ7 Write Active For x16 Configuration CE WE OE BHE BLED H X X X X High Z Deselect Power down Standby L X X H H High Z Output Disabled Active L H L L L Data Out DQo DQ4s Read Active L H L H L Data Out DQg DQy7 Read Active DQg DQ5 in High Z L H L L H Data Out DQg DQ5 Read Active DQg DQ in High Z L H H L L High Z Output Disabled Active L H H H L High Z Output Disabled Active L H H L H High Z Output Disabled Active L L X L L Data In DQo DQ5 Write Active L L X H L Data In 000 005 Write Active DQg DQ5 High Z L L X L H Data In DQg DQ5 Write Active DQo DG in High Z Document 001 49918 Rev A Page 16 of 23 Feedback 2 CYPRESS PERFORM Ordering Information PRELIMINARY CY14B104LA
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