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Cypress CY14B101P User's Manual

1. RECALL Duration Soft Sequence Processing Time CS Q 1 2 3 4 b 6 7 SCK SI 0 0 1 1 1 140 Q eropp gt RWI Hi Z RDY Figure 29 Software RECALL Cycle C 0 1 2 3 4 5 6 7 SCK SI 0 1 1 0 0 0 0 Gf RECALL A Hi Z RWI RDY Notes 12 This is the amount of time it takes to take action on a soft sequence command Vcc power must remain HIGH to effectively register command 13 Commands such as STORE and RECALL lock out IO until operation is complete which further increases this time See the specific command Page 27 of 32 Feedback Document 001 44109 Rev B CY14B101P x SSS CYPRESS PRELIMINARY PERFORM Hardware STORE Cycle CY14B101P Parameter Description Unit Min Max tpHsB HSB To Output Active Time when write latch not set 25 ns tPHSB Hardware STORE Pulse Width 15 ns Figure 30 Hardware STORE Cyclel Write Latch set PHSB HSB IN l A tsTORE DELAY e HDD HSB OUT gt l LZHSB so RWI Be Write Latch not set PHSB HSB IN ll HSB pin is driven high to Vcc only by Internal 100KQ resistor HSB driver is disabled SRAM is disabled as long as HSB IN is driven LOW HSB OUT DELAY DHSB DHSB m RWI N Document 001 44109 Rev B Page 28 of 32 Feedback SE
2. Lu PART 16 16 3 STANDARD PKG HOES S716 3 LEAD FREE PKG SEATING PLANE NN A B 0 397 10 0831 R 0 413L10 4901 0 09212 336 i 0 10512 667 I L B CN 0 004t0 101 x 050012701 x 0009102311 eme emp oque 0 00410 101 001510381 JL 0 0125 0 317 0 011810 2991 EISE IL 00130330 0 01910 482 51 85022 B Page 30 of 32 Feedback Document 001 44109 Rev B Document History Page Submission PRELIMINARY Date CY14B101P Description of Change Orig of Change UNC AESA New Data Sheet GSIN Updated the Feature section Clock rate changed from 40 MHz to 25 MHz Updated nvSRAM STORE RECALL AutoStore Enable Disable sections Removed Soft Sequence added SPI instructions for STORE RECALL AutoStore Enable and Disable Updated SPI with following changes See ECN 11 21 2008 RV ZS Document Title CY14B101P 1 Mbit 128K x 8 Serial SPI nvSRAM with Real Time Clock Added four new SPI instruction GVCH AESA WEN bit cleared on CS going HIGH edge after Write instructions and four Added more information for protocol Added RDY bit to Status Register for indicating Store Recall in progress Document Number 001 44109 REV ECN NO Tt 1939467 A 2607447 B nvSRAM special instructions Added READ RTC and WRITE RTC instructions Changed RTC re
3. ss p J CYPRESS PRELIMINARY CY14B101P PERFORM Table 1 Pin Definitions Figure 1 Pin Diagram 16 Pin SOIC Top View not to scale VRTCcap 17 GND 18 Pin Name UO Type Description CS Input Chip Select Activates the device when pulled LOW Driving this pin HIGH puts the device in low power standby mode SCK Input Serial Clock Runs at speeds up to a maximum of 25 MHz All inputs are latched at the rising edge of this clock Outputs are driven at the falling edge of the clock SI Input Serial Input Pin for input of all SPI instructions and data SO Output Serial Output Pin for output of data through SPI WP Input Write Protect Implements hardware write protection in SPI HOLD Input HOLD Pin Suspends Serial Operation HSB Input Output Hardware Store Busy A weak internal pull up keeps this pin pulled HIGH If not used this pin is left as No Connect Output Indicates busy status of nvSRAM when LOW Input Hardware Store implemented by pulling this pin LOW externally Voap Power Supply AutoStore Capacitor Supplies power to the nvSRAM during power loss to STORE data from the SRAM to nonvolatile elements If AutoStore is not needed this pin must be left as No Connect It must never be connected to GND VatCcap Power Supply Capacitor Backup for RTC Left unconnected if Vatcpat is used VRTCbat Power Supply Battery Backup for RTC Lef
4. 10 001010b must be loaded into the Calibration register to offset this error Note Setting or changing the Calibration register does not affect the test output frequency To set or clear CAL set the write bit W in the flags register at 0x00 to 1 to enable writes to the Flag register Write a value to CAL and then reset the write bit to 0 to disable writes Alarm The alarm function compares user programmed values of alarm time and date stored in the registers 0x01 5 with the corre sponding time of day and date values When a match occurs the alarm internal flag AF is set and an interrupt is generated on INT pin if Alarm Interrupt Enable AIE bit is set Document 001 44109 Rev B PRELIMINARY CY14B101P There are four alarm match fields date hours minutes and seconds Each of these fields has a match bit that is used to determine if the field is used in the alarm match logic Setting the match bit to 0 indicates that the corresponding field is used in the match process Depending on the match bits the alarm occurs as specifically as once a month or as frequently as once every minute Selecting none of the match bits all 1s indicates that no match is required and therefore alarm is disabled Selecting all match bits all Os causes an exact time and date match There are two ways to detect an alarm event by reading the AF flag or monitoring the INT pin The AF flag in the flags register a
5. SCK nnn 45 670123456 7 Op Code 4 bit Address SI mt 0 0 J Vo 0 In Vo jojo Y 0 y 0 Jl eer eieiei kceieiet SO Data LSB HI Z nvSRAM Special Instructions CY14B101P provides four special instructions that allow access to the nvSRAM specific functions STORE RECALL ASDISB and ASENB Table 7 lists these instructions Table 7 nvSRAM Special Instructions Function Name Opcode Operation STORE 0011 1100 Software Store RECALL 0110 0000 Software Recall ASENB 0101 1001 AutoStore Enable ASDISB 0001 1001 AutoStore Disable Software Store STORE When a STORE instruction is executed CY14B101P performs a Software Store operation The STORE operation is issued Document 001 44109 Rev B irrespective of whether a write has taken place since last STORE or RECALL operation Figure 16 Software STORE Operation cs 0 1 2 3 4 5 6 7 SCK SI 0 0 1 1 1 140 0 SO Hi Z To issue this instruction the device must be write enabled WEN bit 1 The instruction is performed by transmitting the STORE opcode on the SI pin following the falling edge of CS The WEN Page 12 of 32 Feedback EE CYPRESS PERFORM bit is cleared on the positive edge of CS following the STORE instruction Software Recall RECALL When a RECALL inst
6. and BP1 pins of the Status Register The write enable and disable status of the device is indicated by WEN bit of the status register The write instructions WRSR WRITE and WRTC and nvSRAM special instruction STORE RECALL ASENB ASDISB need the write to be enabled WEN bit 2 1 before they can be issued Write Enable WREN Instruction On power up the device is always in the write disable state The following WRITE WRSR WRTC or nvSRAM special instruction must therefore be preceded by a Write Enable instruction If the device is not write enabled WEN 0 it ignores the write instructions and returns to the standby state when CS is brought HIGH A new CS falling edge is required to re initiate serial communication The instruction is issued following the falling edge of CS When this instruction is used the WEN bit of status register is set to 1 Note After completion of a write instruction WRSR WRITE or WRTO or nvSRAM special instruction STORE RECALL ASENB ASDISB instruction WEN bit is cleared to 0 This is done to provide protection from any inadvertent writes Therefore WREN instruction needs to be used before a new write instruction can be issued Figure 8 WREN Instruction cs 0 1 2 3 4 5 6 7 SCK SI 40000 0 1 1X0 SO Hi Z Write Disable WRDI Instruction Write Disable instruction disables the write by clearing the WEN
7. status of clock when the bus master is in Standby mode and not CY14B101P device may be driven by a microcontroller with its SPI peripheral running in either of the following two modes m SPI Mode 0 CPOL 0 CPHA 0 m SPI Mode 3 CPOL 1 CPHA 1 For both these modes input data is latched in on the rising edge of Serial Clock SCK starting from the first rising edge after CS goes active If the clock starts from a HIGH state in mode 3 the first rising edge after the clock toggles are considered The output data is available on the falling edge of Serial Clock SCK Figure 4 SPI Mode 0 e E SCK 5 6 7 nu LI s Hr HeHsHaHsH2H1H9 Document 001 44109 Rev B transferring data is m SCK remains at 0 for Mode 0 m SCK remains at 1 for Mode 3 CPOL and CPHA bits must be set in the SPI controller for the either Mode 0 or Mode 3 CY14B101P detects the SPI mode from the status of SCK pin when device is selected by bringing the CS pin LOW If SCK pin is LOW when device is selected SPI Mode 0 is assumed and if SCK pin is HIGH CY14B101P works in SPI Mode 3 Figure 5 SPI Mode 3 c8 SI 7 H6 Hs H4H3H2H1H of Page 6 of 32 Feedback e LL SPI Operating Features Power Up Power up is defined as the condition when the power supply is turned
8. Feedback AA er PI CYPRESS PERFORM I E Real Time Clock Operation nvTIME Operation The CY14B101P offers internal registers that contain clock alarm watchdog interrupt and control functions The RTC registers occupy a separate address space from nvSRAM and are accessible through Read RTC RDRTC and Write RTC WRTO instructions on register addresses 0x00 to OxOF Internal double buffering of the clock and the timer information registers prevents accessing transitional internal clock data during a read or write operation Double buffering also circumvents disrupting normal timing counts or the clock accuracy of the internal clock when accessing clock data Clock and alarm registers store data in BCD format Clock Operations The clock registers maintain time up to 9 999 years in one second increments The time can be set to any calendar time and the clock automatically keeps track of days of the week and month leap years and century transitions There are eight registers dedicated to the clock functions which are used to set time with a write cycle and to read time during a read cycle These registers contain the time of day in BCD format Bits defined as 0 are currently not used and are reserved for future use by Cypress Reading the Clock The double buffered RTC register structure reduces the chance of reading incorrect data from the clock The user must stop internal updates to the C
9. are reset to the Base Time see Setting the Clock on page 14 which is the value last written to the timekeeping registers The control or calibration registers and the OSCEN bit are not affected by the oscillator failed condition Page 14 of 32 Feedback CYPRESS PERFORM The value of OSCF must be reset to 0 when the time registers are written for the first time This initializes the state of this bit which may have become set when the system was first powered on To reset OSCF set the write bit W in the Flags register at 0x00 to a 1 to enable writes to the Flag register Write a 0 to the OSCF bit and then reset the write bit to 0 to disable writes Calibrating the Clock The RTC is driven by a quartz controlled crystal with a nominal frequency of 32 768 kHz Clock accuracy depends on the quality of the crystal and calibration The crystals available in market typically have an error of 20 ppm to 35 ppm However CY14B101P employs a calibration circuit that improves the accuracy to 1 2 ppm at 25 C This implies an error of 2 5 seconds to 5 seconds per month The calibration circuit adds or subtracts counts from the oscillator divider circuit to achieve this accuracy The number of pulses that are suppressed subtracted negative calibration or split added positive calibration depends upon the value loaded into the five calibration bits found in Calibration register at Ox08 The
10. in progress If a STORE RECALL cycle is in progress the device goes into the Standby Power Mode after the STORE RECALL cycle is completed In the Standby Power mode the current drawn by the device drops to Isg SPI Functional Description The CY14B101P uses an 8 bit instruction register Instructions and their operation codes are listed in Table 2 All instructions addresses and data are transferred with the MSB first and start with a HIGH to LOW CS transition There are in all 12 SPI instructions which provide access to most of the functions in nvSRAM Further the WP and HOLD pins provide additional functionality driven through hardware Table 2 Instruction Set Instruction Instruction A Category Name Opcode Operation WREN 0000 0110 Set Write Enable Latch WRDI 0000 0100 Reset Write Bine Enable Latch egister Leben SS 00000101 Read Status Register WRSR 0000 0001 Write Status Register READ 0000 0011 Read Data From SRAM Memory Array Read Write Instructions WRITE 0000 0010 Write Data To Memory Array WRTC 0001 0010 Write RTC ie del ea Instructions RDRTC 0001 0011 Read RTC Registers STORE 0011 1100 Software Store Special NV RECALL 0110 0000 Software Recall Instructions ASENB 0101 1001 AutoStore Enable ASDISB 0001 1001 AutoStore Disable Reserved Reserved 0001 1110 Reserved for Internal use The SPI instructions in CY14B101P are divided based
11. is issued after the falling edge of CS using the opcode for WRSR followed by eight bits of data to be stored in the Status Register Since only bits 2 3 and 7 can be modified by WRSR instruction it is recommended to leave the other bits as 0 while writing to the Status Register Note In CY14B101P the values written to Status Register are saved to nonvolatile memory only after a STORE operation If AutoStore is disabled any modifications to the Status Register must be secured by using a Software STORE operation Figure 6 Read Status Register RDSR Instruction Timing cs r 0 1 23456701 2 3 4 5 6 7 SCK HI Z SO Document 001 44109 Rev B st Bo o o o of1 o 1 MSB LSB D7X D6 D5 D4 D3X D2 D1 X DO MSB Data LSB Page 8 of 32 Feedback EE CYPRESS PERFORM PRELIMINARY CY14B101P Figure 7 Write Status Register WRSR Instruction Timing cs 0 1 23 4 5 6 70 1 scx LTL UU Opcode Data in SI Lo o o o o o 0 1570 o ofp3p2o of so HI Z MSB LSB Write Protection and Block Protection CY14B101P provides features for both software and hardware write protection using WRDI instruction and WP Additionally this device also provides block protection mechanism through BPO
12. of 32 Feedback E Kenner _ c am SES LZ une PRELIMINARY CY14B101P PERFORM Figure 11 Burst Mode Read Instruction Timing cs 01 2 3 4 5 6 7 01 2 3 4 5 6 7 innannnnnannm LL see cx UU Op Code 17 bit Address SI 0000 00 1 1 ojo Jojo Jojo o mre Sc MSB LSB Data Byte 1 Data Byte N SO ler locale 01 00 oi Dok D7 D6 D5 D4 A D3 D2 kp DO MSB LSB MSB LSB Figure 12 Write Instruction Timing 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 20 21 22 23 0 1 2 3 4 5 6 7 SCK pi l Op Code 17 bit Address SI EU 00000 1 0 o Yo Yo y ol ko Ko Kate Yas nz at nl o7 06 08 04 03 02 04 00 MSB LSB MSB Data LSB TA HI Z Figure 13 Burst Mode Write Instruction Timing 01 2 3 4 5 6 7 0 1 2 3 4 5 6 7 UU UU UU UU UU UU sx TUUU uf hun Data Byte 1 Data Byte N 4 po Cl peJpsfb Josfbz or po Op Code 1
13. on their functionality in following types a Status Register Access WRSR and RDSR instructions a Write Protection Functions WREN and WRDI instructions along with WP pin and WEN BPO and BP1 bits a SRAM memory Access READ and WRITE instructions a RTC access RDRTC and WRTC instructions a nvSRAM special instructions STORE RECALL ASENB and ASDISB Page 7 of 32 Feedback Status Register The status register bits are listed in Table 3 The status register consists of Ready bit RDY and data protection bits BP1 BPO WEN and WPEN The RDY bit can be polled to check the Ready Busy status while a nvSRAM STORE cycle is in progress The status register can be modified by WRSR instruc Table 3 Status Register Format PRELIMINARY CY14B101P tion and read by RDSR instruction However only WPEN BP1 and BPO bits of the Status Register can be modified by using WRSR instruction WRSR instruction has no effect on WEN and RDY bits The default value shipped from the factory for BP1 BP2 and WPEN bits is 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 WPEN 0 X X X BP1 0 BPO 0 WEN RDY Table 4 Status Register Bit Definition Bit Definition Description Bit 0 RDY Ready Read Only bit indicates the ready status of device to perform a memory access This bit is set to 1 by the device while a STORE or Software Recall cycle is in progress Bit 1 W
14. progress The RECALL operation in no way alters the data in the nonvolatile elements Hardware Recall Power Up During power up when Vcc crosses Vswircu an automatic RECALL sequence is initiated which transfers the content of nonvolatile memory on to the SRAM A Power Up Recall cycle takes tra time to complete and the memory access is disabled during this time HSB pin is used to detect the Ready status of the device Software Recall Software Recall allows the user to initiate a RECALL operation to restore the content of nonvolatile memory on to the SRAM In CY14B101P this can be done by issuing a RECALL instruction in SPI A Software Recall takes treca to complete during which all memory accesses to nvSRAM are inhibited The controller must provide sufficient delay for the RECALL operation to complete before issuing any memory access instructions Disabling and Enabling AutoStore If the application does not require the AutoStore feature it can be disabled in CY14B101P by using the ASDISB instruction If this is done the nvSRAM does not perform a STORE operation at power down AutoStore can be re enabled by using the ASENB instruction However these operations are not nonvolatile and if the user needs this setting to survive power cycle a STORE operation must be performed following Autostore Disable or Enable operation Note CY14B101P comes from the factory with AutoStore Enabled Note If AutoStore is disabled and
15. static RAM with full featured real time clock in a monolithic integrated circuit with serial SPI interface The memory is organized as 128K words of 8 bits each The embedded nonvolatile elements incorporate the QuantumTrap technology creating the world s most reliable nonvolatile memory The SRAM provides infinite read and write cycles while the QuantumTrap cells provide highly reliable nonvolatile storage of data Data transfers from SRAM to the nonvolatile elements STORE operation takes place automatically at power down On power up data is restored to the SRAM from the nonvolatile memory RECALL operation The STORE and RECALL operations can also be initiated by the user Logic Block Diagram Vee Vear CM Quantum Trap cs kt 128K X 8 Power Control daad Instruction decode WP Write protect A y SCK T Control logic STORE RECALL SRAM ARRAY STORE Control 1 HSB HOLD MEL 128K X 8 RECALL La Instruction D0 D7 register A0 A16 le Xout Address N ou EN A wi Decoder RIC Xin gt INT SI Data I O register MUX SO Status register Cypress Semiconductor Corporation Document 001 44109 Rev B 198 Champion Court San Jose CA 95134 1709 408 943 2600 Revised February 2 2009 Feedback
16. to 1 the alarm match drives the INT pin and the AF flag When set to 0 the alarm match only affects the AF flag PFE Power Fail Enable When set to 1 the alarm match drives the INT pin and the PF flag When set to 0 the power fail monitor affects only the PF flag 0 Reserved for future use H L HIGH LOW When set to 1 the INT pin is driven active HIGH When set to 0 the INT pin is open drain active LOW P L Pulse Level When set to 1 the INT pin is driven active determined by H L by an interrupt source for approximately 200 ms When set to 0 the INT pin is driven to an active level as set by H L until the flags register is read Alarm Day 0x05 D7 D6 D5 D4 D3 D2 D1 DO x M 0 10s Alarm Date Alarm Date Contains the alarm value for the date of the month and the mask bit to select or deselect the date value M Match When this bit is set to 0 the date value is used in the alarm match Setting this bit to 1 causes the match circuit to ignore the date value Alarm Hours D7 D6 D5 DA D3 D2 D1 DO 0x04 M 10s Alarm Hours Alarm Hours Contains the alarm value for the hours and the mask bit to select or deselect the hours value M Match When this bit is set to 0 the hours value is used in the alarm match Setting this bit to 1 causes the match circuit to ignore the hours value Alarm Minutes 0x03 D7 D6 D5 D4 D3 D2 D1 DO x M 10s Alarm Minutes Alarm Minutes Contains the alarm value for the minutes and the mask bit to select or deselect the minu
17. you visit us at cypress com sales Products PSoC Solutions PSoC psoc cypress com General psoc cypress com solutions Clocks amp Buffers clocks cypress com Low Power Low Voltage psoc cypress com low power Wireless wireless cypress com Precision Analog psoc cypress com precision analog Memories memory cypress com LCD Drive psoc cypress com Icd drive Image Sensors image cypress com CAN 2 0b psoc cypress com can USB psoc cypress com usb Cypress Semiconductor Corporation 2008 2009 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Any Source Code software and or firmware is owned by Cypress Semiconductor Corporation Cypress and is p
18. 7 bit Address o NTEEIATOOODUCCGS 2220922095 7 MSB LSB MSB LSB HI Z SO READ RTC RDRTC Instruction pon bit n RTC Flag register desto an to 1 before ean time keeping registers to avoid reading transitional data Read RTC RDRTO instruction allows the user to read the Modifying the RIC Flag registers requires d Write RTC cycle contents of RTC registers Reading the RTC registers through The R bit must be cleared to 0 after completion of the read the serial output SO pin requires the following sequence After operation the CS line is pulled LOW to select a device the RDRTC opcode The easiest way to read RTC registers is to perform RDRTC in is transmitted through the SI line followed by eight address bits burst mode The read may start from the first RTC register 0x00 for selecting the register Any data on the SI line after the address and the CS must be held LOW to allow the data from all 16 RTC bits is ignored The data D7 DO at the specified address is then registers to be transmitted through the SO pin shifted out onto the SO line RDRTC also allows burst mode read Note Read RTC instruction operates at a maximum clock operation When reading multiple bytes from RTC registers the frequency of 25 MHz address rolls over to 0x00 after the last RTC register address OxOF is reached Document 001 44109 Rev B Page 11 of 32 Feedback Kg F CYPRESS PERFORM PRELIMIN
19. 7V to 3 6V DC Electrical Characteristics Over the Operating Range Vcc 2 7V to 3 6V Parameter Description Test Conditions Min Max Unit loci Average Vec Current At fsck 40 MHz 10 mA loce Average Vcc Current All Inputs Don t Care Voc Max 10 mA during STORE Average current for duration tsrore loca Average Vcap Current All Inputs Don t Care Voc Max 5 mA during AutoStore Average current for duration eropp Cycle Isp Vcc Standby Current 5 mA NE Input Leakage Current Vcc Max Vss lt Vin lt Mee 1 1 HA except HSB InputLeakage Current Vcc Max Vss lt Vin x Nee 100 1 HA for HSB loz Off State Output Vec Max Vss E Vout lt Voc 1 1 yA Leakage Current Vu Input HIGH Voltage 2 0 Voc 05 V Vu Input LOW Voltage Vss 0 5 0 8 V Vou Output HIGH Voltage Lo 2 mA 2 4 V VoL Output LOW Voltage loyr 4 mA 0 4 V Vc pl Storage Capacitor Between Vcap pin and Vas 5V Rated 61 180 uF Notes 4 The HSB pin has loyr 2 uA for Voy of 2 4V when both active HIGH and LOW drivers are disabled When they are enabled standard Voy and Vo are valid This parameter is characterized but not tested 5 Vcap Storage capacitor nominal value is 68uF Document 001 44109 Rev B Page 22 of 32 Feedback e x S CYPRESS PRELIMINARY CY14B101P nd PERFORM Data Retention and Endurance Parameter Description Min Unit DATAR Data Retent
20. ARY CY14B101P Figure 14 Read RTC RDRTC Instruction Timing cs r 0 4 448 587 04 23345 657 O41 eo a 8 67 SCK Op Code SI Ao o 0 1 o o 1 1 Vo Xo Yo X o YasfAzfA1 oJ MSB LSB SO b7 oejbs p4jbsyp3 pipo MSB Data LSB WRITE RTC WRTC Instruction WRITE RTC WRTC instruction allows the user to modify the contents of RTC registers The WRTC instruction requires the WEN bit to be set to 1 before it can be issued If WEN bit is O a WREN instruction needs to be issued before using WRTC Writing RTC registers requires the following sequence After the CS line is pulled LOW to select a device WRTC opcode is trans mitted through the SI line followed by eight address bits identi fying the register which is to be written to and one or more bytes of data WRTC allows burst mode write operation When writing more than one registers in burst mode the address rolls over to 0x00 after the last RTC address OxOF is reached Note that writing to RTC timekeeping and control registers require the W bit to be set to 1 The values in these RTC registers take effect only after the W bit is cleared to 0 Write Enable bit WEN is automatically cleared to 0 after completion of the WRTC instruction Figure 15 Write RTC WRTC Instruction Timing cs r
21. CY14B101P in a system with the WP pin tied to ground and still write to the status register WP pin can be used along with WPEN and Block Protect bits BP1 and BPO of the status register to inhibit writes to memory Page 9 of 32 Feedback EE CYPRESS PERFORM When WP pin is LOW and WPEN is set to 1 any modifications to status register are disabled Therefore the memory is protected by setting the BPO and BP1 bits and the WP pin inhibits any modification of the status register bits providing hardware write protection Note WP going LOW when CS is still LOW has no effect on any of the ongoing write operations to the status register Table 6 summarizes all the protection features provided in the CY14B101P Table 6 Write Protection Operation ween WP wen Protected Unprotected Ge X X 0 Protected Protected Protected 0 X 1 Protected Writable Writable 1 LOW 1 Protected Writable Protected 1 HIGH 1 Protected Writable Writable Memory Access All memory accesses are done using the READ and WRITE instructions These instructions cannot be used while a STORE or RECALL cycle is in progress A STORE cycle in progress is indicated by the RDY bit of the status register and the HSB pin Read Sequence READ The read operations on CY14B101P are performed by giving the instruction on Serial Input pin SI and reading the output on Serial Output SO pin The following sequenc
22. D i LM C PERFORM Features 1 Mbit NonVolatile SRAM a Internally organized as 128K x 8 n STORE to QuantumTrap nonvolatile elements initiated automatically on power down AutoStore or by user using HSB pin Hardware Store or SPI instruction Software Store n RECALL to SRAM initiated on power up Power Up Recall or by SPI Instruction Software Recall a Automatic STORE on power down with a small capacitor High Reliability a Infinite Read Write and RECALL cycles a 200 000 STORE cycles to QuantumTrap a Data Retention 20 Years Real Time Clock a Full featured Real Time Clock a Watchdog timer a Clock alarm with programmable interrupts a Capacitor or battery backup for RTC a Backup current of 300 nA High Speed Serial Peripheral Interface SPI a 40 MHz Clock rate RTC Read at 25 MHz a Supports SPI Modes 0 0 0 and 3 1 1 YPRESS PRELIMINARY CY14B101P 1 Mbit 128K x 8 Serial SPI nvSRAM with Real Time Clock m Write Protection a Hardware Protection using Write Protect WP Pin a Software Protection using Write Disable Instruction a Software Block Protection for 1 4 1 2 or entire Array m Low Power Consumption a Single 3V 20 1096 operation a Average Vcc current of 10 mA at 40 MHz operation m Industry Standard Configurations a Commercial and industrial temperatures a 16 pin SOIC Package a RoHS compliant Overview The Cypress CY14B101P combines a 1 Mbit nonvolatile
23. DI STORE Cycle Duration 8 ms toene A Time Allowed to Complete SRAM Cycle 25 ns VswitcH Low Voltage Trigger Level 2 65 V tvccRISE VCC Rise Time 150 US Vips HSB Output Driver Disable Voltage 1 9 V ti zusB HSB To Output Active Time 5 us tuHHD HSB High Active Time 500 ns Switching Waveforms Figure 27 AutoStore or Power Up RECALL HSB OUT Autostore POWER UP RECALL Read and Write Inhibited RWI POWER UP i Read and Write l BROWN POWER UP Read and Write POWER RECALL OUT RECALL DOWN AUTOSTORE AUTOSTORE Notes 8 tra starts from the time Voc rises above Vswirch 9 If an SRAM write has not taken place since the last nonvolatile cycle no AutoStore or Hardware Store takes place 10 On a Hardware Store Software Store Recall AutoStore Enable Disable and AutoStore initiation SRAM operation continues to be enabled for time tper Ay Read and Write cycles are ignored during STORE RECALL and while VCC is below Vewitcu 11 HSB pin is driven HIGH to VCC only by internal 100kOhm resistor HSB driver is disabled Document 001 44109 Rev B Page 26 of 32 Feedback CYPRESS Fie PERFORM Software Controlled STORE RECALL Cycles Description Figure 28 Software STORE Cyclel PRELIMINARY CY14B101P Unit CY14B101P Max 200 US us Min 100 Parameter tRECALL 11 13 tss
24. E 0 0 0 10s Months Months 01 12 Months 0x0D 0 0 10s Day of Month Day Of Month Day of Month 01 31 0x0C 0 0 0 0 0 Day of week Day of week 01 07 0x0B 0 0 10s Hours Hours Hours 00 23 0x0A 0 10s Minutes Minutes Minutes 00 59 0x09 0 10s Seconds Seconds Seconds 00 59 0x08 OSCEN 0 Cal Sign Calibration 00000 Calibration Values DI 0 0 0x07 WDS 0 WDW 0 WDT 000000 Watchdog El 0x06 WIE 0 AIE 0 PFE 0 0 H L 1 P L 0 0 0 Interrupts 3 0x05 M 1 0 10s Alarm Date Alarm Day Alarm Day of Month 01 31 0x04 M 1 0 10s Alarm Hours Alarm Hours Alarm Hours 00 23 0x03 M 1 10 Alarm Minutes Alarm Minutes Alarm Minutes 00 59 0x02 M 1 10 Alarm Seconds Alarm Seconds Alarm Seconds 00 59 0x01 10s Centuries Centuries Centuries 00 99 0x00 WDF AF PF OSCF 0 CAL 0 W 0 R 0 Flags Fl Note 1 designates values shipped from the f actory 2 The unused bits of RTC registers are reserved for future use and should be set to 0 3 This is a binary value not a BCD value Document 001 44109 Rev B Page 18 of 32 Feedback CY14B101P _ gt I x EP CYPRESS PRELIMINARY PERFORM Table 10 Register Map Detail Time Keepi
25. EN Write Enable WEN indicates if the device is write enabled Setting WEN 17 enables writes and setting WEN 0 disables all write operations Bit 2 BPO Block Protect bit 0 Used for block protection For details see Table 5 on page 9 Bit 3 BP1 Block Protect bit 1 Used for block protection For details see Table 5 on page 9 Bit 7 WPEN Write Protect Enable bit Used E enabling the function of Write Protect Pin WP For details see Table 6 on page 10 Read Status Register RDSR Instruction The Read Status Register instruction provides access to the status register This instruction is used to probe the Write Enable Status of the device or the Ready status of the device RDY bit is set by the device to 1 whenever a STORE cycle is in progress The Block Protection and WPEN bits indicate the extent of protection employed This instruction is issued after the falling edge of CS using the opcode for RDSR Write Status Register WRSR Instruction The WRSR instruction enables the user to write to the Status register However this instruction cannot be used to modify bit O and bit 1 WEN and RDY The BPO and BP1 bits can be used to select one of four levels of block protection Further WPEN bit must be set to 1 to enable the use of Write Protect WP pin WRSR instruction is a write instruction and needs writes to be enabled WEN bit set to 1 using the WREN instruction before it is issued The instruction
26. PRELIMINARY CY14B101P PERFORM Table 10 Register Map Detail continued WatchDog Timer 0x07 D7 D6 D5 D4 D3 D2 D1 DO WDS WDW WDT WDS Watchdog Strobe Setting this bit to 1 reloads and restarts the watchdog timer Setting the bit to 0 has no effect The bit is cleared automatically after the watchdog timer is reset The WDS bit is write only Reading it always returns a 0 WDW Watchdog Write Enable Setting this bit to 1 disables any WRITE to the watchdog timeout value D5 DO This enables the user to set the watchdog strobe bit without disturbing the timeout value Setting this bit to O allows bits D5 DO to be written to the watchdog register when the next write cycle is complete This function is explained in more detail in Watchdog Timer on page 15 WDT Watchdog timeout selection The watchdog timer interval is selected by the 6 bit value in this register It represents a multiplier of the 32 Hz count 31 25 ms The range of timeout value is 31 25 ms a setting of 1 to 2 seconds setting of 3 Fh Setting the watchdog timer register to 0 disables the timer These bits can be written only if the WDW bit was set to 0 on a previous cycle Interrupt Status Control 0x06 D7 D6 D5 D4 D3 D2 D1 DO WIE AIE PFE 0 H L P L 0 0 WIE Watchdog Interrupt Enable When set to 1 and a watchdog timeout occurs the watchdog timer drives the INT pin and the WDF flag When set to 0 the watchdog timeout affects only the WDF flag AIE Alarm Interrupt Enable When set
27. S 7 Cypress PRELIMINARY CY14B101P Ordering Information Ordering Code Package Diagram Package Type Operating Range CY14B101P SFXCT 51 85022 16 SOIC Commercial CY14B101P SFXC 51 85022 16 SOIC CY14B101P SFXIT 51 85022 16 SOIC Industrial CY14B101P SFXI 51 85022 16 SOIC All the above parts are Pb free The above table contains advance information Contact your local Cypress sales representative for availability of these parts Part Numbering Nomenclature CY 14 B 101 P SEX CT Option T Tape amp Reel Blank Std Temperature C Commercial 0 to 70 C Pb Free Industrial 40 to 85 C Package SF 16 SOIC P Serial SPI nvSRAM with RTC Density Voltage 101 1 Mb B 3 0V nvSRAM 14 Auto Store Software Store Hardware Store Cypress Document 001 44109 Rev B Page 29 of 32 Feedback CY14B101P PRELIMINARY ES CYPRESS PERFORM Package Diagrams Figure 31 16 Pin 300 mil SOIC Package 51 85022 PIN 1 ID 8 DIMENSIONS IN INCHESEMM MIN 0 29107 391 MAX 009917 594 x REFERENCE JEDEC 119 0 394 10 007 0419110642
28. Vcap is not required it is recommended that the Vcap pin is left open Vcap pin must never be connected to GND Power Up Recall operation cannot be disabled in any case Serial Peripheral Interface SPI Overview The SPI is a four pin interface with Chip Select CS Serial Input SI Serial Output SO and Serial Clock SCK pins CY14B101P provides serial access to nvSRAM through SPI interface The SPI bus on CY14B101P can run at speeds up to 40 MHz for all instructions except RDRTC which runs at 25 MHz The SPI is a synchronous serial interface which uses clock and data pins for memory access and supports multiple devices on the data bus A device on SPI bus is activated using the Chip Select pin The relationship between chip select clock and data is dictated by the SPI mode CY14B101P supports SPI modes 0 and 3 In both these modes data is clocked into the nvSRAM on the rising edge of SCK starting from the first rising edge after CS goes active The SPI protocol is controlled by opcodes These opcodes specify the commands from the bus master to the slave device After CS is activated the first byte transferred from the bus Page 4 of 32 Feedback CY14B101P PRELIMINARY Data Transmission SI SO SPI data bus consists of two lines SI and SO for serial data The master issues instructions to the slave through the SI pin while slave responds through the SO pin Multiple slave devices communication The SI is also re
29. W bit to be set to 1 This bit defaults to 0 on power up Document 001 44109 Rev B Feedback mU ki pr s SS CYPRESS PRELIMINARY CY14B101P PERFORM Maximum Ratings Transient Voltage lt 20 ns on Any Pin to Ground Potential 2 0V to Voc 2 0V Exceeding maximum ratings may shorten the useful life of the Package Power Dissipation device These user guidelines are not tested Capability TA 25 C ENEE 1 0W Storage Temperature 65 C to 150 C Surface Mount Lead Soldering Maximum Accumulated Storage Time Temperature 3 Seconds annen enne eenen 260 C At 150 C Ambient Temperature 1000h DC Output Current 1 output at a time 1s duration 15mA At 85 C Ambient Temperature 20 Years Static Discharge Voltage annen ennn gt 2001V Ambient Temperature with per MIL STD 883 Method 3015 Power Applied nnn eenen 55 C to 150 C Latch up CGumrent nennen enneen enn nerennn gt 200 mA Supply Voltage on Vcc Relative to GND 0 5V to 4 1V Table 11 Operating Range DC Voltage Applied to Outputs Range Ambient Temperature Vcc in High Z State nnee 0 5V to Voc 0 5V Commercial 0 C to 70 C 2 7V to 3 6V Input Voltage nnn anar enen 0 5V to Voc 0 5V Industrial 40 C to 85 C 2
30. Y14B101P time keeping registers before reading clock data to prevent reading of data in transition Stopping the register updates does not affect clock accuracy The updating process is stopped by writing a 1 to the read bit R in the flags register at 0x00 and does not restart until a 0 is written to the read bit The RTC registers are read while the internal clock continues to run After a 0 is written to the read bit R all RTC registers are simultaneously updated within 20 ms Setting the Clock Setting the write bit W in the flags register at 0x00 to a 1 stops updates to the time keeping registers and enables the time to be set The correct day date and time is then written into the registers and must be in 24 hour BCD format The time written is referred to as the Base Time This value is stored in nonvol atile registers and used in the calculation of the current time Resetting the write bit to 0 transfers the values of timekeeping registers to the actual clock counters after which the clock resumes normal operation If the time written to the timekeeping registers is not in the correct BCD format each invalid nibble of the RTC registers continue counting to OxF before rolling over to OxO after which RTC resumes normal operation Note The values entered in the timekeeping alarm calibration and interrupt registers must be saved to nonvolatile memory by a STORE operation Therefo
31. ance cycles of the nonvolatile memory This enables user to perform infinite write operations A write cycle is performed through the SPI WRITE instruction The WRITE instruction is issued through the SI pin of the nvSRAM and consists of the WRITE opcode 3 bytes of address and 1 byte of data Writes to nvSRAM is done at SPI bus speed with zero cycle delay CY14B101P allows burst mode writes to be performed through SPI This enables write operations on consecutive addresses without issuing a new WRITE instruction When the last address in memory is reached in burst mode the address rolls over to 0x0000 and the device continues to write The SPI write cycle sequence is defined in the Memory Access section of SPI Protocol Description Document 001 44109 Rev B A read cycle in CY14B101P is performed at the SPI bus speed and the data is read out with zero cycle delay after the READ instruction is performed The READ instruction is issued through the SI pin of the nvSRAM and consists of the READ opcode and 3 bytes of address The data is read out on the SO pin CY14B101P allows burst mode reads to be performed through SPI This enables reads on consecutive addresses without issuing a new READ instruction When the last address in memory is reached in burst mode read the address rolls over to 0x0000 and the device continues to read The SPI read cycle sequence is defined in the Memory Access section of SPI Protocol Description STORE Op
32. bit to 0 in order to protect the device against inadvertent writes This instruction is issued following the falling edge of CS followed Document 001 44109 Rev B by opcode for WRDI instruction The WEN bit is cleared on the rising edge of CS following a WRDI instruction Figure 9 WRDI Instruction cs 1 234 5 6 7 SCK SI 000 0 o 1 0 o so Hi Z Block Protection Block protection is provided using the BPO and BP1 pins of the Status register These bits can be set using WRSR instruction and probed using the RDSR instruction The nvSRAM is divided into four array segments One quarter one half or all of the memory segments can be protected Any data within the protected segment is read only Table 5 shows the function of Block Protect bits Table 5 Block Write Protect Bits Status Register Bits Level BPI BPO Array Addresses Protected 0 0 0 None 1 1 4 0 1 0x18000 0x1FFFF 2 1 2 1 0 0x10000 0x1FFFF 3 All 1 1 0x00000 0x1FFFF Hardware Write Protection WP Pin The write protect pin WP is used to provide hardware write protection WP pin allows all normal read and write operations when held HIGH When the WP pin is brought LOW and WPEN bit is 1 all write operations to the status register are inhibited The hardware write protection function is blocked when the WPEN bit is 0 This allows the user to install the
33. calibration bits occupy the five lower order bits in the Calibration register These bits are set to represent any value between 0 and 31 in binary form Bit D5 is a sign bit where a 1 indicates positive calibration and a 0 indicates negative calibration Adding counts speeds the clock up and subtracting counts slows the clock down If a binary 1 is loaded into the register it corre sponds to an adjustment of 4 068 or 2 034 ppm offset in oscil lator error depending on the sign Calibration occurs within a 64 minute cycle The first 62 minutes in the cycle may once per minute have one second shortened by 128 or lengthened by 256 oscillator cycles If a binary 1 is loaded into the register only the first two minutes of the 64 minute cycle are modified If a binary 6 is loaded the first 12 are affected and so on Therefore each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125 829 120 actual oscillator cycles that is 4 068 or 2 034 ppm of adjustment per calibration step in the Calibration register To determine the required calibration the CAL bit in the Flags register 0x00 must be set to 1 This causes the INT pin to toggle at a nominal frequency of 512 Hz Any deviation measured from the 512 Hz indicates the degree and direction of the required correction For example a reading of 512 01024 Hz indicates a 20 ppm error Hence a decimal value of
34. commended configuration values Updated tOCS values for normal and room temperature Other changes as per new EROS Removed 8 SOIC package Added two new 8DFN packages Changed tCO parameter to 9 ns Updated data sheet template Replaced CY14B101P with CY14B101PA Changed title to CY14B101PA 1Mbit 128K x 8 Serial SPI nvSRAM with Real Time Clock Moved from Advance information to Preliminary Changed part number from CY14B101PA to CY14B101P Changed X4 X pin names to Man Xin respectively Updated Device operation and SPI peripheral interface description 2654487 02 04 2009 GVCH GSIN PYRS Updated pin description of Vcap pin Added Factory setting values for BP1 BP2 and WPEN bits Updated Real Time Clock operation description Added footnote 2 Added default values to RTC Register Map table 8 Added footnote 3 Updated flag register description in Register Map Detail table 9 Changed C1 C2 values to 21pF 21pF respectively Changed Iga value from 350 nA to 450 nA at hot temperature Changed loca from 5 mA to 10 mA Changed Vrtccap typical value from 2 4V to 3 0V Document 001 44109 Rev B Page 31 of 32 Feedback 7 Cypress PRELIMINARY CY14B101P PERFORM Sales Solutions and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices solution centers manufacturer s representatives and distributors To find the office closest to
35. counter to reload with the watchdog time out value and to be restarted As long as the user sets the WDS bit prior to the counter reaching the terminal value the interrupt and WDT flag never occur New time out values are written by setting the watchdog write bit to 0 When the WDW is 0 new writes to the watchdog time out value bits D5 DO are enabled to modify the time out value When WDW is 1 writes to bits D5 DO are ignored The WDW function enables a user to set the WDS bit without concern that the watchdog timer value is modified A logical diagram of the watchdog timer is shown in Figure 21 on page 16 Note that setting the watchdog time out value to 0 disables the watchdog function The output of the watchdog timer is the flag bit WDF that is set if the watchdog is allowed to time out If the Watchdog Interrupt Enable WIE bit in the Interrupt register is set a hardware interrupt on INT pin is also generated on watchdog timeout The flag and the hardware interrupt are both cleared when user reads the Flags registers Page 15 of 32 Feedback CYPRESS PERFORM Figure 21 Watchdog Timer Block Diagram Oscillator oe I 1 Hz 32 768 KHz 32 Hz v Counter as I WDF A Load WDS Register A b aq WDW m a Watchdog write to Register Watchdog Register Power Monitor T
36. e needs to be followed for a read operation After the CS line is pulled LOW to select a device the read opcode is transmitted through the SI line followed by three bytes of address The Most Significant address byte contains A16 in bit 0 and other bits as don t cares Address bits A15 to AO are sent in the following two address bytes After the last address bit is transmitted on the SI pin the PRELIMINARY CY14B101P data D7 DO at the specific address is shifted out on the SO line on the falling edge of SCK Any other data on SI line after the last address bit is ignored CY14B101P allows reads to be performed in bursts through SPI which can be used to read consecutive addresses without issuing a new READ instruction If only one byte is to be read the CS line must be driven HIGH after one byte of data comes out However the read sequence may be continued by holding the CS line LOW and the address is automatically incremented and data continues to shift out on SO pin When the last data memory address 0x1FFFF is reached the address rolls over to 0x0000 and the device continues to read Write Sequence WRITE The write operations on CY14B101P are performed through the Serial Input SI pin To perform a write operation CY14B101P if the device is write disabled then the device must first be write enabled through the WREN instruction When the writes are enabled WEN 1 WRITE instruction is issued after the falling edg
37. e of CS A WRITE instruction constitutes transmitting the WRITE opcode on SI line followed by 3 bytes address sequence and the data D7 DO which is to be written The Most Significant address byte contains A16 in bit O with other bits being don t cares Address bits A15 to AO are sent in the following two address bytes CY14B101P allows writes to be performed in bursts through SPI which can be used to write consecutive addresses without issuing a new WRITE instruction If only one byte is to be written the CS line must be driven HIGH after the DO LSB of data is transmitted However if more bytes are to be written CS line must be held LOW and address incremented automatically The following bytes on the SI line are treated as data bytes and written in the successive addresses When the last data memory address 0x1FFFF is reached the address rolls over to 0x0000 and the device continues to write The WEN bit is reset to 0 on completion of a WRITE sequence Figure 10 Read Instruction Timing cs r 123 45 6 7 0 1 23 4 5 6 7 20 21 22 230 1 2 3 4 5 6 7 0 sck Op Code 17 bit Address SI E o ooooi oioiokoloaugig dl YA3YA2 A1 AOY MSB LSB SO Document 001 44109 Rev B p7 bejsip4jpsJbz D1 bo MSB Data LSB Page 10
38. ed the SRAM is activated again for read and write operations Hardware Store and HSB pin Operation The HSB pin in CY14B101P is used to control and acknowledge STORE operations If no STORE RECALL is in progress this pin can be used to request a Hardware Store cycle When the HSB pin is driven LOW the CY14B101P conditionally initiates a STORE operation after tpg Ay duration An actual STORE cycle starts only if a write to the SRAM has been performed since the last STORE or RECALL cycle Reads and Writes to the memory are inhibited for tstore duration or as long as HSB pin is LOW The HSB pin also acts as an open drain driver that is internally driven LOW to indicate a busy condition when a STORE cycle initiated by any means or Power up Recall is in progress Upon completion of the STORE operation CY14B101P remains disabled until the HSB pin returns HIGH HSB pin must be left unconnected if not used RECALL Operation A RECALL operation transfers the data stored in the nonvolatile Quantum Trap elements to the SRAM In CY14B101P a RECALL may be initiated in two ways Hardware Recall initiated on power up and Software Recall initiated by a SPI RECALL instruction Internally RECALL is a two step procedure First the SRAM data is cleared Next the nonvolatile information is transferred into the SRAM cells All memory accesses are inhibited while a RECALL Document 001 44109 Rev B PRELIMINARY CY14B101P cycle is in
39. eration STORE operation transfers the data from the SRAM to the nonvolatile Quantum Trap cells The CY14B101P STOREs data to the nonvolatile cells using one of the three STORE operations AutoStore activated on device power down Software Store activated by a STORE instruction in the SPI and Hardware Store activated by the HSB During the STORE cycle an erase of the previous nonvolatile data is first performed followed by a program of the nonvolatile elements After a STORE cycle is initiated further input and output are disabled until the cycle is completed The HSB signal or the RDY bit in the Status register can be monitored by the system to detect if a STORE cycle is in progress The busy status of nvSRAM is indicated by HSB being pulled LOW or RDY bit being set to 1 To avoid unnecessary nonvolatile STOREs AutoStore and Hardware Store operations are ignored unless at least one write operation has taken place since the most recent STORE or RECALL cycle However software initiated STORE cycles are performed regardless of whether a write operation has taken place AutoStore Operation The AutoStore operation is a unique feature of nvSRAM which automatically stores the SRAM data to QuantumTrap during power down This STORE mechanism is implemented using a capacitor VcAp and enables the device to safely STORE the data in the nonvolatile memory when power goes down During normal operation the device draws current from Vcc t
40. ete its specified duration if the Flags register is read If the INT pin is used as a host reset the Flags register is not read during a reset Flags Register The Flag register has three flag bits WDF AF and PF which can be used to generate an interrupt These flags are set by the watchdog timeout alarm match or power fail monitor respec tively The processor can either poll this register or enable inter rupts to be informed when a flag is set These flags are automat ically reset once the register is read The flags register is automatically loaded with the value 0x00 on power up except for the OSCF bit See Stopping and Starting the Oscillator on page 14 Page 16 of 32 Feedback o EE ees Soe Ed Z PERFORM Accessing the Real Time Clock through SPI CY14B101P uses 16 registers for Real Time Clock RTC These registers can be read out or written to by accessing all 16 registers in burst mode or accessing each register one at a time The RDRTC and WRTC instructions are used to access the RTC All the RTC registers can be read in burst mode by issuing the RDRTO instruction and and reading all 16 bytes without bringing the CS pin HIGH The R bit must be set while reading the RTC CYPRESS PRELIMINARY CY14B101P timekeeping registers to ensure that transitional values of time are not read Writes to the RTC register are performed using the WRTC instruction Writing RTC timekeeping reg
41. ferred to as MOSI Master Out Slave In and SO is referred to as MISO Master In Slave Out wn Sna x y9 CYPRESS PERFORM master is the opcode Following the opcode any addresses and data are then transferred The CS must go inactive after an operation is complete and before a new opcode can be issued The commonly used terms used in SPI protocol are given below The SPI Master device controls the operations on a SPI bus An may share the SI and SO lines as described earlier CY14B101P has two separate pins for SI and SO which can be connected with the master as shown in Figure 3 on page 6 Most Significant Bit MSB The SPI protocol requires that the first bit to be transmitted is the Most Significant Bit MSB This is valid for both address and data transmission CY14B101P requires a 3 byte address for any read or write operation However since the actual address is only 17 bits it implies that the first seven bits which are fed in are ignored by the device Although these seven bits are don t care Cypress recommends that these bits are treated as Os to enable SPI bus may have only one master with one or more slave seamless transition to higher memory densities devices All the slaves share the same SPI bus lines and master SPI Master may select any of the slave devices using the Chip Select pin slave device by pulling the CS pin of the slave LOW The master All the operations must be initiated by
42. he CY14B101P provides a power management scheme with power fail interrupt capability It also controls the internal switch to backup power for the clock and protects the memory from low Vee access The power monitor is based on an internal band gap reference circuit that compares the Vcc voltage to VswircH threshold As described in the section AutoStore Operation on page 3 when Vewitcu is reached as Vcc decays from power loss a data store operation is initiated from SRAM to the nonvolatile elements securing the last SRAM data state Power is also switched from Vcc to the backup supply battery or capacitor to operate the RTC oscillator When operating from the backup source read and write opera tions to nvSRAM are inhibited and the clock functions are not available to the user The clock continues to operate in the background The updated clock data is available to the user turecaLL delay after Vcc is restored to the device see AutoStore or Power Up RECALL on page 26 Interrupts The CY14B101P has a Flags register Interrupt register and Interrupt logic that can signal interrupt to the microcontroller There are three potential sources for interrupt watchdog timer power monitor and alarm timer Each of these can be individually enabled to drive the INT pin by appropriate setting in the Interrupt register 0x06 In addition each has an associated flag bit in the Flags register 0x00 that the host processor uses to determi
43. her SPI devices Status Register CY14B101P has an 8 bit status register The bits in the status described in the Table 4 on page 8 register are used to configure the SPI bus These bits are slave device only while the CS pin is LOW device is not selected data through the SI pin is ignored and the serial output pin SO remains in a high impedance state Note A new instruction must begin with the falling edge of Chip Select CS Therefore only one opcode can be issued for each active Chip Select cycle Serial Clock SCK Serial clock is generated by the SPI master_and the communi cation is synchronized with this clock after CS goes LOW CY14B101P allows SPI modes 0 and 3 for data communication In both these modes the inputs are latched by the slave device on the rising edge of SCK and outputs are issued on the falling edge Therefore the first rising edge of SCK signifies the arrival of first bit MSB of SPI instruction on the SI pin Further all data Page 5 of 32 Feedback inputs and outputs are synchronized with SCK Document 001 44109 Rev B ie X l CYPRESS PRELIMINARY CY14B101P PERFORM Figure 3 System Configuration Using SPI nvSRAM SCK MOSI 8 SCK SI so SCK SI SO uController CY14B101P CY14B101P Cs HOLD CS HOLD HOLD1 C82 HOLD2 SPI Modes The two SPI modes are shown in Figure 4 and Figure 5 The
44. ile bits and remain unchanged from the previous power down Before selecting and issuing instructions to the memory a valid and stable Vcc voltage must be applied This voltage must remain valid until the end of the transmission of the instruction Power Down At power down continuous decay of Voc when Vcc drops from the normal operating voltage and below the Vswitcu threshold voltage the device stops responding to any instruction sent to it If a write cycle is in progress during power down it is allowed tpeLay time to complete after Vcc transitions below Vswitcu After this all memory accesses are inhibited and a conditional AutoStore operation is performed AutoStore is not performed if no writes have happened since last RECALL cycle This feature prevents inadvertent writes to nvSRAM from happening during power down However to avoid the possibility of inadvertent writes during power down ensure that the device is deselected and is in Standby Power Mode and the Chip Select CS follows the voltage applied on Vcc Document 001 44109 Rev B PRELIMINARY CY14B101P Active Power and Standby Power Modes When Chip Select CS is LOW the device is selected and is in the Active Power mode The device consumes lec current as specified in DC Electrical Characteristics on page 22 When Chip Select CS is HIGH the device is deselected and the device goes into the Standby Power mode if a STORE or RECALL cycle is not
45. ion 20 Years NVc Nonvolatile STORE Operations 200 K Capacitance Parameter Description Test Conditions Max Unit Cin Input Capacitance TA 25 C f 1MHz 6 pF Cour Output Pin Capacitance Voc 30V 8 pF Thermal Resistance Parameter Description Test Conditions 16 SOIC Unit Oja Thermal Resistance Test conditions follow standard test methods TBD C W Junction to Ambient and procedures for measuring thermal Oo Thermal Resistance impedance per EIA JESD51 TBD C W Junction to Case Figure 24 AC Test Loads and Waveforms 5770 5770 3 0V 3 0V R1 R1 OUTPUT OUTPUT 30 pF R2 5 pF R2 7890 7890 AC Test Conditions Input Pulse Levels AAA OV to 3V Input Rise and Fall Times 10 90 lt 3 ns Input and Output Timing Reference Levels 1 5V Note 6 These parameters are guaranteed by design and are not tested Document 001 44109 Rev B Page 23 of 32 Feedback ss SS CYPRESS PRELIMINARY CY14B101P PERFORM Table 12 RTC Characteristics Parameters Description Test Conditions Min Typ Max Units Lag RTC Backup Current Room Temperature 259C 300 nA Hot Temperature 859C 450 nA VRTCbat RTC Battery Pin Voltage 1 8 3 0 3 3 V VRTCcap RTC Capacitor Pin Voltage 1 5 3 0 3 6 V tocs RTC Oscillator Time to Start 1 2 Sec AC Switching Charac
46. isters and control registers except for the flag register needs the W bit of the flag register to be set to 1 The internal counters are updated with the new date and time setting when the W bit is cleared to 0 All the RTC registers can also be written in burst mode using the WRTC instruction Figure 22 RTC Recommended Component Configuration Recommended Values Y1 32 768KHz C4 21pF CIR C5 21pF gt C275 Note The recommended values for C1 and C2 include board trace capacitance Figure 23 Interrupt Block Diagram WDF Watchd Se Da WDF Watchdog Timer Flag WIE WIE Watchdog Interrupt P L Vec Enable PF d PF Power Fail Flag Power A l id PFE Power Fail Enable Monitor EN d INT AF Alarm Fla PFE E Jo Driver 9 p AIE Alarm Interrupt Enable VINT d P L Pulse Level Vss H L High Low AF Clock Alarm AIE ID en Document 001 44109 Rev B Page 17 of 32 Feedback Ar cypress PERFORM Table 9 RTC Register Map 2 PRELIMINARY CY14B101P Register E Function Range D7 D6 D5 DA D3 D2 D1 DO OxOF 10s Years Years Years 00 99 OxO
47. nd 3 CPOL CPHA 0 0 amp 1 1 and operates as SPI slave The device is enabled using the Chip Select pin CS and accessed through Serial Input SI Serial Output SO and Serial Clock SCK pins CY14B101P provides the feature for hardware and software write protection through WP pin and WRDI instruction CY14B101P also provides mechanisms for block write protection 1 4 1 2 or full array using BPO and BP1 pins in the status register Further the HOLD pin is used to suspend any serial communication without resetting the serial sequence CY14B101P uses the standard SPI opcodes for memory access In addition to the general SPI instructions for read and write CY14B101P provides four special instructions that allow access to four nvSRAM specific functions STORE RECALL AutoStore Disable ASDISB and AutoStore Enable ASENB The major benefit of nvSRAM SPI over serial EEPROMs is that all reads and writes to nvSRAM are performed at the speed of SPI bus with zero cycle delay Therefore no wait time is required after any of the memory accesses The STORE and RECALL operations need finite time to complete and all memory accesses are inhibited during this time While a STORE or RECALL operation is in progress the busy status of the device is indicated by the Hardware Store Busy HSB pin and also reflected on the RDY bit of the Status Register SRAM Write All writes to nvSRAM are carried out on the SRAM and do not use up any endur
48. ne the cause of the interrupt The INT pin driver has two bits that specify its behavior when an interrupt occurs An Interrupt is raised only if both a flag is raised by one of the three sources and the respective interrupt enable bit in Interrupts register is enabled set to 1 After an interrupt source is active two programmable bits H L and P L determine the behavior of the output pin driver on INT pin These two bits are located in the Document 001 44109 Rev B PRELIMINARY CY14B101P Interrupt register and can be used to drive level or pulse mode output from the INT pin In pulse mode the pulse width is internally fixed at approximately 200 ms This mode is intended to reset a host microcontroller In the level mode the pin goes to its active polarity until the Flags register is read by the user This mode is used as an interrupt to a host microcontroller The control bits are summarized in the following section Interrupts are only generated while working on normal power and are not triggered when system is running in backup power mode Note CY14B101P generates valid interrupts only after the Powerup Recall sequence is completed All events on INT pin must be ignored for te duration after powerup Interrupt Register Watchdog Interrupt Enable WIE When set to 1 the watchdog timer drives the INT pin and an internal flag when a watchdog time out occurs When WIE is set to 0 the watchdog timer o
49. ng Years D7 D6 D5 DA D3 D2 D1 DO OxOF 10s Years Years Contains the lower two BCD digits of the year Lower nibble four bits contains the value for years upper nibble four bits contains the value for 10s of years Each nibble operates from 0 to 9 The range for the register is 0 99 Time Keeping Months D7 D6 D5 DA D3 D2 D1 DO Ox0E 0 0 0 10s Month Months Contains the BCD digits of the month Lower nibble four bits contains the lower digit and operates from 0 to 9 upper nibble one bit contains the upper digit and operates from 0 to 1 The range for the register is 1 12 Time Keeping Date D7 D6 D5 DA D3 D2 D1 DO 0x0D 0 0 10s Day of Month Day of Month Contains the BCD digits for the date of the month Lower nibble four bits contains the lower digit and operates from 0 to 9 upper nibble two bits contains the 10s digit and operates from 0 to 3 The range for the register is 1 31 Leap years are automatically adjusted for Time Keeping Day D7 D6 D5 D4 D3 D2 D1 DO 0x0C 0 0 0 0 0 Day of Week Lower nibble three bits contains a value that correlates to day of the week Day of the week is a ring counter that counts from 1 to 7 then returns to 1 The user must assign meaning to the day value because the day is not integrated with the date Time Keeping Hours D7 D6 D5 D4 D3 D2 D1 DO 0x0B 0 0 10s Hours Hours Contains the BCD value of hours in 24 hour format Lower nibble four bits contains the lower digit and operates from 0 to 9 u
50. nly affects the WDF flag in Flags register Alarm Interrupt Enable AIE When set to 1 the alarm match drives the INT pin and an internal flag When AIE is set to 0 the alarm match only affects the AF flag in Flags register Power Fail Interrupt Enable PFE When set to 1 the power fail monitor drives the pin and an internal flag When PFE is set to 0 the power fail monitor only affects the PF flag in Flags register High Low H L When set to a 1 the INT pin is active HIGH and the driver mode is push pull The INT pin drives high only when Vee is greater than Vewitcy When set to a 0 the INT pin is active LOW and the drive mode is open drain The INT pin must be pulled up to Vcc by a 10k resistor while using the interrupt in active LOW mode Pulse Level P L When set to a 1 and an interrupt occurs the INT pin is driven for approximately 200 ms When P L is set to a 0 the INT pin is driven high or low determined by H L until the Flags or Control register is read When an enabled interrupt source activates the INT pin an external host reads the Flags registers to determine the cause Remember that all flags are cleared when the register is read If the INT pin is programmed for Level mode then the condition clears and the INT pin returns to its inactive state If the pin is programmed for Pulse mode then reading the flag also clears the flag and the pin The pulse does not compl
51. nly from the battery when the primary power is removed However the battery is not recharged at any time by the CY14B101P The battery capacity must be chosen for total anticipated cumulative down time required over the life of the system Stopping and Starting the Oscillator The OSCEN bit in the calibration register at 0x08 controls the enable and disable of the oscillator This bit is nonvolatile and is shipped to customers in the enabled set to 0 state To preserve the battery life when the system is in storage OSCEN must be set to 1 This turns off the oscillator circuit extending the battery life If the OSCEN bit goes from disabled to enabled it takes approximately one second two seconds maximum for the oscillator to start While system power is off If the voltage on the backup supply Vrrceap Of VRTCbat falls below their respective minimum level the oscillator may fail The CY14B101P has the ability to detect oscillator failure when system power is restored This is recorded in the OSCF Oscillator Failed bit of the flags register at the address 0x00 When the device is powered on Vcc goes above Vswitcu the OSCEN bit is checked for enabled status If the OSCEN bit is enabled and the oscillator is not active within the first 5 ms the OSCF bit is set to 1 The system must check for this condition and then write 0 to clear the flag Note that in addition to setting the OSCF flag bit the time registers
52. o charge the capacitor connected to the Vcap pin When the voltage on the Vcc pin drops below Vswitcy during power down the device inhibits all memory accesses to nvSRAM and automatically performs a conditional STORE operation using the charge from the Vcap capacitor The AutoStore operation is not initiated if no write cycle has been performed since last RECALL During power down the memory accesses are inhibited after the voltage on Vcc pin drops below Vswitcy To avoid inadvertent writes ensure that CS is not left floating prior to this event Therefore during power down the device must be deselected and CS must be allowed to follow Vcc Figure 2 shows the proper connection of the storage capacitor Vcap for AutoStore operation Refer to DC Electrical Charac teristics on page 22 for the size of the Vcap Page 3 of 32 Feedback Figure 2 AutoStore Mode Vcc e 7 0 1uF Vcc 10kOhm CAP CAP Software Store Operation Software Store allows the user to trigger a STORE operation through a special SPI instruction This operation is initiated irrespective of whether a write has been performed since last nv operation A STORE cycle takes tstore time to complete during which all the memory accesses to nvSRAM are inhibited The RDY bit of the Status register or the HSB pin may be polled to find the Ready Busy status of the nvSRAM After the tstore cycle time is complet
53. on and Vcc crosses Vswitch voltage During this time the Chip Select CS must be enabled to follow the Vcc voltage Therefore CS must be connected to Vcc through a suitable pull up resistor As a built in safety feature Chip Select CS is both edge sensitive and level sensitive After power up the device is not selected until a falling edge is detected on Chip Select CS This ensures that Chip Select CS must have been HIGH before going Low to start the first operation As described earlier nvSRAM performs a Power Up Recall operation after power up and therefore all memory accesses are disabled for tagcA duration after power up The HSB pin can be probed to check the ready busy status of nvSRAM after power up Power On Reset A Power On Reset POR circuit is included to prevent inadvertent writes At power up the device does not respond to any instruction until the Voc reaches the Power On Reset threshold voltage VswircH After Vcc transitions the POR threshold the device is internally reset and performs a Power Up Recall operation The device is in the following state after POR m Deselected after Power up a falling edge is required on Chip Select CS before any instructions are started m Standby Power mode m Not in the Hold Condition m Status register state a Write Enable WEN bit is reset to 0 a WPEN BP1 BPO unchanged from previous power down The WPEN BP1 and BPO bits of the Status Register are nonvol at
54. pper nibble two bits contains the upper digit and operates from 0 to 2 The range for the register is 0 23 Time Keeping Minutes D7 D6 D5 DA D3 D2 D1 DO 0x0A 0 10s Minutes Minutes Contains the BCD value of minutes Lower nibble four bits contains the lower digit and operates from 0 to 9 upper nibble three bits contains the upper minutes digit and operates from 0 to 5 The range for the register is 0 59 Time Keeping Seconds D7 D6 D5 D4 D3 D2 D1 DO 0x09 10s Seconds Seconds Contains the BCD value of seconds Lower nibble four bits contains the lower digit and operates from 0 to 9 upper nibble three bits contains the upper digit and operates from 0 to 5 The range for the register is 0 59 Calibration Control 0X08 D7 D6 D5 DA D3 D2 D1 DO OSCEN 0 Calibration Calibration Sign OSCEN Oscillator Enable When set to 1 the oscillator is stopped When set to 0 the oscillator runs Disabling the oscillator saves battery or capacitor power during storage eg Determines if the calibration adjustment is applied as an addition 1 to or as a subtraction 0 from the time base ign Calibration These five bits control the calibration of the clock Page 19 of 32 Document 001 44109 Rev B Feedback Nn pra SS CYPRESS
55. re while working in AutoStore disabled mode perform a STORE operation after writing into the RTC registers for the modifications to be correctly recorded Document 001 44109 Rev B PRELIMINARY CY14B101P Backup Power The RTC in the CY14B101P is intended for permanently powered operation The Vatccap OF Vrrepat pin is connected depending on whether a capacitor or battery is chosen for the application When the primary power Vcc fails and drops below Vswitcu the device switches to the backup power supply The clock oscillator uses very little current which maximizes the backup time available from the backup source Regardless of the clock operation with the primary source removed the data stored in the nvSRAM is secure having been stored in the nonvolatile elements when power was lost During backup operation the CY14B101P consumes a maximum of 300 nanoamps at room temperature The user must choose capacitor or battery values according to the application Backup time values based on maximum current specifications are shown in the following table Nominal backup times are approximately two times longer Table 8 RTC Backup Time Capacitor Value Backup Time 0 1F 72 hours 0 47F 14 days 1 0F 30 days Using a capacitor has the obvious advantage of recharging the backup source each time the system is powered up If a battery is used a 3V lithium is recommended and the CY14B101P sources current o
56. rite enabled WEN 1 The instruction is performed by transmitting the ASENB opcode on the SI pin following the falling edge of CS The WEN Document 001 44109 Rev B PRELIMINARY CY14B101P bit is cleared on the positive edge of CS following the ASENB instruction Figure 19 AutoStore Enable Operation C a 0412345 6 7 SCH UI sl bo 1No 1 1 o 0 1 so Hi Z HOLD Pin Operation The HOLD pin is used to pause the serial communication When the device is selected and a serial sequence is underway HOLD is used to pause the serial communication with the master device without resetting the ongoing serial sequence To pause the HOLD pin must be brought LOW when the SCK pin is LOW To resume serial communication the HOLD pin must be brought HIGH when the SCK pin is LOW SCK may toggle during HOLD While the device serial communication is paused inputs to the SI pin are ignored and the SO pin is in the high impedance state This pin can be used by the master with the CS pin to pause the serial communication by bringing the pin HOLD LOW and deselecting an SPI slave to establish communication with another slave device without the serial communication being reset The communication may be resumed at a later point by selecting the device and setting the HOLD pin HIGH Figure 20 HOLD Operation AA La Page 13 of 32
57. rotected by and subject to worldwide patent protection United States and foreign United States copyright laws and international treaty provisions Cypress hereby grants to licensee a personal non exclusive non transferable license to copy use modify create derivative works of and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement Any reproduction modification translation compilation or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Cypress reserves the right to make changes without further notice to the materials described herein Cypress does not assume any liability arising out of the application or use of any product or circuit described herein Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress product in a life support systems application implies that the manufacturer assumes all risk of s
58. ruction is executed CY14B101P performs a Software Recall operation To issue this instruction the device must be write enabled WEN 1 The instruction is performed by transmitting the RECALL opcode on the SI pin following the falling edge of CS The WEN bit is cleared on the positive edge of CS following the RECALL instruction Figure 17 Software RECALL Operation es 0 12 3 4 5 6 7 p SCK SI 40 1 1X0 0 00 0 so Hi Z AutoStore Disable ASDISB AutoStore is enabled by default in CY14B101P The AutoStore Disable instruction disables the AutoStore on CY14B101P This setting is not nonvolatile and needs to be followed by a STORE sequence if this is desired to survive power cycle To issue this instruction the device must be write enabled WEN 1 The instruction is performed by transmitting the ASDISB opcode on the SI pin following the falling edge of CS The WEN bit is cleared on the positive edge of CS following the ASDISB instruction Figure 18 AutoStore Disable Operation c8 SCK SI 00 0 1 1 o 0 1Y so Hi Z AutoStore Enable ASENB The AutoStore Enable instruction enables the AutoStore on CY14B101P This setting is not nonvolatile and needs to be followed by a STORE sequence if this is desired to survive power cycle To issue this instruction the device must be w
59. s read or on power up PF D6 by the user It is cleared to 0 when the Flags register is read or on power up Power Fail Flag This read only bit is set to 1 when power falls below the power fail threshold Vswitcu It is cleared to 0 when the Flags register is read or on power up Oscillator Fail Flag Set to 1 on power up if the oscillator is enabled and not running in the first 5 ms of operation This indicates that RTC backup power failed and clock value is no longer valid This bit survives power cycle and is never OSCF CAL cleared internally by the chip The user must check for this condition and write O to clear this flag Calibration Mode When set to 1 a 512 Hz square wave is output on the INT pin When set to 0 the INT pin resumes normal operation This bit defaults to O disabled on power up Write Enable Setting the W bit to 1 freezes updates of the RTC registers The user can then write to RTC registers Alarm registers Calibration register Interrupt register and Flags register Setting the W bit to 0 causes the contents of the RTC registers to be transferred to the time keeping counters if the time has been changed a new base time is loaded This bit defaults to 0 on power up Read Enable Setting R bit to 1 stops clock updates to user RTC registers so that clock updates are not seen during the reading process Set R bit to 0 to resume clock updates to the holding register Setting this bit does not require
60. t 0x00 indicates that a date or time match has occurred The AF bit is set to 1 when a match occurs Reading the flags register clears the alarm flag bit and all others A hardware interrupt pin may also be used to detect an alarm event To set clear or enable an alarm set the W bit in Flags Register 0x00 to 1 to enable writes to Alarm Registers After writing the alarm value clear the W bit back to 0 for the changes to take effect Note CY14B101P requires the alarm match bit for seconds 0x02 D7 to be set to 0 for proper operation of Alarm Flag and Interrupt Watchdog Timer The Watchdog Timer is a free running down counter that uses the 32 Hz clock 31 25 ms derived from the crystal oscillator The oscillator must be running for the watchdog to function It begins counting down from the value loaded in the Watchdog Timer register The timer consists of a loadable register and a free running counter On power up the watchdog time out value in register 0x07 is loaded into the Counter Load register Counting begins on power up and restarts from the loadable value any time the Watchdog Strobe WDS bit is set to 1 The counter is compared to the terminal value of 0 If the counter reaches this value it causes an internal flag and an optional interrupt output You can prevent the time out interrupt by setting WDS bit to 1 prior to the counter reaching 0 This causes the
61. t unconnected if Vatccap is used Xout Output Crystal Output connection Drives crystal on start up Xin Input Crystal Input connection For 32 768 kHz crystal INT Output Interrupt Output Programmable to respond to the clock alarm the watchdog timer and the power monitor Also programmable to either active HIGH push or pull or LOW open drain NC No Connect No Connect This pin is not connected to the die GND Power Supply Ground Vee Power Supply Power Supply 2 7 3 6V Document 001 44109 Rev B Page 2 of 32 EE CYPRESS PRELIMINARY CY14B101P Device Operation SRAM Read CY14B101P is a 1 Mbit nvSRAM memory with integrated RTC and SPI interface All the reads and writes to nvSRAM happen to the SRAM which gives nvSRAM the unique capability to handle infinite writes to the memory The data in SRAM is secured by a STORE sequence that transfers the data in parallel to the nonvolatile Quantum Trap cells A small capacitor VcAp is used to AutoStore the SRAM data in nonvolatile cells when power goes down providing power down data security The Quantum Trap nonvolatile elements built in the reliable SONOS technology make nvSRAM the ideal choice for secure data storage In CY14B101P the 1 Mbit memory array is organized as 128K words x 8 bits The memory is accessed through a standard SPI interface that enables very high clock speeds upto 40 MHz with zero delay read and write cycles CY14B101P supports SPI modes 0 a
62. teristics 25 MHz e peso Alt Parameter Description ENE RDRTC Instruction Unit Min Max Min Max fsck fsck Clock Frequency SCK 40 25 MHz teL twL Clock Pulse Width LOW 11 18 ns icu twH Clock Pulse Width HIGH 11 18 ns tes tcE CS HIGH Time 20 20 ns tess tces CS Setup Time 10 10 ns lcsH lcEH CS Hold Time 10 10 ns tsp tsu Data In Setup Time 5 5 ns tup ty Data In Hold Time 5 5 ns tun tup HOLD Hold Time 5 5 ns tsH tcp HOLD Setup Time 5 5 ns tco ty Output Valid 9 15 ns tHHZ luz HOLD to Output HIGH Z 15 15 ns tHiz liz HOLD to Output LOW Z 15 15 ns tou tuo Output Hold Time 0 0 ns tuzcs Ins Output Disable Time 25 25 ns Notes 7 Current drawn from either Vatccap or Vatcbat When Voc lt VswrrcH Document 001 44109 Rev B Page 24 of 32 Feedback CY14B101P a Sn sE L CYPRESS PRELIMINARY We PER FO RM Figure 25 Synchronous Data Timing Mode 0 ICS cs t oss tcsH SCK tsp SI VALID IN t t oH IHzcs HI Z so HI Z Figure 26 HOLD Timing SCK t HH SH HOLD l tHHZ tHLZ SO Page 25 of 32 Feedback Document 001 44109 Rev B F CYPRESS PRELIMINARY CY14B101P PERFORM AutoStore or Power Up RECALL e CY14B101P Parameters Description Min Max Unit tra l Power Up RECALL Duration 20 ms tstore
63. tes value M Match When this bit is set to 0 the minutes value is used in the alarm match Setting this bit to 1 causes the match circuit to ignore the minutes value Document 001 44109 Rev B Page 20 of 32 Feedback D6 PRELIMINARY 10s Alarm Seconds D3 R CY14B101P DO D1 D2 Alarm Seconds Alarm Seconds D3 DO D4 D1 D2 Centuries DO D1 Time Keeping Centuries WwW D4 D7 Table 10 Register Map Detail continued D2 M 0x02 D5 Contains the alarm value for the seconds and the mask bit to select or deselect the seconds value Match When this bit is set to 0 the seconds value is used in the alarm match Setting this bit to 1 causes the match circuit to ignore the seconds value D5 Flags D3 0 D4 D5 Contains the BCD value of centuries Lower nibble contains the lower digit and operates from 0 to 9 upper nibble CAL D6 10s Centuries contains the upper digit and operates from 0 to 9 The range for the register is 0 99 centuries AF WDF OSCF Watchdog Timer Flag This read only bit is set to 1 when the watchdog timer is allowed to reach 0 without being reset PF Alarm Flag This read only bit is set to 1 when the time and date match the values stored in the alarm registers with the match bits 0 It is cleared when the Flags register i
64. the master activating a also generates the Serial Clock SCK and all the data trans After the slave device is selected with CS going LOW the first byte received is treated as the opcode for the intended operation CY14B101P uses the standard opcodes for memory accesses Serial Opcode In addition to the memory accesses CY14B101P provides additional opcodes for the nvSRAM specific functions STORE mission on SI and SO lines are synchronized with this clock RECALL AutoStore Enable and AutoStore Disable Refer to SPI Slave communication on the SPI bus and acts on the instruction from Table 2 on page 7 for details on opcodes SPI slave device is activated by the master through the Chip Select line A slave device gets the Serial Clock SCK as an input from the SPI master and all the communication is If an invalid op code is received the op code is ignored and the device ignores any additional serial data on the SI pin and no valid data is sent out on the SO pin Opcode for a new instruction synchronized with this clock SPI slave never initiates a Invalid Opcode is recognized only after the next falling edge of CS the master For selecting any slave device the master needs to pull down CY14B101P operates as a slave device and may share the SPI Chip Select CS the corresponding CS pin Any instruction can be issued to a The CY14B101P is selected when the CS pin is LOW When the bus with multiple CY14B101P devices or ot
65. uch use and in doing so indemnifies Cypress against all charges Use may be limited by and subject to the applicable Cypress software license agreement Document 001 44109 Rev B Revised February 2 2009 Page 32 of 32 AutoStore and QuantumTrap are registered trademarks of Cypress Semiconductor Corporation All products and company names mentioned in this document are the trademarks of their respective holders Feedback

Cypress CY14B101P User's Manual

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