Cypress CY14B101LA User's Manual
Contents
1. SEATING PLANE 0 406 0 0160 0 597 0 08355 DETAIL A 51 85061 C Document 001 42879 Rev Page 22 of 25 Feedback PRELIMINARY CY14B101LA CY14B101NA PERFORM Package Diagrams continued Figure 19 32 Pin SOIC 51 85127 PIN 1 ID 0292 7416 DIMENSIONS IN INCHES MM MIN 0 2997 594 0 405110 287 REFERENCE JEDEC MO 119 041910642 PART 2 5323 STANDARD PKG 17 32 5232 3 FREE PKG SEATING PLANE 0 810 20 574 0 822 20 878 0 090 2 286 0 100 2 540 C3 0 004 0 101 NE d 01006 0 152 0 02605601 0 02110533 0 041 041 i 0 050 1 270 003204121 0 004101011 0 0100 0 254 51 85127 0 014 0 355 0 020 0 508 Document 001 42879 Rev Page 23 of 25 Feedback Document History PERFORM PRELIMINARY CY14B101LA CY14B101NA Document Title CY14B101LA CY14B101NA 1 Mbit 128K x 8 64K x 16 nvSRAM Document Number 001 42879 ECN No Submission Date Orig of Change Description of Change 2050747 See ECN UNC PYRS New Data Sheet 2607447 11 14 2008 GVCH AESA Removed 15 ns access speed Updated Features Updated Logic block diagram Added footnote 12 32. 1 A T 3 p 4 18 jp t F F 2 R OOOOOO G H t ooo A A 1 875 zi B 4 6 00 0 10 0 75 3 75 B 6 0 0 10 3 y c 015 4 X 3 lt NZ X XZ SEATING PLANE Pod E s 51 85128 D Document 001 42879 Rev B Page 21 of 25 Feedback CYPRESS PRELIMINARY CY14B101LA CY14B101NA PERFORM Package Diagrams continued Figure 18 48 Pin SSOP 51 85061 DIMENSION IN MM MIN MAX 0180 lt 0 0047 0 210 0 0083 22 313 0 8782 DETAIL A 88517 0 886 PIN 1 LD 27 L d TN 0058 0 396 10 868 0 4045 11735 0 462 11 938 0 4705 1735 0462 11 938 0 4705 155 4 28 54 21 lh 092 0 03742 105 0 04135 R 012 0 005 MINS O MIN B 01 0005 25 0 0105 0 300 0018 025 0 800 5 0206606 GAUGE PLANE 120 lt 0 0472MAX3 f X904 0 050 0 0080 1 04 5 22 313 0 8785 0150 0 0059 22 517 0 88965
3. Pin definition Updated WE HSB and NC pin description Page 4 Updated SRAM READ SRAM WRITE Autostore operation description Updated Figure 4 Page 4 Updated Hardware store operation and Hardware RECALL Power up description Page 4 Updated Software store and software recall description Footnote 1 and 11 referenced for Mode selection Table Added footnote 11 Updated footnote 9 and 10 Page 6 updated Data protection description Maximum Ratings Added Max Accumulated storage time Changed Output short circuit current parameter name to DC output current Changed lcc2 from 6mA to 10mA Changed from 15mA to 35mA Changed lcc4 from 6mA to 5mA Changed Isp from 3mA to 5mA Added for HSB Updated Icc4 and loz Test conditions Changed voltage min value from 68uF to 61uF Added Vcap voltage max value to 180uF Updated footnote 12 and 13 Added footnote 14 Added Data retention and Endurance Table Added thermal resistance value to 48 pin FBGA and 44 TSOP packages Updated Input Rise and Fall time in AC test Conditions Referenced footnote 17 to topa parameter Updated All switching waveforms Updated footnote 17 Added footnote 20 NN I Added Figure 10 SRAM WRITE CYCLE BHE and BLE controlled Changed tstore max value from 12 5ms to 8ms Updated tpg Ay value Added Vupis tuHHD and ti zZusp parameters Updated footnote 24 Added footnote 26 and 27 Software controlled STORE RECALL T
4. LM C PERFORM Features m 20 ns 25 ns and 45 ns Access Times m Internally organized as 128K x 8 CY14B101LA or 64K x 16 CY14B101NA m Hands off Automatic STORE on power down with only a small Capacitor m STORE to QuantumTrap nonvolatile elements initiated by Software device pin or AutoStore on power down m RECALL to SRAM initiated by software or power up m Infinite Read Write and Recall Cycles m 200 000 STORE cycles to QuantumTrap m 20 year data retention m Single 20 to 10 operation m Commercial and Industrial Temperatures m 48 ball FBGA 44 pin TSOP II 48 pin SSOP and 32 pin SOIC packages m Pb free and RoHS compliance YPRESS PRELIMINARY 1 Mbit 128K x 8 64K x 16 nvSRAM CY14B101LA CY14B101NA Functional Description The Cypress CY14B101LA CY14B101NA is a fast static RAM with a nonvolatile element in each memory cell The memory is organized as 128K bytes of 8 bits each or 64K words of 16 bits each The embedded nonvolatile elements incorporate QuantumTrap technology producing the world s most reliable nonvolatile memory The SRAM provides infinite read and write cycles while independent nonvolatile data resides in the highly reliable QuantumTrap cell Data transfers from the SRAM to the nonvolatile elements the STORE operation takes place automatically at power down On power up data is restored to the SRAM the RECALL operation from the nonvolatile memory Both
5. 63996099699 6 44 9 e 808 89659 80898968 Figure 2 Pin Diagram 44 Pin TSOP II 44 TSOP Il 44 TSOP Il x8 168 3 44 TSOP Il 44 TSOP II x8 x1 6 Top View Top View not to scale not to scale Notes 4 Address expansion for 2 Mbit NC pin not connected to die 5 Address expansion for 4 Mbit NC pin not connected to die 6 Address expansion for 8 Mbit NC pin not connected to die 7 Address expansion for 16 Mbit NC pin not connected to die 8 HSB pin is not available in 44 TSOP II x16 package Document 001 42879 Rev B Page 2 of 25 Feedback CYPRESS PRELIMINARY CY14B101LA CY14B101NA 2 Aas Ay 4 We A s 48 SSOP f 32 SOIC As scis 2 Not To Scale Ag Ay 11 Ag DQ 00 DQg Da DQ DQ 15 DQ Vss E DQ Table 1 Pin Definitions Pin Name WO Type Description Apo A16 Address Inputs Used to Select one of the 131 072 bytes of the nvSRAM for x8 Configuration Ag 15 Address Inputs Used to Select one of the 65 536 words of the nvSRAM for x16 Configuration DQ Bidirectional Data I O Lines for x8 Configuration Used as input or out
6. C 2 7V to 3 6V Input Voltage 0 5V to Vcc 0 5V Industrial 40 C to 85 27V to 3 6V Transient Voltage 20 ns on Any Pin to Ground Potential 2 0 to Vcc 2 0V DC Electrical Characteristics Over the Operating Range Vcc 2 7V to 3 6V Parameter Description Test Conditions Min Max Unit Average Vcc Current tac 20 ns Commercial 65 mA tac 25 ns 65 mA tac 45 ns 50 mA Values obtained without output loads lout 9 MA Industrial 70 mA 70 mA 52 mA loca Average Vcc Current All Inputs Don t Care Max 10 mA during STORE Average current for duration tstore mm Average Vcc Currentat All I P cycling at CMOS levels 35 mA tac 200 ns 25 C Values obtained without output loads lour 0 mA typical loca Average Vcap Current All Inputs Don t Care Vcc Max 5 mA during AutoStore Cycle Average current for duration tstore Isp Vcc Standby Current CE gt Vcc 0 2V All others Viy lt 0 2V or gt Vec 0 2V Standby 5 mA current level after nonvolatile cycle is complete Inputs are static f 0 MHz m Input Leakage Current Vcc Max Vss lt Vin Vcc 1 1 5 Input Leakage Current Vcc Max Vss lt Vec 100 1 for HSB loz Off State Output Voc Vss lt Vout lt Vcc or OE gt BHE BLE gt Vi 1 1
7. CY14B101NA ZS45XC 51 85087 44 TSOP II CY14B101NA BA45XCT 51 85128 48 ball FBGA CY14B101NA BA45XC 51 85128 48 ball FBGA CY14B101LA ZS45XIT 51 85087 44 pin TSOP II Industrial CY14B101LA ZS45XI 51 85087 44 TSOP II CY14B101LA BA45XIT 51 85128 48 ball FBGA CY14B101LA BA45XI 51 85128 48 ball FBGA CY14B101LA SP45XIT 51 85061 48 pin SSOP 14 101 5 45 51 85061 48 pin SSOP CY14B101LA SZ45XIT 51 85127 32 pin SOIC CY14B101LA SZ45XI 51 85127 32 pin SOIC CY14B101NA ZS45XIT 51 85087 44 pin TSOP II 14 101 2545 51 85087 44 TSOP II CY14B101NA BA45XIT 51 85128 48 ball FBGA CY14B101NA BA45XI 51 85128 48 ball FBGA parts are Pb free The above table contains Preliminary information Please contact your local Cypress sales representative for availability of these parts Document 001 42879 Rev Page 18 of 25 Feedback PERFORM Part Numbering Nomenclature CY 14 101L A ZS 20 X C T PRELIMINARY Option T Tape amp Reel Blank Std CY14B101LA CY14B101NA Temperature C Commercial 0 to 70 C Pb Free I Industrial 40 to 85 C Speed 20 20 ns 25 25ns Package 45 45 ns Die revision A 2 g Data Bus A 4st Rev SP 48 SSOP L x8 SZ 32 SOIC N x16 De
8. 85127 32 pin SOIC CY14B101LA SZ25XC 51 85127 32 pin SOIC CY14B101NA ZS25XCT 51 85087 44 TSOP II CY14B101NA ZS25XC 51 85087 44 TSOP II CY14B101NA BA25XCT 51 85128 48 FBGA CY14B101NA BA25XC 51 85128 48 ball FBGA CY14B101LA ZS25XIT 51 85087 44 TSOP II Industrial CY14B101LA ZS25XI 51 85087 44 TSOP II CY14B101LA BA25XIT 51 85128 48 FBGA CY14B101LA BA25XI 51 85128 48 FBGA CY14B101LA SP25XIT 51 85061 48 pin SSOP CY14B101LA SP25XI 51 85061 48 pin SSOP CY14B101LA SZ25XIT 51 85127 32 pin SOIC CY14B101LA SZ25XI 51 85127 32 pin SOIC CY14B101NA ZS25XIT 51 85087 44 TSOP II CY14B101NA ZS25XI 51 85087 44 TSOP II CY14B101NA BA25XIT 51 85128 48 ball FBGA CY14B101NA BA25XI 51 85128 48 ball FBGA Document 001 42879 Rev Page 17 of 25 Feedback Z CYPRESS PRELIMINARY CY14B101LA CY14B101NA PERFORM Ordering Information continued po Ordering Code esce Package Type Ee 45 CY14B101LA ZS45XCT 51 85087 44 TSOP II Commercial CY14B101LA ZS45XC 51 85087 44 TSOP II CY14B101LA BA45XCT 51 85128 48 ball FBGA CY14B101LA BA45XC 51 85128 48 ball FBGA CY14B101LA SP45XCT 51 85061 48 pin SSOP CY14B101LA SP45XC 51 85061 48 pin SSOP CY14B101LA SZ45XCT 51 85127 32 pin SOIC CY14B101LA SZ45XC 51 85127 32 pin SOIC CY14B101NA ZS45XCT 51 85087 44 TSOP II
9. Enable to Output Active 0 0 0 ns tuzpE Byte Disable to Output Inactive 8 10 15 ns SRAM Write Cycle twc twc Write Cycle Time 20 25 45 ns tpwe twp Write Pulse Width 15 20 30 ns tscE tew Chip Enable To End of Write 15 20 30 ns tsp tow Data Setup to End of Write 8 10 15 ns tup Data Hold After End of Write 0 0 0 ns taw taw Address Setup to End of Write 15 20 30 ns tsa tas Address Setup to Start of Write 0 0 0 ns tua twR Address Hold After End of Write 0 0 0 ns tuzwell4 17 181 twz Write Enable to Output Disable 8 10 15 ns ia tow Output Active after End of Write 3 3 3 ns taw Enable to End of Write 15 20 30 ns Switching Waveforms Figure 6 SRAM Read Cycle 1 Address Controlled 15 16 191 t Address Address Valid X Data Output Previous Data Valid Output Data Valid Notes 15 WE must be HIGH during SRAM read cycles 16 Device is continuously selected with CE OE and BHE BLE LOW 17 Measured 200 mV from steady state output voltage 18 If WE is low when CE goes low the outputs remain in the high impedance state 19 HSB must remain HIGH during READ and WRITE cycles Document 001 42879 Rev B Page 9 of 25 Feedback ZZ PRELIMINARY CY14B101LA CY14B101NA PERFORM Figure 7 SRAM Read Cycle 2 CE and OE Controlled 15 19 Address Address Valid BHE BLE High Impedance Data Output leg Standby Figure 8 SR
10. Low Voltage Trigger Level 2 65 2 65 2 65 V tVCCRISE VCC Rise Time 150 150 150 us Vppis HSB Output Driver Disable Voltage 1 9 1 9 1 9 V ti zusB HSB To Output Active Time 5 5 5 HS tHHHD HSB High Active Time 500 500 500 ns Switching Waveforms Notes Figure 11 AutoStore or Power Up RECALLPI Vinsa m ea s m Vg ccRISE Note terre gt Note sronE Note26 HSB OUT cee t DELAY lt t 4 Autostore 2 499 ELA POWER UP RECALL lt tHRECALL Read amp Write Inhibited RWI POWER UP Read amp Write BROWN jPOWER UP Read amp Write RECALL OUT RECALL DOWN Autostore Autostore 22 tHREcALL Starts from the time Vcc rises above 23 If an SRAM write has not taken place since the last nonvolatile cycle no AutoStore or Hardware STORE takes place 24 On a Hardware STORE Software STORE Recall AutoStore Enable Disable and AutoStore initiation SRAM operation continues to be enabled for time tpELAY 25 Read and Write cycles are ignored during STORE RECALL and while VCC is below 26 HSB pin is driven high to VCC only by internal 100kOhm resistor HSB d
11. later read cycle 2 The data output repeatedly responds to address changes within the taa access time without the need for transitions on any control input pins This remains valid until another address change or until CE or OE is brought HIGH or WE or HSB is brought LOW SRAM Write A write cycle is performed when CE and WE are LOW and HSB is HIGH The address inputs must be stable before entering the write cycle and must remain stable until CE or WE goes HIGH at the end of the cycle data on the common pins DQg 15 are written into the memory if the data is valid tsp before the end of a WE controlled write or before the end of a CE controlled write The Byte Enable inputs BHE BLE determine which bytes are written in the case of 16 bit words Keep OE HIGH during the entire write cycle to avoid data bus contention on common I O lines If OE is left LOW internal circuitry turns off the output buffers after WE goes LOW AutoStore Operation The CY14B101LA CY14B101NA stores data to the nvSRAM using one of the following three storage operations Hardware STORE activated by HSB Software STORE activated by an address sequence AutoStore on device power down The AutoStore operation is a unique feature of QuantumTrap technology and is enabled by defaut the CY14B101LA CY14B101NA During a normal operation the device draws current from Vcc to charge a capacitor connected to the pin This stored charge i
12. without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Any Source Code software and or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign United States copyright laws and international treaty provisions Cypress hereby grants to licensee a personal non exclusive non transferable license to copy use modify create derivative works of and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement Any reprod
13. 79 Rev B Page 3 of 25 Feedback PERFORM Device Operation The CY14B101LA CY14B101NA nvSRAM is made up of two functional components paired in the same physical cell They are an SRAM memory cell and a nonvolatile QuantumTrap cell The SRAM memory cell operates as a standard fast static RAM Data in the SRAM is transferred to the nonvolatile cell the STORE operation or from the nonvolatile cell to the SRAM the RECALL operation Using this unique architecture all cells are stored and recalled in parallel During the STORE and RECALL operations SRAM read and write operations inhibited The CY14B101LA CY14B101NA supports infinite reads and writes similar to a typical SRAM In addition it provides infinite RECALL operations from the nonvolatile cells and up to 200K STORE operations Refer to the Truth Table For SRAM Operations on page 15 for a complete description of read and write modes SRAM Read The CY14B101LA CY14B101NA performs a read cycle when CE and OE are LOW and WE and HSB are HIGH The address specified on pins Ag 16 or Ag 45 determines which of the 131 072 data bytes or 65 536 words of 16 bits each are accessed Byte enables BHE BLE determine which bytes are enabled to the output in the case of 16 bit words When the read is initiated by an address transition the outputs are valid after a delay of taa read cycle 1 If the read is initiated by CE or OE the outputs are valid at tace or at tpog whichever is
14. AM Write Cycle 1 WE Controlled 18 19 21 twe Address Address J t SCE HA m m BHE BLE Al m d 2 x z E m tip Data Input Input Data Valid Data Output High Impedance gt Note 21 CE or WE must be gt during address transitions Document 001 42879 Rev B Page 10 of 25 Feedback ie PRELIMINARY CY14B101LA CY14B101NA CYPRESS PERFORM Figure 9 SRAM Write Cycle 2 CE Controlled 18 19 21 twe lt Address Address Valid tsa tsce tew TAT N BHE BLE t 2 PWE gt WE t lup Input Data Valid High Impedance Y Data Input Data Output Figure 10 SRAM Write Cycle 3 and BLE Controlled 18 19 21 twe Address X Address Valid SA law BHE BLE A t t SD HD Data Input Input Data Valid High Impedance Data Output Page 11 of 25 Document 001 42879 Rev Feedback gy ous PRELIMINARY CY14B101LA CY14B101NA PERFORM AutoStore Power Up RECALL 20n 25n 45n Parameters Description Min 0105 Max Min sns Max Min oie Max Unit turecat 27 Power Up RECALL Duration 20 20 20 ms 3 STORE Cycle Duration 8 8 8 ms 24 Allowed to Complete SRAM Cycle 20 25 25 ns Vswitcu
15. B101NA provides the HSB pin to control and acknowledge the STORE operations Use the HSB pin to request a Hardware STORE cycle When the HSB pin is driven LOW the CY14B101LA CY14B101NA conditionally initiates a STORE operation after tpg Ay An actual STORE cycle only begins if a write to the SRAM has taken place since the last STORE or RECALL cycle The HSB pin also acts as an open drain driver that is internally driven LOW to indicate a busy condition when the STORE initiated by any means is in progress SRAM read and write operations that are in progress when HSB is driven LOW by any means are given time to complete before the STORE operation is initiated After HSB goes LOW the CY14B101LA CY14B101NA continues SRAM operations for Av However any SRAM write cycles requested after HSB goes LOW are inhibited until HSB returns HIGH If the write latch set HSB is not driven low by the CY14B101LA CY14B101NA but any SRAM read write cycles are inhibited until HSB is returned HIGH by MPU or another external source Page 4 of 25 Feedback During any STORE operation regardless of how it is initiated the CY14B101LA CY14B101NA continues to drive the HSB pin LOW releasing it only when the STORE is complete Upon completion of the STORE operation the CY14B101LA CY14B101NA remains disabled until the HSB pin returns HIGH Leave the HSB unconnected if it is not used Hardware RECALL Power Up Du
16. IMINARY CY14B101LA CY14B101NA PERFORM Hardware STORE Cycle mes 20ns 25ns 45ns Parameters Description Unit Min Max Min Max Min Max tpHsB HSB To Output Active Time when write latch not set 20 25 25 ns tpHsB Hardware STORE Pulse Width 15 15 15 ns tss 29 307 Soft Sequence Processing Time 100 100 100 us Switching Waveforms Figure 14 Hardware STORE Cycle Write latch set HSB IN HSB OUT 5 ZHSI DQ Data Out 2 55 RWI Pa Write latch not set HSB IN q 7 HSB pin is driven high to Vcc only by Internal 100kOhm resistor HSB driver is disabled SRAM is disabled as long as HSB IN is driven low HSB OUT p m RWI K Figure 15 Soft Sequence Processing 301 Soft Sequence tss Soft Sequence tos lt Command gt lt Command lt gt Address Hares Fx AN Address PX Address 6 tsa tew tew ae w Notes 29 This is the amount of time it takes to take action on a soft sequence command Vcc power must remain HIGH to effectively register command 30 Commands such as STORE and RECALL lock out IO until operation is complete which further increases this time See the specific command Document 001 42879 Rev B Page 14 of 25 Feedback CYPRE
17. Leakage Current or WE lt V Vin Input HIGH Voltage 20 Vect0 5 V Input LOW Voltage Vss 0 5 0 8 V Vou Output HIGH Voltage lour 2 mA 24 V VoL Output LOW Voltage lour 4 mA 0 4 V Vcapl 3l Storage Capacitor Between Vcap pin Vss 5V Rated 61 180 Notes 11 Typical conditions for the active current shown on the DC Electrical characteristics are average values 25 C room temperature and Vcc 3V Not 100 tested 12 The HSB pin has Iour 2 uA for of 2 4V when both active high and low drivers are disabled When they are enabled standard and Vo are valid This parameter is characterized but not tested 13 Vcap Storage capacitor nominal value is 68 uF Document 001 42879 Rev Page 7 of 25 Feedback CYPRESS PRELIMINARY CY14B101LA CY14B101NA 7 PERFORM Data Retention and Endurance Parameter Description Min Unit DATAR Data Retention 20 Years NVc Nonvolatile STORE Operations 200 K Capacitance Parameter 14 Description Test Conditions Max Unit Input Capacitance Ta 25 C f 1 MHz 7 pF Cour Output Capacitance Vcc 7010 3 0V 7 pF Thermal Resistance Parameter 41 Description Test Conditions 48 FBGA 48 SSOP 44 Il 32 SOIC Unit Thermal Resistance conditions follow standard 28 82 TBD 31 11 TBD C W Junction to Ambient test methods and procedures for me
18. RAM Output Data 0 0xB1C7 Read SRAM Output Data 0x83E0 Read SRAM Output Data Ox7C1F Read SRAM Output Data 0x703F Read SRAM Output Data 0x8B45 AutoStore Output Data Disable Notes 9 While there are 17 address lines on the CY14B101LA 16 address lines on the CY14B101NA only the 13 address lines A44 A2 are used to control software modes Rest of the address lines are don t care 10 The six consecutive address locations must be in the order listed WE must be HIGH during all six cycles to enable a nonvolatile cycle Document 001 42879 Rev Page 5 of 25 Feedback Table 2 Mode Selection continued CY14B101LA CY14B101NA CE WE BLEM A45 Mode 1 0 Power L H L 0x4E38 Read SRAM Output Data Activel10 0xB1C7 Read SRAM Output Data 0x83E0 Read SRAM Output Data 0x7C1F Read SRAM Output Data 0x703F Read SRAM Output Data 0x4B46 AutoStore Enable Output Data L H L 0 4 38 Read SRAM Output Data Active Ic c0 0xB1C7 Read SRAM Output Data 0x83E0 Read SRAM Output Data 0x7C1F Read SRAM Output Data 0x703F Read SRAM Output Data 0x8FC0 Nonvolatile Output High Z STORE L H L 0x4E38 Read SRAM Output Data Activel10 0xB1C7 Read SRAM Output Data 0x83E0 Read SRAM Output Data 0x7C1F Read SRAM Output Data 0x703F Read SRAM Output Data 0x4C63 Nonvolatile Output High Z Recall Preventing AutoStore Data Protection The AutoSt
19. SS PRELIMINARY CY14B101LA CY14B101NA PERFORM Truth Table For SRAM Operations HSB must remain HIGH for SRAM operations Table 3 Truth Table for x8 Configuration CE WE OE Inputs Outputs 2 Mode Power H X X High Z Deselect Power down Standby L H L Data Out DQo DQ Read Active L H H High Z Output Disabled Active L L X Data in 000 Write Active Table 4 Truth Table for x16 Configuration CE WE OE BHE BLE Inputs Outputs Mode Power H X X X X High Z Deselect Power down Standby L X X H H High Z Output Disabled Active L H L L L Data Out DQo DQ5 Read Active L H L H L Data Out DQg DQ7 Read Active DQg DQ 5 in High Z H L L H Out DQg DQ45 Read Active DQg DQj in High Z L H H L L High Z Output Disabled Active L H H H L High Z Output Disabled Active L H H L H High Z Output Disabled Active L L X L L Data In DQg DQ45 Write Active L L X H L In DQg DQ Write Active DQg DQXAs in High Z L L x L H Data In DQg DQ s5 Write Active DQo DQ High Z Document 001 42879 Rev Page 15 of 25 Feedback Z CYPRESS PRELIMINARY CY14B101LA CY14B101NA PERFORM Ordering Information ye Ordering Code eise Package Type Ee 20 CY14B101LA ZS20XCT 51 85087 44 pin TSOP II Commercial CY14B101LA ZS20XC 51 85087 44 pin TSOP II CY14B101LA BA20XCT 51 85128 48 ball FBGA CY14B101LA BA20XC 51 85128 48
20. able Changed tas to tsa Changed tGHAX to tHa Changed ty value from 1ns to 0 ns Added Figure 13 Added parameter Changed thi ux to tpHsB Updated tss from 70us to 100us Added truth table for SRAM operations Updated ordering information and part numbering nomenclature B 2654484 02 05 09 Document 001 42879 Rev B GVCH PYRS Changed the data sheet from Advance information to Preliminary Referenced Note 15 to parameters ti tyzce tLzoE tuzog tLzwE and Updated Figure 12 Page 24 of 25 Feedback SES 2 PRELIMINARY CY14B101LA CY14B101NA 7 M SS SSS 1 PERFORM Sales Solutions and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices solution centers manufacturer s representatives and distributors To find the office closest to you visit us at cypress com sales Products PSoC Solutions PSoC psoc cypress com General psoc cypress com solutions Clocks amp Buffers clocks cypress com Low Power Low Voltage psoc cypress com low power Wireless wireless cypress com Precision Analog psoc cypress com precision analog Memories memory cypress com LCD Drive psoc cypress com Icd drive Image Sensors image cypress com CAN 2 0b psoc cypress com can USB psoc cypress com usb Cypress Semiconductor Corporation 2008 2009 The information contained herein is subject to change
21. asuring thermal impedance in accordance with EAJESD51 94 TBD 996 TE o ee Figure 5 AC Test Loads 5770 5770 for tri state specs 3 0V 3 0V R1 R1 OUTPUT OUTPUT 30 pF AC Test Conditions Input Pulse Levels Input Rise and Fall Times 10 90 Input and Output Timing Reference Levels Note R2 7890 14 These parameters are guaranteed by design and are not tested Document 001 42879 Rev B R2 7890 8 of 25 Feedback CYPRESS PRELIMINARY CY14B101LA CY14B101NA PERFORM AC Switching Characteristics Parameters 20 ns 25 ns 45 ns s m sius edu es uu Bos SRAM Read Cycle tACE tacs Chip Enable Access Time 20 25 45 ns trell 20 25 45 ns taa Address Access Time 20 25 45 ns tpoE toE Output Enable to Data Valid 10 12 20 ns 9 tou Output Hold After Address Change 3 3 3 ns 17 tiz Chip Enable to Output Active 3 3 3 ns taze li 17 thz Chip Disable to Output Inactive 8 10 15 ns tizog 17 toLz Output Enable to Output Active 0 0 0 ns 171 touz Output Disable to Output Inactive 8 10 15 ns tpu tpa Chip Enable to Power Active 0 0 0 5 tpp tps Chip Disable to Power Standby 20 25 45 ns Byte Enable to Data Valid 10 12 20 ns tLZBE Byte
22. ball FBGA CY14B101LA SP20XCT 51 85061 48 pin SSOP CY14B101LA SP20XC 51 85061 48 pin SSOP CY14B101LA SZ20XCT 51 85127 32 pin SOIC CY14B101LA SZ20XC 51 85127 32 pin SOIC CY14B101NA ZS20XCT 51 85087 44 pin TSOP II CY14B101NA ZS20XC 51 85087 44 pin TSOP II CY14B101NA BA20XCT 51 85128 48 ball FBGA CY14B101NA BA20XC 51 85128 48 ball FBGA CY14B101LA ZS20XIT 51 85087 44 pin TSOP II Industrial CY14B101LA ZS20XI 51 85087 44 TSOP II CY14B101LA BA20XIT 51 85128 48 ball FBGA CY14B101LA BA20XI 51 85128 48 ball FBGA CY14B101LA SP20XIT 51 85061 48 pin SSOP CY14B101LA SP20XI 51 85061 48 pin SSOP CY14B101LA SZ20XIT 51 85127 32 pin SOIC CY14B101LA SZ20XI 51 85127 32 pin SOIC CY14B101NA ZS20XIT 51 85087 44 pin TSOP II CY14B101NA ZS20XI 51 85087 44 pin TSOP II CY14B101NA BA20XIT 51 85128 48 ball FBGA CY14B101NA BA20XI 51 85128 48 ball FBGA Document 001 42879 Rev Page 16 of 25 Feedback Z CYPRESS PRELIMINARY CY14B101LA CY14B101NA PERFORM Ordering Information continued pon Ordering Code esce Package Type Ee 25 CY14B101LA ZS25XCT 51 85087 44 TSOP II Commercial CY14B101LA ZS25XC 51 85087 44 TSOP II CY14B101LA BA25XCT 51 85128 48 FBGA CY14B101LA BA25XC 51 85128 48 FBGA CY14B101LA SP25XCT 51 85061 48 pin SSOP CY14B101LA SP25XC 51 85061 48 pin SSOP CY14B101LA SZ25XCT 51
23. d when Vcc is less than Vswitcu _ If the CY14B101LA CY14B101NA is in a write mode both CE and WE are LOW at power up after a RECALL or STORE the write is inhibited until the SRAM is enabled after 4 745g HSB to output active This protects against inadvertent writes during power up or brown out conditions Noise Considerations Refer to CY application note AN1064 Page 6 of 25 Feedback CYPRESS PRELIMINARY CY14B101LA CY14B101NA PERFORM Maximum Ratings Package Power Dissipation Capability 2595 1 0W Exceeding maximum ratings may impair the useful life of the Surface Mount Pb Soldering device These user guidelines are not tested Temperature 3 260 C Storage Temperature 65 C to 150 C DC Output Current 1 output at a time 1s duration 15 mA Maximum Accumulated Storage Time Static Discharge 2001V At 150 C Ambient Temperature 1000h per MIL STD 883 Method 3015 At 85 C Ambient Temperature 20 Years Latch Up Current gt 200 Ambient Temperature with Power Applied 55 to 150 C Operating Range Supply Voltage on Vcc Relative to GND 0 5V to 4 1V Range Ambient Temperature Voltage Applied to Outputs in High Z State 0 5V to Vec 0 5V Commercial 0 C to 70
24. nsity 101 1 Mb Voltage 3 0 NVSRAM 14 AutoStore Software STORE Hardware STORE Cypress Document 001 42879 Rev B Page 19 of 25 Feedback PERFORM Package Diagrams TOP VIEW 04000019 Jh 0 300 0 012 BASE PLANE mmol 0 800 BSC 0 0315 PRELIMINARY 18 517 0 729 18 313 0 721 FPL 1 0 10 004 SEATING PLANE 1 194 0 047 0 991 0 039 0 150 0 0059 0 050 0 0020 Document 001 42879 Rev B CY14B101LA CY14B101NA Figure 16 44 Pin TSOP II 51 85087 DIMENSION IN MM INCH MAX HRRRRRRRRRRHRHRHRHRHRRHHRRH 10 262 0 404 10 058 0 396 BOTTOM VIEW 10 262 0 404 10 058 0 396 NM T Lo fU N n 0 597 0 0235 0 406 0 0160 HHHEHHEBHHBBHEBBHEHEBHEN 0 210 0 0083 0 120 0 0047 51 85087 A Page 20 of 25 Feedback CYPRESS PRELIMINARY CY14B101LA CY14B101NA PERFORM Package Diagrams continued Figure 17 48 Ball FBGA 6 mm x 10 mm x 1 2 mm 51 85128 TOP VIEW BOTTOM VIEW CORNER 00 05 V 19025 M BB 1 CORNER 00 30 0 05 48 56 6 5 4 3
25. ore function is disabled initiating an AutoStore disable sequence A sequence of read operations is performed in a manner similar to the Software STORE initiation To initiate the AutoStore disable sequence the following sequence of CE controlled read operations must be performed 1 Read address 0x4E38 Valid READ 2 Read address 0xB1C7 Valid READ 3 Read address 0x83E0 Valid READ 4 Read address 0x7C1F Valid READ 5 Read address 0x703F Valid READ 6 Read address 0x8B45 AutoStore Disable The AutoStore is reenabled by initiating an AutoStore enable sequence A sequence of read operations is performed in a manner similar to the Software RECALL initiation To initiate the AutoStore enable sequence the following sequence of CE controlled read operations must be performed 1 Read address 0x4E38 Valid READ 2 Read address 0xB1C7 Valid READ 3 Read address 0x83E0 Valid READ 4 Read address 0x7C1F Valid READ 5 Read address 0x703F Valid READ 6 Read address 0x4B46 AutoStore Enable If the AutoStore function is disabled or reenabled a manual STORE operation Hardware or Software must be issued to save the AutoStore state through subsequent power down cycles The part comes from the factory with AutoStore enabled Document 001 42879 Rev B The CY14B101LA CY14B101NA protects data from corruption during low voltage conditions by inhibiting all externally initiated STORE and write operations The low voltage condition is detecte
26. put lines depending on operation DQo 5 Input Output Bidirectional Data I O Lines for x16 Configuration Used as input or output lines depending on operation WE Input Write Enable Input Active LOW When the chip is enabled and WE is LOW data on the pins is written to the specific address location CE Input Chip Enable Input Active LOW When LOW selects the chip When HIGH deselects the chip OE Input Output Enable Active LOW The active LOW OE input enables the data output buffers during read cycles I O pins are tri stated on deasserting OE HIGH BHE Input Byte High Enable Active LOW Controls DQ45 DQg BLE Input Byte Low Enable Active LOW Controls DQ DQo Vss Ground for the Device Must be connected to the ground of the system Vec Power Power Supply Inputs to the Device 3 0V 20 1090 Supply HSB 8 Input Output Hardware STORE Busy HSB When LOW this output indicates that a Hardware STORE is in progress When pulled LOW external to the chip it initiates a nonvolatile STORE operation A weak internal pull up resistor keeps this pin HIGH if not connected connection optional After each STORE operation HSB is driven HIGH for short time with standard output high current Power Capacitor Supplies power to nvSRAM during power loss to store data from SRAM to Supply nonvolatile elements NC No Connect No Connect This pin is not connected to the die Document 001 428
27. ring power up or after any low power condition Vcc lt Vswitcy an internal RECALL request is latched When Vcc again exceeds the sense voltage of Vswitcy a RECALL cycle is automatically initiated and takes to complete During this time HSB is driven low by the HSB driver Software STORE Data is transferred from SRAM to the nonvolatile memory by a software address sequence The CY14B101LA CY14B101NA Software STORE cycle is initiated by executing sequential CE controlled read cycles from six specific address locations in exact order During the STORE cycle an erase of the previous nonvolatile data is first performed followed by a program of the nonvolatile elements After a STORE cycle is initiated further input and output are disabled until the cycle is completed Because a sequence of READs from specific addresses is used for STORE initiation it is important that no other read or write accesses intervene in the sequence or the sequence is aborted and no STORE or RECALL takes place To initiate the Software STORE cycle the following read sequence must be performed 1 Read Address Ox4E38 Valid READ 2 Read Address 0xB1C7 Valid READ 3 Read Address 0x83E0 Valid READ 4 Read Address Ox7C1F Valid READ 5 Read Address 0x703F Valid READ 6 Read Address Ox8FCO Initiate STORE Cycle Table 2 Mode Selection CY14B101LA CY14B101NA The software sequence may be clocked with CE controlled reads or OE controlled reads Af
28. river is disabled Document 001 42879 Rev B Page 12 of 25 Feedback PRELIMINARY CY14B101LA CY14B101NA Software Controlled STORE RECALL Cycle a 20 ns 25 ns 45 ns Parameters 281 Description Min Max Min Max Min Max Unit tac STORE RECALL Initiation Cycle Time 20 25 45 ns tsa Address Setup Time 0 0 0 ns tew Clock Pulse Width 15 20 30 ns tHa Address Hold Time 0 0 0 ns tRECALL RECALL Duration 200 200 200 us Switching Waveforms Figure 12 CE and OE Controlled Software STORE RECALL Cycle lt c y tac Address sss Address XK SN 6 tow CE tua S t ty Ay gl ON EN lt lt HA OE p DS N lt HSB STORE only lice ES High Impeda 1 m nce DQ DATA E E K K STORE RECALL lt gt RWI Figure 13 Autostore Enable Disable Cycle t RC N Address 6 p tow t RC lt Address x Address 1 DQ DATA Notes 27 The software sequence is clocked with CE controlled or OE controlled reads EXE 28 The six consecutive addresses must be read in the order listed in Table 2 on page 5 WE must be HIGH during all six consecutive cycles Document 001 42879 Rev B Page 13 of 25 Feedback CYPRESS PREL
29. s used by the chip to perform a single STORE operation If the voltage on the Vcc pin drops below Vsyitcu the part automatically disconnects the Vcap pin from Vcc A STORE operation is initiated with power provided by the VcAp capacitor Document 001 42879 Rev CY14B101LA CY14B101NA Figure 4 shows the proper connection of the storage capacitor VcAp for automatic STORE operation Refer to DC Electrical Characteristics on page 7 for the size of The voltage on the Vcap pin is driven to Vcc by a regulator on the chip Place pull up on WE to hold it inactive during power up This pull up is only effective if the WE signal is tri state during power up Many MPUs tri state their controls on power up This must be verified when using the pull up When the nvSRAM comes out of power on recall the MPU must be active or the WE held inactive until the MPU comes out of reset To reduce unnecessary nonvolatile stores AutoStore and Hardware STORE operations are ignored unless at least one write operation has taken place since the most recent STORE or RECALL cycle Software initiated STORE cycles are performed regardless of whether a write operation has taken place The HSB signal is monitored by the system to detect if an AutoStore cycle is in progress Figure 4 AutoStore Mode Vcc e M 0 1uF M Vcc 10kOhm CAP D Vear N ss Hardware STORE Operation The CY14B101LA CY14
30. ter the sixth address in the sequence is entered the STORE cycle commences and the chip is disabled HSB is driven low It is important to use read cycles and not write cycles in the sequence although it is not necessary that OE be LOW for a valid sequence After the cycle time is fulfilled the SRAM is activated again for the read and write operation Software RECALL Data is transferred from nonvolatile memory to the SRAM by a Software address sequence A Software RECALL cycle is initiated with a sequence of read operations in a manner similar to the Software STORE initiation To initiate the RECALL cycle the following sequence of CE controlled read operations must be performed 1 Read Address Ox4E38 Valid READ 2 Read Address 0xB1C7 Valid READ 3 Read Address 0x83E0 Valid READ 4 Read Address 0x7C1F Valid READ 5 Read Address 0x703F Valid READ 6 Read Address 0x4C63 Initiate RECALL Cycle Internally RECALL is a two step procedure First the SRAM data is cleared Next the nonvolatile information is transferred into the SRAM cells After the cycle time the SRAM is again ready for read and write operations The RECALL operation does not alter the data in the nonvolatile elements CE WE OE BLE A45 Ag Mode Power H X X X Not Selected Output High Z Standby L H L X Read SRAM Output Data Active L L X X Write SRAM Input Data Active L H L 0 4 38 Read S
31. the STORE and RECALL operations are also available under software control Logic Block Diagram 2 31 R O w s D E STATIC RAM of ARRAY s D 1024 X 1024 45 Ae R gu oo g Pp E od 4 COLUMN I O go oo o amp DQ DQ DQ 00 5 COLUMN DEC 2 Quatrum Trap 1024 X 1024 rd RECALL POWER CONTROL y STORE RECALL CONTROL HSB SOFTWARE DETECT Au A Note 1 Address Ao Aig for x8 configuration and Address Ag A45 for x16 configuration 2 Data DQy DG for x8 configuration and Data DQ45 for x16 configuration 3 BHE and BLE are applicable for x16 configuration only Cypress Semiconductor Corporation Document 001 42879 198 Champion Court San Jose CA 95134 1709 408 943 2600 Revised January 29 2009 Feedback CYPRESS PRELIMINARY CY14B101LA CY14B101NA Pinouts Figure 1 Pin Diagram 48 FBGA 48 F BGA 48 FBGA x8 x16 Top View Top View not to scale not to scale CAI IAE EWW C O e COMAG Co EHEC MEME Cs Cay Ke Kes ox As Ga CORE Cee ard od Was Cs COIN
32. uction modification translation compilation or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Cypress reserves the right to make changes without further notice to the materials described herein Cypress does not assume any liability arising out of the application or use of any product or circuit described herein Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress product in a life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Use may be limited by and subject to the applicable Cypress software license agreement Document 001 42879 Rev B Revised January 29 2009 Page 25 of 25 AutoStore and QuantumTrap are registered trademarks of Cypress Semiconductor Corporation All products and company names mentioned in this document are the trademarks of their respective holders Feedback
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