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AOC 41A50-144 User's Manual

1. Parameter Min Typ Max Note PVDD 5 6 volts CVDD 5 6 volts Vin Vss 0 5 volt 0 5 Operating temperature 0 degree C 70 degree C Storage temperature 65 degree C 150 degree C Maximum power consumption 2W Table 21 DC Electrical Characteristic Parameter Min Typ Max Note PVDD 3 15 volts 3 3 volts 3 47 volts CVDD 3 15 volts 3 3 volts 3 47 volts Vil COMS inputs 0 3 CVDD Vil TTL inputs 0 8 volts Vih COMS inputs 0 7 CVDD 1 1 CVDD 1 Vih TTL inputs 2 0 volts 5 0 0 5 volts Voh 2 4 volts CVDD Vol 0 2 volts 0 4 volts Input Current JOuA 10 uA PVDD operating supply current mA 20 mA pad 10pF 2 CVDD operating supply current 0 mA 500 mA 3 PEE 1 5V Tolerent TTL Input pads are as follows CRT Interface HSYNC pin 150 VSYNC 148 Host Interface HFS 98 HCLK 103 HDATA 99 RESETN 100 MFB 11 0 MFB3 110 MFB2 111 1 112 MFBO 113 OSD Interface OSD DATA3 121 OSD DATA2 120 OSD DATAI 119 OSD DATAO 118 OSD FSW 122 e Non 5V Tolerant TTL Input Pad is TCLK 141 NOTE 2 When the panel interface is disabled the supply current is 0 mA The drive current of each pad can be programmed in the range of 2 mA to 20 mA capacitive loading 10 pF 11 123 10 124 MFB9 102 MFB8 4104 MFB7 105 MFB6 106 MFB5 107 4 109 NOTE 3 When all circuits are powered down and T
2. 5 3 THE OPTIONAL ON MAINBOARD USING SHUTTLE amp 4 5 4 THE OPTIONAL ON MAINBOARD OR OTHER ACCESSORY USING DIFFERENT PANEL 5 5 SIMPLE INTRODUCTION ABOUT LM500 CHIPSET 5 6 SOFTWARE FLOW CHART A INTERFACE BOARD TROUBLE SHOOTING CHART B INVERTER MODULE TROUBLE SHOOTING CHART I CHI MEl inverter spec amp trouble shooting chart C ADAPTER TROUBLE SHOOTING CHART amp BOM D AUDIO TROUBLE SHOOTING CHART amp BOM E Main chip GMZANI specifications MECHANICAL OF CABINET FRONT 5 14 23 23 50 54 64 65 9 POWER SYSTEM AND CONSUMPTION CURRENT ce 11 MAINBOARD SCHEMATIC DIAGRAM mee 12 ADAPTER SCHEMATIC DIAGRAM 13 AUDIO SCHEMATIC DIAGRAM 1 1 1 10 11 12 13 14 15 1 SPECIFICATIONS FOR LCD MONITOR General specifications LCD PANEL Active display area 17 inches diagonal Pixel pitch 0 264 mm x 0 264 mm Pixel format 1280 x 1024 RGB vertical stripe arrangement Display Color 8 bit 16 7 million colors e External Controls Power On Off Auto key Left key Right key for 4 key e OSD menu Controls Contrast Brightness Focus Clock H position V position Language Recall 7800 Recall 6500 Reset Exit osd Red Green Blue Selected Dos resolution Inpu
3. MCU Block HDATAO MFB7 MFB8 9 HCLI BKLT PWM HFS U302 8XC51 PLCC R431 T2 P1 0 D301 1N4148 RST RXD TXD IRQ SDA MFB 13 RXD P3 0 147 IXD P3 1 187 INTUP3 2 INT1 P3 3 SCL 17 10 63 4 8511 CON IuP35 18 WR P3 6 RD P3 7 R340 20 R301 U300 10K R341 0 XTAL2 21 TEST OP R303 10 K OP 3 24LCO4B 2 1 XTAL1 quer BKLT ON 10 K OP Panel Select 0 K E Select R319 P2 0 A8 P2 1 A9 P2 2 A10 P2 3 A11 P2 4 A12 BKLT ON P2 5 A13 P2 6 A14 P2 7 A15 PSEN ALE PROG PO 7 AD7 KEY1 ORANGE PO 6 AD6 PO 5 AD5 K 7 KEYS AUTO 4 4 KEVA ENTER PO 3 AD3 PO 2 AD2 PO 1 AD1 REYS RIGHT PO 0 ADO CP301 1000 pF C944 C403 0 1 uF 100uF GND HEADER 9 CP302 1000 pF R315 3904 Q304 8403 HEADER 5 4 7K OP 8402 BKLT PWM Leni 1 100uF OP GND Top Victory Electronics Co Ltd itle MICRO CONTROLLER Document Number B 715A820 1 ate Tuesday July 10 2001 0304 LM2596S 5 0 CN301 12V POWER FB301 TO263 a INDUCTOR z C307 330 uF 35V L L C309 330 uF
4. AC IN 100v 240v 1 3 Interface Connectors A AC Power Cable B Video Signal Connectors and Cable C External Adapter 2 1 2 2 2 PRECAUTIONS AND NOTICES ASSEMBLY PRECAUTION 1 Please do not press or scratch LCD panel surface with anything hard And do not soil LCD panel surface by touching with bare hands Polarizer film surface of LCD panel is easy to be flawed In the LCD panel the gap between two glass plates is kept perfectly even to maintain display characteristic and reliability If this panel is subject to hard pressing the following occurs a Uniform color b Orientation of liquid crystal becomes disorder 2 Please wipe out LCD panel surface with absorbent cotton or soft cloth in case of it being soiled 3 Please wipe out drops of adhesive like saliva and water in LCD panel surface immediately They might damage to cause panel surface variation and color change 4 Do not apply any strong mechanical shock to the LCD panel OPERATING PRECAUTIONS 1 Please be sure to unplug the power cord before remove the back cover be sure the power is turn off 2 Please do not change variable resistance settings in MAIN BOARD they are adjusted to the most suitable value If they are changed it might happen LUMINANCE does not satisfy the white balance spec 3 Please consider that LCD backlight takes longer time to become stable of radiation characteristic in low temperature than in room temperature 4 Pleas
5. 1 n 100 op U401B Reserved SCAN IN2 SCAN QUT SCAN OUT2 2ALC21A 1K SRVSS2 ADC GND2 96 6M01 GNDA 96 BGNDA 96 GGNDA RGNDA SUB SGNDA SGNDA PLL RGNDA SUB RGNDA SUB DGNDA CV551 CVSS1A RVSS1 SRVSSI RVSS2 cvss2 RVSS3 RVSS4 CVSS3 CVSS4 DVSS SVSS SYN vss CVSS2A CV555 SUB GNDA PLL DGNDA DAC DGNDA DAC SGNDA ADC AGND ADC AGND 81 82 85 89 93 132 133 Connect two grounds at single point only 0202 SI9933ADY ADC AGND GND PLL_GNDA PANEL P 9200 MMBT3904 1203 600 1206 1 Top Victory Electronics Co Ltd We ADC AGND ZAN1 Bize Document Number 715 1 Thursday September 06 2001 AVDD 3 3 LVDS Block C602 C603 0 1uF 100uF U601 NT7181 TSSOP56 ERED O 7 EDGE TXINO PWRDWN TXIN1 TXIN2 TXOUTO TXOUTO 4 TXOUTI TXING TXOUT1 TXIN27 TXOUT2 TXIN5 TXOUT2 EGRNIO 7J TXOUT3 TXIN7 TXOUT3 8 TXIN9 TXIN12 TXCLKOUT TE TXIN13 TXCLKOUT TXIN14 TXIN10 TXIN11 LVDSVCC didus L601 TXIN15 LVDSGND BEAD120 0603 TXIN18 LVDSGND STS PANEL P TXIN19 LVDSGND 2
6. Turn the POWER button off to on to quit from factory mode in USER mode the OSD window location was placed at middle of screen 2 Clock adjustment Set the Chroma at pattern 63 cross talk pattern or WIN98 95 shut down mode dot pattern Adjust until the vertical Stripe shadow as wide as possible or no visible This function is adjust the PLL divider of ADC to generate an accurate pixel clock Example Hsyn 31 5KHz Pixel freq 25 175MHz from VESA spec The Divider number is Pixel freq x 1000 Hsyn From this formula we get the Divider number if we fill this number in ADC register divider register the PLL of ADC will generate a clock which have same period with above Pixel freq 25 175MHz the accuracy of this clock will effect the size of screen this clock was called PIXEL CLOCK 3 Focus adjustment Set the Chroma at pattern 63 cross talk pattern or WIN98 95 shut down mode dot pattern Adjust the horizontal interference as less as possible This function is adjust the phase shift of PIXEL CLOCK to acquire the right pixel data If the relationship of pixel data and pixel clock not so match we will see the horizontal interference on screen we only find this phenomena in crosstalk pattern or dot pattern other pattern the affect is very light 4 H V Position adjustment Set the Chroma to pattern 1 crosshatch pattern or WIN98 95 full white pattern confirm above item 2 amp 3 functions clock amp focus was done well
7. C6 102 1 SMD 0805 TDK 1000PF 50V 27 C10 11 VCLRCN1EB333K A 2 SMD 0805 0 033 uF 25V 28 C12 13 n VCMEBF2AB184J P 2 DIP 0 18uF 100V ARCO VCMECF2AC184J P DIP 0 18uF 100V THOMSON 29 CAPACITOR VCDSEUSSL220K 4 DIP 22PF 3KV 10 TDK 30 C7 16 17 n VCLFCN1EY105Z A SMD 0805 1 uF 25V TDK 31 C18 VCLFCN1CY225Z A 1 SMD 0805 2 2 yF 16V TDK 32 C21 n VCLFBN1CY475Z A 1 SMD 0805 4 7 uF 16V TDK 33 D1 2 DIODE VSDRLS4148 A 2 SMD RLS4148 ROHM 34 D3 4 VSDRB160L40 A 2 SMD RB160L40 ROHM VSDSMA160 A SMD SMA160 TPC 35 D5 6 VSZRLZ8 2B A 2 SMD RLZ8 2B ROHM 36 D7 8 VSDDA204k A 2 SMD DA204K ROHM 37 1 C 1 C VSITL1451ACNS A 1 SMD TL1451ACNS TEXAS 38 F1 FUSE QFS N302FIDZD A 1 SMD FUSE 3 0A 63 LITTLE Attachment QFS Z302FIDZD A SMD FUSE 3 0 63 055 102 40 L1 2 COIL RCHOLO00071D151A 2 DIP 150uH 10 YST Attachment 1 1000710151 DIP 150uH 10 ik jik 41 PT1 2 TRANS RCVT 1207ID Z A 2 SMD YST 1207 YST Attachment 2 RCVT 12071D Z C SMD WT 1207 WT Attachment 2 1 42 PCB PCB QPWBGL983IDLF3 1 QPWBGL983IDLF3 JEISO LONGMAW TAE 26 SAMPO CORPORATION TROUBLE SHOOTING OF CHI MEI INVERTER DIVTL0037 D42 9 TROUBLE SHOOTING 9 1 NO POWER CHECK ON FUSE FI Vin 12 TO CHANGE 1 4 0A 63V TO CHECK ON Q4 amp Q6 Vout 9V L 044034011 054066012 CHECK ONLI amp
8. DCLK jns width 3 bits 18 bits 36 bits 24 bits 48 bits bits pixel NOTE Numbers in are for two pixels clock mode NOTE The drive current of the panel interface signals is programmable as shown in Table 1 The drive current is to be programmed through the API upon chip initialization Output current is programmable from 2 mA to 20mA in increments of 2 mA Drive strength should be programmed to match the load presented by the cable and input of the panel Values shown are based on a loading of 20pF and a drive strength of 8 mA NOTE 1 The PCLK is the panel shift clock NOTE 2 The DCLK stands for Destination Clock DCLK period Is equal to PCLK period in one pixel clock mode twice the PCLK period in two pixels clock mode NOTE 3 The setup hold time spec for PCLK also applies to PHS and PdispE The setup time t16 and the hold time t17 listed in this table are for the case in which no clock to data skew is added The PVS PHS PdispE Pdata signals are asserted on the rising edge of the PCLK The polarity of the PCLK and its skew are programmable Clock to Data skew can be adjusted in sixteen 800 ps increments In combination with the PCLK polarity inversion the clock to data phase can be adjusted in total of 31 steps NOTE 4 The polarity of the PCLKA and the PCLKB are independently programmable The micro controller must have all the timing parameters of the panel used for the monitor The parameters are to be store
9. GREDS PHS Posee _____ gt 8206 OREDS 0204 75 47 REDZ 48 EBLU7 1NA148 EREDIO 3 OREDIO 3 ADC AGND 0204 ADG AGND 52 53 EBLUS mi ERE EREDIA 7 56 EG NS R205 57 GHN5 VDDA 0205 75 R207 0 62 EGRNA BLUE 83 EGRNG 1N4148 64 EGRNZ 0206 6 HED7 VGA HSYNG ADC AGND 67 66666 2 68 1M4148 69 ERED EGANIO 3 OGRN 0 3 SDA 202 0 70 REDS 71 78 PVS R204 L74 HS EGRN 4 7 OGRN 4 7 HEADER 14 0207 75 75 PWR 144148 48 PDISPE 44 POLKA ADC AGND ADC AGND 45 R212 EBLU O 3 OBLU O 3 RxD lt gt pp 080 CLK n 100 op 3 55 884 192 U401D U401E OSD VREF OSD_HREF 7 10 n bir ar aad cess OSD DATA2 080 74LVT14 ADC 7ALVT14 ADC 080 DATAO cers HSYNC OS D201 58V OSD FSW ADC AGND ADC AGND 080 Reserved 1 4148 R229 R229 PSCAN Reserved RsT1 Let Zanl been Reserved reseted twice X 3 1 3 4 Reserved A ad NC Reserved SCAN INT serve ADC 78LVTI4 aioe Reserved Reserved TMI
10. 0C5 OG3 34 PD26 0 0C4 0C2 35 PD25 0 0C3 0C1 36 PD24 0 0C2 0C0 37 PD23 0 0L7 ORS 38 PD22 0 OR6 OR4 39 PD21 0 ORS OR3 42 PD20 0 OR4 OR2 46 PD19 0 OR3 ORI 47 PD18 0 OR2 ORO 48 PD17 0 EB7 EBS B7 B5 50 PD16 0 EB6 EB4 B6 B4 51 PD15 0 5 5 B3 52 PD14 0 EB4 EB2 B4 B2 53 PD13 0 EB3 EBI B3 81 54 PD12 0 EB2 EBO B2 80 55 PD11 0 EG7 EG5 G7 G5 56 PD10 0 EG6 EG4 G6 G4 57 PD9 0 5 EG3 G5 G3 62 PD8 0 EG4 EG2 G4 G2 42 Description EONA Name 2px clk 2pxl clk 1pxl clk 1pxl clk 8bit 6 bit 8 bit 6 bit TFT 63 PD7 0 EG3 EGI G3 CI 64 PD6 0 EG2 EGO G2 GO 66 PD5 0 ER7 EG5 R7 R5 67 PD4 0 ER6 ERA R6 R4 68 PD3 0 ER5 ER3 R5 R3 69 PD2 0 ERA ER2 RA R2 70 PDI 0 ER3 ERI R3 RI 71 PDO 0 EG2 ERO R2 RO 43 PdispE 0 This output provides a panel display enable signal that is active when flat panel data is valid 74 PHS 0 This output provides the panel line clock signal 73 PVS 0 This output provides the frame start signal 44 PCLKA 0 This output is used to drive the flat panel shift clock 45 PCLKB 0 Same as PCLKA above The polarity and the phase of this signal are independently programmable 75 Pbias 0 This output is used to turn on off the panel bias power or controls backlight 76 Ppwr 0 This output is used to control the power to a flat panel Table 5 Test Pins PIN Name Description 3 PSCAN I En
11. 103P 500V 80 20 Z5V PCS 99459F1033 6 CAP CER 104P 50V 10 X7R SMD 0805 6 PCS 99B26D104D 7 112 CAP CER 271P 50V 5 NPO SMD 0805 PCS 99B15E271D 8 C113 CER 301P 50V 5 NPO SMD 0805 PCS 99B15E301D 9 110 111 CER 332P 50V 10 X7R SMD 1206 2 PCS 99B26D332E 0 C114 CAP CER 102P 50V 10 X7R SMD 0805 PCS 9982601020 1 C117 C118 CAP ELEC 1000U 16V 20 105 C LOW ESR 2 PCS 28D37 1021 2 104 CAP ELEC 120U 400V 20 105 C 650mA 18 36 PCS 281D701211 3 106 CAP ELEC 150U 25V 20 105 C PCS 28147 1511 4 C119 CAP ELEC 470U 16V 20 105 C L0V ESR PCS 28D37 4711 5 C103 CAP 0 47U 300Vac 4 100 22 5 PCS 42A96 474G 6 124 CAP Y2 102P 250Vac 20 P 7 5 gt PCS 42077 102 7 101 102 115 Y2 222P 250Vac 4 209 7 5 3 PCS 42DT1 222F 8 1103 COIL CHOKE 5uH 5 20 RD005 PCS 45M56 509C 9 D104 D105 D108 D109 DIODE IN4148 75V 150mA SMD 4 PCS 15A2N41480 20 D102 D103 DIODE RLS245 SMD 2 PCS 15AHLS2450 21 D106 D107 DIODE SCHOTTKY MBR20100CT 100V 20A 2 PCS 15B3100CT6 DIODE SCHOTTKY MBRF20100CT 100V 20A 15B3201006 DIODE SCHOTTKY FCH20A10 100V 20A 15B320A106 DIODE SCHOTTKY SS20FJK10L 100V 20A 15B3JK10L6 22 10101 DIODE UF4005G 600V 1A PCS 1547400562 23 170102 DIODE ZENER RLZ18C SMD PCS 15735718 0 24 170101 DIODE ZENER RLZ20B SMD 1 PCS 1573572080 25 FOR COVER SCRE 3 20 10 2 pcs 6721430101 26 F101 FUSE T2A 250Vac SLOW BLOW PCS 49F54 202A 27 0105 IC AP431W D
12. 2 1 2P PLUG B2B XHA JST B2B XHA JS P3 1 33A 3278 3 1 3P PLUG B3B XHA JST B3B XHA JS C71 67A 305 3316 1 330uF 20 35V J2 88A 302 45 1 3 5mm P JACK SCJ 0356A B X SC Ji 88A 304 15 1 DC POWER JACK SCD 014A BY SC JP3 89A 171 27 A 1 DC POWER CORD 715A 851 2 1 LCD USB amp AUDIO BRD PARTS LIST OF AUDIO BOARD LOCATION AUPC780A1 P1 33A 3278 P2 33A 3278 33A 8009 VI 56A 572 61 172 R2 61 172 R3 61 172 R12 61A 172 R4 61 172 R10 61A 153M R11 61A 153M R7 61A 1751 R5 61A 1751 R6 61A 1751 C8 67A 309 CI 67A 309 C2 67A 309 C4 67A 309 C5 67A 309 C3 67A 309 VRI 75 3474 1 TIA 4114 D1 81A 2 J2 88A 302 90A 400 J003 95A 90 7004 95A 90 95A 8013 95A 8013 MIA 330 715A 799 12 103 5 103 5 333 5 681 5 683 5 1095 109 5 134 5 153 5 1535 1014 109 7 109 7 109 7 109 7 2223 103 5 25 32 45 23 23 22 32 6128 72 2T 2T 2T 2T 2T 2T 2T 2T 5G oo Quantit ee C RN SPECIFICATION 2P PLUG B2B XHA JST B2B XHA JS 2P PLUG B2B XHA JST B2B XHA JS 2 6 PIN DUAL ROW RIGHT ANGLE AN7522 BY PANASONIC 10K OHM 5 1 4W 10K OHM 5 1 4W 33K OHM 5 1 4W 680 OHM 5 1 4W 68K OHM 5 1 4W 1 OHM 5 3W 1 OHM 5 130K OHM 5 1 2 W 15K OHM 5 1 2W 15K OHM 5 1 2 W 100uF 20 25V Matshushita luF 20 50V luF 20 50V 20 50V 20 50V 2
13. 7 R9 10 VRMHNVA ROOJ A 2 SMD 060300 5 YAGEO 8 11 12 VRMCNV8 102F A 4 SMD 0805 1KQ 1 YAGEO 31 32 9 R13 14 VRMHNVA 752J A 2 SMD 0603 7 5 5 10 R15 16 VRMHNVA 433J A 2 SMD 0603 43KQ 5 YAGEO 11 R17 18 VRMHNVA 271J A 2 SMD 0603 2700 5 YAGEO 12 R27 VRMHNVA 472J A 1 SMD 0603 4 7 5 YAGEO 13 28 29 VRMHNVA 392J A 2 SMD06033 9KO 5 YAGEO 14 R23 24 VRMBNV4 102F A 4 SMD 1206 1KQ 196 YAGEO 25 26 15 R19 20 VRMCNV8 183F A 2 SMD 0805 18KQ 1 YAGEO 16 R21 22 VRMCNV8 133F A 2 SMD 0805 13KQ 1 YAGEO 17 R33 VRMHNVA 363J A 1 SMD 0603 36 5 YAGEO 18 Q1 TRANSISTOR VSTDTC144WKA A 1 SMD DTC144WKA ROHM 19 02 VSTDTA144WKA A 1 SMD DTA144WKA ROHM 20 Q3 5 VSTSST3904 A 2 SMD SST3904 T116 ROHM VSTMMBT3904 A E 21 04 6 VSTCEM9435A A 2 SMD CEM9435A CET 22 07 8 9 VST2SD2150 A 4 SMD 2SD2150 ROHM 23 1 2 CAPACITOR VCLFCN1EY224Z A 2 SMD 0805 0 22 yF 25V TDK 24 C3 4 9 VCLRCN1EB104K A 3 SMD 0805 0 1 uF 25V TDK 25 C5 VCEATU1EC336M 1 DIP UGX 33 yF 25V SANYO VCEATU1VC476M DIP UGX 47 yF 35V 25 SAMPO CORPORATION TROUBLE SHOOTING OF INVERTER DIVTL0037 D42 8 2 COMPONENTS LIST NO REF PART PART NUMBER QTY DESCRIPTION JSUPPLIER REMARK NAME 26
14. Display PIN f Name Description 98 HFS I Host Frame Sync Frames the packet on the serial channel 103 HCLK I Clock signal input for the 3 wire serial communication 99 HDATA IO Data signal for the 3 wire serial communication 100 RESETn I Resets the gmZANI chip to a known state when low 101 IRQ Interrupt request output 115 OSD HREF 5 output for an external OSD controller chip 116 OSD VREF IVSXNC output for an external OSD controller chip 117 OSD CIk Clock output for an external OSD controller chip 118 OSD Data0 I Data input 0 from an external OSD controller chip 119 OSD Datal I Data input 1 from an external OSD controller chip 120 OSD Data2 I Data input 2 from an external OSD controller chip 121 OSD Data3 I Data input 3 from an external OSD controller chip 122 OSD FSW External OSD window display enable Displays data from external OSD controller when high 123 11 IO Multi Function Bus 11 One of twelve multi function signals MFB 11 0 124 MFB10 Multi Function Bus 10 One of twelve multi function signals MFB 11 0 102 MFB9 Multi Function Bus 9 One of twelve multi function signals MFB 11 0 Also used as HDATA3 in a 4 bit host interface configuration 104 MFB8 Multi Function Bus 8 One of twelve multi function signals MFB 11 0 Also used as HDATA2 in a 4 bit host interface confi
15. GND for Red on the board Green 91 Green When using Sync On Green this signal also carries the sync pulse Green 90 N A Tie to Analog GND for Green on the board Blue 87 Blue Blue 86 N A Tie to Analog GND for Blue on the board HSYNC CS 150 Digital composite sync Not applicable for Sync On Green The gmZANI chip has three ADC s analog to digital converters one for each color red green and blue Table 10 summarizes the characteristics of the ADC Table 10 ADC Characteristics MIN TYP MAX NOTE RGB Track amp Hold Amplifiers Band Width 160MHz Settling Time to 1 2 8 5ns Full Scale Input 0 75V BW 160MHz Full Scale Adjust Range R G B Inputs 0 45V 0 95V Full Scale Adjust Sensitivity 1 LSB Measured ADC Output Zero Scale Adjust Range For a larger DC offset from an external video source the AC coupling feature is used to remove the offset Zero Scale Adjust Sensitivity 1 LSB Measured ADC Output ADC RGB Track amp Hold Amplifiers Sampling Frequency fs 20MHz 110MHz DNL 0 9LSB 80 MHz INL 1 5LSB fs 80 MHz Channel to Channel Matching 0 5LSB Effective Number of Bits ENOB 7 Bits fin 1MHz fs 80 MHz Vin 1db below full scale 0 75V Power Dissipation 400mW fs 110 MHz Vdd 3 3V Shut Down Current 100uA Guaranteed by design Independent of full scale R G B input The gmZ
16. L2 INPUT 9V LI OR I2 TO CHANGE Q7 amp Q8 amp C12 amp PTI 09 amp 010 amp 13 amp 2 FUNCTION TEST 27 SAMPO CORPORATION TROUBLE SHOOTING OF CHI MEI INVERTER DIVTL0037 D42 9 2 HIGHT VOLTAGE PROTECTION 1 SHORT R30 OPEN LOAD 2 TEST C14 INPUT POINT TO CHANGE ON VOLTAGE Vh 1600 100V rms PTI OR PT2 FUNCTION TEST OK 9 3 OUTPUT CURRENT ABNORMALITY 1 CHECK ON C6 FREQUNCY amp CHIP amp IC CPIP TO CHANGE ON C6 2 OSCILLATOR FREQUNCY CHIP OR IC CHIP RANGE 100 250 KHZ FUNCTION TEST OK 28 SAMPO CORPORATION TROUBLE SHOOTING OF INVERTER DIVTL0037 D42 9 4 ENBALE ABNORMALITY IF ENBALE ABNORMALITY 1 TO CHECK IC PIN 9 TURN NO FAIL TO CHANGE ON 01402 HAVE 12 VOLTAGES FUNCTION TEST OK 9 5 DIMMING CONTROL ABNORMALITY IF DIMMING ABNORMALITY TO CHECK RI amp R2 amp CO amp R33 HAVE BREAK TO CHANGE ON R1 OR R2 OR C6 amp R33 FUNCTION TEST OK 29 9 SAMPO CORPORATION TROUBLE SHOOTING OF CHI MEI INVERTER DIVTL0037 D42 9 6 TRANSFORMER ABNORMALIT Y IF TRANSFORMER ABNORMALITY TO CHECK C3 amp C4 CHIP OUTLINE OR TO CHANGE ON C3 amp C4 TRANSFORMER OR TRANSFORMER PASS FUNCTION TEST OK 10 INSTRUMENTS FOR TEST 1 DC POWER SUPPLY GPS 3030D 2 AC VIVM VT 181E 3 DIGITAL MULTIMERTER MODEL 34401 4 HIGHTVOLT PROB MODEL 1137A 5 SCOPE MODEL V 6545 6 AC mA METER MODEL 20
17. MLL4148 SMD FULL POWER D302 93A 64 32U 0 MLL4148 SMD BY FULL POWER D202 93A 64 32V 0 LL4148 GS08 SMD BY VISHAY D203 93A 64 32V 0 LL4148 GS08 SMD BY VISHAY D204 93A 64 32V 0 LL4148 GS08 SMD BY VISHAY D205 93A 64 32V 0 LL4148 GS08 SMD BY VISHAY D206 93A 64 32V 0 LL4148 GS08 SMD BY VISHAY D207 93A 64 32V 0 LL4148 GS08 SMD BY VISHAY D301 93A 64 32V 0 LL4148 GS08 SMD BY VISHAY D302 93 64 32 0 114148 6508 SMD BY VISHAY 715 820 3 1 TF1780 MAIN BOARD 125 X 13 70 PARTS LIST OF KEY PC BOARD LOCATION KEPC780EK Quantity SPECIFICATION 101 9A 308 1 PIN TP102 9A 308 1 PIN J7 33A 3252 3 WAFER 3P 3 96mm 90 40A 152 44 LABEL KEPC780EK Q101 57A 419 PPT Q102 57A 419 PPT R101 61A 6021 0352 T 10K OHM 5 1 6W R102 61A 6021 0352 T 10K OHM 5 1 6W R103 61A 6021 0352 T 10K OHM 5 1 6W R104 61A 6021 0352 T 10K OHM 5 1 6W R105 61A 6021 0352 T 10K OHM 5 1 6W R106 61A 6021 0352 T 10K OHM 5 1 6W R107 61A 6021 0352 T 10K OHM 5 1 6W R108 61A 6022 2152 T 220 OHM 5 1 6W C101 65 450 1047T 0 1Uf 80 20 56V Y5V SWI 77 600 1G TACT SWITCH SW2 77 600 1G TACT SWITCH SW3 77A 600 1G TACT SWITCH SWA 77 600 1G TACT SWITCH SW5 77A 600 1G TACT SWITCH LEDI 81A 13 1B LED 5 7 mmBL RYG202N JP2 88A 304 15 DC POWER JACK SCD 014A BY SC J101 95A 90 23 TIN COATED 95A 8014 96 HARNESS 715A 1778 1 1780 LCD K B 71 PARTS LIST OF DC POWER BOARD LOCATION DCPC780A3 Quantity SPECIFICATION P4 33A 3278
18. So in dos mode just set your CLOCK in OSD MENU to zero or use some EDITOR software which can full fill the whole screen ex PE2 HE and then press AUTO Or you can use DOSI EXE which attached in your Driver disk to optimize DOS mode performance V THE PANEL LUMINANCE WAS DOWN Use white pattern and resolution 1280x1024 60Hz CHROMA 7120 measured the center of panel Set Contrast brightness maximal RGB 50 If Y can reach gt 190 cd m2 that means Quit from OSD screen measured Y luminance The lamp still working well so we just re do the With chroma 7120 check Y2 240 10 CD M2 white balance process As following procedure Adjust VR201 until maximal measured Y Use white pattern press MENU button along 240410 cd m2 with AC power plug in you will in factory mode The OSD menu will be at left top of screen If the Y less than 160 cd m2 after the VR201 MAX contrast brightness max then change the LAMP of panel press AUTO button to automatically adjust blacklevel value you will see the sign PASS if FAIL manual adjust the blacklevel until value 43 Set contrast brightness to max and turn the VR201 to max wait for 20 minutes until the luminance Y stable The Y should be larger than 200 cd m2 for panel which already use for a year the Y luminance might be a little down around 180 cd m2 there is acceptable too Follow this manual page 7 item 4 2 method to more detail procedure for do a whit
19. Straight Line might be stuck in Red Green Blue That symptom is cause by bad Panel issue might be the Source IC from Panel is cold solder or open loop so REPLACE THE PANEL TO NEW ONE KEYBOARD BLOCK check Check U302 MCU pin 43 42 41 40 39 at High state 5V without press any key NG Mechanical was stuck Check Replace Tact switch SW105 at keyboard if still no work replace U302 MCU at main board and Press power key and check U302 pin 43 check MCU relative reset circuit and crystal low 0V Check U302 pin 38 LED green will have transition from hi to low or low to hi when we press the power key If still no Led green indicator check Q102 R106 amp LED at keyboard cold solder or bad NG MCU no response Check U302 pin 20 20MHz and pin 44 l VDD 5V 7 and 10 reset 0V 7 at normal If one of this item was NG check the relative circuit condition Keep transition that means eeprom no response Without press key and change mode Check U302 NG pin 16 17 sda scl hi 5V or keep transition Check U300 eeprom 24LC04 relative circuit check U300 pin 7 low NG Check JP202 is Check U300 pin 8 connect vdd 5V and check R300 R301 cold solder Replace eeprom OK no keep transition Replace U302 MCU POWER BLOCK check Note the Waveform of U304 pin 2 can determined the power situation 1 stable rectangle wavefor
20. adj 5 max 5 5 6 0 6 5 mA 940120 0 Frequency 40 50 60 KHZ H V open Vopen 1400 1500 1600 Vrms INO LOAD H V Load Vload 630 730 830 Vrms RL 120KQ 6 FUNCTION LOAD CIRCUIT SYMBOL Vin 12V Vin 12V ON OFF Dimming GND 23 SAMPO CORPORATION TROUBLE SHOOTING OF INVERTER DIVTL0037 D42 7 CIRCUIT DIAGRAM CEM4431 CEM4431 Vin ON OFF il O pe _ DIMMING GND TS Q SAMPO CORPORATION TROUBLE SHOOTING OF CHI MEI INVERTER DIVTL0037 D42 8 PART LIST 8 1 COMPONENTS LIST REF PART PART NUMBER DESCRIPTION SUPPLIER REMARK 1 CONNECTOR VCNCP0015 EJSTA 1 S5B PH SM3 TB JST 2 CON2 3 VCNCP0014 PJSTA 2 5 04 4 0 5 1 JST VCNCP0014 ZGLEA GL SM02 4 0 WH2 GEAN LEA 3 81 2 RESISTOR VRMHNVA 103J A 2 SMD 0603 10KQ 5 YAGEO 4 R84 VRMHNVA 683J A 2 SMD 0603 68KQ 5 YAGEO 5 R56 VRMHNVA 912J A 2 SMD 0603 9 1 596 YAGEO 6 87 8 VRMHNVA 274J A 2 SMD 0603 270KQ 5 YAGEO
21. an external oscillator leave this pin floating If using an external crystal connect crystal between TCLK 141 and XTAL 142 See 5 107 143 PLL RVDDA Analog power for the Reference DDS PLL Must be bypassed with a 0 1 capacitor to pin 144 PLL RGNDA 144 PLL RGNDA Analog ground for the Reference DDS PLL Must be directly connected to the analog system ground plane 145 Reserved For testing purposes only Do not connect 146 SUB RGNDA Dedicated pin for the substrate guard ring that protects the Reference DDS Must be directly connected to the analog system ground plane 148 VSYNC I Vsync input TTL Schmitt trigger input 149 SYN VDD Digital power for CRT Sync input 150 HSYNC CSYNC I Hsync or CRT composite sync input TTL Schmitt trigger input 41 Table 4 TFT Panel Interface BENT Name Uo 2px clk 2pxl clk ile 8bit 6 bit 8 bit 6 bit TFT 6 PD47 0 081 7 PD46 0 080 9 PD45 0 0C1 10 PD44 0 0C0 13 PD43 0 ORI 14 PD42 0 ORO 15 PD41 0 EBI 81 16 PD40 0 EBO 80 17 PD39 0 EGI Gl 19 PD38 0 EGO GO 20 PD37 0 ERI RI 22 PD36 0 ERO RO 23 PD35 0 5 24 PD34 0 086 084 25 PD33 0 085 083 26 PD32 0 084 082 27 PD31 0 083 OBI 28 PD30 0 082 080 29 PD29 0 0C7 0C5 31 PD28 0 0C6 0C4 32 PD27 0
22. analog system ground plane 128 DAC DVDDA Analog power for Destination DDS DAC Must be bypassed with a 0 luF capacitor to pin 127 DAC DGNDA 129 PLL DVDDA Analog power for the Destination DDS PLL Must be bypassed with a 0 1 capacitor to pin 131 DGNDA 130 Reserved For testing purposes only Do not connect 131 PLL DGNDA Analog ground for the Destination DDS PLL Must be directly connected to the analog system ground plane 132 SUB DGNDA Dedicated pin for the substrate guard ring that protects the Destination DDS Must be directly connected to the analog system ground plane 133 SUB SGNDA Dedicated pin for the substrate guard ring that protects the Source DDS Must be i directly connected to the analog system ground plane 134 PLL SGNDA Analog ground for the Source DDS PLL Must be directly connected to the E analog system ground 135 Reserved For testing purposes only Do not connect 136 PLL SVDDA Analog power for the Source DDS DAC Must be bypassed with 0 10L capacitor to pin 134 PLL SGNDA Analog power for the Source DDS DAC Must be by passed with a 0 1 137 SVDDA capacitor to pin 138 DAC_SGNDA 138 DAC_SGNDA Analog power for the Source DDS DAC Must be directly connected to the analog system ground 139 SVDD Digital power for the Source DDS Must be bypassed with a 0 1uF capacitor to digital ground plane 141 TCLK I Reference clock TCLK input from the 50 MHz crystal oscillator 142 XTAL O jlfusing
23. ensure firm grounding The connector information is as follow 5V power from VGA card GND SYNC GND SDA HORIZ SYNC VERT SYNC SCL Apply power to the display by turning the power switch to the ON position and allow about thirty seconds for Panel warm up The Power On indicator lights when the display is on With proper signals feed to the display a pattern or data should appear on the screen adjust the brightness and contrast to the most pleasing display or press auto key to get the best picture quality This monitor has power saving function following the VESA DPMS Be sure to connect the signal cable to the PC If your LM700 LCD monitor requires service it must be returned with the power cord amp Adapter 4 ADJUSTMENT 4 1 ADJUSTMENT CONDITIONS AND PRECAUTIONS 4 2 Adjustments should be undertaken only on following function contrast brightness focus clock h position v position red green blue since 6500 color amp 7800 color ADJUSTMENT METHOD Press MENU button to activate OSD Menu or make a confirmation on desired function Press Left Right button to select the function or done the adjustment H 60KHz x III gt Contrast Ei ovo Be 70 3 x Rd 65 78 White Balance Luminance adjustment Approximately 30 minutes should be allowed for warm up before proceeding white balance adjustment Before started adjust w
24. from a single reference oscillator Auto Configuration Auto Detection Phase and image positioning Input format detection Operation Modes Bypass mode with no filtering Multiple zoom modes With filtering With adaptive ACE filtering Integrated On Screen Display On chip character RAM and ROM for better customization External OSD supported for greater flexibility Supports both landscape and portrait fonts Many other font capabilities including blinking overlay and transparency 38 13 Pin Description Unless otherwise stated unused input pins must be tied to ground and unused output pins left open Table 1 Analog to Digital Converter PIN f Name Description 77 ADC VDD2 Digital power for ADC encoding logic Must be bypassed with 0 1uF capacitor to pin 78 ADC GND2 78 ADC GND2 Digital GND for ADC encoding logic Must be directly connected to the digital system ground plane 79 ADC VDDI Digital power for ADC clocking circuit Must by passed with O 1uF capacitor to pin 80 ACD GNDI 80 ADC GNDI Digital GND for ADC clocking circuit Must be directly connected to the digital system ground plane 81 SUB GNDA Dedicated pin for substrate guard ring that protects the ADC reference system Must be directly connected to the analog system ground plane 82 ADC GNDA Analog ground for ADC analog blocks that are shared by all three channels Incl
25. if that 2 functions failed the H V position will be failed too Adjust the four edge until all four edges are visible at the edge of screen 5 MULTI LANGUAGE function There have 5 language for selection press MENU to selected and confirm press LEFT RIGHT to change the kind of language English Deutch Francais Espanol Italian 6 Reset function Clear each old status of auto configuration and re do auto configuration for all mode This function also recall 7800 color temperature if the monitor status was in Factory mode this reset function will clear Power on counter backlight counter too 7 OSD LOCK function Press Left amp Right key during switching on the monitor the access to the OSD is locked user only has access to Contrast Brightness Auto key If the operator pressed the Left amp Right during switching on the monitor again the OSD is unlocked 8 View Power on counter and reset the Power on counter if not necessary no suggest to entry factory mode The Power on counter was used to record how long the backlight of panel already working the backlight life time was guarantee minimal 25000 hours the maintainer can check the record only in factory mode Press MENU button for 2 seconds along with plug in DC power cord will be in factory mode and the OSD screen will located at left top of panel but take cautions don t press icon 78 amp 65 if you press 78 65 your whit
26. mode and back to user mode Press both Left amp Right button along with Power button off to on once will activate the OSD LOCK function repeat this procedure will disable OSD LOCK In OSD LOCK function all OSD function will be lock except Contrast and Brighness OSD INDEX EXPLANATION CABLE NOT CONNECTED Signal cable not connected INPUT NOT SUPPORT a INPUT frequency out of range H gt 81kHz v gt 75Hz or H lt 28kHz lt 55Hz b INPUT frequency out of VESA spec out of tolerance too far UNSUPPORT mode try different Video card Setting Input frequency out of tolerance but still can catch up by our system if this message show that means this is new user mode AUTO CONFIG will disable THE Different on MAINBOARD or other ACCESSORY when using different PANEL type 1 The MCU software should be change example for CHI MEI panel the MCU part number is 56A 1125 61 M for Hyundai panel the MCU part number is 56A 1125 61 Y and the other ACCESSORY when use different panel type should be change as following 1 2 The INVERTER module for CHI MEI panel part number is 79AL17 1 S for Hyundai panel the INVERTER part number is 79A L17 3 S The cable to Panel side for CHI MEI panel part number is 95 8018 30 1 for HYUNDAI panel is 95 8018 30 3 3 The Dsub cable for CHI MEI is 89A 174D 5BF GLF for Hyundai is 89A 174 L17 3 4 The Mechanical accessory is change or adding as follow CHI MEI PA
27. shooting chart I NO VOICE OUTPUT Plug out the DC power make sure the monitor is in OFF status Use OHM METER measure U1 pin 2 4 channel A is speaker well connected Measure pin 10 12 channel B is speaker well connected YES Plug in the DC power set the monitor ON status Check U1 pin 1 12V YES Check Ul is work properly Check U1 pin 5 standby bias voltage around 4 V YES Check VI pin 9 volume bias around I V 2 YES Check Audio cable and J4 is well connected 36 NG NG NG NG Check J1 J2 is well connected Measured J2 pin 4 5 amp 2 3 is well connected Check is speaker open circuit Check R10 R11 amp J5 S1 is open circuit Check R7 1 Check R4 is open circuit SOUND DISTORTION NG Check U1 pin 2 410 12 is the voltage output VCC 2 Check U1 CHECK SPEAKER AUDIO BOM Bill Of Materias September 7 2001 18 09 14 Pagel Item Quantity Reference Pat 1 3 C1C2C4 2 1 C3 22004 25 3 1 C5 10uF 50V 4 2 C6C7 0 047uUF 5 1 C8 100UF 16V 6 1 C9 100UF 25V 7 l 01 LED 8 2 J1J3 CON2 9 1 J2 EAR PHONE 10 1 J4 AUDIO IN ll l 15 DCIN 12 3 VRIRIR2 10K 13 1 R3 33K 14 1 R4 68K 15 2 R5R6 15K 16 1 7 130K 17 2 R9R8 3K 18 2 RILRIO 1 3W 19 1 812 680 20 1 51 SW SPST 21 1 Ul AN7522 37 GMZANI The gmZAN device utilizes Genesis patented third generation Advanced Image Magnifica
28. to 57MHZ PVS 60 09Hz PHS around 67 KHz refer to input signalz640x480 60 Hz 31k and LED is Replace GMZANI U200 or replace MAINBOARD green If MainBoard being replace please do the content reprogrammed II a THE SCREEN is Abnormal stuck at white screen OSD window can t appear but keyboard amp LED was normal operation At general this symtom is cause by missing panel data or panel power so we must check our wire harness which connected to panel or the panel power controller U202 NG Check if the Wire harness from CN601 amp CN602 loose Check the wire on both Panel side and Mainboard side Yes tight enough Check the Panel Power circuit as above page 15 0202 pin 5 6 7 8 must be 5V Yes Voltage normal Check the LVDS Power L603 L604 L601 L602 L900 3 3V 2 V204 which convert thie Yes Voltage normal Check U200 DATA OUPUT block as Check the both U601 amp 0602 LVDS Input pin 31 45mhz above page 15 65mhz and pin 27 Vsyn pin 28 45khz 65 khz NG no data output Check OSCILLATOR Block as above page 15 all clock is normal Yes Frequency normal Replace both LVDS chip U601 amp U602 Replace U302 MCU and check it RESET pin 10 must be turn high to low when first AC power on OK reset is normal Check U200 DATA OUTPUT block again NG still no data out Replace U200 GMZANI II b The screen had the Vertical
29. with frequency 30K 80Khz 7mA 9Ma Main board Block diagram Input analog RGB amp H V amp ddc signal amp Rs232 communication GMZANI U200 Data Digital RGB DDC chip LVDS chip U601 U602 Panel Control Signal Dhs Dvs Dclk Oscillator 50 mhz Panel Power 5V Communication signal Hclk Hfs Hdata0 Panel Power Control MCU U302 U202 Crystal 20 mhz DC 12V 5Amp Keyboard module INVERTER module EXTERNAL ADAPTER 5 4 SOFTWARE FLOW CHART I Power On Subrotine CHART POWER ON START Initial MCU I O Interrupt vector amp Ram Yes l Initial 1 POC backlight counter Check Eeprom is emptv 2 2 Clr all mode value No Check White balance data 6500 amp 7800 same with the backup data Check POC backlight counter data same with the backup data IF not same overwrite the data with backup value Check Previous power switch status from Eeprom amp other system status Initial GMZANI Check if in Factory mode when power on press the MENU Button will be in FACTORY mode SET factory mode flag No Clear factory mode flag MAIN SUBROTINE LOOP II MAIN SUBROTINE LOOP Main loop start Process Power saving status according to below flow chart result Check GMZAN status is change or not And check Signal cable status cable not connected or not FM is the register which measured the HSYN amp Vsyn
30. 0 HEADER 14 TXIN21 PLLVCC 7 1602 TXIN22 C607 _ C608 BEAD120 0603 TXIN16 PLLGND 10uF 0 01UF TXIN17 PLLGND 16V EBLU O 7 TXIN23 TXIN24 GND TXIN25 GND TXIN26 GND GND TXCLKIN TXOO TX0 O ODD U602 NT7181 TSSOP56 OREDIO 7 2 gt TXINO PWRDWN TXIN1 T Poo POr TXINS TXOUTO TXl O TXO2 TXINA TLOUTI TXO3 TXING ROUTES TX2 0 TXO4 TXIN27 TXOUT2 TX2 0 TXOS TXINS TXOUT2 TX3 0 TXOB OGRN O 7 END UD T3330 TXO9 UT3 AVDD 3 3 A TXIN9 TXIN12 TXCLKOUT TXIN13 TXCLKOUT TXIN14 TXIN10 TXINTO NT AVDD 3 3 OBLU O 7 L603 U904 TXIN15 LVDSGND 120 0603 171117 TXIN18 LVDSGND IN OUT L900 TXIN19 LVDSGND TXIN20 BEAD 120 lt TXIN21 1604 TXIN22 TXIN16 PLLGND BEAD120 0603 3 5 TXIN17 PLLGND TXIN23 TXIN24 GND TXIN25 GND TXIN26 GND GND TXCLKIN GND GND Top Victory Electronics Co Ltd itle LVDS Document Number ustom 715A820 1 Date Tuesday July 10 2001 Sheet
31. 104 104 104 104 104 104 104 104 104 104 104 104 104 104 104 104 104 104 104 104 104 104 104 104 104 104 104 104 104 104 104 104 104 104 104 104 104 104 330 330 330 102 102 100 100 100 100 3 100 3 1013 1013 1013 1013 1013 1013 1013 1013 69 32 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 31 31 31 8T 8T 3 3 3 SPECIFICATION CHIP 0 01UF 50V X7R CHIP 0 1UF 16V X7R CHIP 0 1UF 16V X7R CHIP 0 1UF 16V X7R CHIP 0 1UF 16V X7R CHIP 0 1UF 16V X7R CHIP 0 1UF 16V X7R CHIP 0 1UF 16V X7R CHIP 0 1UF 16V X7R CHIP 0 1UF 16V X7R CHIP 0 1UF 16V X7R CHIP 0 1UF 16V X7R CHIP 0 1UF 16V X7R CHIP 0 1UF 16V X7R CHIP 0 1UF 16V X7R CHIP 0 1UF 16V X7R CHIP 0 1UF 16V X7R CHIP 0 1UF 16V X7R CHIP 0 1UF 16V X7R CHIP 0 1UF 16V X7R CHIP 0 1UF 16V X7R CHIP 0 1UF 16V X7R CHIP 0 1UF 16V X7R CHIP 0 1UF 16V X7R CHIP 0 1UF 16V X7R CHIP 0 1UF 16V X7R CHIP 0 1UF 16V X7R CHIP 0 1UF 16V X7R CHIP 0 1UF 16V X7R CHIP 0 1UF 16V X7R CHIP 0 1UF 16V X7R CHIP 0 1UF 16V X7R CHIP 0 1UF 16V X7R CHIP 0 1UF 16V X7R CHIP 0 1UF 16V X7R CHIP 0 1UF 16V X7R CHIP 0 1UF 16V X7R CHIP 0 1UF 16V X7R CHIP 0 1UF 16V X7R CHIP 0 1UF 16V X7R CHIP 0 1UF 16V X7R CHIP 0 1UF 16V X7R CHIP 0 1UF 16
32. 16 YOKOGAWA 30 6 C ADAPTER MODULE Trouble shooting chart The following spec amp block diagram is offer by CHI SAM for External Adapter part number 80AL17 1 CH Black 80AL17 2 CH White AC ADAPTER CH 1205 TROUBLE SHOOTING NO VOLTAGE CHECK BD101 NO REPLACE AC VOLT I P OK SS F101 NO REPLACE CHECK BD101 V 7 50101 DC VOLT O P CHECK R115 D103 U101 NG 2 CHECK U101 PIN7 12 15 4 NO CHECK C110 U101 CHECK 0101 PIN FREQ 50 70KHZ OK 2 NO CHECK 0101 PIN G amp PIN D WAVE OK CHECK 0106 D107 0102 U103 31 I Adapter Schematic CH 1205 Please see the ADAPTER SCHEMATIC in the end of this Document page 75 32 IV ADAPTER BOM LIST PART 80AL15 2 L I ItemReference Part Quantity Cat 1 IBD101 DIODE BRIDGE KBL405G 600V 4A PCS 15D7L405G6 2 KNIOI AC POWER SOCKET PCS 64P21 0001 3 BEADI BEAD2 BEAD3 BEAD4 BEAD 3 5 3 2 1 6mm 4 PCS 62 353216 4 116 CAP CER 102P 500V 10 5 PCS 9942641025 5 105 CAP CER
33. 200uF 20 16V VR 10K OHM 9mm 30 12 PUSH SW PS02 BAN LED LAMP GREEN CSL 310G3GT 3 5mm P JACK SCJ 0356A B X SC HEAT SINK TIN COATED TIN COATED HARNESS 2P HARNESS 3P 2P SCREW M3X6mm 17 LCD AUDIO BOARD 76 0 X 1 9 POWER SYSTEM AND CONSUMPTION CURRENT ADAPTER MODULE INVERTER MODULE Input AC 110V 60Hz 240V 50Hz Input DC 12V Output DC 12V 5A Output AC 1500V 30K 80KHz Current 14mA Main board power system LM2596S 5 12V to 5V SA SPEC To CPU Eeprom 24c21 control inverter on off 860mA when Cable not Connected 841mA when Normal operation To Chi Mei Panel around 1250mA AIC1084 5V to 3 3V SA SPEC LT1117 5V to 3 3V 800mAspec for LVDS consumption for GMZANI consumption 73 10 PCB LAYOUT LVDS power LT1117 Pore mg 1203 524 098 Uum Bm E MM iy ses 6 Input Connector 2719 S oet prt m oz AIC1084 5V to 3 3v 01 05 20 Panel T ET gt gt CHB mm Power wa 1604 Control ton S pags 245 wib 031 Hip 5 a pyg ho 1 C305 VR adjust for LM2596 convert 12V to 5V Keyboard connector 4 o Lamp Luminance Inverter connector MCU 74 D TOP LEVEL FLOW POWER Power b
34. 3 PCS 76455 0010 76 FOR CNIOI SRK TUBE 54 0 9cm 1 PCS 57705 0090 77 Q101 D107 D106 SRK TUBE 6 16mm 3 PCS 57706 0160 78 FOR C105 SRK TUBE 8 15mm 1 PCS 57708 0150 79 FOR R125 SRK TUBE 8 22mm 1 PCS 57708 0220 80 L101 Toroidal choke coil 2mH TN12 7 7 9 3 5 RD009 1 PCS 45 36 502L 81 0102 NPN 25 4505 400V 0 1A SMD 1 PCS 1402964505 82 0103 0105 NPN C2412K 50V 0 15A SMD 2 PCS 14C2C2412K 83 0104 PNP A1037AK 50V 0 15A SMD PCS 14A21037AK 84 VARIOI VARISTOR SAS 471KD07 74 1 PCS 27111 0001 85 TIOI X FORMER PWR PQ2620 FOR CH 1205 RD010 1 PCS 47810 0040 34 FRONT HEATSINK TCR 05 15 25 ASAHI PCS 85011 0001 FRONT HEATSINK TCR 10 10 20 PCS 85100 0001 SMIRI 1L 35 40mm PCS 80400 0001 FRONT COVER 129 3 63 8 19 34mm PCS 0810400020 BASE COVER 129 3 63 8 18 7mm PCS 0820400020 T E E 2 5 5 02 5 PCs 561807811 FRONT HEATSINK FOR CH 1205 PCS 75170 0060 BOTTOM HEATSINK FOR CH 1205 REV C PCS 75170 005 FRPP FOR CH 1205 BOTTOM HEATSINK PCS 80300 0020 LED HOLDER 5 10 PCS 71720 0010 RATING FOR CH 1205 REV C PCS 0643C00026 15 4mm FOR CH 1205 REV A PCS 0643000031 FOR D106 D107 SILICON RUBBER COVER TO 220ST B 2 PCS 80100 0001 35 6 D AUDIO MODULE Trouble
35. 300P NPO 8125 0 39 2W W W U102 H11A817C300 C112 270P NPO 07 100CT HS101 HEATSINK BEAD3 BEAD 8141 270 1 4W 8140 9 31K 196 1000U 16V C117 D108 1N4148 R145 C118 1000U 16V 12K 1 4W C119 470UA6V U104A 10358 8139 330 1 4W 4 4 2 C121 0 APPROVAL R136 113K 1 LED101 LED U105 AP431W SMD U103 CM431 0 5 72 CHECK BY CH 1205 Document Number Doc Monday July 23 2001 13 AUDIO SCHEMATIC DIAGRAM U1 AN7522 22Q0uF 25V gt 1UF 5OV GND C5 10uF 50V C6 GND 0 047uF C8 EAR PHONE R8 3K GND GND 100uF 16V S1 SWSPST J5 o o 1 2 C9 R12 C IM 100uF 25V 680 V GND D1 LM700A Audio 1 5W X2 Document Number Doc lt ReyCode gt Friday April 27 2001
36. 35V C941 0 1 uF V GND POWER Block 470uF 16V GND AIC 1084 C310 C312 330 uF 35V 330 uF 35V Distribute throughout digital Gnd plane TP701 TP702 TP703 TP704 TP705 TP706 GND GND GND GND GND GND o E T e T T El AOC Top Victorv Electronics Co Ltd GND Size Document Number Rev a 715A820 1 8 Date Tuesdav Julv 10 2001 F101 2A 250V C101 CY 2200P 250V 12 R101 NTCR 3 5A vani _ 1 4 1 R102 470K 1 4W L102 18mH BD101 KBL405G ADAPTER SCHEMATIC CH 1205 C104 120U 400V C102 CY 2200P 250V C103 0 47U 300V R103 470K 1 4W R116 4 7K 1 4W C124 CY 1000P 250V T 0 1U Q103 104 C2412K 4 7K 1 4W R107 180K 1 4W R108 180K 1 4W ZD101 RLZ20B D109 IN4148 R109 180K 1 4W R110 180K 1 4W Q102 25 4505 0102 RLS245 103P 500V 8111 43K 3W MOF C116 1000P 500V C105 T101 PQ2620 for CH 1205 BEAD 1 BEAD D101 UF4005G R130 24 1 4W R132 24 1 AW R131 24 1 4W D106 MBR20100CT 2 R133 24 1 4W 8114 100 1 4W R115 15 1 4W C115 CY 2200P 250V BEAD 4 BEAD D105 1N4148 C106 TR 150U 25V Q104 A1037AK HS101 HEATSINK L II Q101 25 2996 R123 150 1 4W R127 10K R126 510 C113
37. 6W R201 61A 0603 000 CHIP 0 OHM 1 16W R202 61A 0603 000 CHIP 0 OHM 1 16W R203 61A 0603 000 CHIP 0 OHM 1 16W R207 61A 0603 000 CHIP 0 OHM 1 16W R208 61A 0603 000 CHIP 0 OHM 1 16W R229 61A 0603 000 CHIP 0 OHM 1 16W R317 61A 0603 000 CHIP 0 OHM 1 16W R340 61A 0603 000 CHIP 0 OHM 1 16W R603 61A 0603 000 CHIP 0 OHM 1 16W R905 61A 0603 000 CHIP 0 OHM 1 16W R218 61A 0603 101 CHIP 100 OHM 1 16W R219 61A 0603 101 CHIP 100 OHM 1 16W R220 61A 0603 101 CHIP 100 OHM 1 16W R227 61A 0603 101 CHIP 100 OHM 1 16W R213 61A 0603 102 CHIP IKOHM 1 16W R214 61A 0603 102 CHIP 1 16W R216 61A 0603 103 CHIP 10K OHM 1 16W R217 61A 0603 103 CHIP 10K OHM 1 16W R223 61A 0603 103 CHIP 10K OHM 1 16W R224 61A 0603 103 CHIP 10K OHM 1 16W R225 61A 0603 103 CHIP 10K OHM 1 16W R300 61A 0603 103 CHIP 10K OHM 1 16W R301 61A 0603 103 CHIP 10K OHM 1 16W R311 61A 0603 103 CHIP 10K OHM 1 16W R313 61A 0603 103 CHIP 10K OHM 1 16W R315 61A 0603 103 CHIP 10K OHM 1 16W R326 61A 0603 103 CHIP 10K OHM 1 16W R327 61A 0603 103 CHIP 10K OHM 1 16W R328 61A 0603 103 CHIP 10K OHM 1 16W R329 61A 0603 103 CHIP 10K OHM 1 16W R209 61A 0603 202 CHIP 2K OHM 1 16W R210 61A 0603 202 CHIP 2K OHM 1 16W R204 61A 0603 750 CHIP 75 OHM 1 16W R205 61A 0603 750 CHIP 75 OHM 1 16W R206 61A 0603 750 CHIP 75 OHM 1 16W C229 65A 0603 103 32 CHIP 0 01UF 50V X7R C230 65A 0603 103 32 CHIP 0 01UF 50V X7R C231 65A 0603 103 32 CHI
38. 85 C SMD SOT 23 PCS 171AP431WD 28 U104A IC BA10358F SMD PCS 171A10358F 29 U101 C CM3842 PCS 1700 3842 30 10103 CM431 PCS 17000CM431 3l 0102 C H11A817C PCS 17011A817C 32 1101 JUMPER 0 69 8 12 5mm PCS 54J B5 0005 34 1104 JUMPER 0 6 9 8 22 5mm PCS 54J B5 0009 35 1103 1105 1106 JUMPER 0 69 8 5mm 3 PCS 54J B5 0002 36 1102 JUMPER 0 69 8 7 5mm PCS 54J B5 0003 37 LEDIOI LED L 34GD TYPE GREEN PCS 1903112011 38 102 LINE FILTER 18mH UU15 7 RDOO2 PCS 47E10 0010 39 0101 05 FET 25 2996 600V 10A 1 PCS 14K1SK2996 OS FET2SK2761 01MR 600V 10A 14K1SK2761 05 FET 2SK2843 600V 10A 14K1SK2843 40 16101 TCR 3 OHM 5A 109 15 PCS 26B2L50011 33 41 PCB FOR 1205 REV D 1 PCS 11843 0030 42 117 RES 100 1 8W 5 SMD 0805 1 PCS 2242510000 43 109 1110 RES 0 OHM 1 4W 4 59 SMD 1206 2 PCS 2243500000 44 5143 RES 1 8K 1 8W 5 SMD 0805 1 PCS 2242518010 45 2114 RES 100 1 4W 5 SMD 1206 1 PCS 2243510000 46 8124 8127 RES 10K 1 8W 4 59 SMD 0805 2 PCS 2242510020 47 R136 RES 113K 1 8W 1 SMD 0805 1 PCS 2242111330 48 8145 RES 12K 1 4W 5 SMD 1206 1 PCS 2243512020 49 8128 RES 13K 1 8W 5 SMD 0805 1 PCS 2242513020 50
39. ALLES 1140X1 WOODEN FLAT PALLES 1140X1 EPS CUSHION L EPS CUSHION R CARTON AOC BASE SHEET PE BAG PE BAG CLIP BAG ALUMINIUM TAPE 35X25 50CM X 500MX X 0 017MMt DRIVER DISK SPEAKER 16 OHM 2W 30 70 INVERTER BY SAMPO ADAPTOR WHITE SHIELD CBPC SHIELD INVERTER SOFT SHIELD SOFT SHIELD SOFT SHIELD SOFT SHIELD AUDIO CABLE SIGNAL CABLE POWER CORD HARNESS 2P 75mm HARNESS HARNESS SCREW 3X5mm SCREW 3X5 mm SCREW 3X8mm SCREW 3X8 mm SCREW M3X6mm SCREW M3X6mm SCREW M3X6mm SCREW M3X10mm SCREW 12mm SCREW 3X8mm SCREW 4X12mm SCREW 4X16mm LOCATION PARTS LIST OF CABINET continue T780KMGHBAA0A QIA QIA QIA 750A 1030 10128 1030 12128 1030 12128 LCD 170 3 66 SPECIFICATION SCREW SCREW 3X12mm SCREW 3X12mm LCD PANEL M170E1 01 BY CHI MEI LOCATION CN303 CN302 CN602 CN601 R319 JP201 JP303 CN200 U302 C307 C309 C310 C312 C927 C928 C945 FB301 T300 T300 L905 VR501 X300 U201 CN301 CBPC780GM 33A 3802 33A 3802 33A 3802 33A 3802 33A 8009 33A 8009 33A 8009 33A 8810 33A 8013 40A 152 44A 3231 56A 1125 67A 305 67A 305 67A 305 67A 305 67A 305 67A 305 67A 309 71A 55 73A 253 73A 253 73A 259 75 335 90A 372 93A 22 93A 22 95A 9001 5H 9H 10H 14H 2 3 3 2 14 43 8 61 331 331 331 331 331 331 471 28 108 108 103 55 57 6A 67 lt dv PAR
40. AM is divided into a font storage area and a character code storage area For example 64 fonts can be stored in RAM and an OSD window of 768 characters such as 24x32 can still be displayed The first address of SRAM to be read for the first character displayed upper left corner of window is also programmable with an address resolution of 16 8 bits as the top bits of the 12 bit SRAM address The character code is a 12 bit value used as follows D6 0 font map select this is the top seven bits of the address for the first line of font bits D8 7 Background color 00 bcolor0 Ol bcolori 10 bcolor2 11 transparent background D10 9 Foreground color 0 1 2 or 3 Dil Blink enable if set to 1 otherwise no blink Although the OSD color map has room for sixteen colors only seven are used by the internal OSD three background colors and four foreground colors The blink rate is based on either a 32 or 64 frame cycle and the duty cycle may be selected as 25 75 50 50 or 75 2590 The 2 bit foreground and background attributes directly select the color there is no indirect look up i e there is no TMASK function The 2560 addresses of the ROM SRAM are mapped as 10 segments of 256 contiguous addresses each to the OSD memory page of 100h 1FFh in the host interface A 4 bit register value selects the segment to map to the host R W page The character cell height and width are programmable from 5 66 pixels or 2 65 lines The X Y offset of the fo
41. ANI ADC has a built in clamp circuit By inserting series capacitors about 10 nF the DC offset of an external video source can be removed The clamp pulse position and width are programmable 50 2 3 2 Sync Signal Support The gmZANI chip supports digital separate sync Hsync Vsync digital composite sync and analog composite sync also known as sync on green sync types are supported without external sync separation extraction circuits Digital Composite Sync The types of digital composite sync inputs supported are OR AND type No Csync pulses toggling during the vertical sync period type Csync polarity changes during the vertical sync period The gmZanl provides enough sync status information for the firmware to detect the digital composite sync type Sync On Green Analog Composite Sync The voltage level of the sync tip during the vertical sync period can be either 0 3 or 2 3 3 Display Mode Support A mode calculation utility MODECALC EXE provided by Genesis Microchip may be run before compilation of the firmware to determine which input modes can be supported Refer to firmware documents for more details 2 4 Input Timing Measurement As described in section 2 2 2 above input data is sent from the analog to digital converter to the source timing generator STG block The STG block defines a capture window Figure5 The input timing measurement block consists of the source timing m
42. ANI registers Note that the vertical total is solely determined by the input The reference point is as follows The first pixel of a line the pixel whose SCLK rising edge sees the transition of the HSYNC polarity from low to high The first line of a frame the line whose HSYNC rising edge sees the transition of the VSYNC polarity from low to high The gmZANI also supports the use of analog composite sync and digital sync signals as described in Section 2 3 2 Figure 5 Capture Window Source Horizontal Total pixels Reference Point Source Hstart gt lt Source Width us start gt Capture Window Source Height Source Vertical Total lines 49 2 3 Analog to Digital Converter 2 3 1 Pin Connection The RGB signals are to be connected to the gmZANI chip as described in Table 8 and Table 9 Table 8 Pin Connection for RGB Input with Hsync Vsync GmZANI Pin Name Pin Number CRT Signal Name Red 95 Red Red 94 N A Tie to Analog GND for Red on the board Green 91 Green Green 90 N A Tie to Analog GND for Green on the board Blue 87 Blue Blue 86 N A Tie to Analog GND for Blue on the board HSYNC CS 150 Horizontal Sync VSYNC 148 Vertical Sync Table 9 Pin Connection for RGB Input with Composite Sync GmZANI Pin Name Pin Number CRT Signal Name Red 95 Red Red 94 N A Tie to Analog
43. CLK is stopped the CVDD supply current becomes 0 mA 63 7 MECHANICAL OF CABINET FRONT DIS ASSEMBLY For temporary this page still not available Wait for mechanical drawing 64 LOCATION T780KMGHBAA0A AUPC780A1 CBPC780GM DCPC780A3 KEPC780EK 12 381 1 15A 5684 1 15A 5689 1 15 5689 2 26 800 13 33A 3647 1 33A 4058 YL 33A 4060 YL 33A 4061 YL 33A 4062 YL 33A 4063 YL 34A 756 34A 757 V IL 34A 758 YL 34A 759 Y3L 34 760 YL 34A 761 YL 37A 443 1 40 155 237 41 401 948 1 44A 3147 1 44 3148 1 44A 3234 1 44 3234 2 44 3234 5 44A 3253 1 45A 113 1 45A 114 1 45A 116 1 52A 1208 52 194 1 70 L17 3A0C 78A 309 1 79 117 15 80 117 2 85 548 3 85A 574 1 85A 583 1 85A 583 6 85A 583 85A 583 8 89A 173 564 89A 174D SBFGL 89 404C 18 95A 8013 2 29 95A 8014 55A 95A 8018 301 BIA 1030 5128 BIA 1030 5128 BIA 1030 8128 BIA 1030 8128 MIA 330 6128 MIA 330 6128 MIA 330 6128 MIA 1030 10128 MIA 1740 12128 QIA 330 8120 QIA 340 12128 QIA 340 16128 PARTS LIST OF CABINET 65 SPECIFICATION 17 LCD AUDIO BOARD 17 CONVERSION BOARD 17 DC POWER BOARD KEYBOARD RUBBER FOOT MAIN FRAME GND CABLE CLAMP GND CLAMP LCD BAR CODE POWER LED LENS POWER KEY PAD CABLE COVER AUDIO POWER BUTTON VOLUME KNOB SCREW COVER FRONT PANEL AOC BACK COVER SUPPORT FRONT AUDIO SUPPORT BACK BASE ARM COVER LCD HINGE ID LABEL LM 700A OWNERS MANUAL WOODEN FLAT P
44. EAD 120 OHM 0603 FCM160 MTG U3 87A 202 44 1 IC SOCKET 44P PLCC D200 93A 391 39 1 CHIP 70 5 6V ICI MLL752 D201 93A 391 39 1 CHIP ZD 5 6V BY FCIMLL752 D208 93A 391 39 1 CHIP ZD 5 6V BY FCI MLL752 D209 93A 391 39 1 CHIP ZD 5 6V BY FCIMLL752 D210 93A 391 39 1 CHIP ZD 5 6V BY FCIMLL752 D200 93A 391 47 0 ZENER DIODES TZMC5V6 GS8 D201 93A 391 47 0 ZENER DIODES TZMC5V6 GS8 D208 93A 391 47 0 ZENER DIODES TZMC5V6 GS8 D209 93A 391 47 0 ZENER DIODES TZMCS5V6 GS8 D210 93A 391 47 0 ZENER DIODES TZMC5V6 GS8 D200 93A 391 49 0 CHIP ZD 5 6V FULL POWMLL523 D201 93A 391 49 0 CHIP ZD 5 6V FULL POWMLL523 D208 93A 391 49 0 CHIP ZD 5 6V FULL POWMLL523 D209 93A 391 49 0 CHIP ZD 5 6V BY FULL POWMLL523 D210 93A 391 49 0 CHIP ZD 5 6V FULL POWMLL523 D300 93A 602 11 1 SMB340 BY FULL POWER D300 93A 602 12 0 SMB340 BY FCI D300 93A 602 12 0 SMB340 BY FCI D202 93A 64 32 1 LL4148 SMD BY FCI D203 93A 64 32 1 114148 SMD BY D204 93A 64 32 1 LL4148 SMD BY FCI D205 93A 64 32 1 LL4148 SMD BY FCI D206 93A 64 32 1 LL4148 SMD BY FCI D207 93A 64 32 1 114148 SMD BY D301 93A 64 32 1 114148 SMD BY D302 93A 64 32 1 114148 SMD BY FCI D202 93A 64 32 U 0 MLL4148 SMD BY FULL POWER D203 93A 64 320 0 4148 SMD BY FULL POWER D204 93A 64 32U 0 MLL4148 SMD BY FULL POWER D205 93A 64 32U 0 MLL4148 SMD BY FULL POWER D206 93A 64 32U 0 MLL4148 SMD BY FULL POWER D207 93A 64 32U 0 MLL4148 SMD BY FULL POWER D301 93A 64 32U 0
45. NEL M170E1 Hyundai PANELHT17E11 100 MAIN FRAME 15A5684 1 15A5705 1 Panel 750ALCD170 3 750ALCD170 4 5 3 SIMPLE INTRODUCTION about LM700 chipset 1 GMZANI all in one chip solution for ADC OSD scalar and interpolation USE for computer graphics images to convert analog RGB data to digital data with interpolation process zooming generated the OSD font perform overlay function and generate drive timing for LCD PANEL M6759 ALI MCU type 8052 series with 64k Rom size and 512 byte ram Use for calculate frequency pixel dot detect change mode rs232 communication power consumption control OSD index warning etc 24LC21 MicroChip IC EePROM type IK ROM SIZE for saving DDC CONTENT 24C04 ATMEL IC EePROM type 4K ROM SIZE for saving AUTO config data White balance data and Power key status and Backlight counter data LM2569S NS brand switching regulator 12V to 5V with 3A load current AIC 1084 33CM AIC brand linear regulator 5V to 3 3V LVDS use NOVATEK NT7181F Convert the TTL signal to LVDS signal The advantage of LVDS signal is the wire can be lengthen and eliminate wire number low EMI LVDS signal is high frequency but low voltage only 0 35 VPP frequency is seven times higher than TTL MODULE TPYE COMPONENT 1 2 ADAPTER CONVERSION module to convert 110V 240V to 12VDC with 5 0 AMP INVERTER CONVERSION module to convert DC 12V to High Voltage around 1600V
46. P 0 01UF 50V X7R C232 65A 0603 103 32 CHIP 0 01UF 50V X7R C233 65A 0603 103 32 CHIP 0 01UF 50V X7R C234 65A 0603 103 32 CHIP 0 01UF 50V X7R C251 65A 0603 103 32 CHIP 0 01UF 50V X7R C606 65A 0603 103 32 CHIP 0 01UF 50V X7R C608 65A 0603 103 32 CHIP 0 01UF 50V X7R C614 65A 0603 103 32 CHIP 0 01UF 50V X7R 68 LOCATION C616 C201 C202 C204 C205 C207 C208 C209 C210 C211 C212 C213 C215 C217 C218 C219 C220 C221 C222 C223 C225 C226 C227 C228 C237 C244 C245 C246 C300 C304 C308 C311 C405 C601 C602 C604 C618 C619 C939 C940 C941 C942 C944 C250 C303 C306 CP301 CP302 C605 C607 C613 C615 C620 C200 C203 C206 C214 C216 C224 C305 C403 AI780GM 65A 65A 65A 65A 65A 65A 65A 65A 65A 65A 65A 65A 65A 65A 65A 65A 65A 65A 65A 65A 65A 65A 65A 65A 65A 65A 65A 65A 65A 65A 65A 65A 65A 65A 65A 65A 65A 65A 65A 65A 65A 65A 65A 65A 65A 65A 65A 65A 67A 67A 67A 67A 67A 67 67 67 67 67 67 67 67 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 600M 600M 312 312 312 312 312 312 312 312 312 312 312 312 312 103 104 104 104 104
47. RIIS RES 15 1 4W 5 SMD 1206 1 PCS 2243515090 51 2123 RES 150 1 4W 5 SMD 1206 1 PCS 2243515000 52 JRIO7 R108 R109 RI10 RES 180K 1 4W 5 SMD 1206 4 PCS 2243518030 53 2142 RES 2 4K 1 8W 4 19 SMD 0805 1 PCS 2242124010 54 130 131 8132 R133 RES 24 1 4W 5 SMD 1206 4 PCS 2243524090 55 2141 RES 270 1 4W 5 SMD 1206 1 PCS 2243527000 56 R129 RES 3 6K 1 8W 5 SMD 0805 1 PCS 2242536010 57 R137 RES 3 74K 1 8W 1 SMD 0805 1 PCS 2242137410 58 R139 RES 330 1 4W 4 595 SMD 1206 1 PCS 2243533000 59 R105 R106 RES 1 4W 4 59 SMD 1206 2 PCS 2243530040 60 IRIO4 R116 RES 4 7K 1 4W 5 SMD 1206 2 PCS 2243547010 61 118 8144 8120 8134 RES 4 7 1 8W 5 SMD 0805 4 PCS 2242547010 62 JRIO2 R103 RES 470K 1 4W 5 SMD 1206 2 PCS 2243547030 63 RI22 RES 47K 1 8W 4 59 SMD 0805 1 PCS 2242547020 64 8126 RES 510 1 8W 5 SMD 0805 1 PCS 2242551000 65 R138 RES 680 1 8W 1 SMD 0805 1 PCS 2242168000 66 121 RES 8 2K 1 8W 1 SMD 0805 1 PCS 2242182010 67 8140 RES 9 31K 1 8W 1 SMD 0805 1 PCS 2242193110 68 8119 RES CF 4 7 1 8W 5 1 PCS 2222547011 69 8135 RES CuNi lOmQ 1 8 1 PCS 24911 0189 70 RES MOF 43K 4 59 KINK 1 PCS 2376543029 di pias 0 39 OHM 2W 5 NKNP TYPE 275 L PCS 24735 398B 72 FOR C124 SRK TUBE 1 17mm 1 PCS 57101 0170 73 FOR CNIOI RING TERMINAL 70mm 1 PCS 54B2310705 74 FOR PCB SCREW M3 6 ISO SW ZNC 2 PCS 6720530051 75 FOR Q101 D107 D106 SPRING SK 7
48. SERVICE MANUAL SPECTRUM Series LCD Monitor LM 700 LM 700A THESE DOCUMENTS ARE FOR REPAIR SERVICE INFORMATION ONLY EVERY REASONABLE EFFORT HAS BEEN MADE TO ENSURE THE ACCURACY OF THIS MANUAL WE CANNOT GUARANTEE THE ACCURACY OF THIS INFORMATION AFTER THE DATE OF PUBLICATION AND DISCLAIMS RE LIABILITY FOR CHANGES ERRORS OR OMISSIONS MANUFACTURE DATA JULY 2001 REVISE 7 SEP 2001 TABLE OF CONTENTS CA CA CA gt ON PAGE M tL GENERAL SPECIFICATIONS sa ika Nao ieee 12 LCD MONITOR DESCRIPTION i ise gi e kriet 152 INTERFACE CONNEC TOR ctio eet u p paruus 2 PRECAUTION AND NOTICES sisaan aaa VeL ASSEMBEY PRECAUTION ea E HU G 2 2 JOPERATIONG PRECAUTION tei tec eE 2 5 STORAGE PRECAUFION 2 HIGH VOLTAGE WARNING 3 AJJPBRATINC INSTR GCTIOI G 2 ciini ADJUSTMEN tps ta AE A ba 4 1 ADJUSTMENT CONDITIONS AND PRECAUTIONS 42 ADJUSTMENTS METHOD amp DESCRIPTION 4 3 FRONT PANEL CONTROL KNOBS iii ia Eid eR CIRCUIT amp SOFTWARE DESCRIPTION 5 1 THE DIFFERENT BETWEEN EACH PANEL eee 5 2 SPECIAL FUNCTION WITH PRESS KEY
49. Synthesis vco DDS Output Output Clock Course Analog Divider SCLK Adjust PLL amp VCO n Fine Adjust PLL Divider m Prescaler 2 or 1 Source Horizontal Total Divider Analog PLL amp VCO PLL Divider PLL Divider 2 108 2 or 1 TCLK Post Scale 2 or 1 RCLK 48 The table below summarizes the characteristics of the clock recovery circuit Table 7 Clock Recovery Characteristics Minimum Typical Maximum SCLK Frequency IOMHz 135 MHz Sampling Phase Adjustment 0 5 ns step 64 steps Patented digital clock svnthesis technologv makes the gmZANI clock circuits verv immune to temperature voltage drift 2 2 1 Sampling Phase Adjustment The ADC sampling phase is adjusted by delaying the Hsync input at the programmable delay cell inside the gmZANI The delay value can be adjusted in 64 steps 0 5 ns step The accuracy of the sampling phase is checked by the gmZANI and the score can be read in a register This feature will enable accurate auto adjustment of the ADC sampling phase 2 2 2 Source Timing Generator The STG module defines a capture window and sends the input data to the data path block The figure below shows how the window is defined For the horizontal direction it is defined in SCLKs equivalent to a pixel count For the vertical direction it is defined in lines the parameters in the figure that begin with Source are programmed into the gmZ
50. TS LIST OF CONVERSION BOARD SPECIFICATION WAFER 5P RIGHT ANELE PITCH 2 0 WAFER 9P RIGHT ANELE PITCH 2 0 WAFER 10P RIGHT ANELE PITCH WAFER 14P RIGHT ANELE PITCH 2 PIN MIN JUMPER 3 PIN PLUG 3 PIN PLUG 2P SHUNT MINI JUMPER PLUG 14P 90 LABEL CBPC780GM EVA M6759FG BY ALI 330uF 20 35V 330uF 20 35V 330uF 20 35V 330uF 20 35V 330uF 20 35V 330uF 20 35V 470uF 2096 16V BEAD P6H 7 62 5 08 6 4 BY TEC CHOKE COIL BY SHINING CHOKE COIL BY LINEARITY 200UH 5 10K OHM 30 RH0615C14J ALPS HEAT SINK CRYSTAL 20MHz HC 49US OSCILLATOR 50MHz 3 3V HARNESS LOCATION AI780GM SPECIFICATION U601 56A 561 5 NT7181 56L TSSOP U602 56A 561 5 NT7181 56L TSSOP U200 56A 562 8 gmZANI PQFP 160 GENESIS U304 56A 563 1 CHIP LM2596S 5 0 BY NS U305 56A 563 7 AIC1084 33M TO 263 ANALOG U202 56A 566 6 CHIP SI9953DY T1 SILICON U904 56A 585 2 LT1117 SMD SOT223 BY LINEARITY U904 56A 585 4 AIC1117 33CY SOT 223 ANALOG U401 56A 14 CHIP MC74F14 BV MOTOROLA U401 56A 14 P N74F14D BY PHILIPS U203 56A 1133 16 CHIP 24LC21A SN BY MICRO U300 56A 1133 17 AT24COAN 10SC BY ATMEL U300 56A 1133 29 24LC04BT SC 80118 MICRO Q200 57A 417 4 CHIP PMBS3904 BY PHILIPS Q304 57A 417 4 CHIP PMBS3904 BY PHILIPS D303 57A 754 1 BAT54C GS08 5 23 TELEFUKON D303 57A 754 2 54 RP300 61A 125 103 8 CHIP ARRAY 10K OHM 1 16W 8P4R L207 61A 0603 000 CHIP 0 OHM 1 16W R200 61A 0603 000 CHIP 0 OHM 1 1
51. Timing Change Any of the following timing changes e Sync loss DDS tracking error beyond threshold X Horizontal vertical timing change beyond threshold Threshold values are programmable Reading the IRQ status flags will not affect the STM registers Note that if a new IRQ event occurs while the IRQ status register is being read the IRQ signal will become inactive for minimum of one TCLK period and then get re activated The polarity of the IRQ signal is programmable 2 5 Data Path The data path block of gmZANI is shown in Figure 6 Figure 6 gmZANI Data Path 80r6 Sampled Data or from pattern generator Scaling RGB Panel Filter Offset Data Dither Background 80r6 Color Internal OSD External OSD 52 2 5 1 Scaling Filter The gmZANI scaling filter uses an advanced adaptive scaling technique proprietary to Genesis Microchip Inc and provides high quality scaling of real time video and graphics images This is Genesis third generation scaling technology that benefits from the expertise and feedback gained by supporting a wide range of solutions and applications 2 5 2 Gamma Table The gamma table is used to adjust the RGB data for the individual display characteristics of the TFT panel The overall gamma of the display may be set as well as separate corrections for each of the three display channels In addition the gamma table may be used for contrast brightness and white ba
52. V X7R CHIP33PF 50V NPO CHIP 33PF 50V NPO CHIP 33PF 50V NPO CHIP ARRAY 1000PF 8P CHIP ARRAY 1000PF 8P SMD EC 10UF 16V 85C B SMD EC 10UF 16V 85C B SMD EC 10UF 16V 85C B SMD EC 10UF 16V 85C B MD EC 10UF 16V 85C B MD EC 100UF 16V 85C D MD EC 100UF 16V 85C D MD EC 100UF 16V 85C D MD EC 100UF 16V 85C D MD EC 100UF 16V 85C D MD EC 100UF 16V 85C D MD EC 100UF 16V 85C D MD EC 100UF 16V 85C D LOCATION AI780GM SPECIFICATION C603 67A 312 1013 1 SMD EC 100UF 16V 85C D C943 67 312 1013 1 SMD EC 100UF 16V 85C D C313 67A 312 2203 1 SMD EC 22UF 16V 85C CSIZE C314 67 312 2203 1 SMD 22UF 16V 85C CSIZE L200 576 601 1 CHIP BEAD 600 OHM 1206 T13216 L201 576 601 1 CHIP BEAD 600 OHM 1206 T13216 L202 576 601 1 CHIP BEAD 600 OHM 1206 T13216 L203 576 601 1 CHIP BEAD 600 OHM 1206 T13216 L300 576 601 1 CHIP BEAD 600 OHM 1206 T13216 L900 576 601 1 CHIP BEAD 600 OHM 1206 T13216 L601 71A 598 121 1 CHIP BEAD 120 OHM 0603 TB1608 L602 71 59B 121 1 CHIP BEAD 120 OHM 0603 TB1608 L603 71 598 121 1 CHIP BEAD 120 OHM 0603 TB1608 L604 71A 598 121 1 CHIP BEAD 120 OHM 0603 TB1608 R215 71 59B 121 1 CHIP BEAD 120 0603 TB1608 L601 71 59 121 B 0 CHIP BEAD 120 OHM 0603 FCM160 L602 71 59C 121 B 0 CHIP BEAD 120 OHM 0603 FCM160 L603 59C 121 B 0 CHIP BEAD 120 OHM 0603 FCM160 L604 59C 121 B 0 CHIP BEAD 120 OHM 0603 FCM160 R215 59C 1218 0 CHIP B
53. able automatic PCB assembly test When this input is pulled high the automatic PCB assembly test mode is entered An internal pull down resistor drives this input low for normal operation 155 SCAN INI I Scan input 1 used for automatic PCB assembly tesing 157 SCAN IN2 I Scan input 2 used for automatic PCB assembly tesing 159 SCAN OUTI 0 Scan output 1 used for automatic PCB assembly tesing 160 SCAN OUT2 0 Scan output 2 used for automatic PCB assembly tesing 153 Reserved 154 Reserved Table 6 VDD VSS for Core Circuitry Host Interface and Panel Memory Interface PIN f Description 65 40 33 12 149 108 58 21 11 158 151 140 126 114 72 61 49 41 30 18 8 1 PVDD4 PVDDI for panel memory interface Connect to 3 3V Must be the same voltage as the CVDD s SRVDD2 1 CVDD4 CVDD2 1 for core circuitry Connect to 3 3V Must be the same voltage as the PVDD s Digital grounds for core circuiry and panel memory interface 43 1 4 System level Block Diagram CVDD A ADC VDD RVDDA gmZAN1 Core ADC GND RGNDA H 0 p 8 9 E 0 0 A SVDDA 9 gt To Clock SGNDA Generator A DVDDA DGNDA R G B Even Data On Screen osp Fs 24 2 PCLKA Controller PHS HDATA IRQ MPU with Pbia Power Switching Module Host Interface Panel Interface RESETn CVSS Figure 2 Ty
54. anel Hsync frequency Input Hsync frequency Panel Vsync frequency Input Vsync frequency This mode is used when the input resolution is the same as the panel resolution but the input data clock frequency is exceeds the panel clock frequency specification of the panel being used The panel clock is scaled to the Source Clock and the internal data buffers are used to spread out the timing of the input data by making use of the large CRT blanking time to extends the panel horizontal display time 1 5 3 Zoom Panel Clock frequency Source Clock frequency Panel Hsync frequency Input Hsync frequency Panel Vsync frequency Input Vsync frequency This mode is used when the input resolution is less than the panel resolution The input data clock is then locked to the pnael clock which is at a higher frequency The input data is zoomed to the panel resolution 45 1 5 4 Downscaling Panel Clock frequency Source Clock frequency Panel Hsync frequency Input Hsync frequency Panel Vsync frequency Input Vsync frequency This mode is used when the input resolution is greater than the panel resolution to provide enough of a display to enable the user to recover to a supported resolution The input clock is operated at a frequency less than that of the input pixel rate under sampled horizontally and the scaling filter is used to drop input lines In this mode zoom scaling must be disabled 1 5 5 Destination Stand Alone Panel Clock DCLK i
55. d in a non volatile memory As can be seen from this table the wide range of timing programmability of the gmZANI panel interface makes it possible to support various kinds of panels known today 54 Figure 7 timing Diagrams of the TFT Panel Interface One pixel per clock a Vertical size in TFT PVS t PHS t2 PDE b Vsync width and display position in TFT t4 PVS t18 t19 PHS 6 RGBs 8 c Horizontal size in TFT RGB data from data paths d Hsync width in TFT t10 t13 t15 55 Figure 8 Data latch timing of the TFT Panel Interface a Two pixel per clock mode in TFT PDE t16 t13 4 2 t15 PCLK t14 t16 t17 4 m X X voo X EG X ac X X yx am X X umm X X amo X am xy X ya X b One pixel per clock mode in TFT 2 6 2 Power Manager LCD panels require logic power panel bias power and control signals to be sequenced in a specific order otherwise severe damage may occur and disable the panel permanently The gmZANI has a built in power sequencer Power Manager that prevents this kind of damage The Power Manager controls the power up down sequences for LCD panels within the four states described below See the timing diagram Figure 9 56 2 6 2 1 State 0 Power Off The Pbias signal and Ppower signal are low inactive T
56. data pixels of the same width and height as the OSD window but offset to the right and down by 8 pixels lines the border width setting has no effect OSD foreground and background colors always cover the OSD window region of the shadow but transparent background pixels in the OSD will show the half intensity panel data Therefore it is not recommended to use both the shadow feature and transparent background OSD pixels together The shadow does not change the intensity of any panel background color over which it may be located The border and shadow are mutually exclusive only one may be selected at a time The OSD window is not affected by the scaling operation The size will stay the same whether the source input data is scaled or not 2 9 TCLK Input The source timing is measured by using the TCLK input as a reference Also the reference clock to the on chip PLLs are derived from the TCLK It is therefore crucial to have a jitter free clock reference Table 19 shows the requirements for the TCLK signal Table 19 TCLK Specification Frequency 20 MHz to 50 MHz Jitter 250 ps maximum Rise Time 10 to 90 5ns Duty Cycle 40 60 There is also an option to use a crystal instead of an oscillator for the TCLK input This option is selected by pulling down 5 and connecting the crystal between XTAL and TCLK 62 3 ELECTRICAL CHARACTERISTICS Table 20 Absolute Ratings
57. e balance adjust 21 6 B Inverter MODULE Spec amp Trouble Shooting Chart In LM700 model we use CHI MEI panel and the INVERTER PROVIDER is SAMPO CORPORATION I TROUBLE SHOOTING OF CHI MEI INVERTER part no 79AL17 1 S L0037 FOR CHI MEI 17 PANEL SAMPO CORPORATION TROUBLE SHOOTING OF CHHMEI INVERTER DIVTL0037 D42 1 SAMPO PART NO 10037 AOC PART NO 79AL17 1 S 2 SCOPE this is to specify the requirements of the subject parts used in CHI MEI M170E1 17 inch 4 C C F L LCD monitor 3 CONNECTOR PIN ASSIGMENT 4 1 CON1 INPUT MODEL NO 55 5 3 PIN SYMBOL DESCRIPTION 1 Vin Input voltage 12V 2 Vin Input voltage 12V 3 ON OFF JON 3V OFF 0V 4 Dimming Dimming range OV 5 0V 5 GND GND 4 2 2 OUTPUT MODEL NO 5 04 4 0 5 1 PIN SYMBOL DESCRIPTION 1 HV OUTPUT Input H V to lamps 2 HV OUTPUT Input H V to lamps 3 N C N C 4 RETURN Return to control 22 SAMPO CORPORATION TROUBLE SHOOTING OF INVERTER DIVTL0037 D42 5 FUNCTION SPECIFICATIONS The data test with the set of SAMPO and the test circuit is as below ITEM SYMBOL MIN MAX UNIT REMARK Input voltage Vin 10 8 12 13 2 V Input current lin 2200 2500 mA output current lout FOR 1 CCFL adj 0v min min 2 1 2 6 Sa mae Output current FOR 1 CCFL
58. e balance data will overlap with the new one and you must perform the white balance process again The result of counter was place at top of OSD the maximal of record memory was 65000 hours if exceed 65000 hours the counter will keep in 65000 hours until press RESET at osd menu in factory mode The RESET function in factory mode will execute following function 1 clear the Power on counter to zero hours 2 clear old auto configuration status for all mode so the monitor will automatically re do auto config when change to next mode or power on off 4 3 FRONT PANEL CONTROL KNOBS Power button Press to switch on or switch off the monitor Auto button to perform the automatic adjustment from CLOCK FOCUS H V POSITION but no affect the color temperature Left Right button select function or do an adjustment MENU button to activate the OSD window or to confirm the desired function 5 CIRCUIT DESCRIPTION 5 1 SPECIAL FUNCTION with PRESS KEY 5 2 A press Menu button during 2 seconds along with plug in the DC Power cord B That operation will set the monitor into Factorv mode in Factory mode we can do the White balance adjustment with RS232 and view the Backlight counter this counter is use to record the panel activate hours for convenient the maintainer to check the panel backlight life time In Factory mode OSD screen will locate in left top of screen Press POWER button off to on once will quit from factory
59. e pay attention to displaying the same pattern for very long time Image might stick on LCD STORAGE PRECAUTIONS 1 When you store LCD for a long time it is recommended to keep the temperature between 0 40 without the exposure of sunlight and to keep the humidity less than 9096 RH 2 Please do not leave the LCD in the environment of high humidity and high temperature such as 60 C 9096 RH 3 Please do not leave the LCD in the environment of low temperature below 15 HIGH VOLTAGE WARNING The high voltage was only generated by INVERTER module if carelessly contacted the transformer on this module can cause a serious shock the lamp voltage after stable around 600V with lamp current around 8mA and the lamp starting voltage was around 1500V at Ta 25 C 3 OPERATING INSTRUCTIONS This procedure gives you instructions for installing and using the LM700 LCD monitor display 1 Position the display on the desired operation and plug in the power cord into External Adapter AC outlet Three wire power cord must be shielded and is provided as a safety precaution as it connects the chassis and cabinet to the electrical conduct ground If the AC outlet in your location does not have provisions for the grounded type plug the installer should attach the proper adapter to ensure a safe ground potential Connect the 15 pin color display shielded signal cable to your signal system device and lock both screws on the connector to
60. easurement STM block and interrupt request IRQ controller Input timing parameters are measured by the STM block and stored in registers Some input conditions will generate an IRQ to an external micro controller The IRQ generating conditions are programmable 2 4 1 Source Timing Measurement When it receives the active CRT signal R G B and Sync signals the Source Timing Measurement unit begins measuring the horizontal and vertical timing of the incoming signal using the sync signals and TCLKi as a reference Horizontal measurement occurs by measuring a minimum and a maximum value for each parameter to account for TCLKi sampling granularity The measured value is updated every line Vertical parameters are measured in terms of horizontal lines The trailing edge of the Hsync input is used to check the polarity of the Vsync input The table below lists all the parameters that may be read in the source timing measurement STM registers of the gmZANI Table 11 Input Timing Parameters Measured by the STM Block Parameter Unit Updated at HSYNC Missing N A Every 4096 TCLKs and every 80ms 2 bits VSYNC Missing N A Every 80ms HSYNC VSYNC Timing Change N A When the horizontal period delta or the vertical period delta to the previous line frame exceeds the threshold value programmable HSYNC Polarity Positive Negative After register read VSYNC Polarity Positive Negative Every frame Horizo
61. ed amp WHITE Balance 2 if Replace INVERTER only Please re do WHITE Balance 15 PANEL POWER CIRCUIT check R225 should have response from 12V to 0V When we switch the power switch from on to off Check the PPWR panel power relative circuit R223 Q200 U202 pin 5 6 7 8 In normal operation when LED green R223 should 0 v If PPWR no response when the power switch Turn on and turn off replace the U200 GMZANI OK R225 have response Yes Measured the U202 pin 5 6 7 8 5 V Check U202 pin 1 2 3 4 5V Replace 0202 Nmos 519933 OK NG OK INVERTER Control Relative Circuit NG Measured the inveter connector CN303 Pin 1 12V pin 3 on off control 5V on NG still no screen NG no Voltage Check the Bklt On relative circuit R315 0304 R311 In normal operation when LED green R315 Bklt On should 0 v If Bkit On no response when the power switch turn on off Replace the MCU NG Replace INVERTER to new one and Check the screen is normal Replace INVERTER module amp Re do white balance OSCILLATOR BLOCK Measured 0201 Oscillator output R215 50mhZ 2 NG no transition Replace Oscillator U201 Replace Crystal X300 OK has transition NG no transition Measured X300 Crystal output R340 20mhZ OK U200 DATA OUTPUT NG transition Measured PCLK L207 PVS PHS 73 74 from 0200 Is there have any transition Pclk around 47MHz
62. equipment rarely happened Use DOT pattern or win98 99 shut down mode pattern press AUTO key was the OK END interferences disappear NG interferences still exist Adjust FOCUS step by step until the SE 5 i END horizontal interferences disappear NG Yes has extension Put away the additional cable Does your signal cable have an additional cable for extension May be the additional cable grounding is not quite well NO additional extension cable NO all mode Does your noise only exist in one mode only ex only at 1280x1024 75 Hz other is normal Change the Signal cable to new one or Try other brand VGA CARD make sure just only that brand VGA CARD has this problem contact RD Yes only happened on one mode taipei That was cause by you VGA CARD setting your VGA card timing backporch frontporch exceed vesa timing too far for some new AGP VGA CARD such situation always happened So in your control panel icon select monitor setting advance screen adjust at Size icon increase step by step slowly press AUTO key every step you increase the SIZE repeat the procedure increase decrease SIZE one step and press AUTO until the interferences disappear press APPLY to save in your VGA 20 There is an interferences in DOS MODE NOTE the criteria of doing AUTO CONFIGURATION must be a full size screen if the screen not full the auto configuration will fail
63. guration 105 MFB7 jo Multi Function Bus 7 One of twelve multi function signals MFB 11 0 Also used as in a 4 bit host interface configuration 106 MFB6 Multi Function Bus 6 One of twelve multi function signals 11 01 Internally pulled up When externally pulled down sampled at reset the host interface is configured for 4 bits wide In this configuration MFB9 7 are used as HDATA 3 1 107 5 Multi Function Bus 5 One of twelve multi function signals MFB 11 0 Internally pulled up When externally pulled down sampled at reset the chip uses an external crystal resonator across pins 141 and 142 instead of an oscillator 109 MFB4 IO Multi Function Bus 4 One of twelve multi function signals MFB 11 0 110 MFB3 IO Multi Function Bus 3 One of twelve multi function signals MFB 11 0 111 FMB2 IO Multi Function Bus 2 One of twelve multi function signals MFB 11 0 112 IO Multi Function Bus 1 One of twelve multi function signals MFB 11 0 113 MFBO IO Multi Function Bus 0 One of twelve multi function signals MFB 11 0 40 Table 3 Clock Recovery Time Base Conversion PIN Name Description 125 DVDD Digital power for Destination DDS direct digital synthesizer Must be bypassed with a O 1uF capacitor to digital ground plane 127 DAC DGNDA Analog ground for Destination DDS DAC Must be directly connected to the
64. he panel controls and data are forced low This is the final state in the power down sequence PM is kept in state 0 until the panel is enabled 2 6 2 2 State 1 Power On Intermediate step 1 The Ppower is high active the Pbias is low inactive and the panel interface is forced low inactive 2 6 2 3 State 2 Panel Drive Enabled Intermediate step 2 The Ppower is high active the Pbias is low inactive and the panel interface is active 2 6 2 4 State 3 Panel Fully Active This is the final step in the power up sequence with Ppower and Pbias high active and the panel interface active PM is kept in this state until the internal TFT Enable signal controlled by Panel Control register is disabled The panel can be disabled through either an API call under program control or automatically by the gmZANI to prevent damage to the panel Figure 9 Panel Power Sequence TFT EN Bit register bit PPWR Output Data Controls Signals PBias Output State0 lt Statel gt lt State2 gt lt State3 gt lt State2 gt Statel lt StateO gt In Figure 9 above t2 t6 and t3 t5 t1 t2 t3 and t4 are independently programmable from one to eight steps in length The length of each step is in the range of 511 X TCLKi cycle or TCLKi cycle 32193 X where X is any positive integer value equal to or less than 256 TCLKi is the reference clock to the gmZANI chip and ranges from 14 318 MHz to 50 MHz in frequency This progra
65. hite balance please setting the Chroma 7120 MEM Channel 5 to 7800 color and MEM channel 6 to 6500 color our 7800 parameter is x 296 10 y 311 10 Y 160 5cd m2 and 6500 parameter is x 313 10 2329 110 160 5 cd m How to setting MEM channel you can reference to chroma 7120 user guide or simple use SC key and NEXT key to modify xyY value and use ID key to modify the TEXT description Following is the procedure to do white balance adjust Press MENU button during 2 seconds along with plug in the DC power cord will activate the factory mode and the OSD screen will located at left top of panel I Bias Low luminance adjustment 1 Press AUTO button and wait for message Pass check the Blacklevel value on OSD should be large than 30 if less than 30 that means the offset calculation FAIL please manual adjust the blacklevel to value 43 2 set the contrast and brightness on OSD window to maximal value RGB to 50 3 adjustthe VR501 on INTERFACE board until chroma 7120 measurement reach the value X 240 cd m 5 cd m Gain adjustment a adjust 7800 color temperature 4 Setthe Contrast of OSD function to 40 Brightness to 48 5 Switch the chroma 7120 to RGB mode with press MODE button 6 switch the MEM channel to Channel 05 with up or down arrow on chroma 7120 7 The Icd indicator on chroma 7120 will show x 296 10 y 311 10 Y 160 5 cd m 8 Adjust
66. hortage or cold solder Yes all DC level exist Yes there have OSD show Disconnected the Signal cable Loose the Signal cable Is the screen show Cable Not Connected the Signal cable again Led Green Connected Check LED status No nothing is show Led Orange Check Power switch is in Power on ReslaceMCU l l status and check if Power switch had Replace MCU Connected the Signal cable again been stuck Check LED status Led orange OK Keyboard no stuck Led Green NG Check Correspondent t short Check the Wire Harness from CN601 CN602 Measured RGB 1200 201 202 H V Input at U401 was tight enough pin 9 4 was there have signal and Signal cable bad check the Wire connection to panel side too input Normal OK Wire tight enough Measured Oscillator Block Oscillator U201 amp Crystal X300 Check Panel Power Circuit Block OK Panel Power OK OK clock normal Check communication pin between U200 amp p Check U200 Data output Block MCU pin 2 6 7 is it have transition OK U200 data OK OK Mcu have transition NG no transition Replace Inverter and Check Inverter control relative circuit Re do White balance adjust Replace U302 MCU amp check Reset pin 10 must be change from High to low when first AC power plug in Replace U200 Gmzan1 Note 1 if Replace MAIN BOARD Please re do DDC content programm
67. lance temperature adjustments The lookup table has an 8 bit input 256 different RGB entries and produces a 10 bit output 2 5 3 RGB Offset The RGB offsets provide a simple shift positive or negative for each of the three color channels This may be used as a simple brightness adjustment within a limited range The data is clamped to zero for negative offsets and clamped to FFh for positive offsets This adjustment is much faster than recalculating the gamma table and could be used with the OSD user controller to provide a quick brightness adjust An offset range of plus 127 4 to minus 127 4 is available 2 5 4 Panel Data Dither For TFT panels that have fewer than eight bits for each R G B input the gmZANI provides ordered and random dithering patterns to help smoothly shade colors on 6 bit panels 2 5 5 Panel Background Color A solid background color may be selected for a border around the active display area The background color is most often set to black 2 6 Panel Interface The gmZANI chip interfaces directly with all of today s commonly used active matrix flat panels with 640x480 800x600 and 1024x768 resolutions The resolution and the aspect ratio are NOT limited to specific values 2 6 1 TFT Panel Interface Timing Specification The TFT panel interface timing parameters are listed in Table 13 below Refer to three timing diagrams of Figure 7 and Figure 8 for the timing parameter definition All aspects of the gmZANI inte
68. lock 11 PAGE 3 SCHEMATIC DIAGRAM MFB1 MFB2 HDATAO MFB2 MFB7 MFB8 MFB9 TCLK1 SCL SDA IRQ HFS HCLK NGA CON RST RSTI MCU TXD MFB1 MFB2 HDATAO MFB2 MFB7 MFB8 MFB9 TCLK1 SCL SDA IRQ HFS HCLK NGA CON RST RSTI TXD Gmzanl block PAGE 6 ERED dll ERED E GRN dll EBLU dil ORED lll ORED OGRN kl ORN la PHS l PHS IlM vs PDISPE IB JH PoisPE LVDS block LVDS MICRO CONTROLLER ZAN1 AOC Top Victory Electronics Co Ltd itle TOP LEVEL A Size Document Number 763 17 DSN Date Monday December 11 2000 Sheet 75 ID GMZANI Block f Y Sg 0 1206 RVDDA 9 xj 1201 lt 5 8 gt 5 a a 84 96 128 129 137 1 600 1206 BVDDA GVDD ADC RVDDA PLL DVDDA SVDDA 06 VDDA DAC DVDDA PLL SVDD HDATAO MFB7 MFB8 MFB9 L202 fo A 4 600 1206 HFS gt C287 oA UE GND OUT MHz PGND GND 27 28 28 OGHN7 31 OG NS 32 0202 35 OGHNS gt asus 379807 PCLKA oA Ps 3 39 HEDS ADCAGND 38
69. low to HFS high t1 100 ns HFS low to HCLK inactive t2 100 ns HDATA Write to Read Turnaround Time t3 JI HCLK cycle 1 HCLK cycle HCLK cycle t4 100 ns Data in setup time t5 25 ns Data in hold time t6 25 ns Data out valid t7 5ns 10 In the read operation the microcontroller Initiator issues an instruction lasting 12 HCLKs After the last bit of the command is transferred to the gmZANI on the 12 clock the microcontroller must stop driving data before the next rising edge of HCLK at which point the gmZANI will start driving data At the 13 rising edge of HCLK the gmZANI will begin driving data Figure 11 Serial Host Interface Data Transfer Format 2 bits 10 bits 12 bits Command 01 Write 00 2 Read 1x Reserved Note that when the chip is configured for a 4 bit host interface MFB9 7 are used as HDATA 3 1 and HDATA is used as HDATAO The command and address information are transferred as Address 1 0 Command1 0 Address5 2 and Address9 6 The data information is transferred as Data3 0 Data 7 4 Data 11 8 Thus in this mode the HDATA pin carries CommandO Address2 Address6 Data0 Data4 and Data8 On the gmZANI reference design board the microcontroller toggles the HCLK and HDATA lines under program control Genesis Microchip provides API calls to facilitate communication between the microcontroller and the gmZANI Refer to the API reference manual for details 2 7 2 Multi Function Bus MFB The Multi Functi
70. m with equal duty freq around 150K 158KHz that means all power of this interface board is in normal operation all status of 5V amp 3 3V is working well 2 unstable or uneven rectangle waveform without same duty that means ABNORMAL operation was happened check 3 3V or 5V jif short circuit or bad component 3 rectangle waveform with large spike amp harmonic pulse on front side means all 3 3v is no load U200 Gmzanl was shut down and only U302 MCU still working that means the monitor is in power saving status all power system is working well NG Measure input power at U304 LM2596 pin 1 Check ADAPTER and connector if loose 12 2 Check U304 pin 2 is a unstable rectangle wave OK unstable wave NG Check U304 pin 2 is a stable rectangle wave Around 150k 158kHz stable rectangle wave with equal duty without any spike or harmonic pulse NG with harmonic Check all 3 3V amp 5V power there is pulse short circuit or bad component was happened The interface board power is good The interface board is in power saving state press power key to wake up amp check your signal input SCREEN HAS INTERFERENCES OR NOISE CAN T BE FIXED BY AUTO KEY NOTE There is so many kind of interferences 1 One is cause by some VGA CARD that not meet VESA spec or power grounding too bad that influence our circuit 2 other is cause by external interferences move the monitor far from electronic
71. mmability provides enough flexibility to meet a wide range of power sequencing requirements by various panels 57 2 6 3 Panel Interface Drive Strength As mentioned previously the gmZANI has programmable output pads for the TFT panel interface Three groups of panel interface pads panel clock data and control are independently controllable and are programmed using API calls See the API reference manual for details Table 14 Panel Interface Pad Drive Strength Value 4 bits Drive Strength in mA 0 Outputs are in tri state condition 1 2 2 4mA 3 6mA 4 8mA 5 10mA 6 7 8 9 1 12mA 14mA 16mA 18mA 0 11 12 13 14 15 20mA 2 7 Host Interface The host microcontroller interface of the gmZANI has two modes of operation gmB120 compatible mode and a 4 bit serial interface mode 120 compatible mode Four signals consisting of 1 data bit a frame synchronization signal a clock signal and an Interrupt Request signal IRQ This mode is entered when a pull down resistor is not connected to number 106 4 bit serial interface mode Same as gmB120 compatible mode with the addition of three data bits so that four data bits are transferred on each clock edge This mode is entered when a 10K ohm pull down resistor is connected to MFB6 pin number 106 When the chip is configured for 4 bit host interface MFB9 7 are used as HDATA3 1 and HDATA is used a
72. n open loop not locked Panel Hsync frequency DCLK frequency Destination register value Panel Vsync frequency DCLK frequency Dest Htotal register value Dest Vtotal register value This mode is used when the input is changing or not available The OSD may still be used as in all other display modes and stable panel timing signals are produced This mode may be automatically set when gmZANI detects input timing changes that could cause out of spec operation of the panel 1 5 6 Source Stand Alone Panel Clock DCLK in open loop not locked to input Hsync Panel Hsync frequency SCLK frequency Source register value Panel Vsync frequency SCLK frequency Source Htotal register value Source Vtotal register value This mode is used to display the pattern generator data This mode may be useful for testing an LCD panel on the manufacturing line color temperature calibration etc 46 2 FUNCTIONAL DESCRIPTION Figure 3 below shows the main functional blocks inside the gmZANI 2 1 Overall Architecture Figure 3 Block Diagram for gmZANI On Screen Display Control Analog Triple Source Scaling Gamma Panel RGB ADC Timing Engine Control Timing Measurement CLUT Control Panel Generation T Dither MCU Host Clock Pixel Interface Recovery Clock Generator Clock Reference 2 2 Clock Recovery Circuit The gmZANI has a built in clock recovery circuit This circuit consists of a digital clock
73. nt bit map upper left pixel relative to the upper left pixel of the character cell is also programmable from 0 63 pixels or lines The OSD window height and width in characters rows is programmable from 1 64 The Start X Y position for the upper left corner of the OSD window is programmable in panel pixels and lines from 0 2047 There is an optional window border equal width on all four sides of the window or a window shadow the window bottom and right side the border is a solid color that is selected by an SRAM location as RGB444 The border width may be set as 1 2 4 or 8 pixels lines These parameters are summarized in Figure 12 and Table 16 The Font Data D11 0 for each line is displayed with bit D11 first leftmost and DO last The reference point for the OSD start is always the upper left corner of the Panel display which is the start leading edge of Panel Display Enable for both Horizontal and Vertical timing The OSD Window start position sets the location of the first pixel of the OSD to display including any border That is if the border is enabled the start of the character display of the OSD is offset from the OSD start position by the width height of the border 61 To improve the appearance and make it easy to find the OSD window on the screen the user may select optional shadowing 3D effect The Shadow feature operates in the same manner as in the B120 that is it produces a region of half intensity scaler
74. ntal Period Min Max TCLKs and SCLKs After register read HSYNC High Period Min Max TCLKs After register read Vertical Period Lines Every frame VSYNC High Period Lines Every frame Horizontal Display Start SCLKs Every frame Horizontal Display End SCLKs Every frame Vertical Display Start Lines Every frame Vertical Display End Lines Every frame Interlaced Input Detect N A Every frame CRC Data Line Data N A Every frame CSYNC Detect N A Every 80ms 51 The display start end registers store the first and the last pixels lines of the last frame that have RGB data above a programmed threshold The reference point of the STM block is the same as that of the source timing generator STG block The first pixel the pixel whose SCLK rising edge sees the transition of the HSYNC polarity from low to high The first line the line whose HSYNC rising edge sees the transition of the VSYNC polarity from low to high The CRC data and the line data are used to detect a test pattern image sent to the gmZANI input port 2 4 2 IRQ Controller Some input timing conditions can cause the gmZANI chip to generate an IRQ The IRQ generating conditions are programmable as given in the following table Table 12 IRQ Generation Conditions IRQ Event Remark Timing Event One of the three events Leading edge of Vsync input Panel line count the line count is programmable X Every 10ms Only one event may be selected at a time
75. on Bus provides additional 12 pins that are used as general purpose input and output GPIO pins Each pin can be independently configured as input or output MEB pins 9 through 5 have special functions When a 10K ohm pull down resistor is connected to MFB6 MFB6 has an internal pull up resistor MFB9 7 are used as host data bits HDATA3 1 When a 10K ohm pull down resistor is connected to MFB5 MFBS has an internal pull up resistor a crystal can be placed between XTAL and TCLK instead of using an external oscillator for the TCLK input Note that all pins on the multi function bus MFB11 0 are internally pulled up 2 8 On Screen Display Control The gmZANI chip has a built in OSD On Screen Display controller with an integrated font ROM The chip also supports an external OSD controller for monitor vendors to maintain a familiar user interface The internal and external OSD windows may be displayed anywhere the panel Display Enable is active regardless of whether the panel would otherwise display panel background color or active data 60 2 8 1 OSD Color Map Both the internal and external OSD display use a 16 location SRAM block for the color programming Each color location is a twelve bit value that defines the upper four bits of each of the 8 bit Red Blue and Green color components as follows e 03 0 Blue D7 4 of blue component of color 07 4 Green D7 4 of green component of color Dll 8 Red D7 4 of red component of colo
76. pical Stand alone Configuration 44 12V TFT Panel 1 5 Operating Modes The Source Clock also called SCLK in this document and the Panel Clock are defined as follows The Source Clock is the sample clock regenerated from the input Hsync timing called clock recovery by SCLK DDS direct digital synthesis and the PLL The Panel Clock is the timing clock for panel data at the single pixel per clock rate The actual PCLK to the panel may be one half of this frequency for double pixel panel data format When its frequency is different from that of source clock the panel clock is generated by Destination Clock or DCLK DDS PLL There are six display modes Native Slow DCLK Zoom Downscaling Destination Stand Alone and Source Stand Alone Each mode is unique in terms of Input video resolution vs panel resolution Source Clock frequency Panel Clock frequency ratio Source Hsync frequency Panel Hsync frequenc ratio Data source analog RGB panel background color on chip pattern generator 1 5 1 Native Panel Clock frequency Source Clock frequency Panel Hsync frequency Input Hsync frequency Panel Vsync frequency Input Vsync frequency This mode is used when the input resolution is the same as the panel resolution and the input data clock frequency is within the panel clock frequency specification of the panel being used 1 5 2 Slow DCLK Panel Clock frequency Source Clock frequency P
77. r To extend the 4 bit color value programmed to the full 8 bits the following rule is applied if any of the upper four color bits are a 1 then G B data 3 0 1111b otherwise G B data 3 0 0000b 2 8 2 On Chip OSD Controller The internal OSD uses a block of SRAM of 1536x12 bits and a ROM of 1024x12 bits The SRAM is used for both the font data and the character codes while the ROM is used to store the bit data for 56 commonly used characters The font data is for 12 pixel x 18 line characters one bit per pixel The font data starts at address zero The character codes start at any offset with an address resolution of 16 that is greater than the last location at which font data has been written It is the programmer s responsibility to ensure that there is no overlap between fonts and character codes This implementation results in a trade off between the number of unique fonts on screen at any one time and the total number of characters displayed For example one configuration would be 98 font maps 56 fonts in ROM and 42 fonts in SRAM and 768 characters e g in a 24x32 array The on chip OSD of the gmZANI can support a portrait mode in which the LCD monitor screen is rotated 90 degrees In this portrait mode all the fonts must be loaded in the SRAM because the ROM stores fonts for a landscape mode typical orientation only The font size in the portrait mode is 12 pixels by 12 lines As is the case in landscape mode the SR
78. rface are programmable For horizontal parameters Horizontal Display Enable Start Horizontal Display Enable End Horizontal Sync Start and Horizontal Sync End are programmable Vertical Display Enable Start Vertical Display Enable End Vertical Sync Start and Vertical Sync End are also fully programmable In order to maximize panel data setup and hold time the panel clock PCLKA PCLKB output skew is programmable In addition the current drive strength of the panel interface pins is programmable 53 Table 13 gmZANI TFT Panel Interface Timing Signal Name Min Typical Max Unit PVS Period tl 0 16 67 2048 lines ms Frequency 60 Hz Front porch 2 0 2048 lines Back porch a 0 2048 lines Pulse width t4 0 2048 lines PdispE t5 0 Panel height 2048 lines Disp Start from VS 16 0 2048 lines PVSsetuptpPHS 18 1 2048 PCLK 1 PVS hold from PHS t19 1 2048 PCLK 1 PHS Period 0 2048 1024 PCLK 1 Front porch t8 0 2048 PCLK 1 Back porch t9 0 2048 PCLK 1 Pulse width 00 10 2048 PCLK 1 PdispE tll 10 Panel width 2048 1024 PCLK 1 Disp Start fom HS 42 JO 2048 PCLK 1 PCLKA Frequency t13 120 60 MHz PCLKB 4 Clock H 2 04 DCLK 2 3 DCLK 3 DCLK 2 2 DCLK jns Clock L 2 05 DCLK 2 3 DCLK 3 DCLK 2 2 DCLK 5 Tvpe One pxl clock two pxl clock Data Set up 3 06 DCLK 2 5 DCLK 5 DCLK 2 2 DCLK jns Hold 3 07 DCLK 2 5 DCLK 5 DCLK 2 2
79. s For instruction Read Data or Write Data the data order is D3 0 D7 4 D11 8 The burst mode operation then uses three clocks instead of twelve for each 12 bit data or address transmission In both modes a reset pin sets the chip to a known state when the pin is pulled low The RESETn pin must be low for at least 100ns after the CVDD has become stable between 43 15V and 43 45V in order to reset the chip to a known state The gmZANI chip has an on chip pull down resistor in the HFS input pad No external pull up is required The signal stays low until driven high by the microcontroller 58 2 7 1 Serial Communication Protocol In the serial communication between the microcontroller and the gmZANI the microcontroller always acts as an initiator while the gmZANI is always the target The following timing diagram describes the protocol of the serial channel of the gmZANI chip Figure 10 Timing Diagram of the gmZANI Serial Communication Figure 10 Timing Diagram of the gmZANI Serial Communication HDATA Tum Around T ime H HCLK AES WRITE Operation DR 9550 READ Operation 59 Table 15 summarizes the serial channel specification of the gmZANI Refer to Figure 10 for the timing parameter definition Table 15 Serial Channel Specification Parameter Min Typ Max Word Size Instruction and Data 12 bits HCLK
80. status No Yes IFM have change Wake up GMZANI Yes because GMZANI was in Is current system status in Power saving E partial sleeping state No Yes Check the IFM result is in the standard Set mode index amp parameter Mode table Set change mode flag No No confirm the frequency Hsyn or Vsyn from IFM already been changed check the change mode flag Yes had been change Process turn off OSD setting GMZAN laccording to above parameter set LED status set backlight status No Check Auto config mode flag already been set Do Auto config automatically Yes Read Key status and Process on OSD screen Yes if the RS232 buffer is full Check Factory mode flag 1 process the command while adjust white balance in factory mode No Monitoring the time out of osd status if no key input persist for 10 sec the osd time out counter will trigger 6 A Interface Board Trouble Shooting chart Use the PC Win 98 white pattern with some icon on it and Change the Resolution to 640x480 60 Hz 31 KHz NOTICE The free running freq of our system is 48 KHz 60 Hz so we recommend to use another resolution to do trouble shooting this trouble shooting is proceed with 640x480 60Hz 31Khz I NO SCREEN APPEAR DC Power Part Measured Input DC voltage 1 12 V Measured U305 AIC 1084 pin 2 3 3V Check Correspondent component Measured 0904 LT1117 2 3 3 V Is there any s
81. synthesizer and an analog PLL The clock recovery circuit generates the clock used to sample analog RGB data SCLK or source clock This circuit is locked to the HSUNC of the incoming video signal The RCLK generated from the TCLK input is used as a reference clock The clock recovery circuit adjusts the SCLK period so that the feedback pulse generated every SCLK period multiplied by the Source Horizontal Total value as programmed into the registers locks to the rising edge of the Hsync input Even though the initial SCLK frequency and the final SCLK frequency are as far apart as 60MHz locking can be achieved in less than 1ms across the operation voltage temperature range 47 The SCLK frequency 1 SCLK period can be set to the range of 10 to 135 MHz Using the DDS direct digital synthesis technology the clock recovery circuit can generate any SCLK clock frequency within this range The pixel clock DCLK or destination clock is used to drive a panel when the panel clock is different from SCLK or SCLK 2 It is generated by a circuit virtually identical to the clock recovery circuit The difference is that DCLK is locked to SCLK while SCLK is locked to the Hsync input DCLK frequency divided by N is locked to SCLK frequency divided by M The value M and N are calculated and programmed in the register by firmware The value M should be close to the Source Htotal value Figure 4 Clock Recovery Circuit DDS Digital Hsync Clock
82. t Video Signal Analog signal 0 7Vpp Video signal termination impedance 75 OHM Scanning Frequencies Horizontal 29 KHz 80 KHz Vertical 55Hz 75 Hz Pixel clock 135 MHz Factory Preset Timing 18 User Timings 19 Input signal tolerance H tolerance 1 V tolerance Hz Power Source Switching Mode Power Supply AC 100 240 V 50 60 Hz Universal Type Operating Temperature 0 50 C Ambient Non operating Temperature 20C 60 C Humidity Operating 20 to 80 RH non condensing Non Operating 5 to 95 RH 38 7 maximum wet bulb temperature Weight 5 5 kg External Connection 15Pin D type Connector AC power Cord View Angle x axis right left 2 60 y axis up down 40 60 Outside dimension Width x Height x Thickness 422x 449 x 215 mm Plug and Play VESA DDCI DDC2B Power saving VESA DPMS 1 2 LCD MONITOR DESCRIPTION The LCD MONITOR will contain an main board an Inverter module keyboard and External Adapter which house the flat panel control logic brightness control logic DDC and DC DC conversion The Inverter module will drive the backlight of panel The Adapter will provides the 12V DC power 5 Amp to Main board and Inverter module Monitor Block Diagram IEEE x CCFT Drive Flat Panel and CCFL backlight Main Board or Interface Board LI RS232 Connector i For white balance adjustment in factory mode Keyboard ADAPTER HOST Computer Video signal DDC
83. the RED on OSD window until chroma 7120 indicator reached the value R 100 11 12 13 14 adjust the GREEN OSD until chroma 7120 indicator reached G 100 adjust the BLUE on OSD until chroma 7120 indicator reached 100 repeat above procedure item 8 9 10 until chroma 7120 RGB value meet the tolence 100 2 switch the chroma 7120 to xyY mode With press button Adjust the Contrast on OSD window until the Y measurement on chroma 7120 reached the value Y 180 cd m Press 78 on OSD window to save the adjustment result b adjust 6500 color temperature 11 Set the Contrast of OSD function to 40 Brightness to 48 Switch the chroma 7120 to RGB mode with press button switch the MEM channel to Channel 06 with up or down arrow on chroma 7120 Icd indicator on chroma 7120 will show x 313 10 329 10 160 5 cd m Adjust the RED on OSD window until chroma 7120 indicator reached the value R 100 adjust the GREEN on OSD until chroma 7120 indicator reached G 100 adjust the BLUE on OSD until chroma 7120 indicator reached B 100 repeat above procedure item 5 6 7 until chroma 7120 RGB value meet the tolence 100 2 switch the chroma 7120 to xyY mode With press button Adjust the Contrast on OSD window until the Y measurement on chroma 7120 reached the value Y 180 cd m Press 65 on OSD window to save the adjustment result
84. tion technology as well as a proven integrated ADC PLL to provide excellent image quality within a cost effective SVGA XGA LCD monitor solution As a pin compatible replacement for the gmB120 the gmZANI incorporates all of the gmB120 features plus many enhanced features including 10 bit gamma correction Adaptive Contrast Enhancement ACE filtering Sync On Green SOG and an enhanced OSD 1 1 Features Fully integrated 135MHz 8 bit triple ADC PLL and pre amplifier GmZ2 scaling algorithm featuring new Adaptive Contrast Enhancement ACE On chip programmable OSD engine Integrated PLLs 10 bit programmable gamma correction Host interface with 1 or 4 data bits Pin compatible with gmB120 Integrated Analog Front End Integrated 8 bit triple ADC Upto 135MHz sampling rates No additional components needed All color depths up to 24 bits pixel are supported High Quality Advanced Scaling Fully programmable zoom Independent horizontal vertical zoom Enhanced and adaptive scaling algorithm for optimal image quality Recovery Mode Native Mode Input Format Analog RGB up to XGA 85Hz Support for Sync On Green SOG Support for composite sync modes Output Format X Support for 8 or 6 bit panels with high quality dithering One or two pixel output format Built In High Speed Clock Generator Fully programmable timing parameters On chip PLLs generate clocks for the on chip ADC and pixel clock
85. udes bandgap reference master biasing and full scale adjust Must be directly connected to analog system ground plane 84 ADC VDDA Analog power for ADC analog blocks that are shared by all three channels Includes bandgap reference master biasing and full scale adjust Must be bypassed with 0 1uF capacitor to pin 82 ADC GNDA 83 Reserved For internal testing purpose only Do not connect 85 ADC BGNDA Analog ground for the blue channel Must be directly connected to the analog system ground plane 88 ADC BVDDA Analog power for the blue channel Must be bypassed with 0 1uF capacitor to pin 85 BGNDA 86 BLUE Negative analog input for the Blue channel 87 BLUE Positive analog input for the Blue channel 89 GGNDA Analog ground for the green channel Must be directly connected to the analog system ground plane 92 ADC GVDDA Analog power for the green channel Must be bypassed with 0 luF capacitor to pin 89 ADC GGNDA 90 GREEN Negative analog input for the Green channel 91 GREEN Positive analog input for the Green channel 93 ADC RGNDA Analog ground for the red channel Must be directly connected to the analog system ground plane 96 ADC RVDDA Analog power for the red channel Must be bypassed with 0 1 capacitor to pin 93 ADC RGNDA 94 RED I Negative analog input for the Red channel 95 RED I Positive analog input for the Red channel 39 Table 2 Host Interface HIF External On Screen

AOC 41A50-144 User's Manual

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