Analog Devices AD8342 User's Manual
Contents
1. Rev 0 Page 19 of 20 AD8342 OUTLINE DIMENSIONS 0 60 MAX 3 PIN 1 2 75 INDICATOR BSC SQ 12 Mx 0 80 MAX gt 0 90 0 65 TYP 0 85 i nan 1 0 05 MAX Ken A 0 02 NOM SEATING ee PLANE o 0 25 0 20 REF 0 18 COMPLIANT TO JEDEC STANDARDS MO 220 VEED 2 EXCEPT FOR EXPOSED PAD DIMENSION Figure 54 16 Lead Lead Frame Chip Scale Package LFCSP VQ 3mm x 3 mm Body Very Thin Quad CP 16 3 Dimensions in millimeters ORDERING GUIDE Temperature Package Transport Media Models Package Package Description Outline Branding Quanity AD8342ACPZ REEL71 40 C to 85 C 16 Lead Lead Frame Chip Scale Package CP 16 3 Q01 1 500 Reel LFCSP VQ AD8342ACPZ R21 40 C to 85 C 16 Lead Lead Frame Chip Scale Package CP 16 3 Q01 250 Reel ILFCSP VO AD8342ACPZ WP 40 C to 85 C 16 Lead Lead Frame Chip Scale Package CP 16 3 Q01 50 VVaffle Pack LFCSP VQ AD8342 EVAL Evaluation Board 1 12 Pb free part ANALOG DEVICES Rev 0 Page 20 of 20 2005 Analog Devices Inc All rights reserved Trademarks and regis tered trademarks are the property of their respective owners D05352 0 4 05 0 Www analog Com2. 94 100 lt 100 lt 100 lt 100 100 6 lt 100 lt 100 lt 100 1 99 100 1 96 lt 100 lt 100 lt 100 lt 100 lt 100 lt 100 lt 100 100 100 n 7 100 lt 100 lt 100 lt 100 96 100 98 100 lt 100 lt 100 lt 100 lt 100 lt 100 lt 100 100 8 lt 100 lt 100 lt 100 lt 100 lt 100 100 100 100 1 97 lt 100 lt 100 lt 100 100 100 100 9 lt 100 lt 100 lt 100 lt 100 lt 100 100 100 lt 100 lt 100 lt 100 100 99 lt 100 lt 100 100 10 lt 100 lt 100 lt 100 100 lt 100 lt 100 lt 100 lt 100 100 lt 100 1 99 lt 100 lt 100 lt 100 100 11 lt 100 lt 100 lt 100 100 lt 100 lt 100 100 96 100 1 97 lt 100 96 lt 100 lt 100 100 12 lt 100 lt 100 lt 100 lt 100 lt 100 lt 100 100 100 1 99 lt 100 1 98 lt 100 lt 100 lt 100 100 13 lt 100 lt 100 lt 100 lt 100 lt 100 lt 100 100 100 100 1 97 100 1 97 99 100 100 14 lt 100 lt 100 lt 100 lt 100 lt 100 100 lt 100 lt 100 lt 100 100 1 98 98 lt 100 lt 100 100 15 lt 100 lt 100 lt 100 lt 100 lt 100 100 lt 100 lt 100 lt 100 lt 100 100 lt 100 100 100 100 Rev 0 Page 5 of 20 AD8342 ABSOLUTE MAXIMUM RATINGS Ta
3. sa te RERO EE eS 15 cite ag 16 LO Considerations NENNEN 17 High IF Applications isisi 18 Evaluation Board ENEE 19 Outline Dimensions NENNEN 20 Ordering Guide tectae teet 20 Rev 0 Page 2 of 20 SPECIFICATIONS AD8342 Vs 5V TA 25 C far 238 MHz fio 286 MHz LO power 0 dBm Zo 50 O Raus 1 82 kO RF termination 100 O IF termi nated into 100 Q through a 2 1 ratio balun unless otherwise noted Table 1 Parameter Conditions Min Typ Max Unit RF INPUT INTERFACE Return Loss Hi Z input terminated with 100 O off chip resistor 10 dB Input Impedance Frequency 238 MHz measured at RFIN with RFCM ac 1 0 4 kOllpF grounded DC Bias Level Internally generated port must be ac coupled 24 V OUTPUT INTERFACE Output Impedance Differential impedance frequency 48 MHz 10 0 5 kQ pF DC Bias Voltage Supplied externally 475 Vs 5 25 V Power Range Via a 2 1 impedance ratio transformer 13 dBm LO INTERFACE Return Loss 10 dB DC Bias Voltage Internally generated port must be ac coupled Vs 1 6 V POWER DOWN INTERFACE PWDN Threshold 3 5 V PWDN Response Time Device enabled IF output to 9096 of its final level 0 4 us Device disabled supply current 5 mA 4 us PWDN Input Bias Current Device enabled 80 uA Device disabled 100 uA POWER SUPPLY Positive Supply Voltage 4 75 5 5 25 V Quiescent Current VPDC Supply current for bias cells 5 mA IFOP IFOM Su
4. 238 MHz 10 9 8 EE 5 kJ 6 m 2 5 n 5 4 a 3 2 0 8 40 20 0 20 40 60 80 TEMPERATURE C Figure 17 Input P1dB vs Temperature frr 238 MHz fio 286 MHz INPUT P1dB dBm INPUT P1dB dBm PERCENTAGE Rev 0 Page 10 of 20 05352 014 IF FREQUENCY MHz Figure 18 Input P1dB vs IF Frequency 10 05352 031 4 75 4 85 4 95 5 05 5 15 VPOS V D io a Figure 19 Input P1dB vs Vpos far 238 MHz fio 286 MHz 2g NORMAL MEAN 8 3 STD DEV 0 07 IP1dB 238MHz 22 PERCENTAGE 05352 056 MON FD o 00 8 05 8 10 8 15 8 20 8 25 8 30 8 35 8 40 8 45 8 50 8 55 8 60 IP1dB 238MHz Figure 20 Input IP3 Distribution fre 238 MHz fio 286 MHz INPUT IP2 dBm NOISE FIGURE dB 100 05352 010 150 200 250 300 350 400 450 500 55 RF FREQUENCY MHz o Figure 21 Input IP2 vs RF Frequency Second RF R F 50 MHz INPUT IP2 dBm 60 58 56 54 52 50 48 46 44 42 40 IF 10MHz _ IF 48MHz IF 90MHz IF 140MHz 15 13 11 9 7 5 3 1 1 3 5 LO LEVEL dBm Figure 22 Input IP2 vs LO Level far 238 MHz 188MHz 14 0 13 5 13 0 12 5 12 0 11 5 11 0 50
5. m m e a a z LO LEVEL dBm Figure 10 Input IP3 vs LO Level far 238 MHz far 239 MHz 27 26 25 24 m 23 B 22 E B 21 z 20 19 18 8 17 8 40 20 0 20 40 60 80 TEMPERATURE C Figure 11 Input IP3 vs Temperature far 238 MHz far 239 MHz fio 286 MHz INPUT IP3 dBm PERCENTAGE Rev 01 Page 9 of 20 INPUT IP3 dBm AD8342 05352 008 E o e o a o N o o nN a o e o e e o IF FREQUENCY MHz Figure 12 Input IP3 vs IF Frequency 27 26 25 24 23 22 21 20 19 18 05352 028 17 4 75 4 80 4 85 4 90 4 95 5 00 5 05 5 10 5 15 5 20 5 25 VPOS V Figure 13 Input IP3 vs Vpos far 238 MHz far 239 MHz LO Frequency 286 MHz NORMAL MEAN 22 7 STD DEV 0 41 INPUT IP3 238MHz PERCENTAGE 05352 055 0 20 6 21 0 21 4 21 8 22 2 226 23 0 23 4 23 8 24 INPUT IP3 238MHz N Figure 14 Input IP3 Distribution frr 238 MHz fio 286 MHz AD8342 INPUT P1dB dBm 140MHz 50 100 150 200 250 300 350 400 450 500 550 RF FREQUENCY MHz Figure 15 Input P1dB vs RF Frequency E m m A 2d 2 a 2 LO LEVEL dBm Figure 16 Input P1dB vs LO Level far
6. 05352 016 100 150 200 250 300 350 400 450 500 550 RF FREQUENCY MHz Figure 23 Noise Figure vs RF Frequency IF Frequency 48 MHz 05352 029 INPUT IP2 dBm INPUT IP2 dBm NOISE FIGURE dB Rev 0 Page 11 of 20 AD8342 RF 238MHz RF 460MHz 10 50 100 150 200 250 300 35 IF FREQUENCY MHz 05352 011 o Figure 24 Input IP2 vs IF Frequency Second RF R F 50 MHz 60 58 56 54 52 50 48 46 44 42 40 4 75 4 85 4 95 5 05 5 15 5 VPOS V Figure 25 Input IP2 vs Vpos far 238 MHz far 188 MHz fio 286 MHz RF 460MHz 10 60 110 160 210 260 IF FREQUENCY MHz Figure 26 Noise Figure vs IF Frequency 310 05352 017 05352 030 AD8342 NF 140MHz NF 90MHz Lu z 1 s 15 13 11 9 7 5 3 1 5 LO POWER dBm Figure 27 Noise Figure vs LO Power far 238 MHz 5 0 4 5 4 0 3 5 amp 3 0 B z 25 E 9 20 1 5 1 0 0 5 0 18 20 22 24 26 28 30 32 34 Reias KO 05352 024 PERCENTAGE NOISE FIGURE AND INPUT IP3 dBm Figure 28 Gain vs Raas RF Frequency 238 MHz LO Frequency 286MHz 61 59 57 e a INPUT IP2 dBm oa oa A A N 45 1 8 2 0 2 2 2 4 2 6 2 8 3 0 Rpias KO 3 2 3 4 05352 037 INPUT P1
7. unless otherwise noted 6 RF 238MHz a a kJ kJ z z E E RF z 460MHz o eo z 2 1 8 8 50 100 150 200 250 300 350 400 450 500 550 10 50 100 150 200 250 300 350 FREQUENCY MHz IF FREQUENCY MHz Figure 3 Conversion Gain vs RF Frequency Figure 6 Conversion Gain vs IF Frequency 5 0 4 5 4 0 3 5 n T 3 0 kJ S z z 25 x o 9 20 1 5 1 0 8 0 5 S 8 0 8 15 10 5 0 5 4 75 4 85 4 95 5 05 5 15 5 25 LO LEVEL dBm VPOS V Figure 4 Gain vs LO Level RF Frequency 238 MHz Figure 7 Gain vs Vpos far 238 MHz fio 286 MHz 5 0 4 5 7 E z 0 06 4 0 GAIN 238MHz PERCENTAG 3 5 5 3 0 2 2 2 5 5 q m 2 0 amp 1 5 1 0 0 5 8 8 8 0 8 40 20 0 20 40 60 80 3 40 3 45 3 50 3 55 3 60 3 65 3 70 3 75 3 80 3 85 3 90 TEMPERATURE C CONVERSION GAIN 238MHz Figure 5 Gain vs Temperature far 238 MHz fio 286 MHz Figure 8 Conversion Gain Distribution fer 238 MHz fio 286 MHz Rev 0 Page 8 of 20 INPUT IP3 dBm 27 26 25 IF 48MHz 24 IF 90MHz 10MHz 23 22 21 IF 140MHz 19 18 8 17 8 50 100 150 200 250 300 350 400 450 500 550 RF FREQUENCY MHz Figure 9 Input IP3 vs RF Frequency E
8. 302CS series inductors were selected due to their very high self resonant frequency and Q A 1 1 balun was ac coupled to the output to convert the differential output to a single ended signal and present the output with a 50 Q ac loading impedance The performance of the circuit is shown in Figure 52 The aver age ACPR of the adjacent and alternate channels is presented vs output power The circuit provides a 65 dBc ACPR at 13 dBm output power The optimum ACPR power level can be shifted to the right or left by adiusting the output loading and the loss of the input match ADJACENT CHANNELS ACPR dBc ALTERNATE CHANNELS 05352 053 25 20 15 10 5 OUTPUT POWER dBm Figure 52 Single Carrier WCDMA ACPR Performance of Tx Up Conversion Circuit Test Model 1_64 o Rev 0 Page 18 of 20 EVALUATION BOARD AD8342 An evaluation board is available for the AD8342 The evaluation board is configured for single ended signaling at the IF output port via a balun transformer The schematic for the evaluation board is presented in Figure 53 PWDN PWDNO C11 Wi GND VPOS ypos INLO Figure 53 Evaluation Board Table 6 Evaluation Board Configuration Options C10 V 100pF 0 1uF C8 P i i i T f ooor O IF OUT 1000 TRACES e NO GROUND PLANE 1 O IF OUT 05352 003 Component Function Default Conditions R1 R2 R7 Supply decoupling Shorts or power su
9. 342 TOP VIEW Not to Scale IFOP 7 OMM 8 COMM 5 IFOM 6 05352 002 Figure 2 16 Lead LFCSP Table 5 Pin Function Descriptions Pin No Mnemonic Function 1 VPLO Positive Supply Voltage for the LO Buffer 4 75 V to 5 25 V 2 LOCM AC Ground for Limiting LO Amplifier Internally biased to Vs 1 6 V AC couple to ground 3 LOIN LO Input Nominal input level 0 dBm Input level range 10 dBm to 4 dBm relative to 50 0 Internally biased to Vs 1 6 V AC couple 4 5 8 9 13 COMM Device Common DC Ground 6 7 IFOM IFOP Differential IF Outputs Open Collectors Each requires dc bias of 5 00 V nominal 10 EXRB Mixer Bias Voltage Connect resistor from EXRB to ground Typical value of 1 82 kO sets mixer current to nominal value Minimum resistor value from EXRB to ground 1 8 kO Internally biased to 1 17 V 11 PWDN Connect to Ground for Normal Operation Connect pin to Vs for disable mode 12 VPDC Positive Supply Voltage for the DC Bias Cell 4 75 V to 5 25 V 14 RFCM AC Ground for RF Input Internally biased to 2 4 V AC couple to ground 15 RFIN RF Input Internally biased to 2 4 V Must be ac coupled 16 VPMX Positive Supply Voltage for the Mixer 4 75 V to 5 25 V Rev 0 Page 7 of 20 AD8342 TYPICAL PERFORMANCE CHARACTERISTICS Vs 5 V Ta 25 C RF power 10 dBm LO power 0 dBm Zo 50 Reus 1 82 kO RF termination 100 IF terminated into 100 O via a 2 1 ratio balun
10. ANALOG DEVICES Active Receive Mixer LF to 500 MHz AD8342 FUNCTIONAL BLOCK DIAGRAM VPDC PWDN EXRB COMM FEATURES Broadband RF port LF to 500 MHz Conversion gain 3 7 dB Noise figure 12 2 dB Input IP3 22 7 dBm Input P as 8 3 dBm LO drive 0 dBm Differential high impedance RF input port Single ended 50 LO input port Single supply operation 5 V 98 mA Power down mode Exposed paddle LFCSP 3 mm x 3 mm APPLICATIONS Cellular base station receivers ISM receivers Radio links RF instrumentation GENERAL DESCRIPTION The AD8342 is a high performance broadband active mixer It is well suited for demanding receive channel applications that require wide bandwidth on all ports and very low inter modulation distortion and noise figure The AD8342 provides a typical conversion gain of 3 7 dB with an RF frequency of 238 MHz The integrated LO driver presents a 50 Q input impedance with a low LO drive level helping to minimize the external component count The differential high impedance broadband RF port allows for easy interfacing to both active devices and passive filters The RF input accepts input signals as large as 1 6 V p p or 8 dBm relative to 50 at Pras Rev 0 Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result fro
11. Bc LO TO RF INPUT LEAKAGE LO power 0 dBm fio 286 MHz 55 dBc 2x LO TO IF OUTPUT LEAKAGE LO power 0 dBm far 238 MHz fio 286 MHz 47 dBm F terminated into 100 O and measured vvith a differential probe RF TO IF OUTPUT LEAKAGE RF power 10 dBm far 238 MHz fio 286 MHz 32 dBc IF 2 SPURIOUS RF power 10 dBm far 238 MHz fio 286 MHz 70 dBc Frequency ranges are those that were extensively characterized this device can operate over a wider range See the High IF Applications section for details Rev 0 Page 4 of 20 AD8342 SPUR TABLE Vs 5 V Ta 25 C RF and LO power 0 dBm fre 238MHz fio 286MHZ Zo 50 O 1 82 kO RF termination 100 IF terminated into 100 O via a 2 1 ratio balun Note Measured using standard test board Typical noise floor of measurement system 100 dBm Table 3 m nfrr mfio 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 0 100 1 25 54 28 45 35 39 36 42 57 44 42 41 46 59 1 39 3 5 42 6 48 16 50 28 57 37 68 45 54 37 61 2 52 47 51 49 54 56 56 62 62 66 71 80 80 67 79 3 81 57 79 61 82 61 74 69 94 85 89 86 86 90 81 4 78 70 80 79 80 85 87 92 93 96 95 100 1 97 100 95 5 98 79 95 87 96 94 95 88 98
12. O and the RF fio far high side or far fio low side is the intermediate frequency f r In addition to the desired RF signal an RF image is downconverted to the desired IF frequency The image frequency is at fio frr when driven with a high side LO When using a broadband load the conversion gain of the AD8342 is nearly constant over the specified RF input band see Figure 3 The AD8342 is designed to operate over a broad frequency range It is essential to ac couple RF and LO ports to prevent dc offsets from skewing the mixer core in an asymmetrical man ner potentially degrading noise figure and linearity The RF input of the AD8342 is high impedance 1 kQ across the frequency range shown in Figure 41 The input capacitance decreases with frequency due to package parasitics RESISTANCE kQ CAPACITANCE pF 0 0 0 100M 200M 300M 400M 500M 600M 700M 800M 900M 1G FREQUENCY Hz 05352 042 Figure 41 RF Input Impedance The matching or termination used at the RF input of the AD8342 has a direct effect on its dynamic range The charac terization circuit as well as the evaluation board uses a 100 Q resistor to terminate the RF port This termination resistor in shunt with the input stage results in a return loss of better than 10 dBm relative to 50 Table 4 shows gain IP3 P1dB and noise figure for four different input networks This data was measured at a
13. below 1 8 KO are used This resistor sets the dc current through the mixer core The performance effects of changing this resistor can be seen in the Typical Per formance Characteristics section EXTERNAL BIAS VPDC RESISTOR PWDN RFIN RFCM 05352 040 Figure 39 Simplified Schematic Showing the Key Elements of the AD8342 As shown in Figure 40 the IF output pins IFOP and IFOM are directly connected to the open collectors of the NPN transistors in the mixer core so the differential and single ended imped ances looking into this port are relatively high on the order of several kO A connection between the supply voltage and these output pins is required for proper mixer core operation IFOP IFOM LOIN RFIN RFCM 05352 041 COMM Figure 40 AD8342 Simplified Schematic The AD8342 has three pins for the supply voltage VPDC VPMX and VPLO These pins are separated to minimize or eliminate possible parasitic coupling paths within the AD8342 that could cause spurious signals or reduced interport isolation Consequently each of these pins should be well bypassed and decoupled as close to the AD8342 as possible Rev 0 Page 14 of 20 AC INTERFACES The AD8342 is designed to downconvert radio frequencies RF to lower intermediate frequencies IF using a high or low side local oscillator LO The LO is injected into the mixer core at a frequency higher or lower than the desired input RF The difference between the L
14. ble 4 Parameter Stresses above those listed under Absolute Maximum Ratings Supply Voltage Vs RF Input Level LO Input Level PWDN Pin IFOP IFOM Bias Voltage Minimum Resistor from EXRB to COMM Internal Power Dissipation Osa Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Rating may cause permanent damage to the device This is a stress 55V rating only functional operation of the device at these or any 12 dBm other conditions above those indicated in the operational sec 12 dBm tion of this specification is not implied Exposure to absolute Vs 05V maximum rating conditions for extended periods may affect 5 5 V device reliability 1 8 kQ 650 mW 77 C W 135 C 40 C to 85 C 65 C to 150 C ESD CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although this product features WO Cl proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy Sprit 4 electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality ESD SENSITIVE DEVICE Rev 0 Page 6 of 20 AD8342 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 16 VPMX 15 RFIN 14 RFCM 13 COMM PIN 1 VPLO 1 Qf INDICATOR LOCM 2 j LOIN 3 i COMM AV AD8
15. ctral spreading of the downconverted sig nal limiting the sensitivity of the mixer at frequencies close in to any large input signals The internal LO buffer provides enough gain to hard limit the input LO and provide fast switch ing of the mixer core Odd harmonic content present on the LO drive signal should not impact mixer performance however even order harmonics cause the mixer core to commutate in an unbalanced manner potentially degrading noise performance Simple lumped element low pass filtering can be applied to help reject the harmonic content of a given local oscillator as shown in Figure 50 The filter depicted is a common 3 pole Chebyshev designed to maintain a 1 to 1 source to load impedance ratio with no more than 0 5 dB of ripple in the pass band Other filter structures can be effective as long as the second harmonic of the LO is filtered to negligible levels for example 30 dB below the fundamental AD8342 LOCM LOIN COMM LO SOURCE c1 c3 m 2 FOR Rs RL Ciz 1 864 12 KO 1 834 2n cRL 207 2n cRL fc FILTER CUTOFF FREQUENCY 05352 050 Figure 50 Using a Low Pass Filter to Reduce LO Second Harmonic Rev 0 Page 17 of 20 AD8342 HIGH IF APPLICATIONS In some applications it may be desirable to use the AD8342 as an up converting mixer The AD8342 is a broadband mixer capable of both up and down conversion Unlike other mixers that rely on on chip reactive circuitry to optimize pe
16. d to control the power dissipa tion and dynamic range of the AD8342 Because the AD8342 has internal resistive degeneration the conversion gain is pri marily determined by the load impedance and the on chip degeneration resistors Figure 49 shows how gain varies with IF load The external Rais resistor has only a small effect The most direct way to affect conversion gain is by varying the load impedance Small loads result in lower gains while larger loads increase the conversion gain If the IF load impedance is too large it causes a decrease in linearity P1dB IP3 In order to maintain positive conversion gain and preserve SFDR perform ance the differential load presented at the IF port should remain in the range of 100 O to 250 O AD8342 30 MODELED d 25 7 J 2 20 7 z b ki MEASURED u 15 o lt a E 9 10 gt fe 5 A 0 8 10 100 1000 IF LOAD Figure 49 Voltage Conversion Gain vs IF Loading LO CONSIDERATIONS The LOIN port provides a 50 Q load impedance with common mode decoupling on LOCM Again common grade ceramic capacitors provide sufficient signal coupling and bypassing of the LO interface The LO signal needs to have adequate phase noise characteris tics and low second harmonic content to prevent degradation of the noise figure performance of the AD8342 An LO plagued with poor phase noise can result in reciprocal mixing a mecha nism that causes spe
17. dB dBm Figure 29 Input IP2 vs Raus far 238 MHz Second RF RF SOMHz fio 286 MHz Rev 0 Page 12 of 20 NORMAL MEAN 12 25 STD DEV 0 14 NF PERCENTAGE 05352 023 0 11 8 11 9 12 0 12 1 12 2 12 3 12 4 12 5 12 6 12 7 12 8 NOISE FIGURE dB Figure 30 Noise Figure Distribution far 238 MHz fio 286 MHz 105 100 1 8 2 0 2 2 2 4 2 6 2 8 3 0 Rgias KO Figure 31 Noise Figure Input IP3 and Supply Current vs Raas fari 238 MHz frr2 239 MHz fio 286 MHz 10 9 1 8 2 0 2 2 2 4 2 6 2 8 3 0 3 2 3 4 Bas KO Figure 32 Input P1dB vs Reis far 238 MHz fio 286 MHz 05352 036 SUPPLY CURRENT mA 05352 015 LEAKAGE dBc FEEDTHROUGH dBc AD8342 0 120 10 100 20 30 E z 40 R E 60 50 o a gt a 70 20 90 8 0 8 50 250 450 650 850 40 20 0 20 40 60 80 LO FREQUENCY MHz TEMPERATURE C Figure 33 LO to RF Leakage vs LO Frequency LO Power 0 dBm Figure 36 Supply Current vs Temperature o m a s 8 2 2 a m z E R H m 50 100 150 200 250 300 350 400 450 500 550 0 RF FREQUENCY MHz LO FREQUENCY MHz Figure 34 RF to IF Feedthrough RF Power 10 dBm Figu
18. er and Impedance Buffer The high input impedance of the AD8351 allows for a shunt differential termination to provide the desired 100 Q load to the AD8342 IF output port It is necessary to bias the open collector outputs using one of the schemes presented in Figure 47 and Figure 48 Figure 47 illustrates the application of a center tapped impedance trans former The turns ratio of the transformer should be selected to provide the desired impedance transformation In the case of a 50 Q load impedance a 2 to 1 impedance ratio transformer should be used to transform the 50 Q load into a 100 Q differ ential load at the IF output pins Figure 48 illustrates a differen tial IF interface where pull up choke inductors are used to bias the open collector outputs The shunting impedance of the choke inductors used to couple dc current into the mixer core should be large enough at the IF operating frequency so it does not load down the output current before reaching the intended load Additionally the dc current handling capability of the selected choke inductors needs to be at least 45 mA The self resonant frequency of the selected choke should be higher than the intended IF frequency A variety of suitable choke inductors are commercially available from manufacturers such as Murata and Coilcraft Figure 46 shows the loading effects when using nonideal inductors An impedance transforming network may be required to transform the final load impedance
19. ers for the AD8342 were measured with 100 O differential terminations However dif ferent load impedances may be used where circumstances dic tate In general lower load impedances result in lower conver sion gain and lower output P1dB Higher load impedances result in higher conversion gain for small signals but lower IP3 values for both input and output If the IF signal is to be delivered to a remote load more than a few millimeters away at high output frequencies avoid unin tended parasitic effects due to the intervening PCB traces One approach is to use an impedance transforming network or transformer located close to the AD8342 If very wideband out put is desired a nearby buffer amplifier may be a better choice especially if IF response to dc is required An example of such a circuit is presented in Figure 45 in which the AD8351 differen tial amplifier is used to drive a pair of 75 O transmission lines The gain of the buffer can be independently set by appropriate choice of the value for the gain resistor Rc 50 0 5 45 0 4 40 35 g 5 i 30 0 2 Z 25 E 7 4 9 2 4 a 2 ul 15 0 10 0 1 0 0 2 0 100M 200M 300M 400M 500M 600M 700M 800M 900M 1G FREQUENCY Hz 05352 045 Figure 44 IF Port Impedance Re AD8351 V 2 1000 Tx LINE Zo 750 Tx LINE Zo 750 ZL 05352 046 Figure 45 AD8351 Used as Transmission Line Driv
20. ircuit low enough so that phase and magnitude variations are below an acceptable level over the 5 MHz band It is possible to use purely reactive matching to transform a 50 Q source to match the raw 1 kO input impedance of the AD8342 However the L and C component variations could present production concerns due to the sensitivity of the match For this application it is advantageous to shunt down the 1 kO input impedance using an external shunt termination resistor to allow for a lower Q reactive matching network The input is terminated across the RFIN and RFCM pins using a 499 Q termination The termination should be as close to the device as possible to minimize standing wave concerns The RFCM is bypassed to ground using a 1 nF capacitor A dc blocking ca pacitor of 1 nF is used to isolate the dc input voltage present on the RFIN pin from the source A step up impedance transfor mation is realized using a series L shunt C reactive network The actual values used need to accommodate for the series L and stray C parasitics of the connecting transmission line seg ments When using the customer evaluation board with the components specified in Figure 51 the return loss over a 5 MHz band centered at 170 MHz was better than 10 dB External pull up choke inductors are used to feed dc bias into the open collector outputs It is desirable to select pull up choke inductors that present high loading reactance at the output frequency Coilcraft 0
21. l connected to the LO input There are three limiting gain stages between the external LO signal and the switching core The first stage converts the single ended LO drive to a well balanced differential drive The differential drive then passes through two more gain stages which ensures a lim ited signal drives the switching core This affords the user a lower LO drive requirement while maintaining excellent distor tion and compression performance The output signal of these three LO gain stages drives the four transistors within the mixer core to commutate at the rate of the local oscillator frequency The output of the mixer core is taken directly from its open collectors The open collector outputs present a high impedance at the IF frequency The conversion gain of the mixer depends directly on the impedance presented to these open collectors In characterization a 100 Q load was presented to the part via a 2 1 impedance transformer The device also features a power down function Application of a logic low at the PWDN pin allows normal operation A high logic level at the PWDN pin shuts down the AD8342 Power consumption when the part is disabled is less than 10 mW The bias for the mixer is set with an external resistor Raus from the EXRB pin to ground The value of this resistor directly affects the dynamic range of the mixer The external resistor should not be lower than 1 82 kO Permanent damage to the part could result if values
22. m its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners 05352 001 VPLO LOCM LOIN COMM Figure 1 The open collector differential outputs provide excellent bal ance and can be used with a differential filter or IF amplifier such as the AD8369 or AD8351 These outputs can also be con verted to a single ended signal through the use of a matching network or a transformer balun When centered on the VPOS supply voltage the outputs may swing 2 V differentially The AD8342 is fabricated on an Analog Devices proprietary high performance SiGe IC process The AD8342 is available in a 16 lead LFCSP It operates over a 40 C to 85 C temperature range An evaluation board is also available One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 O 2005 Analog Devices Inc All rights reserved AD8342 TABLE OF CONTENTS ee 3 eet 4 Spur Table tre t eter 5 Absolute Maximum Ratings seen 6 BEE AEN eet 6 Pin Configuration and Function Descriptions 7 Typical Performance Characteristics 8 Circuit Descriptions E RUeDEIDIRIGI TE EE 14 REVISION HISTORY 4 05 Revision 0 Initial Version AC Interfaces s
23. n RF frequency of 250 MHz and at an LO frequency of 300 MHz AD8342 Table 4 Dynamic Performance for Various Input Networks Input 500 1000 5000 Matched Network Shunt Shunt Shunt Fig 40 Gain dB 0 66 3 5 5 3 9 3 IIP3 dBm 25 4 22 9 20 6 18 5 P1dB dBm 10 8 8 4 6 3 2 3 NF dB 14 12 5 10 2 10 5 The RF port can also be matched using an LC circuit as shown in Figure 42 500 gt 100nH 1000 j0 Zo 500 fain 250MHz 05352 043 Figure 42 Matching Circuit Impedance transformations of greater than 10 1 result in a higher Q circuit and thus a narrow RF input bandwidth A 1 kO resistor is placed across the RF input of the device in parallel with the device internal input impedance creating a 500 O load This impedance is matched to as close as possible to 50 Q for the source with standard components using a shunt C series L matching circuit see Figure 43 g 8 8 8 Point 1 1000 0 j0 0 Q 0 0 at 250 000 MHz Point 2 500 0 j0 0 Q 0 0 at 250 000 MHz Point 3 55 6 157 2 2 8 at 250 000 MHz Point 4 55 6 j0 1 Q Q 0 0 at 250 000 MHz Figure 43 LC Matching Example Rev 0 Page 15 of 20 AD8342 IF PORT The IF port comprises open collector differential outputs The NPN open collectors can be modeled as current sources that are shunted with resistances of 10 kQ in parallel with capacitances of 1 pF The specified performance numb
24. pply current for mixer Rss 1 82 kO 58 mA VPLO Supply current for LO limiting amplifier 35 mA Total Quiescent Current Vs 5V 85 98 113 mA Power Down Current Device disabled 500 Rev 01 Page 3 of 20 AD8342 AC PERFORMANCE Vs 5V TA 25 C LO power 0 dBm Zo 50 Q Rams 1 82 kO RF termination 100 Q IF terminated into 100 O via a 2 1 ratio balun unless otherwise noted Table 2 Parameter Conditions Min Typ Max Unit RF FREQUENCY RANGE 50 500 MHz LO FREQUENCY RANGE High side LO 60 850 MHz IF FREQUENCY RANGE 10 350 MHz CONVERSION GAIN far 460 MHz fio 550 MHz fir 90 MHz 3 2 dB far 238 MHz fio 286 MHz fir 48 MHz 3 7 dB SSB NOISE FIGURE far 460 MHz fio 550 MHz fir 90 MHz 12 5 dB far 238 MHz fio 286 MHz fir 48 MHz 12 2 dB INPUT THIRD ORDER INTERCEPT far 460 MHZ fer 461 MHz fio 550 MHz 22 2 dBm fir 90 MHz fie 89 MHz each RF tone 10 dBm far 238 MHz fae 239 MHz fio 286MHz 22 7 dBm fir 48MHZ fir 47MHz each RF tone 10 dBm INPUT SECOND ORDER INTERCEPT far 460 MHz far 410 MHz fio 550 MHz fir 90 MHz 50 dBm fir 140 MHz fari 238 MHZ far 188 MHz fio 286 MHz fi 48MHz 44 dBm fir 98 MHz INPUT 1 dB COMPRESSION POINT far 460 MHz fio 550 MHz fir 90 MHz 8 5 dBm far 238 MHz fio 286 MHz fir 48 MHz 8 3 dBm LO TO IF OUTPUT LEAKAGE LO power 0 dBm fio 286 MHz 27 d
25. pply decoupling resistors and filter R1 R2 R7 00 C2 C4 C5 C10 capacitors C4 C6 1000 pF C12 C13 C14 C9 C10 C13 2 100 pF C2 C5 C12 C9 0 1 uF R3 RA Options for single ended IF output circuit R3 Ra Open O R15 16 R15 R16200 R6 C11 Raus resistor that sets the bias current for the mixer core The capacitor R6 1 82 kO provides ac bypass for R6 C11 100 pF R8 Pull down for the PWDN pin R8 10 kO R9 Link to PWDN pin R9 00 C3 R5 C16 L1 RF input C3 provides dc block for RF input R5 provides a resistive input C3 1000 pF termination C16 and L1 are provided for reactive matching the input R5 1000 C14 Open L1200 C1 RF common ac coupling Provides dc block for RF input common C1 1000 pF connection C8 LO input ac coupling Provides dc block for the LO input C7 C8 1000 pF C7 LO common ac coupling Provides dc block for LO input common connection WI Power down The part is on when the PWDN is connected to ground via a 10 kO resistor The part is disabled when PWDN is connected to the positive supply Vs via W1 T1 R12 R11 Z3 IF output interface T1 converts a differential high impedance IF output to T1 TC2 1T 2 1 Mini Circuits Z4 Z1 Z2 R10 single ended When loaded with 50 O this balun presents a 100 O load to R12 2 Open the mixers collectors The center tap of the primary is used to supply the R10 R11 00 bias voltage Vs to the F output pins Z3 Z4 Open Z1 Z2 Open
26. re 37 LO Return Loss vs LO Frequency 100pF EXRB COMM IF OUT 500 VPOS 8 VPOS o LO FREQUENCY MHz 05352 058 Figure 35 LO to IF Feedthrough vs LO Frequency LO Power 0 dBm Figure 38 Characterization Circuit Used to Measure TPC Data Rev 0 Page 13 of 20 AD8342 CIRCUIT DESCRIPTION The AD8342 is an active mixer optimized for operation within the input frequency range of near dc to 500 MHz It has a dif ferential high impedance RF input that can be terminated or matched externally The RF input can be driven either single ended or differentially The LO input is a single ended 50 Q input The IF outputs are differential open collectors The mixer current can be adjusted by the value of an external resistor to optimize performance for gain compression and intermodula tion or for low power operation Figure 39 shows the basic blocks of the mixer including the LO buffer RF voltage to current converter bias cell and mixing core The RF voltage to RF current conversion is done via a resistively degenerated differential pair To drive this port single ended the RFCM pin should be ac grounded while the RFIN pin is ac coupled to the signal source The RF inputs can also be driven differentially The voltage to current converter then drives the emitters of a four transistor switching core This switching core is driven by an amplified version of the local oscillator signa
27. rformance over a specific band the AD8342 is a versatile general purpose device that can be used from arbitrarily low frequencies to sev eral GHz In general the following considerations help to en sure optimum performance e Minimize ac loading impedance of IF port bias network e Maximize power transfer to the desired ac load e For maximum conversion gain and the lowest noise per formance reactively match the input as described in the IF Port section For maximum input compression point and input intercept points resistively terminate the input as described in the IF Port section As an example Figure 51 shows the AD8342 as an up converting mixer for a WCDMA single carrier transmitter de sign For this application it was desirable to achieve 65 dBc adjacent channel power ratio ACPR at a 13 dBm output power level The ACPR is a measure of both distortion and noise carried into an adjacent frequency channel due to the finite intercept points and noise figure of an active device 100pF VPDC PWDN EXRB COMM 5 13 COMM 1nF ETC1 1 13 m 14 RFCM bans gt ond inp V 4990 1nF 2140MHz OUT pur 2 7 a 15 RFIN AJPF7 vb os Amat O olar zik 1oopF i P i VPLO 100pF i ST 100pF 1970MHz osc 05352 052 Figure 51 WCDMA Tx Up Conversion Application Circuit Because a WCDMA channel encompasses a bandwidth of almost 5 MHz it is necessary to keep the Q of the matching c
28. to 100 Q at the IF outputs There are several good reference books that explain general impedance matching procedures including e Chris Bowick RF Circuit Design Newnes Reprint Edition 1997 David M Pozar Microwave Engineering Wiley Text Books Second Edition 1997 Guillermo Gonzalez Microwave Transistor Amplifiers Analysis and Design Prentice Hall Second Edition 1996 150 REAL CHOKES 180 50MHz IDEAL CHOKES 05352 049 Figure 46 IF Port Loading Effects Due to Finite Q Pull Up Inductors Murata BLM18HD601SN 1D Chokes Rev 0 Page 16 of 20 Vs AD8342 05352 047 Figure 47 Biasing the IF Port Open Collector Outputs Using a Center Tapped Impedance Transformer Vs AD8342 COMM s IF OUT IFOP IMPEDANCE 21 1000 TRANSFORMING 2 NETVVORK IF OUT 05352 048 Figure 48 Biasing the IF Port Open Collector Outputs Using Pull Up Choke Inductors The AD8342 is optimized for driving a 100 O load Although the device is capable of driving a wide variety of loads to main tain optimum distortion and noise performance it is advised that the presented load at the IF outputs is close to 100 O The linear differential voltage conversion gain of the mixer can be modeled as Av x Rroap where _1 Ze qm deg R Rioap is the single ended load impedance n is the transistor transconductance and is equal to 1810 Rsus Reis 15 The external Rais resistor is use
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