Home

Hynix HMT351U6BFR8C-H9N0 memory module

1. S1 SO DQSO DQS4 DQSO 1 DQS4 DMO 1 DM4 i DM CSDQS DOS DM CS DQS DQS DM CS DQS DQS DM CS DQS DQS peo W IO0 voo DQ32 W4 IO 0 V0 0 DQI W4 01 DO vol D8 DQ33 W4 YO 1 D4 re D12 DQ2 W4j1 02 vo2 DQ34 W 1 0 2 i5 7 DQ3 W403 o3 DQ35 W r0 3 3 DQ4 W 4 104 DQ36 W V O 4 s DQ5 wW 1 05 105 DQ37 W 1 0 5 ae DQ6 WH1 06 106 ZQ DQ38 W4 1 0 6 s DQ7 W 0O7 Zo 107 pe DQ39 1 07 zo ZQ DQSI RE DQS5 i DQSI DQS5 DMI t DM5 1 DM CS DQS DQS DM CS DQS DQS DM CS DQS DQS DM CS DQS DQS DQ8 W41 00 1 00 DQ40 W 1 0 0 00 DQ9 W jUOI DI 101 D9 DQ41 M 10O 1 D5 hos D13 DQ10 W ro2 102 DQ42 VO 2 DQll W41 03 103 DQ43 W 10 3 VO 3 DQI2 W O 4 1 04 DQ44 W 1 0 4 ie DQI3 W I O 5 Los zQ DQ45 N a S an DQI4 W1 0 6 1 06 L Sar w m s Hed 20 DQI5 W4 1 07 ZQ 107 4 VV ZQ ya DQS2 L Dose m DMD DM6 1 1 DM CS DQS DQS DM CS DQS DQS DM CS DQS DQS UM CS DQS DAS DQI6 W41 00 voo DQ48 1 0 0 0 DQI7 W401 JO1 DQ49 W VO 1 D6 vol D14 D2 D10 DQ50 W 1 0 2 loa DQI8 W 41 02 VO 2 3 TS DQI9 WI03 103 DQ5
2. DQS0 ge c DQS4 DMO DM4 DM CS DQS DQS TE CS DQs DQS DQO w41 0 0 DQ1 w l O1 po Mamm ce D4 DQ2 W41 0 2 Ww DQ3 W41 0 3 DQ35 W41 0 3 DQ4 W l O 4 DQ36 W 41 0 4 DQ5 W I O 5 DQ37 W41 0 5 DQ6 W 41 0 6 ZQ DQ38 W 41 O 6 ZQ 3 DQ7 W41 07 m DQS5 DQ39 w41 0 7 Beet DQS5 DQS1 DMl _ DM5 L DM CS DQS DQS Baie vs Cs DQs DQS DQ8 W O 0 Ww DQ9 W4I 01 pi DQ41 w 1 O D5 DQ10 W41 0 2 DQ42 N 41 0 2 DQ11 W41 0 3 DQ43 N 41 0 3 Dis M i o 5 DQ4s W 1 0 5 DQ13 W41 0 5 DQ14 W4I 0 6 20 DQ46 41 0 6 2031 NN DQ15 W4I 0 7 DQS6 DQ47 v 1 0 7 Ones DQS6 DQS2 DM2 DM6 l E DM CS DQS DQS ads jan CS DQS DQS DQ16 W1 0 0 BAN DQ17 W41 01 p2 Eon Ww uo D6 DQ18 W41 0 2 E DQ19 W41 0 3 DQ51 W41 0 3 Eun lies DQ53 vio 5 1 05 se an Vo 6 ZQ IT DQ54 W41 0 6 ZQ NI DQ23 W41 07 d DQS7 DQ55 w 1 0 7 DQS3 z DOS7 DQS3 DM7 N DM3 A DQ24 woo ipd bQ56 0 0 eS DQ25 W4I 01 p3 DQ57 l O1 D7 DQ26 W41 0 2 DQ58 W41 0 2 DQ27 W41 0 3 DQ59 N 11 0 3 D929 vdio 5 pas i o 8 DQ29 W41 0 5 DQ30 W41 0 6 ZQ T4 Doe WH ie ZQ m DQS8 DQ31 W41 0 7
3. Side Detail A Detail B Ao M 2 50 FULL R 0 80 0 05 EC 4 mu 2 5040 20 8 5 cjo n q o f 1 00 gt 1 27 0 10 gt 0 3 1 0 1 50 0 10 5 00 Note 1 0 13 tolerance on all dimensions unless otherwise stated Units millimeters Rev 1 0 Oct 2010 59
4. Side Detail A Detail B Aon 4 2 50 FULL R 0 80 0 05 EC 4 mu 2 5040 20 8 5 eec m m o f 1 00 gt 1 27 0 10 gt 0 3 1 0 1 50 0 10 5 00 Note 1 0 13 tolerance on all dimensions unless otherwise stated Units millimeters Rev 1 0 Oct 2010 58 hyuix 512Mx72 HMT351U7BFR8C Front 2 10 0 15 Min 1 45 Ie SPD Max R0 70 shag ve l 4 x3 00 0 10 ames A 1730 DETAIL A DETAIL B 2x42 50 0 10 t 9 50 Lad Lo Q 5 1754 9 47 00 s 71 00 gt 128 95 pi gt 133 35 Back O U O
5. Symbol Type Polarity Function Seep DOE SSTL pos Data strobe for input and output data SA0 SA2 _ These signals are tied at the system planar to either Vss or VDDSPD to con figure the serial SPD EEPROM address range This bidirectional pin is used to transfer data into or out of the SPD SDA EEPROM An external resistor may be connected from the SDA bus line to VDDSPD to act as a pullup on the system board This signal is used to clock data into and out of the SPD EEPROM An SCL external resistor may be connected from the SCL bus time to VDDsPD to act as a pullup on the system board vaso pay IMEEM MER Pin Assignments Front Side left 1 60 Back Side right 121 180 Front Side left 61 120 Back Side right 181 240 Pin x64 x72 Pin x64 x72 Pin x64 x72 Pin x64 x72 3 Non ECC ECC Non ECC ECC Non ECC ECC Non ECC ECC 1 VREFDQ VREFDQ 121 Vss Vss 61 A2 A2 181 Al Al 2 Vss Vss 122 DQ4 DQ4 62 VDD VDD 182 VDD VDD 3 DQO DQO 123 DQ5 DQ5 63 CK1 CK1 183 VDD VDD 4 DQ1 DQl 124 Vss Vss 64 CK1 CK1 184 CKO CKO 5 Vss Vss 125 DMO DMO 65 VDD VDD 185 CKO CKO 6 DQSO DQSO 126 NC NC 66 VDD voo lf186 vob VDD 7 DQSO DQSO 127 Vss Vss 67 VREFCA VREFCA 187 NC EVENT 8 Vss Vss 128 DQ6 DQ6 68 NC NC 188 A0 AO 9 DQ2 DQ2 129 DQ7 DQ7 69 VDD VDD 189 VDD VDD 10 DQ3 DQ3 130 Vss Vss 70 A10 A10 190 BA BA1 11 Vss Vss 131 DQ12 DQ12 71 BAO2 BAO 191 VDD VDD 12 DQ8 DQ8 132 DQ13 DQ1
6. Pin Symbol Min Max Unit CKO CKO Cox TBD TBD pF CKE ODT CS CcrRL TBD TBD pF Address RAS CAS WE Ci TBD TBD pF DQ DM DOGS DAS Cio TBD TBD pF 2GB HMT325U6BFR8C Pin Symbol Min Max Unit CKO CKO Cox TBD TBD pF CKE ODT CS CcrRL TBD TBD pF Address RAS CAS WE Ci TBD TBD pF DQ DM DAS DOS Cio TBD TBD pF 2GB HMT325U7BFR8C Pin Symbol Min Max Unit CKO CKO Cox TBD TBD pF CKE ODT CS CcerRL TBD TBD pF Address RAS CAS WE Ci TBD TBD pF DQ DM DOGS DAS Cio TBD TBD pF 4GB HMT351U6BFR8C Pin Symbol Min Max Unit CKO CKO Cox TBD TBD pF CKE ODT CS CcrRL TBD TBD pF Address RAS CAS WE Ci TBD TBD pF DQ DM DAS DAS Cio TBD TBD pF 4GB HMT351U7BFR8C Pin Symbol Min Max Unit CKO CKO Cek TBD TBD pF CKE ODT CS CcrRL TBD TBD pF Address RAS CAS WE C TBD TBD pF DQ DM DQS DAS Cio TBD TBD pF Note 1 Pins not under test are tied to GND 2 These value are guaranteed by design and tested on a sample basis only Rev 1 0 Oct 2010 hynix IDD and I DDQ Specification Parameters and Test Conditions IDD and I DDQ Measurement Conditions In this chapter IDD and IDDQ measurement conditions such as test load and patterns are defined Figure below Measurement Setup and Test Load for IDD and IDDQ optional Measurements shows the setup and test load for IDD and IDDQ measurements e DD currents such as IDDO IDD1 IDD2N IDD2NT IDD2PO IDD2P1 IDD2Q IDD3N IDD3P IDD4R
7. Temperature to Digital Conversion Performance Parameter Condition Min Typ Max Unit Active Range E Temperature Sensor Accuracy Grade B Monitor Range P 40 C lt T4 lt 125 C EOE AO DS 20 C lt TA lt 125 C 2 0 3 0 C Resolution 0 25 C Rev 1 0 Oct 2010 10 hynix Functional Block Diagram 1GB 128Mx64 Module 1Rank of x16 SO DOS linge DOSe a age DQS0 Pw libQs po DQS4 woas p DMO w LDM DM4 Mw Lb DQO w4 1 00 DQ32 W 1 0 0 DQ1 w 1 01 DQ33 w 1 0 1 DQ2 Ww 1 0 2 DQ34 WY 1 0 2 DQ3 W 1 03 DQ35 W 1 0 3 DQ4 W41 0 4 DQ36 N 1 O 4 DQ5 W4 1 05 DQ37 W 1 05 DQ6 W4 1 0 6 DQ38 N 1 O 6 DQ7 W4 1 07 DQ39 WY 1 0 7 DQS1 UDQS DQS5 wv UDQS DQS1 w 4 pas DQS5 w UDQS DMI UM DM5 w UDM DQ8 wW 1 08 DQ40 W 1 0 8 DQ9 w I 0 9 DQ41 w 1 0 9 DQ10 W 1 0 10 DQ42 w 1 0 10 DQ11 W 1 0 11 DQ43 W 1 0 11 DQ12 W 1 0 12 DQ44 W 1 0 12 DQ13 W 1 0 13 DQ45 W 1 0 13 DQl4 W 1 0 14 DQ46 W 1 0 14 DQ15 W4 1 0 15 zd iL DQ47 W 1 0 15 ZQ Ac CS Doce cs DQS2 Wwn iOS DQS6 wA bos DQ52
8. Pin x64 x72 Pin x64 x72 Pin x64 x72 Pin x64 x72 Non ECC ECC Non ECC ECC Non ECC ECC Non ECC ECC 48 NC NC 168 Reset Reset 108 DQ56 DQ56 228 DQ61 DQ61 KEY KEY 109 DQ57 DQ57 229 Vss Vss 49 NC NC 169 CKE1 NC CKE1 NC 110 Vss Vss 230 DM7 DM7 50 CKEO CKEO 170 VoD VDD 111 DQS7 DQS7 231 NC NC 51 VDD VDD 171 NC NC 112 DQS7 DQS7 232 Vss Vss 52 BA2 BA2 172 NC NC 113 Vss Vss 233 DQ62 DQ62 53 NC NC 173 VDD VDD 114 DQ58 DQ58 234 DQ63 DQ63 54 VDD VDD 174 A12 A12 115 DQ59 DQ59 235 Vss Vss 55 All All 175 A9 A9 116 Vss Vss 236 VDDSPD VDDSPD 56 AT A7 176 VDD VDD 117 SAO SAO 237 SA1 SA1 57 VDD Voo 177 A8 A8 118 SCL SCL 238 SDA SDA 58 A5 A52 178 A6 A6 119 SA2 SA2 239 Vss Vss 59 A4 A4 179 VDD VDD 120 VIT VIT 240 VIT VTT 60 VoD voo 180 A3 A3 NC No Connect RFU Reserved Future Use 1 NC pins should not be connected to anything on the DIMM including bussing within the NC group 2 Address pins A3 A8 and BAO and BAI can be mirrored or not mirrored Rev 1 0 Oct 2010 hynix On DI MM Thermal Sensor The DDR3 SDRAM DIMM temperature is monitored by integrated thermal sensor The integrated thermal sensor comply with J EDEC TSE2002av Serial Presence Detect with Temperature Sensor Connection of Thermal Sensor EVENT SCL SDA SAO SPD with sj Integrated c TS
9. DQS8 FN DM 8 DM C Dos DOS T SPD TS integrated Notes CB0 w 00 T CBl W4I 01l pg EVENT gt spa 1 DQ to I O wiring is shown as recom CB2 W 1l 02 EVENT Ao Al 42 mended but may be changed nud Pec 2 DQ DQS DQS ODT DM CKE S rela CB5 W l O 5 m SA0 SAl SA2 ae must be maintained as cB6 W l O 6 md s l CB W l O 7 3 DQ CB DM DQS DQS resistors Refer BAO0 BA2 BA0 BA2 SDRAMs D0 D8 to associated topology diagram A0 A15 A0 A15 SDRAMs DO D8 Vppspp SPD 4 Refer to the appropriate clock wiring RAS RAS SDRAMs D0 D8 Vbb VbbQ topology under the DIMM wiring CAS CAS SDRAMs D0 D8 tt DO D8 details section of this document CKEO CKE SDRAMs D0 D8 VREFDQ D0 D8 5 For each DRAM a unique ZQ resistor WE WE SDRAMs D0 D8 is connected to ground The ZQ resis ODTO ODT SDRAMs D0 D8 Vss e t 4 D0 D8 tor is 2400hm 1 cko gt CK SDRAMs D0 D8 T 6 One SPD exists per module CKO TK SDRAMs D0 D8 VREFCA D0 D8 RESET RESET SDRAMs D0 D8 Rev 1 0 Oct 2010 13 hyuix 4GB 512Mx64 Module 2Rank of x8
10. ODT Signal stable at 0 Pattern Details see Table 7 ppaw Operating Burst Write Current CKE High External clock On tCK CL see Table 1 BL 89 AL 0 CS High between WR Command Address Bank Address Inputs partially toggling according to Table 8 Data IO seamless read data burst with different data between one burst and the next one according to Table 8 DM stable at 0 Bank Activity all banks open WR commands cycling through banks 0 0 1 1 2 2 see Table 8 Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at HIGH Pattern Details see Table 8 pps5B Burst Refresh Current CKE High External clock On tCK CL nRFC see Table 1 BL 89 AL 0 CS High between REF Command Address Bank Address Inputs partially toggling according to Table 9 Data IO MID LEVEL DM stable at 0 Bank Activity REF command every nREF see Table 9 Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Table 9 pve Self Refresh Current Normal Temperature Range Tease 0 85 C Auto Self Refresh ASR Disabled Self Refresh Temperature Range SRT Normal CKE Low External clock Off CK and CK LOW CL see Table 1 BL 89 AL 0 CS Command Address Bank Address Inputs Data lO MID LEVEL DM stable at 0 Bank Activity Self Refresh operation Output Buffer and RTT Enabled in Mode Registers ODT Signal MID LEVEL IppeE
11. 1 975 V V 1 Vin Vout Noltage on any pin relative to Vss 0 4 V 1 975 V V 1 TsrG Storage Temperature 55 to 100 o 1 2 Notes 1 Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rat ing conditions for extended periods may affect reliability 2 Storage Temperature is the case surface temperature on the center top side of the DRAM For the measurement conditions please refer to J ESD51 2 standard 3 VDD and VDDQ must be within 300mV of each other at all times and VREF must not be greater than 0 6XVDDQ When VDD and VDDQ are less than 500mV VREF may be equal to or less than 300mV DRAM Component Operating Temperature Range Temperature Range Symbol Parameter Rating Units Notes Normal Operating Temperature Range 0 to 85 9c 1 2 TOPER Extended Temperature Range 85 to 95 C 13 Notes 1 Operating Temperature TOPER is the case surface temperature on the center top side of the DRAM For mea surement conditions please refer to the JEDEC document J ESD51 2 2 The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported Dur ing operation the DRAM case temperature must be maintaine
12. 128 95 pi gt 133 35 Back O O Side Detail A Detail B 3 18 t 2 50 FULL R 0 80 0 05 lt gt Y 4 a8 2 500020 amp S oc n q o f 1 00 gt 1 27 0 10 gt 0 3 1 0 1 50 0 10 5 00 Note 1 0 13 tolerance on all dimensions unless otherwise stated Rev 1 0 Oct 2010 Units millimeters 56 hynix 256Mx72 HMT325U7BFR8C Front 2 10 0 15 Min 1 45 SPD Max R0 70 she ve l 43 0050 10 gt A 1730 DETAIL A DETAIL B 2x 62 50 0 10 t 9 50 naO Lo Q 5 1754 9 47 00 s 71
13. NW LDQS pi DQ56 w DaS p3 DM2 w LDM DM6 JM LDM DQ16 W 1 0 0 DQ48 W 1 0 0 DQ17 w 1 0 1 DQ49 W 1 0 1 DQ18 W 1 0 2 DQ50 W 1 0 2 DQ19 W 1 0 3 DQ51 W 1 0 3 DQ20 W 1 0 4 DQ52 W 1 0 4 DQ21 W 1 0 5 DQ53 W 1 05 DQ22 W 1 0 6 DQ54 W 1 0 6 DQ23 W 1 07 DQ55 WY 1 07 DQS3 7w UDQS DQS7 7w UDQS DQS3 w 4 UDQS DQS7 w 4 UDQS DM3 w UDM DM7 UDM DQ24 W 1 0 8 DQ56 W 1 0 8 DQ25 W 1 0 9 DQ57 w 1 0 9 DQ26 W4 1 0 10 DQ58 W 1 0 10 DQ27 W 1 0 11 DQ59 W 1 0 11 DQ28 w 1 0 12 DQ60 W 1 0 12 DQ29 W 1 0 13 DQ61 W 1 0 13 DQ30 W 1 0 14 ZQ DQ62 W 1 0 14 ZQ DQ31 W 1 0 15 DQ63 WY 1 0 15 Notes Serial PD 1 DQ to I O wiring is shown as recom SCL gt mended but may be changed we lt gt SDA 2 a E BA0 BA2 BA0 BA2 SDRAMs D0 D3 ships must be maintained as shown mu AD AL AR 3 DQ DM DQS DQS resistors Refer to asso A0 A14 J A0 A14 SDRAMs D0 D3 ciated topology diagram RAS p RAS SDRAMs D0 D3 uc 4 Refer to the appropriate clock wiring _ 2 topology under the DIMM wiring details CAS CAS SDRAMs D0 D3 psi Eun section of this document E 5 The pair CK1 and CK1 is terminated in or E SDRAMS D02D3 VDD VDDQ D0 D3 75ohm but is not used on the module WE WE SDRAMs D0 D3 1 6 A15
14. Rev 1 0 Oct 2010 49 hyuix Table 9 IDD5B Measurement Loop Pattern g g z slalealiclioia Pigg ib Ewe RE BSE Es FF om 0 0 REF 0 0 0 0 0 0 1 12 D D 1 0 0 0 00 0 3 4 BO rt 4 0 0 00 0 5 8 repeat cycles 1 4 but BA 2 0 1 2 5 9 12 repeat cycles 1 4 but BA 2 0 2 2 D Y 13 16 repeat cycles 1 4 but BA 2 0 3 f k 17 20 repeat cycles 1 4 but BA 2 0 4 21 24 repeat cycles 1 4 but BA 2 0 5 25 28 repeat cycles 1 4 but BA 2 0 6 29 32 repeat cycles 1 4 but BA 2 0 7 2 33 nRFC 1 repeat Sub Loop 1 until nRFC 1 Truncate if necessary a DM must be driven LOW all the time DQS DQS are MID LEVEL b DQ signals are MID LEVEL Rev 1 0 Oct 2010 50 hynix Table 10 IDD7 Measurement Loop Pattern ATTENTI ON Sub Loops 10 19 have inverse A 6 3 Pattern and Data Pattern than Sub Loops 0 9 Q L o 8 og S u e eld s Raie sii 35 E OBIS IE 8 SS sje S S no 0 0 ACT 0 0 1 1 0 0 00 0 0 0 0 1 RDA 0 1 0 1 0 0 00 1 0 0 0 00000000 2 D 1 0 0 0 0 0 00 0 0 0 0 a r
15. IDDAW IDD5B IDD6 IDD6ET IDD6TC and IDD7 are measured as time averaged currents with all VDD balls of the DDR3 SDRAM under test tied together Any IDDQ current is not included in IDD cur rents DDQ currents such as IDDQ2NT and IDDQ4R are measured as time averaged currents with all VDDQ balls of the DDR3 SDRAM under test tied together Any IDD current is not included in IDDQ cur rents Attention IDDQ values cannot be directly used to calculate 1O power of the DDR3 SDRAM They can be used to support correlation of simulated 1O power to actual IO power as outlined in the Figure below Correlation from simulated Channel IO Power to actual Channel IO Power supported by IDDQ Measurement In DRAM module application IDDQ cannot be measured separately since VDD and VDDQ are using on merged power layer in Module PCB For IDD and IDDQ measurements the following definitions apply 0 and LOW is defined as VIN lt Vit AC may e l and HIGH is defined as VIN gt Vinac may MID LEVEL is defined as inputs are VREF VDD 2 Timing used for IDD and IDDQ Measurement Loop Patterns are provided in Table 1 Basic IDD and IDDQ Measurement Conditions are described in Table 2 Detailed IDD and IDDQ Measurement Loop Patterns are described in Table 3 through Table 10 e IDD Measurements are done after properly initializing the DDR3 SDRAM This includes but is not lim ited to setting RON RZQ 7 34 Ohm in MR1 Qoff 0g Outp
16. O O Side Detail A Detail B 3 18 2 50 FULL R 0 80 0 05 D a FN s mu 2 50 0 20 g S cl m m o 1 00 gt 1 27 0 10 gt I 03 10 1 50 0 10 5 00 Note 1 0 13 tolerance on all dimensions unless otherwise stated Rev 1 0 Oct 2010 Units millimeters 55 hynix 256Mx64 HMT325U6BFR8C Front 2 10 0 15 Min 1 45 gt iz Max R0 70 y SPD ap 00 4x3 000 10 i v A 1730 DETAIL A DETAIL B 2 x 62 50 0 10 t 9 50 nate N Q 5 1754 9 47 00 s 71 00 gt
17. lt gt SDA CBO W 1 0 0 1 0 0 EVENT Ao Al 2 Vss _ _4 F po p17 CB1 wW 41 01 1 01 D17 CB2 W l O2 e 1 0 2 en d n VREFCA D0 D17 CB3 W 1l 03 1 0 3 Notes CB4 W l 04 1 0 4 1 DQ to I O wiring is shown as recom CB5 W l 05 1 05 mended but may be changed cB6 W 41 06 1 0 6 2 DQ DQS DQS ODT DM CKE S relation CB7 wW4I 07 zo 1 07 zQ ships must be maintained as shown 3 pee ices ete resistors Refer to z gt BAO i associated topology diagram ps itu MEC ODTO ODT SDRAMs D0 D8 4 Refer to Section 3 1 of this document for s DU ODT1 gt ODT SDRAMs D9 D17 details on address mirroring CKEO gt CKE SDRAMs D0 D8 CK0 gt CK SDRAMs D0 D8 5 For each DRAM a unique ZQ resistor is CKEl gt CKE SDRAMs D9 D17 CKO gt CK SDRAMs D0 D8 connected to ground The ZQ resistor is RAS ____ RAS SDRAMs D0 D17 CKl CK SDRAMs D9 D17 2400hm 1 CAS CAS SDRAMs DO D17 ca gt CK SDRAMs D9 D17 6 One SPD exists per module WE WE SDRAMs D0 D17 RESET RESET SDRAMs DO D17 Rev 1 0 Oct 2010 15 hyuix Absolute Maximum Ratings Absolute Maximum DC Ratings Absolute Maximum DC Ratings Symbol Parameter Rating Units Notes VDD VWoltage on VDD pin relative to Vss 0 4 V 1 975 V V 1 VDDQ Voltage on VDDQ pin relative to Vss 0 4V
18. 0 100 VDD Vref 0 100 VDD V 1 VIL CA DC100 DC input logic low VSS Vref 0 100 VSS Vref 0 100 V 1 VIH CA AC175 AC input logic high Vref 0 175 Note2 V 1 2 VIL CA AC175 AC input logic low Note2 Vref 0 175 7 V 1 2 VIH CA AC150 AC Input logic high Vref 0 150 Note2 Vref 0 150 Note2 V 1 2 VIL CA AC150 AC input logic low Note2 Vref 0 150 Note2 Vref 0 150 V 1 2 Reference Voltage for DQ T E Vnetpa pc DM inputs 0 49 VDD 0 51 VDD 0 49 VDD 0 51 VDD V 3 4 Notes 1 Vref 2 VrefDQ DC 2 Refer to Overshoot and Undershoot Specifications on page 30 3 The ac peak noise on Vref may not allow Vger to deviate from Vgerpo pc by more than 1 VDD for reference approx 15 mV 4 For reference approx VDD 2 15 mV Rev 1 0 Oct 2010 18 hyuix Vref Tolerances The dc tolerance limits and ac noise limits for the reference voltages ypefca and Vpefpg are illustrated in figure below It shows a valid reference voltage Vge t as a function of time Vger stands for Vperca and Vnetpo likewise Vref DC is the linear average of Vpor t over a very long period of time e g 1 sec This average has to meet the min max requirements in the table Differential Input Slew Rate Definition on page 25 Further more Vref t may temporarily deviate from Vger pc by no more than 1 VDD voltage VDD Vne t Ve ac noise Ref V Vnet DC Ref DC max VDD 2 VRef DC min VSS Illustration
19. 00 gt 128 95 Pi gt 133 35 Back O U O Side Detail A Detail B 3 18 2 50 FULL R 0 80 0 05 gt Y 4 nu 2 50 0 20 8 S oec n q o f 1 00 gt 1 27 0 10 gt 0 3 1 0 1 50 0 10 5 00 Note 1 0 13 tolerance on all dimensions unless otherwise stated Rev 1 0 Oct 2010 Units millimeters 57 hynix 512Mx64 HMT351U6BFR8C Front 2 10 0 15 Min 1 45 gt Max R0 70 akan y SPD x 43 0050 10 gt A 1730 DETAIL A DETAIL B 2x42 50 0 10 t 9 50 Lad Lo Q 5 1754 9 47 00 s 71 00 gt 128 95 pi gt 133 35 Back O U O
20. 1 nRC nRAS PRE 0 0 1 0 0 0 00 0 0 F 0 m repeat pattern nRC 1 4 until 2 nRC 1 truncate if necessary 1 2 nRC repeat Sub Loop 0 use BA 2 0 1 instead 2 4 nRC repeat Sub Loop 0 use BA 2 0 2 instead 3 6 nRC repeat Sub Loop 0 use BA 2 0 3 instead 4 8 nRC repeat Sub Loop 0 use BA 2 0 4 instead 5 10 nRC repeat Sub Loop 0 use BA 2 0 5 instead 6 12 nRC repeat Sub Loop 0 use BA 2 0 6 instead 7 14 nRC repeat Sub Loop 0 use BA 2 0 7 instead a DM must be driven LOW all the time DQS DQS are used according to RD Commands otherwise MID LEVEL b Burst Sequence driven on each DQ signal by Read Command Outside burst operation DQ signals are MID LEVEL Rev 1 0 Oct 2010 47 hynix Table 5 IDD2N and I DD3N Measurement Loop Pattern s 2 o 9 z anela a ale Rigid 2 Ele Bis e bls 2 2 58 8o i a z 8 aix d d 4 0 0 D 1 0 0 0 0 0 0 0 0 0 0 1 D 1 0 0 0 0 0 0 0 0 0 0 2 D 1111 1 lolojololo i iFjof 3 D Pak hPa eee olo Filol 2 5 1 4 7 repeat Sub Loop 0 use BA 2 0 1 instead D Y 2 8 11 repeat Sub Loop 0 use BA 2 0 2 instead f k 3 12 15 repeat Sub Loop 0 use BA 2 0 3 instead 4 16 19 repeat Sub Loop 0 use BA 2 0 4 instead 5 20 23 repeat Sub Loop 0 use BA 2 0 5 instead 6 24 17 repeat
21. BA 2 0 1 8 2 1623 repeat Sub Loop 0 but BA 2 0 2 3 24 31 repeat Sub Loop 0 but BA 2 0 3 4 32 39 repeat Sub Loop 0 but BA 2 0 4 5 40 47 repeat Sub Loop 0 but BA 2 0 5 6 48 55 repeat Sub Loop 0 but BA 2 0 6 7 56 63 repeat Sub Loop 0 but BA 2 0 7 a DM must be driven LOW all the time DQS DQS are used according to RD Commands otherwise MID LEVEL b Burst Sequence driven on each DQ signal by Read Command Outside burst operation DQ signals are MID LEVEL Table 8 IDDAW Measurement Loop Pattern Q ge x o o c e c Big 3 ge Pig BIER 0 0 WR 0 1 0 0 1 0 00 0 0 0 0 00000000 1 D 1 0 0 0 1 0 00 0 0 0 0 2 3 DD 1 1 1 1 1 0 00 0 0 0 0 4 WR 0 1 0 0 1 0 00 0 0 F 0 00110011 e 5 D 1 0 0 0 1 0 00 0 0 F 0 2 2 6 7 D D 1 1 1 1 1 0 00 0 0 F 0 8 9 1 8 15 repeat Sub Loop 0 but BA 2 0 1 g E 2 16 23 repeat Sub Loop 0 but BA 2 0 2 2 3 24 31 repeat Sub Loop 0 but BA 2 0 2 3 4 32 39 repeat Sub Loop 0 but BA 2 0 2 4 5 40 47 repeat Sub Loop 0 but BA 2 0 5 6 48 55 repeat Sub Loop 0 but BA 2 0 6 7 56 63 repeat Sub Loop 0 but BA 2 0 7 a DM must be driven LOW all the time DQS DQS are used according to WR Commands otherwise MID LEVEL b Burst Sequence driven on each DQ signal by Write Command Outside burst operation DQ signals are MID LEVEL
22. DQ52 El DQ21 1 0 5 DQ53 w no E 20 DQ22 W 1 0 6 DQ54 WM4I rT nn DQ23 W1 0 7 ZQ DQS7 DQ55 w O 7 m DQS3 1 DOS7 DQS3 B NMN DM3 DM CS DQS DQS DM CS DQS DQS DQ24 W4 r0 0 SUE DQ56 1 O 0 DQ25 A 101 D3 DQ57 W1 0 D7 DQ26 WW 1 0 2 DQ58 W1 0 2 DQ27 W41 0 3 DQ59 v 1 0 3 DQ28 W l O 4 DQ60 V 11 O 4 DQ29 WI 0 5 DQ61 W41 0 5 m DQ30 WI 0 6 ZQ DQ62 W1 0 6 ine DQ31 W 1U O 7 DQ63 W 1 0 7 Serial PD Not otes SCL gt sp 1 DQ to 1 O wiring is shown as recom WP gt mended but may be changed zs A0 GALA 2 DQ DQS DQS ODT DM CKE S relation BAO BA2 BA0 BA2 SDRAMs D0 D7 ae Jm ER ships must be maintained as shown A0 A15 Jp A0 A15 SDRAMs D0 D7 3 m ds d ies a to RAS gt RAS SURAMSUS D 4 Refer to the appropriate clock wiring CAS p CAS SDRAMs D0 D7 topology under the DIMM wiring details VDDSPD SPD section of this document y CKE SDRAMs D0 D7 t osa VpbD VbpDQ po p Refer to Section 3 1 of this document for WE P WESSDRAMSDIHD ai cmm details on address mirroring ODTO ODT SDRAMsDO D7 VREFDQ f D0 D7 6 For each DRAM a unique ZQ resistor is CKO CK SDRAMs D0 D7 Vss i D0 D7 connected to ground The ZQ resistor is ke us E VREFCA DO D7 7 AR er module RESET RESET SDRAMs D0 D7 i p Rev 1 0 Oct 2010 12 hynix 2GB 256Mx72 Module 1Rank of x8
23. addr cntl inputs are sampled on the crossing of positive edge of CK and negative edge of CK Output read data is reference to the crossing of CK and CK Both directions of crossing CKEO CKE1 SSTL Active High Activates the SDRAM CK signal when high and deactivates the CK signal when low By deactivating the clocks CKE low initiates the Power Down mode or the Self Refresh mode S0 S1 SSTL Active Low Enables the associated SDRAM command decoder when low and disables the command decoder when high When the command decoder is dis abled new commands are ignored but previous operations continue This signal provides for external rank selection on systems with multiple ranks RAS CAS WE SSTL Active Low RAS CAS and WE ALONG wirH S define the command being entered ODT0 ODT1 SSTL Active High When high termination resistance is enabled for all DQ DQS DQS and DM pins assuming this function is enabled in the Mode Register 1 MR1 VREFDQ Supply Reference voltage for SSTL15 1 0 inputs VREFCA Supply Reference voltage for SSTL 15 command address inputs VDDQ Supply Power supply for the DDR3 SDRAM output buffers to provide improved noise immunity For all current DDR3 unbuffered DIMM designs VDDQ shares the same power plane as VDD pins BAO BA2 SSTL Selects which SDRAM bank of eight is activated AO A15 SSTL During a Bank Activate command c
24. of Vperpc tolerance and Vref ac noise limits The voltage levels for setup and hold time measurements Vinc Vinoo ViL ac and Vii pc are depen dent on Vgr Vref Shall be understood as Vgerpc as defined in figure above This clarifies that dc variations of Vper affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to which setup and hold is measured System timing and voltage budgets need to account for Vger pc deviations from the optimum position within the data eye of the input signals This also clarifies that the DRAM setup hold specification and derating values need to include time and voltage associated with Vporac noise Timing and voltage effects due to ac noise on Vg up to the speci fied limit 196 of VDD are included in DRAM timings and their associated deratings Rev 1 0 Oct 2010 19 hynix AC and DC Logic I nput Levels for Differential Signals Differential signal definition VIL DIFFAC MIN VILDIFFMIN half cycle VIL DIFF MAX Differential Input Voltage i e DQS DQS CK CK VIL DIFF AC MAX l Definition of differential ac swing and time above ac level tpvac Rev 1 0 Oct 2010 20 hynix Differential swing requirements for clock CK CK and strobe DQS DQS Differential AC and DC I nput Levels DDR3 800 1066 1333 amp 1600 Symbol Parameter Unit Notes M
25. 0 7 D 1 0 0 0 0 7 00 0 0 0 0 pe aR Assert and repeat above D Command until 4 nFAW 1 if necessary a DM must be driven LOW all the time DQS DQS are used according to RD Commands otherwise MID LEVEL b Burst Sequence driven on each DQ signal by Read Command Outside burst operation DQ signals are MID LEVEL Rev 1 0 Oct 2010 51 hyuix I DD Specifications Tcase 0 to 95 C Module IDD values in the datasheet are only a calculation based on the component I DD spec The actual measurements may vary according to DQ loading cap 1GB 128M x 64 U DI MM HMT312U6BFR6C Symbol DDR3 1066 DDR3 1333 DDR3 1600 Unit note IDDO 240 260 260 mA IDD1 280 300 300 mA IDD2N 100 120 120 mA IDD2NT 140 160 180 mA IDD2PO 48 48 48 mA IDD2P1 60 60 60 mA IDD2Q 100 120 120 mA IDD3N 120 140 160 mA IDD3P 60 60 60 mA IDDAR 420 520 560 mA IDDAW 420 520 600 mA IDD5B 660 680 680 mA IDD6 48 48 48 mA IDD6ET 60 60 60 mA IDD6TC 60 60 60 mA IDD7 520 680 720 mA 2GB 256M x 64 U DI MM HMT325U6BFR8C Symbol DDR3 1066 DDR3 1333 DDR3 1600 Unit note IDDO 360 400 440 mA IDD1 440 480 520 mA IDD2N 200 240 240 mA IDD2NT 256 280 320 mA IDD2PO 96 96 96 mA IDD2P1 120 120 120 mA IDD2Q 200 240 240 mA IDD3N 240 280 320 mA IDD3P 120 120 120 mA IDDAR 640 760 840 mA IDDAW 640 760 880 mA IDD5B 1200 1240 128
26. 0 mA IDD6 96 96 96 mA IDD6ET 120 120 120 mA IDD6TC 120 120 120 mA IDD7 880 1080 1160 mA Rev 1 0 Oct 2010 52 hynix 2GB 256M x 72 U DI MM HMT325U7BFR8C Symbol DDR3 1066 DDR3 1333 DDR3 1600 Unit note IDDO 405 450 495 mA IDD1 495 540 585 mA IDD2N 225 270 270 mA IDD2NT 288 315 360 mA IDD2PO 108 108 108 mA IDD2P1 135 135 135 mA IDD2Q 225 270 270 mA IDD3N 270 315 360 mA IDD3P 135 135 135 mA IDDAR 720 855 945 mA IDDAW 720 855 990 mA IDD5B 1350 1395 1440 mA IDD6 108 108 108 mA IDD6ET 135 135 135 mA IDD6TC 135 135 135 mA IDD7 990 1215 1305 mA 4GB 512M x 64 U DI MM HMT351U6BFR8C Symbol DDR3 1066 DDR3 1333 DDR3 1600 Unit note IDDO 560 640 760 mA IDD1 640 720 840 mA IDD2N 400 480 480 mA IDD2NT 512 560 640 mA IDD2PO 192 192 192 mA IDD2P1 240 240 240 mA IDD2Q 400 480 480 mA IDD3N 480 560 640 mA IDD3P 240 240 240 mA IDDAR 840 1000 1160 mA IDDAW 840 1000 1200 mA IDD5B 1400 1480 1600 mA IDD6 192 192 192 mA IDDET 240 240 240 mA IDD6TC 240 240 240 mA IDD7 1080 1320 1480 mA Rev 1 0 Oct 2010 hyuix 4GB 512M x 72 U DIMM HMT351U7BFR8C Symbol DDR3 1066 DDR3 1333 DDR3 1600 Unit note IDDO 630 720 855 mA IDD1 720 810 945 mA IDD2N 450 540 540 mA ID
27. 1 W4 1 0 3 d DQ20 AL O4 vo4 DQ52 W 1 0 4 a DQ21 W4 1 05 VO 5 DQ53 W 41 0 5 E DQ22 W41 0 6 106 Za DQ54 W4 1 0 6 UO 6 ane DQ23 W1 07 zo o7 DQ55 W VO 7 zo L4 1o7 2071 DQS3 r1 DOS7 L D 1 DOS7 f 3 DM7 i DM CSDQS DQS DM CS DQS DQS DM CS DQS DQS DM CS DQS DQS DQ24 W 1 00 Loo DQ56 M 1 0 0 100 DQ25 W1 0 1 D3 JO 1 Dii DQ57 M 10 1 D7 vo D15 DQ26 W4 rO 2 102 DQ58 W 10 2 102 DQ27 WH 1 03 103 DQ59 W 1 0 3 103 DQ28 W VO 4 104 DQ60 W 1 0 4 yo4 DQ29 W41 0 5 105 DQ61 WH 1 0 5 yos DQ30 W I O 6 1 06 DQ62 W 4 1 0 6 106 DQ3I vH ro7 20 UO 7 zor DQ63 vH 107 T UO 7 z Serial PD d Notes BA0 BA2 BA0 BA2 SDRAMs D0 D15 TE 3 SCL 1 DQ to 1 O wiring is shown as recom A0 A15 A0 A15 SDRAMs D0 D15 e lt gt SDA mended but may be changed v s but n 1 l CEEI CREDE D8 D15 40 A oA DQ DQS DQS ODT DM CKE 5 relation CRED CRE SDRAMs DO DT sho as L ships must be maintained as shown RAS RAS SDRAMSDU DIS DQ DM DQS DQS resistors Refer to CAS gt CAS SDRAMs D0 D15 VDDSPD SPD associated topology diagram WE gt WESDRAMsDO DIS vj y Q DDIS Refer to Section 3 1 of this document for ODTO ODT SDRAMs D0 D7 details on address mirroring ODT1 ODT SDRAMs D8 D15 VREFDQ t D0 DI5 For each DRAM a unique ZQ resistor is CKO CK SDRAMs D0 D7 Vss po_pis connected to ground The ZQ resistor is
28. 2KB page size 6 5 6 nCK RFC 512Mb 48 60 72 nCK lgrc 1 Gb 59 74 88 nCK REC 2 Gb 86 107 128 nCK Ngec 4 Gb 160 200 240 nCK Ngre 8 Gb 187 234 280 nCK Table 2 Basic I DD and I DDQ Measurement Conditions Symbol Description ppo Operating One Bank Active Precharge Current CKE High External clock On tCK nRC nRAS CL see Table 1 BL 82 AL 0 CS High between ACT and PRE Command Address Bank Address Inputs partially toggling according to Table 3 Data IO MID LEVEL DM stable at 0 Bank Activity Cycling with one bank active at a time 0 0 1 1 2 2 see Table 3 Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Table 3 Ippi Operating One Bank Active Precharge Current CKE High External clock On tCK nRC nRAS nRCD CL see Table 1 BL 82 AL 0 CS High between ACT RD and PRE Command Address Bank Address Inputs Data IO partially toggling according to Table 4 DM stable at 0 Bank Activity Cycling with on bank active at a time 0 0 1 1 2 2 see Table 4 Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Table 4 Rev 1 0 Oct 2010 42 hynix Symbol Description Ipp2N Precharge Standby Current CKE High External clock On tCK CL see Table 1 BL 89 AL 0 CS stable at 1 Command Address Bank Address Inputs partially toggling accordi
29. 3 72 VDD voo 192 RAS RAS 13 DQ9 DQ9 133 Vss Vss 73 WE WE 193 SO SO 14 Vss Vss 134 DM1 DM1 74 CAS CAS 194 VoD VDD 15 DQS1 DQS1 135 NC NC 75 VDD voo 195 ODTO ODTO 16 DQS1 DQS1 1 136 Vss Vss 76 S1 S1 196 A13 A13 NC No Connect RFU Reserved Future Use 1 NC pins should not be connected to anything on the DIMM including bussing within the NC group 2 Address pins A3 A8 and BAO and BAI can be mirrored or not mirrored Rev 1 0 Oct 2010 hynix Front Side left 1 60 Back Side right 121 180 Front Side left 61 120 Back Side right 181 240 Pin x64 x72 Pin x64 x72 Pin x64 x72 Pin x64 x72 Non ECC ECC Non ECC ECC Non ECC ECC Non ECC ECC 17 Vss Vss 137 DQ14 DQ14 77 ODT1 ODT1 197 VDD VDD 18 DQ10 DQ10 138 DQ15 DQ15 78 VDD VDD 198 NC NC 19 DQ11 DQ11 139 Vss Vss 79 NC NC 199 Vss Vss 20 Vss Vss 140 DQ20 DQ20 80 Vss Vss 200 DQ36 DQ36 21 DQ16 DQ16 141 DQ21 DQ21 81 DQ32 DQ32 201 DQ37 DQ37 22 DQ17 DQ17 142 Vss Vss 82 DQ33 DQ33 202 VSS Vss 23 Vss Vss 143 DM2 DM2 83 Vss Vss 203 DM4 DM4 24 DQS2 DQS2 144 NC NC 84 DQS4 DQS4 204 NC NC 25 DQS2 DQS2 145 Vss Vss 85 DQS4 DQS4 205 Vss Vss 26 Vss Vss 146 DQ22 DQ22 86 Vss Vss 206 DQ38 DQ38 27 DQ18 DQ18 147 DQ23 DQ23 87 DQ34 DQ34 207 DQ39 DQ39 28 DQ19 DQ19 148 Vss V
30. 35 9 tREFI ns CWL 2 5 ICKk AVG Reserved ns 1 2 3 4 7 CWL 6 7 fck AvG Reserved ns 4 CWL 5 fcK AVG 2 5 3 3 ns 1 2 3 7 CL 6 CWL 26 CK AVG Reserved ns 1 2 3 4 7 CWL 7 ck AVG Reserved ns 4 CWL 5 ck AvG Reserved ns 4 Nr CWL 6 fck vo 1 875 2 5 ns 1 2 3 4 7 CWL 7 ck AVG Reserved ns 1 2 3 4 7 CWL 8 ck AvG Reserved ns 4 CWL 5 ck AvG Reserved ns 4 C28 CWL 6 lck AVG 1 875 lt 2 5 ns 1 2 3 7 CWL 7 fcK AVG Reserved ns 1 2 3 4 7 CWL 8 fCK AVG Reserved ns 1 2 3 4 CWL 5 6 ck ava Reserved ns 4 CL29 CWL 7 tcxave 1 5 lt 1 875 ns 1 2 3 4 7 CWL 8 ck AvG Reserved ns 1 2 3 4 CWL 5 6 ck AvG Reserved ns 4 CL 10 CWL 7 fcx ave 1 5 lt 1 875 ns 1 2 3 7 CWL 8 lck AvG Reserved ns 1 2 3 4 cL 11 EWL gt 6 7 fekiavo Reserved ns 4 CWL 8 ck AVG 1 25 1 5 ns 1 2 3 Supported CL Settings 6 7 8 9 10 11 Dick Supported CWL Settings 5 6 7 8 ck Rev 1 0 Oct 2010 36 hynix Speed Bin Table Notes Absolute Specification Toper VppQ Vpp 1 5V 0 075 V Notes 1 The CL setting and CWL setting result in tCK AVG MIN and tCK AVG MAX requirements When making a selection of tCK AVG both need to be fulfilled Requirements from CL setting as well as requirements from CWL setting 2 tCK AVG MIN limits Since CAS Latency is not purely analog data and strobe output are synchronized by the DLL all possible intermediate frequencies ma
31. AC Timing and Output Slew Rate Rev 1 0 Oct 2010 29 hynix Overshoot and Undershoot Specifications Address and Control Overshoot and Undershoot Specifications AC Overshoot Undershoot Specification for Address and Control Pins DDR3 DDR3 DDR3 DDR3 Parameter Units 800 1066 1333 1600 Maximum peak amplitude allowed for overshoot area See Figure below 0 4 0 4 0 4 0 4 V Maximum peak amplitude allowed for undershoot area See Figure below 0 4 0 4 0 4 0 4 V Maximum overshoot area above VDD See Figure below 0 67 0 5 0 4 0 33 V ns Maximum undershoot area below VSS See Figure below 0 67 0 5 0 4 0 33 V ns A0 A15 BAO BA3 CS RAS CAS WE CKE ODT See figure below for each parameter definition Maximum Amplitude Overshoot Area VDD Volts E Undershoot Area Maximum Amplitude Time ns Address and Control Overshoot and Undershoot Definition Address and Control Overshoot and Undershoot Definition Rev 1 0 Oct 2010 30 hynix Clock Data Strobe and Mask Overshoot and Undershoot Specifications AC Overshoot Undershoot Specification for Clock Data Strobe and Mask DDR3 DDR3 DDR3 DDR3 Parameter Units 800 1066 1333 1600 Maximum peak amplitude allowed for overshoot area See Figure below 0 4 0 4 0 4 0 4 V Maximum peak amplitude allowed for undershoot area See Figure below 0 4 0 4 0 4 0 4 V M
32. CKO CK SDRAMs D0 D7 2400hm 1 CKI CK SDRAMs D8 D15 VREFCA D0 DI5 One SPD exists per module CK CK SDRAMs D8 D15 RESET J RESET SDRAMs D0 D3 Rev 1 0 Oct 2010 14 hyuix 4GB 512Mx72 Module 2Rank of x8 SO 31 DQSO DQS4 DQSO DOo4 DMO i DM4 1 DM CS DQS DQS DM CSDQS DQS DM CS DQS DQS DM CSDQS DQS DQO Ww l 0O0 1 0 0 DQ32 W41 0 0 1 0 0 DQ W41 01 DO 1 01 D9 DQ33 v 1 0 1 D4 1 01 D13 DQ2 wvH1 02 1 0 2 DQ34 W41 0 2 1 0 2 DQ3 W 03 1 0 3 DQ35 W41 0 3 1 03 DQ4 W l O4 1 0 4 DQ36 W1 0 4 1 0 4 DQ5 WUI 05 1 05 DQ37 W41 0 5 1 05 DQ6 W41 06 1 0 6 Ao DQ38 W1 0 6 1 0 6 DQ7 W JO7 Z 1 07 Z DQ39 W41 0 7 1 07 ZQ DQS1 Ar DOS5 LEE DQS1 DQS5 3 DM1 1 DM5 t DM CS DQS DQS DM CSDQS DQS DM CS D
33. D2NT 576 630 720 mA IDD2PO 216 216 216 mA IDD2P1 270 270 270 mA IDD2Q 450 540 540 mA IDD3N 540 630 720 mA IDD3P 270 270 270 mA IDDAR 945 1125 1305 mA IDDAW 945 1125 1350 mA IDD5B 1575 1665 1800 mA IDD6 216 216 216 mA IDDET 270 270 270 mA IDD6TC 270 270 270 mA IDD7 1215 1485 1665 mA Rev 1 0 Oct 2010 54 hynix Module Dimensions 128Mx64 HMT312UGBFR6C 0 0C Front 2 10 0 15 gt ies Max R0 70 v Min 1 45 SPD 4x3 00 0 10 A DETAIL A DETAIL B 2 x G2 50 0 10 vade fom Qj 3 5 1754 9 17 00 gt 71 00 d 128 95 133 35 Back
34. QS DQS DM CSDQS DQS DQ8 W l O 0 1 0 0 DQ40 W1 0 0 1 0 0 DQ9 w O1 pl 01 p19 DQ41 I 01 ps O1 p14 DQ10 W41 0 2 1 0 2 DQ42 W 1 0 2 1 0 2 DQll W41 0 3 1 0 3 DQ43 W 1 0 3 1 0 3 DQ12 WH1 0 4 1 0 4 DQ44 NI O 4 1 0 4 DQ13 W41 0 5 1 05 zo DQ45 W1 0 5 1 05 DQ14 W4I 0 6 1 0 6 pa DQ46 W1 0 6 1 0 6 DOS2 DQ15 W41 0 7 zQ 1 07 DQS6 DQ47 w 1 0 7 zQ 1 07 z4 DQS2 DQS6 DM2 DM6 1 DM CS DQS DQS DM CSDQS DQS DM CS DQS DQS DM CSDQS DQS DQ16 W41 0 0 1 00 DQ48 W41 0 0 1 0 0 DQ17 w O 1 D2 1 01 D11 DQ49 W41 0 1 D6 1 01 D15 DQ18 W41 0 2 1 02 DQ50 w 1 0 2 1 0 2 DQ19 W41 0 3 1 0 3 DQ51 W41 0 3 1 0 3 DQ20 W1 0 4 1 04 DQ52 W1 0 4 1 0 4 DQ21 W41 05 1 0 5 DQ53 W41 0 5 1 0 5 DQ22 W 1 0 6 1 0 6 ZQ DQ54 W41 0 6 ios 20 DQ23 W1 0 7 E07 DQ55 W1 0 7 mm DQS3 Ari DOS7 Az bl DQS3 bees DM3 1 DM7 DM CS DQS DQS DM CSDQS DQS DM CS DQS DQS DM CSDQS DQS DQ24 W1 0 0 I 1 0 0 DQ56 w 1 0 0 1 0 0 DQ25 W1 0 1 D3 m 1 01 D12 DQ57 W41 0 1 D7 01 D16 DQ26 W1 0 2 1 0 2 DQ58 w I O 2 1 0 2 DQ27 W1 0 3 1 0 3 DQ59 W41 0 3 1 0 3 DQ28 W1 0 4 1 0 4 DQ60 W1 0 4 1 0 4 DQ29 W41 0 5 1 05 DQ61 W1 0 5 1 05 DQ30 W41 0 6 1 0 6 DQ62 W1 0 6 1 0 6 zo DQ31 W41 0 7 20 1 07 ZQ DQ63 W1 0 7 zQ 1 07 nm DQS8 m icd VDDSPD z SPD DQS8 SPD TS integrated VDD VDDQ D0 D17 DM8 To ee cR VREFDQ 4 00 017 DM CS DQS DQS DM CSDQS DQS EVENT
35. QSL DQSU CK DQS DQSL or DQSU DDR3 800 1066 1333 amp 1600 Symbol Parameter Unit Notes Min Max VSEH Single ended high level for strobes VDD 2 0 175 Note 3 V 1 2 Single ended high level for Ck CK VDD 2 0 175 Note 3 V 1 2 VSEL Single ended low level for strobes Note 3 VDD 2 0 175 V 1 2 Single ended low level for CK CK Note 3 VDD 2 0 175 V 1 2 Notes 1 For CK CK use VIH VIL ac of ADD CMD for strobes DQS DQS DQSL DQSL DQSU DQSU use VIH VIL ac of DQs 2 VIH ac VIL ac for DQs is based on VREFDQ VIH ac VIL ac for ADD CMD is based on VREFCA if a reduced ac high or ac low level is used for a signal group then the reduced level applies also here 3 These values are not defined however the single ended signals Ck CK DQS DQS DQSL DQSL DQSU DQSU need to be within the respective limits VIH dc max VIL dc min for single ended signals as well as the limita tions for overshoot and undershoot Refer to Overshoot and Undershoot Specifications on page 30 Differential nput Cross Point Voltage To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe each cross point voltage of differential input signals CK CK and DQS DQS must meet the requirements in table below The differential input cross point voltage VIX is measured from the actual cross point of true and complement signals to t
36. SU has also to comply with certain requirements for single ended signals CK and CK have to approximately reach VSEHmin VSELmax approximately equal to the ac levels VIH ac VIL ac for ADD CMD signals in every half cycle DQS DQSL DQSU DQS DQSL have to reach VSEHmin VSELmax approximately the ac levels VIH ac VIL ac for DQ signals in every half cycle preceding and following a valid transition Note that the applicable ac levels for ADD CMD and DQ s might be different per speed bin etc E g if VIH CA AC150 VI L CA AC150 is used for ADD CMD signals then these ac levels apply also for the single ended signals CK and CK VDD GE VD Seam RR RREREEERS EEG M VSEHmin oo eee ee eee Pe ee bee doe pee eee ees VDD 2 or VDDQ 2 2 e cece SSS eh oe Sebo eee hee Cee Sse CK or DQS VSELmax Single ended requirements for differential signals Note that while ADD CMD and DQ signal requirements are with respect to Vref the single ended compo nents of differential signals have a requirement with respect to VDD 2 this is nominally the same the transition of single ended signals through the ac levels is used to measure setup time For single ended components of differential signals the requirement to reach VSELmax VSEHmin has no bearing on timing but adds a restriction on the common mode characteristics of these signals Rev 1 0 Oct 2010 22 hynix Single ended levels for CK DQS D
37. Sub Loop 0 use BA 2 0 6 instead 7 28 31 repeat Sub Loop 0 use BA 2 0 7 instead a DM must be driven LOW all the time DQS DQS are MID LEVEL b DQ signals are MID LEVEL Table 6 IDD2NT and IDDQ2NT Measurement Loop Pattern v 2 o D g J ala mm 812 BE fwg alg g om U O gt 8 Gia aq aq a 0 0 D 1 0 0 0 0 0 0 0 0 0 0 1 D 1 0 0 0 0 0 0 0 0 0 0 2 p Pa 2 2 a ee Or oe Po oe Flo 3 De ee Sf ie rh Ge of o 2 5 1 4 7 repeat Sub Loop 0 but ODT 0 and BA 2 0 1 D 9 2 8 11 repeat Sub Loop 0 but ODT 1 and BA 2 0 2 2 8 3 1 15 repeat Sub Loop 0 but ODT 1 and BA 2 0 3 4 16 19 repeat Sub Loop 0 but ODT 0 and BA 2 0 4 5 20 23 repeat Sub Loop 0 but ODT 0 and BA 2 0 5 6 24 17 repeat Sub Loop 0 but ODT 1 and BA 2 0 6 7 28 31 repeat Sub Loop 0 but ODT 1 and BA 2 0 7 a DM must be driven LOW all the time DQS DQS are MID LEVEL b DQ signals are MI D LEVEL Rev 1 0 Oct 2010 48 hyuix Table 7 I DD4R and IDDQ4R Measurement Loop Pattern x zi E 2 ol efl sl crl rica ly t Fig 28 BIS 3 S 3 3 3 v 3 o3 8 qT 3 C MEM 0 0 RD 0 1 0 1 0 0 00 0 0 0 0 00000000 1 D 1 0 0 0 0 0 00 0 0 0 0 2 3 DD 1 1 1 1 0 0 0 0 0 0 0 4 RD 0 1 0 1 0 0 00 0 0 F 0 00110011 5 D 1 0 0 0 0 0 00 0 0 F 0 2 6 7 DDl l l l l lol lol lololo Flol D 2 1 8 15 repeat Sub Loop 0 but
38. T Self Refresh Current Extended Temperature Range Tease 0 95 C Auto Self Refresh ASR Disabled Self Refresh Temperature Range SRT Extended CKE Low External clock Off CK and CK LOW CL see Table 1 BL 82 AL 0 CS Command Address Bank Address Inputs Data lO MID LEVEL DM stable at 0 Bank Activity Extended Temperature Self Refresh operation Output Buffer and RTT Enabled in Mode Registers ODT Signal MID LEVEL Ipperc Auto Self Refresh Current Tease 0 95 C Auto Self Refresh ASR Enabled Self Refresh Temperature Range SRT Normal CKE Low External clock Off CK and CK LOW CL see Table 1 BL 89 AL 0 CS Command Address Bank Address Inputs Data IO MID LEVEL DM stable at 0 Bank Activity Auto Self Refresh operation Output Buffer and RTT Enabled in Mode Registers ODT Signal MID LEVEL Rev 1 0 Oct 2010 44 hynix Symbol Description Operating Bank Interleave Read Current CKE High External clock On tCK nRC nRAS nRCD NRRD nFAW CL see Table 1 BL 82 AL CL 1 CS High between ACT and RDA Command Address Bank Address Inputs partially toggling according to Table Ipp 10 Data IO read data burst with different data between one burst and the next one according to Table 10 DM stable at 0 Bank Activity two times interleaved cycling through banks 0 1 7 with different address ing wee Table 10 Output Buffer and RTT Enab
39. able at 1 Command Address Bank Address Inputs stable at 0 Data IO MID LEVEL DM stable at 0 Bank Activity all banks closed Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Ipp3N Active Standby Current CKE High External clock On tCK CL see Table 1 BL 89 AL 0 CS stable at 1 Command Address Bank Address Inputs partially toggling according to Table 5 Data 10 MID LEVEL DM stable at 0 Bank Activity all banks open Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Pattern Details see Table 5 pp3P Active Power Down Current CKE Low External clock On tCK CL see Table 1 BL 8 AL 0 CS stable at 1 Command Address Bank Address Inputs stable at 0 Data lO MID LEVEL DM stable at 0 Bank Activity all banks open Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Rev 1 0 Oct 2010 43 hynix Symbol Description ppar Operating Burst Read Current CKE High External clock On tCK CL see Table 1 BL 8 AL 0 CS High between RD Command Address Bank Address Inputs partially toggling according to Table 7 Data IO seamless read data burst with different data between one burst and the next one according to Table 7 DM stable at 0 Bank Activity all banks open RD commands cycling through banks 0 0 1 1 2 2 see Table 7 Output Buffer and RTT Enabled in Mode Registers
40. ate is verified by design and characterization and may not be subject to production test Differential Output Voltage i e DQS DQS ae ee eee ee vOHdiff AC I I I I rc vOLdiff AC Delta TFdiff Differential Output Slew Rate Definition Differential Output slew Rate Definition Differential Output Slew Rate DDR3 800 DDR3 1066 DDR3 1333 DDR3 1600 Parameter Symbol Min Max Min Max Min Max Min Max Differential Output Slew Rate SRQdiff 5 10 5 10 5 10 TBD 10 V ns Description SR Slew Rate Q Query Output like in DQ which stands for Data in Query Output se Single ended Signals For Ron RZQ 7 setting Units Rev 1 0 Oct 2010 28 hynix Reference Load for AC Timing and Output Slew Rate Figure Below represents the effective reference load of 25 ohms used in defining the relevant AC timing parameters of the device as well as output slew rate measurements It is not intended as a precise representation of any particular system environment or a depiction of the actual load presented by a production tester System designers should use IBIS or other simulation tools to correlate the timing reference load to a system environment Manufacturers correlate to their production test conditions generally one or more coaxial transmission lines terminated at the tester electronics VDDQ m 25 Ohm Aa DUT VTT VDDQ 2 88 8 Reference Load for
41. aximum overshoot area above VDD See Figure below 0 25 0 19 0 15 0 13 V ns Maximum undershoot area below VSS See Figure below 0 25 0 19 0 15 0 13 V ns CK CK DQ DQS DGS DM See figure below for each parameter definition Maximum Amplitude Overshoot Area Undershoot Area Maximum Amplitude Time ns Clock Data Strobe and Mask Overshoot and Undershoot Definition Clock Data Strobe and Mask Overshoot and Undershoot Definition Rev 1 0 Oct 2010 31 hynix Refresh parameters by device density Refresh parameters by device density Parameter RTT_Nom Setting 512Mb 1Gb 2Gb 4Gb 8Gb Units Notes REC COINS iar tRFC 90 110 160 300 350 ns REF command time Average periodic IREFI 0 C lt Tcases 85 C 7 8 7 8 7 8 7 8 7 8 us refresh interval 85 C lt Toases 95 C 3 9 3 9 3 9 3 9 3 9 us Rev 1 0 Oct 2010 32 hyuix Standard Speed Bins DDR3 SDRAM Standard Speed Bins include tCK tRCD tRP tRAS and tRC for each corresponding bin DDR3 800 Speed Bins For specific Notes See Speed Bin Table Notes on page 37 Speed Bin DDR3 800E Unit Notes CL nRCD nRP 6 6 6 Parameter Symbol min max Internal read command to first data tna 15 20 ns ACT to internal read or write delay time Iacp 15 ns PRE command period tap 15 ns ACT to ACT or REF command period fac 52 5 ns ACT to PRE command pe
42. d and Address DDR3 800 1066 1333 1600 Symbol Parameter Unit Notes Min Max VIH CA DC100 DC input logic high Vref 0 100 VDD V 1 VIL CA DC100 DC input logic low VSS Vref 0 100 V 1 VIH CA AC175 AC input logic high Vref 0 175 Note2 V 1 2 VIL CA AC175 AC input logic low Note2 Vref 0 175 V 1 2 VIH CA AC150 AC Input logic high Vref 0 150 Note2 V 1 2 VIL CA AC150 AC input logic low Note2 Vref 0 150 V 1 2 VnetCA DC Reference Voltage for ADD CMD inputs 0 49 VDD 0 51 VDD V 3 4 Notes 1 For input only pins except RESET Vref VrefCA DC 2 Refer to Overshoot and Undershoot Specifications on page 30 3 The ac peak noise on Vger may not allow Vref to deviate from VgercA pc by more than 1 VDD for reference approx 15 mV 4 For reference approx VDD 2 15 mV Rev 1 0 Oct 2010 17 hynix AC and DC I nput Levels for Single Ended Signals DDR3 SDRAM will support two Vih Vil AC levels for DDR3 800 and DDR3 1066 as specified in the table below DDR3 SDRAM will also support corresponding tDS values Table 41 and Table 47 in DDR3 Device Operation as well as derating tables in Table 44 of DDR3 Device Operation depending on Vih Vil AC lev els Single Ended AC and DC I nput Levels for DQ and DM DDR3 800 1066 DDR3 1333 1600 Symbol Parameter Unit Notes Min Max Min Max VIH CA DC100 DC input logic high Vref
43. d between 0 85 C under all operating conditions 3 Some applications require operation of the DRAM in the Extended Temperature Range between 85 C and 95 C case temperature Full specifications are guaranteed in this range but the following additional conditions apply a Refresh commands must be doubled in frequency therefore reducing the Refresh interval tREFI to 3 9 us It is also possible to specify a component with 1X refresh tREFI to 7 8us in the Extended Temperature Range Please refer to the DIMM SPD for option availability b Hynix DDR3 SDRAMs support Auto Self Refresh and Extended Temperature Range and please refer to Hynix component datasheet and or the DIMM SPD for tREFI requirement in the Extended Temperature Range Rev 1 0 Oct 2010 16 hynix AC amp DC Operating Conditions Recommended DC Operating Conditions Recommended DC Operating Conditions Rating Symbol Parameter Units Notes Min Typ Max VDD supply Voltage 1 425 1 500 1 575 12 VDDQ supply Voltage for Output 1 425 1 500 1 575 1 2 Notes 1 Under all conditions VDDQ must be less than or equal to VDD 2 VDDQ tracks with VDD AC parameters are measured with VDD and VDDQ tied together AC amp DC Input Measurement Levels AC and DC Logic I nput Levels for Single Ended Signals AC and DC I nput Levels for Single Ended Command and Address Signals Single Ended AC and DC Input Levels for Comman
44. ead or acp 13 5 _ write delay time 13 125 8 PRE command period trp Fx ns ACT to ACT or REF fac 49 5 _ x command period 49 125 8 ACT to PRE command fee 36 9 tREFI n period CWL 5 lck AvG Reserved ns 1 2 3 4 6 uiis CWL 6 7 fck AvG Reserved ns 4 CWL 2 5 lck AVG 2 5 3 3 ns 1 2 3 6 CL26 CWL 6 amp xave Reserved ns 1 2 3 4 6 CWL 7 ck AVG Reserved ns 4 CWL 5 ck AvG Reserved ns 4 1 875 2 5 CL 7 CWL 6 CK AVG ns 1 2 3 4 6 Reserved CWL 7 CK AVG Reserved ns 1 2 3 4 CWL 5 ck AvG Reserved ns 4 CL 8 CWL 6 lck AVG 1 875 2 5 ns 1 2 3 6 CWL 7 CK AVG Reserved ns 1 2 3 4 Ir CWL 5 6 fck AvG Reserved ns 4 CWL 27 ck AVG 1 5 1 875 ns 1 2 3 4 CWL 5 6 fck AvG Reserved ns 4 CL 10 1 2 CWL 7 fxiave Reserved s D Supported CL Settings 6 8 7 9 10 lick Supported CWL Settings 5 6 7 ck Rev 1 0 Oct 2010 35 hynix DDR3 1600 Speed Bins For specific Notes See Speed Bin Table Notes on page 37 Speed Bin DDR3 1600K CL nRCD nRP 11 11 11 Unit DAE Parameter Symbol min max Internal read command m 13 75 20 ae to first data 13 125 8 ACT to internal read or acp 13 75 _ write delay time 13 125 8 13 75 PRE command period trp 13 125 8 ns ACT to ACT or REF tc 48 75 command period 48 125 8 ACT to ope bus
45. epeat above D Command until nRRD 1 nRRD ACT 0 0 1 1 0 1 00 0 0 F 0 1 nRRD 1 RDA 0 1 0 1 0 1 00 1 0 F 0 00110011 nRRD 2 D 1 0 0 0 0 1 00 0 0 F 0 E repeat above D Command until 2 nRRD 1 2 2 nRRD repeat Sub Loop 0 but BA 2 0 2 2 3 3 nRRD repeat Sub Loop 1 but BA 2 0 3 4 4 nRRD D 1 0 0 0 0 3 00 0 0 F 0 Assert and repeat above D Command until nFAW 1 if necessary 5 nFAW repeat Sub Loop 0 but BA 2 0 2 4 6 nFAW nRRD repeat Sub Loop 1 but BA 2 0 5 7 nFAW 2 nRRD repeat Sub Loop 0 but BA 2 0 6 8 nFAW 3 nRRD repeat Sub Loop 1 but BA 2 0 7 5 9 nFAW 4 nRRD D 1 0 0 0 0 7 00 0 0 F 0 T Assert and repeat above D Command until 2 nFAW 1 if necessary S z 2 nFAW 0 ACT 0 0 1 1 0 0 00 0 0 F 0 B a 10 2 nFAW 1 RDA 0 1 0 1 0 0 00 1 0 F 0 00110011 D 1 0 0 0 0 0 00 0 0 F 0 ena EE Repeat above D Command until 2 nFAW nRRD 1 2 nFAW nRRD ACT 0 0 1 1 0 1 00 0 0 0 0 11 2 nFAW nRRD 1 RDA 0 1 0 1 0 1 00 1 0 0 0 00000000 D 1 0 0 0 0 1 00 0 0 0 0 sone RNS Repeat above D Command until 2 nFAW 2 nRRD 1 12 2 nFAW 2 nRRD repeat Sub Loop 10 but BA 2 0 2 13 2 nFAW 3 nRRD repeat Sub Loop 11 but BA 2 0 3 D 1 0 0 0 0 3 00 0 0 0 0 9c UR RISORSE Assert and repeat above D Command until 3 nFAW 1 if necessary 15 3 nFAW repeat Sub Loop 10 but BA 2 0 2 4 16 3 nFAW nRRD repeat Sub Loop 11 but BA 2 0 5 17 3 nFAW 2 nRRD repeat Sub Loop 10 but BA 2 0 6 18 3 nFAW 3 nRRD repeat Sub Loop 11 but BA 2
46. he midlevel between of VDD and VSS Rev 1 0 Oct 2010 Vix Definition VDD VSS r CK DQS CK DQS 23 hynix Cross point voltage for differential input signals CK DQS DDR3 800 1066 1333 amp 1600 Symbol Parameter Unit Notes Min Max V Differential Input Cross Point Voltage 150 150 mV i relative to VDD 2 for CK CK 175 175 mV 1 Differential Input Cross Point Voltage Vix relative to VDD 2 for DOS DQS 130 oe Um Notes 1 Extended range for Vix is only allowed for clock and if single ended clock input signals CK and CK are monotonic with a single ended swing VSEL VSEH of at least VDD 2 250 mV and when the differential slew rate of CK CK is larger than 3 V ns 2 Refer to the table Single ended levels for CK DQS DQSL DQSU CK DQS DQSL or DQSU on page 23 for VSEL and VSEH standard values Slew Rate Definitions for Single Ended I nput Signals See 7 5 Address Command Setup Hold and Derating on page 137 in DDR3 Device Operation for sin gle ended slew rate definitions for address and command signals See 7 6 Data Setup Hold and Slew Rate Derating on page 144 in DDR3 Device Operation for single ended slew rate definition for data signals Rev 1 0 Oct 2010 24 hynix Slew Rate Definitions for Differential I nput Signals Input slew rate for differential signals CK CK and DQS DQS are defined and measured as sho
47. hyuix DDR3 SDRAM Unbuffered DI MMs Based on 2Gb B Die HMT312U6BFR6C HMT325U6BFR8C HMT325U7BFR8C HMT351U6BFR8C HMT351U7BFR8C Hynix Semiconductor reserves the right to change products or specifications without notice Rev 1 0 Oct 2010 1 hyuix Revision History Revision No History Draft Date Remark 0 1 Initial Release Dec 2009 0 2 Added IDD Specification Feb 2010 0 3 Editorial Change Apr 2010 1 0 DIMM line up 1Rx16 added Oct 2010 Rev 1 0 Oct 2010 hynix Description Hynix Unbuffered DDR3 SDRAM DIMMs Unbuffered Double Data Rate Synchronous DRAM Dual In Line Memory Modules are low power high speed operation memory modules that use Hynix DDR3 SDRAM devices These Unbuffered SDRAM DIMMs are intended for use as main memory when installed in systems such as PCs and workstations Feature VDD 1 5V 0 075V e VDDQ 1 5V 0 075V e VDDSPD 3 0V to 3 6V Functionality and operations comply with the DDR3 SDRAM datasheet 8 internal banks Data transfer rates PC3 10600 PC3 8500 or PC3 6400 Bi directional Differential Data Strobe 8 bit pre fetch Burst Length BL switch on the fly BL 8 or BC Burst Chop 4 Supports ECC error correction and detection On Die Termination ODT supported Temperature sensor with integrated SPD Serial Presence Detect EEPROM RoHS compliant This product is in compliance with the RoHS directive O
48. in Max VIHdiff Differential input high 0 200 Note 3 V 1 VILdiff Differential input logic low Note 3 0 200 V 1 VIHdiff ac Differential input high ac 2 x VIH ac Vref Note 3 V 2 VILdiff ac Differential input low ac Note 3 2 x VIL ac Vref V 2 Notes 1 Used to define a differential signal slew rate 2 For CK CK use VIH VIL ac of AADD CMD and VREFCA for DQS DQS DQSL DQSL DQSU DQSU use VIH VIL ac of DQs and VREFDQ if a reduced ac high or ac low levels is used for a signal group then the reduced level applies also here 3 These values are not defined however the single ended signals Ck CK DQS DQS DQSL DQSL DQSU DQSU need to be within the respective limits VIH dc max VIL dc min for single ended signals as well as the limita tions for overshoot and undershoot Refer to Overshoot and Undershoot Specifications on page 30 Allowed time before ringback tDVAC for CK CK and DQS DQS tDVAC ps tDVAC ps Slew Rate V ns VIH Ldiff ac 350mV VIH Ldiff ac 300mV min max min max gt 4 0 75 175 4 0 57 170 3 0 50 167 2 0 38 163 1 8 34 162 1 6 29 161 1 4 22 159 1 2 13 155 1 0 0 150 1 0 0 150 3 Rev 1 0 Oct 2010 21 hynix Single ended requirements for differential signals Each individual component of a differential signal CK DQS DQSL DQSU CK DQS DQSL of DQ
49. ing to DDR3 1333H or DDR3 1600F should program 13 125 ns in SPD bytes for tAAmin Byte 16 tRCDmin Byte 18 and tRP min Byte 20 Once tRP Byte 20 is programmed to 13 125ns tRCmin Byte 21 23 also should be pro grammed accordingly For example 49 125ns tRASmin tRPmin 36 ns 13 125 ns for DDR3 1333H and 48 125ns tRASmin tRPmin 35 ns 13 125 ns for DDR3 1600K Rev 1 0 Oct 2010 37 hynix Environmental Parameters Symbol Parameter Rating Units Notes ToPR Operating temperature ambient 0 to 55 C 3 Hopr Operating humidity relative 10 to 90 TsrG Storage temperature 50 to 100 oC 1 Herc Storage humidity without condensation 5 to 95 926 1 PpAR Barometric Pressure operating amp storage 105 to 69 K Pascal 1 2 Note 1 Stresses greater than those listed may cause permanent damage to the device This is a stress rating only and device functional operation at or above the conditions indicated is not implied Expousure to absolute maximum rating conditions for extended periods may affect reliablility 2 Up to 9850 ft 3 The component maximum case Temperature Tease shall not exceed the value specified in the DDR3 DRAM component specification Rev 1 0 Oct 2010 38 hynix Pin Capacitance VDD 1 5V VDDQ 1 5V 1GB HMT312U6BFR6C
50. ion A0 A15 SDRAM address bus SCL 12C serial bus clock for EEPROM BA0 BA2 SDRAM bank select SDA 12C serial bus data line for EEPROM RAS SDRAM row address strobe SA0 SA2 C slave address select for EEPROM CAS SDRAM column address strobe VDD SDRAM core power supply WE SDRAM write enable VDDQ SDRAM 1 0 Driver power supply S0 S1 DIMM Rank Select Lines VREFDQ SDRAM 1 O reference supply CKEO CKEl SDRAM clock enable lines VREFCA UT command address reference ODTO ODT1 On die termination control lines Vss Power supply return ground DQ0 DQ63 DIMM memory data bus VDDSPD Serial EEPROM positive power supply CB0 CB7 DIMM ECC check bits NC Spare pins no connect SDRAM data strobes Memory bus analysis tools DQS0 DQS8 positive line of differential pair TEST unused on memory DIMMS LAT SDRAM data strobes DQS0 DQS8 negative line of differential pair RESET Set DRAMs to Known State SDRAM data masks high data strobes T DM0 DM8 x8 based x72 DIMMs VIT SDRAM 1 O termination supply CKO CK1 SDRAM cgi RSVD Reserved for future use positive line of differential pair n SDRAM clocks EISE negative line of differential pair The VDD and VDDQ pins are tied common to a single power plane on these designs Rev 1 0 Oct 2010 hynix I nput Output Functional Descriptions Symbol Type Polarity Function CKO CK1 CK0 CK1 SSTL Differential crossing CK and CK are differential clock inputs All the DDR3 SDRAM
51. is not routed on the module ODTO ODT SDRAMs D0 D3 VREFDQ D0 D3 7 For each DRAM a unique ZQ resistor is bu PECEDRAMEDICES vs D0 D3 Sr ground The ZQ resistor is CK0 CK SDRAMs D0 D3 VREFCA T po p3 8 One SPD exists per module RESET J RESET SDRAMs D0 D3 Rev 1 0 Oct 2010 11 hynix 2GB 256Mx64 Module 1Rank of x8 DOSO 2 DQS4 DQSO DOS4 a a DMO 314 DM4 DM CS DQS DQS 2M CS pas BOS DQ0 w41 0 0 DQ32 W41 op wo post vioz P DQ3 W41 0 3 DQ35 W41 0 3 DQ4 W O 4 DQ36 W41 0 4 DQ5 W 0 5 i Mp DQ6 wW l O 6 ZQ DQ38 VH ZQ DQ7 W 0 7 Ns DOSS D039 W41 0 7 L DQS1 DOSS DQS1 DM _w_ DM5 ES DM CS DQS DQS DM CS DQS DQS DQ8 w 00 DQ40 W41 0 0 DQ9 W l Ol1 pi DQ41 W41 0 D5 DQ10 W1 0 2 DQ42 W41 0 2 DQ11 W41 0 3 DQ43 W41 0 3 DQ12 W41 0 4 DQ44 W41 0 4 DQ13 W41 0 5 DQ45 W4I1 0 5 zi DQ14 W 1 O 6 ZQ E DQ46 11 O 6 ai DQ15 W4I 0 7 DQS6 DQ47 W41 0 7 DQS2 DASG DQS2 DM w DM6 DM CS DQS DQS DM CS DQS DQS DQ16 v 00 Pm E DQU7 W41 01 p2 wW D6 DQ18 W41 0 2 DQ50 W41 0 2 DQ19 W41 0 3 DQ51 W41 0 3 DQ20 1 0 4
52. led in Mode RegistersP ODT Signal stable at 0 Pattern Details see Table 10 a Burst Length BL8 fixed by MRS set MRO A 1 0 200B b Output Buffer Enable set MR1 A 12 OB set MR1 A 5 1 01B RTT Nom enable set MR1 A 9 6 2 011B RTT Wr enable set MR2 A 10 9 10B c Precharge Power Down Mode set MRO A12 0B for Slow Exit or MRO A12 1B for Fast Exit d Auto Self Refresh ASR set MR2 A6 OB to disable or 1B to enable feature e Self Refresh Temperature Range SRT set MR2 A7 OB for normal or 1B for extended temperature range f Read Burst Type Nibble Sequential set MRO A 3 0B Rev 1 0 Oct 2010 45 hyuix Table 3 IDDO Measurement Loop Pattern 8 9 E ES Hd o Rm 6 v Siz BE e eB IE 8 S 3 3 S S oe 0 0 ACT 0 0 1 1 0 0100 0 0 1 2 DD 17 07 00 0 0 0100 0 0 3 4 DD 1 1 1 1 0 0 00 0 0 s repeat pattern 1 4 until nRAS 1 truncate if necessary nRAS PRE 0 0 1 0 0 0100 0 0 0 0 m repeat pattern 1 4 until nRC 1 truncate if necessary 1 nRC 0 ACT 0 0 1 1 0 0 00 0 0 F 0 1 nRC 1 2 DD 1 04 0 0 0 0 00 0 0 F 0 gt 3 1 nRC 3 4 DD 1 1 1 1 0 0o0fo0 o0 o0 F o D s repeat pattern 1 4 until 1 nRC nRAS 1 truncate if necessary 98 1 nRC nRAS PRE 0 0 1 0 0 0 0 0 0 F O a repeat pattern 1 4 until 2 nRC 1 truncate if
53. ltaTRse Single ended output slew rate for falling edge VOH AC VoL AC Vou acy Vor ac l DeltaTFse Notes 1 Output slew rate is verified by design and characterisation and may not be subject to production test vOH AC Single Ended Output Voltage l e DQ Delta TFse Single Ended Output Slew Rate Definition vOI AC Single Ended Output slew Rate Definition Output Slew Rate single ended DDR3 800 DDR3 1066 DDR3 1333 DDR3 1600 Parameter Symbol Min Max Min Max Min Max Min Max bas Single ended Output Slew Rate SRQse 2 5 5 2 5 5 2 5 5 TBD 5 V ns Description SR Slew Rate Q Query Output like in DQ which stands for Data in Query Output se Single ended Signals For Ron RZQ 7 setting Rev 1 0 Oct 2010 27 hynix Differential Output Slew Rate With the reference load for timing measurements output slew rate for falling and rising edges is defined and measured between VOLdiff AC and VOHdiff AC for differential signals as shown in table and Figure below Differential Output Slew Rate Definition Measured Description Defined by From To Differential output slew rate for rising edge VoLdiff AC Vondit Ac Youaitt Ac Votaift Ac DeltaTRaiff Differential output slew rate for falling edge VoHditft AC Vowaitt ac Vouaitt ac Votaitt ac DeltaT Fdiff Notes 1 Output slew r
54. necessary 1 2 nRC repeat Sub Loop 0 use BA 2 0 1 instead 2 4 nRC repeat Sub Loop 0 use BA 2 0 2 instead 3 6 nRC repeat Sub Loop 0 use BA 2 0 3 instead 4 8 nRC repeat Sub Loop 0 use BA 2 0 4 instead 5 10 nRC repeat Sub Loop 0 use BA 2 0 5 instead 6 12 nRC repeat Sub Loop 0 use BA 2 0 6 instead 7 14 nRC repeat Sub Loop 0 use BA 2 0 7 instead a DM must be driven LOW all the time DQS DQS are MID LEVEL b DQ signals are MID LEVEL 46 Rev 1 0 Oct 2010 hynix Table 4 IDD1 Measurement Loop Pattern g g z saM ARA Rig a 3 Pe Sig 8 88 8 Els S S ome F oZ 5 o qT daa c 0 0 ACT 0 0 1 1 0 0 00 0 0 1 2 DD 1 0 0 0 0 0 00 0 0 3 4 DD 1 1 1 1 0 0 00 0 0 0 0 s repeat pattern 1 4 until nRCD 1 truncate if necessary nRCD RD 0 1 0 1 0 0 00 0 0 0 0 00000000 repeat pattern 1 4 until nRAS 1 truncate if necessary nRAS PRE 0 0 1 0 0 0 00 0 0 0 0 ET repeat pattern 1 4 until nRC 1 truncate if necessary 1 nRC 0 ACT 0 0 1 1 0 0 00 0 0 F 0 1 nRC 1 2 DD 1 0 0 0 0 0 00 0 0 F 0 NEN 1 nRC 3 4 DD 1 1 1 1 0 0 00 0 l0 F 0 D Y repeat pattern nRC 1 4 until nRC nRCE 1 truncate if necessary EJB 1 nRC nRCD RD ol 1 lo o o oo olo F o 00110011 m repeat pattern nRC 1 4 until nRC nRAS 1 truncate if necessary
55. ng to Table 5 Data 10 MID LEVEL DM stable at 0 Bank Activity all banks closed Output Buffer and RTT Enabled in Mode RegistersP ODT Signal stable at 0 Pattern Details see Table 5 Ipp2NT Precharge Standby ODT Current CKE High External clock On tCK CL see Table 1 BL 89 AL 0 CS stable at 1 Command Address Bank Address Inputs partially toggling according to Table 6 Data lO MID LEVEL DM stable at 0 Bank Activity all banks closed Output Buffer and RTT Enabled in Mode RegistersP ODT Signal toggling according to Table 6 Pattern Details see Table 6 Ipp2Po Precharge Power Down Current Slow Exit CKE Low External clock On tCK CL see Table 1 BL 89 AL 0 CS stable at 1 Command Address Bank Address Inputs stable at 0 Data IO MID LEVEL DM stable at 0 Bank Activity all banks closed Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Precharge Power Down Mode Slow Exit Ipp2P1 Precharge Power Down Current Fast Exit CKE Low External clock On tCK CL see Table 1 BL 89 AL 0 CS stable at 1 Command Address Bank Address Inputs stable at 0 Data IO MID LEVEL DM stable at 0 Bank Activity all banks closed Output Buffer and RTT Enabled in Mode Registers ODT Signal stable at 0 Precharge Power Down Mode Fast Exit Ipp2Q Precharge Quiet Standby Current CKE High External clock On tCK CL see Table 1 BL 89 AL 0 CS st
56. rdering I nformation Part Number Density Organization Component Composition did FDHS HMT312U6BFR6C G7 H9 PB 1GB 128Mx64 128Mx16 H5TQ2G63BFR 4 1 X HMT325U6BFR8C G7 H9 PB 2GB 256Mx64 256Mx8 H5TQ2G83BFR 8 1 X HMT325U7BFR8C G7 H9 PB 2GB 256Mx72 256Mx8 H5TQ2G83BFR 9 1 X HMT351U6BFR8C G7 H9 PB 4GB 512Mx64 256Mx8 H5TQ2G83BFR 16 2 X HMT351U7BFR8C G7 H9 PB 4GB 512Mx72 256Mx8 H5TQ2G83BFR 18 2 X Rev 1 0 Oct 2010 3 hynix Key Parameters CAS RAS MT s Grade ESK Latency B des p EE CL tRCD tRP ns ns ns ns ns tCK DDR3 1066 G7 1 875 7 13 125 13 125 37 5 50 625 7 7 7 DDR3 1333 H9 1 5 9 13 5 13 5 36 49 5 9 9 9 DDR3 1600 PB 1 25 11 13 75 13 75 35 48 75 11 11 11 Speed Grade Frequency MHz Grade Remark CL6 CL7 CL8 CL9 CL10 CL11 G7 800 1066 1066 H9 800 1066 1066 1333 1333 PB 800 1066 1066 1333 1333 1600 Address Table 1GB 1Rx16 2GB 1Rx8 2GB 1Rx8 4GB 2Rx8 4GB 2Rx8 Refresh Method 8K 64ms 8K 64ms 8K 64ms 8K 64ms 8K 64ms Row Address A0 A13 A0 A14 A0 A14 A0 A14 A0 A14 Column Address A0 A9 A0 A9 A0 A9 A0 A9 A0 A9 Bank Address BAO BA2 BAO BA2 BAO BA2 BAO BA2 BAO BA2 Page Size 2KB 1KB 1KB 1KB 1KB Rev 1 0 Oct 2010 hynix Pin Descriptions Pin Name Description Pin Name Descript
57. riod tras 37 5 9 tREFI ns CL 5 CWL 5 ck AVG Reserved ns L2 34 CL 6 CWL 5 ck AVG 2 5 3 3 ns 1 2 3 Supported CL Settings 6 cK Supported CWL Settings 5 cK Rev 1 0 Oct 2010 33 hyuix DDR3 1066 Speed Bins For specific Notes See Speed Bin Table Notes on page 37 Speed Bin DDR3 1066F Unit Note CL nRCD nRP 7 7 7 Parameter Symbol min max nternal read command to t first data AA 13 125 20 ns ACT to internal read or t write delay time RED 13 125 ns PRE command period trp 13 125 ns ACT to ACT or REF he 50 625 E i command period ACT to PRE command oe 37 5 9 tREFI ns period ae CWL 5 ICK AVG Reserved ns 1 2 3 4 5 CWL 6 lck AVG Reserved ns 4 NS CWL 25 ICK AVG 2 5 3 3 ns 1 2 3 5 7 CWL 6 ICK AVG Reserved ns 1 2 3 4 ers CWL 5 lck AVG Reserved ns 4 7 CWL 6 amp xavo 1 875 lt 2 5 ns 1 2 3 4 n CWL 5 lck AVG Reserved ns 4 7 CWL 6 fave 1 875 lt 2 5 ns 1 2 3 Supported CL Settings 6 7 8 lick Supported CWL Settings 5 6 lick Rev 1 0 Oct 2010 34 hynix DDR3 1333 Speed Bins For specific Notes See Speed Bin Table Notes on page 37 Speed Bin DDR3 1333H CL nRCD nRP 9 9 9 Unit ae Parameter Symbol min max Dad Pih ee tag m 20 n ACT to internal r
58. ss 88 DQ35 DQ35 208 Vss Vss 29 Vss Vss 149 DQ28 DQ28 89 Vss Vss 209 DQ44 DQ44 30 DQ24 DQ24 150 DQ29 DQ29 90 DQ40 DQ40 210 DQ45 DQ45 31 DQ25 DQ25 151 Vss Vss 91 DQ41 DQ41 211 Vss Vss 32 Vss Vss 152 DM3 DM3 92 Vss Vss 212 DM5 DM5 33 DQS3 DQS3 153 NC NC 93 DQS5 DQS5 213 NC NC 34 DQS3 DQS3 154 Vss Vss 94 DQS5 DQS5 214 Vss Vss 35 Vss Vss 155 DQ30 DQ30 95 Vss Vss 215 DQ46 DQ46 36 DQ26 DQ26 156 DQ31 DQ31 96 DQ42 DQ42 216 DQ47 DQ47 37 DQ27 DQ27 157 Vss Vss 97 DQ43 DQ43 217 Vss Vss 38 Vss Vss 158 NC CB4 98 Vss Vss 218 DQ52 DQ52 39 NC CBO 159 NC CB5 99 DQ48 DQ48 219 DQ53 DQ53 40 NC CB1 160 Vss Vss 100 DQ49 DQ49 220 Vss Vss 41 Vss Vss 161 DM8 DM8 101 Vss Vss 221 DM6 DM6 42 NC DQS8 162 NC NC 102 DQS6 DQS6 222 NC NC 43 NC DQS8 163 Vss Vss 103 DQS6 DQS6 223 Vss Vss 44 Vss Vss 164 NC CB6 104 Vss Vss 224 DQ54 DQ54 45 NC CB2 165 NC CB7 105 DQ50 DQ50 225 DQ55 DQ55 46 NC CB3 166 Vss Vss 106 DQ51 DQ51 226 Vss Vss 47 Vss Vss 167 NC NC 107 Vss Vss 227 DQ60 DQ60 NC No Connect RFU Reserved Future Use 1 NC pins should not be connected to anything on the DIMM including bussing within the NC group 2 Address pins A3 A8 and BAO and BAI can be mirrored or not mirrored Rev 1 0 Oct 2010 hynix Front Side left 1 60 Back Side right 121 180 Front Side left 61 120 Back Side right 181 240
59. ut Buffer enabled in MR1 RIT Nom RZQ 6 40 Ohm in MR1 RTT Wr RZQ 2 120 Ohm in MR2 TDQS Feature disabled in MR1 Attention The IDD and IDDQ Measurement Loop Patterns need to be executed at least one time before actual IDD or IDDQ measurement is started Define D CS RAS CAS WE HIGH LOW LOW LOW Define D CS RAS CAS WE HIGH HIGH HIGH HIGH Rev 1 0 Oct 2010 40 hynix Y lob Y DDQ optional Vbpa RESET CK CK CKE Das pas Att 25 Ohm CS DQ DM F C ___ Vppaq 2 RAS CAS WE TDQS TDAS A BA Measurement Setup and Test Load for IDD and IDDQ optional Measurements Note DIMM level Output test load condition may be different from above Application specific IDDQ memory channel Test Load NE Channel IDDQ IDDQ IO Power Simulation Simulation Simulation X Correction Channel IO Power Number Correlation from simulated Channel IO Power to actual Channel IO Power supported by IDDQ Measurement Rev 1 0 Oct 2010 41 hyuix Table 1 Timings used for I DD and I DDQ Measurement Loop Patterns DDR3 1066 DDR3 1333 DDR3 1600 E Symbol Unit 7 7 7 9 9 9 11 11 11 tek 1 875 1 5 1 25 ns CL 7 9 11 nCK RCD 7 9 11 nCK lac 27 33 39 nCK NRAS 20 24 28 nCK Arp 7 9 11 nCK 1KB page size 20 20 24 nCK TE AW 2KB page size 27 30 32 nCK 1KB page size 4 4 5 nCK ARRD
60. vel for output SR Vrr 0 1 x Vppo V 1 VoL AC AC output low measurement level for output SR Vrr 0 1 x Vppo V 1 Notes 1 The swing of 0 1 x Vppo is based on approximately 50 of the static single ended output high or low swing with a driver impedance of 409 and an effective test load of 2522 to Vtr Vppg 2 Differential AC and DC Output Levels Table below shows the output levels used for measurements of single ended signals Differential AC and DC Output Levels DDR3 800 1066 Symbol Parameter Unit Notes 1333 and 1600 Vonditt ac AC differential output high measurement level for output SR 0 2 x VDDQ V 1 VoLaiff ac AC differential output low measurement level for output SR 0 2 X VDDQ V 1 Notes 1 The swing of 0 2 x Vppq is based on approximately 50 of the static differential output high or low swing with a driver impedance of 402 and an effective test load of 2522 to Vr Vppg 2 at each of the differential outputs Rev 1 0 Oct 2010 26 hynix Single Ended Output Slew Rate When the Reference load for timing measurements output slew rate for falling and rising edges is defined and measured between Vo ac and Vop ac for single ended signals are shown in table and Figure below Single ended Output slew Rate Definition Measured Description Defined by From To Single ended output slew rate for rising edge VoL AC VoH AC Vou acy VoL Ac De
61. wn in table and Figure below Differential Input Slew Rate Definition Measured Description Defined by Min ax Differential input slew rate for rising edge TE m CK CK and DQS DQS ViLdiffmax VIHdiffmin VIHdiffmin VILdiffmax Delta TRdiff Differential input slew rate for falling edge TE CR CK CK and DQS DQS ViHdiffmin ViLdiffmax VIHdiffmin VILdiffmax Delta TFdiff Notes The differential signal i e CK CK and DQS DQS must be linear between these thresholds 1 x 9 ay _ d viHdiffmin Uu o a d v Oo 2 0 E p a S Q B Ldiffmax D a Differential Input Slew Rate Definition for DQS DQS and CK CK Differential I nput Slew Rate Definition for DQS DQS and CK CK Rev 1 0 Oct 2010 25 hyuix AC amp DC Output Measurement Levels Single Ended AC and DC Output Levels Table below shows the output levels used for measurements of single ended signals Single ended AC and DC Output Levels DDR3 800 1066 Symbol Parameter Unit Notes 1333 and 1600 VOH DC DC output high measurement level for IV curve linearity 0 8 x VDDQ V VOM DC DC output mid measurement level for IV curve linearity 0 5 x VDDQ V VoL DC DC output low measurement level for IV curve linearity 0 2 x VDDQ V VoH AC AC output high measurement le
62. y not be guaranteed An application should use the next smaller J EDEC standard tCK AVG value 2 5 1 875 1 5 or 1 25 ns when calculating CL nCK tAA ns tCK AVG ns rounding up to the next Supported CL 3 tCK AVG MAX limits Calculate tCK AVG tAA MAX CLSELECTED and round the resulting tCK AVG down to the next valid speed bin i e 3 3ns or 2 5ns or 1 875 ns or 1 25 ns This result is tCK AVG MAX corresponding to CLSE LECTED 4 Reserved settings are not allowed User must program a different value 5 Any DDR3 1066 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design Characterization 6 Any DDR3 1333 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design Characterization 7 Any DDR3 1600 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design Characterization 8 Hynix DDR3 SDRAM devices support down binning to CL 7 and CL 9 and tAA tRCD tRP satisfy mini mum value of 13 125ns SPD settings are also programmed to match For example DDR3 1333H devices supporting down binning to DDR3 1066F should program 13 125 ns in SPD bytes for tAAmin Byte 16 tRCDmin Byte 18 and tRPmin Byte 20 DDR3 1600K devices supporting down binn
63. ycle Address input defines the row address RAO0 RA15 During a Read or Write command cycle Address input defines the column address In addition to the column address AP is used to invoke autopre charge operation at the end of the burst read or write cycle If AP is high autoprecharge is selected and BAO BA1 BA2 defines the bank to be pre charged If AP is low autoprecharge is disabled During a Precharge com mand cycle AP is used in conjunction with BAO BA1 BA2 to control which bank s to precharge If AP is high all banks will be precharged regardless of the state of BAO BA1 or BA2 If AP is low BAO BA1 and BA2 are used to define which bank to precharge A12 BC is sampled during READ and WRITE commands to determine if burst chop on the fly will be per formed HIGH no burst chop LOW burst chopped DQ0 DQ63 CB0 CB7 SSTL Data and Check Bit Input Output pins DM0 DM8 SSTL Active High DM is an input mask signal for write data Input data is masked when DM is sampled High coincident with that input data during a write access DM is sampled on both edges of DQS Although DM pins are input only the DM loading matches the DQ and DQS loading VDD Vss Supply Power and ground for the DDR3 SDRAM input buffers and core logic VDD and VDDQ pins are tied to VDD VDDQ planes on these modules Rev 1 0 Oct 2010 hyuix

Hynix HMT351U6BFR8C-H9N0 memory module

Contents

Download Pdf Manuals

Related Search

Related Contents