Hynix 1GB DDR2 CL5
Contents
1. Front 67 60 gt 2 00 Min A 4 00 0 10 gt on 5 n 8 Detail B Detail A O CO N x v 8 SIDE 3 8MAX gt PIN 2 PIN 40 PIN42 PIN 200 O O 1 00 0 10 p Pie Detail of Contacts B Back 4 20 Detail of Contacts A Detail of Contacts B Front 0 45 0 03 gt he 2 70 AN5 n 2 o 9 n 9 RI N H N o 5 0 60 Mc 1 lt 110 0 05 4 20 Note 1 All dimensions are in millimeters 2 All outline dimensions and tolerances follow the J EDEC standard 3 0 13 tolerance on all dimensions unless otherwise stated 2 40 0 10 1 80 Rev 0 3 Dec 2009 22 hyuix REVISION HISTORY 200pin Unbuffered DDR2 SDRAM SO DI MMs Revision History Date 0 1 Initial data sheet released Jun 2008 0 2 Editorial Correction Sep 2008 0 3 Udated AC Timing Parameters by Speed Grade Dec 2009 Rev 0 3 Dec 2009 232. JCK0 K1 CKi 2 loads 2 loads ICS ODT CKE LDQS UDQS LDM 1 0 0 1 0 1 1 0 2 1 0 3 1 0 4 1 05 1 0 6 1 O 7 UDQS UDQS UDM 1 0 8 1 0 9 1 0 10 1 O 11 1 0 12 1 0 13 1 0 14 1 O 15 D3 SCL SA0 SA1 SDA lt SDA VppSPD ________ _ Serial PD VREF e J SDRAMS D0 D3 VDD 1 SDRAMS DO D3 VDD and VDDQ Vss ALII SDRAMS DO D3 SPD Note 1 Resistor values are 22 ohm 5 Rev 0 3 Dec 2009 hynix 200pin Unbuffered DDR2 SDRAM SO DI MMs FUNCTI ONAL BLOCK DI AGRAM 1GB 128Mbx64 HMP112S6EFR6C tm 132 5 ODT1 t e ODTO T e CKE1 e ckEo 9 sit 1 50 4 L d ICS e Sey kaa 50 Las amp LDQS Aa 8 DQS4 7w LDQS 5 H LDQS 5 DQSO 4 upas UDQS DQS4 J UDQS H UDQS DMO A Lb LDM DM4 J 4 LDM LDM DQ0 wv 1 0 0 1 0 0 DQ32 w 1 0 0 mow w 1 01 1 01
3. Pin Location Pin 40 A A D C Pin 2 Pin 42 Pin 200 Front Side Back Side err d 41 Pin pom D C Rev 0 3 Dec 2009 4 hynix FUNCTI ONAL BLOCK DI AGRAM 512MB 64Mbx64 HMP164S6EFR6C 200pin Unbuffered DDR2 SDRAM SO DI MMs 1 nc ODT1 N C CKE1 PNC PS Sea 139 5 CKEO 1 i S0 bee ed Tx Doso w DQSO0 w DM w DQO DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS2 w DQS2 W 4 DM2 w DQ8 JA J Deg r 10 DQ11 A DQ12 w DQ13 A 34 DQ14 DQ15 v LDQS UDQS LDM 1 0 0 1 01 1 0 2 1 0 3 1 0 4 1 05 1 0 6 1 07 UDQS UDQS UDM 1 0 8 1 0 9 1 O 10 I O 11 1 0 12 1 O 13 1 0 14 1 0 15 CS ODT CKE DO DQS4 wl DQS4 w DM4 w DQ32 A DQ33 A DQ34 A DQ35 wv DQ36 A DQ37 A DQ38 A DQ39 A 55 A 3 05 an __ DM5 w DQ40 A J DQ41 A J DQ42 A DQ43 A DQ44 DQ45 A DQ46 A DQ47 A ICS ODT CKE LDQS UDQS LDM 1 0 0
4. AO Serial PD w gt SDRAMS D0 15 SAl1 Al RAS SDRAMS D0 15 Ae WE ICAS V gt SDRAMS D0 15 dL m ANE SDRAMS DO 15 VppSPD Serial PD VREF 5 SDRAMS D0 D15 b hs VDD SDRAMS D0 D15 VoD and VDDQ 8 loads all CKO 5 6pF __ _ __ gt SDRAMS D0 D15 SPD CK1 _ t 8 loads Note 5 6pF 1 Resistor values are 22 ohm 5 ICKT unless other wide stated Rev 0 3 Dec 2009 7 la 200pin Unbuffered DDR2 SDRAM SO DI MMs ABSOLUTE MAXI MUM RATINGS Parameter Symbol Value Unit Note Voltage on Vpp pin relative to Vss Vpp 10V 2 3V V 1 Voltage on Vppg pin relative to Vss VDDQ 05V 2 3V V 1 Voltage on VDDL pin relative to Vss VDDL 0 5V 2 3 V V 1 Voltage on any pin relative to Vss Vin Vout 0 5V 2 3V V 1 Operating Conditions and Environmental Parameters Parameter Symbol Rating Units Notes DIMM Operating temperature ambient Topr 0 65 C Storage Temperature Tsrc 50 100 C 1 Storage Humidity without condensation Hsrc 5 to 95 96 1 DIMM Barometric Pressure operating amp storage pBAR 105 to 69 K Pascal 2 DRAM Component Case Temperature Range TCASE 0 95 3 Notes 1 Stress greater than those listed may cause permanent damage to the device This is a stress rating only and device functio
5. SDRAMS D0 15 CAS gt SDRAMS D0 15 IWE SDRAMS D0 15 L d cko jCko 4 loads gt CK1 4 loads IKI VppSPD 4 J Serial PD VREF 4 3 VDD I p SDRAMS D0 D3 Vss J SDRAMS DO D3 SPD Note 1 Resistor values are 22 ohm 5 gt SDRAMS DO D3 VoD and VDDQ Rev 0 3 Dec 2009 la VIX 200pin Unbuffered DDR2 SDRAM SO DI MMs FUNCTI ONAL BLOCK DI AGRAM 2GB 256Mbx64 HMP125S6EFR8C poem rm 32 H 596 CKE1 9 ODT1 T T e S1 i e CKEO ODTO 1 Iso CS0 ODTO CKEO CS1 ODT1 CKE1 CSO ODTO CKEO CS1 ODT1 50 Dos DOS DQS4 A DOS DQS DQSO A 4 spas DQS DQS4 N DQS DQS DMO JA 1 DM DM DM4 _ypar DM DM 00 2 1 00 1 00 DQ32 wW 1 0 0 1 0
6. t lt gt 1 0 0 05 3 2 40 0 1p 180 4 20 Note 1 All dimensions are in millimeters 2 All outline dimensions and tolerances follow the J EDEC standard 3 0 13 tolerance on all dimensions unless otherwise stated Rev 0 3 Dec 2009 20 la 200pin Unbuffered DDR2 SDRAM SO DI MMs PACKAGE OUTLINE 128Mx64 HMP112S6EFR6C Front 67 60 2 00 Min HE x 4 00 0 10 4 an 8 5 8 Detail B Detail A ly amp PIN 199 M v 8 S SIDE 3 8MAX gt PIN 200 O Detail B 1 00 0 10 i Detail of Contacts B Back Detail of Contacts A Detail of Contacts B Front etail of Contacts B Back d 4 20 Pala gt a 8 pn Hm 5 H un 9 x Lo 0 60 1 0 45 0 03 gos 1 40 0 10 180 tr 4 20 Note 1 All dimensions are in millimeters 2 All outline dimensions and tolerances follow the J EDEC standard 3 0 13 tolerance on all dimensions unless otherwise stated Rev 0 3 Dec 2009 21 hyuix 200pin Unbuffered DDR2 SDRAM SO DI MMs PACKAGE OUTLINE 256Mx64 HMP125S6EFR8C
7. 168 vss 19 DQ3 20 DQ12 69 NC 70 DQS3 119 NC ODT1 120 NC 169 DQS6 170 DM6 21 vss 22 DQ13 71 VSS 72 121 VSS 122 vss 171 vss 172 VSS 23 DQ8 24 VSS 73 DQ26 74 DQ30 123 DQ32 124 DQ36 173 DQ50 174 DQ54 25 DQ9 26 DM1 75 DQ27 76 DQ31 125 DQ33 126 DQ37 175 DQ51 176 DQ55 27 VSS 28 VSS 77 VSS 78 vss 127 VSS 128 vss 177 vss 178 VSS 29 DQS1 30 CKO 79 CKEO 80 NC CKE1 129 DQS4 130 DM4 179 DQ56 180 DQ60 31 DQS1 32 CKO 81 VDD 82 VDD 131 DQS4 132 181 DQ57 182 DQ61 33 VSS 34 VSS 83 NC 84 NC A15 133 VSS 134 DQ38 183 VSS 184 VSS 35 DQ10 36 DQ14 85 BA2 86 4 135 DQ34 136 DQ39 185 DM7 186 DQS7 37 DQ11 38 DQ15 87 VDD 88 VDD 137 DQ35 138 vss 187 188 DQS7 39 vss 40 vss 89 A12 90 All 139 VSS 140 DQ44 189 DQ58 190 vss 41 vss 42 vss 91 A9 92 A7 141 DQ40 142 DQ45 191 DQ59 192 DQ62 43 DQ16 44 DQ20 93 A8 94 A6 143 DQ41 M4 vss 193 VSS 194 DQ63 45 DQ17 46 DQ21 95 VDD 96 VDD 145 vss 146 DQS5 195 SDA 196 VSS 47 VSS 48 VSS 97 A5 98 A4 147 DM5 148 DQS5 197 SCL 198 SAO 49 DQS2 50 NC 99 A3 100 A2 149 VSS 150 VSS 199 VDDSPD 200 SA1 on Ul Ww
8. CKE 1 0 Input Active High Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal when low By deactivating the clocks CKE low initiates the Power Down mode or the Self Refresh mode S 1 0 Input Active Low Enables the associated DDR2 SDRAM command decoder when low and disables the command decoder when high When the command decoder is disabled new commands are ignored but previous operations continue Rank 0 is selected by 50 Rank 1 is selected by 51 RAS CAS WE Input Active Low When sampled at the cross point of the rising edge of CK and falling edge of CK CAS RAS and WE define the operation to be executed by the SDRAM BA 2 0 Input Selects which DDR2 SDRAM internal bank of four or eight is activated ODT 1 0 Input Active High Asserts on die termination for DQ DM DQS and DQS signals if enabled via the DDR2 SDRAM mode register A 9 0 A10 AP A 15 11 Input During a Bank Activate command cycle difines the row address when sampled at the cross point of the rising edge of CK and falling edge of CK During a Read or Write com mand cycle defines the column address when sampled at the cross point of the rising edge of CK and falling edge of CK In addition to the column address AP is used to invoke autoprecharge operation at the end of the burst read or write cycle If AP is high autoprecharge is selected and BAO BAn defines the bank to be precharg
9. 0 2 tCK Mode register set command cycle time tMRD 2 2 tCK Write preamble tWPRE 0 35 0 35 tCK Write postamble tWPST 0 4 0 6 0 4 0 6 tCK Data Out edge to Clock edge Skew tAC 600 600 500 500 ps Address and control input setup time tIS 350 250 ps Rev 0 3 Dec 2009 16 hyuix 200pin Unbuffered DDR2 SDRAM SO DI MMs Continued DDR2 400 DDR2 533 Parameter Symbol Unit Note Min Max Min Max Address and control input hold time 475 375 ps Read preamble tRPRE 0 9 1 1 0 9 1 1 tCK Read postamble tRPST 0 4 0 6 0 4 0 6 tCK to Active Auto Refresh command tRFC 1275 1275 iz period Row Active to Row Active Delay for 1KB page size tRRD 7 5 7 5 ns Row Active to Row Active Delay for 2KB page size tRRD 10 10 ns Four Activate Window for 1KB page size tFAW 37 5 37 5 ns Four Activate Window for 2KB page size tFAW 50 50 ns CAS to CAS command delay tCCD 2 2 tCK Write recovery time tWR 15 15 ns Auto Precharge Write Recovery Precharge Time tDAL tWR tRP tWR tRP tCK Write to Read Command Delay tWTR 10 15 5 ns Internal read to precharge command delay tRTP 7 5 7 5 ns Exit self refresh to a non read command tXSNR tRFC 10 tRFC 10 ns Exit self refresh to a read command tXSRD 200 200 tCK Exit precharge power down to any non read 2 y 2 tCK command Exit a
10. 1 0 1 1 02 1 0 3 1 0 4 1 05 1 0 6 1 O 7 UDQS UDQS UDM 1 0 8 1 0 9 1 O 10 10 11 1 0 12 1 O 13 1 0 14 1 0 15 D2 DQS2 A 4 DQS2 w DM2 DQ16 A DQ17 A DQ18 A 4 DQ19 A J DQ20 A DQ21 A J DQ22 A DQ23 DQS3 MA DQS3 w DM3 w DQ24 A DQ25 A DQ26 A DQ27 A DQ28 A DQ29 A DQ30 A LDQS UDQS LDM 1 0 0 1 01 1 0 2 1 0 3 1 0 4 1 05 1 0 6 1 O 7 UDQS UDQS UDM 1 0 8 1 09 1 0 10 1 O 11 1 O 12 1 0 13 1 0 14 1 O 15 CS ODT CKE D1 DQS6 wN 56 A 4 DM6 wl DQ48 A DQ49 A DQ50 A DQ51 A J DQ52 A DQ53 DQ54 A DQ55 A DQS7 N DQS7 A Dm w DQ56 A DQ57 A DQ58 A DQ59 A DQ60 A DQ61 A J DQ62 w _ DQ63 A r 3 138 5 BAO BA2 _ SDRAMS D0 3 w gt SDRAMS D0 3 IRAS V gt SDRAMS D0 3 CAS M gt SDRAMS D0 3 IWE V gt SDRAMS D0 3 cko
11. DQ33 WW 1 0 1 1 01 DQ2 1 0 2 1 0 2 DQ34 A 1 0 2 1 0 2 DQ3 A 34 1 0 3 1 0 3 DQ35 WW 1 0 3 1 0 3 DQ4 A 1 0 4 1 0 4 DQ36 A A 1 0 4 L 1 0 4 DQ5 w 1 05 1 05 DQ37 WWwW 1 0 5 m 1 05 06 wv 1 0 6 1 0 6 DQ38 W 1 0 6 1 0 6 DQ7 wv 1 07 1 07 DQ39 A 1 0 7 m 1 07 DQS2 J UDQS DO UDQS D4 DQS5 J UDQS D2 UDQS D6 DQS2 uDQs UDQS 2 55 UDQS UDQS DM2 __ w _ UDM UDM DM5 w UDM UDM DQ8 1 0 8 1 0 8 DQ40 w 1 0 8 H 1 0 8 DQ9 w 1 0 9 1 09 DQ41 pw 1 0 9 tL 1 0 9 DQ10 w 1 0 10 1 0 10 DQ42 A 1 0 10 t 1 0 10 DQ11 wr 1 0 11 1 O 11 DQ43 A 1 0 11 H 1 0 11 DQ12 A 1 0 12 1 0 12 DQ44 A 1 0 12 1 0 12 DQ13 A 1 0 13 1 0 13 DQ45 A 1 0 13 1 0 13 DQ14 w 1 0 14 1 0 14 DQ46 wW 1 0 14 1 0 14 DQ15 w 1 0 15 1 O 15 DQ47 A 1 0 15 1 0 15 EMEN 5 9 ISA O ISA mS A DQS2 LDQS LDQS 9 DQS6 J 4 LDQS A Y m Loos 8 2 52 JUDQS UDQS DQ 6 ___ wyr UDQS UDQS DM2 ___ w _J LDM L
12. Signal Waveform gt Rev 0 3 Dec 2009 9 la Vix 200pin Unbuffered DDR2 SDRAM SO DI MMs Differential Input AC logic Level Symbol Parameter Min Max Units Note Vip ac ac differential input voltage 0 5 Vppo 0 6 V 1 Vix ac ac differential cross point voltage 0 5 Vppg 0 175 0 5 Vppo 0 175 V 2 1 VN DC specifies the allowable DC execution of each input of differential pair such as CK CK DQS DQS LDQS LDQS UDQS and UDGS 2 Vip DC specifies the input differential voltage VtR Vcp required for switching where is the true input such as CK DQS LDQS or UDQS level and Vcp is the complementary input such as CK DOS LDQS or UDQS level The minimum value is equal to Vy4 DC Vij DC Crossing point V V Vep IX or YOX Vssa lt Differential signal levels gt Notes 1 Vip AC specifies the input differential voltage Vrg Vcp required for switching where Vrg is the true input signal such as CK DQS LDQS or UDQS and is the complementary input signal such as CK DQS LDQS or UDQS The minimum value is equal to V ji AC Vi AC 2 The typical value of Vjx AC is expected to be about 0 5 Vppo of the transmitting device and is expected to track variations in Vppg Vix AC indicates the voltage at which differential input signals must cross DIFFERENTIAL AC OUTPUT PARAMETERS
13. Symbol Parameter Min Max Units Note Vox ac ac differential cross point voltage 0 5 Vppo 0 125 0 5 Vppg 0 125 V 1 Notes 1 The typical value of Vox AC is expected to be about 0 5 Vppo of the transmitting device and Vox AC is expected to track variations in Vppq Vox AC indicates the voltage at which differential output signals must cross Rev 0 3 Dec 2009 10 hyuix OUTPUT BUFFER LEVELS OUTPUT AC TEST CONDITIONS 200pin Unbuffered DDR2 SDRAM SO DI MMs Symbol Parameter SSTL_18 Units Notes VorR Output Timing Measurement Reference Level 0 5 Vppg V 1 Notes 1 The VDDQ of the device under test is referenced OUTPUT DC CURRENT DRI VE Symbol Parameter 55 18 Units Notes longc Output Minimum Source DC Current 13 4 mA 1 3 4 lot dg Output Minimum Sink DC Current 13 4 mA 2 3 4 Notes 1 Vono 1 7 V Vout 1420 mV Vout Vppo l oy must be less than 21 ohm for values of between Vppo and VDDQ 280 mV 2 Vopg 1 7 V Vout 280 mV Vgyr Io must be less than 21 ohm for values of between 0 V and 280 mV Ae Ww The dc value of applied to the receiving device is set to The values of l p dc and Io dc are based on the conditions given in Notes 1 and 2 They are used to test device drive current capability to ensure Vi min plus a noise margin and Vj max minus a noise margin are delivered to an SSTL 18 re
14. 0 w 1 01 1 01 DQ33 A 1 0 1 1 01 DQ2 2 1 02 1 02 DQ34 1 0 2 1 0 2 DQ3 w 1 03 DO 1 0 3 D8 DQ35 A 1 1 0 3 D1 1 0 3 D9 DQ4 A 3 1 0 4 1 04 DQ36 A 1 0 4 1 0 4 05 WW 1 05 1 05 DQ37 1 0 5 1 05 06 r 1 0 6 1 0 6 DQ38 w 1 0 6 1 0 6 DQ7 WW 1 07 1 0 7 DQ39 w 1 0 7 1 07 I I I 50 ODTO CKEO CS1 ODT1 CKE1 7CSO ODTO CKEO CS1 ODT1 DQS1 w DQS DQS DQS5 A 1 DQ DQS DQS1 1 DQS DQS DQS5 7N 5 DQS DM1 J DM DM DM5 A 3 DM DM DQ8 1 00 1 00 DQ40 A 1 1 0 0 1 00 DQ9 Wr 1 01 1 01 DQ41 A 3A 1 0 1 1 01 DQ10 w 1 0 2 1 02 DQ42 A 1 0 2 1 0 2 DQ11 A 4 1 0 3 D2 1 03 D10 DQ43 W 1 0 3 D3 1 0 3 D11 DQ12 A 1 0 4 1 04 DQ44 A 1 0 4 1 0 4 DQ13 A 34 1 05 5 DQ45 A 3 1 0 5 705 DQ14 r 1 0 6 1 06 DQ46 w 1 0 6 1 0 6 DQ15 A 1 0 7 1 07 DQ47 7 m 1 07 I b I I 50 ODTO CKEO 651 ODT1 CSO ODTO CKEO CS1 ODT1 CKE1 DQS2 JA 4 DQS DQS 56 1 DQS DQS DQS2 J DQS DQS DQS6 J 1 DQS DQS DM
15. 00 100 mA IDD3P S 48 48 48 mA IDD3N 180 200 220 mA IDDAW 620 800 920 mA IDD4R 620 740 860 mA IDD5B 640 660 680 mA IDD6 40 40 40 mA 1 IDD6 D 20 20 20 mA 1 IDD7 920 1040 1160 mA 1GB 128M x 64 SO DIMM HMP112S6EFR6C Nie DDR2 DDR2 eTO DDR2 Unit Mote IDDO 480 520 560 mA IDD1 580 620 660 mA IDD2P 80 80 80 mA IDD2Q 216 240 256 mA IDD2N 280 320 360 mA IDD3P F 200 200 200 mA IDD3P S 96 96 96 mA IDD3N 360 400 440 mA IDDAW 760 960 1100 mA IDD4R 760 900 1040 mA IDD5B 780 820 860 mA IDD6 80 80 80 mA 1 IDD6 D 40 40 40 mA 1 IDD7 1060 1200 1340 mA Notes 1 IDD6 current values are guaranteed up to Tcase of 85 C max Rev 0 3 Dec 2009 hynix 200pin Unbuffered DDR2 SDRAM SO DI MMs 2GB 256M x 64 SO DIMM HMP125S6EFR8C CA Y5 S5 S6 Symbol DDR2 533 CL4 DDR2 667 CL5 DDR2 800 cL5 amp 6 Unit Note IDDO 800 880 960 mA IDD1 880 960 1040 mA IDD2P 160 160 160 mA IDD2Q 432 480 512 mA IDD2N 560 640 720 mA IDD3P F 400 400 400 mA IDD3P S 192 192 192 mA IDD3N 720 800 880 mA IDDAW 1240 1480 1720 mA IDD4R 1240 1440 1640 mA IDD5B 1560 1640 1720 mA IDD6 160 160 160 mA 1 IDD6 L 80 80 80 mA 1 IDD7 1680 1880 2200 mA Notes 1 IDD6 current values are guaranteed up to Tcase of 85 C max Rev 0 3 Dec 2009 la yuix 200pin Unbuffered DDR2 SDRAM SO DI MMs IDD Measurement Conditions Symbol Conditions Un
16. 2 _ w DM DM DM6 A DM DM DQ16 A 1 0 0 1 00 DQ48 w 1 0 0 1 00 7 1 0 1 rm 1 01 DQ49 1 1 0 1 DQ18 A 2 1 0 2 1 02 DQ50 A 1 0 2 1 0 2 DQ19 A 1 0 3 D4 1 03 D12 DQ51 1 0 3 D5 1 0 3 D13 DQ20 w J 1 0 4 1 04 DQ52 A 1 0 4 1 0 4 DQ21 A 2 1 0 5 1 05 DQ53 A 1 0 5 m 1 05 DQ22 A 1 0 6 1 06 DQ54 A 1 1 0 6 1 06 DQ23 A 4 1 07 1 0 7 DQ55 1 0 7 CS0 ODTO CKEO CS1 ODT1 CKE1 1650 ODTO CKEO CS1 ODT1 53 DQS DQS DQS7 Das DQS DQS3 A ps DQs 57 N DQ5 r DQs DM3 A 1 DM DM DM7 w DM DM DQ24 A 1 0 0 1 00 DQ56 1 1 0 0 1 0 0 DQ25 A 1 0 1 HO DQ57 A 1 01 1 01 DQ26 A 3 1 0 2 1 02 DQ58 w 1 0 2 1 0 2 DQ27 A 1 0 3 D6 1 0 3 D14 DQ59 w 1 0 3 D7 1 0 3 D15 DQ28 A 1 0 4 1 0 4 DQ60 w 1 0 4 1 0 4 DQ29 A 34 1 0 5 1 05 DQ61 A 34 1 05 105 DQ30 w 1 0 6 1 0 6 DQ62 w 1 0 6 1 0 6 DQ31 A 4 1 0 7 1 07 DQ63 W 1 0 7 1 07 po mcm 1109 5 SCL SCL SDA 4 SDA _ gt SDRAMS D0 15 SAO
17. 2GB 256Mx64 16 2 Halogen free This document is a general product description and is subject to change without notice Hynix Semiconductor does not assume any responsibility for use of circuits described No patent licenses are implied Rev 0 3 Dec 2009 1 la VIX 200pin Unbuffered DDR2 SDRAM SO DI MMs SPEED GRADE amp KEY PARAMETERS C4 Y5 S6 S5 Unit DDR2 533 DDR2 667 DDR2 800 DDR2 800 Speed CL3 400 400 400 Mbps Speed CL4 533 533 533 533 Mbps Speed CL5 667 667 800 Mbps Speed CL6 800 Mbps CL tRCD tRP 4 4 4 5 5 5 6 6 6 5 5 9 tCK ADDRESS TABLE Density Organization Ranks SDRAMs eee of row bank column Address pili 512MB 64M x 64 1 64Mb x 16 4 13 A0 A12 3 BAO BA2 10 A0 A9 8 64ms 1GB 128M x 64 2 64Mb x 16 8 13 A0 A12 3 BA0 BA2 10 A0 A9 8K 64ms 2GB 256M x 64 2 128Mb x 8 16 14 A0 A13 3 BAO BA2 10 A0 A9 8K 64ms Rev 0 3 Dec 2009 2 hyuix PIN DESCRI PTI ON 200pin Unbuffered DDR2 SDRAM SO DI MMs Symbol Type Polarity Pin Description CK 1 0 CK 1 0 Input Cross Point The system clock inputs All address an commands lines are sampled on the cross point of the rising edge of CK and falling edge of CK A Delay Locked Loop DLL circuit is driven from the clock inputs and output timing for read operations is synchronized to the input clock
18. DM DM6 w LDM LDM DQ16 1 0 0 1 0 0 DQ48 1 0 0 1 0 0 DQ17 A 1 0 1 101 DQ49 Ww 1 0 1 mm 7 9 DQ18 A 1 0 2 1 0 2 DQ50 A 1 1 0 2 1 0 2 DQ19 w 1 0 3 1 0 3 DQ51 w 1 0 3 m 1 03 DQ20 w 1 0 4 1 0 4 DQ52 w 1 0 4 1 0 4 DQ21 A 23 1 0 5 1 0 5 DQ53 A 1 0 5 1125 22 w 1 0 6 1 0 6 DQ54 A 2 1 0 6 1 0 6 DQ23 A 1 0 7 1 0 7 DQ55 A 1 1 0 7 1 07 53 UDQS D1 UDQS D5 DQS7 _ww UDQS D3 H UDQS D7 DQS3 _____ rw UDQS UDQS DQS7 N JUDQS UDQS DM3 UDM UDM DM7 4 UDM UDM DQ24 WwW 8 108 DQ56 A 1 0 8 H 1 0 8 DQ25 A 1 0 9 1 09 DQ57 A 1 0 9 m 1 09 DQ26 A 41 1 0 10 1 0 10 DQ58 vw 1 0 10 1 0 10 DQ27 w 1 0 11 1 O 11 DQ59 A 1 0 11 uyo1i 28 1 0 12 1 0 12 DQ60 w 1 0 12 1 0 12 DQ29 w 1 0 13 1 0 13 DQ61 A 1 0 13 H 1 0 13 DQ30 w 1 0 14 1 0 14 DQ62 WW 1 0 14 1 0 14 1 0 15 1 O 15 DQ63 A 1 0 15 1 0 15 SCL SCL SDA 4P SDA pecca SA0 A0 139 4 5 1 Serial PD SA1 gt BAO BA2 JA SDRAMS D0 15 I 1 mP A2 WP AO AN Nr gt SDRAMS DO 15 RAS JA 34
19. IGH Viu DC VREF 0 125 VDDQ 0 3 V dc Input logic LOW Vi CDC 0 30 Veer 0 125 V INPUT AC LOGIC LEVEL DDR2 400 533 DDR2 667 800 Parameter Symbol Unit Min Max Min Max AC Input logic HIGH Viu AC VREF 0 250 VREF 0 200 AC Input logic LOW V4 AC 0 250 Vref 0 200 AC INPUT TEST CONDITIONS Symbol Condition Value Units Notes VREF Input reference voltage 0 5 Vppg V 1 VSWING MAX Input signal maximum peak to peak swing 1 0 V 1 SLEW Input signal minimum slew rate 1 0 V ns 2 3 Notes 1 Input waveform timing is referenced to the input signal crossing through the Vper level applied to the device under test 2 The input signal minimum slew rate is to be maintained over the range from to ViH ac min for rising edges and the range from Vper to Vii ac max for falling edges as shown in the below figure 3 AC timings are referenced with input waveforms switching from VIL ac to VIH ac on the positive transitions and VIH ac to VIL ac on the negative transitions Vppo Se ee min min VswNGMA 0 VREF GOD ERE ee ee EL ViL dc max DR n LR E LA NET ViL ac max Vss delta TF delta TR V V V min V REF VIL ac Max Rising Slew IH ac REF Falling Slew delta TF delta TR Figure AC Input Test
20. ceiver The actual current values are derived by shifting the desired driver operating point along a 21 ohm load line to define a convenient driver current for measurement Rev 0 3 Dec 2009 hyuix PIN Capacitance VDD 1 8V VDDQ 1 8V TA 25 512MB HMP164S6EFR6C 200pin Unbuffered DDR2 SDRAM SO DI MMs Pin Symbol Min Max Unit CK CK CCK 12 5 15 pF CKE ODT CS Cll 27 30 pF Address RAS CAS WE 6 2 25 32 pF DQ DM DQS DQS clo 6 7 5 pF 1GB HMP112S6EFR6C Pin Symbol Min Max Unit CK CK CCK 17 20 pF CKE ODT CS Cll 22 25 pF Address RAS CAS WE CI2 28 5 37 pF DQ DM DQS DQS CIO 10 12 pF 2GB HMP125S6EFR8C Pin Symbol Min Max Unit CK CK CCK 17 29 pF CKE ODT CS Cll 24 38 pF Address RAS CAS WE Cl2 31 56 pF DQ DM DQS DQS clo 7 12 pF Notes 1 Pins not under test are tied to GND 2 These value are guaranteed by design and tested on a sample basis only Rev 0 3 Dec 2009 hyuix 200pin Unbuffered DDR2 SDRAM SO DI MMs IDD SPECIFICATIONS Tease 0 to 95 C 512MB 64M x 64 SO DIMM HMP164S6EFR6C DDR2 A DDR2 DDR2 BERN Unnt Nore IDDO 340 360 380 mA IDDI 440 460 480 mA IDD2P 40 40 40 mA IDD2Q 108 120 128 mA IDD2N 140 160 180 mA IDD3P F 100 1
21. connected to Vpp o act as a pull up SCL Input This signals is used to clock data into and out of the SPD EEPROM A resistor may be connected from SCL to VDD to act as a pull up SA 1 0 Input Address pins used to select the Serial Presence Detect base address TEST In Out The TEST pin is reserved for bus analysis tools and is not connected on normal memory modules SODI MMs Rev 0 3 Dec 2009 la yuix 200pin Unbuffered DDR2 SDRAM SO DI MMs PIN ASSI GNMENT Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back Side NO Side NO Side NO Side NO Side NO Side NO Side NO Side 1 VREF 2 vss 51 DQS2 52 DM2 101 Al 102 0 151 DQ42 152 DQ46 VSS 4 DQ4 53 VSS 54 VSS 103 VDD 104 VDD 153 DQ43 154 DQ47 DQO 6 DQ5 55 DQ18 56 DQ22 105 A10 AP 106 BAI 155 VSS 156 VSS 8 57 DQ19 58 DQ23 107 BAO 108 RAS 157 DQ48 158 DQ52 VSS 10 DMO 59 VSS 60 vss 109 WE 110 S0 159 DQ49 160 DQ53 11 DQSO 12 vss 61 DQ24 62 DQ28 111 VDD 112 VDD 161 vss 162 vss 13 DQSO 14 DQ6 63 DQ25 64 DQ29 113 CAS 114 ODTO 163 NC TEST 164 CK1 15 VSS 16 DQ7 65 VSS 66 VSS 115 5 116 A13 165 VSS 166 CKl 17 DQ2 18 67 DM3 68 DQS3 117 VDD 118 VDD 167 DQS6
22. ctive power down to read command tXARD 2 2 tCK Exit Bele power down to read command tXARDS 6 AL 6 AL tCK Slow exit Lower power minimum pulse width high and low pulse width tCKE 4 3 Bes turn on delay tAOND 2 2 2 2 tCK ODT turn on tAON tAC min tAC min d e ns i tCK tCK t ODT turn on Power Down mode tAONPD tAC min 2 max 1 tAC min 2 max 1 ns IODT turn off delay tAOFD 2 5 2 5 2 5 2 5 tCK ODT turn off taoF tAC min 56 tac min fis ODT turn off Power Down mode tAOFPD tAC min 2 E PIAC tAC min 2 ns max 1 max 1 ODT to power down entry latency tANPD 3 3 tCK ODT power down exit latency tAXPD 8 8 tCK OCD drive mode output delay tOIT 0 12 0 12 ns Minimum time clocks remains ON after CKE tDela US tCK US tCK asynchronously drops LOW y EN t i us Average periodic Refresh Interval 39 39 T 3 Notes 1 For details and notes please refer to the relevant Hynix component datasheet HY5PS1G8 16 31CFP 2 0 C Tease lt 85 C 3 85 C lt Tease lt 95 C Rev 0 3 Dec 2009 17 hyuix 200pin Unbuffered DDR2 SDRAM SO DI MMs PATET Symbol DDR2 667 DDR2 800 Unit Note min max min max DQ output access time from CK CK tAC 450 450 400 400 ps DQS output access time from CK CK tDQSCK 400 400 350 350 ps CK high level wi
23. dth tCH 0 45 0 55 0 48 0 52 tCK CK low level width tCL 0 45 0 55 0 48 0 52 tCK CK half period tHP porn perg ps Clock cycle time CL x tCK 3000 8000 2500 8000 ps nei o ws i 50 i ues om om bi ae amp Address input pulse width for each 06 i 0 6 tCK DQ and DM input pulse width for each input tDIPW 0 35 0 35 tCK Data out high impedance time from CK CK tHZ tAC max tAC max ps DQS low impedance time from CK CK tLZ DQS tAC min tAC max tAC min tAC max ps DQ low impedance time from CK CK tLZ DQ 2 tAC min tAC max 2 tAC min tAC max ps iem skew for DQS and associated DQ ipasQ 240 240 ps DQ hold skew factor tQHS 5 340 300 ps DQ DQS output hold time from DQS tQH tHP tQHS tQHS ps transition to associated tDQSs 0 25 40 25 0 25 40 25 CK DQS input high pulse width tDQSH 0 35 0 35 tCK DQS input low pulse width tDQSL 0 35 0 35 tCK DQS falling edge to CK setup time tDSS 0 2 0 2 tCK DQS falling edge hold time from CK tDSH 0 2 0 2 tCK Mode register set command cycle time tMRD 2 2 tCK Write preamble tWPRE 0 35 0 35 tCK Write postamble tWPST 0 4 0 6 0 4 0 6 tCK Address and control input setup time tIS 200 175 ps Address and control input hold time tIH 275 250 ps Read preamble tRPRE 0 9 1 1 0 9 1 1 tCK Read postamble tRPST 0 4 0 6 0 4 0 6 tCK Activate to precharge command tRAS 45 70000 45 70000 ns Row Active to Row Active Delay for 1KB page size tRRD 7 5 7 5
24. ed If AP is low autoprecharge is disabled During a Precharge command cycle AP is used in conjunction with BAO BAn to control which bank s to precharge If AP is high all banks will be precharged regardless of the state of BAO BAn inputs If AP is low then BAO BAn are used to define which bank to precharge DQ 63 0 In Out Data Input Output pins DM 7 0 Input Active High The data write masks associated with one data byte In Write mode DM operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high In Read mode DM lines have no effect DQS 7 0 DQS 7 0 In Out Cross point The data strobe associated with one data byte sourced whit data transfers In Write mode the data strobe is sourced by the controller and is centered in the data window In Read mode the data strobe is sourced by the DDR2 SDRAMs and is sent at leading edge of the data window DQS signals are complements and timing is relative to the crosspoint of respective DQS and DQS If the module is to be operated in single ended strobe mode all DQS signals must be tied on the system board to VSS and DDR2 SDRAM mode registers programmed approriately VppSPD Vss Supply Power supplies for core I O Serial Presense Detect and ground for the module SDA In Out This is a bidirectional pin used to transfer data into or out of the SPD EEPROM A resister must be
25. hyuix 200pin Unbuffered DDR2 SDRAM SO DI MMs based on 1Gb version This Hynix unbuffered Small Outline Dual In Line Memory Module DIMM series consists of 1Gb version E DDR2 SDRAMs in Fine Ball Grid Array FBGA packages on a 200pin glass epoxy substrate This Hynix 1Gb version E based Unbuffered DDR2 SO DIMM series provide a high performance 8 byte interface in 67 60mm width form factor of indus try standard It is suitable for easy interchange and addition FEATURES e JEDEC standard Double Data Rate 2 Synchronous e Programmable Burst Length 4 8 with both DRAMs DDR2 SDRAMs with 1 8V 0 1V Power sequential and interleave mode Supply Auto refresh and self refresh supported e All inputs and outputs are compatible with SSTL 1 8 8192 refresh cycles 64ms interface Serial presence detect with EEPROM Posted CAS e DDR2 SDRAM Package 60 ball x8 84 ball x16 Programmable CAS Latency 3 4 5 and 6 FBGA OCD Off Chip Driver Impedance Adjustment and ODT On Die Termination 67 60 x 30 00 mm form factor E e RoHS compliant Halogen free Fully differential clock operations CK amp CK This product is in compliance with the directive pertaining of RoHS ORDERI NG I NFORMATI ON of of Part Name Density Organization DRAMs ranks Materials HMP164S6EFR6C C4 Y5 S5 S6 512MB 64Mx64 4 1 Halogen free HMP112S6EFR6C C4 Y5 S5 S6 1GB 128Mx64 8 2 Halogen free HMP125S6EFR8C C4 Y5 S5 S6
26. inputs are SWITCHING Operating burst write current All banks open Continuous burst writes BL 4 CL CL IDD AL 0 CK IDDAW tCK IDD RAS tRASmax IDD tRP tRP IDD CKE is HIGH CS is HIGH between valid commands mA Address bus inputs are SWITCHING Data bus inputs are SWITCHING Operating burst read current All banks open Continuous burst reads IOUT OmA BL 4 CL CL IDD IDD4R AL 0 tCK tCK IDD RAS tRASmax IDD tRP tRP IDD CKE is HIGH CS is HIGH between valid com mA mands Address bus inputs are SWITCHING Data pattern is same as IDDAW Burst refresh current CK tCK IDD Refresh command at every tRFC IDD interval is HIGH CS is IDD5B HIGH between valid commands Other control and address bus inputs are SWITCHING Data bus inputs are mA SWITCHING IDD6 Self refresh current CK and CK at CKE lt 0 2V Other control and address bus inputs are FLOATING Data bus inputs are FLOATING IDD6 current values are guaranted up to Tcase of 85 C max mA Operating bank interleave read current All bank interleaving reads IOUT OmA BL 4 CL CL IDD IDD7 AL tRCD IDD 1 tCK IDD tcK tCK IDD tRC tRC IDD tRRD tRRD IDD tRCD 1 tCK IDD CKE is mA HIGH CS is HIGH between valid commands Address bus inputs are STABLE during DESELECTS Data pattern is same as IDDAR Refer to the following page for detailed timing conditions Notes 1 IDD specificat
27. ions are tested after the device is properly initialized 2 Input slew rate is specified by AC Parametric Test Condition 3 IDD parameters are specified with ODT disabled 4 Data bus consists of DQ DM DQS DOS RDQS RDQS LDQS LDQS UDQS and UDQS IDD values must be met with all combina tions of EMRS bits 10 and 11 5 Definitions for IDD LOW is defined as Vin VILAC max HIGH is defined as Vin VIHAC min STABLE is defined as inputs stable at a HIGH or LOW level FLOATING is defined as inputs at VREF VDDQ 2 SWITCHING is defined as inputs changing between HIGH and LOW every other clock cycle once per two clocks for address and control signals and inputs changing between HIGH and LOW every other data transfer once per clock for DQ signals not including masks or strobes Rev 0 3 Dec 2009 15 hynix 200pin Unbuffered DDR2 SDRAM SO DI MMs Electrical Characteristics amp AC Timings Speed Bins and CL tRCD tRP tRC and tRAS for Corresponding Bin Speed DDR2 800 S5 DDR2 800 S6 DDR2 667 Y5 DDR2 533 C4 Unit Bin CL tRCD tRP 5 5 5 6 6 6 5 5 5 4 4 4 Parameter min min min min CAS Latency 5 6 5 4 tCK tRCD 12 5 15 15 15 ns tRP 12 5 15 15 15 ns tRAS 45 45 45 45 ns tRC 57 5 60 60 60 ns AC Timing Parameters by Speed Grade DDR2 400 DDR2 533 Parame
28. its Operating one bank active precharge current tCK tCK IDD tRC tRC IDD RAS tRASmin IDDO IDD CKE is HIGH CS is HIGH between valid commands Address bus inputs are SWITCHING Data bus inputs mA are SWITCHING Operating one bank active read precharge current OUT 0mA BL 4 CL CL IDD AL 0 IDD1 tCK tCK IDD tRC tRC IDD tRAS tRASmin IDD RCD tRCD IDD is HIGH CS is HIGH mA between valid commands Address bus inputs are SWITCHING Data pattern is same as IDDAW IDD2P Precharge power down current All banks idle tCK tCK IDD CKE is LOW Other control and address bus mA inputs are STABLE Data bus inputs are FLOATING 1DD2Q Precharge quiet standby current All banks idle CK tCK IDD CKE is HIGH CS is HIGH Other control MA and address bus inputs are STABLE Data bus inputs are FLOATING IDD2N Precharge standby current All banks idle tCK tCK IDD CKE is HIGH CS is HIGH Other control and mi address bus inputs are SWITCHING Data bus inputs are SWITCHING Active power down current All banks open tCK tCK IDD CKE is LOW Fast PDN Exit MRS 12 0 mA IDD3P Other control and address bus inputs are STABLE Data bus inputs are FLOAT ING Slow PDN Exit MRS 12 1 mA Active standby current All banks open CK tCK IDD RAS tRASmax IDD tRP tRP IDD is I DD3N HIGH CS is HIGH between valid commands Other control and address bus inputs are SWITCHING Data bus mA
29. nal operation at or above the conditions indicated is not implied Exposure to absolute maximum rating con ditions for extended periods may affect reliability 2 Up to 9850 ft 3 If the DRAM case temperature is Above 850C the Auto Refresh command interval has to be reduced to tREFI 23 9us For Measurement conditions of TCASE please refer to the JEDEC document J ESD51 2 DC OPERATING CONDITIONS ssr 1 8 Rating Symbol Parameter Units Notes Min Typ Max VDDQ Supply Voltage for Output 1 7 1 8 1 9 1 2 VREF Input Reference Voltage 0 49 VDDQ 0 50 VDDQ 0 51 VDDQ mV 3 4 VTT Termination Voltage VREF 0 04 VREF VREF 0 04 V 5 VDDSPD EEPROM Supply Voltage 1 8 3 3 Note 1 Min Typ and Max values increase by 100mV for C3 DDR2 533 3 3 3 speed option 2 VDDQ tracks with VDD VDDL tracks with VDD AC parameters are measured with VDD VDDQ and VDD 3 The value of VREF may be selected by the user to provide optimum noise margin in the system Typically the value of VREF is expected to be about 0 5 x VDDQ of the transmitting device and VREF is expected to track varia tions in VDDQ 4 Peak to peak ac noise on VREF may not exceed 2 VREF dc 5 VIT of transmitting device must track VREF of receiving device Rev 0 3 Dec 2009 8 la 200pin Unbuffered DDR2 SDRAM SO DI MMs INPUT DC LOGIC LEVEL Parameter Symbol Min Max Unit Note dc Input logic H
30. ns to Row Active Delay for 2KB IRRD 10 10 i T a Window for 1KB page size tFAW 375 35 A fe a Window for 2KB page size tFAW 50 i 45 n Rev 0 3 Dec 2009 18 hyuix 200pin Unbuffered DDR2 SDRAM SO DI MMs continued Symbol DDR2 667 DDR2 800 Unit Note min max min max CAS to CAS command delay tCCD 2 2 tCK Write recovery time tWR 15 15 ns Aut h it h u o precharge write recovery precharge tDAL WR tRP WR tRP tCK time Internal write to read command delay tWTR 7 5 7 5 ns Internal read to precharge command delay tRTP 7 5 7 5 ns Exit self refresh to a non read command tXSNR tRFC 10 tRFC 10 ns Exit self refresh to a read command tXSRD 200 200 tCK Exit h d t xit precharge power down to any non UP 2 2 tCK read command Exit active power down to read command tXARD 2 2 tCK Exit acti d t d d xit ac ds power down to read comman EXARDS JAL 8 AL tCK Slow exit Lower power CKE minimum pulse width high and low pulse width ICKE 3 3 rh ODT turn on delay tAOND 2 2 2 2 tCK ODT turn on tAON tAC min tAC max 0 7 tAC min tAC max 0 7 ns 2tCK 2tCK ODT turn on Power Down mode tAONPD tAC min 2 tAC max 1 tAC min 2 tAC max 1 ns ODT turn off delay tAOFD 2 5 2 5 2 5 2 5 tCK ODT turn off taor tAC mi AC TAH tAC min C T ns 2 5tCK 2 5tCK ODT turn off Power D
31. own mode tAOFPD tAC min 2 tAC max 1 tAC min 2 tAC max 1 ns ODT to power down entry latency tANPD 3 3 tCK ODT power down exit latency tAXPD 8 8 tCK OCD drive mode output delay tolT 0 12 0 12 ns Minimum time clocks remains ON after CKE Delay tis tCK i uS tCK 7 j asynchronously drops LOW tREFI 7 8 7 8 2 Average periodic Refresh Interval ia tREFI 3 9 3 9 us 3 Notes 1 For details and notes please refer to the relevant Hynix component datasheet HY5PS1G8 16 31CFP 2 0 C Tease lt 85 C 3 85 C lt TcasE lt 95 C Rev 0 3 Dec 2009 19 la Vix 200pin Unbuffered DDR2 SDRAM SO DI MMs PACKAGE OUTLI NE 64Mx64 HMP164S6EFR6C Front 67 60 2 00 Min x 4 00 0 10 a y 9 ooog 5 m OOOO 8 O Detail B Detail A lv amp PIN 1 PIN PIN 41 PIN 199 wv vw 2 15 11 40 gt T 1 80 0 1 47 40 o 8 4 20 S DE Back Detail B 3 8MAX 2 45 11 40 47 40 El d 4 so xo PIN 2 PIN 40 PIN42 PIN 200 3 1 00 0 10 Detail of Contacts A Detail of Contacts B Front Detail of Contacts B Back 0 45 0 03 4 20 2 70 040 1 50 a a a 4 H o un o N A ni R y 0 60
32. ter Symbol Unit Note Min Max Min Max Data Out edge to Clock edge Skew tAC 600 600 500 500 ps DQS Out edge to Clock edge Skew tDQSCK 500 500 450 450 ns Clock High Level Width tCH 0 45 0 55 0 45 0 55 CK Clock Low Level Width tCL 0 45 0 55 0 45 0 55 CK min min Clock Half Period tHP tCL tCH tCL tCH ns System Clock Cycle Time tCK 5000 8000 3750 8000 ps DQ and DM input setup time tDS 150 100 1 DQ and DM input hold time tDH 275 225 5 1 DQ and DM input setup time single ended strobe tDS1 25 25 ps 1 DQ and DM input hold time single ended strobe tDH1 25 25 ps 1 Control Address input Pulse Width for each input 0 6 0 6 tCK DQ and DM nput pulse width for each input pulse tDIPW 0 35 3 0 35 tCK width for each input Data out high impedance window from CK CK tHZ tAC max tAC max ps DQS low impedance time from CK CK tLZ DQS tAC min tAC max tAC min tAC max ps DQ low impedance time from CK CK tLZ DQ 2 tAC min tAC max 2 tAC min tAC max ps DQS DQ skew for DQS and associated DQ signals tDQSQ 350 300 ps DQ hold skew factor tQHS 450 400 ps DQ DQS output hold time from DQS tOH tHP tQHS tHP tQHS ps First DQS latching transition to associated clock tDQSS 0 25 10 25 0 25 0 25 tCK edge DQS input high pulse width tDQSH 0 35 0 35 tCK DQS input low pulse width tDQSL 0 35 0 35 tCK DQS falling edge to CK setup time tDSS 0 2 0 2 tCK DQS falling edge hold time from CK tDSH 0 2
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