Transcend Transcend TS4GHR72V1C memory module
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1. SDRAMs D 18 11 A 17 0 QAA 17 0 gt A 17 0 SDRAMs D 10 1 DOSe t DOS17 t QBA 17 0 gt A 17 0 SDRAMs D 18 11 p mtd ACT n QAACT_n gt ACT n SDRAMs D 10 1 QBACT_n gt ACT n SDRAMs D 18 11 PARITY QAPAR gt PAR SDRAMs D 10 1 QBPAR gt PAR SDRAMs D 18 11 Vopspp y Serial PD CKEO R QACKEO gt CKE SDRAMs D 10 1 E QBCKEO gt CKE SDRAMs D 18 11 Vpp D1 D18 G 1 Voo D1 D18 opto B QAODTO gt ODT SDRAMs D 10 1 QBODTO gt ODT SDRAMs D 18 11 Vit E R V D1 D18 nero CS0 n QACSO n CS n SDRAMs D 10 1 Vss D1 D18 QBCSO n CS n SDRAMs D 18 11 SA2 SA1 Cko t YO t CK t SDRAMs D 18 11 iie Y1_t gt CK t SDRAMs D 10 1 CK0 c YO c gt CK c SDRAMs D 18 11 Scb cit Y1 c CK c SDRAMs D 10 1 SDA CK1_c Samal PD wih RESET n QRST n gt RESET n All SDRAMs eria witi i Thermal sensor Register ALERT_n ERROR IN n gt ALERT n All SDRAMs NOTE 1 Unless otherwise noted resistor values are 15Q 596 2 See the Net Structure diagrams for all resistors associated with the command address and control bus 3 ZQ resistors are 2400 1 For all other resistor values refer to the appropriate wiring diagram and the Transcend logo ar demari en uct offerings and specifications are subject to change iut notice All oth es company names and h re trademarks of their n T Transcend good memories start here www transcend info com Block Diagram 16GB 2Gx72 Modu2. tCK tCK IDD tRC tRC IDD tRAS tRASmin IDD CKE is HIGH CS is HIGH between valid commands Address bus inputs are SWITCHING Data bus inputs are SWITCHING IDDO 1280 mA Operating One bank Active read Precharge current IOUT 0mA BL 8 CL CL IDD AL 0 tCK tCK IDD tRC tRC IDD tRAS tRASmin IDD tRCD tRCD IDD CKE is HIGH CS is HIGH between valid commands Address bus inputs are SWITCHING Data pattern is same as IDDAW IDD1 1450 mA Precharge power down current All banks idle tCK tCK IDD CKE is LOW Other control and address bus inputs are STABLE Data bus inputs are FLOATING IDD2P 500 mA Precharge quiet standby current All banks idle tCK tCK IDD CKE is HIGH CS is HIGH Other control and address bus inputs are STABLE Data bus inputs are FLOATING IDD2Q 1020 mA Precharge standby current All banks idle tCK tCK IDD CKE is HIGH CS is HIGH Other control and address bus inputs are SWITCHING Data bus inputs are SWITCHING IDD2N 1040 mA Active power down current All banks open tCK tCK IDD CKE is LOW Other control and address bus inputs are STABLE Data bus inputs are FLOATING Active standby current All banks open tCK tCK IDD tRAS tRASmax IDD tRP tRP IDD CKE is HIGH CS is HIGH between valid commands Other control and address bus inputs are SWITCHING Data bus inputs are SWITCHING IDD3P IDD3N 570 121
3. IDD2N 1370 mA Active power down current All banks open tCK tCK IDD CKE is LOW Other control and address bus inputs are STABLE Data bus inputs are FLOATING Active standby current All banks open tCK tCK IDD tRAS tRASmax IDD tRP tRP IDD CKE is HIGH CS is HIGH between valid commands Other control and address bus inputs are SWITCHING Data bus inputs are SWITCHING IDD3P IDD3N 870 1540 mA mA Operating burst read current All banks open Continuous burst reads IOUT OMA BL 4 CL CL IDD AL 0 tCK tCK IDD tRAS tRASmax IDD tRP tRP IDD CKE is HIGH CS is HIGH between valid commands Address bus inputs are SWITCHING Data pattern is same as IDD4W IDD4R 2580 mA Operating burst write current All banks open Continuous burst writes BL 8 CL CL IDD AL 0 tCK tCK IDD tRAS tRASmax IDD tRP tRP IDD CKE is HIGH CS is HIGH between valid commands Address bus inputs are SWITCHING Data bus inputs are SWITCHING IDD4R IDD4W 2380 mA Burst refresh current tCK tCK IDD Refresh command at every tRFC IDD interval CKE is HIGH CS is HIGH between valid commands Other control and address bus inputs are SWITCHING Data bus inputs are SWITCHING IDD5 3810 mA Self refresh current CK and CK at OV CKE 0 2V Other control and address bus inputs are FLOATING Data bus inputs are FLOATING IDD6 500 mA Operating bank i
4. VDDQ V AC output high measurement level VOH AC 0 7 0 15 x VDDQ V 1 AC output low measurement level VOL AC 0 7 0 15 x VDDQ V 1 Note 2 The swing of 0 15 x VDDQ is based on approximately 50 of the static single ended output peak to peak j swing with a driver impedance of RZQ 7O and an effective test load of 50Q to VTT VDDQ Differential AC amp DC output levels Parameter Symbol DDR4 1600 1866 2133 Unit Note AC differential output high measurement level AC differential output low measurement level Note 2 The swing of 0 3 x VDDQ is based on approximately 50 of the static differential output peak to peak swing with a driver impedance of RZQ 7O and an effective test load of 500 to VTT VDDQ at each of the differential outputs VOHdiff AC 0 3 x VDDQ V 1 VOLdiff AC 0 3 x VDDQ vi 4 All rights reserved Transcend and the Transcend logo are registered trademarks of Transcend Information Inc Product offerings and specifications are subject to change without notice All other products brand names company names and logos are trad T Transcend good memories start here www transcend info com IDD Specification parameters Definition IDD values are for full operating range of Voltage and Temperature 16GB 2Gx72 Module 2 Rank x4 Parameter Symbol DDR4 2133 CL15 Unit Operating One bank Active Precharge current tCK tCK IDD tRC tRC IDD t
5. and register e Clock Freq 1067MHZ for 2133Mb s Pin 12C slave address select for ee SPD TS and register e Programmable CAS Latency 10 11 12 13 14 15 16 g Register parity input e Programmable Additive Latency Posted CAS VDD SDRAM core power supply 0 CL 2 or CL 1 clock VREFCA SDRAM command address l reference supply e Programmable CAS Write Latency CWL Power supply return ground 11 14 DDR4 2133 VDDSPD pa SPD TS positive power Supply e 8 bit pre fetch ALERT_n Register ALERT_n output e Burst Length 4 8 VPP SDRAM activating power supply RR RESET n Set Register and SDRAMs to a e Bi directional Differential Data Strobe P Known State e On Die Termination with ODT pin T Transcend good memories start here www transcend info com EVENT n SPD signals a thermal event has NC No Connection T occurred SDRAM I O termination supply Reserved for future use Dimensions Unit millimeter Mox 3 90 1 40 0 10 I p 24 28 E 2939 35 TT 22 95 8 00 0 60 0 03 0 85 diram Detail B Pin116 Pin104 T Transcend good memories start here www transcend info com Note 1 Tolerances on all dimensions 0 15mm unless otherwise specified All rights reserved Transcend and the Transcend logo are registered trademarks of Transcend Information Inc Product offerings and specifications are subject to change without n
6. low measurement level VOL DC 0 5 x VDDQ V AC output high measurement level VOH AC 0 7 0 15 x VDDQ V 1 AC output low measurement level VOL AC 0 7 0 15 x VDDQ V 1 Note 1 The swing of 0 15 x VDDQ is based on approximately 5096 of the static single ended output peak to peak j swing with a driver impedance of RZQ 7Q and an effective test load of 500 to VTT VDDQ Differential AC amp DC output levels Parameter Symbol DDR4 1600 1866 2133 Unit Note AC differential output high measurement level AC differential output low measurement level Note 1 The swing of 0 3 x VDDQ is based on approximately 50 of the static differential output peak to peak swing with a driver impedance of RZQ 7O and an effective test load of 500 to VTT VDDQ at each of the differential outputs VOHdiff AC 0 3 x VDDQ V 1 VOLdiff AC 0 3 x VDDQ vi 4 All rights reserved Transcend and the Transcend logo are registered trademarks of Transcend Information Inc Product offerings and specifications are subject to change without notice All other products brand names company names and logos are trad T Transcend good memories start here www transcend info com IDD Specification parameters Definition IDD values are for full operating range of Voltage and Temperature 8GB 1Gx72 Module 1 Rank x4 Parameter Symbol DDR4 2133 CL15 Unit Operating One bank Active Precharge current
7. to DQ loading capacitor nscend Information Inc Product offerings and specifications are subject to change without notice All other products brand names company names and logos ar T Transcend good memories start here www transcend info com Timing Parameters amp Specifications Speed DDR4 2133 Unit Parameter Symbol Min Max Average Clock Period tCK 0 938 lt 1 071 ns CK high level width tCH 0 48 0 52 tCK CK low level width tCL 0 48 0 52 tCK DQS t DQS c to DQ skew per group per paso TBD ICK 2 access DQS tDQS c to DQ Skew determin istic iDosQ TBD ICK 2 per group per access DQ output hold time from DOS t DQS c tQH TBD tCK 2 DQ output hold time deterministic from DQS t DQS c to DQ Skew total per group g per access DBI enabled tDQSQ TER Ul DQ output hold time total from DQS t DQS c DBI enabled tQH TBD Ul DQ to DQ offset per group per ac cess referenced to DQS t DQS c tDQSQ TBD Ul DQS t DQS c differential READ Pre amble 2 clock preamble BERE TER indi DQS t DQS c differential READ Postamble tRPST TBD tCK DQS t DQS c differential WRITE Preamble tWPRE tCK DQS t DQS c differential WRITE Postamble tWPST TBD tCK DQS t and DQS c low impedance time Referenced from RL 1 IARU 16u ps DQS t and DQS c high impedance time Referenced from RL BL 2 tHZ DQS bud ps pe DQS c differential input low pulse tDQSL 0 54 CK in DQS c d
8. 0 mA mA Operating burst read current All banks open Continuous burst reads IOUT OMA BL 4 CL CL IDD AL 0 tCK tCK IDD tRAS tRASmax IDD tRP tRP IDD CKE is HIGH CS is HIGH between valid commands Address bus inputs are SWITCHING Data pattern is same as IDD4W IDD4R 2240 mA Operating burst write current All banks open Continuous burst writes BL 8 CL CL IDD AL 0 tCK tCK IDD tRAS tRASmax IDD tRP tRP IDD CKE is HIGH CS is HIGH between valid commands Address bus inputs are SWITCHING Data bus inputs are SWITCHING IDD4R IDD4W 2050 mA Burst refresh current tCK tCK IDD Refresh command at every tRFC IDD interval CKE is HIGH CS is HIGH between valid commands Other control and address bus inputs are SWITCHING Data bus inputs are SWITCHING IDD5 3480 mA Self refresh current CK and CK at OV CKE 0 2V Other control and address bus inputs are FLOATING Data bus inputs are FLOATING IDD6 260 mA Operating bank interleave read current All bank interleaving reads IOUT OmA BL 8 CL CL IDD AL tRCD IDD 1 tCK IDD tCK tCK IDD Tre tRC IDD tRRD tRRD IDD tRCD 1 tCK IDD CKE is HIGH CS is HIGH between valid commands Address bus inputs are STABLE during DESELECTs Data pattern is same as IDD4R IDD7 3240 mA Note 1 Module IDD was calculated on the specific brand DRAM 2Xnm component IDD and can
9. Height 18 75mm 04 129 Module Maximum Thickness Planar Double Sides 11 130 Reference Raw Card Used Revision 0 Raw card J 08 131 DIMM Module Attributes 1 Row 1 Register 05 132 RDIMM Thermal Heat Spreader Solution Not incorporated 00 133 134 Register Manufacturer ID Code By Manufacturer Variable 135 Register Revision Number By Manufacturer Variable 136 X Address Mapping from Register to DRAM Not Mirrored 00 Moderate Drive 137 Register Output Drive Strength for Control Chip Select ODT GRE 65 Strong Drive Command Address 138 Register Output Drive Strength for CK Moderate Drive 05 139 253 Reserved 00 254 255 Cyclical Redundancy Code CRC a 256 319 Reserved 00 320 321 Module Manufacturer ID Code s 322 Module Manufacturing Location E 323 324 Module Manufacturing Date 325 328 Module Serial Number 329 348 Module Part Number 349 Module Revision Code 00 350 351 DRAM Manufacturer ID Code By Manufacturer Variable 352 DRAM Stepping 00 353 381 Manufacturer Specific Data By Manufacturer Variable 382 383 Reserved 00 384 551 End User Programmable s
10. Latency Time tAAmin 00 124 Fine Offset for SDRAM Maximum Cycle Time i 00 tCKAVGmax 125 Fine Offset for SDRAM Minimum Cycle Time i C2 tCKAVGmin 126 127 Cyclical Redundancy Code 128 Raw Card Extension Module Nominal Height 31 25mm 11 129 Module Maximum Thickness Planar Double Sides 11 130 Reference Raw Card Used Revision 0 Raw card A 00 131 DIMM Module Attributes 2 Row 1 Register 09 132 RDIMM Thermal Heat Spreader Solution Not incorporated 00 133 134 Register Manufacturer ID Code By Manufacturer Variable 135 Register Revision Number By Manufacturer Variable 136 X Address Mapping from Register to DRAM Mirrored 01 Moderate Drive 137 Register Output Drive Strength for Control uhr dau DT one 65 Strong Drive Command Address 138 Register Output Drive Strength for CK Moderate Drive 05 139 253 Reserved 00 254 255 Cyclical Redundancy Code CRC 256 319 Reserved 00 320 321 Module Manufacturer ID Code 322 Module Manufacturing Location 323 324 Module Manufacturing Date 325 328 Module Serial Number 329 348 Module Part Number 349 Module Revision Code 00 350 351 DRAM Manufacturer ID Code By Manufacturer Variable 352 DRAM Stepping 00 353 381 Manufacturer Specific Data By Manufacturer Variable 382 383 Reserved 00 384 551 End User Programmable s T Transcend good memories start here www transcend info com DDR4 e Serial presence detect with EEPRO
11. M TS2GHR72V1 PL e On DIMM Thermal e Asynchronous reset 288Pin DDR4 2133 VLP RDIMM E Pot Pin Identification Funcio Description DDR4 VLP Registered DIMM is high speed low power Register column address strobe memory module that use 2Gx4bits DDR4 SDRAM in dem me FBGA package and a 4Kbits serial EEPROM ona WEn Register write enable input 288 pin printed circuit board DDR4 VLP Registered roh ae DIMM Rank Select Lines input DIMM is a Dual In Line Memory Module and is intended CKEO CKE1 Register clock enable lines input for mounting into 288 pin edge connector sockets ODTO ODT1 aie e CEU NON GONE Synchronous design allows precise cycle control with the Register input for activate input DQ0 Q63 DIMM memory data bus use of system clock Data I O transactions are possible CBO B7 DIMM ECC check bits th ed f DOS R f tion f ies on both edges of DQ ange of operation ieee DQSO t DQS17 t er per d m programmable latencies allow the same device to be l l l l DOSO c DQS17 c Data Buffer data strobes useful for a variety of high bandwidth high performance negative line of differential pair TOR Register clock input positive line of i system applications CKO t CK1 t differential pair eatures i i ive li e RoHS compliant products ie al of afferential pai a Hd SCL I2C serial bus clock for SPD TS e JEDEC standard 1 2V 0 06V power supply and register e VDDQ 1 2V 0 06V SDA 12C serial bus data line for SPD TS
12. MM ECC check bits useful for a variety of high bandwidth high performance memory system applications CK0 c CK1 c Features e RoHS compliant products e JEDEC standard 1 2V 0 06V power supply I2C slave address select for e VDDQ 1 2V 0 06V MADSOAS SPD TS and register PAR Register parity input Clock Freq 1067MHZ for 2133Mb s Pin dies CK m ud VDD SDRAM core power supply e Programmable CAS Latency 10 11 12 13 14 15 16 VREFCA SDRAM command address e Programmable Additive Latency Posted CAS reference supply CL DA SS Power supply return ground TT NC S S V 0 CL 2 or CL 1 clock VDDSPD de SPD TS positive power e Programmable CAS Write Latency CWL supp ALERT_n Register ALERT n output 11 14 DDR4 2133 VPP SDRAM activating power supply e 8 bit pre fetch RESET n aA and SDRAMs to a Burst Langit Arg EVENT n SPD signals a thermal event has e Bi directional Differential Data Strobe occurred V DRAM O termination supply e On Die Termination with ODT pin RFU Reserved for future use e Serial presence detect with EEPROM rk ut notice All other products brand names company names and logos are trademarks of their respective owners Transcend good memories start here www transcend info com 64 60 32 68 235 35 d a Detail C Note 1 Tolerances on all dimensions 0 15mm unless otherwise specified T Transcend good memories s
13. PL Serial Presence Detect Byte No Function Described Standard Specification Vendor Part 0 Number of Bytes Used Number of Bytes in SPD E LE t 23 Device CRC Coverage Me USS ye SPD Byte total 512Byte 1 SPD Revision 2 Key Byte DRAM Device Type DDR4 SDRAM 0C 3 Key Byte Module Type RDIMM 01 4 SDRAM Density and Banks 4Gb 16banks 84 5 SDRAM Addressing ROW 16 Column 10 21 6 SDRAM Package Type DDP 91 7 SDRAM Optional Features 8 SDRAM Thermal and Refresh Options 9 Other SDRAM Optional Features 10 Reserved 00 11 Module Nominal Voltage VDD 1 2V 03 12 Module Organization 2Rank 4bits 08 13 Module Memory Bus Width ECC 72bits 0B 14 Module Thermal Sensor Support 80 15 16 Reserved 00 17 Timebases 00 18 SDRAM Minimum Cycle Time tCKAVGmin 0 938ns 08 19 SDRAM Maximum Cycle Time tCKAVGmax 1 5ns 0C 20 23 CAS Latencies Supported 10 11 12 13 14 15 16 24 Minimum CAS Latency Time tAAmin 13 75ns 6E 25 Minimum RAS to CAS Delay Time tRCDmin 13 75ns 6E 26 Minimum Row Precharge Delay Time tRPmin 13 75ns 6E 27 Upper Nibbles for tRASmin and tRCmin 11 28 Minimum Active to Precharge Delay Time tRASmin 33ns 08 Least Significant Byte Minimum Active to Active Refresh Delay Time ES tRCmin Least Significant Byte Serong d 30 31 Minimum Refresh Recovery Delay Time tRFC1min 260ns 20 08 32 33 Minim
14. QABG 1 0 gt BG 1 0 SDRAMs D 20 1 QBBG 1 0 gt BG 1 0 SDRAMs D 36 21 BA 1 0 QABA 1 0 gt BA 1 0 SDRAMs D 20 1 QBBA 1 0 gt BA 1 0 SDRAMs D 36 21 A 17 0 QAA 17 0 gt A 17 0 SDRAMs D 20 1 QBA 17 0 gt A 17 0 SDRAMs D 36 21 ACT n QAACT n gt ACT n SDRAMs D 20 1 QBACT_n gt ACT n SDRAMs D 36 21 C 2 0 QAC 2 0 gt C 2 0 SDRAMs D 20 1 QBC 2 0 gt C 2 0 SDRAMs D 36 21 PARITY QAPAR gt PAR SDRAMs D 20 1 QBPAR gt PAR SDRAMs D 36 21 CKEO R QACKEO gt CKE SDRAMs D 10 1 E QBCKEO gt CKE SDRAMs D 28 21 CKE1 G QACKE1 gt CKE SDRAMs D 20 11 l QBCKE1 gt CKE SDRAMs D 36 29 ODTO QAODTO gt ODT SDRAMs D 10 1 E QBODTO gt ODT SDRAMs D 28 21 ODT1 R QAODT1 gt ODT SDRAMs D 20 11 QBODT1 gt ODT SDRAMs D 36 29 cso_n QACSO n gt CS n SDRAMs D 10 1 QBCS0_n gt CS n SDRAMs D 28 21 CS1n QACS1_n gt CS n SDRAMs D 20 11 QBCS1_n gt CS n SDRAMs D 36 29 CKO t YO t CK t SDRAMs D 24 21 D 32 29 Y1_t gt CK t SDRAMs D 5 1 D 15 11 Y2 t CK t SDRAMs D 28 25 D 36 33 Y3_t gt CK t SDRAMs D 10 6 D 20 16 CK0 c YO_c gt CK c SDRAMs D 24 21 D 32 29 dai Y1_ gt CK c SDRAMs D 5 1 D 15 11 i Y2 c gt CK c SDRAMs D 28 25 D 36 33 cac Y3_c gt CK c SDRAMs D 10 6 D 20 16 RESET n QRST_n gt RESET n All SDRAMs ALERT n ERROR IN n ALERT n All SDRAMs This technical information is based on indust
15. RAM Stepping 00 353 381 Manufacturer Specific Data By Manufacturer Variable 382 383 Reserved 00 T Transcend good memories start here www transcend info com 384 551 End User Programmable s TS2GHR72V1Z Serial Presence Detect Byte No Function Described Standard Specification Vendor Part 0 Number of Bytes Used Number of Bytes in SPD Se aie 24 Device CRC Coverage SPD Byte total 512Byte 1 SPD Revision 2 Key Byte DRAM Device Type DDR4 SDRAM 0C 3 Key Byte Module Type RDIMM 01 4 SDRAM Density and Banks 4Gb 16banks 84 5 SDRAM Addressing ROW 16 Column 10 21 6 SDRAM Package Type 7 SDRAM Optional Features 8 SDRAM Thermal and Refresh Options z 9 Other SDRAM Optional Features z 10 Reserved 00 11 Module Nominal Voltage VDD 1 2V 03 12 Module Organization 2Rank 4bits 08 13 Module Memory Bus Width ECC 72bits 0B 14 Module Thermal Sensor Support 80 15 16 Reserved 00 17 Timebases 00 18 SDRAM Minimum Cycle Time tCKAVGmin 0 938ns 08 19 SDRAM Maximum Cycle Time tCKAVGmax 1 5ns 0C 20 23 CAS Latencies Supported 10 11 12 13 14 15 16 24 Minimum CAS Latency Time tAAmin 13 75ns 6E 25 Minimum RAS to CAS Delay Time tRCDmin 13 75ns 6E 26 Minimum Row Precharge Delay Time tRPmin 13 75ns 6E 27 Upper Nibbles for tRASmin and tRCmin 11 28 Minim
16. RAS tRASmin IDD CKE is HIGH CS is HIGH between valid commands Address bus inputs are SWITCHING Data bus inputs are SWITCHING IDDO 1600 mA Operating One bank Active read Precharge current IOUT 0mA BL 8 CL CL IDD AL 0 tCK tCK IDD tRC tRC IDD tRAS tRASmin IDD tRCD tRCD IDD CKE is HIGH CS is HIGH between valid commands Address bus inputs are SWITCHING Data pattern is same as IDDAW IDD1 1780 mA Precharge power down current All banks idle tCK tCK IDD CKE is LOW Other control and address bus inputs are STABLE Data bus inputs are FLOATING IDD2P 720 mA Precharge quiet standby current All banks idle tCK tCK IDD CKE is HIGH CS is HIGH Other control and address bus inputs are STABLE Data bus inputs are FLOATING IDD2Q 1310 mA Precharge standby current All banks idle tCK tCK IDD CKE is HIGH CS is HIGH Other control and address bus inputs are SWITCHING Data bus inputs are SWITCHING IDD2N 1370 mA Active power down current All banks open tCK tCK IDD CKE is LOW Other control and address bus inputs are STABLE Data bus inputs are FLOATING Active standby current All banks open tCK tCK IDD tRAS tRASmax IDD tRP tRP IDD CKE is HIGH CS is HIGH between valid commands Other control and address bus inputs are SWITCHING Data bus inputs are SWITCHING IDD3P IDD3N 870 1540 mA mA Operating burst
17. REFCA to deviate from VREFCA DC by more than 196 j VDD for reference approx 12mV 4 For reference approx VDD 2 12mV All rights reserved Transcend and the Transcend logo are registered trademarks of Transcend Information Inc Product offerings and specifications are subject to change without notice All other products brand names company names and logos are trademarks of their respective owners T Transcend good memories start here www transcend info com Differential AC and DC Input Levels DDR4 1600 1866 2133 Parameter Symbol Unit Note Min Max differential input high DC VIHdiff DC 40 150 NOTE 3 V 1 differential input low DC VILdiff DC NOTE 3 0 150 V 1 differential input high AC VIHdiff AC 2 x VIH AC VREF NOTE 3 V 2 differential input low AC VILdiff AC NOTE 3 2 x VIL AC VREF V 2 Note 4 Usedto define a differential signal slew rate 5 for CK t CK_c use VIH CA VIL CA AC of ADD CMD and VREFCA 6 These values are not defined however the differential signals CK t CK c need to be within the respective limits VIH CA DC max VIL CA DC min for single ended signals as well as the limitations for overshoot and undershoot Single ended AC amp DC output levels Parameter Symbol DDR4 1600 1866 2133 Unit Note DC output high measurement level VOH DC 1 1 x VDDQ V DC output mid measurement level VOM DC 0 8 x VDDQ V DC output low measurement level VOL DC 0 5 x
18. S 69 A6 105 VSS 141 SCL 177 DQ23 213 A5 249 DQ35 285 SDA 34 DQ18 70 VDD 106 DQ44 142 VPP 178 VSS 214 A4 250 VSS 286 VPP 35 VSS 71 A3 107 VSS 143 VPP 179 DQ19 215 VDD 251 DQ45 287 VPP 36 DQ28 72 Al 108 DQ40 144 RFU 180 VSS 216 A2 252 VSS 288 VPP Note 1 VPP is 2 5V DC 2 Pin 230 is defined as NC for UDIMMs RDIMMs and LRDIMMs Pin 230 is defined as SAVE_n for NVDIMMs 3 Pins 1 and 145 are defined as NC for UDIMMs RDIMMs and LRDIMMs Pins 1 and 145 are defined as 12V for Hybrid NVDIMM 4 The 5th VPP is required on all modules DIMMs All rights reserved Transcend and the Transcend logo are registered trademarks of Transcend Information Inc Product offerings and specifications are subject to change without notice All other products brand names company names and logos are trademarks of their respective owners T Transcend good memories start here www transcend info com Block Diagram 16GB 2Gx72 Module 2 Rank CS1A n ODT1A CKE1A CS0A n ODTOA CKEOA pase_t DQS9_c DQ 7 4 3 pas10t z DQS10 c DQ 15 12 DQS41 t DQS11_c DQ 23 20 2 DOS12 t DQS12 c DQ 31 28 DQS17 t DOSS t DQS17 c DQS8 c CB 74 CB 3 0 x4 CS1B n ODT1B CKE1B CSOB n ODTOB CKEOB DOSA4 t DQS4 c DQ 35 32 pass t DQS5 c DQ 43 40 DQ 51 48 DOS7 t DQS7 c DQ 59 56 CS1A n ODT1A CKE1A CS0A n ODTOA CKEOA paso_t DQSO0 c DQ 3 0 DQS1 t DQS c DQ 11 8 DQS2 t DQS2_
19. SS 71 A3 107 VSS 143 VPP 179 DQ19 215 VDD 251 DQ45 287 VPP 36 DQ28 72 Al 108 DQ40 144 RFU 180 VSS 216 A2 252 VSS 288 VPP Note 1 VPP is 2 5V DC 2 Pin 230 is defined as NC for UDIMMs RDIMMs and LRDIMMs Pin 230 is defined as SAVE_n for NVDIMMs 3 Pins 1 and 145 are defined as NC for UDIMMs RDIMMs and LRDIMMs Pins 1 and 145 are defined as 12V for Hybrid NVDIMM 4 The 5th VPP is required on all modules DIMMs All rights reserved Transcend and the Transcend logo are registered trademarks of Transcend Information Inc Product offerings and specifications are subject to change without notice All other products brand names company names and logos are trademarks of their respective owners T Transcend good memories start here www transcend info com Block Diagram 8GB 1Gx72 Module 1 Rank x4 QACSO n QBCSO n QAODTO a QBODTO QACKEO i QBCKEO o 2 DQSO t pas4t Basi3t DQSO c DQSA c DQS13 c DQ 33 DQ 35 32 DQ 39 36 a 2 DOS t past0 t DQS5 t Bas14t DQS1_c DQS10 c DQS5 c DQS14 c DQ 11 8 DQ 15 12 DQ 43 40 DQJ47 44 2 Das2 t pase Basis t DQS2 c DQS6 c DQS15 c Da 19 1 DQ 51 48 DQ 55 52 3 3 pas3_t pas12 t pasz fase t DQS3 c DQS12 c DOS c DQS16 c DQ 27 24 DQ 31 28 DQ 59 56 DQ 63 60 BG 1 0 QABG 1 0 gt BG 1 0 SDRAMs D 10 1 QBBG 1 0 gt BG 1 0 SDRAMs D 18 11 BA 1 0 QABA 1 0 gt BA 1 0 SDRAMs D 10 1 A QBBA 1 0 gt BA 1 0
20. T Transcend good memories start here www transcend info com DDR4 e On DIMM Thermal Sensor TS1GHR72V1Z Pin Identification Symbol Function TS2GHR72V12 288Pin DDR4 2133 RDIMM 8GB 16GB Based on 1Gx4 Register column address strobe input Description CS0 n C81 n DDR4 Registered DIMM is high speed low power cS2n csa n DIMM Rank Select Lines input memory module that use 1Gx4bits DDR4 SDRAM in CKEO CKE1 Register clock enable lines input ODTO ODT1 Register on die termination control FBGA package and a 4Kbits serial EEPROM on a lines input 288 pin printed circuit board DDR4 Registered DIMM is a ACT n Register input for activate input DQ0 Q63 DIMM memory data bus mounting into 288 pin edge connector sockets TDQSO9 t TDQS17 t Dummy loads for mixed populations TDQS9 c TDQS17 c Jof x4 based and x8 based RDIMMs Synchronous design allows precise cycle control with the l l DOSO t DQS17 t Data Buffer data strobes use of system clock Data I O transactions are possible A positive line of differential pair Data Buffer data strobes on both edges of DQS Range of operation frequencies DQSO c DQS17 c negative line of differential pair programmable latencies allow the same device to be Register clock input positive line of CKO t CK1 t differential pair Register clocks input negative line of differential pair and register and register Dual In Line Memory Module and is intended for CBO B7 DI
21. be differently measured according to DQ loading capacitor nscend Information Inc Product offerings and specifications are subject to change without notice All other products brand names company names and logos ar T Transcend good memories start here 16GB 2Gx72 Module 2 Rank x4 www transcend info com Parameter Symbol DDR4 2133 CL15 Unit Operating One bank Active Precharge current tCK tCK IDD tRC tRC IDD tRAS tRASmin IDD CKE is HIGH CS is HIGH between valid commands Address bus inputs are SWITCHING Data bus inputs are SWITCHING IDDO 1600 mA Operating One bank Active read Precharge current IOUT 0mA BL 8 CL CL IDD AL 0 tCK tCK IDD tRC tRC IDD tRAS tRASmin IDD tRCD tRCD IDD CKE is HIGH CS is HIGH between valid commands Address bus inputs are SWITCHING Data pattern is same as IDDAW IDD1 1780 mA Precharge power down current All banks idle tCK tCK IDD CKE is LOW Other control and address bus inputs are STABLE Data bus inputs are FLOATING IDD2P 720 mA Precharge quiet standby current All banks idle tCK tCK IDD CKE is HIGH CS is HIGH Other control and address bus inputs are STABLE Data bus inputs are FLOATING IDD2Q 1310 mA Precharge standby current All banks idle tCK tCK IDD CKE is HIGH CS is HIGH Other control and address bus inputs are SWITCHING Data bus inputs are SWITCHING
22. c DQ 19 16 DOS3 t DQS3 c DQ 27 24 CS1B n ODTiB CKE1B CSOB_n ODTOB CKEOB DQS13 t DQS13 c DQ 39 36 DQS14 t DQS14 c DQJ47 44 pasist DQS15 c DQ 52 55 DOS16 t DQS16 c DQ 63 60 8G t 0 BG 1 0JA gt BG 1 0 SDRAMS D 4 0 D 17 13 V BG 1 0 B gt BG 1 0 SDRAMs DIB 5 D 12 9 UDSFD sp Seno BA 1 0 BA 1 0JA gt BA t 0 SDRAMs D 4 0 D 17 13 Vpo DO D17 BA 1 0 B gt BA 1 0 SDRAMs D amp 5 D 12 9 A TT 0 ALTT OA gt A 17 0 SDRAMs D 4 0 D 17 13 Voo D0 D17 A 17 0 8 gt A 17 0 SDRAMs D 8 5 D 12 9 Vn PARITY ACT n PARA gt PAR ACT n SDRAMs D 4 0 D 17 13 PARB gt PAR ACT n SDRAMs D 8 5 D 12 9 VRERCA DO D17 CKEO CKE1 CKEOA gt CKE SDRAMs D 4 0 D 17 13 Vss D0 D17 CKEOB gt CKE SDRAMs D 8 5 D 12 9 ODTO ODT ODTOA gt ODT SDRAMs D 4 0 D 17 13 ODTOB gt ODT SORAMs D 8 5 D 12 9 SA2 CS0 n CS1 n CSOA n CS n SDRAMs D 4 0 D 17 13 ES CSOB_n gt CS n SDRAMs D 8 5 D 12 9 SAO CKO t a YO _t _c gt CKO t c SDRAMs D 8 5 D 12 9 SCL CK0 c YALE c gt CKIC t c SDRAMs DJ4 0 D 17 13 SDA ckt t CKi c Serial PD with Thermal sensor RESET n ORESET n All SDRAMs NOTE 1 Unless otherwise noted resistor values are 15Q 5 2 See the Net Structure diagrams for all resistors associated with the command address and control bus 3 ZQ resistors are 2409 1 For all other resistor values refer to the appro
23. g 88 VOD t24 DQ54 t160 vss M96 Dass 232 A13 268 vss 17 vss ss vss ee sin 125 vss tei Das 97 pose 233 vob 2e9 Dass 18 DS 54 cBe jooj vod M26 Daso fisa vss 198 vss ex4 A evo vss 19 2992 s5 vss jaj oomi jizz vss 163 past c M99 cB7 e35 Noce 271 Dos 20 VSS 56 CB2 92 VDD 128 DQ60 164 DQS1 t 200 VSS 236 VDD 272 VSS 21 DQ14 57 VSS 93 C0 CS2 n NC 129 VSS 165 VSS 201 CB3 237 NC CS3 c C1 273 DQ61 22 VSS 58 RESET n 94 VSS 130 DQ56 166 DQ15 202 VSS 238 SA2 274 VSS 23 DQ10 59 VDD 95 DQ36 131 VSS 167 VSS 208 CKE1 239 VSS 275 DQ57 24 vss eo ckEo ee vss t32 OSS49 168 pati 204 voo 240 Das7_ 276 vss 25 pazo et vod ez pasz t3 Dose ieo vss 205 RFU 241 vss 277 DQS7_c 26 vss 62 AcTn 98 vss isal vss i70 Daet 206 vob 242 Dass 278 DaS7t 27 pate e3 Bao fog TS 3t ia5 poe 171 vss 207 Bat 243 vss 279 vss DQS13 t 28 vss e4 vod jroo DGS2 t36 vss tz2 DQ17 208 ALERT n 244 Das4 c 280 Does 29 DOS I5 65 A12 BC n M01 VSS 137 Dass tz3 vss 209 voo 245 DOS4t 8 vss so DOS Jee A9 tw2 pass fiss vss tz4 Das2 c 210 ait 246 vss es2 Dose 31 VSS 67 VDD 103 VSS 139 SAO 175 DQS2 t 211 A7 247 DQ39 283 VSS 32 DQ22 68 A8 104 DQ34 140 SA1 176 VSS 212 VDD 248 VSS 284 VDDSPD 33 VSS 69 A6 105 VSS 141 SCL 177 DQ23 213 A5 249 DQ35 285 SDA 34 DQ18 70 VDD 106 DQ44 142 VPP 178 VSS 214 A4 250 VSS 286 VPP 35 V
24. ifferential input high pulse tDQSH 0 54 CK DQS t DQS c rising edge to CK t CK c rising edge 1 clock preamble tDQSS 0 27 tek DQS t DQS c falling edge setup time to CK t CK c rising edge tDSS tCK DQS t DQS c falling edge hold time from i CK t CK c rising edge DSH tCK Delay from start of internal write trans action to internal read command for different bank tWTR_S Max 2nCK 2 5ns group Delay from start of internal write trans action to internal read command for same bank tWTR_L Max 4nCK 7 5ns group WRITE recovery time tWR 15 ns Mode Register Set command cycle time tMRD 8 nCK nscend Information Inc Product offerings and specifications are su T Transcend good memories start here www transcend info com Speed DDR4 2133 Unit Parameter Symbol Min Max CAS_n to CAS_n command delay for same bank group tCCD_L 6 nCK CAS n to CAS n command delay for different bank group tCCD_S nCK Auto precharge write recovery precharge uns s IDAL tWR RP tCK nCK ACTIVATE to ACTIVATE Command delay to different bank group for 2KB page size BAD ee Max 4nCk 5 3ns Jen ACTIVATE to ACTIVATE Command delay to different bank group for 1KB page size tBBD Se MARANGA NS IS ACTIVATE to ACTIVATE Command delay to tRRD S different bank group for 1 2KB page size 1 2K Max AnCaS S ns g HU ACTIVATE to ACTIVATE Command delay to same bank group for 2KB page si
25. imum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect reliability 2 Storage Temperature is the case surface temperature on the center top side of the DRAM For the measurement conditions please refer to JESD51 2 standard 3 VPP must be equal or greater than VDD VDDQ at all times AC amp DC Operating Conditions Recommended DC operating conditions Rating Parameter Symbol Unit Notes Min Typ Max Supply voltage VDD 1 14 1 2 1 26 V 1 2 Supply voltage for Output VDDQ 1 14 1 2 1 26 V 12 Wordline supply voltage VPP 2 375 2 5 2 75 V 3 Note 1 Under all conditions VDDQ must be less than or equal to VDD 2 VDDQ tracks with VDD AC parameters are measured with VDD and VDDQ tied together 3 DC bandwidth is limited to 20MHz Single ended AC amp DC input levels for Command and Address DDR4 1600 1866 2133 Parameter Symbol Unit Note Min Max I O Reference Voltage CMD ADD VREFCA DC 0 49 VDDQ 0 51 VDDQ V 12 DC Input Logic High VIH DC VREF 0 075 VDD V DC Input Logic Low VIL DC VSS VREF 0 075 V AC Input Logic High VIH AC VREF 0 1 Note 1 V AC Input Logic Low VIL AC Note 1 VREF 0 1 V Note 1 The AC
26. le 2 Rank x4 QACSO n QAODTO QACKEO QACS1 n QAODT1 QACKE1 2 DQSO t a DQS0 c DQ 3 0 2 post pasto t DQS1_c DQS10_c DQ 11 8 L ba DQ 15 12 1 DQS2 t x DQS11_t DQS2 c DQS11 c DQ 19 16 7 DQ 23 20 8 DOS3 t pasi2 t z DQS3 c DQS12 c DQ 27 24 DQ 31 28 2 gt DQS8 t jd 7 DQS17 t DQS8 c x DQS17_c CB 3 0 j CB 7 4 SA2 Vopsep d Serial PD SA1 Vpp D1 D36 SA0 Vop D1 D36 SAO SA1 SA2 SCL scL vm SDA SDA V D1 D36 vss REFCA Serial PD with Register Vss D1 D36 Thermal sensor NOTE 1 Unless otherwise noted resistor values are 159 5 2 See the Net Structure diagrams for all resistors associated with the command address and control bus 3 ZQ resistors are 2409 1 For all other resistor values refer to the appropriate wiring diagram All rights reserved Transcend and the Transcend logo are ademarks c scend Information Inc Product ecifications are subject to change without notice All other produc es company names and logos are trademarks of their resp T Transcend good memories start here www transcend info com QBCS0_n QBODTO QBCKEO QBCS1 n QBODT1 QBCKE1 7 pas4_t gt pasta t DQS4 c T DQS13 c DQ 35 32 7 DQ 39 36 e 2 2 asst Das 4 t DQS5 c DQS14 c DQ 43 40 DQ 47 44 8 pas _t pasis t 5 DQS6 c DQS15 c DQ 51 48 DQ 55 52 3 DOS t gt paste t gt DOS c DQS16 c DQ 59 56 T DQ 63 60 BG 1 0
27. mage to the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect reliability 5 Storage Temperature is the case surface temperature on the center top side of the DRAM For the measurement conditions please refer to JESD51 2 standard 6 VPP must be equal or greater than VDD VDDQ at all times AC amp DC Operating Conditions Recommended DC operating conditions Rating Parameter Symbol Unit Notes Min Typ Max Supply voltage VDD 1 14 1 2 1 26 V 1 2 Supply voltage for Output VDDQ 1 14 1 2 1 26 V 12 Wordline supply voltage VPP 2 375 2 5 2 75 V 3 Note 4 Under all conditions VDDQ must be less than or equal to VDD 5 VDDQ tracks with VDD AC parameters are measured with VDD and VDDQ tied together 6 DC bandwidth is limited to 20MHz Single ended AC amp DC input levels for Command and Address DDR4 1600 1866 2133 Parameter Symbol Unit Note Min Max I O Reference Voltage CMD ADD VREFCA DC 0 49 VDDQ 0 51 VDDQ V 12 DC Input Logic High VIH DC VREF 0 075 VDD V DC Input Logic Low VIL DC VSS VREF 0 075 V AC Input Logic High VIH AC VREF 0 1 Note 1 V AC Input Logic Low VIL AC Note 1 VREF 0 1 V Note 3 The AC peak noise on VREFCA may not allow V
28. n tWR RP tCK nCK ACTIVATE to ACTIVATE Command delay to different bank group for 2KB page size AD ee Max 4nCk 5 3ns i is ACTIVATE to ACTIVATE Command delay to different bank group for 1KB page size IRRD SUB Max AnGiS 9 fn ne ACTIVATE to ACTIVATE Command delay to tRRD_S different bank group for 1 2KB page size 1 2K Max nGn s 8 g RGI ACTIVATE to ACTIVATE Command delay to same bank group for 2KB page size RRD HAR Max Ane 8 408 HER ACTIVATE to ACTIVATE Command delay to same bank group for 1KB page size as Max 4nCK 5 3ns nek ACTIVATE to ACTIVATE Command delay to tRRD_L same bank group for 1 2KB page size 1 2K Max 4nCK 5 3ns nok Four activate window for 2KB page size tFAW_2K Max 28nCK 30ns ns Four activate window for 1KB page size tFAW_1K Max 20nCK 21ns ns Four activate window for 1 2KB page size tFAW_1 2K Max 16nCK 15ns ns Power up and RESET calibration time tZQinit 1024 F nCK Normal operation Full calibration time tZQoper 512 i nCK Normal operation short calibration time tZQCS 128 nCK Exit Self Refresh to commands not re quiring a locked DLL tXS tRFC min 10ns Exit Self Refresh to commands requir ing a locked DLL tXSDLL tDLLK min Internal READ Command to PRE CHARGE tRTP Command delay Max 4nCK 7 5ns Minimum CKE low width for Self re fresh tCKESR tCKE min 1nCK f entry to exit timing Exit Power Down with DLL on to any valid command Exit Precharge Power Down with XP DLL froze
29. n to commands not requiring a Max 4nCK 6ns s locked DLL CKE minimum pulse width tCKE Max 3nCK 5ns Asynchronous RTT turn on delay Power Down with DLL frozen ONAS ae a0 ns Asynchronous RTT turn off delay Power Down with DLL frozen 1AOFAS 19 29 ns RTT dynamic change skew tADC 0 3 0 7 tCK nscend Information Inc Product offerings and specification Transcend T good memories start here SERIAL PRESENCE DETECT SPECIFICATION www transcend info com TS1GHR72V1Z Serial Presence Detect Byte No Function Described Standard Specification Vendor Part 0 Number of Bytes Used Number of Bytes in SPD ee t 24 Device CRC Coverage yis uade ye SPD Byte total 512Byte 1 SPD Revision 2 Key Byte DRAM Device Type DDR4 SDRAM 0C 3 Key Byte Module Type RDIMM 01 4 SDRAM Density and Banks 4Gb 16banks 84 5 SDRAM Addressing ROW 16 Column 10 21 6 SDRAM Package Type E 7 SDRAM Optional Features S 8 SDRAM Thermal and Refresh Options 9 Other SDRAM Optional Features 10 Reserved 00 11 Module Nominal Voltage VDD 1 2V 03 12 Module Organization 1Rank 4bits 00 13 Module Memory Bus Width ECC 72bits 0B 14 Module Thermal Sensor Support 80 15 16 Reserved 00 17 Timebases 00 18 SDRAM Minimum Cycle Time tCKAVGmin 0 938ns 08 19 SDRAM Maximum Cycle Time tCKAVGmax 1 5ns 0C 20 23 CAS Latencies Su
30. nterleave read current All bank interleaving reads IOUT OmA BL 8 CL CL IDD AL tRCD IDD 1 tCK IDD tCK tCK IDD Tre tRC IDD tRRD tRRD IDD tRCD 1 tCK IDD CKE is HIGH CS is HIGH between valid commands Address bus inputs are STABLE during DESELECTs Data pattern is same as IDD4R IDD7 3580 mA Note 1 Module IDD was calculated on the specific brand DRAM 2Xnm component IDD and can be differently measured according to DQ loading capacitor nscend Information Inc Product offerings and specifications are subject to change without notice All other products brand names company names and logos ar T Transcend good memories start here Timing Parameters amp Specifications www transcend info com group Max 4nCK 7 5ns Speed DDR4 2133 Unit Parameter Symbol Min Max Average Clock Period tCK 0 938 1 071 ns CK high level width tCH 0 48 0 52 tCK CK low level width tCL 0 48 0 52 tCK DQS t DQS c to DQ skew per group per iposQ g TBD tCK 2 access DQS_t DQS_c to DQ Skew determin istic iDosQ TBD ICK 2 per group per access DQ output hold time from DOS t DQS c tQH TBD tCK 2 DQ output hold time deterministic from DQS t DQS c to DQ Skew total per group per access DBI enabled tDQSQ TER Ul DQ output hold time total from DQS t DQS c DBI enabled tQH TBD Ul DQ to DQ offset per group per ac cess refe
31. otice All other products brand names company names and logos are trademarks of their re T Transcend good memories start here www transcend info com Pin Assignments Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin No Name No Name No Name No Name No Name No Name No Name No Name 1 12V5NC 37 VSS 73 VDD 109 VSS 145 12V5 NC 181 DQ29 217 VDD 253 DQ41 vss 38 pae4 74 ckot 110 TOS 4 146 vREFCA 182 vss J218 ckit 254 vss 2 DQS14 t TDQS14 c 3 pas s9 vss 75 CckKoc 111 GSES vss 183 Daes 219 CKi_c 255 possc 4 vss 4o e 76 vbD i 2 vss 148 Das is4 vss eo vob 256 bass t 5 Doo a O57 77 vir faj Dase fisa vss 185 Dass 221 vrr 257 vss e vss 42 vss 78 EVENTn na vss 150 Dat ise DaQS3t 222 PARITY 258 _DQ47 7 BSS 43 Daso 79 Aao t5 Do42 151 vss 187 vss 223 VDD 259 vss s bose a4 vss eo vob 116 vss M52 Doso c 188 Dos 2e4 Bai 260 Daas 9 vss Dae sr BAO m7 Dose 153 Dasot 19 vss 225 Aio AP 261 VSS 10 DQ6 46 VSS 82 RAS_n A16 118 VSS 154 VSS 190 DQ27 _ 226 VDD 262 DQ53 11 VSS 47 CB4 83 VDD 119 DQ48 155 DQ7 191 VSS 227 RFU 263 VSS 12 DQ2 48 VSS 84 SO_n 120 VSS 156 VSS 192 CB5 228 WE n A14 264 DQ49 13 vss 49 CBO 85 VDD 121 IDG815 t 157 pas 193 vss 229 vod ees vss DQS15 t 14 DQi2 s0 vss 86 CAS mAi5 122 Cele Jase vss fioa cB 230 Nc j
32. peak noise on VREFCA may not allow VREFCA to deviate from VREFCA DC by more than 1 j VDD for reference approx 12mV 2 For reference approx VDD 2 12mV All rights reserved Transcend and the Transcend logo are registered trademarks of Transcend Information Inc Product offerings and specifications are subject to change without notice All other products brand names company names and logos are trademarks of their respective owners T Transcend good memories start here www transcend info com Differential AC and DC Input Levels DDR4 1600 1866 2133 Parameter Symbol Unit Note Min Max differential input high DC VIHdiff DC 40 150 NOTE 3 V 1 differential input low DC VILdiff DC NOTE 3 0 150 V 1 differential input high AC VIHdiff AC 2 x VIH AC VREF NOTE 3 V 2 differential input low AC VILdiff AC NOTE 3 2 x VIL AC VREF V 2 Note 1 Used to define a differential signal slew rate 2 for CK t CK_c use VIH CA VIL CA AC of ADD CMD and VREFCA 3 These values are not defined however the differential signals CK_t CK_c need to be within the respective limits VIH CA DC max VIL CA DC min for single ended signals as well as the limitations for overshoot and undershoot Single ended AC amp DC output levels Parameter Symbol DDR4 1600 1866 2133 Unit Note DC output high measurement level VOH DC 1 1 x VDDQ V DC output mid measurement level VOM DC 0 8 x VDDQ V DC output
33. pported 10 11 12 13 14 15 16 24 Minimum CAS Latency Time tAAmin 13 75ns 6E 25 Minimum RAS to CAS Delay Time tRCDmin 13 75ns 6E 26 Minimum Row Precharge Delay Time tRPmin 13 75ns 6E 27 Upper Nibbles for tRASmin and tRCmin 11 28 Minimum Active to Precharge Delay Time tRASmin 33ns 08 Least Significant Byte Minimum Active to Active Refresh Delay Time e tRCmin Least Significant Byte i Arana Ze 30 31 Minimum Refresh Recovery Delay Time tRFC1min 260ns 20 08 32 33 _ Minimum Refresh Recovery Delay Time tRFC2min 160ns 00 05 34 85 Minimum Refresh Recovery Delay Time tRFC4min 110ns 70 03 Minimum Four Activate Window Delay Time 36 37 aWmin y 15ns 00 78 Minimum Activate to Activate Delay Time 399 tRRD Smin different bank group ds is Minimum Activate to Activate Delay Time 33 tRRD_Lmin same bank group Balls e 40 Minimum CAS to CAS Delay Time tCCD Lmin 5 625ns 2E T Transcend good memories start here www transcend info com same bank group 41 59 Reserved 00 60 77 Connector to SDRAM Bit Mapping 78 116 Reserved 00 117 Fine Offset for Minimum CAS to CAS Delay Time 83 tCCD Lmin same bank group 118 Fine Offset for Minimum Activate to Activate Delay B5 Time tRRD_Lmin same bank group 119 Fine Offset for Minimum Activate to Activate Delay CE Time tRRD Smin differen
34. priate wiring diagram This technical information is based on industry standard data and tests believed to be reliable However Transcend makes no warranties either expressed or implied as to its accuracy and assume no liability in connection with the use of this product Transcend reserves the right to make changes in specifications at any time without prior notice and specifications are subject to change without notice All other prc All rights n od Transcend and the Transcend logo are re T Transcend good memories start here www transcend info com Operating Temperature Condition Parameter Symbol Rating Unit Note Operating Temperature TOPER 0t085 C 1 2 Note 3 Operating Temperature is the case surface temperature on the center top side of the DRAM For the measurement conditions please refer to JESD51 2 standard 4 AtO0 85 C operation temperature range are the temperature which all DRAM specification will be supported Absolute Maximum DC Ratings Parameter Symbol Value Unit Note Voltage on VDD relative to Vss VDD 0 3 1 5 V 1 Voltage on VDDQ pin relative to Vss VDDQ 0 3 1 5 V Voltage on VPP pin relative to Vss VPP 0 3 3 0 V 3 Voltage on any pin relative to Vss VIN VOUT 0 3 1 5 V 1 Storage temperature TsTG 55 100 C 1 2 Note 4 Stress greater than those listed under Absolute Maximum Ratings may cause permanent da
35. read current All banks open Continuous burst reads IOUT OmA BL 4 CL CL IDD AL 0 tCK tCK IDD tRAS tRASmax IDD tRP tRP IDD CKE is HIGH CS is HIGH between valid commands Address bus inputs are SWITCHING Data pattern is same as IDD4W IDD4R 2580 mA Operating burst write current All banks open Continuous burst writes BL 8 CL CL IDD AL 0 tCK tCK IDD tRAS tRASmax IDD tRP tRP IDD CKE is HIGH CS is HIGH between valid commands Address bus inputs are SWITCHING Data bus inputs are SWITCHING IDD4R IDD4W 2380 mA Burst refresh current tCK tCK IDD Refresh command at every tRFC IDD interval CKE is HIGH CS is HIGH between valid commands Other control and address bus inputs are SWITCHING Data bus inputs are SWITCHING IDD5 3810 mA Self refresh current CK and CK at OV CKE 0 2V Other control and address bus inputs are FLOATING Data bus inputs are FLOATING IDD6 500 mA Operating bank interleave read current All bank interleaving reads IOUT OmA BL 8 CL CL IDD AL tRCD IDD 1 tCK IDD tCK tCK IDD Tre tRC IDD tRRD tRRD IDD tRCD 1 tCK IDD CKE is HIGH CS is HIGH between valid commands Address bus inputs are STABLE during DESELECTs Data pattern is same as IDD4R IDD7 3580 mA Note 1 Module IDD was calculated on the specific brand DRAM 2Xnm component IDD and can be differently measured according
36. renced to DQS t DQS c tDQSQ TBD Ul DQS t DQS c differential READ Pre amble 2 clock preamble IRENE Tep IGK DQS t DQS c differential READ Postamble tRPST TBD tCK DQS t DQS c differential WRITE Preamble tWPRE tCK DQS t DQS c differential WRITE Postamble tWPST TBD tCK DQS_t and DQS_c low impedance time Referenced from RL 1 tLZ DQs i ps DQS_t and DQS_c high impedance time Referenced from RL BL 2 tHZ DQS Ten ps Sls DQS c differential input low pulse tDQSL 0 54 CK c DQS c differential input high pulse iDQSH 0 54 CK DQS t DQS c rising edge to CK t CK c rising edge 1 clock preamble tDQSS 0 27 IG DQS t DQS c falling edge setup time to g CK t CK_c rising edge tDSS tCK DQS t DQS c falling edge hold time from i CK t CK c rising edge DSH tCK Delay from start of internal write trans action to internal read command for different bank tWTR_S Max 2nCK 2 5ns group Delay from start of internal write trans action to internal read command for same bank IWTR L T Transcend good memories start here www transcend info com WRITE recovery time tWR 15 ns Mode Register Set command cycle time tMRD 8 nCK Speed DDR4 2133 Unit Parameter Symbol Min Max CAS_n to CAS_n command delay for same bank group ICCD L i i nCK CAS_n to CAS_n command delay for different bank group tCCD_S i d nCK Auto precharge write recovery precharge as die add ii
37. ry standard data and tests believed to be reliable However Transcend makes no warranties either expressed or implied as to its accuracy and assume no liability in connection with the use of this product Transcend reserves the right to make changes in specifications at any time without prior notice All rights reserved Transcend and the Transcend logo are ademarksc scend Information Inc Product offerings and specifications are subject to change without notice All other products es company names and logos are trademarks of their resp T Transcend good memories start here www transcend info com Operating Temperature Condition Parameter Symbol Rating Unit Note Operating Temperature TOPER 0t085 C 1 2 Note 1 Operating Temperature is the case surface temperature on the center top side of the DRAM For the measurement conditions please refer to JESD51 2 standard 2 At0 85 C operation temperature range are the temperature which all DRAM specification will be supported Absolute Maximum DC Ratings Parameter Symbol Value Unit Note Voltage on VDD relative to Vss VDD 0 3 1 5 V 1 Voltage on VDDQ pin relative to Vss VDDQ 0 3 1 5 V Voltage on VPP pin relative to Vss VPP 0 3 3 0 V 3 Voltage on any pin relative to Vss VIN VOUT 0 3 1 5 V 1 Storage temperature TSTG 55 100 C 1 2 Note 1 Stress greater than those listed under Absolute Max
38. t bank group 120 Fine Offset for Minimum Active to Active Refresh 00 Delay Time tRCmin 121 Fine Offset for Minimum Row Precharge Delay Time 00 tRPmin 122 Fine Offset for Minimum RAS to CAS Delay Time g 00 tRCDmin 123 Fine Offset for Minimum CAS Latency Time tAAmin X 00 124 Fine Offset for SDRAM Maximum Cycle Time g 00 tCKAVGmax 125 Fine Offset for SDRAM Minimum Cycle Time g C2 tCKAVGmin 126 127 Cyclical Redundancy Code 128 Raw Card Extension Module Nominal Height 31 25mm 11 129 Module Maximum Thickness Planar Double Sides 11 130 Reference Raw Card Used Revision 0 Raw card C 02 131 DIMM Module Attributes 1 Row 1 Register 05 132 RDIMM Thermal Heat Spreader Solution Not incorporated 00 133 134 Register Manufacturer ID Code By Manufacturer Variable 135 Register Revision Number By Manufacturer Variable 136 X Address Mapping from Register to DRAM Not Mirrored 00 Moderate Drive Chip select ODT CKE 137 Register Output Drive Strength for Control Mademte Dave 55 Command Address 138 Register Output Drive Strength for CK Moderate Drive 05 139 253 Reserved 00 254 255 Cyclical Redundancy Code CRC 256 319 Reserved 00 320 321 Module Manufacturer ID Code 322 Module Manufacturing Location 323 324 Module Manufacturing Date z 325 328 Module Serial Number 329 348 Module Part Number 349 Module Revision Code 00 350 351 DRAM Manufacturer ID Code By Manufacturer Variable 352 D
39. tart here www transcend info com Pin Assignments Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin No Name No Name No Name No Name No Name No Name No Name No Name 1 12V5NC 37 VSS 73 VDD 109 VSS 145 12V5 NC 181 DQ29 217 VDD 253 DQ41 vss 38 pae4 74 ckot 110 TPQS14 146 vREFCA 182 vss J218 ckit es4 vss 2 DQS14 t TDQS14 c 3 pas 39 vss 75 CkKoc j OOS vss 183 Daes 219 CKi_c 255 possc 4 vss 4o e 76 voo it 2 vss 148 Dos 184 vss 220 vob 256 DoSs5t 5 Doo a ose 177 vir faj Dase s49 vss 185 Dass 221 vit 257 vss e vss 42 vss 78 EVENTn na vss 150 Dat ise DasS3 1 222 PARITY 258 _DQ47 7 BSS 43 Daso 79 Aao t5 Do42 151 vss 187 vss 223 VDD ese vss s bose a4 vss eo vob 116 vss M52 Doso c 188 Dos 2e4 Bai 260 Daas 9 vss Dae sr BAO m7 Dose 153 Dasot 19 vss 225 Aio AP 261 VSS 10 DQ6 46 VSS 82 RAS_n A16 118 VSS 154 VSS 190 DQ27 _ 226 VDD 262 DQ53 11 VSS 47 CB4 83 VDD 119 DQ48 155 DQ7 191 VSS 227 RFU 263 VSS 12 DQ2 48 VSS 84 SO_n 120 VSS 156 VSS 192 CB5 228 WE n A14 264 DQ49 13 vss 49 cBo ss voo fiai P9572 157 Das 1e3 vss fz29 voo 265 vss 14 pat2 50 vss 86 CAS mais 122 TOSS J158 vss 194 cesi 230 NC 266 DQS6 c DQS15 c 15 vss 51 DOS az opto 123 vss t5e Dats fios vss 231 voo 267 Dase TDQS17 c 16 Dos 52 Deg
40. um Active to Precharge Delay Time tRASmin 33ns 08 Least Significant Byte Minimum Active to Active Refresh Delay Time 29 tRCmin Least Significant Byte so ons fe 30 31 Minimum Refresh Recovery Delay Time tRFC1 min 260ns 20 08 32 83 _ Minimum Refresh Recovery Delay Time tRFC2min 160ns 00 05 34 35 Minimum Refresh Recovery Delay Time tRFC4min 110ns 70 03 Minimum Four Activate Window Delay Time 3E e Amir y 15ns 00 78 Minimum Activate to Activate Delay Time 395 tRRD Smin different bank group dus n Minimum Activate to Activate Delay Time ii tRRD_Lmin same bank group zs 40 Minimum CAS to CAS Delay Time tCCD_Lmin 5 625ns 2E same bank group 41 59 Reserved 00 T Transcend good memories start here www transcend info com 60 77 Connector to SDRAM Bit Mapping 78 116 Reserved 00 417 Fine Offset for Minimum CAS to CAS Delay Time g 83 tCCD_Lmin same bank group 118 Fine Offset for Minimum Activate to Activate Delay B5 Time tRRD Lmin same bank group 119 Fine Offset for Minimum Activate to Activate Delay g CE Time tRRD_Smin different bank group 120 Fine Offset for Minimum Active to Active Refresh r 00 Delay Time tRCmin 121 Fine Offset for Minimum Row Precharge Delay Time 00 tRPmin 122 Fine Offset for Minimum RAS to CAS Delay Time i 00 tRCDmin 123 Fine Offset for Minimum CAS
41. um Refresh Recovery Delay Time tRFC2min 160ns 00 05 34 85 Minimum Refresh Recovery Delay Time tRFC4min 110ns 70 03 Minimum Four Activate Window Delay Time 36 37 AWmin y 15ns 00 78 Minimum Activate to Activate Delay Time 38 tRRD Smin different bank group ME n Minimum Activate to Activate Delay Time ii tRRD Lmin same bank group pale PR 40 Minimum CAS to CAS Delay Time tCCD Lmin 5 625ns 2E same bank group 41 59 Reserved 00 60 77 Connector to SDRAM Bit Mapping T Transcend good memories start here www transcend info com 78 116 Reserved 00 117 Fine Offset for Minimum CAS to CAS Delay Time g 83 tCCD_Lmin same bank group 118 Fine Offset for Minimum Activate to Activate Delay g B5 Time tRRD Lmin same bank group 119 Fine Offset for Minimum Activate to Activate Delay g CE Time tRRD_Smin different bank group 420 Fine Offset for Minimum Active to Active Refresh g 00 Delay Time tRCmin 121 Fine Offset for Minimum Row Precharge Delay Time 00 tRPmin 122 Fine Offset for Minimum RAS to CAS Delay Time 00 tRCDmin 123 Fine Offset for Minimum CAS Latency Time tAAmin 00 124 Fine Offset for SDRAM Maximum Cycle Time 00 tCKAVGmax 125 Fine Offset for SDRAM Minimum Cycle Time C2 tCKAVGmin 126 127 Cyclical Redundancy Code 128 Raw Card Extension Module Nominal
42. z66 DOS6c 15 vss 51 DOS az opto 123 vss t5e Dats fios vss 231 voo 267 Dase TDQS17 c 16 Dos 52 Degg 88 VOD t24 DQ54 t160 vss M96 Dass 232 A13 268 vss 17 vss ss vss ee sin 125 vss tei Das 97 pose 233 vob 2e9 Dass 18 DS 54 cBe jooj vod M26 Daso fisa vss 198 vss ex4 A evo vss 19 2992 s5 vss jaj oomi jizz vss 163 past c M99 cB7 e35 Noce 271 Dos 20 VSS 56 CB2 92 VDD 128 DQ60 164 DQS1 t 200 VSS 236 VDD 272 VSS 21 DQ14 57 VSS 93 C0 CS2 n NC 129 VSS 165 VSS 201 CB3 237 NC CS3 c C1 273 DQ61 22 VSS 58 RESET n 94 VSS 130 DQ56 166 DQ15 202 VSS 238 SA2 274 VSS 23 DQ10 59 VDD 95 DQ36 131 VSS 167 VSS 208 CKE1 239 VSS 275 DQ57 24 vss eo ckEo ee vss t32 OSS49 168 pati 204 voo 240 Das7_ 276 vss 25 pazo et vod ez pasz t3 Dose ieo vss 205 RFU 241 vss 277 Dos7 c 26 vss 62 AcTn 98 vss isaf vss i70 Daet 206 vob 242 Dass 278 DOS71 27 pate e3 Bao fog D99 2t ia5 poe fizi vss eoz Bat e43 vss 279 vss DQS13 t 28 vss e4 vod jroo DGS 2 t36 vss tz2 DQ17 208 ALERT n 244 Das4 c 280 Does 29 DOS I5 Fes A12 BC_n M01 vss 137 Dass tz3 vss 209 voo 245 DOS4t 8 vss 30 DOS Jee A9 two2 Dass fiss vss tz4 DoS2 c 210 ait 246 vss ese2 Dose 31 VSS 67 VDD 103 VSS 139 SAO 175 DQS2 t 211 A7 247 DQ39 283 VSS 32 DQ22 68 A8 104 DQ34 140 SA1 176 VSS 212 VDD 248 VSS 284 VDDSPD 33 VS
43. ze IRRD LAR Max Ane 8 4n HK ACTIVATE to ACTIVATE Command delay to same bank group for 1KB page size TARDE Max 4nCk 5 3ns i us ACTIVATE to ACTIVATE Command delay to tRRD L same bank group for 1 2KB page size 1 2K Max 4nCK 5 3ns nes Four activate window for 2KB page size tFAW 2K Max 28nCK 30ns ns Four activate window for 1KB page size tFAW 1K Max 20nCK 21ns ns Four activate window for 1 2KB page size tFAW 1 2K Max 16nCK 15ns ns Power up and RESET calibration time tZQinit 1024 g nCK Normal operation Full calibration time tZQoper 512 nCK Normal operation short calibration time tZQCS 128 nCK Exit Self Refresh to commands not re quiring a locked DEL tXS tRFC min 10ns Exit Self Refresh to commands requir ing a lacked DLL tXSDLL tDLLK min Internal READ Command to PRE CHARGE tRTP Command delay Max 4nCK 7 5ns Minimum CKE low width for Self re fresh tCKESR tCKE min 1nCK f entry to exit timing Exit Power Down with DLL on to any valid command Exit Precharge Power Down with XP DLL frozen to commands not requiring a Max 4nCK 6ns locked DLL CKE minimum pulse width tCKE Max 3nCK 5ns Asynchronous RTT turn on delay Power Down with DLL frozen AONAR hp 30 us Asynchronous RTT turn off delay Power Down with DLL frozen indita 9 a9 ns RTT dynamic change skew tADC 0 3 0 7 tCK Transcend T good memories start here SERIAL PRESENCE DETECT SPECIFICATION www transcend info com TS2GHR72V1
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