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Intel Core i3-4340TE

1. B B B B B B B B Hex Vec B B B B B B B B Hex Vec i Li Li Li Ji f il i iJ i Li i li Li Jii t tt t tt t t t tt ttt t t 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1 1J 0 0 1 0 1 0J CAh 2 5100 1111 0 110 0 ECh 2 8500 1 1 J 0 0 1 0 1 1 CBh 2 5200 1111 0 i 10 1 EDh 2 8600 1 1 J 0 0 1 1 0 0J CCh 2 5300 11111011111 0 EEh 2 8700 1 1 J 0 0 1 1 0 1 CDh 2 5400 111110111 1 EFh 2 8800 1 1 J 0 J 0 1 1 1 0J CEh 2 5500 1111 1 00 0 0J FOh 2 8900 1 i J 0 0 11 1 1 CFh 2 5600 111111 0100 1 F1h 2 9000 1 1 J 0 1 0 0 0 0 J DOh 2 5700 111111 001 0 F2h 2 9100 1 1 J 0 1 0 0 01 Dih 2 5800 111111 01011 F3h 2 9200 1 1 J 0 1 0 0 1 0J D2h 2 5900 111111 010 0 F4h 2 9300 1 1 J 0 1 0 0 1 1 D3h 2 6000 111111 0110 1 F5h 2 9400 1 1 J 0 1 0 1 0 0J D4h 2 6100 111111 011 0 F6h 2 9500 1 1 J 0 1 0 1 0 1 D5h 2 6200 11111101111 FZh 2 9600 1 1 J 0 1 0 1 1 0J D6h 2 6300 11111110 0 0J F8h 2 9700 1 1 J 0 1 0 1 1 1 DZh 2 6400 11111110 0 1 F9h 2 9800 1 1 J 0 1 1 0 0 0J D8h 2 6500 11111110110 FAh 2 9900 1 1i J 0 11 0 01J D9h 2 6600 1111111011 1 FBh 3 0000 1 1J 01 1 0 1 0J DAh 2 6700 1111111110 0 FCh 3 0100 1 1 J 0 1 1 0 1 1 DBh 2 6800 1111111110 1 FDh 3 0200 1 1 J 0 1 1 1 0 0J DCh 2 6900 111111111 0 FEh 3 0300 1 1J 01 1 1 01 DDh 2 7000 1111
2. Symbol Definition and Conditions Min Max Units Notes V Negative Edge Threshold 0 275 0 500 v 7 n Voltage Vccio TERM Vccro TERM V Positive Edge Threshold 0 550 0 725 V _ P Voltage VCCIO_TERM VCCIO_TERM Cbus Bus Capacitance per Node N A 10 pF Cpad Pad Capacitance 0 7 1 8 pF Ileak000 leakage current at 0 V 0 6 mA _ Ileak025 VAR current at 0 25 _ 0 4 mA _ CCIO_TERM Ileak050 leakage current at 0 50 _ 0 2 mA _ Vccio TERM Ileak075 leakage current at 0 75 _ 0 13 mA Vecio_TERM Ileak100 mas current at _ 0 10 mA B CCIO_TERM Notes 1 Vccio reRM Supplies the PECI interface PECI behavior does not affect Vcc o_renw Minimum maximum specifications 2 The leakage specification applies to powered devices on the PECI bus 3 The PECI buffer internal pull up resistance measured at 0 75 Vccio TERM Input Device Hysteresis The input buffers in both client and host models must use a Schmitt triggered input design for improved noise immunity Use the following figure as a guide for input buffer design Input Device Hysteresis g S Vito Maximum Vp Minimum Minimum Vy PECI Low Range PECI Ground Valid Input Hysteresis Signal Range Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family Datasheet Volume 1
3. MWAIT C6 MWAIT C3 P LVL3 I O Read P_LVL2 I O i N as 6 da WP V C While individual threads can request low power C states power saving actions only take place once the core C state is resolved Core C states are automatically resolved by the processor For thread and core C states a transition to and from CO is required before entering any other C state Coordination of Thread Power States at the Core Level Processor Core C State Thread 1 co C1 C3 c6 C7 co co co co co CO c co Cii Cii Cii Git Thread 0 c3 co ci C3 C3 C3 C6 Co C1 C3 C6 C6 C7 Co C1 C3 C6 C7 Note 1 If enabled the core C state will be C1E if all cores have resolved a core C1 state or higher Reguesting Low Power Idle States The primary software interfaces for reguesting low power idle states are through the MWAIT instruction with sub state hints and the HLT instruction for C1 and C1E However software may make C state requests using the legacy method of I O reads from the ACPI defined processor clock control registers referred to as P_LVLx This method of requesting C states provides legacy support for operating systems that initiate C state transitions using I O reads For legacy operating systems P_LVLx I O reads are converted within the processor to the equivalent MWAIT C state request Therefore P_LVLx reads do not directly result in I O reads to the system The feat
4. Desktop Processor Thermal Profiles This section provides thermal profiles for the Desktop processor families Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron March 2015 Processor Family Datasheet Volume 1 of 2 Order No 328897 010 67 intel 5 1 1 Figure 15 Table 22 Processor PCG 2013D and PCG 2014 Thermal Profile Processor Thermal Management Thermal Test Vehicle Thermal Profile for Processor PCG 2013D and PCG 2014 80 N U1 N o TTV Case Temperature C 9 o eo U1 Tease 0 33 Power 45 0 55 50 45 40 0 20 40 60 80 100 TTV Power W See the following table for discrete points that constitute the thermal profile Thermal Test Vehicle Thermal Profile for Processor PCG 2013D and PCG 2014 Power W TcasE MAX Power W TcasE MAX Power W TcasE MAX C C C Y 0 33 Power 45 26 53 58 54 62 82 0 45 00 28 54 24 56 63 48 2 45 66 30 54 90 58 64 14 4 46 32 32 55 56 60 64 80 6 46 98 34 56 22 62 65 46 8 47 64 36 56 88 64 66 12 10 48 30 38 57 54 66 66 78 12 48 96 40 58 20 68 67 44 14 49 62 42 58 86 70 68 10 16 50 28 44 59 52 72 68 76 18 50 94 46 60 18 74 69 42 20 51 60 48 60 84 76 70 08 22 52 26 50 61 50 78 70 74 24 52 92 52 62 16 continued continued continued Desktop 4th Generation Intel Core Proces
5. Power W Tcase_max C 38 60 28 40 61 10 42 61 92 44 62 74 46 63 56 48 64 38 50 65 20 52 66 02 54 66 84 56 67 66 58 68 48 60 69 30 62 70 12 64 70 94 65 71 35 5 1 3 Processor PCG 2013B Thermal Profile Figure 17 Thermal Test Vehicle Thermal Profile for Processor PCG 2013B 253 S 70 4 Trase 0 51 Power 48 5 65 4 E g 50 1 E A4 9 8 50 T Ea 40 T T T T 1 0 10 20 30 40 50 TIV Power W See the following table for discrete points that constitute the thermal profile Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 70 Order No 328897 010 Thermal Management Processor Table 24 Thermal Test Vehicle Thermal Profile for Processor PCG 2013B Power W Tcase Max C Y 0 51 Power 48 5 0 48 50 2 49 52 4 50 54 6 51 56 8 52 58 10 53 60 12 54 62 14 55 64 16 56 66 18 57 68 20 58 70 22 59 72 24 60 74 26 61 76 28 62 78 30 63 80 32 64 82 34 65 84 36 66 86 38 67 88 40 68 90 42 69 92 44 70 94 45 71 45 Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron March 2015 Order No 328897 010 Processor Family Datasheet Volume 1 of 2 71 m n tel Processor Thermal Management 5 1 4 P
6. The decision to demote a core from C6 C7 to C3 or C3 C6 C7 to C1 state is based on each core s immediate residency history and interrupt rate If the interrupt rate experienced on a core is high and the residence in a deep C state between such interrupts is low the core can be demoted to a C3 or C1 state A higher interrupt pattern is required to demote a core to C1 state as compared to C3 state This feature is disabled by default BIOS must enable it in the PMG CST CONFIG CONTROL register The auto demotion policy is also configured by this register Package C States The processor supports CO C1 C1E C3 C6 and C7 on some SKUs power states The following is a summary of the general rules for package C state entry These apply to all package C states unless specified otherwise e A package C state request is determined by the lowest numerical core C state amongst all cores e A package C state is automatically resolved by the processor depending on the core idle power states and the status of the platform components Each core can be at a lower idle power state than the package if the platform does not grant the processor permission to enter a requested package C state The platform may allow additional power savings to be realized in the processor Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron March 2015 Processor Family Datasheet
7. m Power Management Processor n te j 4 3 2 e Reduced possible overshoot undershoot signal quality issues seen by the processor I O buffer receivers caused by reflections from potentially un terminated transmission lines When a given rank is not populated the corresponding chip select and CKE signals are not driven At reset all rows must be assumed to be populated until it can be determined that the rows are not populated This is due to the fact that when CKE is tri stated with an SO DIMM present the SO DIMM is not ensured to maintain data integrity CKE tri state should be enabled by BIOS where appropriate since at reset all rows must be assumed to be populated DRAM Power Management and Initialization The processor implements extensive support for power management on the SDRAM interface There are four SDRAM operations associated with the Clock Enable CKE signals which the SDRAM controller supports The processor drives four CKE pins to perform these operations The CKE is one of the power save means When CKE is off the internal DDR clock is disabled and the DDR power is reduced The power saving differs according to the selected mode and the DDR type used For more information refer to the IDD table in the DDR specification The processor supports three different types of power down modes in package CO The different power down modes can be enabled through configuring PM PDWN config 0 0 0 MCHBAR The t
8. continued Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron March 2015 Order No 328897 010 Processor Family Datasheet Volume 1 of 2 13 Processor Introduction Term Description DVI Digital Visual Interface DVI is the interface specified by the DDWG Digital Display Working Group Embedded Controller ECC Error Correction Code eDP embedded DisplayPort EPG Electrical Power Gating EU Execution Unit FMA Floating point fused Multiply Add instructions FSC Fan Speed Control HDCP High bandwidth Digital Content Protection HDMI High Definition Multimedia Interface HFM High Frequency Mode iDCT Inverse Discrete Cosine Transform IHS Integrated Heat Spreader GFX Graphics GSA Graphics in System Agent GUI Graphical User Interface IMC Integrated Memory Controller Inte 8 64 Technology 64 bit memory extensions to the IA 32 architecture Inte DPST Intel Display Power Saving Technology Inte FDI Intel Flexible Display Interface Inte TSX NI Intel Transactional Synchronization Extensions New Instructions Inte TXT Intel Trusted Execution Technology Inte Intel Virtualization Technology Processor virtualization when used in conjunction with V
9. 1 0 0 11 1 0 4Eh 1 2700 0 1110 J 00l0 70h 1 6100 0 1 0 0 1 1 1 1 4Fh 1 2800 O 1 1 1 0 0 0 1 71h 1 6200 0 1 0 1 0 0 0 0 50h 1 2900 0 111001110 72h 1 6300 0 1 0 1 00 011 5ih 1 3000 0 1110011 41 73h 1 6400 0 1 0 1 00 1 0 52h 1 3100 O 1i 1 1 0 1 0 0 74h 1 6500 0 1 0 1 0 0 1 1 53h 1 3200 0 1 1 1 0 1 0 1 75h 1 6600 0 1 0 1 01 0l 0 54h 1 3300 O 1i 1 1 0 1 1 0 76h 1 6700 O 1 0 1 0 1 0 1 55h 1 3400 O 1i 1 1 0 1 1 1 77h 1 6800 0 1 0 1 0 1 1J 0 56h 1 3500 0 1111 0010 78h 1 6900 0 1 0 1 01111 57h 1 3600 O 1i 1 1 1 0 0 1 79h 1 7000 O 1i 0O 1 1 0 0 0 58h 1 3700 0 11110110 Z7Ah 1 7100 0 1 0 1 10 0J1 59h 1 3800 0 11110111 7Bh 1 7200 0 1 0 11 0 1 0J 5Ah 1 3900 0 111110 0 7Ch 1 7300 0 1 0 11 0 1 1 5Bh 1 4000 O i 1i 1 1 1 0 1 7Dh 1 7400 O 1ij O i 1i 1 0 0 5Ch 1 4100 O i 1i 1 1 1 1 0 7Eh 1 7500 O 1ij 0O 1i 1 1 0 1 5Dh 1 4200 O i i 1i 1i 1 1 1 7Fh 1 7600 O 1ijO i ij1i 1 O 5Eh 1 4300 100 0 0l 0100 80h 1 7700 0 1 0 1 1 1 1 1 5Fh 1 4400 10100 01010 11 81h 1 7800 0 1 1 0 l0 0 0 0 60h 1 4500 1000 010110 82h 1 7900 0 1 1 0 0 0 011 61h 1 4600 100001011 11 83h 1 8000 0 1 1 0 0 0 1 0 62h 1 4700 1000 01110 0 84h 1 8100 0 1 1 0 00 111 63h 1 4800 1010001110 11 85h 1 8200 continued continued Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desk
10. B8h 2 3300 10101101111 11 97h 2 0000 1 0 11 1 0 10 1 B9h 2 3400 1010 1 10 100 98h 2 0100 1 0 1 11 0 110 BAh 2 3500 1 0j0 1 1 0 0 1 99h 2 0200 1 0 11 1 0 1 1 BBh 2 3600 10 0 1 1 01 0 9Ah 2 0300 1 0 J11 1 1 0 0J BCh 2 3700 1010 1 10 1 1 9Bh 2 0400 1 0 1 11 1 0 1 BDh 2 3800 1010 1110 0 9Ch 2 0500 1 0 11 1 i l1 0 BEh 2 3900 1010 1 i 10 1 9Dh 2 0600 1 0 11 1 1111 BFh 2 4000 101011111110 9Eh 2 0700 1 i 0 0 0 0 0 0J COh 2 4100 1010 1111 1 9Fh 2 0800 1 i J 0 0 0 0 01 Cih 2 4200 101 0 000 0 J AOh 2 0900 1 i J 00 0 0 10J C2h 2 4300 10110 000 1 A1h 2 1000 1 i 0 0 0 0 11 C3h 2 4400 1011 0 001 0J A2h 2 1100 1 i J 00 0 1 0 0J C4h 2 4500 1011 0 010111 A3h 2 1200 1 i J 00 0 1 01 C5h 2 4600 1011 0 010 0J A4h 2 1300 1 i J 00 0 1 10 C6h 2 4700 1011 0 0110 1 A5h 2 1400 1 i J 00 0 1i 1 1 C7h 2 4800 1010 01110 A6h 2 1500 1 i J 00 1 0 10 0J C8h 2 4900 1011 0 01111 AZh 2 1600 1 i J 00 1 0 0 1 C9h 2 5000 continued continued Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 Order No 328897 010 97 Processor Electrical Specifications 2 em D
11. Band Ripple 10 PSO 15 PS1 Vcc Ripple 50 15 PS2 mV 3 5 6 7 8 60 15 PS3 Default Vcc voltage for Vcc BooT initial power A V up ie 2013D PCG N n 95 A 4 8 Icc l 2013C PCG B 75 A 4 8 Icc l 2013B PCG _ _ 58 A 4 8 Icc continued Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 102 Order No 328897 010 Electrical Specifications Processor n te Symbol Parameter Min Typ Max Unit Note ios 5 PCG _ _ 48 A 4 8 cc Pmax end P O 153 w 9 2013C PCG Pmax Pmax 121 Ww 9 2013B PCG Pmax Pmax E m 99 W 9 Paine BT PEG 83 w 9 Notes 1 Unless otherwise noted all specifications in this table are based on estimates and simulations or empirical data 2 Each processor is programmed with a maximum valid voltage identification value VID that is set at manufacturing and cannot be altered Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range This differs from the VID employed by the processor during a power management event Adaptive Thermal Monitor Enhanced Intel SpeedStep Technology or Low Power States 3 The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE lands at
12. and resolution settings on each of the active display devices connected The digital ports on the processor can be configured to support DisplayPort HDMI DVI For Desktop designs digital port D can be configured as eDPx4 in addition to dedicated x2 port for Intel FDI for VGA The following table shows examples of valid three display configurations through the processor Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron March 2015 Processor Family Datasheet Volume 1 of 2 Order No 328897 010 35 intel Processor Interfaces Table 9 Valid Three Display Configurations through the Processor Display 1 Display 2 Display 3 Maximum Maximum Maximum Resolution Display Resolution Resolution Display 1 Display 2 3 4096x2304 G 24 Hz HDMI HDMI DP 40x21 60 H 2560x1600 60 Hz kk ie ix DVI DVI DP 1920x1200 60 Hz 3840x2160 60 Hz DP DP DP 3840x2160 60 Hz 3840x2160 4096x2304 24 Hz VGA DP HDMI 1920x120 60H LAUD AUS 60 Hz 2560x1600 60 Hz 3840x2160 Q 4096x2304 24 Hz eDP DP HDMI 3840x2160 60 Hz 60 Hz 2560x1600 60 Hz eDP DP DP 3840x2160 60 Hz 3840x2160 60 Hz 4096x2304 24 Hz eDP HDMI HDMI 3840x2160 60 Hz 2560x1600 60 Hz Notes 1 Requires support of 2 channel DDR3 DDR3L 1600 MT s configuration for driving 3 simultaneous 3840x2160 60 Hz display resolutions 2 DP and eDP resolutions in the abo
13. 0 806 2 2 4 2 35 85 6 1 016 2013A 2 2 2 2 35 85 6 1 021 2 1 2 2 35 90 6 1 141 5 5 Thermal Specifications This section provides thermal specifications Thermal Profile and design guidelines for enabled thermal solutions to cool the processor Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 76 Order No 328897 010 Thermal Management Processor intel Performance Targets The following table provides boundary conditions and performance targets as guidance for thermal solution design Thermal solutions must be able to comply with the Maximum Tcase Thermal Profile Table 28 Boundary Conditions Performance Targets and Tcase Specifications bow maximum Tcase max 2 Package Platform I Airflow TcasE P Processor PCG TDP TDP Heatsink RPM Thermal ic Wed Ycad Profile Desktop 40 C y 0 33 74 0 C 4C GT2 95W 2014 88W 88W ATIVE CU 3100 RPM Power 45 0 Core DHA A 0 358 C W me 40 C y 0 33 72 7 C 4C GT2 95W 2013D 84W 84W 3100 RPM Power 45 0 Core DHA A 0 381 C W m 40 C y 0 41 71 4 C 4C GT2 65W 65W 65W 3100 RPM Power 44 7 Core DHA B 0 485 C W m 40 C y 0 41 66 8 C 2C GT2 65W 2013C 54W 54W 3100 RPM Power 44 7 Core DHA B 0 495 C W XEM 40 C y 0 41 66 4 C 2C GT1 65W 53W
14. 010 m e Package Mechanical Specifications Processor n te Figure 27 2014 Processor Package Land Pin Side Components OOCOOOOOO OOOOOOOO Blap aa B am am cm am adele 88 Bg 9 m moe c 22 20 LAND PIN SIDE COMPONENT VIEW BOTTOM 8 9 Processor Storage Specifications The following table includes a list of the specifications for device storage in terms of maximum and minimum temperatures and relative humidity These conditions should not be exceeded in storage or transportation Table 61 Processor Storage Specifications Parameter Description Minimum Maximum Notes The non operating device storage temperature Damage latent or otherwise may occur when subjected to for any length of time 55 C 125 C 1 2 3 Tabsolute storage The ambient storage temperature limit Tsustained storage in shipping media for a sustained 5 C 40 C 4 5 period of time continued Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family March 2015 Datasheet Volume 1 of 2 Order No 328897 010 113 Processor Package Mechanical Specifications Parameter Description Minimum Maximum Notes The maximum device storage relative 0 o RHsustained storage humidity for a sustained period of time 60 Q 24 C 5 6 A prolonged or extended period of time TIMEs
15. 0S Q 9Q0Q OOOOPOOODOOOCPOD CO ODOLOOOOOODOODOLOCO ODOOOOPDOCOOOODOOPDOL ECOCODODOLDOCDOOOODODOODOODO QqQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQ DOPOCOOCOCOODODOCOCOCOOOGOOODOODOOCOOOOOOOOOODO ODOOOOGOODOOODGDOODOOODOODOOCOODOOOCDOOOCO OECO ODDOOCOLOOOOOOCOOCPOCOOOOOOCOCOCOOOOOOCOCOCO III QQQQQQ QQQQQQQ QQ Q Q9 Q9 9 S9SQ6QQ099 99 e e e S S CC CC I CIC CC CIC CU CU CIC CU CIC CU ES OOOOOSSSOSOOOOSOSOOOSOOOOSOOOOooooooosooH QQQQQQQQQQ QQQQQQQQ Q Q QQ QQQQQQQQ QQQQQQQQQ QQQQQQQQ o S QQQQQQQ ZOQ T oo QQQQQQQQ ooooooog nn ao 0000 OOO00000g0000000000 meo e ee on QQQ 9 999999999 999N9999N99999999999999999999990 QQQQQQQQQQQQQQQQQQQQQQQQQ QQQQQQQQQQQQQQQQQQ QQQQQQQQQQQQQQQQQQQQQQQQQQ9QQ9QS9e9Q0SQ SQ9o SQQQ QQQQQQQQQQQQQQQQ QQQQQQQQQQQQQQQQQQQQQQQQQQ QQQQQQQQQQQQQQQQQQQQ9QQ9QQQQQQQQQQQQQQQQQQQQ C5656565656565656565656365650565650565056563636565656505066365656305656565050 99999999999999999999999N909999999990090999 QQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQ QQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQ QSQSQQQQQQQQQQQQQQQQQQQQSQQ9QQ9Q QQ 999999909999999999 QSQQQQQQQ 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 112 Order No 328897
16. 72 6 C and at a worst case design point of 40 C local ambient this will result in Wea 72 6 40 95 0 34 C W Similarly for a system with a design target of 45 C ambient the Wc at DTS 1 needed will be 0 29 C W The second point defines the thermal solution performance ca at TconrRoL The following table lists the required Wc for the various TDP processors These two points define the operational limits for the processor for DTS 1 1 implementation At TconrRoL the fan speed must be programmed such that the resulting Yc is better than or equivalent to the required Uc listed in the following table Similarly the fan speed should be set at DTS 1 such that the thermal solution performance is better than or equivalent to the Yc requirements at TAMBIENT max The fan speed controller must linearly ramp the fan speed from processor DTS TconrRoL to processor DTS 1 Digital Thermal Sensor DTS 1 1 Definition Points Example DTS 1 1 Maximum fan speed to Uc O DTS 1 meet Tcase maximum at TDP PWM Wa DTS Tcontroi Minimum allowed fan speed atTcontrol d T T I DTS Processor Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 74 Order No 328897 010 Thermal Management Processor n tel
17. 90 6 7 Phase Locked Loop PLL Signal si tee rni eene sena tena eed kak te sla Ka bla DR klar a alba 91 6 8 Testability Signals c n na nam la an n OBERE dae A D BARA a wel Q uiua ms ERR DEWA aa D da A n 91 6 9 Error and Thermal Protection Signals ccceeeeeeeee ee kaka aa nalan k eee eee ale an a emen 92 6 10 Power Sequencing Signal Sisirs al k eese kaka kk lad kan k a kn a dea kada AA ale kak kk ae radara K k daa 92 6 11 Processor Power Signals eee jas ast en E dak Eua Lei dak din V da gadi ha yan tak 93 6 12 S nse cire Drm 93 6 13 Ground and Non Critical to Function NCTF Signals ccccceeeeeeeeee ee kk kk 93 6 14 Processor Internal Pull Up Pull Down Terminations csse 93 Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 4 Order No 328897 010 m Contents Processor n tel j 7 0 Electrical Specifications leeeeeeeieeeieeeesesesesenn ka kana kn nana ana uan u kana an uan u nanna uu uu ua uan uu ka 94 7 1 Integrated Voltage Regulator nak cates dlya kalana dala bun ba W k a ce tea kav dila k aa E Rx RR E 94 7 2 Power and Ground LandS 3 sie bett prem na k n A kak n ex RE AR MA XR RR aim Eu E d RR di d n 94 7 3 Vee Voltage Identification VID s sis eei sese n v c
18. AU31 SB_CKEO AW29 continued continued continued Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family Datasheet Volume 1 of 2 118 March 2015 Order No 328897 010 Processor Ball and Signal Information Processor Signal Name Ball Signal Name Ball Signal Name Ball SB_DQ3 AH35 SB_DQ62 AF6 SB MA13 AR15 SB DQ30 AP29 SB DQ63 AF7 SB MA14 AV27 SB DQ31 AP28 SB DQ7 AH34 SB MA15 AY28 SB DQ32 AR12 SB DQ8 AL34 SB MA2 AM22 SB DQ33 AP12 SB DQ9 AL35 SB MA3 AM23 SB DQ34 AL13 SB DQSO AF35 SB MA4 AP23 SB DQ35 AL12 SB DQS1 AL33 SB MA5 AL23 SB DQ36 AR13 SB DQS2 AP33 SB MA6 AY24 SB DQ37 AP13 SB DQS3 AN28 SB MA7 AV25 SB DQ38 AM13 SB DQS4 AN12 SB MA8 AU26 SB DQ39 AM12 SB_DQS5 AP8 SB MA9 AW25 SB DQ4 AD34 SB DQS6 AL8 SB ODTO AM17 SB DQ40 AR9 SB DQS7 AG7 SB ODT1 AL16 SB DQ41 AP9 SB DQS8 AN25 SB ODT2 AM16 SB DQ42 AR6 SB DQSNO AF34 SB ODT3 AK15 SB DQ43 AP6 SB DQSN1 AK33 SB_RAS AM18 SB_DQ44 AR10 SB_DQSN2 AN33 SB_WE AK16 SB_DQ45 AP10 SB_DQSN3 AN29 SKTOCC D38 SB_DQ46 AR7 SB_DQSN4 AN13 SM_DRAMPWRO AK21 K SB_DQ47 AP7 SB_DQSN5 AR8 SM_DRAMRST AK22 SB_DQ48 AM9 SB_DQSN6 AM8 SM_RCOMPO R1 SB_DQ49 AL9 SB DQSN7 AG6 SM RCOMP1 P1 SB DQ5 AD35 SB DQSN8 AN26 SM
19. CH is a half duplex bidirectional channel used for link management and device control The Hot Plug Detect HPD signal serves as an interrupt request for the sink device The processor is designed in accordance with the VESA DisplayPort Standard Version 1 2a The processor supports VESA DisplayPort PHY Compliance Test Specification 1 2a and VESA DisplayPort Link Layer Compliance Test Specification 1 2a DisplayPort Overview Source Device Main Link Sink Device Isochronous Streams DisplayPc AUX CH Link Device Managemet Hot Plug Detect Interrupt Request High Definition Multimedia Interface HDMI The High Definition Multimedia Interface HDMI is provided for transmitting uncompressed digital audio and video signals from DVD players set top boxes and other audiovisual sources to television sets projectors and other video displays It can carry high quality multi channel audio data and all standard and high definition consumer electronics video formats The HDMI display interface connecting the processor and display devices uses transition minimized differential signaling TMDS to carry audiovisual information through the same HDMI cable HDMI includes three separate communications channels TMDS DDC and the optional CEC consumer electronics control CEC is not supported on the processor As shown in the following figure the HDMI cable carries four different
20. CKN 3 0 SB CKP 3 0 SB CKN 3 0 Output DDR3 DDR3L Command Signals Single ended DDR3 DDR3L SA BS 2 0 SB BS 2 0 SA WE SB WE SA RAS Output SB RAS SA CAS SB CAS SA MA 15 0 SB MA 15 0 DDR3 DDR3L Control Signals Single ended DDR3 DDR3L SA CKE 3 0 SB CKE 3 0 SA CS 3 0 SB_CS 3 0 Output SA ODT 3 0 SB ODT 3 0 Single ended CMOS Output SM_DRAMRST continued Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron March 2015 Processor Family Datasheet Volume 1 of 2 Order No 328897 010 99 Processor Electrical Specifications Signal Group Type Signals DDR3 DDR3L Data Signals 2 Single ended DDR3 DDR3L Bi SA_DQ 63 0 SB_DQ 63 0 directional Differential DDR3 DDR3L Bi SA_DQSP 7 0 SA_DQSN 7 0 SB_DQSP 7 0 SB_DQSN 7 0 directional DDR3 DDR3L Compensation Analog Input SM_RCOMP 2 0 DDR3 DDR3L Reference Voltage Signals DDR3 DDR3L Output SM_VREF SA_DIMM_VREFDQ SB_DIMM_VREFDQ Testability ITP XDP Single ended CMOS Input TCK TDI TMS TRST Single ended GTL TDO Single ended Output DBR Single ended GTL BPM 7 0 Single ended GTL PREQ Single ended GTL PRDY Control Sideband Single ended GTL Input Open PROCHOT Drain Output Single ended Asynchronous
21. Chipset Family Platform Controller Hub PCH Specification Update 330551 Intel 9 Series Chipset Family Platform Controller Hub PCH Thermal Mechanical PESAR KE 330549 Specifications and Design Guidelines http Advanced Configuration and Power Interface 3 0 www acpi info PCI Local Bus Specification 3 0 http www pcisig com specifications PCI Express Base Specification Revision 2 0 http www pcisig com DDR3 SDRAM Specification http www jedec org DisplayPort Specification http www vesa org Intel 64 and IA 32 Architectures Software Developer s Manuals http www intel com products processor manuals index htm Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron March 2015 Processor Family Datasheet Volume 1 of 2 Order No 328897 010 17 m n tel Processor Interfaces 2 0 Interfaces 2 1 System Memory Interface e Two channels of DDR3 DDR3L Unbuffered Dual In Line Memory Modules UDIMM or DDR3 DDR3L Unbuffered Small Outline Dual In Line Memory Modules SO DIMM with a maximum of two DIMMs per channel e Single channel and dual channel memory organization modes e Data burst length of eight for all memory organization modes e Memory data transfer rates of 1333 MT s and 1600 MT s e 64 bit wide channels e DDR3 DDR3L I O Voltage of 1 5 V for Desktop e The type
22. DTS outputs a temperature relative to the maximum supported operating temperature of the processor Tjmax regardless of TCC activation offset It is the responsibility of software to convert the relative temperature to an absolute temperature The absolute reference temperature is readable in the TEMPERATURE_TARGET MSR 1A2h The temperature returned by the DTS is an implied negative integer indicating the relative offset from Tjmax The DTS does not report temperatures greater than Tjmax The DTS relative temperature readout directly impacts the Adaptive Thermal Monitor trigger point When a package DTS indicates that it has reached the TCC activation a reading of Oh except when the TCC activation offset is changed the TCC will activate and indicate an Adaptive Thermal Monitor event A TCC activation will lower both IA core and graphics core frequency voltage or both Changes to the temperature can be detected using two programmable thresholds located in the processor thermal MSRs These thresholds have the capability of generating interrupts using the core s local APIC Refer to the Intel 64 and IA 32 Architectures Software Developer s Manual for specific register and programming details 5 9 1 Digital Thermal Sensor Accuracy Taccuracy The error associated with DTS measurements will not exceed 5 C within the entire operating range 5 10 Intel Turbo Boost Technology Thermal Considerations Intel Turbo Boost Technology allows proc
23. E12 PEG TXN7 C5 RSVD AV2 PEG RXN4 F11 PEG TXN8 E2 RSVD AV20 PEG_RXN5 G10 PEG_TXN9 F3 RSVD AV24 PEG_RXN6 F9 PEG_TXPO A12 RSVD AV29 PEG RXN7 G8 PEG TXP1 B11 RSVD AW12 PEG RXN8 D4 PEG TXP10 G1 RSVD AW23 PEG RXN9 E5 PEG TXP11 H2 RSVD AW24 PEG RXPO E15 PEG TXP12 J1 RSVD AW27 PEG_RXP1 D14 PEG_TXP13 K2 RSVD AY18 PEG_RXP10 F5 PEG_TXP14 M2 RSVD H12 PEG_RXP11 G4 PEG_TXP15 L1 RSVD H14 PEG_RXP12 H5 PEG_TXP2 C10 RSVD H15 PEG_RXP13 J4 PEG_TXP3 B9 RSVD J15 continued continued continued Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family Datasheet Volume 1 of 2 116 March 2015 Order No 328897 010 Processor Ball and Signal Information Processor intel Signal Name Ball Signal Name Ball Signal Name Ball RSVD J17 RSVD_TP P37 SA_DQ20 AM37 RSVD J40 SA BSO AV12 SA DQ21 AM38 RSVD J9 SA BS1 AY11 SA DQ22 AP37 RSVD L10 SA BS2 AT21 SA DQ23 AP40 RSVD L12 SA_CAS AU9 SA_DQ24 AV37 RSVD M10 SA_CKO AY15 SA_DQ25 AW37 RSVD M11 SA_CK1 AW15 SA_DQ26 AU35 RSVD M38 SA_CK2 AV14 SA_DQ27 AV35 RSVD N35 SA_CK3 AW13 SA_DQ28 AT37 RSVD P33 SA_CKEO AV22 SA_DQ29 AU37 RSVD R33 SA_CKE1 AT23 SA_DQ3 AF39 RSVD R3
24. Family Datasheet Volume 1 of 2 March 2015 8 Order No 328897 010 Revision History Processor Revision History Revision Description Date 001 Initial Release June 2013 002 Added Desktop 4th Generation Intel Core i7 4771 i5 4440 i5 4440S i3 4340 i3 4330 i3 4330T i3 4130 and i3 4130T processors Added Desktop Intel Pentium G3430 G3420 G3220 G3420T G3220T processors Updated Section 4 2 4 Core C State Rules Updated Section 4 2 5 Package C States Minor edits throughout for clarity September 2013 003 Minor edits throughout for clarity November 2013 004 Added Desktop Intel Celeron G1830 G1820 and G1820T processors Added Section 4 2 6 Package C States and Display Resolutions December 2013 005 Updated Table 39 Testability Signals March 2014 006 s Added Desktop 4th Generation Intel Core i7 4790 i7 4790S i7 4790T i7 4785T i5 4690 i5 4690S i5 4690T i5 4590 i5 4590S i5 4590T i5 4460 i5 4460S i5 4460T i3 4360 i3 4350 i3 4350T i3 4150 i3 4150T processors Added Desktop Intel Pentium G3450 G3440 G3440T G3240 G3240T processors Added Desktop Intel Celeron G1850 G1840 G1840T processors Added Section 5 5 Thermal Specifications May 2014 007 008 Added Desktop 4th Generation Intel Core i7 4790K i5 4690K processors Added Desktop Intel Pentium G3258 processor Added Desktop 4
25. M30 VSS R6 VSS Y4 VSS M32 VSS R7 VSS Y5 VSS M34 VSS R8 VSS Y6 VSS M35 VSS Ti VSS_NCTF AU40 VSS M37 VSS T2 VSS_NCTF AV39 VSS M4 VSS T33 VSS_NCTF AW38 VSS M40 VSS T36 VSS_NCTF AY3 VSS M5 VSS T37 VSS_NCTF B38 VSS M6 VSS T38 VSS_NCTF B39 VSS M7 VSS T39 VSS_NCTF C40 VSS M9 VSS T4 VSS NCTF D40 VSS N1 VSS T5 VSS_SENSE F40 VSS N2 VSS T6 continued continued Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 Order No 328897 010 125
26. Max Units Notes Vit Input Low Voltage Vccro our 0 3 V 2 Vin Input High Voltage Vccro our 0 7 V 2 4 VoL Output Low Voltage Vecio_out 0 1 V 2 VoH Output High Voltage Vccio our 0 9 V 2 4 Ron Buffer on Resistance 23 73 Q u ele m oa Notes 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 The Vccro our referred to in these specifications refers to instantaneous VCCIO_OUT 3 For VIN between 0 V and Vccro our Measured when the driver is tri stated 4 Vr and Voy may experience excursions above Vccro our However input signal drivers must comply with the signal quality specifications Table 55 GTL Signal Group and Open Drain Signal Group DC Specifications Symbol Parameter Min Max Units Notes Input Low Voltage TAP except Vit TOK ge E Vcc o_TERM 0 6 V 2 Input High Voltage TAP except Vin TOK 4 get E Vecio_term 0 72 V 2 4 VIL Input Low Voltage TCK Vccio TERM 0 4 V 2 Vin Input High Voltage TCK Vccio TERM 0 8 T V 2 4 Vuysteresis Hysteresis Voltage Vecio_term 0 2 V Ron Buffer on Resistance TDO 12 28 Q VIL Input Low Voltage other GTL Vccro_term 0 6 V 2 continued Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 106
27. Mode Impedance must be present when the Receiver terminations are first enabled to ensure that the Receiver Detect occurs properly Compensation of this impedance can start immediately and the 15 Rx Common Mode Impedance constrained by RLRX CM to 50 2 20 must be within the specified range by the time Detect is entered 6 Low impedance defined during signaling Parameter is captured for 5 0 GHz by RLTX DIFF 7 8 1 Platform Environment Control Interface PECI DC Characteristics The PECI interface operates at a nominal voltage set by Vccio term The set of DC electrical specifications shown in the following table is used with devices normally operating from a Vccio term interface supply Vecio_TERM Nominal levels will vary between processor families All PECI devices will operate at the Vccio term level determined by the processor installed in the system Table 57 Platform Environment Control Interface PECI DC Electrical Limits Symbol Definition and Conditions Min Max Units Notes Rup Internal pull up resistance 15 45 Q 3 Vin Input Voltage Range 0 15 Vero ui V _ Hysteresis 0 1 Vhysteresis y Vccio TERM N A V T continued Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron March 2015 Order No 328897 010 Processor Family Datasheet Volume 1 of 2 107 7 8 2 Figure 23 Processor Electrical Specifications
28. Multiple 1280x1024 60 Hz PC6 Multiple 1920x1080 60 Hz PC3 Multiple 1920x1200 60 Hz PC3 Multiple 1920x1440 60 Hz PC3 Multiple 2048x1536 60 Hz PC3 Multiple 2560x1600 60 Hz PC2 Multiple 2560x1920 60 Hz PC2 Multiple 2880x1620 60 Hz PC2 Multiple 2880x1800 60 Hz PC2 Multiple 3200x1800 60 Hz PC2 Multiple 3200x2000 60 Hz PC2 Multiple 3840x2160 60 Hz PC2 Multiple 3840x2160 30 Hz PC2 Multiple 4096x2160 24 Hz PC2 Notes 1 For multiple display cases the resolution listed is the highest native resolution of all enabled displays and PSR is internally disabled that is dual display with one 800x600 60 Hz display and one 2560x1600 60 Hz display will result in a deepest available package C state of PC2 2 Microcode Update rev 00000010 or newer must be used Integrated Memory Controller IMC Power Management The main memory is power managed during normal operation and in low power ACPI Cx states Disabling Unused System Memory Outputs Any system memory SM interface signal that goes to a memory module connector in which it is not connected to any actual memory devices such as SO DIMM connector is unpopulated or is single sided is tri stated The benefits of disabling unused SM S ignals are Reduced power consumption Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family Datasheet Volume 1 of 2 60 March 2015 Order No 328897 010
29. Order No 328897 010 Processor Ball and Signal Information Processor 9 0 Note Table 62 Processor Ball and Signal Information This chapter provides processor ball information The following table provides the ball list by signal name References to SA_ECC_CB 7 0 and SB_ECC_CB 7 0 are for processor SKUs that support ECC These signals are reserved on the Desktop 4th Generation Intel Core processor family Processor Ball List by Signal Name Signal Name Ball Signal Name Ball Signal Name Ball BCLKN V4 CFG3 W38 DDID_TXDN1 B16 BCLKP V5 CFG4 V39 DDID_TXDN2 C17 BPM 0 G39 CFG5 U39 DDID TXDN3 B18 BPM 1 J39 CFG6 U40 DDID_TXDPO B15 BPM 2 G38 CFG V38 DDID TXDP1 A16 BPM 3 H37 CFG8 T40 DDID_TXDP2 B17 BPM 4 H38 CFG9 Y35 DDID TXDP3 A18 BPM 5 J38 DBR G40 DISP_INT D18 BPM 6 K39 DDIB_TXBNO F17 DMI RXNO T3 BPM 7 K37 DDIB_TXBN1 G18 DMI_RXN1 V1 CATERR M36 DDIB_TXBN2 H19 DMI_RXN2 V2 CFG_RCOMP H40 DDIB_TXBN3 G20 DMI_RXN3 W3 CFGO AA37 DDIB_TXBPO E17 DMI_RXPO U3 CFG1 Y38 DDIB_TXBP1 F18 DMI RXP1 Ul CFG10 AA34 DDIB_TXBP2 G19 DMI_RXP2 W2 CFG11 V37 DDIB_TXBP3 F20 DMI_RXP3 Y3 CFG12 Y34 DDIC_TXCNO E19 DMI_TXNO AA5 CFG13 U38 DDIC_TXCN1 D20 DMI_TXN1 AB4 CFG14 W34 DDIC_TXCN2 E21 DMI TXN2 ACA CFG15 V35 DDIC_TXCN3 D22 DMI_TXN3 AC2 CFG16 Y37 DDIC_TXCPO D19 DMI_TXPO AA4 CFG17 Y36 DDIC_TXCP1 C20 DMI TXP1 AB3 CFG18 W36 DDIC_TXCP2 D21 D
30. Pentium Processor Family and Desktop Intel Celeron March 2015 Processor Family Datasheet Volume 1 of 2 Order No 328897 010 11 m n tel Processor Introduction e Intel Advanced Vector Extensions 2 0 Intel AVX2 e Intel Advanced Encryption Standard New Instructions Intel AES NI e PCLMULQDQ Instruction e Intel Secure Key e Intel Transactional Synchronization Extensions New Instructions Intel TSX NI e PAIR Power Aware Interrupt Routing e SMEP Supervisor Mode Execution Protection e Enhanced Intel Speedstep Technology Note The availability of the features may vary between processor SKUs 1 2 Interfaces The processor supports the following interfaces e DDR3 DDR3L e Direct Media Interface DMI e Digital Display Interface DDI e PCI Express 1 3 Power Management Support Processor Core e Full support of ACPI C states as implemented by the following processor C states CO C1 C1E C3 C6 C7 e Enhanced Intel SpeedStep Technology System e S0 S3 S4 S5 Memory Controller e Conditional self refresh e Dynamic power down PCI Express e LOs and Li ASPM power management capability DMI e LOs and Li ASPM power management capability Processor Graphics Controller e Intel Rapid Memory Power Management Intel RMPM e Intel Smart 2D Display Technology Intel S2DDT e Graphics Render C state RC6 Desktop 4th Generation Intel Core Processor
31. THERMTRIP IVR_ERROR CMOS Output Single ended GTL CATERR Single ended Asynchronous PM_SYNC RESET PWRGOOD PWR_DEBUG CMOS Input Single ended Asynchronous Bi PECI directional Single ended GTL Bi directional CFG 19 0 Single ended Analog Input SM_RCOMP 2 0 Voltage Regulator Single ended CMOS Input VR_READY Single ended CMOS Input VIDALERT Single ended Open Drain Output VIDSCLK Single ended GTL Input Open VIDSOUT Drain Output Differential Analog Output VCC_SENSE VSS_SENSE Power Ground Other Single ended Power VCC VDDQ Ground VSS VSS_NCTF 3 No Connect RSVD RSVD_NCTF continued Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family Datasheet Volume 1 of 2 100 March 2015 Order No 328897 010 Electrical Specifications Processor n te Signal Group Type Signals Test Point RSVD_TP Other SKTOCC PCI Express Graphics Differential PCI Express Input PEG_RXP 15 0 PEG_RXN 15 0 Differential PCI Express Output PEG_TXP 15 0 PEG_TXN 15 0 Single ended Analog Input PEG_RCOMP Digital Media Interface DMI Differential DMI Input DMI_RXP 3 0 DMI_RXN 3 0 Differential DMI Output DMI_TXP 3 0 DMI_TXN 3 0 Digital Display Interface Differential DDI Output DDIB_TXP 3 0 DDIB_TXN 3 0 D
32. Table 26 5 4 Note Digital Thermal Sensor DTS 1 1 Thermal Solution Performance Above TCONTROL Processor Wo at DTS Wo at DTS 1 Wo at DTS 1 Wea at DTS 1 TDP TconrRoL 2 At System At System At System TAMBIENT At System TAMBIENT TAMBIENT MAX TAMBIENT MAX MAX 50 C MAX 30 C 40 C 45 C 88 W 0 619 0 387 0 330 0 273 84 W 0 627 0 390 0 330 0 270 65W 0 793 0 482 0 405 0 328 45 W 1 207 0 699 0 588 0 477 35 W 1 406 0 753 0 610 0 467 Notes 1 Wca at DTS TconrRoL is applicable to systems that have an internal Trise Troom temperature to Processor cooling fan inlet of less than 10 C In case the expected Trise is greater than 10 C a correction factor should be used as explained below For each 1 C Trise above 10 C the correction factor CF is defined as CF 1 7 processor TDP 2 Example A chassis Trise assumption is 12 C for a 95 W TDP processor CF 1 7 95 W 0 018 W For Trrse gt 10 C Uca at TcontroL Value provide in Column 2 Trise 10 CF Wca 0 627 12 10 0 018 0 591 C W In this case the fan speed should be set slightly higher equivalent to Wc 0 591 C W Fan Speed Control Scheme with Digital Thermal Sensor DTS 2 0 To simplify processor thermal specification compliance the processor calculates the DTS Thermal Profile from Tconrno Offset TCC Activation Temperature TDP and the Thermal Margin Slope provid
33. Volume 1 of 2 Order No 328897 010 55 n te Processor Power Management For package C states the processor is not required to enter CO state before entering any other C state Entry into a package C state may be subject to auto demotion that is the processor may keep the package in a deeper package C state than requested by the operating system if the processor determines using heuristics that the deeper C state results in better power performance The processor exits a package C state when a break event is detected Depending on the type of break event the processor does the following e If a core break event is received the target core is activated and the break event message is forwarded to the target core If the break event is not masked the target core enters the core CO state and the processor enters package CO state If the break event is masked the processor attempts to re enter its previous package state e Ifthe break event was due to a memory access or snoop request But the platform did not request to keep the processor in a higher package C state the package returns to its previous C state And the platform requests a higher power C state the memory access or snoop request is serviced and the package remains in the higher power C state The following table shows package C state resolution for a dual core processor The following figure summarizes package C state transi
34. Volume 1 of 2 March 2015 50 Order No 328897 010 Power Management Processor Table 15 Table 16 Table 17 4 2 4 2 1 Direct Media Interface DMI States State Description LO Full on Active transfer state LOs First Active Power Management low power state Low exit latency Li Lowest Active Power Management Longer exit latency L3 Lowest power state power off Longest exit latency G S and C Interface State Combinations Global Sleep S Processor Processor System Clocks Description G State Package C State State State GO SO CO Full On On Full On GO S0 C1 C1E Auto Halt On Auto Halt GO SO C3 Deep Sleep On Deep Sleep GO SO C6 C7 Deep Power On Deep Power down down Gi S3 Power off Off except RTC Suspend to RAM G1 S4 Power off Off except RTC Suspend to Disk G2 S5 Power off Off except RTC Soft Off G3 NA Power off Power off Hard off D S and C Interface State Combination Graphics Sleep S Package C Description Adapter D State State State DO S0 CO Full On Displaying DO S0 C1 C1E Auto Halt Displaying DO S0 C3 Deep sleep Displaying DO S0 C6 C7 Deep Power down Displaying D3 S0 Any Not displaying D3 S3 N A Not displaying Graphics Core is powered off D3 S4 N A Not displaying suspend to disk Processor Core Power Management While executing code Enhanced Intel Spe
35. WRITE Command delay e tRP PRECHARGE Command Period e CWL CAS Write Latency e Command Signal modes 1N indicates a new command may be issued every clock and 2N indicates a new command may be issued every 2 clocks Command launch mode programming depends on the transfer rate and memory configuration Table 6 DDR3 DDR3L System Memory Timing Support Segment Transfer Rate tCL tCK tRCD tRP CWL DPC CMD MT s tCK tCK tCK Mode 1N 2N 1333 8 9 8 9 8 9 7 2N All segments 1N 2N 1600 10 11 10 11 10 11 8 2N Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family Datasheet Volume 1 of 2 20 March 2015 Order No 328897 010 n e Interfaces Processor n tel Note 2 1 3 Note Figure 2 System memory timing support is based on availability and is subject to change System Memory Organization Modes The Integrated Memory Controller IMC supports two memory organization modes single channel and dual channel Depending upon how the DIMM Modules are populated in each memory channel a number of different configurations can exist Single Channel Mode In this mode all memory cycles are directed to a single channel Single channel mode is used when either Channel A or Channel B DIMM connectors are populated in any order but not both Dual Channel Mode Intel Flex Memory Te
36. be disabled and any DLL circuitry related ONLY to unused signals should be disabled The input path must be gated to prevent spurious results due to noise on the unused signals typically handled automatically when input receiver is disabled DRAM Running Average Power Limitation RAPL RAPL is a power and time constant pair DRAM RAPL defines an average power constraint for the DRAM domain Constraint is controlled by the PCU Platform entities PECI or in band power driver can specify a power limit for the DRAM domain PCU continuously monitors the extant of DRAM throttling due to the power limit and rebudgets the limit between DIMMs DDR Electrical Power Gating EPG The DDR I O of the processor supports Electrical Power Gating DDR EPG while the processor is at C3 or deeper power state In C3 or deeper power state the processor internally gates Vppo for the majority of the logic to reduce idle power while keeping all critical DDR pins such as SM_DRAMRST CKE and VREF in the appropriate state In C7 the processor internally gates Vccio_term for all non critical state to reduce idle power In S3 or C state transitions the DDR does not go through training mode and will restore the previous training information PCI Express Power Management e Active power management is supported using LOs and Li states e All inputs and outputs disabled in L2 L3 Ready state Direct Media Interface DMI Power Management Active power man
37. components that are included in the package 8 6 Processor Materials The following table lists some of the package components and associated materials Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 110 Order No 328897 010 m Package Mechanical Specifications Processor n tel Table 60 Processor Materials Component Material Integrated Heat Spreader IHS Nickel Plated Copper Substrate Fiber Reinforced Resin Substrate Lands Gold Plated Copper 8 7 Processor Markings The following figure shows the top side markings on the processor This diagram aids in the identification of the processor Figure 25 Processor Top Side Markings GRP1LINE1 GRP1LINE2 GRP1LINE3 GRP1LINE4 Production SSPEC Se GRP1LINE1 i M C YY GRP1LINE2 BRAND PROC GRP1LINE3 SSPEC SPEED GRP1LINE4 COUNTRY OF ORIGIN GRPILINES FPO e4 8 8 Processor Land Coordinates The following figures show the bottom view of the processor package Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family March 2015 Datasheet Volume 1 of 2 Order No 328897 010 111 Processor Package Mechanical Specifications Figure 26 Processor Package Land Coordinates QQQQQQQQ QQQQQQQSQ Q0
38. daa dea a nan ka a aa a 33 8 HDMI OVGVICW s ik 34 9 PECI Host Clients Connection Exampl k i xx xisli kl naka lena kel ela E n al aa a 38 10 Device to Domain Mapping StfU ct U Ss s sk n meme nne 42 11 Processor Power States sul kaka ka kas tkt n kk aan da a Rer a k b l ass kl k DES M kak MEER a REA VERE 49 12 Idle Power Management Breakdown of the Processor Cores sss 52 13 Thread and Core C State Entry and Exit aaraa 53 14 Package C State Entry and Exit leise n l eken pex kaka Ra W k sa ta saxa ee na ak aja a nada a a aj taa sana ei 57 15 Thermal Test Vehicle Thermal Profile for Processor PCG 2013D and PCG 2014 68 16 Thermal Test Vehicle Thermal Profile for Processor PCG 2013C ceceeeeeeeeeee eee eeeeeaee 69 17 Thermal Test Vehicle Thermal Profile for Processor PCG 2013B cceeeeeeeeeeeeeee teenies 70 18 Thermal Test Vehicle Thermal Profile for Processor PCG 2013A sese 72 19 Thermal Test Vehicle TTV Case Temperature Tcase Measurement Location 73 20 Digital Thermal Sensor DTS 1 1 Definition Points esses 74 21 Digital Thermal Sensor DTS Thermal Profile Definition essem 76 22 Package Power Control iin rrt nea kelan le tie as v rcx Mx Ra FF RE TER e EFE ANKE RE 84 23 Input Device Hysteresis s
39. deeper state however has allowed a package C6 state In package C3 state the L3 shared cache is valid Package C6 State A processor enters the package C6 low power state when e At least one core is in the C6 state e The other cores are in a C6 or deeper power state and the processor has been granted permission by the platform e Ifthe cores are requesting C7 state but the platform is limiting to a package C6 state the last level cache in this case can be flushed In package C6 state all cores have saved their architectural state and have had their core voltages reduced to zero volts It is possible the L3 shared cache is flushed and turned off in package C6 state If at least one core is requesting C6 state the L3 cache will not be flushed Package C7 State The processor enters the package C7 low power state when all cores are in the C7 state In package C7 the processor will take action to remove power from portions of the system agent Core break events are handled the same way as in package C3 or C6 state Note C7 state may not be available on all SKUs Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 58 Order No 328897 010 Power Management Processor n tel Note 4 2 6 Note Table 20 Package C6 state is the deepest C state supported on discrete graphics sys
40. eisiu sarma nna kun tes rase ek D a Gade wedded ci ERR exa e kd a ea k ke e ba a 108 24 Processor Package Assembly SKeth 0 cccctcecetsncscecdneaeasseseecncnecsteecededdacasaecataedtsaeanens 109 25 Processor TopsSide Markings iiie ods sanes base ER und media wa QURE cina E RR Ra e aa RA 111 26 Processor Package Land C rrdihal68x say ai sesa a kesa na h nana aa iaaio kala emen nnns 112 27 2014 Processor Package Land Pin Side Components 113 Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 6 Order No 328897 010 m Tables Processor n tel Tables 1 pese ken Ke diye e hall cere bu Dv a bela be Ka k e Saya D nl De eos A KERO Ny e xek 13 2 Related Documents n ka dl akan ancna k na kin Dawn ail W ba anan Dia siae ka ue da pa ark se aa ka an 16 3 Processor DIMM Support by PrOdU Ct sikak ak l ak sk l k kil aka k baka aa lk alacak ay a k aa a ca aj ai al 19 4 Supported UDIMM Module Configurat OnS l khk khkhkhkwjkill kk kk kk kk kk kk kk kaka kk kk kak kak kk kk a kk kk k 19 5 Supported SO DIMM Module Configurations AIO Only sese 20 6 DDR3 DDR3L System Memory Timing Support ssssssssssssseene meme 20 7 PCI Express Supported Configurations in Desktop Products cccccceeeee
41. execution cores Each execution core has an instruction cache data cache and 256 KB L2 cache All execution cores share the L3 cache Processor Graphics Intel Processor Graphics A unit of DRAM corresponding to four to eight devices in parallel ignoring ECC These Rang devices are usually but not always mounted on a single side of a SO DIMM SCI System Control Interrupt SCI is used in the ACPI protocol SF Strips and Fans SMM System Management Mode SMX Safer Mode Extensions Storage Conditions A non operational state The processor may be installed in a platform in a tray or loose Processors may be sealed in packaging or exposed to free air Under these conditions processor landings should not be connected to any supply voltages have any I Os biased or receive any clocks Upon exposure to free air that is unsealed packaging or a device removed from packaging material the processor must be handled in accordance with moisture sensitivity labeling MSL as indicated on the packaging material continued Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron March 2015 Order No 328897 010 Processor Family Datasheet Volume 1 of 2 15 Processor Introduction Term Description SVID Serial Voltage Identifi
42. memory Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 54 Order No 328897 010 Power Management Processor n tel Note 4 2 5 Core C6 State Individual threads of a core can enter the C6 state by initiating a P LVL3 I O read or an MWAIT C6 instruction Before entering core C6 state the core will save its architectural state to a dedicated SRAM Once complete a core will have its voltage reduced to zero volts During exit the core is powered on and its architectural state is restored Core C7 State Individual threads of a core can enter the C7 state by initiating a P_LVL4 I O read to the P BLK or by an MWAIT C7 instruction The core C7 state exhibits the same behavior as the core C6 state C7 state may not be available on all SKUs C State Auto Demotion In general deeper C states such as C6 state have long latencies and have higher energy entry exit costs The resulting performance and energy penalties become significant when the entry exit frequency of a deeper C state is high Therefore incorrect or inefficient usage of deeper C states have a negative impact on idle power To increase residency and improve idle power in deeper C states the processor supports C state auto demotion There are two C state auto demotion options e C7 C6 to C3 state e C7 C6 C3 To C1 state
43. of 2 108 March 2015 Order No 328897 010 n Package Mechanical Specifications Processor n tel 8 0 Figure 24 8 1 8 2 Package Mechanical Specifications The processor is packaged in a Flip Chip Land Grid Array package that interfaces with the motherboard using the LGA1150 socket The package consists of a processor mounted on a substrate land carrier An integrated heat spreader IHS is attached to the package substrate and core and serves as the mating surface for processor thermal solutions such as a heatsink The following figure shows a sketch of the processor package components and how they are assembled together The package components shown in the following figure include the following 1 Integrated Heat Spreader IHS Thermal Interface Material TIM Processor core die Package substrate Ur ww 9 Capacitors Processor Package Assembly Sketch Die TIM vas Substrate gt Capacitors LGA1150 Socket System Board gt Processor Component Keep Out Zone The processor may contain components on the substrate that define component keep out zone requirements A thermal and mechanical solution design must not intrude into the required keep out zones Decoupling capacitors are typically mounted to the land side of the package substrate Refer to the LGA1150 Socket Application Guide for keep out zones The location and quantity of package capacitors may change du
44. of the DIMM modules supported by the processor is dependent on the PCH SKU in the target platform Desktop PCH platforms support non ECC UDIMMs only All In One platforms AIO support SO DIMMs e Theoretical maximum memory bandwidth of 21 3 GB s in dual channel mode assuming 1333 MT s 25 6 GB s in dual channel mode assuming 1600 MT s e 1Gb 2Gb and 4Gb DDR3 DDR3L DRAM device technologies are supported Using 4Gb DRAM device technologies the largest system memory capacity possible is 32 GB assuming Dual Channel Mode with four x8 dual ranked DIMM memory configuration e Up to 64 simultaneous open pages 32 per channel assuming 8 ranks of 8 bank devices e Processor on die VREF generation for DDR DQ Read and Write as well as CMD ADD e Command launch modes of 1n 2n e On Die Termination ODT e Asynchronous ODT e Intel Fast Memory Access Intel FMA Just in Time Command Scheduling Command Overlap Out of Order Scheduling Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 18 Order No 328897 010 m Interfaces Processor n tel j 2 1 1 System Memory Technology Supported The Integrated Memory Controller IMC supports DDR3 DDR3L protocols with two independent 64 bit wide channels each accessing one or two DIMMs The type of memory supported by the processor is dep
45. power management topics Advanced Configuration and Power Interface ACPI States Processor Core Integrated Memory Controller IMC PCI Express Direct Media Interface DMI Processor Graphics Controller Figure 11 Processor Power States CO Active mode C1 Auto Halt C1E Auto Halt Low freq low voltage C3 L1 L2 caches flush clocks off C6 Save core states before shutdown C7 Similar to C6 L3 flush Note Power states availability may vary between the different SKUs Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron March 2015 Processor Family Datasheet Volume 1 of 2 Order No 328897 010 49 n te Processor Power Management 4 1 Advanced Configuration and Power Interface ACPI States Supported This section describes the ACPI states supported by the processor Table 11 System States State Description G0 SO Full On Mode Suspend to RAM STR Context saved to memory S3 Hot state is not supported by the G1 S3 Cold processor G1 S4 Suspend to Disk STD All power lost except wakeup on PCH G2 S5 Soft off All power lost except wakeup on PCH Total reboot G3 Mechanical off All power removed from system Table 12 Processor Core Package State Support State Description CO Active mode processor executing code C1 AutoHALT state C1E AutoHALT stat
46. protocol defined in Embedded Controller Support Provided by the PCH The temperature reported over PECI is always a negative value and represents a delta below the onset of thermal control circuit TCC activation as indicated by PROCHOT see Processor Temperature on page 78 Systems that implement fan speed control must be designed to use this data Systems that do not alter the fan speed only need to ensure the case temperature meets the thermal profile specifications Analysis indicates that real applications are unlikely to cause the processor to consume maximum power dissipation for sustained time periods Intel recommends that complete thermal solution designs target the Thermal Design Power TDP instead of the maximum processor power consumption The Adaptive Thermal Monitor feature is intended to help protect the processor in the event that an application exceeds the TDP recommendation for a sustained time period For more details on this feature see Adaptive Thermal Monitor on page 78 To ensure maximum flexibility for future processors systems should be designed to the Thermal Solution Capability guidelines even if a processor with lower power dissipation is currently planned Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family March 2015 Datasheet Volume 1 of 2 Order No 328897 010 65 n n tel Processor Thermal Management Tabl
47. the VESA DisplayPort Standard Version 1 Revision 2 e The processor supports High bandwidth Digital Content Protection HDCP for high definition content playback over digital interfaces e The processor also integrates dedicated a Mini HD audio controller to drive audio on integrated digital display interfaces such as HDMI and DisplayPort The HD audio controller on the PCH would continue to support down CODECs and so on The processor Mini HD audio controller supports two High Definition Audio streams simultaneously on any of the three digital ports e The processor supports streaming any 3 independent and simultaneous display combination of DisplayPort HDMI DVI eDP VGA monitors with the exception of 3 simultaneous display support of HDMI DVI In the case of 3 simultaneous displays two High Definition Audio streams over the digital display interfaces are supported e Each digital port is capable of driving resolutions up to 3840x2160 at 60 Hz through DisplayPort and 4096x2304 at 24 Hz 2560x1600 at 60 Hz using HDMI e DisplayPort Aux CH DDC channel Panel power sequencing and HPD are supported through the PCH Figure 6 Processor Display Architecture Transcoder eDP DP encoder SORT MUX Timing VDIP DPT SRID Display Transcoder A Pipe A DP HDMI Timing VDIP 3 DP Display i Transcoder B ir Pipe B DP HDMI Timing VDIP Panel Fitting Port Mux DP HDMI DVI Transcoder C DP DP HDMI HDMI
48. the processor can enter The following table lists display resolutions and deepest available package C State The display resolutions are examples using common values for blanking and pixel rate Actual results will vary The table shows the deepest possible Package C state System workload system idle and AC or DC power also affect the deepest possible Package C state Deepest Package C State Available Number of Displays 1 Native Resolution Deepest Available Package C State Single 800x600 60 Hz PC6 Single 1024x768 60 Hz PC6 Single 1280x1024 60 Hz PC6 Single 1920x1080 60 Hz PC6 Single 1920x1200 60 Hz PC6 Single 1920x1440 60 Hz PC6 Single 2048x1536 60 Hz PC6 Single 2560x1600 60 Hz PC6 Single 2560x1920 60 Hz PC3 continued Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron March 2015 Processor Family Datasheet Volume 1 of 2 Order No 328897 010 59 4 3 4 3 1 Processor Power Management Number of Displays 1 Native Resolution Deepest Available Package C State Single 2880x1620 60 Hz PC3 Single 2880x1800 60 Hz PC3 Single 3200x1800 60 Hz PC3 Single 3200x2000 60 Hz PC3 Single 3840x2160 60 Hz PC3 Single 3840x2160 30 Hz PC3 Single 4096x2160 24 Hz PC3 Multiple 800x600 60 Hz PC6 Multiple 1024x768 60 Hz PC6
49. the socket with a 20 MHz bandwidth oscilloscope 1 5 pF maximum probe capacitance and 1 MQ minimum impedance The maximum length of ground wire on the probe should be less than 5 mm Ensure external noise from the system is not coupled into the oscilloscope probe 4 Icc_max Specification is based on the Vcc loadline at worst case highest tolerance and ripple The Vcc specifications represent static and transient limits 6 The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE lands Voltage regulation feedback for voltage regulator circuits must also be taken from processor VCC_SENSE and VSS_SENSE lands 7 PSx refers to the voltage regulator power state as set by the SVID protocol 8 PCG is Platform Compatibility Guide previously known as FMB These guidelines are for estimation purposes only 9 Pmax is the maximum power the processor will dissipate as measured at VCC SENSE and VSS_SENSE lands The processor may draw this power for up to 10 ms before it regulates to PL2 Ui Table 49 Memory Controller Vppg Supply DC Voltage and Current Specifications Symbol Parameter Min Typ Max Unit Note Processor I O supply voltage for DDR3 DDR3L Typ 5 1 5 Typ 5 V 2 3 5 DC AC specification VDDQ DC AC DDR3 DDR3L Processor I O supply voltage for DDR3L DC Typ 5 1 35 Typ 5 V 2 3 AC specification VDDQ DC AC DDR3 DDR3L IcCmax_vppg DDR3 Max Current for Vppo Rail DD
50. vertices output by the VF function The VS unit produces an output vertex reference for every input vertex reference received from the VF unit in the order received Geometry Shader GS Stage The GS stage receives inputs from the VS stage Compiled application provided GS programs specifying an algorithm to convert the vertices of an input object into some output primitives For example a GS shader may convert lines of a line strip into polygons representing a corresponding segment of a blade of grass centered on the line Or it could use adjacency information to detect silhouette edges of triangles and output polygons extruding out from the edges Clip Stage The Clip stage performs general processing on incoming 3D objects However it also includes specialized logic to perform a Clip Test function on incoming objects The Clip Test optimizes generalized 3D Clipping The Clip unit examines the position of incoming vertices and accepts rejects 3D objects based on its Clip algorithm Strips and Fans SF Stage The SF stage performs setup operations required to rasterize 3D objects The outputs from the SF stage to the Windower stage contain implementation specific information required for the rasterization of objects and also supports clipping of primitives to some extent Windower IZ WIZ Stage The WIZ unit performs an early depth test which removes failing pixels and eliminates unnecessary processing overhead The Windower u
51. 000 0l o l o l J lo ol 2ch 0 9300 0 o o o l l Jo o OCh 0 6100 0 l0 l o l lo l 2Dh 0 9400 0 o o o l l Jo l 0Dh 0 6200 0 l0 l o l J ol 2Eh 0 9500 0 o o o l l J o 0Eh 0 6300 0 l0 l o l l l l 2Fh 0 9600 0 0 o 0 l l l l 0Fh 0 6400 0l o l l lo olo ol 30h 0 9700 0 o o lo lo Jo o J 10h 0 6500 0 0 1 1 0 0 0 1 31h 0 9800 0 o o lo lolo l iih 0 6600 0 l0 l l lo oll ol 32h 0 9900 0 o o lo lo l o 12h 0 6700 0 0 1 1 0 0 1 1 33h 1 0000 0 o o lo lo 1 1 13h 0 6800 0 l0 l l lo l lo ol 34h 1 0100 0 o o lo l Jo o J 14h 0 6900 0 0 1 1 0 1 0 1 35h 1 0200 0 o o lo l lo l l is5h 0 7000 0 0 1 1 0 1 1 0 36h 1 0300 0 o o lo l l o 6h 0 7100 0 0 1 1 0 1 1 1 37h 1 0400 0 o o lo l l l izh 0 7200 0 l0 l olo ol 38h 1 0500 0 o o l lo Jo o 18h 0 7300 0 l0 l olo l 39h 1 0600 0 o o l lo lo l 19h 0 7400 0 l0 l ol ol 3Ah 1 0700 0 o o l lo J o 4Ah 0 7500 0 0 1 1 1 0 1 1 3Bh 1 0800 0 0 0 1 1 0 1 1 1Bh 0 7600 0 0 1 11 1 0 0 3Ch 1 0900 O 0 O0 1 1 1 0 0 1Ch 0 7700 0 0 1 1 1 1 0 1 3Dh 1 1000 0 o o l L lo l 1Dh 0 7800 0 0 1 1 1 1 1 0 3Eh 1 1100 0 o o l l J o 1 Eh 0 7900 0 0 1 1 1 1 1 1 3Fh 1 1200 0 0 0 1 1 1 1 1 1Fh 0 8000 0 l lo o loo Jo
52. 1111 111 1 FFh 3 0400 1 1i J 0 1 1 1 J1 0J DEh 2 7100 1 1iJ 0 1 1 1 1 1 DFh 2 7200 1 1 J 1 0 0 0 0 0J EOh 2 7300 1 1iJ 1 0 0 0 0 1J Eth 2 7400 1 i J 1 0 0 0 1 0J E2h 2 7500 1 1 J 1 0 0 0 1 1 E3h 2 7600 1 1i J 1 0 0 1 0 0J E4h 2 7700 1 1i J 1 0 0 1 0 1J E5h 2 7800 1 i J 1 0 0 1 1 0J E6h 2 7900 1 1 1 0 0 1 1 1 E7h 2 8000 1 1i J 1 0 1 0 0 0J E8h 2 8100 1 i J 1 0 1 0 0 1J E9h 2 8200 1 1i J1J 0 1 0 1 0J EAh 2 8300 1 i J1J 0 1 0 1 1 EBh 2 8400 continued Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 98 Order No 328897 010 m Electrical Specifications Processor n te 7 4 7 5 Note Table 47 Reserved or Unused Signals The following are the general types of reserved RSVD signals and connection guidelines e RSVD these signals should not be connected e RSVD TP these signals should be routed to a test point e RSVD_NCTF these signals are non critical to function and may be left un connected Arbitrary connection of these signals to VCC VDDQ VSS or to any other signal including each other may result in component malfunction or incompatibility with future processors See Signal Description on page 86 for a pin listing of the processor and the location of all reserv
53. 23 VCC C28 VCC G25 VCC K25 VCC C29 VCC G26 VCC K27 VCC C30 VCC G27 VCC K29 VCC C31 VCC G28 VCC K31 VCC C32 VCC G29 VCC K33 VCC C33 VCC G30 VCC K35 VCC C34 VCC G31 VCC L15 VCC C35 VCC G32 VCC L16 VCC D25 VCC G33 VCC L17 VCC D27 VCC G34 VCC L18 VCC D29 VCC G35 VCC L19 VCC D31 VCC H23 VCC L20 VCC D33 VCC H25 VCC L21 VCC D35 VCC H27 VCC L22 VCC E24 VCC H29 VCC L23 VCC E25 VCC H31 VCC L24 VCC E26 VCC H33 VCC L25 VCC E27 VCC H35 VCC L26 VCC E28 VCC J21 VCC L27 continued continued continued Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 120 Order No 328897 010 Processor Ball and Signal Information Processor Signal Name Ball Signal Name Ball Signal Name Ball VCC L28 VDDQ AU20 VSS AC34 VCC L29 VDDQ AU24 VSS AC35 VCC L30 VDDQ AV10 VSS AC36 VCC L31 VDDQ AV11 VSS AC37 VCC L32 VDDQ AV13 VSS AC38 VCC L33 VDDQ AV18 VSS AC39 VCC L34 VDDQ AV23 VSS AC40 VCC M13 VDDQ AV8 VSS AC6 VCC M15 VDDQ AW16 VSS AC7 VCC M17 VDDQ AY12 VSS AD1 VCC M19 VDDQ AY14 VSS AD2 VCC M21 VDDQ AY9 VSS AD3 VCC M23 VIDALERT B37 VSS AD33 VCC M25 VIDSCLK C38 VSS AD36 VCC M27 VIDSOUT C37 VSS AD4 VCC M29 VSS A11 VSS AD5 VCC M33 VSS A13 VSS AD6 VCC M8 VSS A15 VSS A
54. 3 raw bit rate on the data pins of 8 0 GT s resulting in a real bandwidth per pair of 984 MB s using 128b 130b encoding to transmit data across this interface This also does not account for packet overhead and link maintenance Maximum theoretical bandwidth on the interface of 16 GB s in each direction simultaneously for an aggregate of 32 GB s when x16 Gen 3 e Hierarchical PCI compliant configuration mechanism for downstream devices e Traditional PCI style traffic asynchronous snooped PCI ordering Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron March 2015 Processor Family Datasheet Volume 1 of 2 Order No 328897 010 23 m n tel Processor Interfaces e PCI Express extended configuration space The first 256 bytes of configuration space aliases directly to the PCI Compatibility configuration space The remaining portion of the fixed 4 KB block of memory mapped space above that starting at 100h is known as extended configuration space e PCI Express Enhanced Access Mechanism Accessing the device configuration space in a flat memory mapped fashion e Automatic discovery negotiation and training of link out of reset e Traditional AGP style traffic asynchronous non snooped PCI X Relaxed ordering e Peer segment destination posted write traffic no peer to peer read traffic in Virtual Channel 0 DMI gt PCI Express Port 0
55. 4 SA_CKE2 AU22 SA_DQ30 AT35 RSVD T34 SA_CKE3 AU23 SA_DQ31 AW35 RSVD T35 SA CKNO AY16 SA DQ32 AY6 RSVD T8 SA CKN1 AV15 SA DQ33 AUG RSVD U8 SA CKN2 AW14 SA DQ34 AV4 RSVD w8 SA_CKN3 AY13 SA_DQ35 AU4 RSVD Y8 SA_CS 0 AU14 SA_DQ36 AW6 RSVD_TP A4 SA_CS 1 AV9 SA_DQ37 AV6 RSVD_TP AV1 SA_CS 2 AU10 SA_DQ38 AW4 RSVD_TP AW2 SA_CS 3 AW8 SA_DQ39 AY4 RSVD_TP B3 SA_DIMM_VREF AB39 SA_DQ4 AD37 DQ RSVD_TP C2 SA DQ40 AR1 SA DQO AD38 RSVD TP D1 SA_DQ41 AR4 SA_DQ1 AD39 RSVD_TP H16 SA_DQ42 AN3 SA_DQ10 AK38 RSVD_TP J10 SA_DQ43 AN4 SA DQ11 AK39 RSVD TP J12 SA DQ44 AR2 SA DQ12 AH37 RSVD TP J13 SA DQ45 AR3 SA DQ13 AH38 RSVD TP J16 SA DQ46 AN2 SA DQ14 AK37 RSVD TP J8 SA DQ47 AN1 SA_DQ15 AK40 RSVD_TP K11 SA DQ48 AL1 SA_DQ16 AM40 RSVD_TP K12 SA_DQ49 AL4 SA_DQ17 AM39 RSVD_TP K13 SA_DQ5 AD40 SA DQ18 AP38 RSVD TP K8 SA DQ50 AJ3 SA_D019 AP39 RSVD_TP N36 SA_DQ51 AJ4 SA_DQ2 AF38 RSVD_TP N38 SA_DQ52 AL2 continued continued continued Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron March 2015 Order No 328897 010 Processor Family Datasheet Volume 1 of 2 117 Processor Processor Ball and Signal Information Signal Name Ball Sign
56. 53W 3100 RPM Power 44 7 Core DHA B 0 495 C W 45 C y 0 51 71 5 C 4C GT2 45W1 45W 45W Active Short 3000RPM Power 48 5 DHA D 0 595 C W 45 C y 0 51 66 4 C 4C GT2 35W1 2013B 35W 35W Active Short 3999 RPM Power 48 5 DHA D 0 595 C W 45 C y 0 51 66 4 C 2C GT2 35W 35W 35W Active Short 3999 RPM Power 48 5 ene 0 595 C W Notes 1 TDP shown here 95W for example represents the maximum expected platform TDP in the next generation platform for this type of SKU This placeholder value is provided as a guideline for hardware design for the next generation platform 2 Platform Compatibility Guide PCG provides a design target for meeting all planned processor frequency requirements For more information refer to Voltage and Current Specifications on page 102 3 N A 4 These boundary conditions and performance targets are used to generate processor thermal specifications and to provide guidance for heatsink design Values are for the heatsink shown in the adjacent column are calculated at sea level and are expected to meet the Thermal Profile at TDP Tia is the local ambient temperature of the heatsink inlet air Airflow is through the heatsink fins with zero bypass for a passive heatsink RPM is fan revolutions per minute for an active heatsink Yca is the maximum target mean 3 sigma for the thermal characterization parameter For more information on the the
57. AT4 VSS B23 VSS AR27 VSS AT5 VSS B24 VSS AR30 VSS AT6 VSS B26 VSS AR31 VSS AT7 VSS B28 VSS AR32 VSS AT8 VSS B30 VSS AR33 VSS AT9 VSS B32 VSS AR34 VSS AU2 VSS B34 VSS AR35 VSS AU25 VSS B36 VSS AR36 VSS AU3 VSS B4 VSS AR37 VSS AU30 VSS B8 VSS AR38 VSS AU34 VSS C12 VSS AR39 VSS AU38 VSS C14 VSS AR40 VSS AU5 VSS C16 VSS AR5 VSS AU7 VSS C18 VSS AT1 VSS AV21 VSS C19 VSS AT10 VSS AV28 VSS C21 VSS AT11 VSS AV3 VSS C23 VSS AT12 VSS AV30 VSS C3 VSS AT13 VSS AV34 VSS C36 VSS AT14 VSS AV38 VSS C4 continued continued continued Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron March 2015 Order No 328897 010 Processor Family Datasheet Volume 1 of 2 123 Processor Processor Ball and Signal Information Signal Name Ball Signal Name Ball Signal Name Ball VSS C6 VSS F22 VSS H30 VSS Dii VSS F24 VSS H32 VSS D13 VSS F26 VSS H34 VSS D15 VSS F28 VSS H36 VSS D17 VSS F30 VSS H39 VSS D2 VSS F32 VSS H4 VSS D23 VSS F34 VSS H7 VSS D24 VSS F36 VSS H8 VSS D26 VSS F4 VSS H9 VSS D28 VSS F7 VSS J11 VSS D30 VSS G11 VSS J14 VSS D32 VSS G12 VSS J18 VSS D34 VSS G13 VSS J19 VSS D36 VSS G14 VSS J20 VSS D37 VSS G15 VSS J3 VSS D5 VSS G16 VSS J36 VSS D6 VSS G17 VSS J37 VSS D7 VSS G21 VSS J6 VSS D9 VSS G3 VSS J7 VSS E10 VSS G36 VS
58. CHOT is asserted by the system will result in the processor immediately transitioning to the minimum frequency and corresponding voltage using Frequency control Clock modulation is not activated in this case The TCC will remain active until the system de asserts PROCHOT Use of PROCHOT in input or bi directional mode can allow VR thermal designs to target maximum sustained current instead of maximum current Systems should still provide proper cooling for the Voltage Regulator VR and rely on PROCHOT only as a backup in case of system cooling failure The system thermal design should allow the power delivery circuitry to operate within its temperature specification even while the processor is operating at its Thermal Design Power THERMTRIP Signal Regardless of whether or not Adaptive Thermal Monitor is enabled in the event of a catastrophic cooling failure the processor will automatically shut down when the silicon has reached an elevated temperature refer to the THERMTRIP definition in Error and Thermal Protection Signals on page 92 THERMTRIP activation is independent of processor activity The temperature at which THERMTRIP asserts is not user configurable and is not software visible Digital Thermal Sensor Each processor execution core has an on die Digital Thermal Sensor DTS that detects the core s instantaneous temperature The DTS is the preferred method of monitoring processor die temperature because e tis located
59. CLK and VIDSCLK comprise a three Input GTL Output Open VIDSOUT signal serial synchronous interface used to transfer Drain VIDSCLK power management information between the Output Open Drain VIDALERT processor and the voltage regulator controllers Input CMOS Sense Signals Sense Signals Signal Name Description Direction Buffer Type VCC_SENSE VSS_SENSE voltage near the silicon VCC_SENSE and VSS_SENSE provide an isolated low impedance connection to the processor input Vcc voltage O and ground The signals can be used to sense or measure A Ground and Non Critical to Function NCTF Signals Ground and Non Critical to Function NCTF Signals Signal Name Description Direction Buffer Type VSS Processor ground node GND VSS_NCTF mechanical reliability Non Critical to Function These pins are for package Processor Internal Pull Up Pull Down Terminations Processor Internal Pull Up Pull Down Terminations Signal Name Pull Up Pull Down Rail Value BPM 7 0 Pull Up VCCIO_TERM 40 60 Q PREQ Pull Up VCCIO_TERM 40 60 Q TDI Pull Up VCCIO_TERM 30 70 Q TMS Pull Up VCCIO_TERM 30 70 Q CFG 17 0 Pull Up VCCIO_OUT 5 8 kQ CATERR Pull Up VCCIO_TERM 30 70 Q Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron March 2015 Order No 328897 010 Proce
60. D7 VCC P8 VSS A17 VSS AD8 VCC_SENSE E40 VSS A23 VSS AE33 VCCIO_OUT L40 VSS A5 VSS AE36 VCOMP_OUT P4 VSS A7 VSS AE37 VDDQ AJ12 VSS AA3 VSS AE40 VDDQ AJ13 VSS AA33 VSS AES VDDQ AJ15 VSS AA35 VSS AE8 VDDQ AJ17 VSS AA38 VSS AF1 VDDQ AJ20 VSS AA6 VSS AF33 VDDQ AJ21 VSS AA7 VSS AF36 VDDQ AJ24 VSS AA8 VSS AF4 VDDQ AJ25 VSS AB34 VSS AF5 VDDQ AJ28 VSS AB37 VSS AF8 VDDQ AJ29 VSS AB5 VSS AG33 VDDQ AJ9 VSS AB6 VSS AG36 VDDQ AT17 VSS AB7 VSS AG37 VDDQ AT22 VSS AC3 VSS AG38 VDDQ AU15 VSS AC33 VSS AG39 continued continued continued Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron March 2015 Order No 328897 010 Processor Family Datasheet Volume 1 of 2 121 Processor Processor Ball and Signal Information Signal Name Ball Signal Name Ball Signal Name Ball VSS AG40 VSS AK14 VSS AM2 VSS AG5 VSS AK18 VSS AM24 VSS AG8 VSS AK19 VSS AM27 VSS AH1 VSS AK24 VSS AM3 VSS AH2 VSS AK25 VSS AM30 VSS AH3 VSS AK26 VSS AM31 VSS AH33 VSS AK27 VSS AM32 VSS AH36 VSS AK28 VSS AM33 VSS AH4 VSS AK29 VSS AM34 VSS AH5 VSS AK30 VSS AM35 VSS AH8 VSS AK36 VSS AM36 VSS AJ11 VSS AK4 VSS AM4 VSS AJ14 VSS AK5 VSS AM5 VSS AJ16 VSS AK6 VSS AN10 VSS AJ18 VSS AK7 VSS AN11 VSS AJ19 VSS AK8 VSS AN14 VSS AJ22 VSS AK9 VSS AN16 VSS AJ23 VSS A
61. DIC_TXP 3 0 DDIC_TXN 3 0 DDID_TXP 3 0 DDID_TXN 3 0 Intel FDI Single ended CMOS Input FDI_CSYNC Single ended Asynchronous DISP_INT CMOS Input Differential FDI Output FDI_TXP 1 0 FDI_TXN 1 0 Notes 1 See Signal Description on page 86 for signal description details 2 SA and SB refer to DDR3 DDR3L Channel A and DDR3 DDR3L Channel B 7 6 Test Access Port TAP Connection Due to the voltage levels supported by other components in the Test Access Port TAP logic Intel recommends the processor be first in the TAP chain followed by any other components within the system A translation buffer should be used to connect to the rest of the chain unless one of the other components is capable of accepting an input of the appropriate voltage Two copies of each signal may be required with each driving a different voltage level The processor supports Boundary Scan JTAG IEEE 1149 1 2001 and IEEE 1149 6 2003 standards A few of the I O pins may support only one of those standards 7 7 DC Specifications The processor DC specifications in this section are defined at the processor pins unless noted otherwise See Signal Description on page 86 for the processor pin listings and signal definitions e The DC specifications for the DDR3 DDR3L signals are listed in the Voltage and Current Specifications section e The Voltage and Current Specifications section lists the DC specifications for the processor and are valid onl
62. Datasheet Volume 1 of 2 86 March 2015 Order No 328897 010 Signal Description Processor intel Signal Name Description Direction Buffer Table 32 Memory Channel B Signals Type SA RAS RAS Control Signal This signal is used with SA CAS and O SA_WE along with SA_CS to define the SRAM Commands DDR3 DDR3L CAS Control Signal This signal is used with SA_RAS and O SA_CAS SA_WE along with SA_CS to define the SRAM Commands DDR3 DDR3L Data Strobes SA_DQS 8 0 and its complement signal group SA_DQS 8 0 make up a differential strobe pair The data is captured at the I O SA DQSN 8 0 crossing point of SA DQS 8 0 and SA_DQS 8 0 during read DDR3 DDR3L and write transactions Data Bus Channel A data signal interface to the SDRAM data I O SA_DQ 63 0 _DE 63 0 bus DDR3 DDR3L SA MAT15 0 Memory Address These signals are used to provide the O _MA 15 0 multiplexed row and column address to the SDRAM DDR3 DDR3L SDRAM Differential Clock These signals are Channel A SDRAM Differential clock signal pairs The crossing of the O SA_CK 3 0 positive edge of SA_CK and the negative edge of its complement SA_CK are used to sample the command and control signals on DDR3 DDR3L the SDRAM Clock Enable 1 per rank These signals are used to e Initialize the SDRAMs during power up O SA_CKE 3 0 a e Power down SDRAM ranks DDR3 DDR3L e Place all SDRAM ranks into and out of self r
63. Desktop 4th Generation Intel Core Processor Family Desktop Intel9 Pentium Processor Family and Desktop Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 Order No 328897 010 You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel products described herein You agree to grant Intel a non exclusive royalty free license to any patent claim thereafter drafted which includes subject matter disclosed herein No license express or implied by estoppel or otherwise to any intellectual property rights is granted by this document All information provided here is subject to change without notice Contact your Intel representative to obtain the latest Intel product specifications and roadmaps The products described may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request Copies of documents which have an order number and are referenced in this document may be obtained by calling 1 800 548 4725 or visit http www intel com design literature htm Intel technologies features and benefits depend on system configuration and may require enabled hardware software or service activation Learn more at http www intel com or from the OEM or retailer No computer system can be absolutely secure Intel Hyper Threading Tech
64. E ec3 C3 Ww e C6 C7 W C6 C7 Power C W 1 2 W 1 3 W 1 4 4 5 9 w W 6 7 5 9 5 9 5 9 10 Pind ipi with 16 16 1 0 3 5 3 4 0 35 5 on page Graphics 72 Notes 1 The package C state power is the worst case power in the system configured as follows Not 100 tested Specified by design characterization a Memory configured for DDR3 1333 and populated with two DIMMs per channel b DMI and PCIe links are at L1 Specification at DTS 50 C and minimum voltage loadline Specification at DTS 50 C and minimum voltage loadline Specification at DTS 35 C and minimum voltage loadline These DTS values in Notes 2 4 are based on the TCC Activation MSR having a value of 100 see Processor Temperature on page 78 These values are specified at Vcc vax and Vyom for all other voltage rails for all processor frequencies Systems must be designed to ensure the processor is not to be subjected to any static Vcc and Icc combination wherein Vccp exceeds Vccp wax at specified Iccp See the loadline specifications Thermal Design Power TDP should be used for processor thermal solution design targets TDP is not the maximum power that the processor can dissipate TDP is measured at DTS 1 TDP is achieved with the Memory configured for DDR3 1333 and 2 DIMMs per channel Platform Compatibility Guide PCG previously known as FMB provides a design target for meeting all planned processor frequency requirements 5 1
65. Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 12 Order No 328897 010 Introduction Processor 1 4 1 5 1 6 Table 1 intel e Intel Seamless Display Refresh Rate Switching with eDP port e Intel Display Power Saving Technology Intel DPST Thermal Management Support e Digital Thermal Sensor e Adaptive Thermal Monitor e THERMTRIP and PROCHOT support e On Demand Mode e Memory Open and Closed Loop Throttling e Memory Thermal Throttling e External Thermal Sensor TS on DIMM and TS on Board e Render Thermal Throttling e Fan speed control with DTS Package Support The processor socket type is noted as LGA1150 The package is a 37 5 x 37 5 mm Flip Chip Land Grid Array FCLGA 1150 See the appropriate Processor Thermal Mechanical Design Guidelines and LGA1150 Socket Application Guide for complete details on the package Terminology Terminology Term Description APD Active Power down B D F Bus Device Function BGA Ball Grid Array BLC Backlight Compensation BLT Block Level Transfer BPP Bits per pixel CKE Clock Enable CLTM Closed Loop Thermal Management DDI Digital Display Interface DDR3 Third generation Double Data Rate SDRAM memory technology DLL Delay Locked Loop DMA Direct Memory Access DMI Direct Media Interface DP DisplayPort DTS Digital Thermal Sensor
66. In x2APIC mode APIC registers are accessed through Model Specific Register MSR interfaces In this mode the x2APIC architecture provides significantly increased processor addressability and some enhancements on interrupt delivery e Increased range of processor addressability in x2APIC mode Physical xAPIC ID field increases from 8 bits to 32 bits allowing for interrupt processor addressability up to 4G 1 processors in physical destination mode A processor implementation of x2APIC architecture can support fewer than 32 bits in a software transparent fashion Logical xAPIC ID field increases from 8 bits to 32 bits The 32 bit logical x2APIC ID is partitioned into two sub fields a 16 bit cluster ID and a 16 bit logical ID within the cluster Consequently 2 20 16 processors can be addressed in logical destination mode Processor implementations can support fewer than 16 bits in the cluster ID sub field and logical ID sub field in a software agnostic fashion e More efficient MSR interface to access APIC registers To enhance inter processor and self directed interrupt delivery as well as the ability to virtualize the local APIC the APIC register set can be accessed only through MSR based interfaces in x2APIC mode The Memory Mapped IO MMIO interface used by xAPIC is not supported in x2APIC mode Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron M
67. Is both VLWs and IPI For the above features BIOS must test the associated capability bit before attempting to access any of the above registers For more information refer to the Intel Trusted Execution Technology Measured Launched Environment Programming Guide 3 3 Intel Hyper Threading Technology Intel HT Technology The processor supports Intel Hyper Threading Technology Intel HT Technology that allows an execution core to function as two logical processors While some execution resources such as caches execution units and buses are shared each logical processor has its own architectural state with its own set of general purpose registers and control registers This feature must be enabled using the BIOS and requires operating system support Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 44 Order No 328897 010 n e Technologies Processor n tel 3 4 Note 3 5 Intel recommends enabling Intel HT Technology with Microsoft Windows 8 and Microsoft Windows 7 and disabling Intel HT Technology using the BIOS for all previous versions of Windows operating systems For more information on Intel HT Technology see http www intel com technology platform technology hyper threading Intel Turbo Boost Technology 2 0 The Intel Turbo Boost Technology 2 0 allows the process
68. K 0 15 Vppg Vin Input High Voltage SM DRAMPWROK 0 45 Vppg 1 0 Ron_UP D0 DDR3 DDR3L Data Buffer pull up Resistance 20 26 32 Ron_DN D0 DDR3 DDR3L Data Buffer pull down Resistance 20 26 32 RoDT D0 DDR3 DDR3L On die termination eguivalent resistance for data signals 38 50 62 Vopr Dc DDR3 DDR3L On die termination DC working point driver set to receive mode 0 45 Vpbo 0 5 Vppo 0 55 Vppo Ron_UP CK DDR3 DDR3L Clock Buffer pull up Resistance 20 26 32 5 11 13 Ron_DN CK DDR3 DDR3L Clock Buffer pull down Resistance 20 26 32 5 11 13 Row UP CMD DDR3 DDR3L Command Buffer pull up Resistance 15 20 25 5 11 13 Ron_DN CMD DDR3 DDR3L Command Buffer pull down Resistance 15 20 25 5 11 13 Ron_UP CTL DDR3 DDR3L Control Buffer pull up Resistance 19 25 31 5 11 13 continued Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family Datasheet Volume 1 of 2 104 March 2015 Order No 328897 010 Electrical Specifications Processor n te 2 3 Symbol Parameter Min Typ Max Units Notes DDR3 DDR3L Control 5 11 Row DN CTL Buffer pull down 19 25 31 Q 13 i Resist
69. L11 VSS AN18 VSS AJ26 VSS AL14 VSS AN19 VSS AJ27 VSS AL17 VSS AN22 VSS AJ30 VSS AL21 VSS AN23 VSS AJ31 VSS AL22 VSS AN24 VSS AJ32 VSS AL24 VSS AN27 VSS AJ33 VSS AL27 VSS AN30 VSS AJ34 VSS AL30 VSS AN36 VSS AJ35 VSS AL36 VSS AN37 VSS AJ36 VSS AL37 VSS AN40 VSS AJ37 VSS AL38 VSS AN5 VSS AJ40 VSS AL39 VSS AN6 VSS AJ5 VSS AL40 VSS AN7 VSS AJ8 VSS AL5 VSS AN8 VSS AK1 VSS AM1 VSS AN9 VSS AK10 VSS AM11 VSS AP1 VSS AK11 VSS AM14 VSS AP11 VSS AK12 VSS AM15 VSS AP14 VSS AK13 VSS AM19 VSS AP15 continued continued continued Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family Datasheet Volume 1 of 2 122 March 2015 Order No 328897 010 Processor Ball and Signal Information Processor Signal Name Ball Signal Name Ball Signal Name Ball VSS AP24 VSS AT15 VSS AV7 VSS AP27 VSS AT16 VSS AW26 VSS AP30 VSS AT2 VSS AW3 VSS AP36 VSS AT24 VSS AW30 VSS AP4 VSS AT25 VSS AW32 VSS AP5 VSS AT26 VSS AW34 VSS AR11 VSS AT27 VSS AW36 VSS AR14 VSS AT28 VSS AW7 VSS AR16 VSS AT29 VSS AY17 VSS AR17 VSS AT3 VSS AY23 VSS AR18 VSS AT30 VSS AY26 VSS AR19 VSS AT32 VSS AY27 VSS AR20 VSS AT34 VSS AY30 VSS AR21 VSS AT36 VSS AY5 VSS AR22 VSS AT38 VSS AY7 VSS AR23 VSS AT39 VSS B10 VSS AR24 VSS
70. M For bus N Structures for Domain A Bus N Root entry N Bus 0 Root entry O Root entry table Context entry 255 Context entry 0 Address Translation Context entry Table Structures for Domain B For bus 0 Intel VT d functionality often referred to as an Intel VT d Engine has typically been implemented at or near a PCI Express host bridge component of a computer system This might be in a chipset component or in the PCI Express functionality of a processor with integrated I O When one such Intel VT d engine receives a PCI Express transaction from a PCI Express bus it uses the B D F number associated with the transaction to search for an Intel VT d translation table In doing so it uses the B D F number to traverse the data structure shown in the above figure If it finds a valid Intel VT d table in this data structure it uses that table to translate the address provided on the PCI Express bus If it does not find a valid translation table for a given translation this results in an Intel VT d fault If Intel VT d translation is required the Intel VT d engine performs an N level table walk For more information refer to Intel Virtualization Technology for Directed I O Architecture Specification http download intel com technology computing vptech Intel r _VT_for_Direct_IO pdf Intel VT d Features The processor supports the following Intel VT d features Desk
71. MI_TXP2 AC5 CFG19 V36 DDIC_TXCP3 C22 DMI_TXP3 AC1 CFG2 AA36 DDID_TXDNO cis DP_RCOMP R4 continued continued continued Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron March 2015 Order No 328897 010 Processor Family Datasheet Volume 1 of 2 115 Processor Processor Ball and Signal Information Signal Name Ball Signal Name Ball Signal Name Ball DPLL_REF_CLKN W6 PEG_RXP14 K5 PEG_TXP4 C8 DPLL_REF_CLKP w5 PEG_RXP15 L4 PEG_TXP5 B7 EDP_DISP_UTIL E16 PEG_RXP2 E13 PEG_TXP6 A6 FC_K9 K9 PEG_RXP3 D12 PEG_TXP7 B5 FC_Y7 Y7 PEG_RXP4 E11 PEG TXP8 E1 FDI CSYNC D16 PEG RXP5 F10 PEG TXP9 F2 FDIO TXONO B14 PEG_RXP6 E9 PM_SYNC P36 FDIO_TXON1 C13 PEG RXP7 F8 PRDY L39 FDIO_TXOPO A14 PEG RXP8 D3 PREQ L37 FDIO_TXOP1 B13 PEG RXP9 E4 PROCHOT K38 IST_TRIGGER C39 PEG TXNO B12 PWR DEBUG N40 IVR ERROR R36 PEG TXN1 C11 PWRGOOD AB35 PECI N37 PEG TXN10 G2 RESET M39 PEG_RCOMP P3 PEG TXN11 H3 RSVD AB33 PEG RXNO F15 PEG TXN12 J2 RSVD AB36 PEG RXN1 E14 PEG TXN13 K3 RSVD AB8 PEG_RXN10 F6 PEG_TXN14 M3 RSVD AC8 PEG_RXN11 G5 PEG TXN15 L2 RSVD AK20 PEG RXN12 H6 PEG TXN2 D10 RSVD AL20 PEG RXN13 J5 PEG TXN3 C9 RSVD AT40 PEG_RXN14 K6 PEG_TXN4 D8 RSVD AU1 PEG_RXN15 L5 PEG_TXN5 C7 RSVD AU27 PEG_RXN2 F13 PEG TXN6 B6 RSVD AU39 PEG RXN3
72. Order No 328897 010 Electrical Specifications Processor n te Symbol Parameter Min Max Units Notes V H Input High Voltage other GTL Vecio_term 0 72 B V 2 4 Ron Buffer on Resistance CFG BPM 16 24 Q Ron Buffer on Resistance other GTL 12 28 Q _ lu Input Leakage Current 150 HA 3 Notes 1 Unless otherwise noted all specifications in this table apply to all processor frequencies 2 The Vccro our referred to in these specifications refers to instantaneous VCCIO_OUT 3 For VIN between 0 V and Vccio_term Measured when the driver is tri stated 4 Vin and Voy may experience excursions above Vccio_ term However input signal drivers must comply with the signal quality specifications Table 56 PCI Express DC Specifications Symbol Parameter Min Typ Max Units Notes caisse DC Differential Tx Impedance Gen 1 80 _ 120 Q 1 6 Only DC Differential Tx Impedance Gen 2 and ZTx DIFF DC B 120 Q 1 6 Gen 3 ZRX DC DC Common Mode Rx Impedance 40 60 Q 1 4 5 Piet tas DC Differential Rx Impedance Geni 80 _ 120 Q 1 Only PEG_RCOMP Comp Resistance 24 75 25 25 25 Q 2 3 Notes 1 See the PCI Express Base Specification for more details 2 PEG_RCOMP should be connected to Vcomp our through a 25 2 1 resistor 3 Intel allows using 24 9 Q 1 resistors 4 DC impedance limits are needed to ensure Receiver detect 5 The Rx DC Common
73. POWER_LIMIT_2 TURBO_POWER_LIMIT MSR 0610h bits 46 32 Occasional brief power excursions may occur for periods of less than 10 ms over PL2 Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 82 Order No 328897 010 a Thermal Management Processor n tel The processor monitors its own power consumption to control turbo behavior assuming the following The power monitor is not 100 tested across all processors The Power Limit 2 PL2 control is only valid for power levels set at or above TDP and under workloads with similar activity ratios as the product TDP workload This also assumes the processor is working within other product specifications Setting power limits PL1 or PL2 below TDP are not ensured to be followed and are not characterized for accuracy Under unknown work loads and unforeseen applications the average processor power may exceed Power Limit 1 PL1 Uncharacterized workloads may exist that could result in higher turbo frequencies and power If that were to happen the processor Thermal Control Circuitry TCC would protect the processor The TCC protection must be enabled by the platform for the product to be within specification An illustration of Intel Turbo Boost Technology power control is shown in the following sections and figures Multiple controls operate simult
74. Q PCLMULQDQ is a Single Instruction Multiple Data SIMD instruction that computes the 128 bit carry less multiplication of two 64 bit operands without generating and propagating carries Carry less multiplication is an essential processing component of several cryptographic systems and standards Hence accelerating carry less multiplication can significantly contribute to achieving high speed secure computing and communication Intel Secure Key The processor supports Intel Secure Key formerly known as Digital Random Number Generator DRNG a software visible random number generation mechanism supported by a high quality entropy source This capability is available to programmers through the RDRAND instruction The resultant random number generation capability is designed to comply with existing industry standards in this regard ANSI X9 82 and NIST SP 800 90 Some possible usages of the RDRAND instruction include cryptographic key generation as used in a variety of applications including communication digital signatures secure storage and so on 3 7 Intel Transactional Synchronization Extensions New Instructions Intel TSX NI Intel Transactional Synchronization Extensions New Instructions Intel TSX NI Intel TSX NI provides a set of instruction extensions that allow programmers to specify regions of code for transactional synchronization Programmers can use these Desktop 4th Generation Intel Core Processor Fam
75. QoS guarantees Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 40 Order No 328897 010 En Technologies Processor n tel e Descriptor Table Exiting Descriptor table exiting allows a VMM to protect a guest operating system from an internal malicious software based attack by preventing relocation of key system data structures like IDT interrupt descriptor table GDT global descriptor table LDT local descriptor table and TSS task segment selector AVMM using this feature can intercept by a VM exit attempts to relocate these data structures and prevent them from being tampered by malicious software Intel VT d Objectives The key Intel VT d objectives are domain based isolation and hardware based virtualization A domain can be abstractly defined as an isolated environment in a platform to which a subset of host physical memory is allocated Intel VT d provides accelerated I O performance for a virtualized platform and provides software with the following capabilities e I O device assignment and security for flexibly assigning I O devices to VMs and extending the protection and isolation properties of VMs for I O operations e DMA remapping for supporting independent address translations for Direct Memory Accesses DMA from devices e Interrupt remapping for supporti
76. R3L zi 2 5 A Average Current for Vppq Iccava vpbQ Standby Rail during Standby 12 20 mA 4 Notes 1 The current supplied to the SO DIMM modules is not included in this specification Includes AC and DC error where the AC noise is bandwidth limited to under 20 MHz No reguirement on the breakdown of AC versus DC noise Measured at 50 C This specification applies to desktop processors Ma AE Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family March 2015 Datasheet Volume 1 of 2 Order No 328897 010 103 intel Table 50 Table 51 VCCIO_OUT VCOMP_OUT and VCCIO_TERM Processor Electrical Specifications Symbol Parameter Typ Max Units Notes VCCIO_OUT ICCIO_OUT Termination Voltage Maximum External Load 1 0 300 mA VCOMP_OUT Termination Voltage 1 0 VCCIO_TERM Termination Voltage 1 0 V Notes 1 VCOMP 2 Internal processor power for signal termination OUT may only be used to connect to PEG RCOMP and DP RCOMP DDR3 DDR3L Signal Group DC Specifications Symbol Parameter Typ Max Units Notes VIL Input Low Voltage Vppo 2 0 43 Vppo V 2 4 11 Vin Input High Voltage 0 57 Vppq Vpoo 2 V 3 11 VIL Input Low Voltage SM DRAMPWRO
77. RADA A edad a EAM RUN I E dE 90 37 Direct Media Interface DMI Processor to PCH Serial Interface esses 90 38 Phase Locked Loop PLL Signals i oiii tune nna nnn rented kn Waaa ak naa kh an Ra Xx AA FON AA 91 39 Testability Signals tirer etr er ea t eret bur xa ana la Sx ad kx E add Dade bal dua ad PDA ened 91 40 Error and Thermal Protection Signals aaa 92 41 Power SEQUENCING Signals eese ds hek nda kk k kek b kek pie darka k ka DE rata atri ar j s aja ERRENA 92 42 Processor Power Signals ritmi v deri kama dika PERRA MERE XR DE e a ER aa dies ka a aka k va 93 43 Sense Signals irte tte kaka b a banan ada va ban LA DERE RA Wina b bav da naa b la b n Da b ka n di dak d D RN 93 44 Ground and Non Critical to Function NCTF Signals kk kk eee eens e 93 45 Processor Internal Pull Up Pull Down Terminations cesesseee nme 93 46 Voltage Regulator VR 12 5 Voltage Identification a aaa kk kk kk kk kk kk kk KK AKA 95 47 Signal GroU S aa siy gya d l W ada yek na an cing aida cikla dana D kala a ba daa daka W kak Sanaa l ta aa 99 48 Processor Core Active and Idle Mode DC Voltage and Current Specifications 102 49 Memory Controller Vppg Supply DC Voltage and Current Specifications 103 50 VCCIO OUT VCOMP OUT and VCCIO TERM kk kk nemen nnne 104 51 DDR3 DDR3L Signal Group DC Speci
78. RCOMP2 R2 SB DQ50 AL6 SB_ECC_CBO AM26 SM_VREF AB38 SB DQ51 AL7 SB ECC CB1 AM25 SSC DPLL REF U5 SB DQ52 AM10 SB ECC CB2 AP25 CLKN SB DQ53 AL10 SB ECC CB3 AP26 SSC DPLL REF U6 CLKP SB_DQ54 AM6 SB_ECC_CB4 AL26 TCK D39 SB_DQ55 AM7 SB_ECC_CB5 AL25 TDI F38 SB_DQ56 AH6 SB_ECC_CB6 AR26 TDO F39 SB_DQ57 AH7 SB_ECC_CB7 AR25 TESTLO_N5 N5 SB DQ58 AE6 SB MAO AL19 TESTLO P6 P6 SB DQ59 AE7 SB MA1 AK23 THERMTRIP F37 SB_DQ6 AG34 SB MA10 AP18 TMS E39 SB DQ60 AJ6 SB MA11 AY25 TRST E37 SB_DQ61 AJ7 SB MA12 AV26 continued continued continued Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron March 2015 Order No 328897 010 Processor Family Datasheet Volume 1 of 2 119 n te Processor Processor Ball and Signal Information Signal Name Ball Signal Name Ball Signal Name Ball VCC A24 VCC E29 VCC J22 VCC A25 VCC E30 VCC J23 VCC A26 VCC E31 VCC J24 VCC A27 VCC E32 VCC J25 VCC A28 VCC E33 VCC J26 VCC A29 VCC E34 VCC J27 VCC A30 VCC E35 VCC J28 VCC B25 VCC F23 VCC J29 VCC B27 VCC F25 VCC J30 VCC B29 VCC F27 VCC J31 VCC B31 VCC F29 VCC J32 VCC B33 VCC F31 VCC J33 VCC B35 VCC F33 VCC J34 VCC C24 VCC F35 VCC J35 VCC C25 VCC G22 VCC K19 VCC C26 VCC G23 VCC K21 VCC C27 VCC G24 VCC K
79. S Ki VSS E18 VSS G37 VSS K10 VSS E20 VSS G6 VSS K14 VSS E22 VSS G7 VSS K15 VSS E23 VSS G9 VSS K16 VSS E3 VSS H1 VSS K17 VSS E36 VSS H10 VSS K18 VSS E38 VSS H11 VSS K20 VSS E6 VSS H13 VSS K22 VSS E7 VSS H17 VSS K24 VSS E8 VSS H18 VSS K26 VSS Fi VSS H20 VSS K28 VSS F12 VSS H21 VSS K30 VSS F14 VSS H22 VSS K32 VSS F16 VSS H24 VSS K34 VSS F19 VSS H26 VSS K36 VSS F21 VSS H28 VSS K4 continued continued continued Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family Datasheet Volume 1 of 2 124 March 2015 Order No 328897 010 Processor Ball and Signal Information Processor Signal Name Ball Signal Name Ball Signal Name Ball VSS K40 VSS N3 VSS T7 VSS K7 VSS N33 VSS U2 VSS Lil VSS N34 VSS U33 VSS L13 VSS N39 VSS U34 VSS L14 VSS N4 VSS U35 VSS L3 VSS N6 VSS U36 VSS L35 VSS N7 VSS U37 VSS L36 VSS N8 VSS U4 VSS L38 VSS P2 VSS U7 VSS L6 VSS P34 VSS V3 VSS L7 VSS P35 VSS V33 VSS L8 VSS P38 VSS V34 VSS L9 VSS P39 VSS V40 VSS Mi VSS P40 VSS V6 VSS M12 VSS P5 VSS V7 VSS M14 VSS P7 VSS v8 VSS M16 VSS R3 VSS wi VSS M18 VSS R35 VSS w33 VSS M20 VSS R37 VSS w35 VSS M22 VSS R38 VSS w37 VSS M24 VSS R39 VSS w4 VSS M26 VSS R40 VSS W7 VSS M28 VSS R5 VSS Y33 VSS
80. Specific Registers Non Critical to Function NCTF locations are typically redundant ground or non critical NCTF reserved so the loss of the solder joint continuity at end of life conditions will not affect the overall product functionality ODT On Die Termination OLTM Open Loop Thermal Management PCG Platform Compatibility Guide PCG previously known as FMB provides a design target for meeting all planned processor frequency requirements Platform Controller Hub The chipset with centralized platform capabilities including PCH the main I O interfaces along with display connectivity audio features power management manageability security and storage features The Platform Environment Control Interface PECI is a one wire interface that PECI provides a communication channel between Intel processor and chipset components to external monitoring devices Case to ambient thermal characterization parameter psi A measure of thermal U ca solution performance using total package power Defined as Tcase Tia Total Package Power PCI Express Graphics External Graphics using PCI Express Architecture It is a PEG high speed serial interface where configuration is software compatible with the existing PCI specifications PL1 PL2 Power Limit 1 and Power Limit 2 PPD Pre charge Power down Processor The 64 bit multi core component package Processor Core The term processor core refers to Si die itself which can contain multiple
81. Timing VDIP DVI eDP PCH Display o o G o g 2 c o o 2 fa o E o DDI Ports B C and D Display Pipe C _ ke Controller Display is the presentation stage of graphics This involves e Pulling rendered data from memory e Converting raw data into pixels e Blending surfaces into a frame Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 32 Order No 328897 010 m e Interfaces Processor n te j Figure 7 e Organizing pixels into frames e Optionally scaling the image to the desired size e Re timing data for the intended target e Formatting data according to the port output standard DisplayPort DisplayPort is a digital communication interface that uses differential signaling to achieve a high bandwidth bus interface designed to support connections between PCs and monitors projectors and TV displays DisplayPort is also suitable for display connections between consumer electronics devices such as high definition optical disc players set top boxes and TV displays A DisplayPort consists of a Main Link Auxiliary channel and a Hot Plug Detect signal The Main Link is a unidirectional high bandwidth and low latency channel used for transport of isochronous data streams such as uncompressed video and audio The Auxiliary Channel AUX
82. Use a 49 9 Q 1 _ resistor to ground FC Future Compatibility signals are signals that are available for FC x compatibility with other processors A test point may be placed on the board for these lands PM SYNC Power Management Sync A sideband signal to communicate I power management status from the platform to the processor CMOS Signal is for debug I PWR_DEBUG Asynchronous CMOS IST_TRIGGER Signal is for IFDIM testing only CMOS Signal is for debug If both THERMTRIP and this signal are IVR ERROR simultaneously asserted the processor has encountered an O m unrecoverable power delivery fault and has engaged automatic CMOS shutdown as a result RESET Platform Reset pin driven by the PCH I CMOS RSVD RESERVED All signals that are RSVD and RSVD_NCTF must be No Connect left unconnected on the board Intel recommends that all Test Point RSVD_TP RSVD_TP signals have via test points Non Critical to RSVD_NCTF Function DRAM Reset Reset signal from processor to DRAM devices One O SM_DRAMRST signal common to all channels CMOS TESTLO_x TESTLO should be individually connected to Vss through a resistor Note 1 PCIe bifurcation support varies with the processor and PCH SKUs used Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron March 2015 Order No 328897 010 Processor Family Datasheet Volume 1 o
83. a ba ak naa be ke sea daa aa b dari d ka aa e d na 94 7 4 Reserved or Unused SiIgr i a S ss s lak na akikkak k l kk k abl kk h kk kk a lea kaleka K k k a k nasi nn nn 99 VEIT reno 99 7 6 Test Access Port TAP Connection ss nayki asas nala Aka naa ka Aya AE kana ana RR kal EA EUR aa a 101 7 7 DC Specifications kuh ake abi dana tac ak k yaka bik avan k kad n W k Un medi Di aka a ka da lk darka b a ce 101 7 8 Voltage and Current Sp cificatiO s i si i a kak kal ll kak lak ka bik dak kak l ka kala aka kala k kala 102 7 8 1 Platform Environment Control Interface PECI DC Characteristics 107 7 8 2 Input Device Eyst f 6 iS is nis b na w en c ucro as g MEER 108 8 0 Package Mechanical Specifications eeeeeeeeseie eese se aka kaka nana nau uan ua uu an ua au u aku 109 8 1 Processor Component Keep Out ZONE kk kk kk kaka enne menm 109 8 2 Package Loading Specifications kk kk kk kk eee eee ka kak ka 109 8 3 Package Handling Guidelines kk c ra tei P ka da K k dala bi ga Pe kah ky d k b k aa Dak da xa Ein ka 110 8 4 Package Insertion Specifications aaa aaraa 110 8 5 Processor Mass Sp cificatlOll ss asad kak lak eect eee niii daka kl k aa k ka kake a kak ka abay a 110 8 6 Processor Materials sy uc cil io eri ia Eten i s gas bant ba b n babed a n na Wak a T
84. aGeMe nt cece eene nnn nnn nnn 51 4 2 1 Enhanced Intel SpeedStep Technology Key Features eene 51 4 2 2 Low Power Idle States accessere ben enata na Rn ARRA kk a kara d ala ba aa ka kan aa da 52 Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family March 2015 Datasheet Volume 1 of 2 Order No 328897 010 3 m n tel Processor Contents 4 2 3 Requesting Low Power Idle States aaraa 53 4 2 4 Core CsState Rules etae sams kokan n kala ka dt Aa karn ba dev aa rer E AA lar ea a kan EWAY AA 54 4 2 5 Package C States ints s sentite dar n sg kala d a W Va wal a rex ea b kata kn 55 4 2 6 Package C States and Display Resolutions aaa 59 4 3 Integrated Memory Controller IMC Power Management aaa 60 4 3 1 Disabling Unused System Memory Outputs sssssssseseseeeee nnne 60 4 3 2 DRAM Power Management and Initialization c cece esac ee ects eee ee kk 61 4 3 3 DRAM Running Average Power Limitation RAPL aaa 63 4 3 4 DDR Electrical Power Gating EPG sss nemen nen 63 4 4 PCI Express Power Management 2 retinet kak nna rna ka ek h k ua cR e lay k ean dk xana d t aA ER ERR RR 63 4 5 Direct Media Interface DMI Power Management sssssssssssesesenmem enne 63 4 6 Graphics Power Management sis aa nil sula ayan x h
85. aa a w h Za ban dak kn a cad 110 8 7 Processor Marking Sk sao yan dar Dn GR SIN dawa sads N E INN AERE NEN AE kn Cans DA b n CUNT MAR 111 8 8 Processor Land Coordin te ss sya ay esa ruat haka haaa kal xa EEE kalara a y a a naa kwan a a la 111 8 9 Processor Storage Specifications aaa aaa kak kk kk aka 113 9 0 Processor Ball and Signal Inform at O k k k klllllkdldllkkklkkkkkkkkkkkkkkk kk kk kak kk kaka kaka kak ka uan u ka ua au u aku 115 Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family March 2015 Datasheet Volume 1 of 2 Order No 328897 010 5 a n tel Processor Figures Figures 1 Platformi Block Dladtam sasar see Helen E ka n ba nO d ma ka a Wa kj 11 2 Intel Flex Memory Technology Operations cssccsecceecsecceeeeeeeeecceeeeeeaueeeeaeeeaueseesages 21 3 PCI Express Related Register Structures in the PrOC SSOF cccsseseeeeeeeee ene kk kk kK KK KK 25 4 PCI Express Typical Operation 16 Lanes Mapping cccceceeeeeeeeeee tetas teens ee kk kk kk 26 5 Processor Graphics Controller Unit Block Diagram cceeeeeeeee eects eee kk ne 29 6 Processor Display Ar hitectU hes ss su an ina sina ra nanan kad n e naa al ede n cirea ra Ra wa da sa as m Ra AA 32 7 DisplayPort O Ve Fv l W ves cce tache dave ArT EUELA EENEN ERE ITECA std dd ara j kr
86. abilities of the processor See the PCI Express Base Specification 3 0 for details on PCI Express PCI Express Support The PCI Express lanes PEG 15 0 TX and RX are fully compliant to the PCI Express Base Specification Revision 3 0 The processor with the PCH support the configurations shown in the following table may vary depending on PCH SKUs PCI Express Supported Configurations in Desktop Products Configuration Desktop 1x8 2x4 GFX 1 0 2x8 GFX I O 1x16 GFX I O e The port may negotiate down to narrower widths Support for x16 x8 x4 x2 x1 widths for a single PCI Express mode e 2 5 GT s 5 0 GT s and 8 GT s PCI Express bit rates are supported e Gen 1 Raw bit rate on the data pins of 2 5 GT s resulting in a real bandwidth per pair of 250 MB s given the 8b 10b encoding used to transmit data across this interface This also does not account for packet overhead and link maintenance Maximum theoretical bandwidth on the interface of 4 GB s in each direction simultaneously for an aggregate of 8 GB s when x16 Gen 1 e Gen 2 Raw bit rate on the data pins of 5 0 GT s resulting in a real bandwidth per pair of 500 MB s given the 8b 10b encoding used to transmit data across this interface This also does not account for packet overhead and link maintenance Maximum theoretical bandwidth on the interface of 8 GB s in each direction simultaneously for an aggregate of 16 GB s when x16 Gen 2 e Gen
87. agement is supported using LOs L1 state Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron March 2015 Processor Family Datasheet Volume 1 of 2 Order No 328897 010 63 m n tel Processor Power Management 4 6 4 6 1 4 6 2 4 6 3 Graphics Power Management Intel Rapid Memory Power Management Intel RMPM Intel Rapid Memory Power Management Intel RMPM conditionally places memory into self refresh when the processor is in package C3 or deeper power state to allow the system to remain in the lower power states longer for memory not reserved for graphics memory Intel RMPM functionality depends on graphics display state relevant only when processor graphics is being used as well as memory traffic patterns generated by other connected I O devices Graphics Render C State Render C state RC6 is a technique designed to optimize the average power to the graphics render engine during times of idleness RC6 is entered when the graphics render engine blitter engine and the video engine have no workload being currently worked on and no outstanding graphics memory transactions When the idleness condition is met the processor graphics will program the graphics render engine internal power rail into a low voltage state Intel Graphics Dynamic Frequency Intel Graphics Dynamic Frequency Technology is the ability of the processor and grap
88. al Name Ball Signal Name Ball SA_DQ53 AL3 SA_ECC_CB3 AV31 SB_CKE1 AY29 SA_DQ54 AJ2 SA ECC CB4 AT33 SB CKE2 AU28 SA DQ55 AJ1 SA_ECC_CB5 AU33 SB_CKE3 AU29 SA_DQ56 AG1 SA_ECC_CB6 AT31 SB_CKNO AM21 SA_DQ57 AG4 SA_ECC_CB7 AW31 SB_CKN1 AP21 SA_DQ58 AE3 SA MAO AU13 SB CKN2 AN21 SA DQ59 AE4 SA_MA1 AV16 SB_CKN3 AP20 SA_DQ6 AF37 SA MA10 AW11 SB CS 0 AP17 SA DQ60 AG2 SA MA11 AV19 SB CS 1 AN15 SA DQ61 AG3 SA MA12 AU19 SB CS 2 AN17 SA DQ62 AE2 SA MA13 AY10 SB CS 3 AL15 SA DQ63 AE1 SA MA14 AT20 SB DIMM VREF AB40 D SA_DQ7 AF40 SA MA15 AU21 s SB DQO AE34 SA DQ8 AH40 SA MA2 AU16 SB DQ1 AE35 SA DQ9 AH39 SA MA3 AW17 SB DQ10 AK31 SA DQSNO AE38 SA MA4 AU17 SB DQ11 AL31 SA DQSN1 A338 SA MA5 AW18 SB DQ12 AK34 SA DQSN2 AN38 SA MA6 AV17 SB DQ13 AK35 SA DQSN3 AU36 SA MA7 AT18 SB DQ14 AK32 SA DQSN4 AW5 SA MA8 AU18 SB DQ15 AL32 SA DQSN5 AP2 SA MA9 AT19 SB DQ16 AN34 SA DQSN6 AK2 SA ODTO AW10 SB DQ17 AP34 SA DQSN7 AF2 SA ODT1 AY8 SB DQ18 AN31 SA DQSN8 AU32 SA ODT2 AW9 SB_DQ19 AP31 SA_DQSPO AE39 SA_ODT3 AU8 SB_DQ2 AG35 SA_DQSP1 AJ39 SA RAS AU12 SB DQ20 AN35 SA DQSP2 AN39 SA_WE AU11 SB DQ21 AP35 SA DQSP3 AV36 SB BSO AK17 SB DQ22 AN32 SA DQSP4 AV5 SB_BS1 AL18 SB_DQ23 AP32 SA_DQSP5 AP3 SB_BS2 AW28 SB_DQ24 AM29 SA_DQSP6 AK3 SB_CAS AP16 SB_DQ25 AM28 SA_DQSP7 AF3 SB_CKO AM20 SB_DQ26 AR29 SA_DQSP8 AV32 SB_CK1 AP22 SB_DQ27 AR28 SA_ECC_CBO AW33 SB_CK2 AN20 SB_DQ28 AL29 SA_ECC_CB1 AV33 SB_CK3 AP19 SB_DQ29 AL28 SA_ECC_CB2
89. ance DDR3 DDR3L Reset Ron_UP RST Buffer pull up 40 80 130 Q Resistance DDR3 DDR3L Reset RON_DN RST Buffer pull up 40 80 130 Q xx Resistance Input Leakage Current DQ CK I 0V E 0 7 mA 0 2 Vppo 0 8 Vppg Input Leakage Current CMD CTL Ir 0V 1 0 mA 0 2 Vppo 0 8 Vppo Command COMP SM_RCOMPO Resistance 99 100 101 Q 8 SM_RCOMP1 Data COMP Resistance 74 25 75 75 75 Q 8 SM_RCOMP2 ODT COMP Resistance 99 100 101 Q 8 Notes 1 Unless otherwise noted all specifications in this table apply to all processor frequencies Vy is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value Vin is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value Vin and Voy may experience excursions above Vppo However input signal drivers must comply with the signal quality specifications This is the pull up down driver resistance Rrterm is the termination on the DIMM and in not controlled by the processor The minimum and maximum values for these signals are programmable by BIOS to one of the two sets 8 SM RCOMPx resistance must be provided on the system board with 1 resistors SM RCOMPx resistors are to Vss 9 SM DRAMPWROK rise and fall time must be lt 50 ns measured between Vppo 0 15 and Vppo 0 47 10 SM VREF is defined as Vppo 2 11 Maximum minimum range is correct however center point is subject to chan
90. aneously allowing for customization for multiple system thermal and power limitations These controls provide turbo optimizations within system constraints 5 10 2 Package Power Control The package power control allows for customization to implement optimal turbo within platform power delivery and package thermal solution limitations Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron March 2015 Processor Family Datasheet Volume 1 of 2 Order No 328897 010 83 intel Table 29 Processor Thermal Management Intel Turbo Boost Technology 2 0 Package Power Control Settings MSR Address MSR_TURBO_POWER_LIMIT 610h Control Bit Default Description POWER_LIMIT_1 PL1 14 0 SKU TDP This value sets the average power limit over a long time period This is normally aligned to the TDP of the part and steady state cooling capability of the thermal solution The default value is the TDP for the SKU e PL1 limit may be set lower than TDP in real time for specific needs such as responding to a thermal event If it is set lower than TDP the processor may require to use frequencies below the guaranteed P1 frequency to control the low power limits The PL1 Clamp bit 16 should be set to enable the processor to use frequencies below P1 to control the set power limit PLI limit may be set higher than TDP If set higher than TDP the pro
91. arch 2015 Order No 328897 010 Processor Family Datasheet Volume 1 of 2 47 n n tel Processor Technologies e The semantics for accessing APIC registers have been revised to simplify the programming of frequently used APIC registers by system software Specifically the software semantics for using the Interrupt Command Register ICR and End Of Interrupt EOI registers have been modified to allow for more efficient delivery and dispatching of interrupts e The x2APIC extensions are made available to system software by enabling the local x2APIC unit in the x2APIC mode To benefit from x2APIC capabilities a new operating system and a new BIOS are both needed with special support for X2APIC mode e The x2APIC architecture provides backward compatibility to the xAPIC architecture and forward extendible for future Intel platform innovations Note Intel x2APIC Technology may not be available on all SKUs For more information see the Intel 64 Architecture x2APIC Specification at http www intel com products processor manuals 3 9 Power Aware Interrupt Routing PAIR The processor includes enhanced power performance technology that routes interrupts to threads or cores based on their sleep states As an example for energy savings it routes the interrupt to the active cores without waking the deep idle cores For performance it routes the interrupt to the idle C1 cores without interrupting the already heavily l
92. aunched environment MLE Intel TXT also requires the system to contain a TPM v1 s For more information visit http www intel com technology security Requires a system with Intel Turbo Boost Technology Intel Turbo Boost Technology and Intel Turbo Boost Technology 2 0 are only available on select Intel processors Consult your PC manufacturer Performance varies depending on hardware software and system configuration For more information visit https www ssl intel com content www us en architecture and technology turbo boost turbo boost technology html Intel Advanced Vector Extensions Intel AVX are designed to achieve higher throughput to certain integer and floating point operations Due to varying processor power characteristics utilizing AVX instructions may cause a some parts to operate at less than the rated frequency and b some parts with Intel Turbo Boost Technology 2 0 to not achieve any or maximum turbo frequencies Performance varies depending on hardware software and system configuration and you should consult your system manufacturer for more information Intel Advanced Vector Extensions refers to Intel AVX Intel AVX2 or Intel AVX 512 For more information on Intel Turbo Boost Technology 2 0 visit https www ssl intel com content www us en architecture and technology turbo boost turbo boost technology html Intel Intel Core Celeron Pentium Intel SpeedStep and the Intel logo are trademarks of Intel Corporat
93. aven dana PR aa kamal nan oa ba w bak na kak a kla n kalk n a 64 4 6 1 Intel Rapid Memory Power Management Intel RMPM eene 64 4 6 2 Graphics Render CS ta t yas bal n bala ae bak n k sends cena esed A a bawk al s t gas 64 4 6 3 Intel Graphics Dynamic FrequenCy hL hL ll lk k lll kk kk nennen nns 64 5 0 Thermal Management aaa aaa anas sasar nasa asas an kun una au nau ananas an nuna ada uu unum ua an u nau una uan 65 5 1 Desktop Processor Thermal Profil S isi aaa leke kala a kar 67 5 1 1 Processor PCG 2013D and PCG 2014 Thermal Profile hllllE 68 5 1 2 Processor PCG 2013C Thermal Profile ccccee cesses e esse ease ee mmm 69 5 1 3 Processor PCG 2013B Thermal Profile sees 70 5 1 4 Processor PCG 2013A Thermal Profile esses 72 5 2 Thermal Metrology correr aeui turae Ren en tec eheu eb kak H k me dak ak RR T IA vijas da RE aa dej tk 73 5 3 Fan Speed Control Scheme with Digital Thermal Sensor DTS 1 1 usse 73 5 4 Fan Speed Control Scheme with Digital Thermal Sensor DTS 2 0 esee 75 5 5 Thiermal SpecifICatiOrnis x ace rire nderit in kil wa REB ERR as vis ERR CER AERE asi dikan ka ROC UA 76 5 6 Processor Temiperatite su occi yan yaylan a n ade nda dat uin eu reda Dias iae cds 78 5 7 Adaptive Thermal Molllt s iieri soda i nas n aka ein ko On
94. bstantial gains in performance and lower power consumption over previous generations Up to 20 Execution Units are supported depending on the processor SKU Next Generation Intel Clear Video Technology HD Support is a collection of video playback and enhancement features that improve the end user s viewing experience Encode transcode HD content Playback of high definition content including Blu ray Disc Superior image quality with sharper more colorful images Playback of Blu ray disc S3D content using HDMI 1 4a specification compliant with 3D DirectX Video Acceleration DXVA support for accelerating video processing Full AVC VC1 MPEG2 HW Decode Advanced Scheduler 2 0 1 0 XPDM support Windows 8 Windows 7 OSX Linux operating system support DirectX 11 1 DirectX 11 DirectX 10 1 DirectX 10 DirectX 9 support OpenGL 4 0 support Switchable Graphics support on AIO platforms with MxM solutions only Processor Graphics Controller GT The Graphics Engine Architecture includes 3D compute elements Multi format HW assisted decode encode pipeline and Mid Level Cache MLC for superior high definition playback video quality and improved 3D performance and media The Display Engine handles delivering the pixels to the screen GSA Graphics in System Agent is the primary channel interface for display memory accesses and PCI like traffic in and out Desktop 4th Generation Intel Core Processo
95. cation TAC Thermal Averaging Constant TAP Test Access Point Tus The case temperature of the processor measured at the geometric center of the top side of the TTV IHS TCC Thermal Control Circuit TcoNrRnoL S a static value that is below the TCC activation temperature and used as a TconrRoL trigger point for fan speed control When DTS gt TconrRoL the processor must comply to the TTV thermal profile TDP Thermal Design Power Thermal solution should be designed to dissipate this target power level TDP is not the maximum power that the processor can dissipate TLB Translation Look aside Buffer TTV Thermal Test Vehicle A mechanically eguivalent package that contains a resistive heater in the die to evaluate thermal solutions TM Thermal Monitor A power reduction feature designed to decrease temperature after the processor has reached its maximum operating temperature Vcc Processor core power supply VDDQ DDR3 DDR3L power supply VF Vertex Fetch VID Voltage Identification VS Vertex Shader VLD Variable Length Decoding VMM Virtual Machine Monitor VR Voltage Regulator Vss Processor ground x1 Refers to a Link or Port with one Physical Lane x2 Refers to a Link or Port with two Physical Lanes x4 Refers to a Link or Port with four Physical Lanes x8 Refers to a Link or Port with eight Physical Lanes x16 Refers to a Link or Port with sixteen Physical Lanes 1 7 Related Documents Table 2 Related Documents Document Docume
96. cessor could stay at that power level continuously and cooling solution improvements may be required POWER_LIMIT_1_TIME behavior to maintain time averaged power at or below PL1 The Turbo Time Parameter hardware default value is 1 second however 28 seconds is This value is a time parameter that adjusts the algorithm 23 17 1 sec recommended for most mobile applications POWER_LIMIT_2 PL2 46 32 1 25 x TDP PL2 establishes the upper power limit of turbo operation above TDP primarily for platform power supply considerations Power may exceed this limit for up to 10 ms The default for this limit is 1 25 x TDP however the BIOS may reprogram the default value to maximize the performance within platform power supply considerations Setting this limit to TDP will limit the processor to only operate up to the TDP It does not disable turbo because turbo is opportunistic and power temperature dependent Many workloads will allow some turbo frequencies for powers at or below TDP Figure 22 5 10 3 Package Power Control POWER LIMIT 2 POWER LIMIT 1 PL1 TDP Package Power Temperature or Energy POWER LIMIT 1 Time Time Turbo Time Parameter Turbo Time Parameter is a mathematical parameter units in seconds that controls the Intel Turbo Boost Technology algorithm using an average of energy usage During a maximum power turbo event of about 1 25 x TDP the processor could sus
97. chnology Mode The IMC supports Intel Flex Memory Technology Mode Memory is divided into symmetric and asymmetric zones The symmetric zone starts at the lowest address in each channel and is contiguous until the asymmetric zone begins or until the top address of the channel with the smaller capacity is reached In this mode the system runs with one zone of dual channel mode and one zone of single channel mode simultaneously across the whole memory array Channels A and B can be mapped for physical channel 0 and 1 respectively or vice versa however channel A size must be greater or equal to channel B size Intel Flex Memory Technology Operations TOM Non interleaved access EE Dual channel interleaved access CHA CH B CH A and CH B can be configured to be physical channels 0 or 1 B The largest physical memory amount of the smaller size memory module C The remaining physical memory amount of the larger size memory module Dual Channel Symmetric Mode Dual Channel Symmetric mode also known as interleaved mode provides maximum performance on real world applications Addresses are ping ponged between the channels after each cache line 64 byte boundary If there are two requests and the second request is to an address on the opposite channel from the first that request can be sent before data from the first request has returned If two consecutive cache lines are requested both
98. cif Cat OS aaa 66 22 Thermal Test Vehicle Thermal Profile for Processor PCG 2013D and PCG 2014 68 23 Thermal Test Vehicle Thermal Profile for Processor PCG 2013C sss 69 24 Thermal Test Vehicle Thermal Profile for Processor PCG 2013B KK kk 71 25 Thermal Test Vehicle Thermal Profile for Processor PCG 20134 sese 72 26 Digital Thermal Sensor DTS 1 1 Thermal Solution Performance Above Tcowrnor 75 27 Thermal Margin Slope rrr dk pi nana Dak ian ya sies Ren EORR a wa Dab da bak RARE RR A RETE REX va 76 28 Boundary Conditions Performance Targets and Tease Specifications useseseseuses 77 29 Intel Turbo Boost Technology 2 0 Package Power Control Settings seseeeese 84 30 Signal Description Buffer Types va s n d ha kl A HERR a a aa W ak dara kad W k A 86 31 Memory Channel A Signals da lak s pak en ya kek ea ta Wa kak W k ka Wa bda bka ala aa d le d a W hala Ya kek ka 86 32 Memory Channel B SIidi a l5 ricco ee o pen b ba n r DA w Ya B wa xt piec s de a C KE 87 33 Memory Reference and Compensation S gnalS kh kh h khk khk k kk kk kk kaka ka 88 34 Reset and Miscellaneous Signals ssssssssssssssses nnne eene nee 89 35 PCI Express Graphics Interface SignalsS nines 90 36 Display Interface Sigrials J ii iier teri oe ea ERR kan usen re bre A
99. cores are in a power state deeper than C1 C1E state however the package low power state is limited to C1 C1E using the PMG CST CONFIG CONTROL MSR e All cores have requested C1 state using HLT or MWAIT C1 and C1E auto promotion is enabled in IA32 MISC ENABLES No notification to the system occurs upon entry to C1 C1E state Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family March 2015 Datasheet Volume 1 of 2 Order No 328897 010 57 m e n tel Processor Power Management Package C2 State Package C2 state is an internal processor state that cannot be explicitly requested by software A processor enters Package C2 state when e All cores and graphics have requested a C3 or deeper power state however constraints LTR programmed timer events in the near future and so on prevent entry to any state deeper than C 2 state Or e All cores and graphics are in the C3 or deeper power states and a memory access request is received Upon completion of all outstanding memory requests the processor transitions back into a deeper package C state Package C3 State A processor enters the package C3 low power state when e At least one core is in the C3 state e The other cores are in a C3 state or deeper power state and the processor has been granted permission by the platform e The platform has not granted a request to a package C6 or
100. ctive cores the processor takes the following into consideration e The number of cores operating in the CO state e The estimated core current consumption e The estimated package prior and present power consumption e The package temperature Any of these factors can affect the maximum frequency for a given workload If the power current or thermal limit is reached the processor will automatically reduce the frequency to stay within its TDP limit Turbo processor frequencies are only active if the operating system is requesting the PO state For more information on P states and C states see Power Management on page 49 Intel Advanced Vector Extensions 2 0 Intel AVX2 Intel Advanced Vector Extensions 2 0 Intel AVX2 is the latest expansion of the Intel instruction set Intel AVX2 extends the Intel Advanced Vector Extensions Intel AVX with 256 bit integer instructions floating point fused multiply add FMA instructions and gather operations The 256 bit integer vectors benefit math codec image and Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron March 2015 Processor Family Datasheet Volume 1 of 2 Order No 328897 010 45 n n tel Processor Technologies digital signal processing software FMA improves performance in face detection professional imaging and high performance computing Gather operations increase vectorization o
101. d be made Thermal Test Vehicle TTV Case Temperature Tcase Measurement Location Measure Tcase at N the geometric center of the package V LO DN RN SE ss RP N S ERU ee D e i Ka N i o 37 5 THERM X OF CALIFORNIA can machine the groove and attach a thermocouple to the IHS The supplier is subject to change without notice THERM X OF CALIFORNIA 1837 Whipple Road Hayward Ca 94544 Ernesto B Valencia 1 510 441 7566 Ext 242 ernestov therm x com The vendor part number is XTMS1565 Fan Speed Control Scheme with Digital Thermal Sensor DTS 1 1 To correctly use DTS 1 1 the designer must first select a worst case scenario TAMBIENT and ensure that the Fan Speed Control FSC can provide a Uc that is equivalent or greater than the Uc specification The DTS 1 1 implementation consists of two points a Wc at TconrRoL and a Uc at DTS 1 Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron March 2015 Processor Family Datasheet Volume 1 of 2 Order No 328897 010 73 n n tel Processor Thermal Management Figure 20 The Wc point at DTS 1 defines the minimum Wc required at TDP considering the worst case system design Tamprent design point Wea Tcase Max 7 TAMBIENT TARGET TDP For example for a 95 W TDP part the Tease maximum is
102. dress range is supported Pass Through The processor supports the following added new Intel VT d features e 4 level Intel VT d Page walk Both default Intel VT d engine as well as the IGD Intel VT d engine are upgraded to support 4 level Intel VT d tables adjusted guest address width 48 bits e Intel VT d superpage support of Intel VT d superpage 2 MB 1 GB for the default Intel VT d engine that covers all devices except IGD IGD Intel VT d engine does not support superpage and BIOS should disable superpage in default Intel VT d engine when iGFX is enabled Intel VT d Technology may not be available on all SKUs Intel Trusted Execution Technology Intel TXT Intel Trusted Execution Technology Intel TXT defines platform level enhancements that provide the building blocks for creating trusted platforms The Intel TXT platform helps to provide the authenticity of the controlling environment such that those wishing to rely on the platform can make an appropriate trust decision The Intel TXT platform determines the identity of the controlling environment by accurately measuring and verifying the controlling software Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron March 2015 Processor Family Datasheet Volume 1 of 2 Order No 328897 010 43 m n tel Processor Technologies Another aspect of the trust decision is the ability o
103. e wa N b d K Dede nda Sont cc EN cr MENS ba 78 5 8 THERMTRIPZ Sigh l rine rr aa exuit xan sies ai a a a RE kaya a E aa Ku a Za RF EXER 81 5 9 Digital Thermal Sensorer tanna ec ehe Pu b l naka ka a anu aa ERAN ARR Rx UE LEE ENDE aaa fis Kat 81 5 9 1 Digital Thermal Sensor Accuracy Taccuracy sssssssssses eene 82 5 10 Intel Turbo Boost Technology Thermal Considerations ceeeeeee 82 5 10 1 Intel Turbo Boost Technology Power Control and Reporting s es 82 5 10 2 Package Power Control essei nibe tace cet a cidade RR ER kalek D qaa EORR seas 83 5 10 3 Turbo Time Parameter bieds sans vaja tad bises kb ERR NN UU OU E 84 6 0 Signal DeSCriptiOn cccceeeeeeeee eee vara kk kaka kak kk kaka kk rasas eases esse an u ua usa sana uan ua uu nau u sa aa aku uan anku ak a 86 6 1 System Memory Interface SignalS ilk akla kl allkl eee eee eee akla da kan a kl kaka ka kaka a ka aka nn 86 6 2 Memory Reference Compensation S gnalS MLkh hk l k k l kk kk kk nemen 88 6 3 Reset and Miscellaneous Signals sss nennen emen 89 6 4 PCI Express Interface Signals si eoo rtt sae tern rta kr b nk dad Haa aae sa Rana kat edit av 90 6 5 Display Interface Signals 1 a rere erento ata eR up sex ehe HW he da NEU ated EA nisi 90 6 6 Direct Media Interface DMI isi kck ck ll ka kak ak ak kak l k ms ka kan ala ka a ee a ala kad a ae alarak aka a
104. e 21 Desktop Processor Thermal Specifications Product PCG Max Max Min Max Max Min TTV Min Max Power Power Power Power Power Power Thermal TcasE TTV Packag Packag Package Packag Package Package Design C TcasE e C1E ec3 C3 W e C6 C7 W C6 C7 Power C W 1 2 W 1 3 W 1 4 4 5 9 W W 6 7 5 9 5 9 5 9 10 Processo r PCG Quad 2013D Core 2013D and PCG Processor and 26 20 1 0 3 5 3 4 0 84 5 2014 with 2014 Thermal Graphics Profile on page 68 Processo Quad r PCG Core 2013C Processor 2013C 23 17 1 0 3 5 3 4 0 65 5 Thermal with Profile Graphics on page 69 Processo r PCG eise 2013C with 2013C 23 17 1 0 3 5 3 4 0 54 5 Thermal G Profile raphics on page 69 Processo Quad r PCG Core 2013B Processor 2013B 18 11 1 0 3 5 3 4 0 45 5 Thermal with Profile Graphics on page 70 e Processo Processor 2013A 16 16 1 0 3 5 3 4 0 35 5 des 2013A with Thermal Graphics continued Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 66 Order No 328897 010 Thermal Management Processor n tel Uy desc OUI Product PCG Max Max Min Max Max Min TTV Min Max Power Power Power Power Power Power Thermal TCASE TTV Packag Packag Package Packag Package Package Design C TcasE e C1
105. e 64 bit downstream address format but the processor never generates an address above 64 GB Bits 63 36 will always be zeros e 64 bit upstream address format but the processor responds to upstream read transactions to addresses above 64 GB addresses where any of Bits 63 36 are nonzero with an Unsupported Request response Upstream write transactions to addresses above 64 GB will be dropped e Re issues Configuration cycles that have been previously completed with the Configuration Retry status e PCI Express reference clock is 100 MHz differential clock e Power Management Event PME functions e Dynamic width capability e Message Signaled Interrupt MSI and MSI X messages e Polarity inversion Note The processor does not support PCI Express Hot Plug 2 2 2 PCI Express Architecture Compatibility with the PCI addressing model is maintained to ensure that all existing applications and drivers operate unchanged The PCI Express configuration uses standard mechanisms as defined in the PCI Plug and Play specification The processor PCI Express ports support Gen 3 At 8 GT s Gen 3 operation results in twice as much bandwidth per lane as compared to Gen 2 operation The 16 lanes PEG can operate at 2 5 GT s 5 GT s or 8 GT s Gen 3 PCI Express uses a 128b 130b encoding that is about 23 more efficient than the 8b 10b encoding used in Gen 1 and Gen 2 The PCI Express architecture is specified in three layers Transacti
106. e DIMMs and holds Vppo 2 as reference voltage SA DIMM VREFDQ SB DIMM VREFDQ DDR3 DDR3L Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 88 Order No 328897 010 Signal Description Processor 6 3 Table 34 Reset and Miscellaneous Signals Reset and Miscellaneous Signals intel Signal Name Description Direction Buffer Type Configuration Signals The CFG signals have a default value of 1 if not terminated on the board e CFG 1 0 Reserved configuration lane A test point may be placed on the board for these lanes e CFG 2 PCI Express Static x16 Lane Numbering Reversal 1 Normal operation 0 Lane numbers reversed e CFG 3 MSR Privacy Bit Feature 1 Debug capability is determined by IA32 Debug Interface MSR C80h bit 0 setting I O CFG 19 0 0 IA32 Debug Interface MSR C80h bit 0 default setting overridden GTL e CFG 4 Reserved configuration lane A test point may be placed on the board for this lane CFG 6 5 PCI Express Bifurcation 1 00 1 x8 2 x4 PCI Express 01 reserved 10 2 x8 PCI Express 11 1x16 PCI Express e CFG 19 7 Reserved configuration lanes A test point may be placed on the board for these lands CFG RCOMP Configuration resistance compensation
107. e processor features are not available on all platforms Refer to the processor Specification Update document for details Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 10 Order No 328897 010 Introduction Processor n tel Figure 1 1 1 Platform Block Diagram PCI Express 3 0 2 DIMMs CH CHA Digital Display Processor System Memory Interface DDI 3 interfaces Intel Flexible Display Interface Intel FDI x2 Direct Media Interface 2 0 DMI 2 0 x4 Analog Display VGA USB 3 0 up to 6 Ports USB 2 0 8 Ports SATA 6 GB s up to 6 Ports SPI Flash SE Integrated LAN Platform Controller Hub PCH PCI Express 2 0 up to 8 Ports Intel High Definition Audio Intel HD Audio LPC Trusted Platform SMBus 2 0 Module TPM 1 2 Super IO EC GPIOs Supported Technologies e Intel Virtualization Technology Intel VT e Intel Active Management Technology 9 5 Intel AMT 9 5 e Intel Trusted Execution Technology Intel TXT e Intel Streaming SIMD Extensions 4 2 Intel SSE4 2 e Intel Hyper Threading Technology Intel HT Technology e Intel 64 Architecture e Execute Disable Bit e Intel Turbo Boost Technology 2 0 Desktop 4th Generation Intel Core Processor Family Desktop Intel
108. e processor silicon exceeds the Thermal Control Circuit TCC activation temperature Adaptive Thermal Monitor uses TCC activation to reduce processor power using a combination of methods The first method Freguency control similar to Thermal Monitor 2 TM2 in previous generation processors involves the processor reducing its operating freguency using the core ratio multiplier and internal core voltage This combination of lower freguency and core voltage results in a reduction of the processor power consumption The second method clock modulation known as Thermal Monitor 1 or TM1 in previous generation processors reduces power consumption by modulating starting and stopping the internal processor core clocks The processor intelligently selects the appropriate TCC method to use on a dynamic basis BIOS is not required to select a specific method as with previous generation processors supporting TM1 or TM2 The temperature at which Adaptive Thermal Monitor activates the Thermal Control Circuit is factory calibrated and is not user configurable Snooping and interrupt processing are performed in the normal manner while the TCC is active When the TCC activation temperature is reached the processor will initiate TM2 in attempt to reduce its temperature If TM2 is unable to reduce the processor temperature TM1 will be also be activated TM1 and TM2 will work together clocks will be modulated at the lowest frequency ratio to reduce power dissi
109. e to manufacturing efficiencies but will remain within the component keep in This keep in zone includes solder paste and is a post reflow maximum height for the components Package Loading Specifications The following table provides dynamic and static load specifications for the processor package These mechanical maximum load limits should not be exceeded during heatsink assembly shipping conditions or standard use condition Also any Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron March 2015 Processor Family Datasheet Volume 1 of 2 Order No 328897 010 109 n tel Processor Package Mechanical Specifications mechanical system or component testing should not exceed the maximum limits The processor package substrate should not be used as a mechanical reference or load bearing surface for thermal and mechanical solution Table 58 Processor Loading Specifications Parameter Minimum Maximum Notes Static Compressive Load _ 600 N 135 Ibf 1 2 3 Dynamic Compressive 712 N 160 Ibf 1 3 4 Load Notes 1 These specifications apply to uniform compressive loading in a direction normal to the processor IHS 2 This is the maximum static force that can be applied by the heatsink and retention solution to maintain the heatsink and processor interface 3 These specifications are based on limited testing for design charact
110. e with lowest freguency and voltage operating point C3 Execution cores in C3 state flush their L1 instruction cache L1 data cache and L2 cache to the L3 shared cache Clocks are shut off to each core C6 Execution cores in this state save their architectural state before removing core voltage Execution cores in this state behave similarly to the C6 state If all execution cores C7 request C7 state L3 cache ways are flushed until it is cleared If the entire L3 cache is flushed voltage will be removed from the L3 cache Power removal to SA Cores and L3 will reduce power consumption C7 may not be available on all SKUs Table 13 Integrated Memory Controller States State Description Power up CKE asserted Active mode Pre charge CKE de asserted not self refresh with all banks closed Power down Active Power CKE de asserted not self refresh with minimum one bank active down Self Refresh CKE de asserted using device self refresh Table 14 PCI Express Link States State Description LO Full on Active transfer state LOs First Active Power Management low power state Low exit latency L1 Lowest Active Power Management Longer exit latency L3 Lowest power state power off Longest exit latency Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family Datasheet
111. ed in the following table TCC Activation Offset is O for the processors Using the DTS Thermal Profile the processor can calculate and report the Thermal Margin where a value less than 0 indicates that the processor needs additional cooling and a value greater than 0 indicates that the processor is sufficiently cooled Refer to the processor Thermal Mechanical Design Guidelines TMDG for additional information see Related Documents Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron March 2015 Processor Family Datasheet Volume 1 of 2 Order No 328897 010 75 m n tel Processor Thermal Management Figure 21 Digital Thermal Sensor DTS Thermal Profile Definition DTS 0 aaa EAE ESSE a TCC Activation THERM MARGIN lt O ome a gt Teona Offset Ww a H DTS Thermal A Tona Profile LJ THERM_MARGIN gt 0 Thermal Margin Slope TDP POWER W Table 27 Thermal Margin Slope PCG Die TDP W TCC Activation Temperature Thermal Configuration Temperature C Control Offset Margin Native MSR 1A2h 23 16 MSR 1A2h 15 8 Slope Core GT c W 2014 4 2 4 2 88 100 20 0 634 4 2 4 2 84 100 20 0 654 2013D 4 0 4 2 82 100 20 0 671 4 2 4 2 65 92 6 0 722 2013C 2 2 2 2 54 100 20 1 031 2 1 2 2 53 100 20 1 051 2013B 4 2 4 2 45 85 6 0 806 4 2 4 2 35 75 6
112. ed signals For reliable operation always connect unused inputs or bi directional signals to an appropriate signal level Unused active high inputs should be connected through a resistor to ground VSS Unused outputs maybe left unconnected however this may interfere with some Test Access Port TAP functions complicate debug probing and prevent boundary scan testing A resistor must be used when tying bi directional signals to power or ground When tying any signal to power or ground a resistor will also allow for system testability Signal Groups Signals are grouped by buffer type and similar characteristics as listed in the following table The buffer type indicates which signaling technology and specifications apply to the signals All the differential signals and selected DDR3 DDR3L and Control Sideband signals have On Die Termination ODT resistors Some signals do not have ODT and need to be terminated on the board All Control Sideband Asynchronous signals are required to be asserted de asserted for at least 10 BCLKs with maximum Trise Tfall of 6 ns for the processor to recognize the proper signal state See the DC Specifications section and AC Specifications section Signal Groups Signal Group Type Signals System Reference Clock Differential CMOS Input BCLKP BCLKN DPLL REF CLKP DPLL REF CLKN SSC DPLL REF CLKP SSC DPLL REF CLKN DDR3 DDR3L Reference Clocks Differential DDR3 DDR3L SA CKP 3 0 SA
113. edStep Technology optimizes the processor s frequency and core voltage based on workload Each frequency and voltage operating point is defined by ACPI as a P state When the processor is not executing code it is idle A low power idle state is defined by ACPI as a C state In general deeper power C states have longer entry and exit latencies Enhanced Intel SpeedStep Technology Key Features The following are the key features of Enhanced Intel SpeedStep Technology Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron March 2015 Processor Family Datasheet Volume 1 of 2 Order No 328897 010 51 En n tel Processor Power Management 4 2 2 Caution Figure 12 e Multiple frequency and voltage points for optimal performance and power efficiency These operating points are known as P states e Frequency selection is software controlled by writing to processor MSRs The voltage is optimized based on the selected frequency and the number of active processor cores Once the voltage is established the PLL locks on to the target frequency All active processor cores share the same frequency and voltage In a multi core processor the highest frequency P state requested among all active cores is selected Software requested transitions are accepted at any time If a previous transition is in progress the new transition is d
114. ee aa 23 8 Processor Supported Audio Formats over HDMI and DisplayPort c eceeeeeeeeeeeeeees 35 9 Valid Three Display Configurations through the Processor aa 36 10 DisplayPort and embedded DisplayPort Resolutions for 1 2 4 Lanes Link Data Rate of RBR HBR and HBR24 44444 4 44x4xxxkkkk kk kk kk kk enses kaka aka ka kaka ka ka kak kk kak kk k ka a kk kk nnn nn 36 Ll System SERL Sil sao belde b ka naya d maya ta dln da Kimi vga DA hinds dis i na Ked S Wak KA Du SO dD 50 12 Processor Core Package State SUpport lk aaa kek ke kla k kala lala 50 13 Integrated Memory Controller Stat 8 s si say s aaa aaraa 50 14 PCLExpress Link States sz xuna bk atr rear seniee an Raa he Da RR FERA ab k l NEAR RR end ERRARE RN AE d 50 15 Direct Media Interface DMI States kik k k da hila kala Wak k aak darka bala d k k ala d E k hala na nun da 51 16 G S and C Interface State Combinations 00 cee kk kk kk kk kk kk kk kk kk ka K k kk kk a kk kk 51 17 D S and C Interface State COMbDINATION ec kk kk kk kk kk kk kk kK kk kK kak kk k kk kk ak kk 51 18 Coordination of Thread Power States at the Core LevelLMKhk KAk wW l kk kk kk ka 53 19 Coordination of Core Power States at the Package Level L LAL K k k kk kk 56 20 Deepest Package C State Available i i k s ulu al k lk k l kak h k kak kk Ak ka kala kk a aa al al kk a ala a da 59 21 Desktop Processor Thermal Spe
115. eferred until the previous transition is completed e The processor controls voltage ramp rates internally to ensure glitch free transitions e Because there is low transition latency between P states a significant number of transitions per second are possible Low Power Idle States When the processor is idle low power idle states C states are used to save power More power savings actions are taken for numerically higher C states However higher C states have longer exit and entry latencies Resolution of C states occur at the thread processor core and processor package level Thread level C states are available if Intel Hyper Threading Technology is enabled Long term reliability cannot be assured unless all the Low Power Idle States are enabled Idle Power Management Breakdown of the Processor Cores Core 0 State Core N State Processor Package State Entry and exit of the C states at the thread and core level are shown in the following figure Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 52 Order No 328897 010 m Power Management Processor n tel Figure 13 Table 18 4 2 3 Thread and Core C State Entry and Exit MWAIT C1 HLT _ gt MWAIT C7 a P_LVL4 I O Read MWAIT C1 HLT ee SALS C1E
116. efresh during STR Chip Select 1 per rank These signals are used to select O SA_CS 3 0 particular SDRAM components during the active state There is one Chip Select for each SDRAM rank DDR3 DDR3L On Die Termination Active Termination Control O SA_ODT 3 0 _ODT 3 0 DDR3 DDR3L Signal Name Description Direction Buffer Type Bank Select These signals define which banks are selected O SB_BS 2 0 within each SDRAM rank DDR3 DDR3L Write Enable Control Signal This signal is used with O SB_WE SB_RAS and SB_CAS along with SB_CS to define the SDRAM Commands DDR3 DDR3L RAS Control Signal This signal is used with SB CAS and O SB_RAS SB_WE along with SB_CS to define the SRAM Commands DDR3 DDR3L SB CAS CAS Control Signal This signal is used with SB_RAS and O SB_WE along with SB_CS to define the SRAM Commands DDR3 DDR3L Data Strobes SB_DQS 8 0 and its complement signal group SB_DQS 8 0 make up a differential strobe pair The data is captured at the I O SB DQSN 8 0 crossing point of SB DQS 8 0 and its SB DQS Z 8 0 during DDR3 DDR3L read and write transactions i Data Bus Channel B data signal interface to the SDRAM data I O SB_DQ 63 0 bus DDR3 DDR3L Memory Address These signals are used to provide the O SB_MA 15 0 multiplexed row and column address to the SDRAM DDR3 DDR3L continued Desktop 4th Generation Intel Core Processor Family Desktop Intel Pen
117. endent on the PCH SKU in the target platform Note The IMC supports a maximum of two DDR3 DDR3L DIMMs per channel thus allowing up to four device ranks per channel Note The support of DDR3 DDR3L frequencies and number of DIMMs per channel is SKU dependent Table 3 Processor DIMM Support by Product Processor Cores Package DIMM per Channel DDR3 DDR3L 1 DPC 1333 1600 Dual Core uLGA 2 DPC 1333 1600 1 DPC 1333 1600 Quad Core uLGA 2 DPC 1333 1600 DDR3 DDR3L Data Transfer Rates e 1333 MT s PC3 10600 e 1600 MT s PC3 12800 AIO platform DDR3 DDR3L SO DIMM Modules e Raw Card B Single Ranked x8 unbuffered non ECC e Raw Card F Dual Ranked x8 planar unbuffered non ECC Desktop platform UDIMM Modules e Raw Card A Single Ranked x8 unbuffered non ECC e Raw Card B Dual Ranked x8 unbuffered non ECC e Standard 1Gb 2Gb and 4Gb technologies and addressing are supported for x8 devices There is no support for memory modules with different technologies or capacities on opposite sides of the same memory module If one side of a memory module is populated the other side is either identical or empty Table 4 Supported UDIMM Module Configurations Raw DIMM DRAM DRAM of of of of Page Size Card Capacity Device Organization DRAM Physical Row Col Banks Version Technology Devices Devices Address Inside Ranks Bits DRAM Desktop Platforms Unbuffered Non ECC Supported DIMM Module Configu
118. erating systems on IA x86 processors Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron March 2015 Processor Family Datasheet Volume 1 of 2 Order No 328897 010 39 m n tel Processor Technologies e More reliable Due to the hardware support VMMs can now be smaller less complex and more efficient This improves reliability and availability and reduces the potential for software conflicts e More secure The use of hardware transitions in the VMM strengthens the isolation of VMs and further prevents corruption of one VM from affecting others on the same system Intel VT x Features The processor supports the following Intel VT x features e Extended Page Table EPT Accessed and Dirty Bits EPT A D bits enabled VMMs to efficiently implement memory management and page classification algorithms to optimize VM memory operations such as de fragmentation paging live migration and check pointing Without hardware support for EPT A D bits VMMs may need to emulate A D bits by marking EPT paging structures as not present or read only and incur the overhead of EPT page fault VM exits and associated software processing e Extended Page Table Pointer EPTP switching EPTP switching is a specific VM function EPTP switching allows guest software in VMX non root operation supported by EPT to request a different EPT paging structure hie
119. erature has dropped below the maximum operating temperature and the hysteresis timer has expired the TCC goes inactive and clock modulation ceases Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family March 2015 Datasheet Volume 1 of 2 Order No 328897 010 79 En n tel Processor Thermal Management Immediate Transition to Combined TM1 and TM2 When the TCC is activated the processor will sequentially step down the ratio multipliers and VIDs in an attempt to reduce the silicon temperature If the temperature continues to increase and exceeds the TCC activation temperature by approximately 5 C before the lowest ratio VID combination has been reached the processor will immediately transition to the combined TM1 TM2 condition The processor remains in this state until the temperature has dropped below the TCC activation point Once below the TCC activation temperature TM1 will be discontinued and TM2 will be exited by stepping up to the appropriate ratio VID state Critical Temperature Flag If TM2 is unable to reduce the processor temperature then TM1 will be also be activated TM1 and TM2 will then work together to reduce power dissipation and temperature It is expected that only a catastrophic thermal solution failure would create a situation where both TM1 and TM2 are active If TM1 and TM2 have both been active for greater than 20 m
120. erization Loading limits are for the package only and do not include the limits of the processor socket 4 Dynamic loading is defined as an 50g shock load 2X Dynamic Acceleration Factor with a 500g maximum thermal solution 8 3 Package Handling Guidelines The following table includes a list of guidelines on package handling in terms of recommended maximum loading on the processor IHS relative to a fixed substrate These package handling loads may be experienced during heatsink removal Table 59 Package Handling Guidelines Parameter Maximum Recommended Notes Shear 311 N 70 Ibf 1 4 Tensile 111 N 25 Ibf 2 4 Torque 3 95 N m 35 Ibf in 3 4 Notes 1 A shear load is defined as a load applied to the IHS in a direction parallel to the IHS top surface 2 Atensile load is defined as a pulling load applied to the IHS in a direction normal to the IHS surface 3 A torque load is defined as a twisting load applied to the IHS in an axis of rotation normal to the IHS top surface 4 These guidelines are based on limited testing for design characterization 8 4 Package Insertion Specifications The processor can be inserted into and removed from an LGA1150 socket 15 times The socket should meet the LGA1150 socket requirements detailed in the LGA1150 Socket Application Guide 8 5 Processor Mass Specification The typical mass of the processor is 27 0 g 0 95 oz This mass weight includes all the
121. essor cores and integrated graphics cores to run faster than the baseline frequency During a turbo event the processor can exceed its TDP power for brief periods Turbo is invoked opportunistically and automatically as long as the processor is conforming to its temperature power delivery and current specification limits Thus thermal solutions and platform cooling that are designed to less than thermal design guidance may experience thermal and performance issues since more applications will tend to run at or near the maximum power limit for significant periods of time 5 10 1 Intel Turbo Boost Technology Power Control and Reporting Package processor core and internal graphics core powers are self monitored and correspondingly reported out e With the processor turbo disabled rolling average power over 5 seconds will not exceed the TDP rating of the part for typical applications e With turbo enabled see Figure 22 on page 84 For the PLi Package rolling average of the power set in POWER LIMIT 1 TURBO POWER LIMIT MSR 0610h bits 14 0 over time window set in POWER LIMIT 1 TIME TURBO POWER LIMIT MSR 0610h bits 23 17 must be less than or equal to the TDP package power as read from the PACKAGE POWER SKU MSR 0614h for typical applications Power control is valid only when the processor is operating in turbo PL1 lower than the package TDP is not guaranteed For the PL2 Package power will be controlled to a value set in
122. f 2 89 intel Processor Signal Description 6 4 PCI Express Interface Signals Table 35 PCI Express Graphics Interface Signals Signal Name Description Direction Buffer Type PEG RCOMP PCI Express Resistance Compensation PEG_RXP 15 0 PCI Express Receive Differential Pair I PEG_RXN 15 0 PCI Express PEG_TXP 15 0 PCI Express Transmit Differential Pair O PEG_TXN 15 0 PCI Express 6 5 Display Interface Signals Table 36 Display Interface Signals Signal Name Description Direction Buffer Type FDI_TXP 1 0 Intel Flexible Display Interface Transmit Differential Pair O FDI_TXN 1 0 FDI DDIB_TXP 3 0 Digital Display Interface Transmit Differential Pair O DDIB_TXN 3 0 FDI DDIC_TXP 3 0 Digital Display Interface Transmit Differential Pair O DDIC_TXN 3 0 FDI DDID_TXP 3 0 Digital Display Interface Transmit Differential Pair O DDID_TXN 3 0 FDI FDI CSYNC Intel Flexible Display Interface Sync I CMOS Intel Flexible Display Interface Hot Plug Interrupt I DISP INT Asynchronous CMOS 6 6 Direct Media Interface DMI Table 37 Direct Media Interface DMI Processor to PCH Serial Interface Signal Name Description Direction Buffer Type DMI RXP 3 0 DMI Input from PCH Direct Media Interface receive I DMI RXN 3 0 differential pair DMI DMI TXP 3 0 DMI Output to PCH Direct Media Interface transmit O DMI TXN 3 0 differential pair DMI Desktop 4th Generation Inte
123. f pixel data for many common Windows operations The BLT engine can be used for the following e Move rectangular blocks of data between memory locations e Data alignment e To perform logical operations raster ops The rectangular block of data does not change as it is transferred between memory locations The allowable memory transfers are between cacheable system memory and frame buffer memory frame buffer memory and frame buffer memory and within system memory Data to be transferred can consist of regions of memory patterns or solid color fills A pattern is always 8 x 8 pixels wide and may be 8 16 or 32 bits per pixel The BLT engine expands monochrome data into a color depth of 8 16 or 32 bits BLTs can be either opaque or transparent Opaque transfers move the data specified to the destination Transparent transfers compare destination color to source color and write according to the mode of transparency selected Data is horizontally and vertically aligned at the destination If the destination for the BLT overlaps with the source memory location the BLT engine specifies which area in memory to begin the BLT transfer Hardware is included for all 256 raster operations source pattern and destination defined by Microsoft including transparent BLT The BLT engine has instructions to invoke BLT and stretch BLT operations permitting software to set up instruction buffers and use batch processing The BLT engine can perform
124. f the platform to resist attempts to change the controlling environment The Intel TXT platform will resist attempts by software processes to change the controlling environment or bypass the bounds set by the controlling environment Intel TXT is a set of extensions designed to provide a measured and controlled launch of system software that will then establish a protected environment for itself and any additional software that it may execute These extensions enhance two areas e The launching of the Measured Launched Environment MLE e The protection of the MLE from potential corruption The enhanced platform provides these launch and control interfaces using Safer Mode Extensions SMX The SMX interface includes the following functions e Measured Verified launch of the MLE e Mechanisms to ensure the above measurement is protected and stored in a secure location e Protection mechanisms that allow the MLE to control attempts to modify itself The processor also offers additional enhancements to System Management Mode SMM architecture for enhanced security and performance The processor provides new MSRs to e Enable a second SMM range e Enable SMM code execution range checking e Select whether SMM Save State is to be written to legacy SMRAM or to MSRs e Determine if a thread is going to be delayed entering SMM e Determine if a thread is blocked from entering SMM e Targeted SMI enable disable threads from responding to SM
125. fications aaa 104 52 Digital Display Interface Group DC Specifications c kk kk kk kk kk kk nmn 105 53 embedded DisplayPort eDP Group DC Specifications aaa 106 Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family March 2015 Datasheet Volume 1 of 2 Order No 328897 010 7 m n tel Processor Tables CMOS Signal Group DC Specifications cece na k la nian n a naba k ka WA WE WAL S nemen 106 GTL Signal Group and Open Drain Signal Group DC Specifications 106 PCI Express DC SpecificatiOns eese ka k da xa w k hk k l awa ak adan b j Qa la ak k da an EAR lk 107 Platform Environment Control Interface PECI DC Electrical Lim tS hkL W k k kk E 107 Processor Loading SpedcificatiOn 8 xak cay l ya xaka a eee eee dakan l ya nensem nen 110 Package Handling Guidelines s si s xaran tre ke tueantur a R k kr tme na Ae lec nu n aa aa a DAD aka jai 110 Processor Materials r pp xww lt rrrrmrmm 111 Processor Storage Specifications iecit reet n E b ka ete r d anaes bad r t dala y k ak DR RR 113 Processor Ball List by Signal Name ee kake kek emm kbk aka alal kelka kak ka eka a ka aa daa 115 Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor
126. ge during MRC boot training 12 Processor may be damaged if Vi exceeds the maximum voltage for extended periods 13 The MRC during boot training might optimize Roy outside the range specified Table 52 Digital Display Interface Group DC Specifications Symbol Parameter Min Typ Max Units VIL HPD Input Low Voltage 0 8 V Vin HPD Input High Voltage 2 25 3 6 V Vaux Tx pu peak to peak voltage at transmitting 0 39 1 38 V evice Aux peak to peak voltage at receiving _ Vaux Rx device 0 32 1 36 V Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron March 2015 Order No 328897 010 Processor Family Datasheet Volume 1 of 2 105 n n tel Processor Electrical Specifications Table 53 embedded DisplayPort eDP Group DC Specifications Symbol Parameter Min Typ Max Units Vit HPD Input Low Voltage 0 02 _ 0 21 V Vin HPD Input High Voltage 0 84 1 05 V VoL eDP_DISP_UTIL Output Low Voltage 0 1 Vcc V Vou eDP_DISP_UTIL Output High Voltage 0 9 Vcc _ V Rup eDP_DISP_UTIL Internal pull up 100 Q Rpown eDP_DISP_UTIL Internal pull down 100 _ Q C NE ee eee o3 gas v Vaux Rx a peak voltage at receiving 0 32 _ 1 36 v e ka COMP Resistance 24 75 25 25 25 Q Note 1 COMP resistance is to VCOMP_OUT Table 54 CMOS Signal Group DC Specifications Symbol Parameter Min
127. hardware clipping during BLTs Multi Graphics Controllers Multi Monitor Support The processor supports simultaneous use of the Processor Graphics Controller GT and a x16 PCI Express Graphics PEG device The processor supports a maximum of 2 displays connected to the PEG card in parallel with up to 2 displays connected to the processor and PCH When supporting Multi Graphics Multi Monitors drag and drop between monitors and the 2x8PEG is not supported Digital Display Interface DDI e The processor supports Three Digital Display x4 DDI interfaces that can be configured as DisplayPort HDMI or DVI DisplayPort can be configured to use 1 2 or 4 lanes depending on the bandwidth requirements and link data rate of RBR 1 62 GT s HBR 2 7 GT s and HBR2 5 4 GT s When configured as HDMI DDIx4 port can support 2 97 GT s In addition Digital Port D x4 DDI interface can also be configured to carry embedded DisplayPort eDPx4 Built in displays are only supported on Digital Port D One dedicated Intel FDI Port for legacy VGA support on the PCH Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron March 2015 Processor Family Datasheet Volume 1 of 2 Order No 328897 010 31 m n tel Processor Interfaces e The HDMI interface supports HDMI with 3D 4K Deep Color and x v Color The DisplayPort interface supports
128. hics cores to opportunistically increase frequency and or voltage above the guaranteed processor and graphics frequency for the given part Intel Graphics Dynamic Frequency Technology is a performance feature that makes use of unused package power and thermals to increase application performance The increase in frequency is determined by how much power and thermal budget is available in the package and the application demand for additional processor or graphics performance The processor core control is maintained by an embedded controller The graphics driver dynamically adjusts between P States to maintain optimal performance power and thermals The graphics driver will always try to place the graphics engine in the most energy efficient P state Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 64 Order No 328897 010 n Thermal Management Processor n tel 5 0 Thermal Management This chapter provides both component level and system level thermal management Topics covered include processor thermal specifications thermal profiles thermal metrology fan speed control adaptive thermal monitor THERMTRIP signal Digital Thermal Sensor DTS Intel Turbo Boost Technology package power control power plane control and turbo time parameter The processor requires a thermal solution to maintain
129. ial pairs that Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron March 2015 Processor Family Datasheet Volume 1 of 2 Order No 328897 010 33 m n te Processor Interfaces Figure 8 make up the TMDS data and clock channels These channels are used to carry video audio and auxiliary data In addition HDMI carries a VESA DDC The DDC is used by an HDMI Source to determine the capabilities and characteristics of the Sink Audio video and auxiliary control status data is transmitted across the three TMDS data channels The video pixel clock is transmitted on the TMDS clock channel and is used by the receiver for data recovery on the three data channels The digital display data signals driven natively through the PCH are AC coupled and needs level shifting to convert the AC coupled signals to the HDMI compliant digital signals The processor HDMI interface is designed in accordance with the High Definition Multimedia Interface with 3D 4K Deep Color and x v Color HDMI Overview HDMI Source HDMI Sink HDMI T E HDMI R E Y g Hot Plug Detect CEC Line optional Digital Video Interface The processor Digital Ports can be configured to drive DVI D DVI uses TMDS for transmitting data from the transmitter to the receiver which is similar to the HDMI protocol except for the audio and CEC Refe
130. ied with the voltage determined by the processor Serial Voltage IDentification SVID interface Table 46 on page 95 specifies the voltage level for the various VIDs 7 3 Vcc Voltage Identification VID The processor uses three signals for the serial voltage identification interface to support automatic selection of voltages The following table specifies the voltage level corresponding to the 8 bit VID value transmitted over serial VID A 1 in this table refers to a high voltage level and a 0 refers to a low voltage level If the voltage regulation circuit cannot supply the voltage that is requested the voltage regulator must disable itself VID signals are CMOS push pull drivers See the Voltage and Current Specifications section for the DC specifications for these signals The VID codes will change due to temperature and or current load changes to minimize the power of the part A voltage range is provided in the Voltage and Current Specifications section The specifications are set so that one voltage regulator can operate with all supported frequencies Individual processor VID values may be set during manufacturing so that two devices at the same core frequency may have different default VID settings This is shown in the VID range values in the Voltage and Current Specifications section The processor provides the ability to operate while transitioning to an adjacent VID and its associated voltage This will represent a DC shift in
131. iguration the furthest DIMM from the processor of any given channel must always be populated first 2 1 3 2 Intel Fast Memory Access Intel FMA Technology Enhancements The following sections describe the Just in Time Scheduling Command Overlap and Out of Order Scheduling Intel FMA technology enhancements Just in Time Command Scheduling The memory controller has an advanced command scheduler where all pending requests are examined simultaneously to determine the most efficient request to be issued next The most efficient request is picked from all pending requests and issued to system memory Just in Time to make optimal use of Command Overlapping Thus instead of having all memory access requests go individually through an arbitration mechanism forcing requests to be executed one at a time the requests can be started without interfering with the current request allowing for concurrent issuing of requests This allows for optimized bandwidth and reduced latency while maintaining appropriate command spacing to meet system memory protocol Command Overlap Command Overlap allows the insertion of the DRAM commands between the Activate Pre charge and Read Write commands normally used as long as the inserted commands do not affect the currently executing command Multiple commands can be issued in an overlapping manner increasing the efficiency of system memory protocol Out of Order Scheduling While leveraging the Just in Time Sched
132. ily Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 46 Order No 328897 010 Technologies Processor intel extensions to achieve the performance of fine grain locking while actually programming using coarse grain locks Details on Intel TSX NI are in the Inte Architecture Instruction Set Extensions Programming Reference 3 8 Intel 64 Architecture x2APIC The x2APIC architecture extends the xAPIC architecture that provides key mechanisms for interrupt delivery This extension is primarily intended to increase processor addressability Specifically x2APIC e Retains all key elements of compatibility to the xAPIC architecture Delivery modes Interrupt and processor priorities Interrupt sources Interrupt destination types e Provides extensions to scale processor addressability for both the logical and physical destination modes e Adds new features to enhance performance of interrupt delivery e Reduces complexity of logical destination mode interrupt delivery on link based architectures The key enhancements provided by the x2APIC architecture over xAPIC are the following e Support for two modes of operation to provide backward compatibility and extensibility for future platform innovations In xAPIC compatibility mode APIC registers are accessed through memory mapped interface to a 4K Byte page identical to the xAPIC architecture
133. indication that the Vcc and Vppg power supplies are stable and within specifications This requirement applies regardless of the S state of the processor Clean implies that the signal will remain low capable of sinking leakage current without glitches from the time that the power supplies are turned on until the supplies come within specification The signal must then transition monotonically to a high state I Asynchronous CMOS SKTOCC SKTOCC Socket Occupied PROC_DETECT Processor Detect This signal is pulled down directly 0 Ohms on the processor package to ground There is no connection to the processor silicon for this signal System board designers may use this signal to determine if the processor is present Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family Datasheet Volume 1 of 2 92 March 2015 Order No 328897 010 Signal Description Processor 6 11 Table 42 6 12 Table 43 6 13 Table 44 6 14 Table 45 Processor Power Signals Processor Power Signals intel Signal Name Description Direction Buffer Type VCC Processor core power rail Ref VCCIO_OUT Processor power reference for I O Ref VDDQ Processor I O supply voltage for DDR3 Ref VCOMP_OUT Processor power reference for PEG Display RCOMP Ref VIDALERT VIDS
134. instruction The deadline corresponding to the Timed MWAIT instruction expires e An interrupt directed toward a single thread wakes only that thread e If any thread in a core is in active in CO state the core s C state will resolve to CO state e Any interrupt coming into the processor package may wake any core e A system reset re initializes all processor cores Core CO State The normal operating state of a core where code is being executed Core C1 C1E State C1 C1E is a low power state entered when all threads within a core execute a HLT or MWAIT C1 C1E instruction A System Management Interrupt SMI handler returns execution to either Normal state or the C1 C1E state See the Intel 64 and IA 32 Architectures Software Developer s Manual for more information While a core is in C1 C1E state it processes bus snoops and snoops from other threads For more information on C1E state see Package C States on page 55 Core C3 State Individual threads of a core can enter the C3 state by initiating a P LVL2 I O read to the P BLK or an MWAIT C3 instruction A core in C3 state flushes the contents of its L1 instruction cache L1 data cache and L2 cache to the shared L3 cache while maintaining its architectural state All core clocks are stopped at this point Because the core s caches are flushed the processor does not wake any core that is in the C3 state when either a snoop is detected or when another core accesses cacheable
135. ion in the U S and or other countries Other names and brands may be claimed as the property of others Copyright 2013 2015 Intel Corporation All rights reserved Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 2 Order No 328897 010 m Contents Processor n tel j Contents Revision HlS O 9 1 011 tkO di UC O ID 10 1 1 Supported Technologies eski enin er kaza d zab kk kla nk r ka DR d k Galak j ik a KR kr 11 1 2 Iii tela CCS win idest D ka ean RM a wa S w SAR Mai Ea dui ar n d a Si WA DG kn raw 12 1 3 Power Management SUpport cs eiie rures hln nek n ekla E Kw nae Q REP Da n Ee b e e DAE asa 12 1 4 Thermal Management Support 4 4 a aaa aaa ada sa naa aa a 13 1 5 Package SUPPO Em 13 1 6 T rminol0GV meer RU 13 1 7 Related Doc m NtS sy sisi nuna 16 2 0 T I1 LO IF A CO sk suk kak xi kax nak ka ka kl a wak ka a a aki a w kaka a lrA kra ras a i a i i kr won r a di ji siw is a ar aya 18 2 1 System Memory Interface oci ergo nek n nda an n Mak w al gts n ben
136. iption Buffer Types Signal Description PCI Express PCI Express interface signals These signals are compatible with PCI Express 3 0 Signaling Environment AC Specifications and are AC coupled The buffers are not 3 3 V tolerant See the PCI Express Base Specification 3 0 DMI Direct Media Interface signals These signals are compatible with PCI Express 2 0 Signaling Environment AC Specifications but are DC coupled The buffers are not 3 3 V tolerant CMOS CMOS buffers 1 05V tolerant DDR3 DDR3L DDR3 DDR3L buffers 1 5 V tolerant A Analog reference or output May be used as a threshold voltage or for buffer compensation GTL Gunning Transceiver Logic signaling technology Ref Voltage reference signal Asynchronous 1 Signal has no timing relationship with any reference clock 1 Qualifier for a buffer type 6 1 System Memory Interface Signals Table 31 Memory Channel A Signals Signal Name Description Direction Buffer Type j Bank Select These signals define which banks are selected O SA_BS 2 0 within each SDRAM rank DDR3 DDR3L Write Enable Control Signal This signal is used with O SA_WE SA_RAS and SA_CAS along with SA_CS to define the SDRAM Commands DDR3 DDR3L continued Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family
137. irtual Machine Monitor software enables multiple robust independent software environments inside a single platform Inte Intel Virtualization Technology Intel VT for Directed I O Intel VT d is a hardware assist under system software Virtual Machine Manager or OS control for enabling T O device virtualization Intel VT d also brings robust security by providing protection from errant DMAs by using DMA remapping a key feature of Intel VT d IOV I O Virtualization ISI Inter Symbol Interference ITPM Integrated Trusted Platform Module LCD Liquid Crystal Display LFM Low Frequency Mode LFM is Pn in the P state table It can be read at MSR CEh 47 40 LFP Local Flat Panel LPDDR3 Low Power Third generation Double Data Rate SDRAM memory technology MCP Multi Chip Package continued Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family Datasheet Volume 1 of 2 14 March 2015 Order No 328897 010 Introduction Processor intel Term Description MFM Minimum Freguency Mode MFM is the minimum ratio supported by the processor and can be read from MSR CEh 55 48 MLE Measured Launched Environment MLC Mid Level Cache MSI Message Signaled Interrupt MSL Moisture Sensitive Labeling MSR Model
138. l Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 90 Order No 328897 010 Signal Description Processor 6 7 Table 38 6 8 Table 39 Phase Locked Loop PLL Signals Phase Locked Loop PLL Signals intel Signal Name Description Direction Buffer Type BCLKP Differential bus clock input to the processor I BCLKN Diff Clk DPLL_REF_CLKP Embedded Display Port PLL Differential Clock In I DPLL_REF_CLKN 135 MHz Diff Clk SSC_DPLL_REF_CLKP Spread Spectrum Embedded DisplayPort PLL I SSC DPLL REF CLKN Differential Clock In 135 MHz Diff Clk Testability Signals Testability Signals Signal Name Description Direction Buffer Type Breakpoint and Performance Monitor Signals BPM I7 Outputs from the processor that indicate the status of I O 7 0 breakpoints and programmable counters used for GTL monitoring processor performance Debug Reset This signal is used only in systems where DBR no debug port is implemented on the system board o DBR is used by a debug port interposer so that an in target probe can drive system reset Processor Ready This signal is a processor output o PRDY used by debug tools to determine processor debug readiness GTL PREO Processor Request This signal is used by debug tools I Q to request debug operation of the processor GTL Tes
139. l Temperature Sensor DTS reaches a value of 0 DTS temperatures reported using PECI may not equal zero when PROCHOT is activated the TCC will be activated and the PROCHOT signal will be asserted if configured as bi directional This indicates the processor temperature has met or exceeded the factory calibrated trip temperature and it will take action to reduce the temperature Upon activation of the TCC the processor will stop the core clocks reduce the core ratio multiplier by 1 ratio and restart the clocks All processor activity stops during this frequency transition that occurs within 2 us Once the clocks have been restarted at the new lower frequency processor activity resumes while the core voltage is reduced by the internal voltage regulator Running the processor at the lower frequency and voltage will reduce power consumption and should allow the processor to cool off If after 1 ms the processor is still too hot the temperature has not dropped below the TCC activation point DTS still 0 and PROCHOT is still active then a second frequency and voltage transition will take place This sequence of temperature checking and frequency and voltage reduction will continue until either the minimum frequency has been reached or the processor temperature has dropped below the TCC activation point If the processor temperature remains above the TCC activation point even after the minimum frequency has been reached then clock modulation desc
140. le system Intel VT comprises technology components to support virtualization of platforms based on Intel architecture microprocessors and chipsets Intel Virtualization Technology Intel VT for IA 32 Intel 64 and Intel Architecture Intel VT x added hardware support in the processor to improve the virtualization performance and robustness Intel Virtualization Technology for Directed I O Intel VT d extends Intel VT x by adding hardware assisted support to improve I O device virtualization performance Intel VT x specifications and functional descriptions are included in the Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3B and is available at http www intel com products processor manuals index htm The Intel VT d specification and other Intel VT documents can be referenced at http www intel com technology virtualization index htm https sharedspaces intel com sites PCDC SitePages Ingredients ingredient aspx ing VT Intel VT x Objectives Intel VT x provides hardware acceleration for virtualization of IA platforms Virtual Machine Monitor VMM can use Intel VT x features to provide an improved reliable virtualized platform By using Intel VT x a VMM is e Robust VMMs no longer need to use paravirtualization or binary translation This means that off the shelf operating systems and applications can be run without any special steps e Enhanced Intel VT enables VMMs to run 64 bit guest op
141. may be retrieved simultaneously since they are ensured to Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron March 2015 Processor Family Datasheet Volume 1 of 2 Order No 328897 010 21 m n tel Processor Interfaces be on opposite channels Use Dual Channel Symmetric mode when both Channel A and Channel B DIMM connectors are populated in any order with the total amount of memory in each channel being the same When both channels are populated with the same memory capacity and the boundary between the dual channel zone and the single channel zone is the top of memory the IMC operates completely in Dual Channel Symmetric mode Note The DRAM device technology and width may vary from one channel to the other 2 1 3 1 System Memory Frequency In all modes the frequency of system memory is the lowest frequency of all memory modules placed in the system as determined through the SPD registers on the memory modules The system memory controller supports one or two DIMM connectors per channel The usage of DIMM modules with different latencies is allowed but in that case the worst latency among two channels will be used For dual channel modes both channels must have a DIMM connector populated and for single channel mode only a single channel may have one or both DIMM connectors populated Note In a two DIMM Per Channel 2DPC layout memory conf
142. near the hottest portions of the die e It can accurately track the die temperature and ensure that the Adaptive Thermal Monitor is not excessively activated Temperature values from the DTS can be retrieved through e A software interface using processor Model Specific Register MSR e A processor hardware interface as described in Platform Environmental Control Interface PECI on page 37 When temperature is retrieved by the processor MSR it is the instantaneous temperature of the given core When temperature is retrieved using PECI it is the average of the highest DTS temperature in the package over a 256 ms time window Intel recommends using the PECI reported temperature for platform thermal control that benefits from averaging such as fan speed control The average DTS temperature may not be a good indicator of package Adaptive Thermal Monitor activation or rapid increases in temperature that triggers the Out of Specification status bit within the PACKAGE THERM STATUS MSR 1Bih and IA32 THERM STATUS MSR 19Ch Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron March 2015 Processor Family Datasheet Volume 1 of 2 Order No 328897 010 81 n n tel Processor Thermal Management Code execution is halted in C1 or deeper C states Package temperature can still be monitored through PECI in lower C states Unlike traditional thermal devices the
143. ng isolation and routing of interrupts from devices and external interrupt controllers to appropriate VMs e Reliability for recording and reporting to system software DMA and interrupt errors that may otherwise corrupt memory or impact VM isolation Intel VT d accomplishes address translation by associating a transaction from a given I O device to a translation table associated with the Guest to which the device is assigned It does this by means of the data structure in the following illustration This table creates an association between the device s PCI Express Bus Device Function B D F number and the base address of a translation table This data structure is populated by a VMM to map devices to translation tables in accordance with the device assignment restrictions above and to include a multi level translation table VT d Table that contains Guest specific address translations Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family March 2015 Datasheet Volume 1 of 2 Order No 328897 010 41 m n tel Processor Technologies Figure 10 Device to Domain Mapping Structures Dev 31 Func 7 Context entry 255 Dev 0 Func 1 Dev 0 Func 0 Context entry0 gt A Bus 255 Root entry 255 Context entry Table Address Translation EL T
144. nology Intel HT Technology is available on select Intel Core processors It requires an Intel HT Technology enabled system Consult your PC manufacturer Performance will vary depending on the specific hardware and software used Not available on Intel Core i5 750 For more information including details on which processors support Intel HT Technology visit http www intel com info hyperthreading Intel High Definition Audio Intel HD Audio requires an Intel HD Audio enabled system Consult your PC manufacturer for more information Sound quality will depend on equipment and actual implementation For more information about Intel HD Audio refer to http www intel com design chipsets hdaudio htm Intel 64 architecture requires a system with a 64 bit enabled processor chipset BIOS and software Performance will vary depending on the specific hardware and software you use Consult your PC manufacturer for more information For more information visit http www intel com content www us en architecture and technology microarchitecture intel 64 architecture general html Intel Virtualization Technology Intel VT requires a computer system with an enabled Intel processor BIOS and virtual machine monitor VMM Functionality performance or other benefits will vary depending on hardware and software configurations Software applications may not be compatible with all operating systems Consult your PC manufacturer For m
145. nt Number Location 2 of 2 Desktop 4th Generation Intel Core9 Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron9 Processor Family Datasheet Volume 328898 Update Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron9 Processor Family Specification 328899 continued Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family Datasheet Volume 1 of 2 16 March 2015 Order No 328897 010 Introduction Processor intel Document Document Number Location Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family Desktop Intel Celeron Processor Family and Intel Xeon 328900 Processor E3 1200 v3 Product Family Thermal Mechanical Design Guidelines LGA1150 Socket Application Guide 328999 Intel 8 Series C220 Series Chipset Family Platform Controller Hub PCH 328904 Datasheet Intel 8 Series C220 Series Chipset Family Platform Controller Hub PCH Pet 328905 Specification Update Intel 8 Series C220 Series Chipset Family Platform Controller Hub PCH Thermal A a es P 328906 Mechanical Specifications and Design Guidelines Intel 9 Series Chipset Family Platform Controller Hub PCH Datasheet 330550 Intel 9 Series
146. o n n da bak a n k DEAR N 18 2 1 1 System Memory Technology SupDOrt ed M hk A Avkhk kh k kllkkkkkkkk eens kk kk kk kk e 19 2 1 2 System Memory Timing SUp DOF y 33y i lt k kalek dina b n emnes a Ok Aa 20 2 1 3 System Memory Organization MOdeS MhK KAk C k L kkk kk kk kk kk kkkkkkkkkkkk kaka kak ka 21 2 2 PCI Express Interface kan lek bane dli eni d ak TR dian k lind lA V na r k kaba A bke K n 4 dik RR UNA A RO V n er k ba 23 2 2 1 PCI Express SUPPOMt ti a ar ttr teer Minaka ba kun d rena da k kura tele halk V tani Yaw day k 23 2 2 2 PCI Express Architecture y a teal ur ee tha a k b naka x Poen iv RE Rae ua HEAR NAA MiN 24 2 2 3 PCI Express Configuration Mechanism csse nnn 24 2 3 Direct Media Interface DMI eeeeseseseeeeses kan kaka ke ka R da wak ak leka ka ada aa e hu kan aa aa daa d a ann nn 26 274 Processor Gf plii s sadu E 28 2 5 Processor Graphics Controller G1 wcscseiceccscesescececsseeetnegaeassesaegeneviedeecedeaaasensebayecnerers 28 2 5 1 3D and Video Engines for Graphics Processing aaa 29 2 5 2 Multi Graphics Controllers Multi Monitor Support sesseesne 31 2 6 Digital Display Interface DDI jay anak naka raa n nekan adan mne eene ese 31 2 7 Intel Flexible Display Interface Intel FDI cesses nnns 37 2 8 Platform Environmental Control Interface PECI s sssssssssssrssrrrrr
147. o translate the memory mapped PCI Express configuration space accesses from the host processor to PCI Express configuration cycles To maintain compatibility with PCI configuration addressing mechanisms it is recommended that system software access the enhanced configuration space using 32 bit operations 32 bit aligned only See the PCI Express Base Specification for details of both the PCI compatible and PCI Express Enhanced configuration mechanisms and transaction rules PCI Express Port The PCI Express interface on the processor is a single 16 lane x16 port that can also be configured at narrower widths The PCI Express port is being designed to be compliant with the PCI Express Base Specification Revision 3 0 PCI Express Lanes Connection The following figure demonstrates the PCIe lane mapping Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family March 2015 Datasheet Volume 1 of 2 Order No 328897 010 25 n n tel Processor Interfaces Figure 4 PCI Express Typical Operation 16 Lanes Mapping o 9 c o o e Tv gt lt T e 1 X 4 Controller h ED El E 8 s x B 2 3 Direct Media Interface DMI Direct Media Interface DMI connects the processor and the PCH Next generation DMI2 is supported Note Only DMI x4 configuration is supported e DMI 2 0 suppo
148. oaded cores This enhancement is mostly beneficial for high interrupt scenarios like Gigabit LAN WLAN peripherals and so on 3 10 Execute Disable Bit The Execute Disable Bit allows memory to be marked as executable when combined with a supporting operating system If code attempts to run in non executable memory the processor raises an error to the operating system This feature can prevent some classes of viruses or worms that exploit buffer overrun vulnerabilities and can thus help improve the overall security of the system See the Inte 64 and IA 32 Architectures Software Developer s Manuals for more detailed information 3 11 Supervisor Mode Execution Protection SMEP Supervisor Mode Execution Protection provides the next level of system protection by blocking malicious software attacks from user mode code when the system is running in the highest privilege level This technology helps to protect from virus attacks and unwanted code from harming the system For more information refer to Intel 64 and IA 32 Architectures Software Developer s Manual Volume 3A at http www intel com Assets PDF manual 253668 pdf Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 48 Order No 328897 010 Power Management Processor n te 4 0 Power Management This chapter provides information on the following
149. ol aoh 1 1300 0 o o lolo Jo o 20h 0 8100 0 l loo lololo la nh 1 1400 continued continued Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 Order No 328897 010 95 Processor Electrical Specifications 3 rr o B B B B B B B B Hex Vec B B B B B B B B Hex Vec i ijiji i i i i il i li i li Li Jii tjt tt tt t t t tt ttt t t 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 1 0 0 0 0 1 0 42h 1 1500 0 110 01 010 64h 1 4900 0 1 0 0 0 0 1 1 43h 1 1600 O 1 1 0 0 1 0 1 65h 1 5000 0 1 0 0 0 1 0 0 44h 1 1700 O 1 1 0 0 1 1 0 66h 1 5100 0 1 0 0 0 1 0 1 45h 1 1800 O 1 1 0 0 1 1 1 67h 1 5200 0 1 0 0 0 1 1l 0 46h 1 1900 0 110 1J 0 010 68h 1 5300 0 1 0 0 0 1 1 1 47h 1 2000 O 1 1 0 1 0 0 1 69h 1 5400 O 1 0 0 1 0 0 0 48h 1 2100 O 1 1 0 1 0 1 0 6Ah 1 5500 0 1 0 0 1 0 0 1 49h 1 2200 O 1 1 0 1 0 1 1 6Bh 1 5600 0 1 0 0 1 0 1 0J 4Ah 1 2300 0 110 11 0 0 6Ch 1 5700 0 1 0 01 0 1 1 4Bh 1 2400 O 1 1 0 1 1 0 1 6Dh 1 5800 0 1 0 0 1 1 0 0J 4Ch 1 2500 0 11011111 0 6Eh 1 5900 0 1 0 0 11 0 111 4Dh 1 2600 0 1 1 0 1 1 1 1 6Fh 1 6000 0
150. on Layer Data Link Layer and Physical Layer See the PCI Express Base Specification 3 0 for details of PCI Express architecture 2 2 3 PCI Express Configuration Mechanism The PCI Express external graphics link is mapped through a PCI to PCI bridge structure Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 24 Order No 328897 010 m Interfaces Processor n tel j Figure 3 PCI Express Related Register Structures in the Processor PCI PCI Bridge PCI PCI PEGO representing Compatible Express root PCI Host Bridge Device Express ports Device Device 1 and Device 0 Device 6 DMI PCI Express extends the configuration space to 4096 bytes per device function as compared to 256 bytes allowed by the conventional PCI specification PCI Express configuration space is divided into a PCI compatible region that consists of the first 256 bytes of a logical device s configuration space and an extended PCI Express region that consists of the remaining configuration space The PCI compatible region can be accessed using either the mechanisms defined in the PCI specification or using the enhanced PCI Express configuration access mechanism described in the PCI Express Enhanced Configuration Mechanism section The PCI Express Host Bridge is required t
151. or core to opportunistically and automatically run faster than its rated operating frequency render clock if it is operating below power temperature and current limits The Intel Turbo Boost Technology 2 0 feature is designed to increase performance of both multi threaded and single threaded workloads Maximum frequency is dependant on the SKU and number of active cores No special hardware support is necessary for Intel Turbo Boost Technology 2 0 BIOS and the operating system can enable or disable Intel Turbo Boost Technology 2 0 Compared with previous generation products Intel Turbo Boost Technology 2 0 will increase the ratio of application power to TDP Thus thermal solutions and platform cooling that are designed to less than thermal design guidance might experience thermal and performance issues since more applications will tend to run at the maximum power limit for significant periods of time Intel Turbo Boost Technology 2 0 may not be available on all SKUs Intel Turbo Boost Technology 2 0 Frequency The processor rated frequency assumes that all execution cores are running an application at the thermal design power TDP However under typical operation not all cores are active Therefore most applications are consuming less than the TDP at the rated frequency To take advantage of the available thermal headroom the active cores can increase their operating frequency To determine the highest performance frequency amongst a
152. ore information visit http www intel com go virtualization The original equipment manufacturer must provide TPM functionality which requires a TPM supported BIOS TPM functionality must be initialized and may not be available in all countries For Enhanced Intel SpeedStep Technology see the Processor Spec Finder at http ark intel com or contact your Intel representative for more information ntel AES NI requires a computer system with an AES NI enabled processor as well as non Intel software to execute the instructions in the correct sequence AES NI is available on select Intel processors For availability consult your reseller or system manufacturer For more information see http software intel com en us articles intel advanced encryption standard instructions aes ni ntel Active Management Technology Intel AMT should be used by a knowledgeable IT administrator and requires enabled systems software activation and connection to a corporate network Intel AMT functionality on mobile systems may be limited in some situations Your results will depend on your specific implementation Learn more by visiting Intel Active Management Technology No computer system can provide absolute security under all conditions Intel Trusted Execution Technology Intel TXT requires a computer with ntel Virtualization Technology an Intel TXT enabled processor chipset BIOS Authenticated Code Modules and an Intel TXT compatible measured
153. own Dynamic power down of memory is employed during normal operation Based on idle conditions a given memory rank may be powered down The IMC implements aggressive CKE control to dynamically put the DRAM devices in a power down state The processor core controller can be configured to put the devices in active power down CKE de assertion with open pages or pre charge power down CKE de Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 62 Order No 328897 010 m Power Management Processor n tel 4 3 2 4 4 3 3 4 3 4 4 4 4 5 assertion with all pages closed Pre charge power down provides greater power savings but has a bigger performance impact since all pages will first be closed before putting the devices in power down mode If dynamic power down is enabled all ranks are powered up before doing a refresh cycle and all ranks are powered down at the end of refresh DRAM I O Power Management Unused signals should be disabled to save power and reduce electromagnetic interference This includes all signals associated with an unused memory channel Clocks CKE ODE and CS signals are controlled per DIMM rank and will be powered down for unused ranks The I O buffer for an unused signal should be tri stated output driver disabled the input receiver differential sense amp should
154. pation and temperature With a properly designed and characterized thermal solution it is anticipated that the TCC will only be activated for very short periods of time when running the most power intensive applications The processor performance impact due to these brief periods of TCC activation is expected to be so minor that it would be immeasurable An under designed thermal solution that is not able to prevent excessive activation of the TCC in the anticipated ambient environment may cause a noticeable performance loss and in some cases may result in a Tcase that exceeds the specified maximum temperature and may affect the long term reliability of the processor In addition a thermal solution that is significantly under designed may not be capable of cooling the processor even when the TCC is active continuously See the appropriate processor Thermal Mechanical Design Guidelines for information on designing a compliant thermal solution The Thermal Monitor does not require any additional hardware software drivers or interrupt handling routines The following sections provide more details on the different TCC mechanisms used by the processor Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 78 Order No 328897 010 Thermal Management Processor n tel Frequency Control When the Digita
155. play Interface Intel FDI e The Intel Flexible Display Interface Intel FDI passes display data from the processor source to the PCH sink for display through a display interface on the PCH e Intel FDI supports 2 lanes at 2 7 GT s fixed frequency This can be configured to 1 or 2 lanes depending on the bandwidth requirements e Intel FDI supports 8 bits per color only e Side band sync pin FDI_CSYNC e Side band interrupt pin DISP INT This carries combined interrupt for HPDs of all the ports AUX and I C completion events and so on e Intel FDI is not encrypted as it drives only VGA and content protection is not supported on VGA Platform Environmental Control Interface PECI PECI is an Intel proprietary interface that provides a communication channel between Intel processors and external components like Super I O SIO and Embedded Controllers EC to provide processor temperature Turbo TDP and memory throttling control mechanisms and many other services PECI is used for platform thermal management and real time control and configuration of processor features and performance PECI Bus Architecture The PECI architecture is based on a wired OR bus that the clients as processor PECI can pull up high with strong drive The idle state on the bus is near zero The following figure demonstrates PECI design and connectivity While the host originator can be a third party PECI host one of the PECI clients is a p
156. pportunities for many applications In addition to the vector extensions this generation of Intel processors adds new bit manipulation instructions useful in compression encryption and general purpose software For more information on Intel AVX see http www intel com software avx 3 6 Intel Advanced Encryption Standard New Instructions Intel AES NI The processor supports Intel Advanced Encryption Standard New Instructions Intel AES NI that are a set of Single Instruction Multiple Data SIMD instructions that enable fast and secure data encryption and decryption based on the Advanced Encryption Standard AES Intel AES NI are valuable for a wide range of cryptographic applications such as applications that perform bulk encryption decryption authentication random number generation and authenticated encryption AES is broadly accepted as the standard for both government and industry applications and is widely deployed in various protocols Intel AES NI consists of six Intel SSE instructions Four instructions AESENC AESENCLAST AESDEC and AESDELAST facilitate high performance AES encryption and decryption The other two AESIMC and AESKEYGENASSIST support the AES key expansion procedure Together these instructions provide a full hardware for supporting AES offering security high performance and a great deal of flexibility PCLMULQDQ Instruction The processor supports the carry less multiplication instruction PCLMULQD
157. r Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 28 Order No 328897 010 m Interfaces Processor n tel j Figure 5 2 5 1 Processor Graphics Controller Unit Block Diagram Full MPEG2 VCI AVC Decode Fixed Function Post Processing Full AVC Encode Partial MPEG2 VCI Encode 3D and Video Engines for Graphics Processing The Gen 7 5 3D engine provides the following performance and power management enhancements 3D Pipeline The 3D graphics pipeline architecture simultaneously operates on different primitives or on different portions of the same primitive All the cores are fully programmable increasing the versatility of the 3D Engine 3D Engine Execution Units e Supports up to 20 EUs The EUs perform 128 bit wide execution per clock e Support SIMD8 instructions for vertex processing and SIMD16 instructions for pixel processing Vertex Fetch VF Stage The VF stage executes 3DPRIMITIVE commands Some enhancements have been included to better support legacy D3D APIs as well as SGI OpenGL Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron March 2015 Processor Family Datasheet Volume 1 of 2 Order No 328897 010 29 m n tel Processor Interfaces Vertex Shader VS Stage The VS stage performs shading of
158. r to the HDMI section for more information on the signals and data transmission To drive DVI I through the back panel the VGA DDC signals are connected along with the digital data and clock signals from one of the Digital Ports When a system has support for a DVI I port then either VGA or the DVI D through a single DVI I connector can be driven but not both simultaneously The digital display data signals driven natively through the processor are AC coupled and need level shifting to convert the AC coupled signals to the HDMI compliant digital signals Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 34 Order No 328897 010 m Interfaces Processor n tel j Table 8 embedded DisplayPort embedded DisplayPort eDP is an embedded version of the DisplayPort standard oriented towards applications such as notebook and All In One PCs Digital Port D can be configured as eDP Like DisplayPort embedded DisplayPort also consists of a Main Link Auxiliary channel and an optional Hot Plug Detect signal The eDP on the processor can be configured for 2 or 4 lanes The processor supports embedded DisplayPort eDP Standard Version 1 2 and VESA embedded DisplayPort Standard Version 1 2 Integrated Audio e HDMI and display port interfaces carry audio along with video e Processor support
159. rarchy This is a feature by which software in VMX non root operation can request a change of EPTP without a VM exit Software can choose among a Set of potential EPTP values determined in advance by software in VMX root operation e Pause loop exiting Support VMM schedulers seeking to determine when a virtual processor of a multiprocessor virtual machine is not performing useful work This situation may occur when not all virtual processors of the virtual machine are currently scheduled and when the virtual processor in question is in a loop involving the PAUSE instruction The new feature allows detection of such loops and is thus called PAUSE loop exiting The processor core supports the following Intel VT x features e Extended Page Tables EPT EPT is hardware assisted page table virtualization It eliminates VM exits from the guest operating system to the VMM for shadow page table maintenance e Virtual Processor IDs VPID Ability to assign a VM ID to tag processor core hardware structures such as TLBs This avoids flushes on VM transitions to give a lower cost VM transition time and an overall reduction in virtualization overhead e Guest Preemption Timer Mechanism for a VMM to preempt the execution of a guest operating system after an amount of time specified by the VMM The VMM sets a timer value before entering a guest The feature aids VMM developers in flexibility and Quality of Service
160. rations A 1 GB 1 Gb 128M X8 8 1 14 10 8 8K continued Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family March 2015 Datasheet Volume 1 of 2 Order No 328897 010 19 intel Processor Interfaces Raw DIMM DRAM DRAM of of of of Page Size Card Capacity Device Organization DRAM Physical Row Col Banks Version Technology Devices Devices Address Inside Ranks Bits DRAM 2 GB 1 Gb 128 MX8 16 2 14 10 8 8K 4 GB 2 Gb 256 MX8 16 2 15 10 8 8K B 4 GB 4 Gb 512 MX8 8 1 15 10 8 8K 8 GB 4 Gb 512 MX8 16 2 16 10 8 8K Note DIMM module support is based on availability and is subject to change Table 5 Supported SO DIMM Module Configurations AIO Only Raw Card DIMM DRAM of DRAM of Row Col of Banks Page Size Version Capacity Organization Devices Address Bits Inside DRAM 1 GB 128 M x 8 8 14 10 8 8K B 2 GB 256Mx8 8 15 10 8 8K 4 GB 512Mx8 8 16 10 8 8K 2 GB 128Mx8 16 14 10 8 8K F 4 GB 256Mx8 16 15 10 8 8K 8 GB 512Mx8 16 16 10 8 8K Note System memory configurations are based on availability and are subject to change 2 1 2 System Memory Timing Support The IMC supports the following DDR3 DDR3L Speed Bin CAS Write Latency CWL and command signal mode timings on the main memory interface e tCL CAS Latency e tRCD Activate Command to READ or
161. ribed below at that minimum frequency will be initiated There is no end user software or hardware mechanism to initiate this automated TCC activation behavior A small amount of hysteresis has been included to prevent rapid active inactive transitions of the TCC when the processor temperature is near the TCC activation temperature Once the temperature has dropped below the trip temperature and the hysteresis timer has expired the operating frequency and voltage transition back to the normal system operating point using the intermediate VID frequency points Transition of the VID code will occur first to insure proper operation as the frequency is increased Clock Modulation Clock modulation is a second method of thermal control available to the processor Clock modulation is performed by rapidly turning the clocks off and on at a duty cycle that should reduce power dissipation by about 50 typically a 30 50 duty cycle Clocks often will not be off for more than 32 microseconds when the TCC is active Cycle times are independent of processor frequency The duty cycle for the TCC when activated by the Thermal Monitor is factory configured and cannot be modified It is possible for software to initiate clock modulation with configurable duty cycles A small amount of hysteresis has been included to prevent rapid active inactive transitions of the TCC when the processor temperature is near its maximum operating temperature Once the temp
162. rmal characterization parameter refer to the processor Thermal Mechanical Design Guidelines see Related Documents section 5 Maximum Tcase Thermal Profile is the specification that must be complied to Any Attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other system components 6 Tcase max at Platform TDP is calculated using the maximum Tcase Thermal Profile and the platform TDP 7 ATCA Reference Heatsink supports Socket B and is not tooled for Socket H Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron March 2015 Order No 328897 010 Processor Family Datasheet Volume 1 of 2 77 En n tel Processor Thermal Management 5 6 Processor Temperature A software readable field in the TEMPERATURE TARGET register contains the minimum temperature at which the TCC will be activated and PROCHOT will be asserted The TCC activation temperature is calibrated on a part by part basis and normal factory variation may result in the actual TCC activation temperature being higher than the value listed in the register TCC activation temperatures may change based on processor stepping frequency or manufacturing efficiencies 5 7 Adaptive Thermal Monitor The Adaptive Thermal Monitor feature provides an enhanced method for controlling the processor temperature when th
163. rocessor PCG 2013A Thermal Profile Figure 18 Thermal Test Vehicle Thermal Profile for Processor PCG 2013A 70 4 T un Trase 0 51 Power 48 5 TIV Case Temperature C un un 40 T T T T T T T T 1 0 5 10 15 20 25 30 35 40 TTV Power W See the following table for discrete points that constitute the thermal profile Table 25 Thermal Test Vehicle Thermal Profile for Processor PCG 2013A Power W Tcase max C Power W Tcase max C Y 0 51 Power 48 5 30 63 80 0 48 50 32 64 82 2 49 52 34 65 84 4 50 54 35 66 35 6 51 56 8 52 58 10 53 60 12 54 62 14 55 64 16 56 66 18 57 68 20 58 70 22 59 72 24 60 74 26 61 76 28 62 78 continued Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 72 Order No 328897 010 n Thermal Management Processor n tel 5 2 Figure 19 Note 5 3 Thermal Metrology The maximum Thermal Test Vehicle TTV case temperatures Tcase max can be derived from the data in the appropriate TTV thermal profile earlier in this chapter The TTV Tease is measured at the geometric top center of the TTV integrated heat spreader IHS The following figure illustrates the location where Tcase temperature measurements shoul
164. rocessor PECI device Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron March 2015 Processor Family Datasheet Volume 1 of 2 Order No 328897 010 37 intel Figure 9 PECI Host Clients Connection Example Processor Interfaces EO H gt nX PECI Q2 s 1X Host Originator Ceci 10pF Node Q3 nX PECI Client Additional PECI Clients Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family Datasheet Volume 1 of 2 38 March 2015 Order No 328897 010 Technologies Processor n tel 3 0 3 1 Technologies This chapter provides a high level description of Intel technologies implemented in the processor The implementation of the features may vary between the processor SKUs Details on the different technologies of Intel processors and other relevant external notes are located at the Intel technology web site http www intel com technology Intel Virtualization Technology Intel VT Intel virtualization Technology Intel VT makes a single system appear as multiple independent systems to software This allows multiple independent operating systems to run simultaneously on a sing
165. rocessor and graphics cores This is contrary to the internally generated Adaptive Thermal Monitor response e Clock modulation is not activated The TCC will remain active until the system de asserts PROCHOT The processor can be configured to generate an interrupt upon assertion and de assertion of the PROCHOT signal Refer to the appropriate Platform Thermal Mechanical Design Guidelines see Related Doucments section for details on implementing the bi directional PROCHOT feature Note Toggling PROCHOT more than once in 1 5 ms period will result in constant Pn state of the processor Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 80 Order No 328897 010 Thermal Management Processor n tel Note 5 8 5 9 A corner case exists for PROCHOT configured as a bi directional signal that can cause several milliseconds of delay to a system assertion of PROCHOT when the output function is asserted As an output PROCHOT Processor Hot will go active when the processor temperature monitoring sensor detects that one or more cores has reached its maximum safe operating temperature This indicates that the processor Thermal Control Circuit TCC has been activated if enabled As an input assertion of PROCHOT by the system will activate the TCC for all cores TCC activation when PRO
166. rsssrrrnrserrnnrrrrnrnsrnnrnns 37 2 9 1 PECL B s Architecture ouis cpi teet D ran biwa e Ne eru Rea cR NN EA SAFE NDA ERE 37 3 0 TECHNMOlLOGICS me 39 3 1 Intel Virtualization Technology Intel VT ccccccescceeceeeeeeeceeeaeeceseeeeeaeesaeeeeeeaeeseeees 39 3 2 Intel Trusted Execution Technology Intel TXT ccccccseccceeeeeeeeeeeeeeeeeesaeeeseeesaeeeenes 43 3 3 Intel Hyper Threading Technology Intel HT TechnolOgy l E 44 3 4 Intel Turbo Boost Technology 2 0 cccccesecseeceeeeeaeeeaeeeeseseeaeseseeeeseeeseeeeeeeeeeeeseeeeeens 45 3 5 Intel Advanced Vector Extensions 2 0 Intel AVX2 44444444k kk kk kk kk ka 45 3 6 Intel Advanced Encryption Standard New Instructions Intel AES NI 46 3 7 Intel Transactional Synchronization Extensions New Instructions Intel TSX NI 46 3 8 Intel 64 Architecture x2APIC ass 47 3 9 Power Aware Interrupt Routing PAIR a aaa aaraa 48 3 10 Execute Disable Bit i oreet rr ren et reina b ka RR needa Apis tints Mr d URN ROS A GU RR 48 3 11 Supervisor Mode Execution Protection SMEP cceeeeeeeeeee sees eee nemen 48 4 0 Power Management sseesseseeseususeuuuuu akan uu RR RR ARRA n uu RR uu kaka u uu nnna 49 4 1 Advanced Configuration and Power Interface ACPI States Supported 50 4 2 Processor Core Power Man
167. rt e Compliant to Direct Media Interface Second Generation DMI2 e Four lanes in each direction Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 26 Order No 328897 010 m Interfaces Processor n tel j 5 GT s point to point DMI interface to PCH is supported Raw bit rate on the data pins of 5 0 GB s resulting in a real bandwidth per pair of 500 MB s given the 8b 10b encoding used to transmit data across this interface Does not account for packet overhead and link maintenance Maximum theoretical bandwidth on interface of 2 GB s in each direction simultaneously for an aggregate of 4 GB s when DMI x4 Shares 100 MHz PCI Express reference clock 64 bit downstream address format but the processor never generates an address above 64 GB Bits 63 36 will always be zeros 64 bit upstream address format but the processor responds to upstream read transactions to addresses above 64 GB addresses where any of Bits 63 36 are nonzero with an Unsupported Request response Upstream write transactions to addresses above 64 GB will be dropped Supports the following traffic types to or from the PCH DMI gt DRAM DMI gt processor core Virtual Legacy Wires VLWs Resetwarn or MSIs only Processor core gt DMI APIC and MSI interrupt messaging support Message Signaled In
168. s CATERR is used for signaling the following types of errors GTL Legacy MCERRs CATERR is asserted for 16 BCLKs Legacy IERRs CATERR remains asserted until warm or cold reset Platform Environment Control Interface A serial I O PECI sideband interface to the processor it is used primarily for thermal power and error management Asynchronous Processor Hot PROCHOT goes active when the processor temperature monitoring sensor s detects that the processor PROCHOT has reached its maximum safe operating temperature This GTL Input indicates that the processor Thermal Control Circuit TCC has Open Drain Output been activated if enabled This signal can also be driven to the processor to activate the TCC Thermal Trip The processor protects itself from catastrophic overheating by use of an internal thermal sensor This sensor is set well above the normal operating temperature to ensure O THERMTRIP that there are no false trips The processor will stop all Asynchronous OD execution when the junction temperature exceeds approximately 130 C This is signaled to the system by the THERMTRIP pin Asynchronous CMOS Power Sequencing Signals Power Sequencing Signals Signal Name Description Direction Buffer Type SM_DRAMPWROK SM_DRAMPWROK Processor Input This signal connects to the PCH DRAMPWROK I Asynchronous CMOS PWRGOOD The processor requires this input signal to be a clean
169. s and the processor temperature has not dropped below the TCC activation point the Critical Temperature Flag in the IA32_THERM_STATUS MSR will be set This flag is an indicator of a catastrophic thermal solution failure and that the processor cannot reduce its temperature Unless immediate action is taken to resolve the failure the processor will probably reach the Thermtrip temperature see Testability Signals on page 91 within a short time To prevent possible permanent silicon damage Intel recommends removing power from the processor within V second of the Critical Temperature Flag being set PROCHOT Signal An external signal PROCHOT processor hot is asserted when the processor core temperature has exceeded its specification If Adaptive Thermal Monitor is enabled it must be enabled for the processor to be operating within specification the TCC will be active when PROCHOT is asserted The processor can be configured to generate an interrupt upon the assertion or de assertion of PROCHOT By default the PROCHOT signal is set to bi directional However it is recommended to configure the signal as an input only When configured as an input or bi directional signal PROCHOT can be used for thermally protecting other platform components should they overheat as well When PROCHOT is driven by an external device e The package will immediately transition to the minimum operation points voltage and frequency supported by the p
170. s two DMA controllers to output two High Definition audio streams on two digital ports simultaneously e Supports only the internal HDMI and DP CODECs Processor Supported Audio Formats over HDMI and DisplayPort Audio Formats HDMI DisplayPort AC 3 Dolby Digital Yes Yes Dolby Digital Plus Yes Yes DTS HD Yes Yes LPCM 192 kHz 24 bit 8 Channel Yes Yes Dolby TrueHD DTS HD Master Audio Yes Yes Lossless Blu Ray Disc Audio Format The processor will continue to support Silent stream Silent stream is an integrated audio feature that enables short audio streams such as system events to be heard over the HDMI and DisplayPort monitors The processor supports silent streams over the HDMI and DisplayPort interfaces at 44 1 kHz 48 kHz 88 2 kHz 96 kHz 176 4 kHz and 192 kHz sampling rates Multiple Display Configurations The following multiple display configuration modes are supported with appropriate driver software e Single Display is a mode with one display port activated to display the output to one display device e Intel Display Clone is a mode with up to three display ports activated to drive the display content of same color depth setting but potentially different refresh rate and resolution settings to all the active display devices connected e Extended Desktop is a mode with up to three display ports activated to drive the content with potentially different color depth refresh rate
171. ses the parameters provided by the SF unit in the object specific rasterization algorithms The WIZ unit rasterizes objects into the corresponding set of pixels The Windower is also capable of performing dithering whereby the illusion of a higher resolution when using low bpp channels in color buffers is possible Color dithering diffuses the sharp color bands seen on smooth shaded objects Video Engine The Video Engine handles the non 3D media video applications It includes support for VLD and MPEG2 decode in hardware 2D Engine The 2D Engine contains BLT Block Level Transfer functionality and an extensive set of 2D instructions To take advantage of the 3D during engine s functionality some BLT functions make use of the 3D renderer Processor Graphics VGA Registers The 2D registers consists of original VGA registers and others to support graphics modes that have color depths resolutions and hardware acceleration features that go beyond the original VGA standard Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 30 Order No 328897 010 m Interfaces Processor n tel j 2 5 2 Note 2 6 Logical 128 Bit Fixed BLT and 256 Fill Engine This BLT engine accelerates the GUI of Microsoft Windows operating systems The 128 bit BLT engine provides hardware acceleration of block transfers o
172. sor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family Datasheet Volume 1 of 2 68 March 2015 Order No 328897 010 Thermal Management Processor 5 1 2 Figure 16 Table 23 Power W TcasE MAX c 80 71 40 82 72 06 84 72 72 Processor PCG 2013C Thermal Profile Thermal Test Vehicle Thermal Profile for Processor PCG 2013C 75 1 N e T un Tease 0 41 Power 44 7 g o ul un un o TTV Case Temperature C un T 30 T 40 TTV Power W 70 See the following table for discrete points that constitute the thermal profile Thermal Test Vehicle Thermal Profile for Processor PCG 2013C Power W Tcase_max C Power W Tcase_max C Y 0 41 Power 44 7 18 52 08 0 44 7 20 52 90 2 45 52 22 53 72 4 46 34 24 54 54 6 47 16 26 55 36 8 47 98 28 56 18 10 48 80 30 57 00 12 49 62 32 57 82 14 50 44 34 58 64 16 51 26 36 59 46 continued continued Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron March 2015 Order No 328897 010 Processor Family Datasheet Volume 1 of 2 69 n tel Processor Thermal Management
173. specification This is significant when each channel is populated with more ranks Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron March 2015 Processor Family Datasheet Volume 1 of 2 Order No 328897 010 61 m e n tel Processor Power Management Selection of power modes should be according to power performance or thermal trade offs of a given system e When trying to achieve maximum performance and power or thermal consideration is not an issue use no power down e Ina system which tries to minimize power consumption try using the deepest power down mode possible PPD DLL off with a low idle timer value e In high performance systems with dense packaging that is tricky thermal design the power down mode should be considered in order to reduce the heating and avoid DDR throttling caused by the heating The default value that BIOS configures in PM PDWN config O0 0 0 MCHBAR is 6080h that is PPD DLL off mode with idle timer of 80h or 128 DCLKs This is a balanced setting with deep power down mode and moderate idle timer value The idle timer expiration count defines the number of DCKLs that a rank is idle that causes entry to the selected power mode As this timer is set to a shorter time the IMC will have more opportunities to put DDR in power down There is no BIOS hook to set this register Customers choosing to change the value of
174. ssor Family Datasheet Volume 1 of 2 93 En n tel Processor Electrical Specifications 7 0 Electrical Specifications This chapter provides the processor electrical specifications including integrated voltage regulator VR Vcc Voltage Identification VID reserved and unused signals signal groups Test Access Points TAP and DC specifications 7 1 Integrated Voltage Regulator A new feature to the processor is the integration of platform voltage regulators into the processor Due to this integration the processor has one main voltage rail Vcc and a voltage rail for the memory interface Vppo compared to six voltage rails on previous processors The Vcc voltage rail will supply the integrated voltage regulators which in turn will regulate to the appropriate voltages for the cores cache system agent and graphics This integration allows the processor to better control on die voltages to optimize between performance and power savings The processor Vcc rail will remain a VID based voltage with a loadline similar to the core voltage rail also called Vcc in previous processors 7 2 Power and Ground Lands The processor has VCC VDDQ and VSS ground lands for on chip power distribution All power lands must be connected to their respective processor power planes all VSS lands must be connected to the system ground plane Use of multiple power and ground planes is recommended to reduce I R drop The VCC lands must be suppl
175. t Clock This signal provides the clock input for the TCK processor Test Bus also known as the Test Access I Port This signal must be driven low or allowed to float GTL during power on Reset Test Data In This signal transfers serial test data into I TDI the processor This signal provides the serial input needed for JTAG specification support GTL Test Data Out This signal transfers serial test data out o TDO of the processor This signal provides the serial output o Drai needed for JTAG specification support pen Sram Test Mode Select This is a JTAG specification I TMS supported signal used by debug tools GTL Test Reset This signal resets the Test Access Port I TRST TAP logic This signal must be driven low during power GTL on Reset Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron March 2015 Order No 328897 010 Processor Family Datasheet Volume 1 of 2 91 intel 6 9 Table 40 6 10 Table 41 Processor Signal Description Error and Thermal Protection Signals Error and Thermal Protection Signals Signal Name Description Direction Buffer Type Catastrophic Error This signal indicates that the system has experienced a catastrophic error and cannot continue to operate The processor will set this for non recoverable O CATERR machine check errors or other unrecoverable internal error
176. tain Power_Limit_2 for up to approximately 1 5 the Turbo Time Parameter See the appropriate processor Thermal Mechanical Design Guidelines for more information see Related Documents section If the power value and or Turbo Time Parameter is Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 84 Order No 328897 010 m e Thermal Management Processor n tel changed during runtime it may take a period of time possibly up to approximately 3 to 5 times the Turbo Time Parameter depending on the magnitude of the change and other factors for the algorithm to settle at the new control limits Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family March 2015 Datasheet Volume 1 of 2 Order No 328897 010 85 Processor Signal Description 6 0 Signal Description This chapter describes the processor signals The signals are arranged in functional groups according to the associated interface or category The following notations are used to describe the signal type Notation Signal Type I Input pin O Output pin I O Bi directional Input Output pin The signal description also includes the type of buffer used for the particular signal see the following table Table 30 Signal Descr
177. temperatures within its operating limits Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components within the system Maintaining the proper thermal environment is key to reliable long term system operation A complete solution includes both component and system level thermal management features Component level thermal solutions can include active or passive heatsinks attached to the processor integrated heat spreader IHS To allow the optimal operation and long term reliability of Intel processor based systems the processor must remain within the minimum and maximum case temperature Tcase specifications as defined by the applicable thermal profile Thermal solutions not designed to provide this level of thermal capability may affect the long term reliability of the processor and system The processors implement a methodology for managing processor temperatures that is intended to support acoustic noise reduction through fan speed control and to assure processor reliability Selection of the appropriate fan speed is based on the relative temperature data reported by the processor s Digital Temperature Sensor DTS The DTS can be read using the Platform Environment Control Interface PECI as described in Processor Temperature on page 78 Alternatively when PECI is monitored by the PCH the processor temperature can be read from the PCH using the SMBus
178. tems with PCI Express Graphics PEG Package C7 state is the deepest C state supported on integrated graphics systems or switchable graphics systems during integrated graphics mode However in most configurations package C6 will be more energy efficient than package C7 state As a result package C7 state residency is expected to be very low or zero in most scenarios where the display is enabled Logic internal to the processor will determine whether package C6 or package C7 state is the most efficient There is no need to make changes in BIOS or system software to prioritize package C6 state over package C7 state Package C States and Display Resolutions The integrated graphics engine has the frame buffer located in system memory When the display is updated the graphics engine fetches display data from system memory Different screen resolutions and refresh rates have different memory latency requirements These requirements may limit the deepest Package C state the processor can enter Other elements that may affect the deepest Package C state available are the following e Display is on or off e Single or multiple displays e Native or non native resolution e Panel Self Refresh PSR technology Display resolution is not the only factor influencing the deepest Package C state the processor can get into Device latencies interrupt response latencies and core C states are among other factors that influence the final package C state
179. terrupt MSI and MSI X messages Downstream SMI SCI and SERR error indication Legacy support for ISA regime protocol PHOLD PHOLDA required for parallel port DMA floppy drive and LPC bus masters DC coupling no capacitors between the processor and the PCH Polarity inversion PCH end to end lane reversal across the link Supports Half Swing low power low voltage DMI Error Flow DMI can only generate SERR in response to errors never SCI SMI MSI PCI INT or GPE Any DMI related SERR activity is associated with Device 0 DMI Link Down The DMI link going down is a fatal unrecoverable error If the DMI data link goes to data link down after the link was up then the DMI link hangs the system by not allowing the link to retrain to prevent data corruption This link behavior is controlled by the PCH Downstream transactions that had been successfully transmitted across the link prior to the link going down may be processed as normal No completions from downstream non posted transactions are returned upstream over the DMI link after a link down event Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron March 2015 Order No 328897 010 Processor Family Datasheet Volume 1 of 2 27 intel 2 4 2 5 Processor Interfaces Processor Graphics The processor graphics contains a generation 7 5 graphics core architecture This enables su
180. th Generation Intel Core i3 4370 i5 i3 4360T i3 4160 i3 4160T processors Added Desktop Intel Pentium G3460 G3450T G3250 G3250T processor Added PCG 2014 Updated Table 21 Desktop Processor Thermal Specifications Updaed Table 26 Digital Thermal Sensor DTS 1 1 Thermal Solution Performance Above TconTROL Updated Table 27 Thermal Margin Slope Updated Table 28 Boundary Conditions Performance Tagets and Tcase Specifications Updaed Table 48 Processor Core Active and Idle Mode DC Voltage and Current Specifications June 2014 July 2014 009 Added Figure 27 2014 Processor Package Land Pin Side Components July 2014 010 Added Desktop 4th Generation Intel Core i3 4370T i3 4170 i3 4170T processors Added Desktop Intel Pentium G3470 G3460T G3260 G3260T processor March 2015 Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 Order No 328897 010 9 m n tel Processor Introduction Note Introduction The Desktop 4th Generation Intel Core processor family Desktop Intel Pentium processor family and Desktop Intel Celeron processor family are 64 bit multi core processors built on 22 nanometer process technology The processors are designed for a two chip platform consisting of a processor and Platform Con
181. the loadline Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 94 Order No 328897 010 Electrical Specifications Processor Table 46 Voltage Regulator VR 12 5 Voltage Identification B B 5 8 5 8 5 B Hex Vee BIB B B B B B B Hex Vec I I I I I t t tt t t Lel t t t t te est se 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 o o o lo lo Jo o J ooh 0 0000 0 o l o lololo l21h 0 8200 0 o o o lo lolo l 01h 0 5000 0l 0 l o loo l ol 22h 0 8300 0 o o o lo lo l o 02h 0 5100 0 0o l o loo l 41 23h 0 8400 0 o o o lo lo l l 03h 0 5200 0l 0 l lolo lo ol 24h 0 8500 0 o o o lo l Jo o J 04h 0 5300 0 0 1 0 0 1 0 1 25h 0 8600 0 o o o lo l Jo l o5h 0 5400 0 0 1 0 0 1 1 0 26h 0 8700 0 o o o lo l J o 06h 0 5500 0 0 1 0 0 1 1 1 27h 0 8800 0 o o o lo l l l ozh 0 5600 0l 0 l lo l lo lo ol 28h 0 8900 0 o o o l lo Jo o J 08h 0 5700 0l 0o l o l lolo l l2oh 0 9000 0 o o o l lo Jo l 09h 0 5800 0 l0 l o l lo l ol 2Ah 0 9100 0 o o o l lo J o 0Ah 0 5900 0 o l o l lo l l 2Bh 0 9200 0 o o o l lo J J OBh 0 6
182. this register can do it by changing it in the BIOS For experiments this register can be modified in real time if BIOS does not lock the IMC registers 4 3 2 1 Initialization Role of CKE During power up CKE is the only input to the SDRAM that has its level recognized other than the DDR3 DDR3L reset pin once power is applied It must be driven LOW by the DDR controller to make sure the SDRAM components float DQ and DQS during power up CKE signals remain LOW while any reset is active until the BIOS writes to a configuration register Using this method CKE is ensured to remain inactive for much longer than the specified 200 micro seconds after power and clocks to SDRAM devices are stable 4 3 2 2 Conditional Self Refresh During SO idle state system memory may be conditionally placed into self refresh state when the processor is in package C3 or deeper power state Refer to Intel Rapid Memory Power Management Intel RMPM for more details on conditional self refresh with Intel HD Graphics enabled When entering the S3 Suspend to RAM STR state or SO conditional self refresh the processor core flushes pending cycles and then enters SDRAM ranks that are not used by Intel graphics memory into self refresh The CKE signals remain LOW so the SDRAM devices perform self refresh The target behavior is to enter self refresh for package C3 or deeper power states as long as there are no memory requests to service 4 3 2 3 Dynamic Power D
183. tions Table 19 Coordination of Core Power States at the Package Level Package C State Core 0 Note 1 If enabled the package C state will be C1E if all cores have resolved a core Ci state or higher Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 56 Order No 328897 010 m Power Management Processor n tel Figure 14 Package C State Entry and Exit lt This is the normal operating state for the processor The processor remains in the normal state when at least one of its cores is in the CO or C1 state or when the platform has not granted permission to the processor to go into a low power state Individual cores may be in lower power idle states while the package is in CO state Package CO State Package C1 C1E State No additional power reduction actions are taken in the package C1 state However if the C1E sub state is enabled the processor automatically transitions to the lowest supported core clock frequency followed by a reduction in voltage The package enters the C1 low power state when e At least one core is in the C1 state e The other cores are in a C1 or deeper power state The package enters the C1E state when e All cores have directly requested C1E using MWAIT C1 with a C1E sub state hint e All
184. tium Processor Family and Desktop Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 Order No 328897 010 87 n tel Processor Signal Description Signal Name Description Direction Buffer Type SDRAM Differential Clock Channel B SDRAM Differential SB_CK 3 0 clock signal pair The crossing of the positive edge of SB_CK O and the negative edge of its complement SB_CK are used to DDR3 DDR3L sample the command and control signals on the SDRAM Clock Enable 1 per rank These signals are used to e Initialize the SDRAMs during power up O SB_CKE 3 0 Power down SDRAM ranks DDR3 DDR3L e Place all SDRAM ranks into and out of self refresh during STR Chip Select 1 per rank These signals are used to select O SB_CS 3 0 particular SDRAM components during the active state There is one Chip Select for each SDRAM rank DDR3 DDR3L SB ODT 3 0 On Die Termination Active Termination Control O DDR3 DDR3L 6 2 Memory Reference Compensation Signals Table 33 Memory Reference and Compensation Signals Signal Name Description Direction Buffer Type System Mem Impedance Compensation I SM_RCOMP 2 0 ys ory Impedance Compensatio DDR3 DDR3L Reference Voltage This signal is used as o SM_VREF a reference voltage to the DDR3 DDR3L controller and is DDR3 DDR3L defined as Vppo 2 Memory Channel A B DIMM DQ Voltage Reference O The output pins are connected to th
185. top 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 42 Order No 328897 010 Technologies Processor n tel Note 3 2 e Memory controller and processor graphics comply with the Intel VT d 1 2 Specification e Two Intel VT d DMA remap engines iGFX DMA remap engine Default DMA remap engine covers all devices except iGFX e Support for root entry context entry and default context e 39 bit guest physical address and host physical address widths e Support for 4 KB page sizes e Support for register based fault recording only for single entry only and support for MSI interrupts for faults e Support for both leaf and non leaf caching e Support for boot protection of default page table e Support for non caching of invalid page table entries e Support for hardware based flushing of translated but pending writes and pending reads on IOTLB invalidation e Support for Global Domain specific and Page specific IOTLB invalidation e MSI cycles MemWr to address FEEx xxxxh not translated Translation faults result in cycle forwarding to VBIOS region byte enables masked for writes Returned data may be bogus for internal agents PEG DMI interfaces return unsupported request status e Interrupt remapping is supported e Queued invalidation is supported e Intel VT d translation bypass ad
186. top Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 96 Order No 328897 010 Electrical Specifications Processor B B B B B B B B Hex Vec B B B B B B B B Hex Vec il i Li li li Li J i ili li i li i Jii tjt t t t tjt t tt t ET ttt t 7J 6 5 4 3 2 1 0 7 6 5 4 3 210 1000 0111110 86h 1 8300 1 0 1 0 1 0 l0 0J A8h 2 1700 1010001111 41 87h 1 8400 1 0 1 0 1 0 0 1 A9h 2 1800 1000 1 0100 88h 1 8500 1 0 1 0 1 01 0 AAh 2 1900 1000 1010 1 89h 1 8600 1 0 1 0 1 0 111 ABDh 2 2000 100 0 10 1 0J 8Ah 1 8700 1 0 1 0 1 1i 0 0J ACh 2 2100 1000 1011 8Bh 1 8800 1 0 J1 0 1 i 0 1 ADh 2 2200 1000 110 0 8Ch 1 8900 1 0 1 01 1i l1 0 AEh 2 2300 1010 0 i 10 1 8Dh 1 9000 1 0 10 1 1111 AFh 2 2400 1010011111 0 8Eh 1 9100 1 0 1 1 0 0 0 0J BOh 2 2500 1000 1111 1 8Fh 1 9200 1 0 1 1 0 0 0 1 Bih 2 2600 1001 0l 0100 90h 1 9300 1 0 1 1 0 0 10 B2h 2 2700 1010101010 11 91h 1 9400 1 0 1 1 0 0 11 B3h 2 2800 10101010110 92h 1 9500 1 0 1 1 0 10 0 B4h 2 2900 1010101011 1 93h 1 9600 1 0 11 0 10 1 B5h 2 3000 1 0 j0 1 0 1 0 0 94h 1 9700 1 0 1 1 0 1 1 0 B6h 2 3100 1 0j0 1 0 1 0 1 95h 1 9800 1 0 1 1 0 1 1 1 B7h 2 3200 1 0j0 1 0 1 1 0 96h 1 9900 1 0 11 1 0 10 0
187. troller Hub PCH The processors are designed to be used with the Intel 8 Series chipset See the following figure for an example platform block diagram Throughout this document the Desktop 4th Generation Intel Core processor family Desktop Intel Pentium processor family and Desktop Intel Celeron processor family may be referred to simply as processor Throughout this document the Desktop 4th Generation Intel Core processor family refers to the Desktop 4th Generation Intel Core i7 4790 i7 4790S i7 4790T i7 4790K i7 4785T i7 4771 i7 4770R i7 4770K i7 4770 i7 4770S i7 4770T i7 4765T i5 4690 i5 4690S i5 4690T i5 4690K i5 4670R i5 4670K i5 4670 i5 4670S i5 4670T i5 4670R i5 4590 i5 4590S i5 4590T i5 4570R i5 4570S i5 4570T i5 4570 i5 4460 i5 4460S i5 4460T i5 4440 i5 4440S i5 4430 i5 4430S i3 4370 i3 4370T i3 4360 i3 4360T i3 4350 i3 4350T i3 4340 i3 4330 i3 4330T i3 4170 i3 4170T i3 4150 i3 4160 i3 4160T i3 4150T i3 4130 and i3 4130T processors Throughout this document the Desktop Intel Pentium processor family refers to the Intel Pentium G3470 G3460 G3460T G3450 G3450T G3440 G3440T G3430 G3420 G3420T G3258 G3260 G3260T G3250 G3250T G3240 G3240T G3220 and G3220T processors Throughout this document the Desktop Intel Celeron processor family refers to the Intel Celeron G1850 G1840 G1840T G1830 G1820 and G1820T processors Som
188. uling and Command Overlap enhancements the IMC continuously monitors pending requests to system memory for the best use of bandwidth and reduction of latency If there are multiple requests to the same open page these requests would be launched in a back to back manner to make optimum use of the open memory page This ability to reorder requests on the fly allows the IMC to further reduce latency and increase bandwidth efficiency Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family Datasheet Volume 1 of 2 March 2015 22 Order No 328897 010 m Interfaces Processor n tel j 2 1 3 3 2 2 2 2 1 Table 7 Data Scrambling The system memory controller incorporates a Data Scrambling feature to minimize the impact of excessive di dt on the platform system memory VRs due to successive 1s and Os on the data bus Past experience has demonstrated that traffic on the data bus is not random and can have energy concentrated at specific spectral harmonics creating high di dt which is generally limited by data patterns that excite resonance between the package inductance and on die capacitances As a result the system memory controller uses a data scrambling feature to create pseudo random patterns on the system memory data bus to reduce the impact of any excessive di dt PCI Express Interface This section describes the PCI Express interface cap
189. ure known as I O MWAIT redirection must be enabled in the BIOS The BIOS can write to the C state range field of the PMG_IO_CAPTURE MSR to restrict the range of I O addresses that are trapped and emulate MWAIT like functionality Any P_LVLx reads outside of this range do not cause an I O redirection to MWAIT Cx like request The reads fall through like a normal I O instruction Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron March 2015 Processor Family Datasheet Volume 1 of 2 Order No 328897 010 53 m n tel Processor Power Management Note When P_LVLx I O instructions are used MWAIT sub states cannot be defined The MWAIT sub state is always zero if I O MWAIT redirection is used By default P_LVLx I O redirections enable the MWAIT break on EFLAGS IF feature that triggers a wakeup on an interrupt even if interrupts are masked by EFLAGS IF 4 2 4 Core C State Rules The following are general rules for all core C states unless specified otherwise e A core C state is determined by the lowest numerical thread state such as Thread 0 requests C1E state while Thread 1 requests C3 state resulting in a core C1E state See the G S and C Interface State Combinations table e A core transitions to CO state when An interrupt occurs There is an access to the monitored address if the state was entered using an MWAIT Timed MWAIT
190. ustained storage typically associated with customer shelf 0 Months 6 Months 6 life Notes 1 Refers to a component device that is not assembled in a board or socket that is not to be electrically connected to a voltage reference or I O signals 2 Specified temperatures are based on data collected Exceptions for surface mount reflow are specified in by applicable JEDEC standard Non adherence may affect processor reliability 3 Tagsoiure Storage applies to the unassembled component only and does not apply to the shipping media moisture barrier bags or desiccant 4 Intel branded board products are certified to meet the following temperature and humidity limits that are given as an example only Non Operating Temperature Limit 40 C to 70 C Humidity 50 to 90 non condensing with a maximum wet bulb of 28 C Post board attach storage temperature limits are not specified for non Intel branded boards 5 The JEDEC J JSTD 020 moisture level rating and associated handling practices apply to all moisture sensitive devices removed from the moisture barrier bag 6 Nominal temperature and humidity conditions and durations are given and tested within the constraints imposed by Tsustained storage aNd customer shelf life in applicable Intel box and bags Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family Datasheet Volume 1 of 2 114 March 2015
191. ve table are supported for 4 lanes with link data rate HBR2 The following table shows the DP eDP resolutions supported for 1 2 or 4 lanes depending on link data rate of RBR HBR and HBR2 Table 10 DisplayPort and embedded DisplayPort Resolutions for 1 2 4 Lanes Link Data Rate of RBR HBR and HBR2 Link Data Rate Lane Count 1 2 4 RBR 1064x600 1400x1050 2240x1400 HBR 1280x960 1920x1200 2880x1800 HBR2 1920x1200 2880x1800 3840x2160 Any 3 displays can be supported simultaneously using the following rules e Maximum of 2 HDMIs e Maximum of 2 DVIS e Maximum of 1 HDMI and 1 DVI e Any 3 DisplayPort e One VGA e One eDP High bandwidth Digital Content Protection HDCP HDCP is the technology for protecting high definition content against unauthorized copy or unreceptive between a source computer digital set top boxes and so on and the sink panels monitor and TVs The processor supports HDCP 1 4 for content protection over wired displays HDMI DVI and DisplayPort The HDCP 1 4 keys are integrated into the processor and customers are not required to physically configure or handle the keys Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family Datasheet Volume 1 of 2 36 March 2015 Order No 328897 010 Interfaces Processor n tel 2 7 2 8 2 8 1 Intel Flexible Dis
192. y while meeting specifications for junction temperature clock frequency and input voltages Read all notes associated with each parameter Desktop 4th Generation Intel Core Processor Family Desktop Intel Pentium Processor Family and Desktop Intel Celeron Processor Family March 2015 Datasheet Volume 1 of 2 Order No 328897 010 101 n tel Processor Electrical Specifications e AC tolerances for all DC rails include dynamic load currents at switching frequencies up to 1 MHz 7 8 Voltage and Current Specifications Table 48 Processor Core Active and Idle Mode DC Voltage and Current Specifications Symbol Parameter Min Typ Max Unit Note 2013D 1 75 Operational 2013C 1 75 VID VID Range 1 65 2013B 175 1 86 V 2 2013A 1 75 Idle VID package VID Range 1 5 1 6 1 65 V 2 C6 C7 Loadline 2014 PCG 1 5 slope within 2013D PCG 1 5 the VR R DC LL 2013C PCG 1 5 mQ 3 5 6 8 regulation loop 2013B PCG 1 5 capability 2013A PCG 1 5 Loadline 2014 PCG 2 4 slope in 2013D PCG 2 4 R_AC_LL response to 2013C PCG 2 4 ma dynamic load increase 2013B PCG 2 4 events 2013A PCG 2 4 Loadline 2014 PCG 3 0 slope in 2013D PCG 3 0 RAGU O5 os 2013C PCG 3 0 ma dynamic load release 2013B PCG 3 0 events 2013A PCG 3 0 T OVS Overshoot 500 uS time v_OVS Overshoot 50 mV Vcc Vcc TOB Tolerance 20 PSO PS1 PS2 PS3 mV 3 5 6 7 8
193. ype of CKE power down can be configured through PDWN mode bits 15 12 and the idle timer can be configured through PDWN idle counter bits 11 0 The different power down modes supported are e No power down CKE disable e Active power down APD This mode is entered if there are open pages when de asserting CKE In this mode the open pages are retained Power saving in this mode is the lowest Power consumption of DDR is defined by IDD3P Exiting this mode is defined by tXP small number of cycles For this mode DRAM DLL must be on e PPD DLL off In this mode the data in DLLs on DDR are off Power saving in this mode is the best among all power modes Power consumption is defined by IDD2P1 Exiting this mode is defined by tXP but also tXPDLL 10 20 according to DDR type cycles until first data transfer is allowed For this mode DRAM DLL must be off The CKE is determined per rank whenever it is inactive Each rank has an idle counter The idle counter starts counting as soon as the rank has no accesses and if it expires the rank may enter power down while no new transactions to the rank arrives to queues The idle counter begins counting at the last incoming transaction arrival It is important to understand that since the power down decision is per rank the IMC can find many opportunities to power down ranks even while running memory intensive applications the savings are significant may be few Watts according to the DDR

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